[PATCH 19/20] s390: Rename insn format VRR_0VVU to VRI_0VVU

[Jens Remus]

This aligns the VRI-l instruction format name according to
specification. [1]  Commit a98a6fa2d8ef ("s390: Add arch15
instructions") erroneously added it as VRR instruction format.

[1]: IBM z/Architecture Principles of Operation, SA22-7832-14, IBM z17,
     https://www.ibm.com/docs/en/module_1678991624569/pdf/SA22-7832-14.pdf

opcodes/
	* s390-opc.c (INSTR_VRR_0VVU, MASK_VRR_0VVU): Rename to
	INSTR_VRI_0VVU and MASK_VRI_0VVU.
	* s390-opc.txt (vtz): Use renamed insn format VRI_0VVU.

Signed-off-by: Jens Remus <jremus@linux.ibm.com>
---
 opcodes/s390-opc.c   | 4 ++--
 opcodes/s390-opc.txt | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
index 40eccc41b8ba..25eff6c8ef45 100644
--- a/opcodes/s390-opc.c
+++ b/opcodes/s390-opc.c
@@ -476,6 +476,7 @@ unused_s390_operands_static_asserts (void)
 #define INSTR_S_00         4, { 0,0,0,0,0,0 }                    /* e.g. hsch  */
 #define INSTR_S_RD         4, { D_20,B_16,0,0,0,0 }              /* e.g. stck  */
 #define INSTR_VRV_VVXRDU   6, { V_8,D_20,VX_12,B_16,U4_32,0 }    /* e.g. vgef  */
+#define INSTR_VRI_0VVU     6, { V_12,V_16,U16_20,0,0,0 }         /* e.g. vtz   */
 #define INSTR_VRI_V0U      6, { V_8,U16_16,0,0,0,0 }             /* e.g. vgbm  */
 #define INSTR_VRI_V        6, { V_8,0,0,0,0,0 }                  /* e.g. vzero */
 #define INSTR_VRI_V0UUU    6, { V_8,U8_16,U8_24,U4_32,0,0 }      /* e.g. vgm   */
@@ -534,7 +535,6 @@ unused_s390_operands_static_asserts (void)
 #define INSTR_VRR_VV0U0U   6, { V_8,V_12,U4_32,U4_24,0,0 }       /* e.g. vistr */
 #define INSTR_VRR_0V       6, { V_12,0,0,0,0,0 }                 /* e.g. vtp   */
 #define INSTR_VRR_0V0U     6, { V_12,U16_20,0,0,0,0 }            /* e.g. vtp   */
-#define INSTR_VRR_0VVU     6, { V_12,V_16,U16_20,0,0,0 }         /* e.g. vtz   */
 #define INSTR_VRR_0VV0U    6, { V_12,V_16,U4_24,0,0,0 }          /* e.g. vcp   */
 #define INSTR_VRR_RV0U     6, { R_8,V_12,U4_24,0,0,0 }           /* e.g. vcvb  */
 #define INSTR_VRR_RV0UU    6, { R_8,V_12,U4_24,U4_28,0,0 }       /* e.g. vcvb  */
@@ -711,6 +711,7 @@ unused_s390_operands_static_asserts (void)
 #define MASK_S_00         { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 }
 #define MASK_S_RD         { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_VRV_VVXRDU   { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+#define MASK_VRI_0VVU     { 0xff, 0xf0, 0x00, 0x00, 0x00, 0xff }
 #define MASK_VRI_V0U      { 0xff, 0x0f, 0x00, 0x00, 0xf0, 0xff }
 #define MASK_VRI_V        { 0xff, 0x0f, 0xff, 0xff, 0xf0, 0xff }
 #define MASK_VRI_V0UUU    { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff }
@@ -769,7 +770,6 @@ unused_s390_operands_static_asserts (void)
 #define MASK_VRR_VV0U0U   { 0xff, 0x00, 0xff, 0x0f, 0x00, 0xff }
 #define MASK_VRR_0V       { 0xff, 0xf0, 0xff, 0xff, 0xf0, 0xff }
 #define MASK_VRR_0V0U     { 0xff, 0xf0, 0xf0, 0x00, 0x00, 0xff }
-#define MASK_VRR_0VVU     { 0xff, 0xf0, 0x00, 0x00, 0x00, 0xff }
 #define MASK_VRR_0VV0U    { 0xff, 0xf0, 0x0f, 0x0f, 0xf0, 0xff }
 #define MASK_VRR_RV0U     { 0xff, 0x00, 0xff, 0x0f, 0xf0, 0xff }
 #define MASK_VRR_RV0UU    { 0xff, 0x00, 0xff, 0x00, 0xf0, 0xff }
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index 5dc2765642fa..d95caa8bb791 100644
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -2205,7 +2205,7 @@ e6000000004e vcvbq VRR_VV0U2 "vector convert to binary 128 bit" arch15 zarch
 e6000000004a vcvdq VRI_VV0UU "vector convert to decimal 128 bit" arch15 zarch
 
 e6000000005f vtp VRR_0V0U "vector test decimal" arch15 zarch optparm
-e6000000007f vtz VRR_0VVU "vector test zoned" arch15 zarch
+e6000000007f vtz VRI_0VVU "vector test zoned" arch15 zarch
 
 # Concurrent-Functions Facility
 
-- 
2.53.0