[PATCH 04/20] s390: clcl operands R1 and R2 must be register pairs

[Jens Remus]

clcl R1,R2 operands R1 and R2 each designate an even-odd pair of
general registers and must designate an even-numbered register;
otherwise, a specification exception is recognized. [1, 2]

[1]: IBM ESA/390 Principles of Operation, SA22-7201-07, z900,
     https://publibfp.dhe.ibm.com/epubs/pdf/dz9ar007.pdf

[2]: IBM z/Architecture Principles of Operation, SA22-7832-14, IBM z17,
     https://www.ibm.com/docs/en/module_1678991624569/pdf/SA22-7832-14.pdf

opcodes/
	* s390-opc.c (INSTR_RR_RERE, MASK_RR_RERE): New RR_RERE
	instruction format.
	* s390-opc.txt (clcl): Use RR_RERE instruction format.

gas/testsuite/
	* gas/s390/esa-g5.d (clcl): Operands R1 and R2 must designate an
	even-odd register pair.
	* gas/s390/esa-g5.s (clcl): Likewise.

Signed-off-by: Jens Remus <jremus@linux.ibm.com>
---
 gas/testsuite/gas/s390/esa-g5.d | 2 +-
 gas/testsuite/gas/s390/esa-g5.s | 2 +-
 opcodes/s390-opc.c              | 2 ++
 opcodes/s390-opc.txt            | 2 +-
 4 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/gas/testsuite/gas/s390/esa-g5.d b/gas/testsuite/gas/s390/esa-g5.d
index 7265da65180e..f386fad8b1d8 100644
--- a/gas/testsuite/gas/s390/esa-g5.d
+++ b/gas/testsuite/gas/s390/esa-g5.d
@@ -120,7 +120,7 @@ Disassembly of section .text:
 .*:	b2 41 00 68 [	 ]*cksm	%r6,%r8
 .*:	55 65 af ff [	 ]*cl	%r6,4095\(%r5,%r10\)
 .*:	d5 ff 5f ff af ff [	 ]*clc	4095\(256,%r5\),4095\(%r10\)
-.*:	0f 69 [	 ]*clcl	%r6,%r9
+.*:	0f 68 [	 ]*clcl	%r6,%r8
 .*:	a9 69 5f ff [	 ]*clcle	%r6,%r9,4095\(%r5\)
 .*:	95 ff 5f ff [	 ]*cli	4095\(%r5\),255
 .*:	bd 6a 5f ff [	 ]*clm	%r6,10,4095\(%r5\)
diff --git a/gas/testsuite/gas/s390/esa-g5.s b/gas/testsuite/gas/s390/esa-g5.s
index 5adb458ca27f..1334e48877a9 100644
--- a/gas/testsuite/gas/s390/esa-g5.s
+++ b/gas/testsuite/gas/s390/esa-g5.s
@@ -114,7 +114,7 @@ foo:
 	cksm	%r6,%r8
 	cl	%r6,4095(%r5,%r10)
 	clc	4095(256,%r5),4095(%r10)
-	clcl	%r6,%r9
+	clcl	%r6,%r8
 	clcle	%r6,%r9,4095(%r5)
 	cli	4095(%r5),255
 	clm	%r6,10,4095(%r5)
diff --git a/opcodes/s390-opc.c b/opcodes/s390-opc.c
index 2cb36aacddb5..e4f8fee9e3e6 100644
--- a/opcodes/s390-opc.c
+++ b/opcodes/s390-opc.c
@@ -404,6 +404,7 @@ unused_s390_operands_static_asserts (void)
 #define INSTR_RR_R0        2, { R_8, 0,0,0,0,0 }                 /* e.g. spm   */
 #define INSTR_RR_RR        2, { R_8,R_12,0,0,0,0 }               /* e.g. lr    */
 #define INSTR_RR_RER       2, { RE_8,R_12,0,0,0,0 }              /* e.g. dr    */
+#define INSTR_RR_RERE      2, { RE_8,RE_12,0,0,0,0 }             /* e.g. clcl  */
 #define INSTR_RR_U0        2, { U8_8, 0,0,0,0,0 }                /* e.g. svc   */
 #define INSTR_RR_UR        2, { U4_8,R_12,0,0,0,0 }              /* e.g. bcr   */
 #define INSTR_RRR_F0FF     4, { F_24,F_28,F_16,0,0,0 }           /* e.g. ddtr  */
@@ -638,6 +639,7 @@ unused_s390_operands_static_asserts (void)
 #define MASK_RR_R0        { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RR_RR        { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RR_RER       { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+#define MASK_RR_RERE      { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RR_U0        { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RR_UR        { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
 #define MASK_RRR_F0FF     { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 }
diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
index c936df825e0c..d531e7e57964 100644
--- a/opcodes/s390-opc.txt
+++ b/opcodes/s390-opc.txt
@@ -40,7 +40,7 @@ b21a cfc S_RD "compare and form codeword" g5 esa,zarch
 49 ch RX_RRRD "compare halfword" g5 esa,zarch
 55 cl RX_RRRD "compare logical" g5 esa,zarch
 d5 clc SS_L0RDRD "compare logical" g5 esa,zarch
-0f clcl RR_RR "compare logical long" g5 esa,zarch
+0f clcl RR_RERE "compare logical long" g5 esa,zarch
 95 cli SI_URD "compare logical" g5 esa,zarch
 bd clm RS_RURD "compare logical characters under mask" g5 esa,zarch
 15 clr RR_RR "compare logical" g5 esa,zarch
-- 
2.53.0