[PATCH 3 12/16] MIPS: Add GINV(+VIRT) ASE for MIPSr6/microMIPS6

[Maciej W. Rozycki]

On Thu, 5 Feb 2026, Jovan Dmitrovic via Binutils wrote:

> From: Faraz Shahbazker <fshahbazker@wavecomp.com>

 This is R5 rather than R6 stuff.

 Please update the change accordingly throughout and also add the missing 
commit description; naming the ISA specs used will be good having there 
along with a short summary of the architectural feature.

 Obviously it also means it's not blocked by any of the microMIPSr6 stuff 
and can go in right away as soon as it meets our coding standards.

  Maciej