[PATCH v3 1/2] x86: ACE_V1 support for AMX-shared instructions

[Jiang, Haochen]

> From: Jan Beulich <jbeulich@suse.com>
> Sent: Friday, September 11, 2026 8:43 PM
> 
> On 09.09.2026 15:25, Rohan Shenoy wrote:
> > Enable ACE_V1 architecture, and reuse the pre-existing AMX-shared
> > instructions for tile management, row moves, and row converts under
> > ACE_V1, also allowing TMM register usage.
> >
> > Reference: AI Compute Extensions (ACE) Specification, v1.16.2
> > https://x86ecosystem.org/wp-
> content/uploads/2026/06/ACE_v1_Specification_public.pdf
> >
> > Co-authored-by: Ganesh Gopalasubramanian
> <Ganesh.Gopalasubramanian@amd.com>
> > Co-authored-by: Umesh Kalvakuntla <Umesh.Kalvakuntla@amd.com>
> > ---
> >  gas/config/tc-i386.c                         | 12 ++++--
> >  gas/doc/c-i386.texi                          |  3 +-
> >  gas/testsuite/gas/i386/x86-64-ace_v1-intel.d | 44
> +++++++++++++++++++
> >  gas/testsuite/gas/i386/x86-64-ace_v1.d       | 44 +++++++++++++++++++
> >  gas/testsuite/gas/i386/x86-64-ace_v1.s       | 44 +++++++++++++++++++
> >  gas/testsuite/gas/i386/x86-64.exp            |  2 +
> >  opcodes/i386-dis-evex-prefix.h               | 20 ++++-----
> >  opcodes/i386-dis.c                           | 13 +++++-
> 
> As you're only enabling existing insns, there shouldn't be any disassembler
> changes here. These also aren't covered by the description. Please split
> out and properly describe.

Agreed. Please at least mention that in log.

> 
> > --- /dev/null
> > +++ b/gas/testsuite/gas/i386/x86-64-ace_v1-intel.d
> > @@ -0,0 +1,44 @@
> > +#as: -march=generic64+ace_v1
> > +#as:
> > +#objdump: -dw -Mintel
> > +#name: 64-bit ACE v1 insns (Intel disassembly)
> 
> I don't think an Intel syntax disassembly test is needed here. All you're
> after is correct behavior of the assembler. (Unless of course in the 2nd
> patch you add to this. But then the Intel syntax disassembly case would
> still more logically be introduced there.)

Exactly, we are only sharing insns here. More appropriate test just needs
to focus on that.

> 
> > --- a/opcodes/i386-gen.c
> > +++ b/opcodes/i386-gen.c
> > @@ -269,6 +269,8 @@ static const dependency isa_dependencies[] =
> >      "RTM|HLE" },
> >    { "TSXLDTRK",
> >      "RTM" },
> > +  { "ACE_V1",
> > +    "AVX10_V2_AUX|AVX10_1_AUX|64" },
> 
> Related to the comments on changes to tc-i386.c: I think we want to have
> an internal TILE feature, which then both AMX_TILE and ACE_V1 depend on.
> That'll be what LDTILECFG, STTILECFG, TILERELEASE, and TILEZERO would be
> switched to, without any need to introduce secondary, almost identical
> templates.

This might lead to issue that when we are disabling both AMX-TILE and ACEV1,
those ISAs will not be disabled.

Thx,
Haochen