[PATCH] RISC-V: Add Sspmp extension support
Jiawei
jiawei@iscas.ac.cn
Fri Sep 11 07:51:36 GMT 2026
This patch adds minimal support for the Sspmp, Sspmpen and Smpmpdeleg
extensions[1], and their CSRs.
[1] https://docs.riscv.org/reference/isa/extensions/sspmp/_attachments/riscv-spmp.pdf
bfd/ChangeLog:
* elfxx-riscv.c (riscv_implicit_subsets): Add smpmpdeleg, sspmp and
sspmpen extensions.
(riscv_supported_std_s_ext): Ditto.
gas/ChangeLog:
* NEWS: Add RISC-V Sspmp, Sspmpen and Smpmpdeleg extensions.
* config/tc-riscv.c (enum riscv_csr_class): Add CSR_CLASS_SMPMPDELEG,
CSR_CLASS_SSPMPEN and CSR_CLASS_SSPMPEN_32.
(riscv_csr_address): Add Smpmpdeleg, Sspmpen and Sspmpenh cases.
* testsuite/gas/riscv/csr-version-1p10.d: Add new CSR testcases.
* testsuite/gas/riscv/csr-version-1p10.l: Ditto.
* testsuite/gas/riscv/csr-version-1p11.d: Ditto.
* testsuite/gas/riscv/csr-version-1p11.l: Ditto.
* testsuite/gas/riscv/csr-version-1p12.d: Ditto.
* testsuite/gas/riscv/csr-version-1p12.l: Ditto.
* testsuite/gas/riscv/csr-version-1p13.d: Ditto.
* testsuite/gas/riscv/csr-version-1p13.l: Ditto.
* testsuite/gas/riscv/csr.s: Add mpmpdeleg, spmpen and spmpenh CSRs.
* testsuite/gas/riscv/march-help.l: Ditto.
* testsuite/gas/riscv/spmpen-rv32.d: New test.
* testsuite/gas/riscv/spmpen-rv32.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (CSR_SPMPEN, CSR_SPMPENH, CSR_MPMPDELEG): New.
(DECLARE_CSR): Add spmpen, spmpenh and mpmpdeleg CSRs.
---
bfd/elfxx-riscv.c | 6 ++++++
gas/NEWS | 2 ++
gas/config/tc-riscv.c | 10 ++++++++++
gas/testsuite/gas/riscv/csr-version-1p10.d | 6 ++++++
gas/testsuite/gas/riscv/csr-version-1p10.l | 16 ++++++++++++++++
gas/testsuite/gas/riscv/csr-version-1p11.d | 6 ++++++
gas/testsuite/gas/riscv/csr-version-1p11.l | 16 ++++++++++++++++
gas/testsuite/gas/riscv/csr-version-1p12.d | 6 ++++++
gas/testsuite/gas/riscv/csr-version-1p12.l | 16 ++++++++++++++++
gas/testsuite/gas/riscv/csr-version-1p13.d | 6 ++++++
gas/testsuite/gas/riscv/csr-version-1p13.l | 16 ++++++++++++++++
gas/testsuite/gas/riscv/csr.s | 7 +++++++
gas/testsuite/gas/riscv/march-help.l | 3 +++
gas/testsuite/gas/riscv/spmpen-rv32.d | 11 +++++++++++
gas/testsuite/gas/riscv/spmpen-rv32.s | 2 ++
include/opcode/riscv-opc.h | 10 ++++++++++
16 files changed, 139 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/spmpen-rv32.d
create mode 100644 gas/testsuite/gas/riscv/spmpen-rv32.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 72ce77e4fbb..c93a2492146 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1340,6 +1340,7 @@ static const struct riscv_implicit_subset riscv_implicit_subsets[] =
{"smaia", "+ssaia", check_implicit_always},
{"smcdeleg", "+ssccfg", check_implicit_always},
+ {"smpmpdeleg", "+smcsrind,+sspmp", check_implicit_always},
{"smcsrind", "+sscsrind", check_implicit_always},
{"smcntrpmf", "+zicsr", check_implicit_always},
{"smctr", "+zicsr", check_implicit_always},
@@ -1352,6 +1353,8 @@ static const struct riscv_implicit_subset riscv_implicit_subsets[] =
{"ssaia", "+zicsr", check_implicit_always},
{"ssccfg", "+sscsrind", check_implicit_always},
+ {"sspmpen", "+sspmp", check_implicit_always},
+ {"sspmp", "+sscsrind", check_implicit_always},
{"sscsrind", "+zicsr", check_implicit_always},
{"sscofpmf", "+zicsr", check_implicit_always},
{"sscounterenw", "+zicsr", check_implicit_always},
@@ -1613,6 +1616,7 @@ static const struct riscv_supported_ext riscv_supported_std_s_ext[] =
{"smcntrpmf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"smctr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"smepmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"smpmpdeleg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"smpmpmt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"smrnmi", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"smstateen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -1644,6 +1648,8 @@ static const struct riscv_supported_ext riscv_supported_std_s_ext[] =
{"smnpm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"smmpm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"sspm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"sspmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"sspmpen", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"supm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{NULL, 0, 0, 0, 0}
};
diff --git a/gas/NEWS b/gas/NEWS
index 8b07d86daa3..bbe09b62401 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -5,6 +5,8 @@
* The avr target supports .gnu_attribute 4 (Tag_GNU_AVR_VTABLE_AS).
For details, see https://sourceware.org/PR34305
+* Add support for the RISC-V Sspmp, Sspmpen, Smpmpdeleg extensions.
+
Changes in 2.47:
* New command line option --reloc-section-sym=[all|internal|none]
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 3abbadc59c1..e49780e8bdf 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -83,6 +83,7 @@ enum riscv_csr_class
CSR_CLASS_SMCNTRPMF, /* Smcntrpmf */
CSR_CLASS_SMCNTRPMF_32, /* Smcntrpmf, rv32 only */
CSR_CLASS_SMCTR, /* Smctr */
+ CSR_CLASS_SMPMPDELEG, /* Smpmpdeleg */
CSR_CLASS_SMRNMI, /* Smrnmi */
CSR_CLASS_SMSTATEEN, /* Smstateen only */
CSR_CLASS_SMSTATEEN_32, /* Smstateen RV32 only */
@@ -105,6 +106,8 @@ enum riscv_csr_class
CSR_CLASS_SSTC_32, /* Sstc RV32 only */
CSR_CLASS_SSTC_AND_H_32, /* Sstc RV32 only (with H) */
CSR_CLASS_SSCTR, /* Ssctr */
+ CSR_CLASS_SSPMPEN, /* Sspmpen */
+ CSR_CLASS_SSPMPEN_32, /* Sspmpen, RV32 only */
CSR_CLASS_SSQOSID, /* Ssqosid */
CSR_CLASS_XTHEADVECTOR, /* xtheadvector only */
};
@@ -1124,6 +1127,7 @@ riscv_csr_address (const char *csr_name,
extension = "smstateen";
break;
case CSR_CLASS_SMCTR: extension = "smctr"; break;
+ case CSR_CLASS_SMPMPDELEG: extension = "smpmpdeleg"; break;
case CSR_CLASS_SSAIA:
case CSR_CLASS_SSAIA_AND_H:
case CSR_CLASS_SSAIA_32:
@@ -1173,6 +1177,12 @@ riscv_csr_address (const char *csr_name,
extension = "sstc";
break;
case CSR_CLASS_SSCTR: extension = "ssctr"; break;
+ case CSR_CLASS_SSPMPEN_32:
+ is_rv32_only = true;
+ /* Fall through. */
+ case CSR_CLASS_SSPMPEN:
+ extension = "sspmpen";
+ break;
case CSR_CLASS_DEBUG:
break;
case CSR_CLASS_XTHEADVECTOR:
diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d
index f05b3b55585..b4dd5712018 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p10.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.d
@@ -649,6 +649,8 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+72159073[ ]+csrw[ ]+mcyclecfgh,a1
[ ]+[0-9a-f]+:[ ]+72202573[ ]+csrr[ ]+a0,minstretcfgh
[ ]+[0-9a-f]+:[ ]+72259073[ ]+csrw[ ]+minstretcfgh,a1
+[ ]+[0-9a-f]+:[ ]+31602573[ ]+csrr[ ]+a0,mpmpdeleg
+[ ]+[0-9a-f]+:[ ]+31659073[ ]+csrw[ ]+mpmpdeleg,a1
[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc
[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1
[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause
@@ -849,6 +851,10 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+24e59073[ ]+csrw[ ]+vsctrctl,a1
[ ]+[0-9a-f]+:[ ]+34e02573[ ]+csrr[ ]+a0,mctrctl
[ ]+[0-9a-f]+:[ ]+34e59073[ ]+csrw[ ]+mctrctl,a1
+[ ]+[0-9a-f]+:[ ]+18302573[ ]+csrr[ ]+a0,spmpen
+[ ]+[0-9a-f]+:[ ]+18359073[ ]+csrw[ ]+spmpen,a1
+[ ]+[0-9a-f]+:[ ]+19302573[ ]+csrr[ ]+a0,spmpenh
+[ ]+[0-9a-f]+:[ ]+19359073[ ]+csrw[ ]+spmpenh,a1
[ ]+[0-9a-f]+:[ ]+00002573[ ]+csrr[ ]+a0,ustatus
[ ]+[0-9a-f]+:[ ]+00059073[ ]+csrw[ ]+ustatus,a1
[ ]+[0-9a-f]+:[ ]+00402573[ ]+csrr[ ]+a0,uie
diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.l b/gas/testsuite/gas/riscv/csr-version-1p10.l
index 4b6f57389ee..bf6c194ff60 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p10.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p10.l
@@ -957,6 +957,10 @@
.*Info: macro .*
.*Warning: invalid CSR `minstretcfgh', needs `smcntrpmf' extension
.*Info: macro .*
+.*Warning: invalid CSR `mpmpdeleg', needs `smpmpdeleg' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mpmpdeleg', needs `smpmpdeleg' extension
+.*Info: macro .*
.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
.*Info: macro .*
.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
@@ -1683,6 +1687,18 @@
.*Info: macro .*
.*Warning: invalid CSR `mctrctl', needs `smctr' extension
.*Info: macro .*
+.*Warning: invalid CSR `spmpen', needs `sspmpen' extension
+.*Info: macro .*
+.*Warning: invalid CSR `spmpen', needs `sspmpen' extension
+.*Info: macro .*
+.*Warning: invalid CSR `spmpenh', needs rv32i extension
+.*Info: macro .*
+.*Warning: invalid CSR `spmpenh', needs `sspmpen' extension
+.*Info: macro .*
+.*Warning: invalid CSR `spmpenh', needs rv32i extension
+.*Info: macro .*
+.*Warning: invalid CSR `spmpenh', needs `sspmpen' extension
+.*Info: macro .*
.*Warning: invalid CSR `fflags', needs `f' extension
.*Info: macro .*
.*Warning: invalid CSR `fflags', needs `f' extension
diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d
index f2f8af9046e..9b1050d04ff 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p11.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.d
@@ -649,6 +649,8 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+72159073[ ]+csrw[ ]+mcyclecfgh,a1
[ ]+[0-9a-f]+:[ ]+72202573[ ]+csrr[ ]+a0,minstretcfgh
[ ]+[0-9a-f]+:[ ]+72259073[ ]+csrw[ ]+minstretcfgh,a1
+[ ]+[0-9a-f]+:[ ]+31602573[ ]+csrr[ ]+a0,mpmpdeleg
+[ ]+[0-9a-f]+:[ ]+31659073[ ]+csrw[ ]+mpmpdeleg,a1
[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc
[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1
[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause
@@ -849,6 +851,10 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+24e59073[ ]+csrw[ ]+vsctrctl,a1
[ ]+[0-9a-f]+:[ ]+34e02573[ ]+csrr[ ]+a0,mctrctl
[ ]+[0-9a-f]+:[ ]+34e59073[ ]+csrw[ ]+mctrctl,a1
+[ ]+[0-9a-f]+:[ ]+18302573[ ]+csrr[ ]+a0,spmpen
+[ ]+[0-9a-f]+:[ ]+18359073[ ]+csrw[ ]+spmpen,a1
+[ ]+[0-9a-f]+:[ ]+19302573[ ]+csrr[ ]+a0,spmpenh
+[ ]+[0-9a-f]+:[ ]+19359073[ ]+csrw[ ]+spmpenh,a1
[ ]+[0-9a-f]+:[ ]+00002573[ ]+csrr[ ]+a0,ustatus
[ ]+[0-9a-f]+:[ ]+00059073[ ]+csrw[ ]+ustatus,a1
[ ]+[0-9a-f]+:[ ]+00402573[ ]+csrr[ ]+a0,uie
diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.l b/gas/testsuite/gas/riscv/csr-version-1p11.l
index eb2322b672c..09b03f677b5 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p11.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p11.l
@@ -953,6 +953,10 @@
.*Info: macro .*
.*Warning: invalid CSR `minstretcfgh', needs `smcntrpmf' extension
.*Info: macro .*
+.*Warning: invalid CSR `mpmpdeleg', needs `smpmpdeleg' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mpmpdeleg', needs `smpmpdeleg' extension
+.*Info: macro .*
.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
.*Info: macro .*
.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
@@ -1679,6 +1683,18 @@
.*Info: macro .*
.*Warning: invalid CSR `mctrctl', needs `smctr' extension
.*Info: macro .*
+.*Warning: invalid CSR `spmpen', needs `sspmpen' extension
+.*Info: macro .*
+.*Warning: invalid CSR `spmpen', needs `sspmpen' extension
+.*Info: macro .*
+.*Warning: invalid CSR `spmpenh', needs rv32i extension
+.*Info: macro .*
+.*Warning: invalid CSR `spmpenh', needs `sspmpen' extension
+.*Info: macro .*
+.*Warning: invalid CSR `spmpenh', needs rv32i extension
+.*Info: macro .*
+.*Warning: invalid CSR `spmpenh', needs `sspmpen' extension
+.*Info: macro .*
.*Warning: invalid CSR `fflags', needs `f' extension
.*Info: macro .*
.*Warning: invalid CSR `fflags', needs `f' extension
diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d
index d9d352923bc..ec677c59995 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p12.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.d
@@ -649,6 +649,8 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+72159073[ ]+csrw[ ]+mcyclecfgh,a1
[ ]+[0-9a-f]+:[ ]+72202573[ ]+csrr[ ]+a0,minstretcfgh
[ ]+[0-9a-f]+:[ ]+72259073[ ]+csrw[ ]+minstretcfgh,a1
+[ ]+[0-9a-f]+:[ ]+31602573[ ]+csrr[ ]+a0,mpmpdeleg
+[ ]+[0-9a-f]+:[ ]+31659073[ ]+csrw[ ]+mpmpdeleg,a1
[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc
[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1
[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause
@@ -849,6 +851,10 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+24e59073[ ]+csrw[ ]+vsctrctl,a1
[ ]+[0-9a-f]+:[ ]+34e02573[ ]+csrr[ ]+a0,mctrctl
[ ]+[0-9a-f]+:[ ]+34e59073[ ]+csrw[ ]+mctrctl,a1
+[ ]+[0-9a-f]+:[ ]+18302573[ ]+csrr[ ]+a0,spmpen
+[ ]+[0-9a-f]+:[ ]+18359073[ ]+csrw[ ]+spmpen,a1
+[ ]+[0-9a-f]+:[ ]+19302573[ ]+csrr[ ]+a0,spmpenh
+[ ]+[0-9a-f]+:[ ]+19359073[ ]+csrw[ ]+spmpenh,a1
[ ]+[0-9a-f]+:[ ]+00002573[ ]+csrr[ ]+a0,0x0
[ ]+[0-9a-f]+:[ ]+00059073[ ]+csrw[ ]+0x0,a1
[ ]+[0-9a-f]+:[ ]+00402573[ ]+csrr[ ]+a0,0x4
diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.l b/gas/testsuite/gas/riscv/csr-version-1p12.l
index 13c63e196b5..f61cdcaebbd 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p12.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p12.l
@@ -677,6 +677,10 @@
.*Info: macro .*
.*Warning: invalid CSR `minstretcfgh', needs `smcntrpmf' extension
.*Info: macro .*
+.*Warning: invalid CSR `mpmpdeleg', needs `smpmpdeleg' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mpmpdeleg', needs `smpmpdeleg' extension
+.*Info: macro .*
.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
.*Info: macro .*
.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
@@ -1403,6 +1407,18 @@
.*Info: macro .*
.*Warning: invalid CSR `mctrctl', needs `smctr' extension
.*Info: macro .*
+.*Warning: invalid CSR `spmpen', needs `sspmpen' extension
+.*Info: macro .*
+.*Warning: invalid CSR `spmpen', needs `sspmpen' extension
+.*Info: macro .*
+.*Warning: invalid CSR `spmpenh', needs rv32i extension
+.*Info: macro .*
+.*Warning: invalid CSR `spmpenh', needs `sspmpen' extension
+.*Info: macro .*
+.*Warning: invalid CSR `spmpenh', needs rv32i extension
+.*Info: macro .*
+.*Warning: invalid CSR `spmpenh', needs `sspmpen' extension
+.*Info: macro .*
.*Warning: invalid CSR `ustatus' for the privileged spec `1.12'
.*Info: macro .*
.*Warning: invalid CSR `ustatus' for the privileged spec `1.12'
diff --git a/gas/testsuite/gas/riscv/csr-version-1p13.d b/gas/testsuite/gas/riscv/csr-version-1p13.d
index 5d3cef8c4da..abd736f38d2 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p13.d
+++ b/gas/testsuite/gas/riscv/csr-version-1p13.d
@@ -649,6 +649,8 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+72159073[ ]+csrw[ ]+mcyclecfgh,a1
[ ]+[0-9a-f]+:[ ]+72202573[ ]+csrr[ ]+a0,minstretcfgh
[ ]+[0-9a-f]+:[ ]+72259073[ ]+csrw[ ]+minstretcfgh,a1
+[ ]+[0-9a-f]+:[ ]+31602573[ ]+csrr[ ]+a0,mpmpdeleg
+[ ]+[0-9a-f]+:[ ]+31659073[ ]+csrw[ ]+mpmpdeleg,a1
[ ]+[0-9a-f]+:[ ]+74102573[ ]+csrr[ ]+a0,mnepc
[ ]+[0-9a-f]+:[ ]+74159073[ ]+csrw[ ]+mnepc,a1
[ ]+[0-9a-f]+:[ ]+74202573[ ]+csrr[ ]+a0,mncause
@@ -849,6 +851,10 @@ Disassembly of section .text:
[ ]+[0-9a-f]+:[ ]+24e59073[ ]+csrw[ ]+vsctrctl,a1
[ ]+[0-9a-f]+:[ ]+34e02573[ ]+csrr[ ]+a0,mctrctl
[ ]+[0-9a-f]+:[ ]+34e59073[ ]+csrw[ ]+mctrctl,a1
+[ ]+[0-9a-f]+:[ ]+18302573[ ]+csrr[ ]+a0,spmpen
+[ ]+[0-9a-f]+:[ ]+18359073[ ]+csrw[ ]+spmpen,a1
+[ ]+[0-9a-f]+:[ ]+19302573[ ]+csrr[ ]+a0,spmpenh
+[ ]+[0-9a-f]+:[ ]+19359073[ ]+csrw[ ]+spmpenh,a1
[ ]+[0-9a-f]+:[ ]+00002573[ ]+csrr[ ]+a0,0x0
[ ]+[0-9a-f]+:[ ]+00059073[ ]+csrw[ ]+0x0,a1
[ ]+[0-9a-f]+:[ ]+00402573[ ]+csrr[ ]+a0,0x4
diff --git a/gas/testsuite/gas/riscv/csr-version-1p13.l b/gas/testsuite/gas/riscv/csr-version-1p13.l
index a7055817996..452b40001ec 100644
--- a/gas/testsuite/gas/riscv/csr-version-1p13.l
+++ b/gas/testsuite/gas/riscv/csr-version-1p13.l
@@ -673,6 +673,10 @@
.*Info: macro .*
.*Warning: invalid CSR `minstretcfgh', needs `smcntrpmf' extension
.*Info: macro .*
+.*Warning: invalid CSR `mpmpdeleg', needs `smpmpdeleg' extension
+.*Info: macro .*
+.*Warning: invalid CSR `mpmpdeleg', needs `smpmpdeleg' extension
+.*Info: macro .*
.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
.*Info: macro .*
.*Warning: invalid CSR `mnepc', needs `smrnmi' extension
@@ -1399,6 +1403,18 @@
.*Info: macro .*
.*Warning: invalid CSR `mctrctl', needs `smctr' extension
.*Info: macro .*
+.*Warning: invalid CSR `spmpen', needs `sspmpen' extension
+.*Info: macro .*
+.*Warning: invalid CSR `spmpen', needs `sspmpen' extension
+.*Info: macro .*
+.*Warning: invalid CSR `spmpenh', needs rv32i extension
+.*Info: macro .*
+.*Warning: invalid CSR `spmpenh', needs `sspmpen' extension
+.*Info: macro .*
+.*Warning: invalid CSR `spmpenh', needs rv32i extension
+.*Info: macro .*
+.*Warning: invalid CSR `spmpenh', needs `sspmpen' extension
+.*Info: macro .*
.*Warning: invalid CSR `ustatus' for the privileged spec `1.13'
.*Info: macro .*
.*Warning: invalid CSR `ustatus' for the privileged spec `1.13'
diff --git a/gas/testsuite/gas/riscv/csr.s b/gas/testsuite/gas/riscv/csr.s
index 79206444fa3..c56dfc19ab5 100644
--- a/gas/testsuite/gas/riscv/csr.s
+++ b/gas/testsuite/gas/riscv/csr.s
@@ -367,6 +367,9 @@
csr mcyclecfgh
csr minstretcfgh
+ # Smpmpdeleg extension
+ csr mpmpdeleg
+
# smrnmi
csr mnepc
csr mncause
@@ -485,6 +488,10 @@
csr vsctrctl
csr mctrctl
+ # Sspmpen
+ csr spmpen
+ csr spmpenh
+
# Supported in previous priv spec, but dropped now
csr ustatus # 0x0 in 1.10, dropped in 1.12
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 4ca7038c66c..486d8575f5a 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -135,6 +135,7 @@ All available -march extensions for RISC-V:
smcntrpmf 1.0
smctr 1.0
smepmp 1.0
+ smpmpdeleg 1.0
smpmpmt 1.0
smrnmi 1.0
smstateen 1.0
@@ -166,6 +167,8 @@ All available -march extensions for RISC-V:
smnpm 1.0
smmpm 1.0
sspm 1.0
+ sspmp 1.0
+ sspmpen 1.0
supm 1.0
xandesbfhcvt 5.0
xandesvbfhcvt 5.0
diff --git a/gas/testsuite/gas/riscv/spmpen-rv32.d b/gas/testsuite/gas/riscv/spmpen-rv32.d
new file mode 100644
index 00000000000..fd3380aad11
--- /dev/null
+++ b/gas/testsuite/gas/riscv/spmpen-rv32.d
@@ -0,0 +1,11 @@
+#as: -march=rv32i_zicsr_sspmpen -mpriv-spec=1.13 -mcsr-check --fatal-warnings
+#objdump: -dr -Mpriv-spec=1.13
+#source: spmpen-rv32.s
+.*:[ ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <.text>:
+[ ]+[0-9a-f]+:[ ]+18302573[ ]+csrr[ ]+a0,spmpen
+[ ]+[0-9a-f]+:[ ]+193025f3[ ]+csrr[ ]+a1,spmpenh
diff --git a/gas/testsuite/gas/riscv/spmpen-rv32.s b/gas/testsuite/gas/riscv/spmpen-rv32.s
new file mode 100644
index 00000000000..402de9edb15
--- /dev/null
+++ b/gas/testsuite/gas/riscv/spmpen-rv32.s
@@ -0,0 +1,2 @@
+csrr a0, spmpen
+csrr a1, spmpenh
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index da3f51ac2c1..12deebb5b1d 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -4518,6 +4518,11 @@
#define CSR_SCTRDEPTH 0x15f
#define CSR_VSCTRCTL 0x24e
#define CSR_MCTRCTL 0x34e
+/* Sspmpen extension. */
+#define CSR_SPMPEN 0x183
+#define CSR_SPMPENH 0x193
+/* Smpmpdeleg extension. */
+#define CSR_MPMPDELEG 0x316
/* Zicfissp CSR addresses. */
#define CSR_SSP 0x11
/* Unprivileged Floating-Point CSR addresses. */
@@ -5722,6 +5727,11 @@ DECLARE_CSR(sctrstatus, CSR_SCTRSTATUS, CSR_CLASS_SSCTR, PRIV_SPEC_CLASS_NONE, P
DECLARE_CSR(sctrdepth, CSR_SCTRDEPTH, CSR_CLASS_SSCTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(vsctrctl, CSR_VSCTRCTL, CSR_CLASS_SSCTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
DECLARE_CSR(mctrctl, CSR_MCTRCTL, CSR_CLASS_SMCTR, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+/* Sspmpen extension. */
+DECLARE_CSR(spmpen, CSR_SPMPEN, CSR_CLASS_SSPMPEN, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+DECLARE_CSR(spmpenh, CSR_SPMPENH, CSR_CLASS_SSPMPEN_32, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
+/* Smpmpdeleg extension */
+DECLARE_CSR(mpmpdeleg, CSR_MPMPDELEG, CSR_CLASS_SMPMPDELEG, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
/* Zicfiss CSRs. */
DECLARE_CSR(ssp, CSR_SSP, CSR_CLASS_ZICFISS, PRIV_SPEC_CLASS_NONE, PRIV_SPEC_CLASS_NONE)
/* Dropped CSRs. */
--
2.43.0
More information about the Binutils
mailing list