[PATCH v3 1/2] x86: ACE_V1 support for AMX-shared instructions
Rohan Shenoy
RohanRadhesh.Shenoy@amd.com
Wed Sep 9 13:25:17 GMT 2026
Enable ACE_V1 architecture, and reuse the pre-existing AMX-shared
instructions for tile management, row moves, and row converts under
ACE_V1, also allowing TMM register usage.
Reference: AI Compute Extensions (ACE) Specification, v1.16.2
https://x86ecosystem.org/wp-content/uploads/2026/06/ACE_v1_Specification_public.pdf
Co-authored-by: Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
Co-authored-by: Umesh Kalvakuntla <Umesh.Kalvakuntla@amd.com>
---
gas/config/tc-i386.c | 12 ++++--
gas/doc/c-i386.texi | 3 +-
gas/testsuite/gas/i386/x86-64-ace_v1-intel.d | 44 +++++++++++++++++++
gas/testsuite/gas/i386/x86-64-ace_v1.d | 44 +++++++++++++++++++
gas/testsuite/gas/i386/x86-64-ace_v1.s | 44 +++++++++++++++++++
gas/testsuite/gas/i386/x86-64.exp | 2 +
opcodes/i386-dis-evex-prefix.h | 20 ++++-----
opcodes/i386-dis.c | 13 +++++-
opcodes/i386-gen.c | 3 ++
opcodes/i386-opc.h | 3 ++
opcodes/i386-opc.tbl | 45 +++++++++++---------
opcodes/i386-reg.tbl | 2 +-
12 files changed, 197 insertions(+), 38 deletions(-)
create mode 100644 gas/testsuite/gas/i386/x86-64-ace_v1-intel.d
create mode 100644 gas/testsuite/gas/i386/x86-64-ace_v1.d
create mode 100644 gas/testsuite/gas/i386/x86-64-ace_v1.s
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index ce9cc8236fa..6ad210ba404 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1207,6 +1207,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (pconfig, PCONFIG, PCONFIG, false),
SUBARCH (waitpkg, WAITPKG, WAITPKG, false),
SUBARCH (cldemote, CLDEMOTE, CLDEMOTE, false),
+ SUBARCH (ace_v1, ACE_V1, ACE_V1, false),
SUBARCH (amx_int8, AMX_INT8, ANY_AMX_INT8, false),
SUBARCH (amx_bf16, AMX_BF16, ANY_AMX_BF16, false),
SUBARCH (amx_fp16, AMX_FP16, ANY_AMX_FP16, false),
@@ -1907,6 +1908,7 @@ _is_cpu (const i386_cpu_attr *a, enum i386_cpu cpu)
case CpuAPX_F: return a->bitfield.cpuapx_f;
case CpuAVX10_2: return a->bitfield.cpuavx10_2;
case CpuAMX_TRANSPOSE: return a->bitfield.cpuamx_transpose;
+ case CpuACE_V1: return a->bitfield.cpuace_v1;
case Cpu64: return a->bitfield.cpu64;
case CpuNo64: return a->bitfield.cpuno64;
default:
@@ -12588,7 +12590,10 @@ output_insn (const struct last_insn *last_insn)
unsigned int feature_2_used = 0;
if ((i.xstate & xstate_tmm) == xstate_tmm
- || is_cpu (&i.tm, CpuAMX_TILE))
+ || is_cpu (&i.tm, CpuAMX_TILE)
+ || is_cpu (&i.tm, CpuACE_V1)
+ || maybe_cpu (&i.tm, CpuAMX_TILE)
+ || maybe_cpu (&i.tm, CpuACE_V1))
feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_TMM;
if (is_cpu (&i.tm, Cpu8087)
@@ -17073,8 +17078,9 @@ static bool check_register (const reg_entry *r)
return false;
if (r->reg_type.bitfield.tmmword
- && (!cpu_arch_flags.bitfield.cpuamx_tile
- || flag_code != CODE_64BIT))
+ && ((!cpu_arch_flags.bitfield.cpuamx_tile
+ && !cpu_arch_flags.bitfield.cpuace_v1)
+ || flag_code != CODE_64BIT))
return false;
if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx)
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 3ce70810d4e..f0aec60fda8 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -245,6 +245,7 @@ accept various extension mnemonics. For example,
@code{amx_movrs},
@code{amx_avx512},
@code{amx_tile},
+@code{ace_v1},
@code{vmx},
@code{vmfunc},
@code{smx},
@@ -1737,7 +1738,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.amx_int8} @tab @samp{.amx_bf16} @tab @samp{.amx_fp16}
@item @samp{.amx_complex} @tab @samp{.amx_transpose} @tab @samp{.amx_tf32}
@item @samp{.amx_fp8} @tab @samp{.amx_movrs} @tab @samp{.amx_avx512}
-@item @samp{.amx_tile}
+@item @samp{.amx_tile} @tab @samp{.ace_v1}
@item @samp{.kl} @tab @samp{.widekl} @tab @samp{.uintr} @tab @samp{.hreset}
@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme}
diff --git a/gas/testsuite/gas/i386/x86-64-ace_v1-intel.d b/gas/testsuite/gas/i386/x86-64-ace_v1-intel.d
new file mode 100644
index 00000000000..d5aeddfc1bd
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-ace_v1-intel.d
@@ -0,0 +1,44 @@
+#as: -march=generic64+ace_v1
+#as:
+#objdump: -dw -Mintel
+#name: 64-bit ACE v1 insns (Intel disassembly)
+#source: x86-64-ace_v1.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <start>:
+[ ]*[a-f0-9]+:[ ]*c4 e2 7b 49 c0[ ]+tilezero tmm0
+[ ]*[a-f0-9]+:[ ]*c4 e2 78 49 01[ ]+ldtilecfg \[rcx\]
+[ ]*[a-f0-9]+:[ ]*c4 e2 79 49 01[ ]+sttilecfg \[rcx\]
+[ ]*[a-f0-9]+:[ ]*c4 e2 78 49 c0[ ]+tilerelease
+[ ]*[a-f0-9]+:[ ]*62 f2 65 48 4a ca[ ]+tilemovrow zmm1,tmm2,ebx
+[ ]*[a-f0-9]+:[ ]*62 f3 7d 48 07 ca 08[ ]+tilemovrow zmm1,tmm2,0x8
+[ ]*[a-f0-9]+:[ ]*62 62 6e 48 4a f5[ ]+tcvtrowd2ps zmm30,tmm5,edx
+[ ]*[a-f0-9]+:[ ]*62 63 7e 48 07 f5 08[ ]+tcvtrowd2ps zmm30,tmm5,0x8
+[ ]*[a-f0-9]+:[ ]*62 62 6f 48 6d f5[ ]+tcvtrowps2bf16h zmm30,tmm5,edx
+[ ]*[a-f0-9]+:[ ]*62 63 7f 48 07 f5 08[ ]+tcvtrowps2bf16h zmm30,tmm5,0x8
+[ ]*[a-f0-9]+:[ ]*62 62 6c 48 6d f5[ ]+tcvtrowps2phh zmm30,tmm5,edx
+[ ]*[a-f0-9]+:[ ]*62 63 7c 48 07 f5 08[ ]+tcvtrowps2phh zmm30,tmm5,0x8
+[ ]*[a-f0-9]+:[ ]*62 62 6e 48 6d f5[ ]+tcvtrowps2bf16l zmm30,tmm5,edx
+[ ]*[a-f0-9]+:[ ]*62 63 7e 48 77 f5 08[ ]+tcvtrowps2bf16l zmm30,tmm5,0x8
+[ ]*[a-f0-9]+:[ ]*62 62 6d 48 6d f5[ ]+tcvtrowps2phl zmm30,tmm5,edx
+[ ]*[a-f0-9]+:[ ]*62 63 7f 48 77 f5 08[ ]+tcvtrowps2phl zmm30,tmm5,0x8
+[0-9a-f]+ <_intel>:
+[ ]*[a-f0-9]+:[ ]*c4 e2 7b 49 c0[ ]+tilezero tmm0
+[ ]*[a-f0-9]+:[ ]*c4 e2 78 49 01[ ]+ldtilecfg \[rcx\]
+[ ]*[a-f0-9]+:[ ]*c4 e2 79 49 01[ ]+sttilecfg \[rcx\]
+[ ]*[a-f0-9]+:[ ]*c4 e2 78 49 c0[ ]+tilerelease
+[ ]*[a-f0-9]+:[ ]*62 f2 65 48 4a ca[ ]+tilemovrow zmm1,tmm2,ebx
+[ ]*[a-f0-9]+:[ ]*62 f3 7d 48 07 ca 08[ ]+tilemovrow zmm1,tmm2,0x8
+[ ]*[a-f0-9]+:[ ]*62 62 6e 48 4a f5[ ]+tcvtrowd2ps zmm30,tmm5,edx
+[ ]*[a-f0-9]+:[ ]*62 63 7e 48 07 f5 08[ ]+tcvtrowd2ps zmm30,tmm5,0x8
+[ ]*[a-f0-9]+:[ ]*62 62 6f 48 6d f5[ ]+tcvtrowps2bf16h zmm30,tmm5,edx
+[ ]*[a-f0-9]+:[ ]*62 63 7f 48 07 f5 08[ ]+tcvtrowps2bf16h zmm30,tmm5,0x8
+[ ]*[a-f0-9]+:[ ]*62 62 6c 48 6d f5[ ]+tcvtrowps2phh zmm30,tmm5,edx
+[ ]*[a-f0-9]+:[ ]*62 63 7c 48 07 f5 08[ ]+tcvtrowps2phh zmm30,tmm5,0x8
+[ ]*[a-f0-9]+:[ ]*62 62 6e 48 6d f5[ ]+tcvtrowps2bf16l zmm30,tmm5,edx
+[ ]*[a-f0-9]+:[ ]*62 63 7e 48 77 f5 08[ ]+tcvtrowps2bf16l zmm30,tmm5,0x8
+[ ]*[a-f0-9]+:[ ]*62 62 6d 48 6d f5[ ]+tcvtrowps2phl zmm30,tmm5,edx
+[ ]*[a-f0-9]+:[ ]*62 63 7f 48 77 f5 08[ ]+tcvtrowps2phl zmm30,tmm5,0x8
diff --git a/gas/testsuite/gas/i386/x86-64-ace_v1.d b/gas/testsuite/gas/i386/x86-64-ace_v1.d
new file mode 100644
index 00000000000..58a8ce21b07
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-ace_v1.d
@@ -0,0 +1,44 @@
+#as: -march=generic64+ace_v1
+#as:
+#objdump: -dw
+#name: 64-bit ACE v1 insns
+#source: x86-64-ace_v1.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <start>:
+[ ]*[a-f0-9]+:[ ]*c4 e2 7b 49 c0[ ]+tilezero %tmm0
+[ ]*[a-f0-9]+:[ ]*c4 e2 78 49 01[ ]+ldtilecfg \(%rcx\)
+[ ]*[a-f0-9]+:[ ]*c4 e2 79 49 01[ ]+sttilecfg \(%rcx\)
+[ ]*[a-f0-9]+:[ ]*c4 e2 78 49 c0[ ]+tilerelease
+[ ]*[a-f0-9]+:[ ]*62 f2 65 48 4a ca[ ]+tilemovrow %ebx,%tmm2,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f3 7d 48 07 ca 08[ ]+tilemovrow \$0x8,%tmm2,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 62 6e 48 4a f5[ ]+tcvtrowd2ps %edx,%tmm5,%zmm30
+[ ]*[a-f0-9]+:[ ]*62 63 7e 48 07 f5 08[ ]+tcvtrowd2ps \$0x8,%tmm5,%zmm30
+[ ]*[a-f0-9]+:[ ]*62 62 6f 48 6d f5[ ]+tcvtrowps2bf16h %edx,%tmm5,%zmm30
+[ ]*[a-f0-9]+:[ ]*62 63 7f 48 07 f5 08[ ]+tcvtrowps2bf16h \$0x8,%tmm5,%zmm30
+[ ]*[a-f0-9]+:[ ]*62 62 6c 48 6d f5[ ]+tcvtrowps2phh %edx,%tmm5,%zmm30
+[ ]*[a-f0-9]+:[ ]*62 63 7c 48 07 f5 08[ ]+tcvtrowps2phh \$0x8,%tmm5,%zmm30
+[ ]*[a-f0-9]+:[ ]*62 62 6e 48 6d f5[ ]+tcvtrowps2bf16l %edx,%tmm5,%zmm30
+[ ]*[a-f0-9]+:[ ]*62 63 7e 48 77 f5 08[ ]+tcvtrowps2bf16l \$0x8,%tmm5,%zmm30
+[ ]*[a-f0-9]+:[ ]*62 62 6d 48 6d f5[ ]+tcvtrowps2phl %edx,%tmm5,%zmm30
+[ ]*[a-f0-9]+:[ ]*62 63 7f 48 77 f5 08[ ]+tcvtrowps2phl \$0x8,%tmm5,%zmm30
+[0-9a-f]+ <_intel>:
+[ ]*[a-f0-9]+:[ ]*c4 e2 7b 49 c0[ ]+tilezero %tmm0
+[ ]*[a-f0-9]+:[ ]*c4 e2 78 49 01[ ]+ldtilecfg \(%rcx\)
+[ ]*[a-f0-9]+:[ ]*c4 e2 79 49 01[ ]+sttilecfg \(%rcx\)
+[ ]*[a-f0-9]+:[ ]*c4 e2 78 49 c0[ ]+tilerelease
+[ ]*[a-f0-9]+:[ ]*62 f2 65 48 4a ca[ ]+tilemovrow %ebx,%tmm2,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f3 7d 48 07 ca 08[ ]+tilemovrow \$0x8,%tmm2,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 62 6e 48 4a f5[ ]+tcvtrowd2ps %edx,%tmm5,%zmm30
+[ ]*[a-f0-9]+:[ ]*62 63 7e 48 07 f5 08[ ]+tcvtrowd2ps \$0x8,%tmm5,%zmm30
+[ ]*[a-f0-9]+:[ ]*62 62 6f 48 6d f5[ ]+tcvtrowps2bf16h %edx,%tmm5,%zmm30
+[ ]*[a-f0-9]+:[ ]*62 63 7f 48 07 f5 08[ ]+tcvtrowps2bf16h \$0x8,%tmm5,%zmm30
+[ ]*[a-f0-9]+:[ ]*62 62 6c 48 6d f5[ ]+tcvtrowps2phh %edx,%tmm5,%zmm30
+[ ]*[a-f0-9]+:[ ]*62 63 7c 48 07 f5 08[ ]+tcvtrowps2phh \$0x8,%tmm5,%zmm30
+[ ]*[a-f0-9]+:[ ]*62 62 6e 48 6d f5[ ]+tcvtrowps2bf16l %edx,%tmm5,%zmm30
+[ ]*[a-f0-9]+:[ ]*62 63 7e 48 77 f5 08[ ]+tcvtrowps2bf16l \$0x8,%tmm5,%zmm30
+[ ]*[a-f0-9]+:[ ]*62 62 6d 48 6d f5[ ]+tcvtrowps2phl %edx,%tmm5,%zmm30
+[ ]*[a-f0-9]+:[ ]*62 63 7f 48 77 f5 08[ ]+tcvtrowps2phl \$0x8,%tmm5,%zmm30
diff --git a/gas/testsuite/gas/i386/x86-64-ace_v1.s b/gas/testsuite/gas/i386/x86-64-ace_v1.s
new file mode 100644
index 00000000000..10fbc8d9adf
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-ace_v1.s
@@ -0,0 +1,44 @@
+# Check 64-bit ACE V1 instructions
+
+ .text
+start:
+ tilezero %tmm0
+ ldtilecfg (%rcx)
+ sttilecfg (%rcx)
+ tilerelease
+
+ tilemovrow %ebx, %tmm2, %zmm1
+ tilemovrow $8, %tmm2, %zmm1
+
+ tcvtrowd2ps %edx, %tmm5, %zmm30
+ tcvtrowd2ps $8, %tmm5, %zmm30
+
+ .irp p, h, l
+ tcvtrowps2bf16\p %edx, %tmm5, %zmm30
+ tcvtrowps2bf16\p $8, %tmm5, %zmm30
+
+ tcvtrowps2ph\p %edx, %tmm5, %zmm30
+ tcvtrowps2ph\p $8, %tmm5, %zmm30
+ .endr
+
+_intel:
+ .intel_syntax noprefix
+
+ tilezero tmm0
+ ldtilecfg [rcx]
+ sttilecfg [rcx]
+ tilerelease
+
+ tilemovrow zmm1, tmm2, ebx
+ tilemovrow zmm1, tmm2, 8
+
+ tcvtrowd2ps zmm30, tmm5, edx
+ tcvtrowd2ps zmm30, tmm5, 8
+
+ .irp p, h, l
+ tcvtrowps2bf16\p zmm30, tmm5, edx
+ tcvtrowps2bf16\p zmm30, tmm5, 8
+
+ tcvtrowps2ph\p zmm30, tmm5, edx
+ tcvtrowps2ph\p zmm30, tmm5, 8
+ .endr
diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp
index eb10d9b8b9f..58ef1a0e21b 100644
--- a/gas/testsuite/gas/i386/x86-64.exp
+++ b/gas/testsuite/gas/i386/x86-64.exp
@@ -691,6 +691,8 @@ run_list_test "x86-64-amx-inval"
run_dump_test "x86-64-amx"
run_dump_test "x86-64-amx-intel"
run_dump_test "x86-64-amx-bad"
+run_dump_test "x86-64-ace_v1"
+run_dump_test "x86-64-ace_v1-intel"
if { ![istarget "*-*-aix*"]
&& ![istarget "*-*-*bsd*"]
diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h
index 0135703912a..fd2e29432ab 100644
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -248,11 +248,11 @@
{ Bad_Opcode },
{ "vpmovssdb", { EXxmmqd, XM }, 0 },
},
- /* PREFIX_EVEX_0F384A_W_0_L_2 */
+ /* PREFIX_EVEX_0F384A_X86_64_W_0_L_2 */
{
{ Bad_Opcode },
- { "tcvtrowd2ps", { XM, Rtmm, VexGdq }, 0 },
- { "tilemovrow", { XM, Rtmm, VexGdq }, 0 },
+ { "tcvtrowd2ps", { XM, Rtmm, VexGd }, 0 },
+ { "tilemovrow", { XM, Rtmm, VexGd }, 0 },
},
/* PREFIX_EVEX_0F3852 */
{
@@ -275,12 +275,12 @@
{ Bad_Opcode },
{ "vp2intersectY%DQ", { MaskG, Vex, EXx, EXxEVexS }, 0 },
},
- /* PREFIX_EVEX_0F386D_W_0_L_2 */
+ /* PREFIX_EVEX_0F386D_X86_64_W_0_L_2 */
{
- { "tcvtrowps2phh", { XM, Rtmm, VexGdq }, 0 },
- { "tcvtrowps2bf16l", { XM, Rtmm, VexGdq }, 0 },
- { "tcvtrowps2phl", { XM, Rtmm, VexGdq }, 0 },
- { "tcvtrowps2bf16h", { XM, Rtmm, VexGdq }, 0 },
+ { "tcvtrowps2phh", { XM, Rtmm, VexGd }, 0 },
+ { "tcvtrowps2bf16l", { XM, Rtmm, VexGd }, 0 },
+ { "tcvtrowps2phl", { XM, Rtmm, VexGd }, 0 },
+ { "tcvtrowps2bf16h", { XM, Rtmm, VexGd }, 0 },
},
/* PREFIX_EVEX_0F3872 */
{
@@ -324,7 +324,7 @@
{ "%XEvfmsub213s%XW", { XMScalar, VexScalar, EXdq, EXxEVexR }, 0 },
{ "v4fnmadds%XS", { XMScalar, VexScalar, Mxmm }, 0 },
},
- /* PREFIX_EVEX_0F3A07_W_0_L_2 */
+ /* PREFIX_EVEX_0F3A07_X86_64_W_0_L_2 */
{
{ "tcvtrowps2phh", { XM, Rtmm, Ib }, 0 },
{ "tcvtrowd2ps", { XM, Rtmm, Ib }, 0 },
@@ -402,7 +402,7 @@
{ Bad_Opcode },
{ "vfpclasss%XW", { MaskG, EXdq, Ib }, 0 },
},
- /* PREFIX_EVEX_0F3A77_W_0_L_2 */
+ /* PREFIX_EVEX_0F3A77_X86_64_W_0_L_2 */
{
{ Bad_Opcode },
{ "tcvtrowps2bf16l", { XM, Rtmm, Ib }, 0 },
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 44529d0aa82..db957d1638f 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -600,6 +600,7 @@ fetch_error (const instr_info *ins)
#define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
#define VexGdq { OP_VEX, dq_mode }
#define VexGb { OP_VEX, b_mode }
+#define VexGd { OP_VEX, d_mode }
#define VexGv { OP_VEX, v_mode }
#define VexTmm { OP_VEX, tmm_mode }
#define XMVexI4 { OP_REG_VexI4, x_mode }
@@ -14289,8 +14290,16 @@ OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
}
break;
case 512:
- names = att_names_zmm;
- ins->evex_used |= EVEX_len_used;
+ if (bytemode == d_mode)
+ {
+ names = att_names32;
+ ins->evex_used |= EVEX_len_used;
+ }
+ else
+ {
+ names = att_names_zmm;
+ ins->evex_used |= EVEX_len_used;
+ }
break;
default:
abort ();
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index cf37d8786e9..0a7e3008065 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -269,6 +269,8 @@ static const dependency isa_dependencies[] =
"RTM|HLE" },
{ "TSXLDTRK",
"RTM" },
+ { "ACE_V1",
+ "AVX10_V2_AUX|AVX10_1_AUX|64" },
{ "AMX_TILE",
"XSAVE|64" },
{ "AMX_INT8",
@@ -478,6 +480,7 @@ static bitfield cpu_flags[] =
BITFIELD (WAITPKG),
BITFIELD (UINTR),
BITFIELD (CLDEMOTE),
+ BITFIELD (ACE_V1),
BITFIELD (AMX_INT8),
BITFIELD (AMX_BF16),
BITFIELD (AMX_FP16),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index cd8f228f5a9..1e3ffe8c487 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -367,6 +367,8 @@ enum i386_cpu
CpuAVX10_2,
/* Intel AMX-TRANSPOSE Instructions support required. */
CpuAMX_TRANSPOSE,
+ /* ACE V1 instructions support required. */
+ CpuACE_V1,
/* Not supported in the 64bit mode */
CpuNo64,
@@ -405,6 +407,7 @@ enum i386_cpu
cpuapx_f:1, \
cpuavx10_2:1, \
cpuamx_transpose:1, \
+ cpuace_v1:1, \
/* NOTE: This field needs to remain last. */ \
cpuno64:1
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 8ff7bf1828e..9540166f751 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3238,20 +3238,24 @@ xresldtrk, 0xf20f01e9, TSXLDTRK, NoSuf, {}
// TSXLDTRK instructions end.
-// AMX instructions.
+// AMX & ACE_V1 instructions.
ldtilecfg, 0x49/0, APX_F(AMX_TILE), Modrm|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex }
+ldtilecfg, 0x49/0, ACE_V1, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex }
sttilecfg, 0x6649/0, APX_F(AMX_TILE), Modrm|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex }
+sttilecfg, 0x6649/0, ACE_V1, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex }
tcmmimfp16ps, 0x666c, AMX_COMPLEX, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
tcmmrlfp16ps, 0x6c, AMX_COMPLEX, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
tdpbf16ps, 0xf35c, AMX_BF16, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
tdpfp16ps, 0xf25c, AMX_FP16, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
-tdpbssd, 0xf25e, AMX_INT8, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
-tdpbuud, 0x5e, AMX_INT8, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
-tdpbusd, 0x665e, AMX_INT8, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
-tdpbsud, 0xf35e, AMX_INT8, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
+
+<tdpb:pfx, uu:, ss:f2, su:f3, us:66>
+
+tdpb<tdpb>d, 0x<tdpb:pfx>5e, AMX_INT8, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
+
+<tdpb>
tileloadd, 0xf24b, APX_F(AMX_TILE), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
tileloaddt1, 0x664b, APX_F(AMX_TILE), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
@@ -3259,9 +3263,8 @@ tileloaddrs, 0xf24a, APX_F(AMX_MOVRS), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoS
tileloaddrst1, 0x664a, APX_F(AMX_MOVRS), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
tilestored, 0xf34b, APX_F(AMX_TILE), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { RegTMM, Unspecified|BaseIndex }
-tilerelease, 0x49c0, AMX_TILE, Vex128|Space0F38|VexW0|NoSuf, {}
-
-tilezero, 0xf249, AMX_TILE, Modrm|Vex128|Space0F38|VexW0|NoSuf, { RegTMM }
+tilerelease, 0x49c0, AMX_TILE|ACE_V1, Vex128|Space0F38|VexW0|NoSuf, {}
+tilezero, 0xf249, AMX_TILE|ACE_V1, Modrm|Vex128|Space0F38|VexW0|NoSuf, { RegTMM }
<z:pfx, z0:, z1:66>
@@ -3292,22 +3295,22 @@ tdpbhf8ps, 0xf2fd, AMX_FP8, Modrm|Vex128|Map5|Src2VVVV|VexW0|NoSuf, { RegTMM, Re
tdphbf8ps, 0xf3fd, AMX_FP8, Modrm|Vex128|Map5|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
tdphf8ps, 0x66fd, AMX_FP8, Modrm|Vex128|Map5|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
-tcvtrowd2ps, 0xf34a, AMX_AVX512, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
-tcvtrowd2ps, 0xf307, AMX_AVX512, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
+tcvtrowd2ps, 0xf34a, AMX_AVX512|ACE_V1, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
+tcvtrowd2ps, 0xf307, AMX_AVX512|ACE_V1, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
-tcvtrowps2bf16h, 0xf26d, AMX_AVX512, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
-tcvtrowps2bf16h, 0xf207, AMX_AVX512, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
-tcvtrowps2bf16l, 0xf36d, AMX_AVX512, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
-tcvtrowps2bf16l, 0xf377, AMX_AVX512, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
-tcvtrowps2phh, 0x6d, AMX_AVX512, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
-tcvtrowps2phh, 0x07, AMX_AVX512, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
-tcvtrowps2phl, 0x666d, AMX_AVX512, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
-tcvtrowps2phl, 0xf277, AMX_AVX512, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
+tcvtrowps2bf16h, 0xf26d, AMX_AVX512|ACE_V1, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
+tcvtrowps2bf16h, 0xf207, AMX_AVX512|ACE_V1, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
+tcvtrowps2bf16l, 0xf36d, AMX_AVX512|ACE_V1, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
+tcvtrowps2bf16l, 0xf377, AMX_AVX512|ACE_V1, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
+tcvtrowps2phh, 0x6d, AMX_AVX512|ACE_V1, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
+tcvtrowps2phh, 0x07, AMX_AVX512|ACE_V1, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
+tcvtrowps2phl, 0x666d, AMX_AVX512|ACE_V1, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
+tcvtrowps2phl, 0xf277, AMX_AVX512|ACE_V1, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
-tilemovrow, 0x664a, AMX_AVX512, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
-tilemovrow, 0x6607, AMX_AVX512, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
+tilemovrow, 0x664a, AMX_AVX512|ACE_V1, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
+tilemovrow, 0x6607, AMX_AVX512|ACE_V1, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
-// AMX instructions end.
+// AMX & ACE_V1 instructions end.
// KEYLOCKER instructions.
diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl
index 74234c503d6..3a4fa885177 100644
--- a/opcodes/i386-reg.tbl
+++ b/opcodes/i386-reg.tbl
@@ -344,7 +344,7 @@ zmm28, Class=RegSIMD|Zmmword, RegVRex|RegRex, 4, Dw2Inval, 79
zmm29, Class=RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval, 80
zmm30, Class=RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, 81
zmm31, Class=RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, 82
-// TMM registers for AMX
+// TMM registers for AMX/ACE V1
tmm0, Class=RegSIMD|Tmmword, 0, 0, Dw2Inval, Dw2Inval
tmm1, Class=RegSIMD|Tmmword, 0, 1, Dw2Inval, Dw2Inval
tmm2, Class=RegSIMD|Tmmword, 0, 2, Dw2Inval, Dw2Inval
--
2.34.1
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