[PATCH v3 2/2] x86: ACE_V1 support for ACE-specific instructions
Rohan Shenoy
RohanRadhesh.Shenoy@amd.com
Wed Sep 9 13:25:18 GMT 2026
Add assembler and disassembler support for block scale register and its
operations, tile move write, outer product instructions:
- BSRINIT, BSRMOVF/H/L.
- TILEMOVCOL, TILEMOVROW (write-to tmm form).
- TOP2BF16PS, TOP4BSSD/BSUD/BUSD/BUUD, and TOP4MX* variants.
Reference: AI Compute Extensions (ACE) Specification, v1.16.2
https://x86ecosystem.org/wp-content/uploads/2026/06/ACE_v1_Specification_public.pdf
Co-authored-by: Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
Co-authored-by: Umesh Kalvakuntla <Umesh.Kalvakuntla@amd.com>
---
gas/NEWS | 4 +
gas/config/tc-i386.c | 12 ++-
gas/testsuite/gas/i386/x86-64-ace_v1-intel.d | 50 +++++++++++++
gas/testsuite/gas/i386/x86-64-ace_v1.d | 50 +++++++++++++
gas/testsuite/gas/i386/x86-64-ace_v1.s | 56 ++++++++++++++
opcodes/i386-dis-evex-len.h | 77 +++++++++++++++++++-
opcodes/i386-dis-evex-prefix.h | 64 ++++++++++++++++
opcodes/i386-dis-evex-w.h | 35 ++++++++-
opcodes/i386-dis-evex-x86-64.h | 35 +++++++++
opcodes/i386-dis-evex.h | 14 ++--
opcodes/i386-dis.c | 71 ++++++++++++++++++
opcodes/i386-gen.c | 1 +
opcodes/i386-opc.h | 1 +
opcodes/i386-opc.tbl | 32 +++++++-
opcodes/i386-reg.tbl | 2 +
15 files changed, 490 insertions(+), 14 deletions(-)
diff --git a/gas/NEWS b/gas/NEWS
index 8b07d86daa3..e5c93f4b3bd 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,9 @@
-*- text -*-
+* Add support for the x86 ACE V1 (AI Compute Extensions) instructions,
+ including tile data movement, block scale register operations and tile
+ outer products.
+
* Add support for the x86 AVX10_V2_AUX instructions.
* The avr target supports .gnu_attribute 4 (Tag_GNU_AVR_VTABLE_AS).
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 6ad210ba404..cc8cc30b247 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -3963,6 +3963,7 @@ const type_names[] =
{ { .bitfield = { .class = RegSIMD, .tmmword = 1 } }, "rTMM" },
{ { .bitfield = { .class = RegMask } }, "Mask reg" },
{ { .bitfield = { .class = RegBND } }, "rBND" },
+ { { .bitfield = { .class = RegBSR } }, "bsr" },
};
static void
@@ -9902,7 +9903,8 @@ match_template (char mnem_suffix)
&& (intel_syntax || intel_mnemonic))
found_reverse_match |= Opcode_FloatR;
}
- else if (is_cpu (t, CpuFMA4) || is_cpu (t, CpuXOP))
+ else if (is_cpu (t, CpuFMA4) || is_cpu (t, CpuXOP)
+ || is_cpu (t, CpuACE_V1))
{
found_reverse_match = Opcode_VexW;
goto check_operands_345;
@@ -10228,7 +10230,8 @@ match_template (char mnem_suffix)
i.tm.opcode_modifier.vexw ^= VEXW0 ^ VEXW1;
/* In 3-operand insns XOP.W changes which operand goes into XOP.vvvv. */
- i.tm.opcode_modifier.vexvvvv = VexVVVV_SRC1;
+ if (!is_cpu (t, CpuACE_V1))
+ i.tm.opcode_modifier.vexvvvv = VexVVVV_SRC1;
swap_first_2:
j = i.tm_types[0].bitfield.imm8;
@@ -11108,7 +11111,7 @@ process_operands (void)
not ModR/M.rm. To avoid special casing this in build_modrm_byte(), fake a
new destination operand here, while converting the source one to register
number 0. */
- if (i.tm.mnem_off == MN_tilezero)
+ if (i.tm.mnem_off == MN_tilezero || i.tm.mnem_off == MN_bsrinit)
{
copy_operand (1, 0);
i.op[0].regs -= i.op[0].regs->reg_num;
@@ -17086,6 +17089,9 @@ static bool check_register (const reg_entry *r)
if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx)
return false;
+ if (r->reg_type.bitfield.class == RegBSR && !cpu_arch_flags.bitfield.cpuace_v1)
+ return false;
+
/* Don't allow fake index register unless allow_index_reg isn't 0. */
if (!allow_index_reg && r->reg_num == RegIZ)
return false;
diff --git a/gas/testsuite/gas/i386/x86-64-ace_v1-intel.d b/gas/testsuite/gas/i386/x86-64-ace_v1-intel.d
index d5aeddfc1bd..3dcc0392759 100644
--- a/gas/testsuite/gas/i386/x86-64-ace_v1-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-ace_v1-intel.d
@@ -15,16 +15,41 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*c4 e2 78 49 c0[ ]+tilerelease
[ ]*[a-f0-9]+:[ ]*62 f2 65 48 4a ca[ ]+tilemovrow zmm1,tmm2,ebx
[ ]*[a-f0-9]+:[ ]*62 f3 7d 48 07 ca 08[ ]+tilemovrow zmm1,tmm2,0x8
+[ ]*[a-f0-9]+:[ ]*62 f2 e5 48 4a ca[ ]+tilemovrow tmm1,zmm2,ebx
+[ ]*[a-f0-9]+:[ ]*62 f3 fd 48 07 ca 08[ ]+tilemovrow tmm1,zmm2,0x8
+[ ]*[a-f0-9]+:[ ]*62 f2 e5 48 4b ca[ ]+tilemovcol tmm1,zmm2,ebx
+[ ]*[a-f0-9]+:[ ]*62 f3 fd 48 2f ca 08[ ]+tilemovcol tmm1,zmm2,0x8
[ ]*[a-f0-9]+:[ ]*62 62 6e 48 4a f5[ ]+tcvtrowd2ps zmm30,tmm5,edx
[ ]*[a-f0-9]+:[ ]*62 63 7e 48 07 f5 08[ ]+tcvtrowd2ps zmm30,tmm5,0x8
[ ]*[a-f0-9]+:[ ]*62 62 6f 48 6d f5[ ]+tcvtrowps2bf16h zmm30,tmm5,edx
[ ]*[a-f0-9]+:[ ]*62 63 7f 48 07 f5 08[ ]+tcvtrowps2bf16h zmm30,tmm5,0x8
[ ]*[a-f0-9]+:[ ]*62 62 6c 48 6d f5[ ]+tcvtrowps2phh zmm30,tmm5,edx
[ ]*[a-f0-9]+:[ ]*62 63 7c 48 07 f5 08[ ]+tcvtrowps2phh zmm30,tmm5,0x8
+[ ]*[a-f0-9]+:[ ]*62 d6 ff 48 95 c2[ ]+bsrmovh bsr0,zmm10
+[ ]*[a-f0-9]+:[ ]*62 f6 ff 48 95 41 7f[ ]+bsrmovh bsr0,ZMMWORD PTR \[rcx\+0x1fc0\]
+[ ]*[a-f0-9]+:[ ]*62 f6 7f 48 95 c4[ ]+bsrmovh zmm4,bsr0
+[ ]*[a-f0-9]+:[ ]*62 f6 7f 48 95 41 80[ ]+bsrmovh ZMMWORD PTR \[rcx-0x2000\],bsr0
[ ]*[a-f0-9]+:[ ]*62 62 6e 48 6d f5[ ]+tcvtrowps2bf16l zmm30,tmm5,edx
[ ]*[a-f0-9]+:[ ]*62 63 7e 48 77 f5 08[ ]+tcvtrowps2bf16l zmm30,tmm5,0x8
[ ]*[a-f0-9]+:[ ]*62 62 6d 48 6d f5[ ]+tcvtrowps2phl zmm30,tmm5,edx
[ ]*[a-f0-9]+:[ ]*62 63 7f 48 77 f5 08[ ]+tcvtrowps2phl zmm30,tmm5,0x8
+[ ]*[a-f0-9]+:[ ]*62 d6 fe 48 95 c2[ ]+bsrmovl bsr0,zmm10
+[ ]*[a-f0-9]+:[ ]*62 f6 fe 48 95 41 7f[ ]+bsrmovl bsr0,ZMMWORD PTR \[rcx\+0x1fc0\]
+[ ]*[a-f0-9]+:[ ]*62 f6 7e 48 95 c4[ ]+bsrmovl zmm4,bsr0
+[ ]*[a-f0-9]+:[ ]*62 f6 7e 48 95 41 80[ ]+bsrmovl ZMMWORD PTR \[rcx-0x2000\],bsr0
+[ ]*[a-f0-9]+:[ ]*c4 e2 fb 49 c0[ ]+bsrinit bsr0
+[ ]*[a-f0-9]+:[ ]*62 f6 f4 48 95 c3[ ]+bsrmovf bsr0,zmm1,zmm3
+[ ]*[a-f0-9]+:[ ]*62 f6 f4 48 95 41 7f[ ]+bsrmovf bsr0,zmm1,ZMMWORD PTR \[rcx\+0x1fc0\]
+[ ]*[a-f0-9]+:[ ]*62 f3 6c 48 8d c9 00[ ]+top4mxbf8ps tmm1,zmm1,zmm2,0x0
+[ ]*[a-f0-9]+:[ ]*62 f3 6f 48 8d c9 00[ ]+top4mxbhf8ps tmm1,zmm1,zmm2,0x0
+[ ]*[a-f0-9]+:[ ]*62 f3 6e 48 8d c9 00[ ]+top4mxhbf8ps tmm1,zmm1,zmm2,0x0
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 48 8d c9 00[ ]+top4mxhf8ps tmm1,zmm1,zmm2,0x0
+[ ]*[a-f0-9]+:[ ]*62 f3 6f 48 8f c9 00[ ]+top4mxbssps tmm1,zmm1,zmm2,0x0
+[ ]*[a-f0-9]+:[ ]*62 f2 6e 48 5c c1[ ]+top2bf16ps tmm0,zmm1,zmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 6f 48 5e c1[ ]+top4bssd tmm0,zmm1,zmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 6e 48 5e c1[ ]+top4bsud tmm0,zmm1,zmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 6d 48 5e c1[ ]+top4busd tmm0,zmm1,zmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 6c 48 5e c1[ ]+top4buud tmm0,zmm1,zmm2
[0-9a-f]+ <_intel>:
[ ]*[a-f0-9]+:[ ]*c4 e2 7b 49 c0[ ]+tilezero tmm0
[ ]*[a-f0-9]+:[ ]*c4 e2 78 49 01[ ]+ldtilecfg \[rcx\]
@@ -32,13 +57,38 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*c4 e2 78 49 c0[ ]+tilerelease
[ ]*[a-f0-9]+:[ ]*62 f2 65 48 4a ca[ ]+tilemovrow zmm1,tmm2,ebx
[ ]*[a-f0-9]+:[ ]*62 f3 7d 48 07 ca 08[ ]+tilemovrow zmm1,tmm2,0x8
+[ ]*[a-f0-9]+:[ ]*62 f2 e5 48 4a ca[ ]+tilemovrow tmm1,zmm2,ebx
+[ ]*[a-f0-9]+:[ ]*62 f3 fd 48 07 ca 08[ ]+tilemovrow tmm1,zmm2,0x8
+[ ]*[a-f0-9]+:[ ]*62 f2 e5 48 4b ca[ ]+tilemovcol tmm1,zmm2,ebx
+[ ]*[a-f0-9]+:[ ]*62 f3 fd 48 2f ca 08[ ]+tilemovcol tmm1,zmm2,0x8
[ ]*[a-f0-9]+:[ ]*62 62 6e 48 4a f5[ ]+tcvtrowd2ps zmm30,tmm5,edx
[ ]*[a-f0-9]+:[ ]*62 63 7e 48 07 f5 08[ ]+tcvtrowd2ps zmm30,tmm5,0x8
[ ]*[a-f0-9]+:[ ]*62 62 6f 48 6d f5[ ]+tcvtrowps2bf16h zmm30,tmm5,edx
[ ]*[a-f0-9]+:[ ]*62 63 7f 48 07 f5 08[ ]+tcvtrowps2bf16h zmm30,tmm5,0x8
[ ]*[a-f0-9]+:[ ]*62 62 6c 48 6d f5[ ]+tcvtrowps2phh zmm30,tmm5,edx
[ ]*[a-f0-9]+:[ ]*62 63 7c 48 07 f5 08[ ]+tcvtrowps2phh zmm30,tmm5,0x8
+[ ]*[a-f0-9]+:[ ]*62 d6 ff 48 95 c2[ ]+bsrmovh bsr0,zmm10
+[ ]*[a-f0-9]+:[ ]*62 f6 ff 48 95 41 7f[ ]+bsrmovh bsr0,ZMMWORD PTR \[rcx\+0x1fc0\]
+[ ]*[a-f0-9]+:[ ]*62 f6 7f 48 95 c4[ ]+bsrmovh zmm4,bsr0
+[ ]*[a-f0-9]+:[ ]*62 f6 7f 48 95 41 80[ ]+bsrmovh ZMMWORD PTR \[rcx-0x2000\],bsr0
[ ]*[a-f0-9]+:[ ]*62 62 6e 48 6d f5[ ]+tcvtrowps2bf16l zmm30,tmm5,edx
[ ]*[a-f0-9]+:[ ]*62 63 7e 48 77 f5 08[ ]+tcvtrowps2bf16l zmm30,tmm5,0x8
[ ]*[a-f0-9]+:[ ]*62 62 6d 48 6d f5[ ]+tcvtrowps2phl zmm30,tmm5,edx
[ ]*[a-f0-9]+:[ ]*62 63 7f 48 77 f5 08[ ]+tcvtrowps2phl zmm30,tmm5,0x8
+[ ]*[a-f0-9]+:[ ]*62 d6 fe 48 95 c2[ ]+bsrmovl bsr0,zmm10
+[ ]*[a-f0-9]+:[ ]*62 f6 fe 48 95 41 7f[ ]+bsrmovl bsr0,ZMMWORD PTR \[rcx\+0x1fc0\]
+[ ]*[a-f0-9]+:[ ]*62 f6 7e 48 95 c4[ ]+bsrmovl zmm4,bsr0
+[ ]*[a-f0-9]+:[ ]*62 f6 7e 48 95 41 80[ ]+bsrmovl ZMMWORD PTR \[rcx-0x2000\],bsr0
+[ ]*[a-f0-9]+:[ ]*c4 e2 fb 49 c0[ ]+bsrinit bsr0
+[ ]*[a-f0-9]+:[ ]*62 f6 f4 48 95 c3[ ]+bsrmovf bsr0,zmm1,zmm3
+[ ]*[a-f0-9]+:[ ]*62 f6 f4 48 95 41 7f[ ]+bsrmovf bsr0,zmm1,ZMMWORD PTR \[rcx\+0x1fc0\]
+[ ]*[a-f0-9]+:[ ]*62 f3 6c 48 8d c9 00[ ]+top4mxbf8ps tmm1,zmm1,zmm2,0x0
+[ ]*[a-f0-9]+:[ ]*62 f3 6f 48 8d c9 00[ ]+top4mxbhf8ps tmm1,zmm1,zmm2,0x0
+[ ]*[a-f0-9]+:[ ]*62 f3 6e 48 8d c9 00[ ]+top4mxhbf8ps tmm1,zmm1,zmm2,0x0
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 48 8d c9 00[ ]+top4mxhf8ps tmm1,zmm1,zmm2,0x0
+[ ]*[a-f0-9]+:[ ]*62 f3 6f 48 8f c9 00[ ]+top4mxbssps tmm1,zmm1,zmm2,0x0
+[ ]*[a-f0-9]+:[ ]*62 f2 6e 48 5c c1[ ]+top2bf16ps tmm0,zmm1,zmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 6f 48 5e c1[ ]+top4bssd tmm0,zmm1,zmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 6e 48 5e c1[ ]+top4bsud tmm0,zmm1,zmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 6d 48 5e c1[ ]+top4busd tmm0,zmm1,zmm2
+[ ]*[a-f0-9]+:[ ]*62 f2 6c 48 5e c1[ ]+top4buud tmm0,zmm1,zmm2
diff --git a/gas/testsuite/gas/i386/x86-64-ace_v1.d b/gas/testsuite/gas/i386/x86-64-ace_v1.d
index 58a8ce21b07..02b60be798d 100644
--- a/gas/testsuite/gas/i386/x86-64-ace_v1.d
+++ b/gas/testsuite/gas/i386/x86-64-ace_v1.d
@@ -15,16 +15,41 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*c4 e2 78 49 c0[ ]+tilerelease
[ ]*[a-f0-9]+:[ ]*62 f2 65 48 4a ca[ ]+tilemovrow %ebx,%tmm2,%zmm1
[ ]*[a-f0-9]+:[ ]*62 f3 7d 48 07 ca 08[ ]+tilemovrow \$0x8,%tmm2,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 e5 48 4a ca[ ]+tilemovrow %ebx,%zmm2,%tmm1
+[ ]*[a-f0-9]+:[ ]*62 f3 fd 48 07 ca 08[ ]+tilemovrow \$0x8,%zmm2,%tmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 e5 48 4b ca[ ]+tilemovcol %ebx,%zmm2,%tmm1
+[ ]*[a-f0-9]+:[ ]*62 f3 fd 48 2f ca 08[ ]+tilemovcol \$0x8,%zmm2,%tmm1
[ ]*[a-f0-9]+:[ ]*62 62 6e 48 4a f5[ ]+tcvtrowd2ps %edx,%tmm5,%zmm30
[ ]*[a-f0-9]+:[ ]*62 63 7e 48 07 f5 08[ ]+tcvtrowd2ps \$0x8,%tmm5,%zmm30
[ ]*[a-f0-9]+:[ ]*62 62 6f 48 6d f5[ ]+tcvtrowps2bf16h %edx,%tmm5,%zmm30
[ ]*[a-f0-9]+:[ ]*62 63 7f 48 07 f5 08[ ]+tcvtrowps2bf16h \$0x8,%tmm5,%zmm30
[ ]*[a-f0-9]+:[ ]*62 62 6c 48 6d f5[ ]+tcvtrowps2phh %edx,%tmm5,%zmm30
[ ]*[a-f0-9]+:[ ]*62 63 7c 48 07 f5 08[ ]+tcvtrowps2phh \$0x8,%tmm5,%zmm30
+[ ]*[a-f0-9]+:[ ]*62 d6 ff 48 95 c2[ ]+bsrmovh %zmm10,%bsr0
+[ ]*[a-f0-9]+:[ ]*62 f6 ff 48 95 41 7f[ ]+bsrmovh 0x1fc0\(%rcx\),%bsr0
+[ ]*[a-f0-9]+:[ ]*62 f6 7f 48 95 c4[ ]+bsrmovh %bsr0,%zmm4
+[ ]*[a-f0-9]+:[ ]*62 f6 7f 48 95 41 80[ ]+bsrmovh %bsr0,-0x2000\(%rcx\)
[ ]*[a-f0-9]+:[ ]*62 62 6e 48 6d f5[ ]+tcvtrowps2bf16l %edx,%tmm5,%zmm30
[ ]*[a-f0-9]+:[ ]*62 63 7e 48 77 f5 08[ ]+tcvtrowps2bf16l \$0x8,%tmm5,%zmm30
[ ]*[a-f0-9]+:[ ]*62 62 6d 48 6d f5[ ]+tcvtrowps2phl %edx,%tmm5,%zmm30
[ ]*[a-f0-9]+:[ ]*62 63 7f 48 77 f5 08[ ]+tcvtrowps2phl \$0x8,%tmm5,%zmm30
+[ ]*[a-f0-9]+:[ ]*62 d6 fe 48 95 c2[ ]+bsrmovl %zmm10,%bsr0
+[ ]*[a-f0-9]+:[ ]*62 f6 fe 48 95 41 7f[ ]+bsrmovl 0x1fc0\(%rcx\),%bsr0
+[ ]*[a-f0-9]+:[ ]*62 f6 7e 48 95 c4[ ]+bsrmovl %bsr0,%zmm4
+[ ]*[a-f0-9]+:[ ]*62 f6 7e 48 95 41 80[ ]+bsrmovl %bsr0,-0x2000\(%rcx\)
+[ ]*[a-f0-9]+:[ ]*c4 e2 fb 49 c0[ ]+bsrinit %bsr0
+[ ]*[a-f0-9]+:[ ]*62 f6 f4 48 95 c3[ ]+bsrmovf %zmm3,%zmm1,%bsr0
+[ ]*[a-f0-9]+:[ ]*62 f6 f4 48 95 41 7f[ ]+bsrmovf 0x1fc0\(%rcx\),%zmm1,%bsr0
+[ ]*[a-f0-9]+:[ ]*62 f3 6c 48 8d c9 00[ ]+top4mxbf8ps \$0x0,%zmm2,%zmm1,%tmm1
+[ ]*[a-f0-9]+:[ ]*62 f3 6f 48 8d c9 00[ ]+top4mxbhf8ps \$0x0,%zmm2,%zmm1,%tmm1
+[ ]*[a-f0-9]+:[ ]*62 f3 6e 48 8d c9 00[ ]+top4mxhbf8ps \$0x0,%zmm2,%zmm1,%tmm1
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 48 8d c9 00[ ]+top4mxhf8ps \$0x0,%zmm2,%zmm1,%tmm1
+[ ]*[a-f0-9]+:[ ]*62 f3 6f 48 8f c9 00[ ]+top4mxbssps \$0x0,%zmm2,%zmm1,%tmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 6e 48 5c c1[ ]+top2bf16ps %zmm2,%zmm1,%tmm0
+[ ]*[a-f0-9]+:[ ]*62 f2 6f 48 5e c1[ ]+top4bssd %zmm2,%zmm1,%tmm0
+[ ]*[a-f0-9]+:[ ]*62 f2 6e 48 5e c1[ ]+top4bsud %zmm2,%zmm1,%tmm0
+[ ]*[a-f0-9]+:[ ]*62 f2 6d 48 5e c1[ ]+top4busd %zmm2,%zmm1,%tmm0
+[ ]*[a-f0-9]+:[ ]*62 f2 6c 48 5e c1[ ]+top4buud %zmm2,%zmm1,%tmm0
[0-9a-f]+ <_intel>:
[ ]*[a-f0-9]+:[ ]*c4 e2 7b 49 c0[ ]+tilezero %tmm0
[ ]*[a-f0-9]+:[ ]*c4 e2 78 49 01[ ]+ldtilecfg \(%rcx\)
@@ -32,13 +57,38 @@ Disassembly of section \.text:
[ ]*[a-f0-9]+:[ ]*c4 e2 78 49 c0[ ]+tilerelease
[ ]*[a-f0-9]+:[ ]*62 f2 65 48 4a ca[ ]+tilemovrow %ebx,%tmm2,%zmm1
[ ]*[a-f0-9]+:[ ]*62 f3 7d 48 07 ca 08[ ]+tilemovrow \$0x8,%tmm2,%zmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 e5 48 4a ca[ ]+tilemovrow %ebx,%zmm2,%tmm1
+[ ]*[a-f0-9]+:[ ]*62 f3 fd 48 07 ca 08[ ]+tilemovrow \$0x8,%zmm2,%tmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 e5 48 4b ca[ ]+tilemovcol %ebx,%zmm2,%tmm1
+[ ]*[a-f0-9]+:[ ]*62 f3 fd 48 2f ca 08[ ]+tilemovcol \$0x8,%zmm2,%tmm1
[ ]*[a-f0-9]+:[ ]*62 62 6e 48 4a f5[ ]+tcvtrowd2ps %edx,%tmm5,%zmm30
[ ]*[a-f0-9]+:[ ]*62 63 7e 48 07 f5 08[ ]+tcvtrowd2ps \$0x8,%tmm5,%zmm30
[ ]*[a-f0-9]+:[ ]*62 62 6f 48 6d f5[ ]+tcvtrowps2bf16h %edx,%tmm5,%zmm30
[ ]*[a-f0-9]+:[ ]*62 63 7f 48 07 f5 08[ ]+tcvtrowps2bf16h \$0x8,%tmm5,%zmm30
[ ]*[a-f0-9]+:[ ]*62 62 6c 48 6d f5[ ]+tcvtrowps2phh %edx,%tmm5,%zmm30
[ ]*[a-f0-9]+:[ ]*62 63 7c 48 07 f5 08[ ]+tcvtrowps2phh \$0x8,%tmm5,%zmm30
+[ ]*[a-f0-9]+:[ ]*62 d6 ff 48 95 c2[ ]+bsrmovh %zmm10,%bsr0
+[ ]*[a-f0-9]+:[ ]*62 f6 ff 48 95 41 7f[ ]+bsrmovh 0x1fc0\(%rcx\),%bsr0
+[ ]*[a-f0-9]+:[ ]*62 f6 7f 48 95 c4[ ]+bsrmovh %bsr0,%zmm4
+[ ]*[a-f0-9]+:[ ]*62 f6 7f 48 95 41 80[ ]+bsrmovh %bsr0,-0x2000\(%rcx\)
[ ]*[a-f0-9]+:[ ]*62 62 6e 48 6d f5[ ]+tcvtrowps2bf16l %edx,%tmm5,%zmm30
[ ]*[a-f0-9]+:[ ]*62 63 7e 48 77 f5 08[ ]+tcvtrowps2bf16l \$0x8,%tmm5,%zmm30
[ ]*[a-f0-9]+:[ ]*62 62 6d 48 6d f5[ ]+tcvtrowps2phl %edx,%tmm5,%zmm30
[ ]*[a-f0-9]+:[ ]*62 63 7f 48 77 f5 08[ ]+tcvtrowps2phl \$0x8,%tmm5,%zmm30
+[ ]*[a-f0-9]+:[ ]*62 d6 fe 48 95 c2[ ]+bsrmovl %zmm10,%bsr0
+[ ]*[a-f0-9]+:[ ]*62 f6 fe 48 95 41 7f[ ]+bsrmovl 0x1fc0\(%rcx\),%bsr0
+[ ]*[a-f0-9]+:[ ]*62 f6 7e 48 95 c4[ ]+bsrmovl %bsr0,%zmm4
+[ ]*[a-f0-9]+:[ ]*62 f6 7e 48 95 41 80[ ]+bsrmovl %bsr0,-0x2000\(%rcx\)
+[ ]*[a-f0-9]+:[ ]*c4 e2 fb 49 c0[ ]+bsrinit %bsr0
+[ ]*[a-f0-9]+:[ ]*62 f6 f4 48 95 c3[ ]+bsrmovf %zmm3,%zmm1,%bsr0
+[ ]*[a-f0-9]+:[ ]*62 f6 f4 48 95 41 7f[ ]+bsrmovf 0x1fc0\(%rcx\),%zmm1,%bsr0
+[ ]*[a-f0-9]+:[ ]*62 f3 6c 48 8d c9 00[ ]+top4mxbf8ps \$0x0,%zmm2,%zmm1,%tmm1
+[ ]*[a-f0-9]+:[ ]*62 f3 6f 48 8d c9 00[ ]+top4mxbhf8ps \$0x0,%zmm2,%zmm1,%tmm1
+[ ]*[a-f0-9]+:[ ]*62 f3 6e 48 8d c9 00[ ]+top4mxhbf8ps \$0x0,%zmm2,%zmm1,%tmm1
+[ ]*[a-f0-9]+:[ ]*62 f3 6d 48 8d c9 00[ ]+top4mxhf8ps \$0x0,%zmm2,%zmm1,%tmm1
+[ ]*[a-f0-9]+:[ ]*62 f3 6f 48 8f c9 00[ ]+top4mxbssps \$0x0,%zmm2,%zmm1,%tmm1
+[ ]*[a-f0-9]+:[ ]*62 f2 6e 48 5c c1[ ]+top2bf16ps %zmm2,%zmm1,%tmm0
+[ ]*[a-f0-9]+:[ ]*62 f2 6f 48 5e c1[ ]+top4bssd %zmm2,%zmm1,%tmm0
+[ ]*[a-f0-9]+:[ ]*62 f2 6e 48 5e c1[ ]+top4bsud %zmm2,%zmm1,%tmm0
+[ ]*[a-f0-9]+:[ ]*62 f2 6d 48 5e c1[ ]+top4busd %zmm2,%zmm1,%tmm0
+[ ]*[a-f0-9]+:[ ]*62 f2 6c 48 5e c1[ ]+top4buud %zmm2,%zmm1,%tmm0
diff --git a/gas/testsuite/gas/i386/x86-64-ace_v1.s b/gas/testsuite/gas/i386/x86-64-ace_v1.s
index 10fbc8d9adf..006b461b164 100644
--- a/gas/testsuite/gas/i386/x86-64-ace_v1.s
+++ b/gas/testsuite/gas/i386/x86-64-ace_v1.s
@@ -9,6 +9,10 @@ start:
tilemovrow %ebx, %tmm2, %zmm1
tilemovrow $8, %tmm2, %zmm1
+ tilemovrow %ebx, %zmm2, %tmm1
+ tilemovrow $8, %zmm2, %tmm1
+ tilemovcol %ebx, %zmm2, %tmm1
+ tilemovcol $8, %zmm2, %tmm1
tcvtrowd2ps %edx, %tmm5, %zmm30
tcvtrowd2ps $8, %tmm5, %zmm30
@@ -19,8 +23,32 @@ start:
tcvtrowps2ph\p %edx, %tmm5, %zmm30
tcvtrowps2ph\p $8, %tmm5, %zmm30
+
+ bsrmov\p %zmm10, %bsr0
+ bsrmov\p 8128(%rcx), %bsr0
+
+ bsrmov\p %bsr0, %zmm4
+ bsrmov\p %bsr0, -8192(%rcx)
.endr
+ bsrinit %bsr0
+ bsrmovf %zmm3, %zmm1, %bsr0
+ bsrmovf 8128(%rcx), %zmm1, %bsr0
+
+ top4mxbf8ps $0, %zmm2, %zmm1, %tmm1
+ top4mxbhf8ps $0, %zmm2, %zmm1, %tmm1
+ top4mxhbf8ps $0, %zmm2, %zmm1, %tmm1
+ top4mxhf8ps $0, %zmm2, %zmm1, %tmm1
+
+ top4mxbssps $0, %zmm2, %zmm1, %tmm1
+
+ top2bf16ps %zmm2, %zmm1, %tmm0
+
+ top4bssd %zmm2, %zmm1, %tmm0
+ top4bsud %zmm2, %zmm1, %tmm0
+ top4busd %zmm2, %zmm1, %tmm0
+ top4buud %zmm2, %zmm1, %tmm0
+
_intel:
.intel_syntax noprefix
@@ -31,6 +59,10 @@ _intel:
tilemovrow zmm1, tmm2, ebx
tilemovrow zmm1, tmm2, 8
+ tilemovrow tmm1, zmm2, ebx
+ tilemovrow tmm1, zmm2, 8
+ tilemovcol tmm1, zmm2, ebx
+ tilemovcol tmm1, zmm2, 8
tcvtrowd2ps zmm30, tmm5, edx
tcvtrowd2ps zmm30, tmm5, 8
@@ -41,4 +73,28 @@ _intel:
tcvtrowps2ph\p zmm30, tmm5, edx
tcvtrowps2ph\p zmm30, tmm5, 8
+
+ bsrmov\p bsr0, zmm10
+ bsrmov\p bsr0, ZMMWORD PTR [rcx+8128]
+
+ bsrmov\p zmm4, bsr0
+ bsrmov\p ZMMWORD PTR [rcx-8192], bsr0
.endr
+
+ bsrinit bsr0
+ bsrmovf bsr0, zmm1, zmm3
+ bsrmovf bsr0, zmm1, ZMMWORD PTR [rcx+8128]
+
+ top4mxbf8ps tmm1, zmm1, zmm2, 0
+ top4mxbhf8ps tmm1, zmm1, zmm2, 0
+ top4mxhbf8ps tmm1, zmm1, zmm2, 0
+ top4mxhf8ps tmm1, zmm1, zmm2, 0
+
+ top4mxbssps tmm1, zmm1, zmm2, 0
+
+ top2bf16ps tmm0, zmm1, zmm2
+
+ top4bssd tmm0, zmm1, zmm2
+ top4bsud tmm0, zmm1, zmm2
+ top4busd tmm0, zmm1, zmm2
+ top4buud tmm0, zmm1, zmm2
diff --git a/opcodes/i386-dis-evex-len.h b/opcodes/i386-dis-evex-len.h
index 370710915de..b0449c28a75 100644
--- a/opcodes/i386-dis-evex-len.h
+++ b/opcodes/i386-dis-evex-len.h
@@ -51,6 +51,27 @@ static const struct dis386 evex_len_table[][3] = {
{ PREFIX_TABLE (PREFIX_EVEX_0F384A_X86_64_W_0_L_2) },
},
+ /* EVEX_LEN_0F384A_X86_64_W_1 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_EVEX_0F384A_X86_64_W_1_L_2) },
+ },
+
+ /* EVEX_LEN_0F384B_X86_64_W_0 */
+ {
+ { X86_64_EVEX_PFX_TABLE (PREFIX_VEX_0F384B_X86_64_L_0_W_0) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ },
+
+ /* EVEX_LEN_0F384B_X86_64_W_1 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_EVEX_0F384B_X86_64_W_1_L_2) },
+ },
+
/* EVEX_LEN_0F385A */
{
{ Bad_Opcode },
@@ -65,7 +86,21 @@ static const struct dis386 evex_len_table[][3] = {
{ VEX_W_TABLE (EVEX_W_0F385B_L_2) },
},
- /* EVEX_LEN_0F386D_X86_64_W_0_M_1 */
+ /* EVEX_LEN_0F385C_X86_64_W_0 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_EVEX_0F385C_X86_64_W_0_L_2) },
+ },
+
+ /* EVEX_LEN_0F385E_X86_64_W_0 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_EVEX_0F385E_X86_64_W_0_L_2) },
+ },
+
+ /* EVEX_LEN_0F386D_X86_64_W_0 */
{
{ Bad_Opcode },
{ Bad_Opcode },
@@ -107,6 +142,13 @@ static const struct dis386 evex_len_table[][3] = {
{ PREFIX_TABLE (PREFIX_EVEX_0F3A07_X86_64_W_0_L_2) },
},
+ /* EVEX_LEN_0F3A07_X86_64_W_1 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_EVEX_0F3A07_X86_64_W_1_L_2) },
+ },
+
/* EVEX_LEN_0F3A18 */
{
{ Bad_Opcode },
@@ -142,6 +184,13 @@ static const struct dis386 evex_len_table[][3] = {
{ VEX_W_TABLE (EVEX_W_0F3A23_L_n) },
},
+ /* EVEX_LEN_0F3A2F_X86_64_W_1 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_EVEX_0F3A2F_X86_64_W_1_L_2) },
+ },
+
/* EVEX_LEN_0F3A38 */
{
{ Bad_Opcode },
@@ -184,6 +233,20 @@ static const struct dis386 evex_len_table[][3] = {
{ PREFIX_TABLE (PREFIX_EVEX_0F3A77_X86_64_W_0_L_2) },
},
+ /* EVEX_LEN_0F3A8D_X86_64_W_0 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_EVEX_0F3A8D_X86_64_W_0_L_2) },
+ },
+
+ /* EVEX_LEN_0F3A8F_X86_64_W_0 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_EVEX_0F3A8F_X86_64_W_0_L_2) },
+ },
+
/* EVEX_LEN_MAP5_6E */
{
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_6E_L_0) },
@@ -207,4 +270,16 @@ static const struct dis386 evex_len_table[][3] = {
{ "vbmacxor16x16x16", { XM, Vex, EXx }, NO_PREFIX },
{ "vbmacxor16x16x16", { XM, Vex, EXx }, NO_PREFIX },
},
+ /* EVEX_LEN_MAP6_95_X86_64_W_0 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_EVEX_MAP6_95_X86_64_W_0_L_2) },
+ },
+ /* EVEX_LEN_MAP6_95_X86_64_W_1 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_EVEX_MAP6_95_X86_64_W_1_L_2) },
+ },
};
diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h
index fd2e29432ab..3db0b233155 100644
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -254,6 +254,18 @@
{ "tcvtrowd2ps", { XM, Rtmm, VexGd }, 0 },
{ "tilemovrow", { XM, Rtmm, VexGd }, 0 },
},
+ /* PREFIX_EVEX_0F384A_X86_64_W_1_L_2 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "tilemovrow", { TMM, Ux, VexGd }, 0 },
+ },
+ /* PREFIX_EVEX_0F384B_X86_64_W_1_L_2 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "tilemovcol", { TMM, Ux, VexGd }, 0 },
+ },
/* PREFIX_EVEX_0F3852 */
{
{ "vdpphp%XS", { XM, Vex, EXx }, 0 },
@@ -268,6 +280,18 @@
{ VEX_W_TABLE (VEX_W_0F3853) },
{ "vp4dpws%XSds", { XM, Vex, Mxmm }, 0 },
},
+ /* PREFIX_EVEX_0F385C_X86_64_W_0_L_2 */
+ {
+ { Bad_Opcode },
+ { "top2bf16ps", { TMM, Ux, Vex }, 0 },
+ },
+ /* PREFIX_EVEX_0F385E_X86_64_W_0_L_2 */
+ {
+ { "top4buud", { TMM, Ux, Vex }, 0 },
+ { "top4bsud", { TMM, Ux, Vex }, 0 },
+ { "top4busd", { TMM, Ux, Vex }, 0 },
+ { "top4bssd", { TMM, Ux, Vex }, 0 },
+ },
/* PREFIX_EVEX_0F3868 */
{
{ Bad_Opcode },
@@ -331,6 +355,12 @@
{ "tilemovrow", { XM, Rtmm, Ib }, 0 },
{ "tcvtrowps2bf16h", { XM, Rtmm, Ib }, 0 },
},
+ /* PREFIX_EVEX_0F3A07_X86_64_W_1_L_2 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "tilemovrow", { TMM, Ux, Ib }, 0 },
+ },
/* PREFIX_EVEX_0F3A08 */
{
{ "vrndscalep%XH", { XM, EXxh, EXxEVexS, Ib }, 0 },
@@ -357,6 +387,12 @@
{ Bad_Opcode },
{ "vgetmants%XW", { XMScalar, VexScalar, EXdq, EXxEVexS, Ib }, 0 },
},
+ /* PREFIX_EVEX_0F3A2F_X86_64_W_1_L_2 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "tilemovcol", { TMM, Ux, Ib }, 0 },
+ },
/* PREFIX_EVEX_0F3A42_W_0 */
{
{ Bad_Opcode },
@@ -409,6 +445,20 @@
{ Bad_Opcode },
{ "tcvtrowps2phl", { XM, Rtmm, Ib }, 0 },
},
+ /* PREFIX_EVEX_0F3A8D_X86_64_W_0_L_2 */
+ {
+ { "top4mxbf8ps", { TMM, Ux, Vex, Ib }, 0 },
+ { "top4mxhbf8ps", { TMM, Ux, Vex, Ib }, 0 },
+ { "top4mxhf8ps", { TMM, Ux, Vex, Ib }, 0 },
+ { "top4mxbhf8ps", { TMM, Ux, Vex, Ib }, 0 },
+ },
+ /* PREFIX_EVEX_0F3A8F_X86_64_W_0_L_2 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "top4mxbssps", { TMM, Ux, Vex, Ib }, 0 },
+ },
/* PREFIX_EVEX_0F3AC2 */
{
{ "vcmpp%XH", { MaskG, Vex, EXxh, EXxEVexS, CMP }, 0 },
@@ -833,6 +883,20 @@
{ Bad_Opcode },
{ "vfnmsub231p%XH", { XM, Vex, EXxh, EXxEVexR }, 0 },
},
+ /* PREFIX_EVEX_MAP6_95_X86_64_W_0_L_2 */
+ {
+ { Bad_Opcode },
+ { "bsrmovl", { EXEvexXNoBcst, BSR }, 0 },
+ { Bad_Opcode },
+ { "bsrmovh", { EXEvexXNoBcst, BSR }, 0 },
+ },
+ /* PREFIX_EVEX_MAP6_95_X86_64_W_1_L_2 */
+ {
+ { "bsrmovf", { BSR, Vex, EXEvexXNoBcst }, 0 },
+ { "bsrmovl", { BSR, EXEvexXNoBcst }, 0 },
+ { Bad_Opcode },
+ { "bsrmovh", { BSR, EXEvexXNoBcst }, 0 },
+ },
/* PREFIX_EVEX_MAP6_D6 */
{
{ Bad_Opcode },
diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h
index f0f00e44143..8353a39fa3e 100644
--- a/opcodes/i386-dis-evex-w.h
+++ b/opcodes/i386-dis-evex-w.h
@@ -353,6 +353,12 @@
/* EVEX_W_0F384A_X86_64 */
{
{ EVEX_LEN_TABLE (EVEX_LEN_0F384A_X86_64_W_0) },
+ { EVEX_LEN_TABLE (EVEX_LEN_0F384A_X86_64_W_1) },
+ },
+ /* EVEX_W_0F384B_X86_64 */
+ {
+ { EVEX_LEN_TABLE (EVEX_LEN_0F384B_X86_64_W_0) },
+ { EVEX_LEN_TABLE (EVEX_LEN_0F384B_X86_64_W_1) },
},
/* EVEX_W_0F3859 */
{
@@ -369,6 +375,14 @@
{ "vbroadcasti32x8", { XM, Mymm }, PREFIX_DATA },
{ "vbroadcasti64x4", { XM, Mymm }, PREFIX_DATA },
},
+ /* EVEX_W_0F385C_X86_64 */
+ {
+ { EVEX_LEN_TABLE (EVEX_LEN_0F385C_X86_64_W_0) },
+ },
+ /* EVEX_W_0F385E_X86_64 */
+ {
+ { EVEX_LEN_TABLE (EVEX_LEN_0F385E_X86_64_W_0) },
+ },
/* EVEX_W_0F386D_X86_64 */
{
{ EVEX_LEN_TABLE (EVEX_LEN_0F386D_X86_64_W_0) },
@@ -399,6 +413,7 @@
/* EVEX_W_0F3A07_X86_64 */
{
{ EVEX_LEN_TABLE (EVEX_LEN_0F3A07_X86_64_W_0) },
+ { EVEX_LEN_TABLE (EVEX_LEN_0F3A07_X86_64_W_1) },
},
/* EVEX_W_0F3A18_L_n */
{
@@ -429,6 +444,11 @@
{ "vshuff32x4", { XM, Vex, EXx, Ib }, PREFIX_DATA },
{ "vshuff64x2", { XM, Vex, EXx, Ib }, PREFIX_DATA },
},
+ /* EVEX_W_0F3A2F_X86_64 */
+ {
+ { Bad_Opcode },
+ { EVEX_LEN_TABLE (EVEX_LEN_0F3A2F_X86_64_W_1) },
+ },
/* EVEX_W_0F3A38_L_n */
{
{ "vinserti32x4", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
@@ -476,6 +496,14 @@
{
{ EVEX_LEN_TABLE (EVEX_LEN_0F3A77_X86_64_W_0) },
},
+ /* EVEX_W_0F3A8D_X86_64 */
+ {
+ { EVEX_LEN_TABLE (EVEX_LEN_0F3A8D_X86_64_W_0) },
+ },
+ /* EVEX_W_0F3A8F_X86_64 */
+ {
+ { EVEX_LEN_TABLE (EVEX_LEN_0F3A8F_X86_64_W_0) },
+ },
/* EVEX_W_MAP4_8F_R_0 */
{
{ "pop2", { { PUSH2_POP2_Fixup, q_mode}, Eq }, NO_PREFIX },
@@ -570,4 +598,9 @@
{
{ "vbitrevb", { XM, EXx }, NO_PREFIX },
{ Bad_Opcode }
- }
+ },
+ /* EVEX_W_MAP6_95_X86_64 */
+ {
+ { EVEX_LEN_TABLE (EVEX_LEN_MAP6_95_X86_64_W_0) },
+ { EVEX_LEN_TABLE (EVEX_LEN_MAP6_95_X86_64_W_1) },
+ },
diff --git a/opcodes/i386-dis-evex-x86-64.h b/opcodes/i386-dis-evex-x86-64.h
index 93acb0ba18d..0011a91d470 100644
--- a/opcodes/i386-dis-evex-x86-64.h
+++ b/opcodes/i386-dis-evex-x86-64.h
@@ -3,6 +3,21 @@
{ Bad_Opcode },
{ VEX_W_TABLE (EVEX_W_0F384A_X86_64) },
},
+ /* X86_64_EVEX_0F384B */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (EVEX_W_0F384B_X86_64) },
+ },
+ /* X86_64_EVEX_0F385C */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (EVEX_W_0F385C_X86_64) },
+ },
+ /* X86_64_EVEX_0F385E */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (EVEX_W_0F385E_X86_64) },
+ },
/* X86_64_EVEX_0F386D */
{
{ Bad_Opcode },
@@ -13,13 +28,33 @@
{ Bad_Opcode },
{ VEX_W_TABLE (EVEX_W_0F3A07_X86_64) },
},
+ /* X86_64_EVEX_0F3A2F */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (EVEX_W_0F3A2F_X86_64) },
+ },
/* X86_64_EVEX_0F3A77 */
{
{ Bad_Opcode },
{ VEX_W_TABLE (EVEX_W_0F3A77_X86_64) },
},
+ /* X86_64_EVEX_0F3A8D */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (EVEX_W_0F3A8D_X86_64) },
+ },
+ /* X86_64_EVEX_0F3A8F */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (EVEX_W_0F3A8F_X86_64) },
+ },
/* X86_64_EVEX_MAP5_6F */
{
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_EVEX_MAP5_6F_X86_64) },
},
+ /* X86_64_EVEX_MAP6_95 */
+ {
+ { Bad_Opcode },
+ { VEX_W_TABLE (EVEX_W_MAP6_95_X86_64) },
+ },
diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
index fe515a01932..00a6fdc9460 100644
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -377,7 +377,7 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
{ X86_64_EVEX_MEM_W_TABLE (VEX_W_0F3849_X86_64_L_0) },
{ X86_64_TABLE (X86_64_EVEX_0F384A) },
- { X86_64_EVEX_MEM_W_TABLE (VEX_W_0F384B_X86_64_L_0) },
+ { X86_64_TABLE (X86_64_EVEX_0F384B) },
{ "vrcp14p%XW", { XM, EXx }, PREFIX_DATA },
{ "vrcp14s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
{ "vrsqrt14p%XW", { XM, EXx }, 0 },
@@ -396,9 +396,9 @@ static const struct dis386 evex_table[][256] = {
{ VEX_W_TABLE (EVEX_W_0F3859) },
{ EVEX_LEN_TABLE (EVEX_LEN_0F385A) },
{ EVEX_LEN_TABLE (EVEX_LEN_0F385B) },
+ { X86_64_TABLE (X86_64_EVEX_0F385C) },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { X86_64_TABLE (X86_64_EVEX_0F385E) },
{ Bad_Opcode },
/* 60 */
{ Bad_Opcode },
@@ -636,7 +636,7 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
+ { X86_64_TABLE (X86_64_EVEX_0F3A2F) },
/* 30 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -742,9 +742,9 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ { X86_64_TABLE (X86_64_EVEX_0F3A8D) },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { X86_64_TABLE (X86_64_EVEX_0F3A8F) },
/* 90 */
{ Bad_Opcode },
{ Bad_Opcode },
@@ -1624,7 +1624,7 @@ static const struct dis386 evex_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
+ { X86_64_TABLE (X86_64_EVEX_MAP6_95) },
{ "vfmaddsub132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
{ "vfmsubadd132p%XH", { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
/* 98 */
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index db957d1638f..bdb3a7f4566 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -513,6 +513,7 @@ fetch_error (const instr_info *ins)
#define RMBH { OP_REG, bh_reg }
#define RMAX { OP_REG, ax_reg }
#define RMDX { OP_REG, dx_reg }
+#define BSR { OP_G, bsr_mode }
#define eAX { OP_IMREG, eAX_reg }
#define AL { OP_IMREG, al_reg }
@@ -723,6 +724,8 @@ enum
ymmq_mode,
/* TMM operand */
tmm_mode,
+ /* Block scale register operand. */
+ bsr_mode,
/* d_mode in 32bit, q_mode in 64bit mode. */
m_mode,
/* pair of v_mode operands */
@@ -972,6 +975,7 @@ enum
MOD_0F38F8,
MOD_VEX_0F3849_X86_64_L_0_W_0,
+ MOD_VEX_0F3849_X86_64_L_0_W_1,
MOD_EVEX_MAP4_60,
MOD_EVEX_MAP4_61,
@@ -996,6 +1000,7 @@ enum
RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0,
RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3,
+ RM_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3,
};
enum
@@ -1143,6 +1148,7 @@ enum
PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0,
PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1,
PREFIX_VEX_0F384A_X86_64_W_0_L_0,
+ PREFIX_VEX_0F3849_X86_64_L_0_W_1_M_1,
PREFIX_VEX_0F384B_X86_64_L_0_W_0,
PREFIX_VEX_0F3850_W_0,
PREFIX_VEX_0F3851_W_0,
@@ -1215,8 +1221,12 @@ enum
PREFIX_EVEX_0F383A,
PREFIX_EVEX_0F3841_W_0,
PREFIX_EVEX_0F384A_X86_64_W_0_L_2,
+ PREFIX_EVEX_0F384A_X86_64_W_1_L_2,
+ PREFIX_EVEX_0F384B_X86_64_W_1_L_2,
PREFIX_EVEX_0F3852,
PREFIX_EVEX_0F3853,
+ PREFIX_EVEX_0F385C_X86_64_W_0_L_2,
+ PREFIX_EVEX_0F385E_X86_64_W_0_L_2,
PREFIX_EVEX_0F3868,
PREFIX_EVEX_0F386D_X86_64_W_0_L_2,
PREFIX_EVEX_0F3872,
@@ -1227,10 +1237,12 @@ enum
PREFIX_EVEX_0F38AB,
PREFIX_EVEX_0F3A07_X86_64_W_0_L_2,
+ PREFIX_EVEX_0F3A07_X86_64_W_1_L_2,
PREFIX_EVEX_0F3A08,
PREFIX_EVEX_0F3A0A,
PREFIX_EVEX_0F3A26,
PREFIX_EVEX_0F3A27,
+ PREFIX_EVEX_0F3A2F_X86_64_W_1_L_2,
PREFIX_EVEX_0F3A42_W_0,
PREFIX_EVEX_0F3A52,
PREFIX_EVEX_0F3A53,
@@ -1239,6 +1251,8 @@ enum
PREFIX_EVEX_0F3A66,
PREFIX_EVEX_0F3A67,
PREFIX_EVEX_0F3A77_X86_64_W_0_L_2,
+ PREFIX_EVEX_0F3A8D_X86_64_W_0_L_2,
+ PREFIX_EVEX_0F3A8F_X86_64_W_0_L_2,
PREFIX_EVEX_0F3AC2,
PREFIX_EVEX_MAP4_4x,
@@ -1312,6 +1326,8 @@ enum
PREFIX_EVEX_MAP6_BA,
PREFIX_EVEX_MAP6_BC,
PREFIX_EVEX_MAP6_BE,
+ PREFIX_EVEX_MAP6_95_X86_64_W_0_L_2,
+ PREFIX_EVEX_MAP6_95_X86_64_W_1_L_2,
PREFIX_EVEX_MAP6_D6,
PREFIX_EVEX_MAP6_D7,
};
@@ -1405,11 +1421,18 @@ enum
X86_64_VEX_MAP7_F8_L_0_W_0_R_0,
X86_64_EVEX_0F384A,
+ X86_64_EVEX_0F384B,
+ X86_64_EVEX_0F385C,
+ X86_64_EVEX_0F385E,
X86_64_EVEX_0F386D,
X86_64_EVEX_0F3A07,
+ X86_64_EVEX_0F3A2F,
X86_64_EVEX_0F3A77,
+ X86_64_EVEX_0F3A8D,
+ X86_64_EVEX_0F3A8F,
X86_64_EVEX_MAP5_6F,
+ X86_64_EVEX_MAP6_95,
};
enum
@@ -1605,30 +1628,41 @@ enum
EVEX_LEN_0F381B,
EVEX_LEN_0F3836,
EVEX_LEN_0F384A_X86_64_W_0,
+ EVEX_LEN_0F384A_X86_64_W_1,
+ EVEX_LEN_0F384B_X86_64_W_0,
+ EVEX_LEN_0F384B_X86_64_W_1,
EVEX_LEN_0F385A,
EVEX_LEN_0F385B,
+ EVEX_LEN_0F385C_X86_64_W_0,
+ EVEX_LEN_0F385E_X86_64_W_0,
EVEX_LEN_0F386D_X86_64_W_0,
EVEX_LEN_0F38C6,
EVEX_LEN_0F38C7,
EVEX_LEN_0F3A00,
EVEX_LEN_0F3A01,
EVEX_LEN_0F3A07_X86_64_W_0,
+ EVEX_LEN_0F3A07_X86_64_W_1,
EVEX_LEN_0F3A18,
EVEX_LEN_0F3A19,
EVEX_LEN_0F3A1A,
EVEX_LEN_0F3A1B,
EVEX_LEN_0F3A23,
+ EVEX_LEN_0F3A2F_X86_64_W_1,
EVEX_LEN_0F3A38,
EVEX_LEN_0F3A39,
EVEX_LEN_0F3A3A,
EVEX_LEN_0F3A3B,
EVEX_LEN_0F3A43,
EVEX_LEN_0F3A77_X86_64_W_0,
+ EVEX_LEN_0F3A8D_X86_64_W_0,
+ EVEX_LEN_0F3A8F_X86_64_W_0,
EVEX_LEN_MAP5_6E,
EVEX_LEN_MAP5_7E,
EVEX_LEN_MAP6_80_W_0,
EVEX_LEN_MAP6_80_W_1,
+ EVEX_LEN_MAP6_95_X86_64_W_0,
+ EVEX_LEN_MAP6_95_X86_64_W_1,
};
enum
@@ -1843,9 +1877,12 @@ enum
EVEX_W_0F383A_P_1,
EVEX_W_0F3841,
EVEX_W_0F384A_X86_64,
+ EVEX_W_0F384B_X86_64,
EVEX_W_0F3859,
EVEX_W_0F385A_L_n,
EVEX_W_0F385B_L_2,
+ EVEX_W_0F385C_X86_64,
+ EVEX_W_0F385E_X86_64,
EVEX_W_0F386D_X86_64,
EVEX_W_0F3870,
EVEX_W_0F3872_P_2,
@@ -1860,6 +1897,7 @@ enum
EVEX_W_0F3A1B_L_2,
EVEX_W_0F3A21,
EVEX_W_0F3A23_L_n,
+ EVEX_W_0F3A2F_X86_64,
EVEX_W_0F3A38_L_n,
EVEX_W_0F3A39_L_n,
EVEX_W_0F3A3A_L_2,
@@ -1870,6 +1908,8 @@ enum
EVEX_W_0F3A70,
EVEX_W_0F3A72,
EVEX_W_0F3A77_X86_64,
+ EVEX_W_0F3A8D_X86_64,
+ EVEX_W_0F3A8F_X86_64,
EVEX_W_MAP4_8F_R_0,
EVEX_W_MAP4_F8_P1_M_1,
@@ -1893,6 +1933,7 @@ enum
EVEX_W_MAP5_7E_P_1,
EVEX_W_MAP6_80,
EVEX_W_MAP6_81,
+ EVEX_W_MAP6_95_X86_64,
};
typedef bool (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
@@ -2719,6 +2760,10 @@ static const char att_names_tmm[][8] = {
"%tmm4", "%tmm5", "%tmm6", "%tmm7"
};
+static const char att_names_bsr[][8] = {
+ "%bsr0"
+};
+
static const char att_names_mask[][8] = {
"%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
};
@@ -4194,6 +4239,14 @@ static const struct dis386 prefix_table[][4] = {
{ "tileloaddrs", { TMM, MVexSIBMEM }, 0 },
},
+ /* PREFIX_VEX_0F3849_X86_64_L_0_W_1_M_1 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3) },
+ },
+
/* PREFIX_VEX_0F384B_X86_64_L_0_W_0 */
{
{ Bad_Opcode },
@@ -8137,6 +8190,7 @@ static const struct dis386 vex_w_table[][2] = {
{
/* VEX_W_0F3849_X86_64_L_0 */
{ MOD_TABLE (MOD_VEX_0F3849_X86_64_L_0_W_0) },
+ { MOD_TABLE (MOD_VEX_0F3849_X86_64_L_0_W_1) },
},
{
/* VEX_W_0F384A_X86_64 */
@@ -8713,6 +8767,11 @@ static const struct dis386 mod_table[][2] = {
{ PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) },
{ PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1) },
},
+ {
+ /* MOD_VEX_0F3849_X86_64_L_0_W_1 */
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_1_M_1) },
+ },
#include "i386-dis-evex-mod.h"
};
@@ -8823,6 +8882,10 @@ static const struct dis386 rm_table[][8] = {
/* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3 */
{ "tilezero", { TMM, Skip_MODRM }, 0 },
},
+ {
+ /* RM_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3 */
+ { "bsrinit", { BSR, Skip_MODRM }, 0 },
+ },
};
#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
@@ -12119,6 +12182,14 @@ print_register (instr_info *ins, unsigned int reg, unsigned int rexmask,
}
names = att_names_bnd;
break;
+ case bsr_mode:
+ if (reg)
+ {
+ oappend (ins, "(bad)");
+ return;
+ }
+ names = att_names_bsr;
+ break;
case indir_v_mode:
if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
{
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 0a7e3008065..67981b84dea 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -584,6 +584,7 @@ static const struct {
CLASS (RegSIMD),
CLASS (RegMask),
CLASS (RegBND),
+ CLASS (RegBSR),
};
#undef CLASS
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 1e3ffe8c487..907351ead34 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -904,6 +904,7 @@ enum operand_class
RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
RegMask, /* Vector Mask register */
RegBND, /* Bound register */
+ RegBSR, /* Block scale register */
};
/* Special operand instances. */
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 9540166f751..317c0b03f96 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -62,6 +62,8 @@
#define RegBND Class=RegBND
+#define RegBSR Class=RegBSR
+
#define Mmword Qword
#define Oword Xmmword
@@ -3255,8 +3257,6 @@ tdpfp16ps, 0xf25c, AMX_FP16, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegT
tdpb<tdpb>d, 0x<tdpb:pfx>5e, AMX_INT8, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
-<tdpb>
-
tileloadd, 0xf24b, APX_F(AMX_TILE), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
tileloaddt1, 0x664b, APX_F(AMX_TILE), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
tileloaddrs, 0xf24a, APX_F(AMX_MOVRS), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
@@ -3312,6 +3312,34 @@ tilemovrow, 0x6607, AMX_AVX512|ACE_V1, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Im
// AMX & ACE_V1 instructions end.
+// ACE_V1 instructions.
+
+bsrinit, 0xf249, ACE_V1, Modrm|Vex128|Space0F38|VexW1|NoSuf, { RegBSR }
+bsrmovf, 0x95, ACE_V1, Modrm|EVex512|Map6|VexW1|Src1VVVV|Disp8MemShift=6|NoSuf, { RegZMM|Unspecified|BaseIndex, RegZMM, RegBSR }
+bsrmovh, 0xf295, ACE_V1, D|Modrm|EVex512|Map6|VexW1|Disp8MemShift=6|NoSuf, { RegZMM|Unspecified|BaseIndex, RegBSR }
+bsrmovl, 0xf395, ACE_V1, D|Modrm|EVex512|Map6|VexW1|Disp8MemShift=6|NoSuf, { RegZMM|Unspecified|BaseIndex, RegBSR }
+
+tilemovcol, 0x662f, ACE_V1, Modrm|EVex512|Space0F3A|VexW1|NoSuf, { Imm8, RegZMM, RegTMM }
+tilemovcol, 0x664b, ACE_V1, Modrm|EVex512|Space0F38|VexW1|Src2VVVV|NoSuf, { Reg32, RegZMM, RegTMM }
+tilemovrow, 0x6607, ACE_V1, Modrm|EVex512|Space0F3A|VexW1|NoSuf, { Imm8, RegZMM, RegTMM }
+tilemovrow, 0x664a, ACE_V1, Modrm|EVex512|Space0F38|VexW1|Src2VVVV|NoSuf, { Reg32, RegZMM, RegTMM }
+
+top2bf16ps, 0xf35c, ACE_V1, Modrm|EVex512|Space0F38|VexW0|Src2VVVV|NoSuf, { RegZMM, RegZMM, RegTMM }
+
+top4b<tdpb>d, 0x<tdpb:pfx>5e, ACE_V1, Modrm|EVex512|Space0F38|VexW0|Src2VVVV|NoSuf, { RegZMM, RegZMM, RegTMM }
+
+<tdpb>
+
+<top4mx8:pfx, bf:, bhf:f2, hbf:f3, hf:66>
+
+top4mx<top4mx8>8ps, 0x<top4mx8:pfx>8d, ACE_V1, Modrm|EVex512|Space0F3A|VexW0|Src2VVVV|NoSuf, { Imm8, RegZMM, RegZMM, RegTMM }
+
+<top4mx8>
+
+top4mxbssps, 0xf28f, ACE_V1, Modrm|EVex512|Space0F3A|VexW0|Src2VVVV|NoSuf, { Imm8, RegZMM, RegZMM, RegTMM }
+
+// ACE_V1 instructions end.
+
// KEYLOCKER instructions.
loadiwkey, 0xf30f38dc, KL, Load|Modrm|NoSuf, { RegXMM, RegXMM }
diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl
index 3a4fa885177..f68dbbf8067 100644
--- a/opcodes/i386-reg.tbl
+++ b/opcodes/i386-reg.tbl
@@ -353,6 +353,8 @@ tmm4, Class=RegSIMD|Tmmword, 0, 4, Dw2Inval, Dw2Inval
tmm5, Class=RegSIMD|Tmmword, 0, 5, Dw2Inval, Dw2Inval
tmm6, Class=RegSIMD|Tmmword, 0, 6, Dw2Inval, Dw2Inval
tmm7, Class=RegSIMD|Tmmword, 0, 7, Dw2Inval, Dw2Inval
+// Block scale register for ACE V1
+bsr0, Class=RegBSR, 0, 0, Dw2Inval, Dw2Inval
// Bound registers for MPX
bnd0, Class=RegBND, 0, 0, Dw2Inval, 126
bnd1, Class=RegBND, 0, 1, Dw2Inval, 127
--
2.34.1
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