[PATCH] RISC-V: Support Zvabd version 0.9
Bohan Lei
garthlei@linux.alibaba.com
Wed Sep 9 08:24:33 GMT 2026
Unfortunately Zvabd was not as frozen as we had expected.
The ARC updated the instruction variants and encodings of Zvabd
(https://github.com/riscv/riscv-isa-manual/pull/3279), and the latest
approved version is version 0.9
(https://github.com/riscv/integer-vector-absolute-difference/releases/tag/v0.9).
This commit updates support for Zvabd to v0.9.
bfd/ChangeLog:
* elfxx-riscv.c: Change Zvabd version to 0.9.
gas/ChangeLog:
* NEWS: Update.
* testsuite/gas/riscv/march-help.l: Update testcase.
* testsuite/gas/riscv/zvabd.d: Ditto.
* testsuite/gas/riscv/zvabd.s: Ditto.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VABS_V): Remove.
(MASK_VABS_V): Ditto.
(MATCH_VABD_VV): Use new encoding.
(MATCH_VABDU_VV): Ditto.
(MATCH_VABD_VX): Ditto.
(MASK_VABD_VX): Ditto.
(MATCH_VWABDA_VV): Ditto.
(MATCH_VABDU_VX): Ditto.
(MASK_VABDU_VX): Ditto.
(MATCH_VWABDAU_VV): Ditto.
(MATCH_VWABDA_VX): Ditto.
(MASK_VWABDA_VX): Ditto.
(MATCH_VWABDAU_VX): Ditto.
(MASK_VWABDAU_VX): Ditto.
opcodes/ChangeLog:
* riscv-opc.c: Support new encodings and variants of Zvabd
instructions.
---
bfd/elfxx-riscv.c | 2 +-
gas/NEWS | 2 ++
gas/testsuite/gas/riscv/march-help.l | 2 +-
gas/testsuite/gas/riscv/zvabd.d | 14 +++++++++-----
gas/testsuite/gas/riscv/zvabd.s | 4 ++++
include/opcode/riscv-opc.h | 18 ++++++++++++------
opcodes/riscv-opc.c | 6 +++++-
7 files changed, 34 insertions(+), 14 deletions(-)
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 72ce77e4fbb..b3fd32adb06 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1542,7 +1542,7 @@ static const struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zve64x", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zve64f", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
- {"zvabd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvabd", ISA_SPEC_CLASS_DRAFT, 0, 9, 0 },
{"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvfbdota32f", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
diff --git a/gas/NEWS b/gas/NEWS
index 8b07d86daa3..0d3bdf924e7 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -5,6 +5,8 @@
* The avr target supports .gnu_attribute 4 (Tag_GNU_AVR_VTABLE_AS).
For details, see https://sourceware.org/PR34305
+* Add support for new variants and encodings of RISC-V Zvabd extension v0.9.
+
Changes in 2.47:
* New command line option --reloc-section-sym=[all|internal|none]
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 4ca7038c66c..17e204b213a 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -69,7 +69,7 @@ All available -march extensions for RISC-V:
zve64x 1.0
zve64f 1.0
zve64d 1.0
- zvabd 1.0
+ zvabd 0.9
zvbb 1.0
zvbc 1.0
zvfbdota32f 1.0
diff --git a/gas/testsuite/gas/riscv/zvabd.d b/gas/testsuite/gas/riscv/zvabd.d
index 8e5f1197a78..c336999ca24 100644
--- a/gas/testsuite/gas/riscv/zvabd.d
+++ b/gas/testsuite/gas/riscv/zvabd.d
@@ -6,8 +6,12 @@
Disassembly of section .text:
0+000 <target>:
-[ ]+[0-9a-f]+:[ ]+4a282257[ ]+vabs.v[ ]+v4,v2
-[ ]+[0-9a-f]+:[ ]+4620a257[ ]+vabd.vv[ ]+v4,v2,v1
-[ ]+[0-9a-f]+:[ ]+4e20a257[ ]+vabdu.vv[ ]+v4,v2,v1
-[ ]+[0-9a-f]+:[ ]+5620a257[ ]+vwabda.vv[ ]+v4,v2,v1
-[ ]+[0-9a-f]+:[ ]+5a20a257[ ]+vwabdau.vv[ ]+v4,v2,v1
+[ ]+[0-9a-f]+:[ ]+56206257[ ]+vabs.v[ ]+v4,v2
+[ ]+[0-9a-f]+:[ ]+5620a257[ ]+vabd.vv[ ]+v4,v2,v1
+[ ]+[0-9a-f]+:[ ]+56256257[ ]+vabd.vx[ ]+v4,v2,a0
+[ ]+[0-9a-f]+:[ ]+5a20a257[ ]+vabdu.vv[ ]+v4,v2,v1
+[ ]+[0-9a-f]+:[ ]+5a256257[ ]+vabdu.vx[ ]+v4,v2,a0
+[ ]+[0-9a-f]+:[ ]+f6208257[ ]+vwabda.vv[ ]+v4,v2,v1
+[ ]+[0-9a-f]+:[ ]+f6254257[ ]+vwabda.vx[ ]+v4,v2,a0
+[ ]+[0-9a-f]+:[ ]+fa208257[ ]+vwabdau.vv[ ]+v4,v2,v1
+[ ]+[0-9a-f]+:[ ]+fa254257[ ]+vwabdau.vx[ ]+v4,v2,a0
diff --git a/gas/testsuite/gas/riscv/zvabd.s b/gas/testsuite/gas/riscv/zvabd.s
index 4a930702e23..296937b6f70 100644
--- a/gas/testsuite/gas/riscv/zvabd.s
+++ b/gas/testsuite/gas/riscv/zvabd.s
@@ -1,6 +1,10 @@
target:
vabs.v v4, v2
vabd.vv v4, v2, v1
+ vabd.vx v4, v2, a0
vabdu.vv v4, v2, v1
+ vabdu.vx v4, v2, a0
vwabda.vv v4, v2, v1
+ vwabda.vx v4, v2, a0
vwabdau.vv v4, v2, v1
+ vwabdau.vx v4, v2, a0
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index da3f51ac2c1..a3d817e1c1a 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2276,16 +2276,22 @@
#define MATCH_VSM3ME_VV 0x82002077
#define MASK_VSM3ME_VV 0xfe00707f
/* Zvabd instructions. */
-#define MATCH_VABS_V 0x48082057
-#define MASK_VABS_V 0xfc0ff07f
-#define MATCH_VABD_VV 0x44002057
+#define MATCH_VABD_VV 0x54002057
#define MASK_VABD_VV 0xfc00707f
-#define MATCH_VABDU_VV 0x4c002057
+#define MATCH_VABD_VX 0x54006057
+#define MASK_VABD_VX 0xfc00707f
+#define MATCH_VABDU_VV 0x58002057
#define MASK_VABDU_VV 0xfc00707f
-#define MATCH_VWABDA_VV 0x54002057
+#define MATCH_VABDU_VX 0x58006057
+#define MASK_VABDU_VX 0xfc00707f
+#define MATCH_VWABDA_VV 0xf4000057
#define MASK_VWABDA_VV 0xfc00707f
-#define MATCH_VWABDAU_VV 0x58002057
+#define MATCH_VWABDA_VX 0xf4004057
+#define MASK_VWABDA_VX 0xfc00707f
+#define MATCH_VWABDAU_VV 0xf8000057
#define MASK_VWABDAU_VV 0xfc00707f
+#define MATCH_VWABDAU_VX 0xf8004057
+#define MASK_VWABDAU_VX 0xfc00707f
/* Zcb instructions. */
#define MATCH_C_LBU 0x8000
#define MASK_C_LBU 0xfc03
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 63a15e505f3..7c75b6a0b73 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2242,11 +2242,15 @@ const struct riscv_opcode riscv_opcodes[] =
{"vsm3me.vv", 0, INSN_CLASS_ZVKSH, "Vd,Vt,Vs", MATCH_VSM3ME_VV, MASK_VSM3ME_VV, match_opcode, 0},
/* Zvabd instructions. */
-{"vabs.v", 0, INSN_CLASS_ZVABD, "Vd,VtVm", MATCH_VABS_V, MASK_VABS_V, match_opcode, 0},
+{"vabs.v", 0, INSN_CLASS_ZVABD, "Vd,VtVm", MATCH_VABD_VX, MASK_VABD_VX | MASK_RS1, match_opcode, INSN_ALIAS},
{"vabd.vv", 0, INSN_CLASS_ZVABD, "Vd,Vt,VsVm", MATCH_VABD_VV, MASK_VABD_VV, match_opcode, 0},
+{"vabd.vx", 0, INSN_CLASS_ZVABD, "Vd,Vt,sVm", MATCH_VABD_VX, MASK_VABD_VX, match_opcode, 0},
{"vabdu.vv", 0, INSN_CLASS_ZVABD, "Vd,Vt,VsVm", MATCH_VABDU_VV, MASK_VABDU_VV, match_opcode, 0},
+{"vabdu.vx", 0, INSN_CLASS_ZVABD, "Vd,Vt,sVm", MATCH_VABDU_VX, MASK_VABDU_VX, match_opcode, 0},
{"vwabda.vv", 0, INSN_CLASS_ZVABD, "Vd,Vt,VsVm", MATCH_VWABDA_VV, MASK_VWABDA_VV, match_opcode, 0},
+{"vwabda.vx", 0, INSN_CLASS_ZVABD, "Vd,Vt,sVm", MATCH_VWABDA_VX, MASK_VWABDA_VX, match_opcode, 0},
{"vwabdau.vv", 0, INSN_CLASS_ZVABD, "Vd,Vt,VsVm", MATCH_VWABDAU_VV, MASK_VWABDAU_VV, match_opcode, 0},
+{"vwabdau.vx", 0, INSN_CLASS_ZVABD, "Vd,Vt,sVm", MATCH_VWABDAU_VX, MASK_VWABDAU_VX, match_opcode, 0},
/* ZCB instructions. */
{"c.lbu", 0, INSN_CLASS_ZCB, "Ct,Wcb(Cs)", MATCH_C_LBU, MASK_C_LBU, match_opcode, INSN_DREF|INSN_1_BYTE },
--
2.47.1
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