[PATCH v2 2/2] x86: ACE_V1 support for ACE-specific instructions

Jiang, Haochen haochen.jiang@intel.com
Mon Sep 7 08:43:20 GMT 2026


> From: Rohan Shenoy <RohanRadhesh.Shenoy@amd.com>
> Sent: Saturday, September 5, 2026 3:49 PM
> diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
> index 414fd90f787..8a9961044fa 100644
> --- a/opcodes/i386-dis.c
> +++ b/opcodes/i386-dis.c
> @@ -3106,6 +3152,10 @@ static const struct dis386 reg_table[][8] = {
>    {
>      { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0) },
>    },
> +  /* REG_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3 */
> +  {
> +    { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3_R_0) },
> +  },
>    /* REG_VEX_0F38F3_L_0_P_0 */
>    {
>      { Bad_Opcode },
> @@ -8824,6 +8888,10 @@ static const struct dis386 rm_table[][8] = {
>      /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3 */
>      { "tilezero",	{ TMM, Skip_MODRM }, 0 },
>    },
> +  {
> +    /* RM_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3_R_0 */
> +    { "bsrinit",	{ BSR, Skip_MODRM }, 0 },
> +  },
>  };
> 
>  #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
> @@ -12129,6 +12197,14 @@ print_register (instr_info *ins, unsigned int reg,
> unsigned int rexmask,
>  	}
>        names = att_names_bnd;
>        break;
> +    case bsr_mode:
> +      if (reg)
> +	{
> +	  oappend (ins, "(bad)");
> +	  return;
> +	}
> +      names = att_names_bsr;
> +      break;

It is a redundant check after you pass REG table since both are prohibiting
non-zero values. And considering how easily it could be to use MODRM part
to use more register number after introducing more BSRs, we might should
remove the REG table pass. Changing one line in the future should be better.

Thx,
Haochen

>      case indir_v_mode:
>        if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
>  	{



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