[PATCH v2 1/2] x86: ACE_V1 support for AMX-shared instructions

[Jan Beulich]

On 07.09.2026 09:06, Jiang, Haochen wrote:
>> From: Rohan Shenoy <RohanRadhesh.Shenoy@amd.com>
>> Sent: Saturday, September 5, 2026 3:49 PM
>>
>> Enable ACE_V1 architecture, and reuse the pre-existing AMX-shared
>> instructions for tile management, row moves, and row converts under
>> ACE_V1, also allowing TMM register usage.
>>
>> Reject invalid EVEX.V' encoding for the shared instructions: V' must be
>> set when VVVV is unused or encodes an r32 register.
> 
> Although ACE documentation said that, it is extremely weird to do so.
> I believe it is yet another documentation mess up here. Using V' could
> let us easily get EGPR under APX, just like how we extend 16 vector
> registers to 32 vector registers. This makes the patch need an almost
> immediate re-do after co-operating with APX, probably leading to the
> drop for PREFIX_EVEX_V_ILLEGAL. It makes no sense to prohibit EGPR
> when there is APX, under the circumstance that APX will appear on
> DMR. It is a much earlier show-up than ACEv1. We should not take
> EGPR out from consideration when implementing ACE.
> 
> Even if we really end up with APX part out, which is not ideal, at least
> the invalid test is missing.

There's no question: Unless the ACE spec is changed to indicate that it
precludes APX (which would imo be insane), both features should operate
correctly together from the start. Imo the ACE spec would benefit from
being updated to cover APX aspects.

Jan