[PATCH v5 2/2] RISC-V: Add SpacemiT vendor extension xsmtvdotii
Jiawei
jiawei@iscas.ac.cn
Wed May 13 13:51:35 GMT 2026
> SpacemiT defines Intrinsic Matrix Extension (IME) specification [1].
> SpacemiT A100 implements version 1.0 of the SpacemiT Vector Dot Product
> II Extension (XsmtVdotII v1.0) [2], a subset of the full IME
> specification.
>
> [1]
> https://github.com/spacemit-com/riscv-ime-extension-spec/releases/download/v1.0/spacemit-ime-asciidoc.pdf
> [2]
> https://github.com/spacemit-com/docs-ai/blob/main/en/architecture/ime_extension.md
> ---
> bfd/elfxx-riscv.c | 11 ++
> gas/NEWS | 2 +-
> gas/config/tc-riscv.c | 102 ++++++++++++++++
> gas/doc/c-riscv.texi | 8 ++
> gas/testsuite/gas/riscv/march-help.l | 1 +
> gas/testsuite/gas/riscv/x-smt-vdot-fail.l | 64 +++++-----
> gas/testsuite/gas/riscv/x-smt-vdot-ii-fail.d | 3 +
> gas/testsuite/gas/riscv/x-smt-vdot-ii-fail.l | 99 ++++++++++++++++
> gas/testsuite/gas/riscv/x-smt-vdot-ii-fail.s | 118 +++++++++++++++++++
> gas/testsuite/gas/riscv/x-smt-vdot-ii.d | 69 +++++++++++
> gas/testsuite/gas/riscv/x-smt-vdot-ii.s | 73 ++++++++++++
> include/opcode/riscv-opc.h | 41 +++++++
> include/opcode/riscv.h | 7 ++
> opcodes/riscv-dis.c | 36 ++++++
> opcodes/riscv-opc.c | 67 ++++++++---
> 15 files changed, 652 insertions(+), 49 deletions(-)
> create mode 100644 gas/testsuite/gas/riscv/x-smt-vdot-ii-fail.d
> create mode 100644 gas/testsuite/gas/riscv/x-smt-vdot-ii-fail.l
> create mode 100644 gas/testsuite/gas/riscv/x-smt-vdot-ii-fail.s
> create mode 100644 gas/testsuite/gas/riscv/x-smt-vdot-ii.d
> create mode 100644 gas/testsuite/gas/riscv/x-smt-vdot-ii.s
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 5fdbc1698af..d54c4abafd7 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1230,6 +1230,7 @@ static const struct riscv_implicit_subset
> riscv_implicit_subsets[] =
> {"xtheadzvamo", "+zaamo", check_implicit_always},
>
> {"xsmtvdot", "+zve32x", check_implicit_always},
> + {"xsmtvdotii", "+xsmtvdot", check_implicit_always},
>
> {"v", "+zve64d,+zvl128b", check_implicit_always},
> {"zvfh", "+zvfhmin,+zfhmin", check_implicit_always},
> @@ -1647,6 +1648,7 @@ static const struct riscv_supported_ext
> riscv_supported_vendor_x_ext[] =
> {"xmipsexectl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"xmipslsp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {"xsmtvdot", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> + {"xsmtvdotii", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
> {NULL, 0, 0, 0, 0}
> };
>
> @@ -3067,6 +3069,11 @@ riscv_multi_subset_supports
> (riscv_parse_subset_t *rps,
> return riscv_subset_supports (rps, "xmipslsp");
> case INSN_CLASS_XSMTVDOT:
> return riscv_subset_supports (rps, "xsmtvdot");
> + case INSN_CLASS_XSMTVDOTII:
> + return riscv_subset_supports (rps, "xsmtvdotii");
> + case INSN_CLASS_XSMTVDOT_OR_XSMTVDOTII:
> + return (riscv_subset_supports (rps, "xsmtvdot")
> + || riscv_subset_supports (rps, "xsmtvdotii"));
> default:
> rps->error_handler
> (_("internal: unreachable INSN_CLASS_*"));
> @@ -3372,6 +3379,10 @@ riscv_multi_subset_supports_ext
> (riscv_parse_subset_t *rps,
> return "xsfvfnrclipxfqf";
> case INSN_CLASS_XSMTVDOT:
> return "xsmtvdot";
> + case INSN_CLASS_XSMTVDOTII:
> + return "xsmtvdotii";
> + case INSN_CLASS_XSMTVDOT_OR_XSMTVDOTII:
> + return _("xsmtvdot' or `xsmtvdotii");
> default:
> rps->error_handler
> (_("internal: unreachable INSN_CLASS_*"));
> diff --git a/gas/NEWS b/gas/NEWS
> index e47d55b05dc..2d86f0c1719 100644
> --- a/gas/NEWS
> +++ b/gas/NEWS
> @@ -1,7 +1,7 @@
> -*- text -*-
>
> * Add support for RISC-V vendor extensions:
> - SpacemiT: xsmtvdot v1.0.
> + SpacemiT: xsmtvdot v1.0, xsmtvdotii v1.0.
>
> Changes in 2.46:
>
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index 9c062ad3521..841f227e931 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -1771,6 +1771,8 @@ validate_riscv_insn (const struct riscv_opcode
> *opc, int length)
> }
> break;
> case 'p': /* Vendor-specific (SpacemiT) operands. */
> + size_t n;
> + size_t s;
> switch (*++oparg)
> {
> case 'V':
> @@ -1783,11 +1785,29 @@ validate_riscv_insn (const struct riscv_opcode
> *opc, int length)
> USE_BITS (OP_MASK_SPACEMIT_IME_VS1,
> OP_SH_SPACEMIT_IME_VS1);
> break;
> + case 'm':
> + USE_BITS (OP_MASK_SPACEMIT_IME_VMASK,
> + OP_SH_SPACEMIT_IME_VMASK);
> + break;
> default:
> goto unknown_validate_operand;
> }
> break;
> + case 'u': /* Integer immediate, 'XpuN@S' ...
> + N-bit unsigned immediate at bit S. */
> + n = strtol (oparg + 1, (char **)&oparg, 10);
> + if (*oparg != '@')
> + goto unknown_validate_operand;
> + s = strtol (oparg + 1, (char **)&oparg, 10);
> + oparg--;
> + USE_IMM (n, s);
> + break;
> + case 'n':
> + case 'b':
> + used_bits |= ENCODE_SPACEMIT_IME_UIMM2_SP (-1U);
> + break;
> case 'w':
> + case 'x':
> USE_BITS (OP_MASK_SPACEMIT_IME_WI, OP_SH_SPACEMIT_IME_WI);
> break;
> default:
> @@ -4311,6 +4331,8 @@ riscv_ip (char *str, struct riscv_cl_insn *ip,
> expressionS *imm_expr,
> break;
>
> case 'p': /* Vendor-specific (SpacemiT) operands. */
> + size_t n;
> + size_t s;
> switch (*++oparg)
> {
> case 'V':
> @@ -4340,10 +4362,66 @@ riscv_ip (char *str, struct riscv_cl_insn *ip,
> expressionS *imm_expr,
> }
> INSERT_OPERAND (SPACEMIT_IME_VS1, *ip, regno>>1);
> continue;
> + case 'm':
> + if (!reg_lookup (&asarg, RCLASS_VECR, ®no))
> + break;
> + if (regno >= 2)
> + {
> + error.msg
> + = _("illegal operands (mask must be v0/v1)");
> + error.missing_ext = NULL;
> + goto out;
> + }
> + INSERT_OPERAND (SPACEMIT_IME_VMASK, *ip, regno);
> + continue;
> default:
> goto unknown_riscv_ip_operand;
> }
> break;
> + case 'u': /* Integer immediate, 'XpuN@S' ...
> + N-bit unsigned immediate at bit S. */
> + n = strtol (oparg + 1, (char **)&oparg, 10);
> + if (*oparg != '@')
> + goto unknown_riscv_ip_operand;
> + s = strtol (oparg + 1, (char **)&oparg, 10);
> + oparg--;
> + my_getExpression (imm_expr, asarg, force_reloc);
> + check_absolute_expr (ip, imm_expr, false);
> + if (!VALIDATE_U_IMM (imm_expr->X_add_number, n))
> + as_bad (_("improper immediate value (%"PRIu64")"),
> + imm_expr->X_add_number);
> + INSERT_IMM (n, s, *ip, imm_expr->X_add_number);
> + imm_expr->X_op = O_absent;
> + asarg = expr_parse_end;
> + continue;
> + case 'n': /* Xpn: stride (0-1), paired with Xpx. */
> + my_getExpression (imm_expr, asarg, force_reloc);
> + check_absolute_expr (ip, imm_expr, false);
> + if (imm_expr->X_add_number < 0
> + || imm_expr->X_add_number >= 2)
> + break;
> + ip->insn_opcode
> + |= ENCODE_SPACEMIT_IME_UIMM2_SP
> + (imm_expr->X_add_number);
> + imm_expr->X_op = O_absent;
> + asarg = expr_parse_end;
> + continue;
> + case 'b': /* Xpb: stride (0-3), paired with Xpw. */
> + my_getExpression (imm_expr, asarg, force_reloc);
> + check_absolute_expr (ip, imm_expr, false);
> + if (imm_expr->X_add_number < 0
> + || imm_expr->X_add_number >= 4)
> + {
> + as_bad (_("bad value for stride field,"
> + " value must be 0..3"));
> + break;
> + }
> + ip->insn_opcode
> + |= ENCODE_SPACEMIT_IME_UIMM2_SP
> + (imm_expr->X_add_number);
> + imm_expr->X_op = O_absent;
> + asarg = expr_parse_end;
> + continue;
> case 'w':
> /* Xpw: optional data-width suffix, i8 only (WI=3).
> If omitted, defaults to i8. */
> @@ -4363,6 +4441,30 @@ riscv_ip (char *str, struct riscv_cl_insn *ip,
> expressionS *imm_expr,
> regno = 3;
> INSERT_OPERAND (SPACEMIT_IME_WI, *ip, regno);
> continue;
> + case 'x':
> + /* Xpx: optional data-width suffix, i4 or i8 (WI=2/3).
> + If omitted, defaults to i8. */
> + if (*asarg == ',')
> + {
> + if (strcmp (asarg + 1, "i4") == 0)
> + regno = 2;
> + else if (strcmp (asarg + 1, "i8") == 0)
> + regno = 3;
> + else
> + {
> + error.msg
> + = _("illegal operands (invalid data type)");
> + error.missing_ext = NULL;
> + goto out;
> + }
> + asarg += 3;
> + }
> + else if (*asarg != '\0')
> + goto unknown_riscv_ip_operand;
> + else
> + regno = 3;
> + INSERT_OPERAND (SPACEMIT_IME_WI, *ip, regno);
> + continue;
> default:
> goto unknown_riscv_ip_operand;
> }
> diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
> index 0b1a4265843..0cd21c8d157 100644
> --- a/gas/doc/c-riscv.texi
> +++ b/gas/doc/c-riscv.texi
> @@ -926,4 +926,12 @@ documented in
> @url{https://github.com/spacemit-com/riscv-ime-extension-spec/rele
> SpacemiT X60 implement version 1.0 of the SpacemiT Vector Dot Product
> Extension (XsmtVdot v1.0), a subset of the full IME specification,
> documented in
> @url{https://github.com/spacemit-com/docs-ai/blob/main/en/architecture/ime_extension.md}.
>
> +@item XSmtVdotII
> +The XSmtVdotII extension provides instructions for vector dot.
> +
> +SpacemiT defines Intrinsic Matrix Extension (IME) specification,
> +documented in
> @url{https://github.com/spacemit-com/riscv-ime-extension-spec/releases/download/v1.0/spacemit-ime-asciidoc.pdf}.
> +SpacemiT A100 implement version 1.0 of the SpacemiT Vector Dot
> Product II Extension (XsmtVdotII v1.0), a subset of the full IME
> specification,
> +documented in
> @url{https://github.com/spacemit-com/docs-ai/blob/main/en/architecture/ime_extension.md}.
> +
> @end table
> diff --git a/gas/testsuite/gas/riscv/march-help.l
> b/gas/testsuite/gas/riscv/march-help.l
> index 6e52669e9a4..d70d1cf2bb6 100644
> --- a/gas/testsuite/gas/riscv/march-help.l
> +++ b/gas/testsuite/gas/riscv/march-help.l
> @@ -187,3 +187,4 @@ All available -march extensions for RISC-V:
> xmipsexectl 1.0
> xmipslsp 1.0
> xsmtvdot 1.0
> + xsmtvdotii 1.0
> diff --git a/gas/testsuite/gas/riscv/x-smt-vdot-fail.l
> b/gas/testsuite/gas/riscv/x-smt-vdot-fail.l
> index 77511d45296..56c7185d2a5 100644
> --- a/gas/testsuite/gas/riscv/x-smt-vdot-fail.l
> +++ b/gas/testsuite/gas/riscv/x-smt-vdot-fail.l
> @@ -39,35 +39,35 @@
> .*:42: Error: illegal operands \(invalid data type\) `smt.vmadot1u
> v2,v4,v5,i2'
> .*:43: Error: illegal operands \(invalid data type\) `smt.vmadot2u
> v2,v4,v5,i4'
> .*:44: Error: illegal operands \(invalid data type\) `smt.vmadot3u
> v2,v4,v5,i16'
> -.*:2: Error: unrecognized opcode `smt.vmadot v2,v3,v4', extension
> `xsmtvdot' required
> -.*:3: Error: unrecognized opcode `smt.vmadotu v2,v3,v4', extension
> `xsmtvdot' required
> -.*:4: Error: unrecognized opcode `smt.vmadotsu v2,v3,v4', extension
> `xsmtvdot' required
> -.*:5: Error: unrecognized opcode `smt.vmadotus v2,v3,v4', extension
> `xsmtvdot' required
> -.*:6: Error: unrecognized opcode `smt.vmadot1u v2,v4,v5', extension
> `xsmtvdot' required
> -.*:7: Error: unrecognized opcode `smt.vmadot1 v2,v4,v5', extension
> `xsmtvdot' required
> -.*:8: Error: unrecognized opcode `smt.vmadot1su v2,v4,v5', extension
> `xsmtvdot' required
> -.*:9: Error: unrecognized opcode `smt.vmadot1us v2,v4,v5', extension
> `xsmtvdot' required
> -.*:10: Error: unrecognized opcode `smt.vmadot2u v2,v4,v5', extension
> `xsmtvdot' required
> -.*:11: Error: unrecognized opcode `smt.vmadot2 v2,v4,v5', extension
> `xsmtvdot' required
> -.*:12: Error: unrecognized opcode `smt.vmadot2su v2,v4,v5', extension
> `xsmtvdot' required
> -.*:13: Error: unrecognized opcode `smt.vmadot2us v2,v4,v5', extension
> `xsmtvdot' required
> -.*:14: Error: unrecognized opcode `smt.vmadot3u v2,v4,v5', extension
> `xsmtvdot' required
> -.*:15: Error: unrecognized opcode `smt.vmadot3 v2,v4,v5', extension
> `xsmtvdot' required
> -.*:16: Error: unrecognized opcode `smt.vmadot3su v2,v4,v5', extension
> `xsmtvdot' required
> -.*:17: Error: unrecognized opcode `smt.vmadot3us v2,v4,v5', extension
> `xsmtvdot' required
> -.*:18: Error: unrecognized opcode `smt.vmadot v2,v3,v4,i8', extension
> `xsmtvdot' required
> -.*:19: Error: unrecognized opcode `smt.vmadotu v2,v3,v4,i8',
> extension `xsmtvdot' required
> -.*:20: Error: unrecognized opcode `smt.vmadotsu v2,v3,v4,i8',
> extension `xsmtvdot' required
> -.*:21: Error: unrecognized opcode `smt.vmadotus v2,v3,v4,i8',
> extension `xsmtvdot' required
> -.*:22: Error: unrecognized opcode `smt.vmadot1u v2,v4,v5,i8',
> extension `xsmtvdot' required
> -.*:23: Error: unrecognized opcode `smt.vmadot1 v2,v4,v5,i8',
> extension `xsmtvdot' required
> -.*:24: Error: unrecognized opcode `smt.vmadot1su v2,v4,v5,i8',
> extension `xsmtvdot' required
> -.*:25: Error: unrecognized opcode `smt.vmadot1us v2,v4,v5,i8',
> extension `xsmtvdot' required
> -.*:26: Error: unrecognized opcode `smt.vmadot2u v2,v4,v5,i8',
> extension `xsmtvdot' required
> -.*:27: Error: unrecognized opcode `smt.vmadot2 v2,v4,v5,i8',
> extension `xsmtvdot' required
> -.*:28: Error: unrecognized opcode `smt.vmadot2su v2,v4,v5,i8',
> extension `xsmtvdot' required
> -.*:29: Error: unrecognized opcode `smt.vmadot2us v2,v4,v5,i8',
> extension `xsmtvdot' required
> -.*:30: Error: unrecognized opcode `smt.vmadot3u v2,v4,v5,i8',
> extension `xsmtvdot' required
> -.*:31: Error: unrecognized opcode `smt.vmadot3 v2,v4,v5,i8',
> extension `xsmtvdot' required
> -.*:32: Error: unrecognized opcode `smt.vmadot3su v2,v4,v5,i8',
> extension `xsmtvdot' required
> -.*:33: Error: unrecognized opcode `smt.vmadot3us v2,v4,v5,i8',
> extension `xsmtvdot' required
> +.*:2: Error: unrecognized opcode `smt.vmadot v2,v3,v4', extension
> `xsmtvdot' or `xsmtvdotii' required
> +.*:3: Error: unrecognized opcode `smt.vmadotu v2,v3,v4', extension
> `xsmtvdot' or `xsmtvdotii' required
> +.*:4: Error: unrecognized opcode `smt.vmadotsu v2,v3,v4', extension
> `xsmtvdot' or `xsmtvdotii' required
> +.*:5: Error: unrecognized opcode `smt.vmadotus v2,v3,v4', extension
> `xsmtvdot' or `xsmtvdotii' required
> +.*:6: Error: unrecognized opcode `smt.vmadot1u v2,v4,v5', extension
> `xsmtvdot' or `xsmtvdotii' required
> +.*:7: Error: unrecognized opcode `smt.vmadot1 v2,v4,v5', extension
> `xsmtvdot' or `xsmtvdotii' required
> +.*:8: Error: unrecognized opcode `smt.vmadot1su v2,v4,v5', extension
> `xsmtvdot' or `xsmtvdotii' required
> +.*:9: Error: unrecognized opcode `smt.vmadot1us v2,v4,v5', extension
> `xsmtvdot' or `xsmtvdotii' required
> +.*:10: Error: unrecognized opcode `smt.vmadot2u v2,v4,v5', extension
> `xsmtvdot' or `xsmtvdotii' required
> +.*:11: Error: unrecognized opcode `smt.vmadot2 v2,v4,v5', extension
> `xsmtvdot' or `xsmtvdotii' required
> +.*:12: Error: unrecognized opcode `smt.vmadot2su v2,v4,v5', extension
> `xsmtvdot' or `xsmtvdotii' required
> +.*:13: Error: unrecognized opcode `smt.vmadot2us v2,v4,v5', extension
> `xsmtvdot' or `xsmtvdotii' required
> +.*:14: Error: unrecognized opcode `smt.vmadot3u v2,v4,v5', extension
> `xsmtvdot' or `xsmtvdotii' required
> +.*:15: Error: unrecognized opcode `smt.vmadot3 v2,v4,v5', extension
> `xsmtvdot' or `xsmtvdotii' required
> +.*:16: Error: unrecognized opcode `smt.vmadot3su v2,v4,v5', extension
> `xsmtvdot' or `xsmtvdotii' required
> +.*:17: Error: unrecognized opcode `smt.vmadot3us v2,v4,v5', extension
> `xsmtvdot' or `xsmtvdotii' required
> +.*:18: Error: unrecognized opcode `smt.vmadot v2,v3,v4,i8', extension
> `xsmtvdot' or `xsmtvdotii' required
> +.*:19: Error: unrecognized opcode `smt.vmadotu v2,v3,v4,i8',
> extension `xsmtvdot' or `xsmtvdotii' required
> +.*:20: Error: unrecognized opcode `smt.vmadotsu v2,v3,v4,i8',
> extension `xsmtvdot' or `xsmtvdotii' required
> +.*:21: Error: unrecognized opcode `smt.vmadotus v2,v3,v4,i8',
> extension `xsmtvdot' or `xsmtvdotii' required
> +.*:22: Error: unrecognized opcode `smt.vmadot1u v2,v4,v5,i8',
> extension `xsmtvdot' or `xsmtvdotii' required
> +.*:23: Error: unrecognized opcode `smt.vmadot1 v2,v4,v5,i8',
> extension `xsmtvdot' or `xsmtvdotii' required
> +.*:24: Error: unrecognized opcode `smt.vmadot1su v2,v4,v5,i8',
> extension `xsmtvdot' or `xsmtvdotii' required
> +.*:25: Error: unrecognized opcode `smt.vmadot1us v2,v4,v5,i8',
> extension `xsmtvdot' or `xsmtvdotii' required
> +.*:26: Error: unrecognized opcode `smt.vmadot2u v2,v4,v5,i8',
> extension `xsmtvdot' or `xsmtvdotii' required
> +.*:27: Error: unrecognized opcode `smt.vmadot2 v2,v4,v5,i8',
> extension `xsmtvdot' or `xsmtvdotii' required
> +.*:28: Error: unrecognized opcode `smt.vmadot2su v2,v4,v5,i8',
> extension `xsmtvdot' or `xsmtvdotii' required
> +.*:29: Error: unrecognized opcode `smt.vmadot2us v2,v4,v5,i8',
> extension `xsmtvdot' or `xsmtvdotii' required
> +.*:30: Error: unrecognized opcode `smt.vmadot3u v2,v4,v5,i8',
> extension `xsmtvdot' or `xsmtvdotii' required
> +.*:31: Error: unrecognized opcode `smt.vmadot3 v2,v4,v5,i8',
> extension `xsmtvdot' or `xsmtvdotii' required
> +.*:32: Error: unrecognized opcode `smt.vmadot3su v2,v4,v5,i8',
> extension `xsmtvdot' or `xsmtvdotii' required
> +.*:33: Error: unrecognized opcode `smt.vmadot3us v2,v4,v5,i8',
> extension `xsmtvdot' or `xsmtvdotii' required
> diff --git a/gas/testsuite/gas/riscv/x-smt-vdot-ii-fail.d
> b/gas/testsuite/gas/riscv/x-smt-vdot-ii-fail.d
> new file mode 100644
> index 00000000000..4b5944511b0
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/x-smt-vdot-ii-fail.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv64gcv_xsmtvdotii
> +#source: x-smt-vdot-ii-fail.s
> +#error_output: x-smt-vdot-ii-fail.l
> diff --git a/gas/testsuite/gas/riscv/x-smt-vdot-ii-fail.l
> b/gas/testsuite/gas/riscv/x-smt-vdot-ii-fail.l
> new file mode 100644
> index 00000000000..3bc22641173
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/x-smt-vdot-ii-fail.l
> @@ -0,0 +1,99 @@
> +.*: Assembler messages:
> +.*:3: Error: illegal operands \(vd must be even\) `smt.vmadot v1,v3,v4'
> +.*:4: Error: illegal operands \(vd must be even\) `smt.vmadotu v1,v3,v4'
> +.*:5: Error: illegal operands \(vd must be even\) `smt.vmadotsu v1,v3,v4'
> +.*:6: Error: illegal operands \(vd must be even\) `smt.vmadotus v1,v3,v4'
> +.*:7: Error: illegal operands \(vd must be even\) `smt.vmadot1u v1,v4,v5'
> +.*:8: Error: illegal operands \(vd must be even\) `smt.vmadot1 v1,v4,v5'
> +.*:9: Error: illegal operands \(vd must be even\) `smt.vmadot1su
> v1,v4,v5'
> +.*:10: Error: illegal operands \(vd must be even\) `smt.vmadot1us
> v1,v4,v5'
> +.*:11: Error: illegal operands \(vd must be even\) `smt.vmadot2u
> v1,v4,v5'
> +.*:12: Error: illegal operands \(vd must be even\) `smt.vmadot2 v1,v4,v5'
> +.*:13: Error: illegal operands \(vd must be even\) `smt.vmadot2su
> v1,v4,v5'
> +.*:14: Error: illegal operands \(vd must be even\) `smt.vmadot2us
> v1,v4,v5'
> +.*:15: Error: illegal operands \(vd must be even\) `smt.vmadot3u
> v1,v4,v5'
> +.*:16: Error: illegal operands \(vd must be even\) `smt.vmadot3 v1,v4,v5'
> +.*:17: Error: illegal operands \(vd must be even\) `smt.vmadot3su
> v1,v4,v5'
> +.*:18: Error: illegal operands \(vd must be even\) `smt.vmadot3us
> v1,v4,v5'
> +.*:20: Error: illegal operands \(vs1 must be even\) `smt.vmadot1u
> v2,v3,v5'
> +.*:21: Error: illegal operands \(vs1 must be even\) `smt.vmadot1
> v2,v3,v5'
> +.*:22: Error: illegal operands \(vs1 must be even\) `smt.vmadot1su
> v2,v3,v5'
> +.*:23: Error: illegal operands \(vs1 must be even\) `smt.vmadot1us
> v2,v3,v5'
> +.*:24: Error: illegal operands \(vs1 must be even\) `smt.vmadot2u
> v2,v3,v5'
> +.*:25: Error: illegal operands \(vs1 must be even\) `smt.vmadot2
> v2,v3,v5'
> +.*:26: Error: illegal operands \(vs1 must be even\) `smt.vmadot2su
> v2,v3,v5'
> +.*:27: Error: illegal operands \(vs1 must be even\) `smt.vmadot2us
> v2,v3,v5'
> +.*:28: Error: illegal operands \(vs1 must be even\) `smt.vmadot3u
> v2,v3,v5'
> +.*:29: Error: illegal operands \(vs1 must be even\) `smt.vmadot3
> v2,v3,v5'
> +.*:30: Error: illegal operands \(vs1 must be even\) `smt.vmadot3su
> v2,v3,v5'
> +.*:31: Error: illegal operands \(vs1 must be even\) `smt.vmadot3us
> v2,v3,v5'
> +.*:33: Error: illegal operands \(invalid data type\) `smt.vmadot1u
> v2,v4,v5,i4'
> +.*:34: Error: illegal operands \(invalid data type\) `smt.vmadot1
> v2,v4,v5,i4'
> +.*:35: Error: illegal operands \(invalid data type\) `smt.vmadot1su
> v2,v4,v5,i4'
> +.*:36: Error: illegal operands \(invalid data type\) `smt.vmadot1us
> v2,v4,v5,i4'
> +.*:37: Error: illegal operands \(invalid data type\) `smt.vmadot2u
> v2,v4,v5,i4'
> +.*:38: Error: illegal operands \(invalid data type\) `smt.vmadot2
> v2,v4,v5,i4'
> +.*:39: Error: illegal operands \(invalid data type\) `smt.vmadot2su
> v2,v4,v5,i4'
> +.*:40: Error: illegal operands \(invalid data type\) `smt.vmadot2us
> v2,v4,v5,i4'
> +.*:41: Error: illegal operands \(invalid data type\) `smt.vmadot3u
> v2,v4,v5,i4'
> +.*:42: Error: illegal operands \(invalid data type\) `smt.vmadot3
> v2,v4,v5,i4'
> +.*:43: Error: illegal operands \(invalid data type\) `smt.vmadot3su
> v2,v4,v5,i4'
> +.*:44: Error: illegal operands \(invalid data type\) `smt.vmadot3us
> v2,v4,v5,i4'
> +.*:46: Error: illegal operands \(invalid data type\) `smt.vmadot
> v2,v3,v4,i1'
> +.*:47: Error: illegal operands \(invalid data type\) `smt.vmadot
> v2,v3,v4,i2'
> +.*:48: Error: illegal operands \(invalid data type\) `smt.vmadot
> v2,v3,v4,i3'
> +.*:49: Error: illegal operands \(invalid data type\) `smt.vmadot
> v2,v3,v4,i5'
> +.*:50: Error: illegal operands \(invalid data type\) `smt.vmadot
> v2,v3,v4,i7'
> +.*:51: Error: illegal operands \(invalid data type\) `smt.vmadot
> v2,v3,v4,i16'
> +.*:52: Error: illegal operands \(invalid data type\) `smt.vmadot
> v2,v3,v4,i32'
> +.*:53: Error: illegal operands \(invalid data type\) `smt.vmadot
> v2,v3,v4,i64'
> +.*:54: Error: illegal operands \(invalid data type\) `smt.vmadot
> v2,v3,v4,i40'
> +.*:55: Error: illegal operands \(invalid data type\) `smt.vmadot1u
> v2,v4,v5,i2'
> +.*:56: Error: illegal operands \(invalid data type\) `smt.vmadot2u
> v2,v4,v5,i16'
> +.*:57: Error: illegal operands \(invalid data type\) `smt.vmadot3u
> v2,v4,v5,i32'
> +.*:60: Error: illegal operands \(vd must be even\) `smt.vmadotu.sp
> v1,v4,v5,v0,0,i8'
> +.*:61: Error: illegal operands \(vs1 must be even\) `smt.vmadotu.sp
> v2,v3,v5,v0,0,i8'
> +.*:63: Error: illegal operands \(mask must be v0/v1\) `smt.vmadotu.sp
> v2,v4,v5,v2,0,i8'
> +.*:65: Error: illegal operands \(invalid data type\) `smt.vmadotu.sp
> v2,v4,v5,v0,2,i4'
> +.*:66: Error: illegal operands \(invalid data type\) `smt.vmadotu.sp
> v2,v4,v5,v0,3,i4'
> +.*:68: Error: bad value for stride field, value must be 0\.\.3
> +.*:68: Error: illegal operands `smt.vmadotu.sp v2,v4,v5,v0,4,i8'
> +.*:70: Error: illegal operands \(mask must be v0/v1\) `smt.vmadotu.hp
> v2,v3,v4,v2,0,i4'
> +.*:72: Error: improper immediate value \(8\)
> +.*:74: Error: illegal operands \(vd must be even\) `smt.vfwmadot
> v1,v3,v4'
> +.*:75: Error: illegal operands \(vd must be even\) `smt.vfwmadot1
> v1,v4,v5'
> +.*:76: Error: illegal operands \(vd must be even\) `smt.vfwmadot2
> v1,v4,v5'
> +.*:77: Error: illegal operands \(vd must be even\) `smt.vfwmadot3
> v1,v4,v5'
> +.*:79: Error: illegal operands \(vs1 must be even\) `smt.vfwmadot1
> v2,v3,v5'
> +.*:80: Error: illegal operands \(vs1 must be even\) `smt.vfwmadot2
> v2,v3,v5'
> +.*:81: Error: illegal operands \(vs1 must be even\) `smt.vfwmadot3
> v2,v3,v5'
> +.*:83: Error: improper immediate value \(4\)
> +.*:84: Error: improper immediate value \(4\)
> +.*:85: Error: improper immediate value \(4\)
> +.*:86: Error: improper immediate value \(4\)
> +.*:88: Error: illegal operands \(vd must be even\) `smt.vpack.vv
> v1,v3,v4,0'
> +.*:89: Error: improper immediate value \(4\)
> +.*:90: Error: illegal operands \(vd must be even\) `smt.vupack.vv
> v1,v3,v4,0'
> +.*:91: Error: improper immediate value \(4\)
> +.*:96: Error: illegal operands \(invalid data type\) \`smt\.vmadot
> v2,v3,v4,i4'
> +.*:97: Error: illegal operands \(invalid data type\) \`smt\.vmadotu
> v2,v3,v4,i4'
> +.*:98: Error: illegal operands \(invalid data type\) \`smt\.vmadotsu
> v2,v3,v4,i4'
> +.*:99: Error: illegal operands \(invalid data type\) \`smt\.vmadotus
> v2,v3,v4,i4'
> +.*:100: Error: unrecognized opcode \`smt\.vmadotu\.sp
> v2,v4,v5,v0,0,i4', extension \`xsmtvdotii' required
> +.*:101: Error: unrecognized opcode \`smt\.vmadot\.sp
> v2,v4,v5,v0,0,i4', extension \`xsmtvdotii' required
> +.*:102: Error: unrecognized opcode \`smt\.vmadotsu\.sp
> v2,v4,v5,v0,0,i4', extension \`xsmtvdotii' required
> +.*:103: Error: unrecognized opcode \`smt\.vmadotus\.sp
> v2,v4,v5,v0,0,i4', extension \`xsmtvdotii' required
> +.*:104: Error: unrecognized opcode \`smt\.vmadotu\.hp
> v2,v3,v4,v0,0,i4', extension \`xsmtvdotii' required
> +.*:105: Error: unrecognized opcode \`smt\.vmadot\.hp
> v2,v3,v4,v0,0,i4', extension \`xsmtvdotii' required
> +.*:106: Error: unrecognized opcode \`smt\.vmadotsu\.hp
> v2,v3,v4,v0,0,i4', extension \`xsmtvdotii' required
> +.*:107: Error: unrecognized opcode \`smt\.vmadotus\.hp
> v2,v3,v4,v0,0,i4', extension \`xsmtvdotii' required
> +.*:108: Error: unrecognized opcode \`smt\.vfwmadot v2,v3,v4',
> extension \`xsmtvdotii' required
> +.*:109: Error: unrecognized opcode \`smt\.vfwmadot1 v2,v4,v5',
> extension \`xsmtvdotii' required
> +.*:110: Error: unrecognized opcode \`smt\.vfwmadot2 v2,v4,v5',
> extension \`xsmtvdotii' required
> +.*:111: Error: unrecognized opcode \`smt\.vfwmadot3 v2,v4,v5',
> extension \`xsmtvdotii' required
> +.*:112: Error: unrecognized opcode \`smt\.vnpack\.vv v2,v3,v4,0',
> extension \`xsmtvdotii' required
> +.*:113: Error: unrecognized opcode \`smt\.vnspack\.vv v2,v3,v4,0',
> extension \`xsmtvdotii' required
> +.*:114: Error: unrecognized opcode \`smt\.vnpack4\.vv v2,v3,v4,0',
> extension \`xsmtvdotii' required
> +.*:115: Error: unrecognized opcode \`smt\.vnspack4\.vv v2,v3,v4,0',
> extension \`xsmtvdotii' required
> +.*:116: Error: unrecognized opcode \`smt\.vpack\.vv v2,v3,v4,0',
> extension \`xsmtvdotii' required
> +.*:117: Error: unrecognized opcode \`smt\.vupack\.vv v2,v3,v4,0',
> extension \`xsmtvdotii' required
> diff --git a/gas/testsuite/gas/riscv/x-smt-vdot-ii-fail.s
> b/gas/testsuite/gas/riscv/x-smt-vdot-ii-fail.s
> new file mode 100644
> index 00000000000..9b8877270a5
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/x-smt-vdot-ii-fail.s
> @@ -0,0 +1,118 @@
> +target:
> + # vmadot/vmadot1/2/3: vd must be even
> + smt.vmadot v1, v3, v4
> + smt.vmadotu v1, v3, v4
> + smt.vmadotsu v1, v3, v4
> + smt.vmadotus v1, v3, v4
> + smt.vmadot1u v1, v4, v5
> + smt.vmadot1 v1, v4, v5
> + smt.vmadot1su v1, v4, v5
> + smt.vmadot1us v1, v4, v5
> + smt.vmadot2u v1, v4, v5
> + smt.vmadot2 v1, v4, v5
> + smt.vmadot2su v1, v4, v5
> + smt.vmadot2us v1, v4, v5
> + smt.vmadot3u v1, v4, v5
> + smt.vmadot3 v1, v4, v5
> + smt.vmadot3su v1, v4, v5
> + smt.vmadot3us v1, v4, v5
> + # vmadot1/2/3: vs1 must be even
> + smt.vmadot1u v2, v3, v5
> + smt.vmadot1 v2, v3, v5
> + smt.vmadot1su v2, v3, v5
> + smt.vmadot1us v2, v3, v5
> + smt.vmadot2u v2, v3, v5
> + smt.vmadot2 v2, v3, v5
> + smt.vmadot2su v2, v3, v5
> + smt.vmadot2us v2, v3, v5
> + smt.vmadot3u v2, v3, v5
> + smt.vmadot3 v2, v3, v5
> + smt.vmadot3su v2, v3, v5
> + smt.vmadot3us v2, v3, v5
> + # vmadot1/2/3: i4 invalid (only i8 valid via Xpw)
> + smt.vmadot1u v2, v4, v5, i4
> + smt.vmadot1 v2, v4, v5, i4
> + smt.vmadot1su v2, v4, v5, i4
> + smt.vmadot1us v2, v4, v5, i4
> + smt.vmadot2u v2, v4, v5, i4
> + smt.vmadot2 v2, v4, v5, i4
> + smt.vmadot2su v2, v4, v5, i4
> + smt.vmadot2us v2, v4, v5, i4
> + smt.vmadot3u v2, v4, v5, i4
> + smt.vmadot3 v2, v4, v5, i4
> + smt.vmadot3su v2, v4, v5, i4
> + smt.vmadot3us v2, v4, v5, i4
> + # vmadot/vmadot1/2/3: invalid data type
> + smt.vmadot v2, v3, v4, i1
> + smt.vmadot v2, v3, v4, i2
> + smt.vmadot v2, v3, v4, i3
> + smt.vmadot v2, v3, v4, i5
> + smt.vmadot v2, v3, v4, i7
> + smt.vmadot v2, v3, v4, i16
> + smt.vmadot v2, v3, v4, i32
> + smt.vmadot v2, v3, v4, i64
> + smt.vmadot v2, v3, v4, i40
> + smt.vmadot1u v2, v4, v5, i2
> + smt.vmadot2u v2, v4, v5, i16
> + smt.vmadot3u v2, v4, v5, i32
> +
> + # vmadot.sp: vd/vs1 must be even
> + smt.vmadotu.sp v1, v4, v5, v0, 0, i8
> + smt.vmadotu.sp v2, v3, v5, v0, 0, i8
> + # vmadot.sp: mask must be v0/v1
> + smt.vmadotu.sp v2, v4, v5, v2, 0, i8
> + # vmadot.sp: i4 only valid with stride 0/1
> + smt.vmadotu.sp v2, v4, v5, v0, 2, i4
> + smt.vmadotu.sp v2, v4, v5, v0, 3, i4
> + # vmadot.sp: stride >= 4 out of range
> + smt.vmadotu.sp v2, v4, v5, v0, 4, i8
> + # vmadot.hp: mask must be v0/v1
> + smt.vmadotu.hp v2, v3, v4, v2, 0, i4
> + # vmadot.hp: stride >= 8 out of range
> + smt.vmadotu.hp v2, v3, v4, v0, 8, i4
> + # vfwmadot: vd must be even
> + smt.vfwmadot v1, v3, v4
> + smt.vfwmadot1 v1, v4, v5
> + smt.vfwmadot2 v1, v4, v5
> + smt.vfwmadot3 v1, v4, v5
> + # vfwmadot1/2/3: vs1 must be even
> + smt.vfwmadot1 v2, v3, v5
> + smt.vfwmadot2 v2, v3, v5
> + smt.vfwmadot3 v2, v3, v5
> + # vnpack/vnspack/vnpack4/vnspack4: imm2 out of range
> + smt.vnpack.vv v2, v3, v4, 4
> + smt.vnspack.vv v2, v3, v4, 4
> + smt.vnpack4.vv v2, v3, v4, 4
> + smt.vnspack4.vv v2, v3, v4, 4
> + # vpack/vupack: vd must be even, imm2 out of range
> + smt.vpack.vv v1, v3, v4, 0
> + smt.vpack.vv v2, v3, v4, 4
> + smt.vupack.vv v1, v3, v4, 0
> + smt.vupack.vv v2, v3, v4, 4
> +
> + # xsmtvdotii - extension required (xsmtvdotii-only insns need
> xsmtvdotii)
> + .option push
> + .option arch, rv64gcv_xsmtvdot
> + smt.vmadot v2, v3, v4, i4
> + smt.vmadotu v2, v3, v4, i4
> + smt.vmadotsu v2, v3, v4, i4
> + smt.vmadotus v2, v3, v4, i4
> + smt.vmadotu.sp v2, v4, v5, v0, 0, i4
> + smt.vmadot.sp v2, v4, v5, v0, 0, i4
> + smt.vmadotsu.sp v2, v4, v5, v0, 0, i4
> + smt.vmadotus.sp v2, v4, v5, v0, 0, i4
> + smt.vmadotu.hp v2, v3, v4, v0, 0, i4
> + smt.vmadot.hp v2, v3, v4, v0, 0, i4
> + smt.vmadotsu.hp v2, v3, v4, v0, 0, i4
> + smt.vmadotus.hp v2, v3, v4, v0, 0, i4
> + smt.vfwmadot v2, v3, v4
> + smt.vfwmadot1 v2, v4, v5
> + smt.vfwmadot2 v2, v4, v5
> + smt.vfwmadot3 v2, v4, v5
> + smt.vnpack.vv v2, v3, v4, 0
> + smt.vnspack.vv v2, v3, v4, 0
> + smt.vnpack4.vv v2, v3, v4, 0
> + smt.vnspack4.vv v2, v3, v4, 0
> + smt.vpack.vv v2, v3, v4, 0
> + smt.vupack.vv v2, v3, v4, 0
> + .option pop
> diff --git a/gas/testsuite/gas/riscv/x-smt-vdot-ii.d
> b/gas/testsuite/gas/riscv/x-smt-vdot-ii.d
> new file mode 100644
> index 00000000000..7eb161644fa
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/x-smt-vdot-ii.d
> @@ -0,0 +1,69 @@
> +#as: -march=rv64gcv_xsmtvdotii
> +#objdump: -dr
> +
> +.*:[ ]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+c241b12b[ ]+smt.vmadot[ ]+v2,v3,v4,i4
> +[ ]+[0-9a-f]+:[ ]+c241812b[ ]+smt.vmadotu[ ]+v2,v3,v4,i4
> +[ ]+[0-9a-f]+:[ ]+c241a12b[ ]+smt.vmadotsu[ ]+v2,v3,v4,i4
> +[ ]+[0-9a-f]+:[ ]+c241912b[ ]+smt.vmadotus[ ]+v2,v3,v4,i4
> +[ ]+[0-9a-f]+:[ ]+e241b12b[ ]+smt.vmadot[ ]+v2,v3,v4
> +[ ]+[0-9a-f]+:[ ]+e241812b[ ]+smt.vmadotu[ ]+v2,v3,v4
> +[ ]+[0-9a-f]+:[ ]+e241a12b[ ]+smt.vmadotsu[ ]+v2,v3,v4
> +[ ]+[0-9a-f]+:[ ]+e241912b[ ]+smt.vmadotus[ ]+v2,v3,v4
> +[ ]+[0-9a-f]+:[ ]+e241b12b[ ]+smt.vmadot[ ]+v2,v3,v4
> +[ ]+[0-9a-f]+:[ ]+e241812b[ ]+smt.vmadotu[ ]+v2,v3,v4
> +[ ]+[0-9a-f]+:[ ]+e241a12b[ ]+smt.vmadotsu[ ]+v2,v3,v4
> +[ ]+[0-9a-f]+:[ ]+e241912b[ ]+smt.vmadotus[ ]+v2,v3,v4
> +[ ]+[0-9a-f]+:[ ]+e652012b[ ]+smt.vmadot1u[ ]+v2,v4,v5
> +[ ]+[0-9a-f]+:[ ]+e652312b[ ]+smt.vmadot1[ ]+v2,v4,v5
> +[ ]+[0-9a-f]+:[ ]+e652212b[ ]+smt.vmadot1su[ ]+v2,v4,v5
> +[ ]+[0-9a-f]+:[ ]+e652112b[ ]+smt.vmadot1us[ ]+v2,v4,v5
> +[ ]+[0-9a-f]+:[ ]+e652412b[ ]+smt.vmadot2u[ ]+v2,v4,v5
> +[ ]+[0-9a-f]+:[ ]+e652712b[ ]+smt.vmadot2[ ]+v2,v4,v5
> +[ ]+[0-9a-f]+:[ ]+e652612b[ ]+smt.vmadot2su[ ]+v2,v4,v5
> +[ ]+[0-9a-f]+:[ ]+e652512b[ ]+smt.vmadot2us[ ]+v2,v4,v5
> +[ ]+[0-9a-f]+:[ ]+e652812b[ ]+smt.vmadot3u[ ]+v2,v4,v5
> +[ ]+[0-9a-f]+:[ ]+e652b12b[ ]+smt.vmadot3[ ]+v2,v4,v5
> +[ ]+[0-9a-f]+:[ ]+e652a12b[ ]+smt.vmadot3su[ ]+v2,v4,v5
> +[ ]+[0-9a-f]+:[ ]+e652912b[ ]+smt.vmadot3us[ ]+v2,v4,v5
> +[ ]+[0-9a-f]+:[ ]+c852012b[ ]+smt.vmadotu.sp[
> ]+v2,v4,v5,v0,0,i4
> +[ ]+[0-9a-f]+:[ ]+c85201ab[ ]+smt.vmadotu.sp[
> ]+v2,v4,v5,v0,1,i4
> +[ ]+[0-9a-f]+:[ ]+c852312b[ ]+smt.vmadot.sp[
> ]+v2,v4,v5,v0,0,i4
> +[ ]+[0-9a-f]+:[ ]+c852212b[ ]+smt.vmadotsu.sp[
> ]+v2,v4,v5,v0,0,i4
> +[ ]+[0-9a-f]+:[ ]+c852112b[ ]+smt.vmadotus.sp[
> ]+v2,v4,v5,v0,0,i4
> +[ ]+[0-9a-f]+:[ ]+e852012b[ ]+smt.vmadotu.sp[
> ]+v2,v4,v5,v0,0
> +[ ]+[0-9a-f]+:[ ]+e85201ab[ ]+smt.vmadotu.sp[
> ]+v2,v4,v5,v0,1
> +[ ]+[0-9a-f]+:[ ]+e852312b[ ]+smt.vmadot.sp[ ]+v2,v4,v5,v0,0
> +[ ]+[0-9a-f]+:[ ]+e852212b[ ]+smt.vmadotsu.sp[
> ]+v2,v4,v5,v0,0
> +[ ]+[0-9a-f]+:[ ]+e852112b[ ]+smt.vmadotus.sp[
> ]+v2,v4,v5,v0,0
> +[ ]+[0-9a-f]+:[ ]+e852812b[ ]+smt.vmadotu.sp[
> ]+v2,v4,v5,v0,2
> +[ ]+[0-9a-f]+:[ ]+e85281ab[ ]+smt.vmadotu.sp[
> ]+v2,v4,v5,v0,3
> +[ ]+[0-9a-f]+:[ ]+e852b12b[ ]+smt.vmadot.sp[ ]+v2,v4,v5,v0,2
> +[ ]+[0-9a-f]+:[ ]+e852a12b[ ]+smt.vmadotsu.sp[
> ]+v2,v4,v5,v0,2
> +[ ]+[0-9a-f]+:[ ]+e852912b[ ]+smt.vmadotus.sp[
> ]+v2,v4,v5,v0,2
> +[ ]+[0-9a-f]+:[ ]+ea52812b[ ]+smt.vmadotu.sp[
> ]+v2,v4,v5,v1,2
> +[ ]+[0-9a-f]+:[ ]+ea52b12b[ ]+smt.vmadot.sp[ ]+v2,v4,v5,v1,2
> +[ ]+[0-9a-f]+:[ ]+cc41812b[ ]+smt.vmadotu.hp[
> ]+v2,v3,v4,v0,0,i4
> +[ ]+[0-9a-f]+:[ ]+cc41912b[ ]+smt.vmadotu.hp[
> ]+v2,v3,v4,v0,1,i4
> +[ ]+[0-9a-f]+:[ ]+ec41812b[ ]+smt.vmadotu.hp[
> ]+v2,v3,v4,v0,0
> +[ ]+[0-9a-f]+:[ ]+d041812b[ ]+smt.vmadot.hp[
> ]+v2,v3,v4,v0,0,i4
> +[ ]+[0-9a-f]+:[ ]+d441812b[ ]+smt.vmadotsu.hp[
> ]+v2,v3,v4,v0,0,i4
> +[ ]+[0-9a-f]+:[ ]+d841812b[ ]+smt.vmadotus.hp[
> ]+v2,v3,v4,v0,0,i4
> +[ ]+[0-9a-f]+:[ ]+ce41812b[ ]+smt.vmadotu.hp[
> ]+v2,v3,v4,v1,0,i4
> +[ ]+[0-9a-f]+:[ ]+9e41c12b[ ]+smt.vfwmadot[ ]+v2,v3,v4
> +[ ]+[0-9a-f]+:[ ]+9e52512b[ ]+smt.vfwmadot1[ ]+v2,v4,v5
> +[ ]+[0-9a-f]+:[ ]+9e52612b[ ]+smt.vfwmadot2[ ]+v2,v4,v5
> +[ ]+[0-9a-f]+:[ ]+9e52712b[ ]+smt.vfwmadot3[ ]+v2,v4,v5
> +[ ]+[0-9a-f]+:[ ]+6241812b[ ]+smt.vnpack.vv[ ]+v2,v3,v4,0
> +[ ]+[0-9a-f]+:[ ]+6241912b[ ]+smt.vnpack.vv[ ]+v2,v3,v4,1
> +[ ]+[0-9a-f]+:[ ]+6241c12b[ ]+smt.vnspack.vv[ ]+v2,v3,v4,0
> +[ ]+[0-9a-f]+:[ ]+4241812b[ ]+smt.vnpack4.vv[ ]+v2,v3,v4,0
> +[ ]+[0-9a-f]+:[ ]+4241c12b[ ]+smt.vnspack4.vv[ ]+v2,v3,v4,0
> +[ ]+[0-9a-f]+:[ ]+6641812b[ ]+smt.vpack.vv[ ]+v2,v3,v4,0
> +[ ]+[0-9a-f]+:[ ]+6641912b[ ]+smt.vpack.vv[ ]+v2,v3,v4,1
> +[ ]+[0-9a-f]+:[ ]+6641c12b[ ]+smt.vupack.vv[ ]+v2,v3,v4,0
> diff --git a/gas/testsuite/gas/riscv/x-smt-vdot-ii.s
> b/gas/testsuite/gas/riscv/x-smt-vdot-ii.s
> new file mode 100644
> index 00000000000..d80e07c49b9
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/x-smt-vdot-ii.s
> @@ -0,0 +1,73 @@
> +target:
> + # vmadot (xsmtvdotii only: i4 dtype)
> + smt.vmadot v2, v3, v4, i4
> + smt.vmadotu v2, v3, v4, i4
> + smt.vmadotsu v2, v3, v4, i4
> + smt.vmadotus v2, v3, v4, i4
> + # vmadot default (i8)
> + smt.vmadot v2, v3, v4
> + smt.vmadotu v2, v3, v4
> + smt.vmadotsu v2, v3, v4
> + smt.vmadotus v2, v3, v4
> + # vmadot explicit i8
> + smt.vmadot v2, v3, v4, i8
> + smt.vmadotu v2, v3, v4, i8
> + smt.vmadotsu v2, v3, v4, i8
> + smt.vmadotus v2, v3, v4, i8
> + # vmadot1/2/3 (shared with xsmtvdot, i8 only)
> + smt.vmadot1u v2, v4, v5
> + smt.vmadot1 v2, v4, v5
> + smt.vmadot1su v2, v4, v5
> + smt.vmadot1us v2, v4, v5
> + smt.vmadot2u v2, v4, v5
> + smt.vmadot2 v2, v4, v5
> + smt.vmadot2su v2, v4, v5
> + smt.vmadot2us v2, v4, v5
> + smt.vmadot3u v2, v4, v5
> + smt.vmadot3 v2, v4, v5
> + smt.vmadot3su v2, v4, v5
> + smt.vmadot3us v2, v4, v5
> + # vmadot.sp with Xp9 stride (0/1) and i4
> + smt.vmadotu.sp v2, v4, v5, v0, 0, i4
> + smt.vmadotu.sp v2, v4, v5, v0, 1, i4
> + smt.vmadot.sp v2, v4, v5, v0, 0, i4
> + smt.vmadotsu.sp v2, v4, v5, v0, 0, i4
> + smt.vmadotus.sp v2, v4, v5, v0, 0, i4
> + # vmadot.sp with Xp9 stride (0/1) and i8 (default)
> + smt.vmadotu.sp v2, v4, v5, v0, 0, i8
> + smt.vmadotu.sp v2, v4, v5, v0, 1, i8
> + smt.vmadot.sp v2, v4, v5, v0, 0, i8
> + smt.vmadotsu.sp v2, v4, v5, v0, 0, i8
> + smt.vmadotus.sp v2, v4, v5, v0, 0, i8
> + # vmadot.sp with Xpk stride (2/3) and i8
> + smt.vmadotu.sp v2, v4, v5, v0, 2, i8
> + smt.vmadotu.sp v2, v4, v5, v0, 3, i8
> + smt.vmadot.sp v2, v4, v5, v0, 2, i8
> + smt.vmadotsu.sp v2, v4, v5, v0, 2, i8
> + smt.vmadotus.sp v2, v4, v5, v0, 2, i8
> + # vmadot.sp with mask v1
> + smt.vmadotu.sp v2, v4, v5, v1, 2, i8
> + smt.vmadot.sp v2, v4, v5, v1, 2, i8
> + # vmadot.hp
> + smt.vmadotu.hp v2, v3, v4, v0, 0, i4
> + smt.vmadotu.hp v2, v3, v4, v0, 1, i4
> + smt.vmadotu.hp v2, v3, v4, v0, 0, i8
> + smt.vmadot.hp v2, v3, v4, v0, 0, i4
> + smt.vmadotsu.hp v2, v3, v4, v0, 0, i4
> + smt.vmadotus.hp v2, v3, v4, v0, 0, i4
> + smt.vmadotu.hp v2, v3, v4, v1, 0, i4
> + # vfwmadot
> + smt.vfwmadot v2, v3, v4
> + smt.vfwmadot1 v2, v4, v5
> + smt.vfwmadot2 v2, v4, v5
> + smt.vfwmadot3 v2, v4, v5
> + # vnpack/vnspack/vnpack4/vnspack4
> + smt.vnpack.vv v2, v3, v4, 0
> + smt.vnpack.vv v2, v3, v4, 1
> + smt.vnspack.vv v2, v3, v4, 0
> + smt.vnpack4.vv v2, v3, v4, 0
> + smt.vnspack4.vv v2, v3, v4, 0
> + # vpack/vupack
> + smt.vpack.vv v2, v3, v4, 0
> + smt.vpack.vv v2, v3, v4, 1
> + smt.vupack.vv v2, v3, v4, 0
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index 31b7e7a06a7..cc090670458 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -3890,6 +3890,47 @@
> #define MASK_SMT_VMADOT3SU 0x9e00f0ff
> #define MATCH_SMT_VMADOT3US 0x8600902b
> #define MASK_SMT_VMADOT3US 0x9e00f0ff
> +/* Int Sparse Matrix Multi-Accumulation. */
> +#define MATCH_SMT_VMADOT_SP 0x8800302b
> +#define MASK_SMT_VMADOT_SP 0x9c00707f
> +#define MATCH_SMT_VMADOTSU_SP 0x8800202b
> +#define MASK_SMT_VMADOTSU_SP 0x9c00707f
> +#define MATCH_SMT_VMADOTU_SP 0x8800002b
> +#define MASK_SMT_VMADOTU_SP 0x9c00707f
> +#define MATCH_SMT_VMADOTUS_SP 0x8800102b
> +#define MASK_SMT_VMADOTUS_SP 0x9c00707f
> +/* Shaping High-Precision Matrix Multiplication Accumulation. */
> +#define MATCH_SMT_VMADOTU_HP 0x8c00002b
> +#define MASK_SMT_VMADOTU_HP 0x9c00007f
> +#define MATCH_SMT_VMADOT_HP 0x9000002b
> +#define MASK_SMT_VMADOT_HP 0x9c00007f
> +#define MATCH_SMT_VMADOTSU_HP 0x9400002b
> +#define MASK_SMT_VMADOTSU_HP 0x9c00007f
> +#define MATCH_SMT_VMADOTUS_HP 0x9800002b
> +#define MASK_SMT_VMADOTUS_HP 0x9c00007f
> +/* Floating-Point Expansion Matrix Multi-Accumulation. */
> +#define MATCH_SMT_VFWMADOT 0x9e00402b
> +#define MASK_SMT_VFWMADOT 0xfe0070ff
> +/* Floating-Point Sliding Window Expansion Multi-Accumulation. */
> +#define MATCH_SMT_VFWMADOT1 0x9e00502b
> +#define MASK_SMT_VFWMADOT1 0xfe00f0ff
> +#define MATCH_SMT_VFWMADOT2 0x9e00602b
> +#define MASK_SMT_VFWMADOT2 0xfe00f0ff
> +#define MATCH_SMT_VFWMADOT3 0x9e00702b
> +#define MASK_SMT_VFWMADOT3 0xfe00f0ff
> +/* Element Indentation Assembly. */
> +#define MATCH_SMT_VNPACK_VV 0x6200002b
> +#define MASK_SMT_VNPACK_VV 0xfe00407f
> +#define MATCH_SMT_VNSPACK_VV 0x6200402b
> +#define MASK_SMT_VNSPACK_VV 0xfe00407f
> +#define MATCH_SMT_VNPACK4_VV 0x4200002b
> +#define MASK_SMT_VNPACK4_VV 0xfe00407f
> +#define MATCH_SMT_VNSPACK4_VV 0x4200402b
> +#define MASK_SMT_VNSPACK4_VV 0xfe00407f
> +#define MATCH_SMT_VPACK_VV 0x6600002b
> +#define MASK_SMT_VPACK_VV 0xfe0040ff
> +#define MATCH_SMT_VUPACK_VV 0x6600402b
> +#define MASK_SMT_VUPACK_VV 0xfe0040ff
> /* Unprivileged Counter/Timers CSR addresses. */
> #define CSR_CYCLE 0xc00
> #define CSR_TIME 0xc01
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index 3a32abfcf3c..9c3979a7056 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -141,6 +141,9 @@ static inline unsigned int riscv_insn_length
> (insn_t insn)
> ((RV_X(x, 25, 2) << 5) | (RV_X(x, 9, 3) << 2))
> #define EXTRACT_MIPS_SDP_IMM(x) \
> ((RV_X(x, 25, 2) << 5) | (RV_X(x, 10, 2) << 3))
> +/* Vendor-specific (SPACEMIT) encode macros. */
> +#define ENCODE_SPACEMIT_IME_UIMM2_SP(x) \
> + ((RV_X (x, 0, 1) << 7) | (RV_X (x, 1, 1) << 15))
>
> #define ENCODE_ITYPE_IMM(x) \
> (RV_X(x, 0, 12) << 20)
> @@ -426,6 +429,8 @@ static inline unsigned int riscv_insn_length
> (insn_t insn)
> #define OP_SH_SPACEMIT_IME_VS1 16
> #define OP_MASK_SPACEMIT_IME_WI 0x3
> #define OP_SH_SPACEMIT_IME_WI 29
> +#define OP_MASK_SPACEMIT_IME_VMASK 0x1
> +#define OP_SH_SPACEMIT_IME_VMASK 25
>
> /* ABI names for selected x-registers. */
>
> @@ -615,6 +620,8 @@ enum riscv_insn_class
> INSN_CLASS_XMIPSEXECTL,
> INSN_CLASS_XMIPSLSP,
> INSN_CLASS_XSMTVDOT,
> + INSN_CLASS_XSMTVDOTII,
> + INSN_CLASS_XSMTVDOT_OR_XSMTVDOTII,
> };
>
> /* This structure holds information for a particular instruction. */
> diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> index 93d41343772..3d71666e703 100644
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -933,10 +933,35 @@ print_insn_args (const char *oparg, insn_t l,
> bfd_vma pc, disassemble_info *info
> print (info->stream, dis_style_register, "%s",
> riscv_vecr_names_numeric[vs]);
> break;
> + case 'm':
> + {
> + unsigned vm = EXTRACT_OPERAND (SPACEMIT_IME_VMASK, l);
> + print (info->stream, dis_style_register, "%s",
> + riscv_vecr_names_numeric[vm]);
> + }
> + break;
> default:
> goto undefined_modifier;
> }
> break;
> + case 'n': /* Xpn/Xpb: uimm2 stride, encoded across bits 7,15. */
> + case 'b':
> + {
> + unsigned sp = ((l >> 7) & 1) | (((l >> 15) & 1) << 1);
> + print (info->stream, dis_style_immediate, "%u", sp);
> + }
> + break;
> + case 'u': /* XpuN@S: N-bit unsigned immediate at bit S. */
> + {
> + long n = strtol (oparg + 1, (char **)&oparg, 10);
> + if (*oparg != '@')
> + goto undefined_modifier;
> + long s = strtol (oparg + 1, (char **)&oparg, 10);
> + oparg--;
> + unsigned val = (l >> s) & ((1U << n) - 1);
> + print (info->stream, dis_style_immediate, "%u", val);
> + }
> + break;
> case 'w':
> /* Xpw: optional data-width suffix, i8 only. WI==3 (i8)
> is the default and is omitted from the output. */
> @@ -946,6 +971,17 @@ print_insn_args (const char *oparg, insn_t l,
> bfd_vma pc, disassemble_info *info
> goto undefined_modifier;
> }
> break;
> + case 'x':
> + /* Xpx: optional data-width suffix, i4 or i8. WI==3 (i8)
> + is the default and is omitted from the output. */
> + {
> + unsigned wi = EXTRACT_OPERAND (SPACEMIT_IME_WI, l);
> + if (wi == 2)
> + print (info->stream, dis_style_text, ",i4");
> + else if (wi != 3)
> + print (info->stream, dis_style_text, ",i8");
> + }
> + break;
>
I have a couple of questions about the xsmtvdotii operand handling.
First, in the disassembler handling of Xpx:
if (wi == 2)
print (..., ",i4");
else if (wi != 3)
print (..., ",i8");
Should the last case instead go to undefined_modifier? Xpx seems to allow
only WI == 2 and WI == 3, so WI == 0/1 should not be printed as i8.
Second, for the .sp forms, the comment says that the Xpb/Xpw form is listed
first so that the disassembler picks it for round-trip correctness, but the
actual opcode table lists the Xpn/Xpx form first.
Also, Xpn is the stride 0..1 form in the assembler, while Xpb accepts 0..3.
The disassembler currently prints the raw 2-bit stride for both Xpn and Xpb.
Should the Xpn disassembler path reject stride values 2 and 3, so that
invalid
i4 + stride 2/3 encodings are not printed as valid mnemonics?
> default:
> goto undefined_modifier;
> }
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index 417918bb6f6..680a1f0610e 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -3581,26 +3581,61 @@ const struct riscv_opcode riscv_opcodes[] =
>
> /* SpacemiT custom instructions. */
> /* Int Matrix Multi-Accumulation. */
> -{"smt.vmadot", 0, INSN_CLASS_XSMTVDOT, "XpVd,Vs,VtXpw",
> MATCH_SMT_VMADOT, MASK_SMT_VMADOT, match_opcode, 0 },
> -{"smt.vmadotu", 0, INSN_CLASS_XSMTVDOT, "XpVd,Vs,VtXpw",
> MATCH_SMT_VMADOTU, MASK_SMT_VMADOTU, match_opcode, 0 },
> -{"smt.vmadotsu", 0, INSN_CLASS_XSMTVDOT, "XpVd,Vs,VtXpw",
> MATCH_SMT_VMADOTSU, MASK_SMT_VMADOTSU, match_opcode, 0 },
> -{"smt.vmadotus", 0, INSN_CLASS_XSMTVDOT, "XpVd,Vs,VtXpw",
> MATCH_SMT_VMADOTUS, MASK_SMT_VMADOTUS, match_opcode, 0 },
> +{"smt.vmadot", 0, INSN_CLASS_XSMTVDOTII, "XpVd,Vs,VtXpx",
> MATCH_SMT_VMADOT, MASK_SMT_VMADOT, match_opcode, 0 },
> +{"smt.vmadot", 0, INSN_CLASS_XSMTVDOT_OR_XSMTVDOTII,
> "XpVd,Vs,VtXpw", MATCH_SMT_VMADOT, MASK_SMT_VMADOT, match_opcode, 0 },
> +{"smt.vmadotu", 0, INSN_CLASS_XSMTVDOTII, "XpVd,Vs,VtXpx",
> MATCH_SMT_VMADOTU, MASK_SMT_VMADOTU, match_opcode, 0 },
> +{"smt.vmadotu", 0, INSN_CLASS_XSMTVDOT_OR_XSMTVDOTII,
> "XpVd,Vs,VtXpw", MATCH_SMT_VMADOTU, MASK_SMT_VMADOTU, match_opcode, 0 },
> +{"smt.vmadotsu", 0, INSN_CLASS_XSMTVDOTII, "XpVd,Vs,VtXpx",
> MATCH_SMT_VMADOTSU, MASK_SMT_VMADOTSU, match_opcode, 0 },
> +{"smt.vmadotsu", 0, INSN_CLASS_XSMTVDOT_OR_XSMTVDOTII,
> "XpVd,Vs,VtXpw", MATCH_SMT_VMADOTSU, MASK_SMT_VMADOTSU, match_opcode, 0 },
> +{"smt.vmadotus", 0, INSN_CLASS_XSMTVDOTII, "XpVd,Vs,VtXpx",
> MATCH_SMT_VMADOTUS, MASK_SMT_VMADOTUS, match_opcode, 0 },
> +{"smt.vmadotus", 0, INSN_CLASS_XSMTVDOT_OR_XSMTVDOTII,
> "XpVd,Vs,VtXpw", MATCH_SMT_VMADOTUS, MASK_SMT_VMADOTUS, match_opcode, 0 },
> /* Int Sliding Window Multi-Accumulation. */
> /* Sliding Value = 1. */
> -{"smt.vmadot1u", 0, INSN_CLASS_XSMTVDOT, "XpVd,XpVs,VtXpw",
> MATCH_SMT_VMADOT1U, MASK_SMT_VMADOT1U, match_opcode, 0 },
> -{"smt.vmadot1", 0, INSN_CLASS_XSMTVDOT, "XpVd,XpVs,VtXpw",
> MATCH_SMT_VMADOT1, MASK_SMT_VMADOT1, match_opcode, 0 },
> -{"smt.vmadot1su", 0, INSN_CLASS_XSMTVDOT, "XpVd,XpVs,VtXpw",
> MATCH_SMT_VMADOT1SU, MASK_SMT_VMADOT1SU, match_opcode, 0 },
> -{"smt.vmadot1us", 0, INSN_CLASS_XSMTVDOT, "XpVd,XpVs,VtXpw",
> MATCH_SMT_VMADOT1US, MASK_SMT_VMADOT1US, match_opcode, 0 },
> +{"smt.vmadot1u", 0, INSN_CLASS_XSMTVDOT_OR_XSMTVDOTII,
> "XpVd,XpVs,VtXpw", MATCH_SMT_VMADOT1U, MASK_SMT_VMADOT1U,
> match_opcode, 0 },
> +{"smt.vmadot1", 0, INSN_CLASS_XSMTVDOT_OR_XSMTVDOTII,
> "XpVd,XpVs,VtXpw", MATCH_SMT_VMADOT1, MASK_SMT_VMADOT1, match_opcode, 0 },
> +{"smt.vmadot1su", 0, INSN_CLASS_XSMTVDOT_OR_XSMTVDOTII,
> "XpVd,XpVs,VtXpw", MATCH_SMT_VMADOT1SU, MASK_SMT_VMADOT1SU,
> match_opcode, 0 },
> +{"smt.vmadot1us", 0, INSN_CLASS_XSMTVDOT_OR_XSMTVDOTII,
> "XpVd,XpVs,VtXpw", MATCH_SMT_VMADOT1US, MASK_SMT_VMADOT1US,
> match_opcode, 0 },
> /* Sliding Value = 2. */
> -{"smt.vmadot2u", 0, INSN_CLASS_XSMTVDOT, "XpVd,XpVs,VtXpw",
> MATCH_SMT_VMADOT2U, MASK_SMT_VMADOT2U, match_opcode, 0 },
> -{"smt.vmadot2", 0, INSN_CLASS_XSMTVDOT, "XpVd,XpVs,VtXpw",
> MATCH_SMT_VMADOT2, MASK_SMT_VMADOT2, match_opcode, 0 },
> -{"smt.vmadot2su", 0, INSN_CLASS_XSMTVDOT, "XpVd,XpVs,VtXpw",
> MATCH_SMT_VMADOT2SU, MASK_SMT_VMADOT2SU, match_opcode, 0 },
> -{"smt.vmadot2us", 0, INSN_CLASS_XSMTVDOT, "XpVd,XpVs,VtXpw",
> MATCH_SMT_VMADOT2US, MASK_SMT_VMADOT2US, match_opcode, 0 },
> +{"smt.vmadot2u", 0, INSN_CLASS_XSMTVDOT_OR_XSMTVDOTII,
> "XpVd,XpVs,VtXpw", MATCH_SMT_VMADOT2U, MASK_SMT_VMADOT2U,
> match_opcode, 0 },
> +{"smt.vmadot2", 0, INSN_CLASS_XSMTVDOT_OR_XSMTVDOTII,
> "XpVd,XpVs,VtXpw", MATCH_SMT_VMADOT2, MASK_SMT_VMADOT2, match_opcode, 0 },
> +{"smt.vmadot2su", 0, INSN_CLASS_XSMTVDOT_OR_XSMTVDOTII,
> "XpVd,XpVs,VtXpw", MATCH_SMT_VMADOT2SU, MASK_SMT_VMADOT2SU,
> match_opcode, 0 },
> +{"smt.vmadot2us", 0, INSN_CLASS_XSMTVDOT_OR_XSMTVDOTII,
> "XpVd,XpVs,VtXpw", MATCH_SMT_VMADOT2US, MASK_SMT_VMADOT2US,
> match_opcode, 0 },
> /* Sliding Value = 3. */
> -{"smt.vmadot3u", 0, INSN_CLASS_XSMTVDOT, "XpVd,XpVs,VtXpw",
> MATCH_SMT_VMADOT3U, MASK_SMT_VMADOT3U, match_opcode, 0 },
> -{"smt.vmadot3", 0, INSN_CLASS_XSMTVDOT, "XpVd,XpVs,VtXpw",
> MATCH_SMT_VMADOT3, MASK_SMT_VMADOT3, match_opcode, 0 },
> -{"smt.vmadot3su", 0, INSN_CLASS_XSMTVDOT, "XpVd,XpVs,VtXpw",
> MATCH_SMT_VMADOT3SU, MASK_SMT_VMADOT3SU, match_opcode, 0 },
> -{"smt.vmadot3us", 0, INSN_CLASS_XSMTVDOT, "XpVd,XpVs,VtXpw",
> MATCH_SMT_VMADOT3US, MASK_SMT_VMADOT3US, match_opcode, 0 },
> +{"smt.vmadot3u", 0, INSN_CLASS_XSMTVDOT_OR_XSMTVDOTII,
> "XpVd,XpVs,VtXpw", MATCH_SMT_VMADOT3U, MASK_SMT_VMADOT3U,
> match_opcode, 0 },
> +{"smt.vmadot3", 0, INSN_CLASS_XSMTVDOT_OR_XSMTVDOTII,
> "XpVd,XpVs,VtXpw", MATCH_SMT_VMADOT3, MASK_SMT_VMADOT3, match_opcode, 0 },
> +{"smt.vmadot3su", 0, INSN_CLASS_XSMTVDOT_OR_XSMTVDOTII,
> "XpVd,XpVs,VtXpw", MATCH_SMT_VMADOT3SU, MASK_SMT_VMADOT3SU,
> match_opcode, 0 },
> +{"smt.vmadot3us", 0, INSN_CLASS_XSMTVDOT_OR_XSMTVDOTII,
> "XpVd,XpVs,VtXpw", MATCH_SMT_VMADOT3US, MASK_SMT_VMADOT3US,
> match_opcode, 0 },
> +/* Int Sparse Matrix Multi-Accumulation.
> + Each mnemonic has two entries: Xpb (stride 0-3) paired with Xpw (i8)
> + listed first so the disassembler picks it for round-trip correctness,
> + then Xpn (stride 0-1) paired with Xpx (i4/i8) as the assembler
> + fallback for the narrower stride + i4 form. */
> +{"smt.vmadotu.sp", 0, INSN_CLASS_XSMTVDOTII,
> "XpVd,XpVs,Vt,XpVm,XpnXpx", MATCH_SMT_VMADOTU_SP,
> MASK_SMT_VMADOTU_SP, match_opcode, 0 },
> +{"smt.vmadotu.sp", 0, INSN_CLASS_XSMTVDOTII,
> "XpVd,XpVs,Vt,XpVm,XpbXpw", MATCH_SMT_VMADOTU_SP,
> MASK_SMT_VMADOTU_SP, match_opcode, 0 },
> +{"smt.vmadot.sp", 0, INSN_CLASS_XSMTVDOTII,
> "XpVd,XpVs,Vt,XpVm,XpnXpx", MATCH_SMT_VMADOT_SP, MASK_SMT_VMADOT_SP,
> match_opcode, 0 },
> +{"smt.vmadot.sp", 0, INSN_CLASS_XSMTVDOTII,
> "XpVd,XpVs,Vt,XpVm,XpbXpw", MATCH_SMT_VMADOT_SP, MASK_SMT_VMADOT_SP,
> match_opcode, 0 },
> +{"smt.vmadotsu.sp", 0, INSN_CLASS_XSMTVDOTII,
> "XpVd,XpVs,Vt,XpVm,XpnXpx", MATCH_SMT_VMADOTSU_SP,
> MASK_SMT_VMADOTSU_SP, match_opcode, 0 },
> +{"smt.vmadotsu.sp", 0, INSN_CLASS_XSMTVDOTII,
> "XpVd,XpVs,Vt,XpVm,XpbXpw", MATCH_SMT_VMADOTSU_SP,
> MASK_SMT_VMADOTSU_SP, match_opcode, 0 },
> +{"smt.vmadotus.sp", 0, INSN_CLASS_XSMTVDOTII,
> "XpVd,XpVs,Vt,XpVm,XpnXpx", MATCH_SMT_VMADOTUS_SP,
> MASK_SMT_VMADOTUS_SP, match_opcode, 0 },
> +{"smt.vmadotus.sp", 0, INSN_CLASS_XSMTVDOTII,
> "XpVd,XpVs,Vt,XpVm,XpbXpw", MATCH_SMT_VMADOTUS_SP,
> MASK_SMT_VMADOTUS_SP, match_opcode, 0 },
> +/* Shaping High-Precision Matrix Multiplication Accumulation. */
> +{"smt.vmadotu.hp", 0, INSN_CLASS_XSMTVDOTII,
> "Vd,Vs,Vt,XpVm,Xpu3@12Xpx", MATCH_SMT_VMADOTU_HP,
> MASK_SMT_VMADOTU_HP, match_opcode, 0 },
> +{"smt.vmadot.hp", 0, INSN_CLASS_XSMTVDOTII,
> "Vd,Vs,Vt,XpVm,Xpu3@12Xpx", MATCH_SMT_VMADOT_HP, MASK_SMT_VMADOT_HP,
> match_opcode, 0 },
> +{"smt.vmadotsu.hp", 0, INSN_CLASS_XSMTVDOTII,
> "Vd,Vs,Vt,XpVm,Xpu3@12Xpx", MATCH_SMT_VMADOTSU_HP,
> MASK_SMT_VMADOTSU_HP, match_opcode, 0 },
> +{"smt.vmadotus.hp", 0, INSN_CLASS_XSMTVDOTII,
> "Vd,Vs,Vt,XpVm,Xpu3@12Xpx", MATCH_SMT_VMADOTUS_HP,
> MASK_SMT_VMADOTUS_HP, match_opcode, 0 },
> +/* Floating-Point Expansion Matrix Multi-Accumulation. */
> +{"smt.vfwmadot", 0, INSN_CLASS_XSMTVDOTII, "XpVd,Vs,Vt",
> MATCH_SMT_VFWMADOT, MASK_SMT_VFWMADOT, match_opcode, 0 },
> +/* Floating-Point Sliding Window Expansion Multi-Accumulation. */
> +{"smt.vfwmadot1", 0, INSN_CLASS_XSMTVDOTII, "XpVd,XpVs,Vt",
> MATCH_SMT_VFWMADOT1, MASK_SMT_VFWMADOT1, match_opcode, 0 },
> +{"smt.vfwmadot2", 0, INSN_CLASS_XSMTVDOTII, "XpVd,XpVs,Vt",
> MATCH_SMT_VFWMADOT2, MASK_SMT_VFWMADOT2, match_opcode, 0 },
> +{"smt.vfwmadot3", 0, INSN_CLASS_XSMTVDOTII, "XpVd,XpVs,Vt",
> MATCH_SMT_VFWMADOT3, MASK_SMT_VFWMADOT3, match_opcode, 0 },
> +/* Element Indentation Assembly. */
> +{"smt.vnpack.vv", 0, INSN_CLASS_XSMTVDOTII, "Vd,Vs,Vt,Xpu2@12",
> MATCH_SMT_VNPACK_VV, MASK_SMT_VNPACK_VV, match_opcode, 0 },
> +{"smt.vnspack.vv", 0, INSN_CLASS_XSMTVDOTII, "Vd,Vs,Vt,Xpu2@12",
> MATCH_SMT_VNSPACK_VV, MASK_SMT_VNSPACK_VV, match_opcode, 0 },
> +{"smt.vnpack4.vv", 0, INSN_CLASS_XSMTVDOTII, "Vd,Vs,Vt,Xpu2@12",
> MATCH_SMT_VNPACK4_VV, MASK_SMT_VNPACK4_VV, match_opcode, 0 },
> +{"smt.vnspack4.vv", 0, INSN_CLASS_XSMTVDOTII, "Vd,Vs,Vt,Xpu2@12",
> MATCH_SMT_VNSPACK4_VV, MASK_SMT_VNSPACK4_VV, match_opcode, 0 },
> +{"smt.vpack.vv", 0, INSN_CLASS_XSMTVDOTII, "XpVd,Vs,Vt,Xpu2@12",
> MATCH_SMT_VPACK_VV, MASK_SMT_VPACK_VV, match_opcode, 0 },
> +{"smt.vupack.vv", 0, INSN_CLASS_XSMTVDOTII, "XpVd,Vs,Vt,Xpu2@12",
> MATCH_SMT_VUPACK_VV, MASK_SMT_VUPACK_VV, match_opcode, 0 },
>
> /* Terminate the list. */
> {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
>
Reviewed-by: Jiawei <jiawei@iscas.ac.cn>
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