[PATCH 04/23] aarch64: Remove unused operand SM3_IMM2

[Alice Carlotti]

This operand was intended to be used for the sm3tt* instructions, but
those were added with operand Em instead.


diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 0b72fc1a54ffd5b25380ac73558d0a5e3384e18b..bc279ff32ca3d48aa0efe6f06ab1966f2b514bc4 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6460,7 +6460,6 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
     case AARCH64_OPND_Em:
     case AARCH64_OPND_Em16:
     case AARCH64_OPND_Em8:
-    case AARCH64_OPND_SM3_IMM2:
       operand->reglane.regno = default_value;
       break;
 
@@ -7050,7 +7049,6 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 	case AARCH64_OPND_Em:
 	case AARCH64_OPND_Em16:
 	case AARCH64_OPND_Em8:
-	case AARCH64_OPND_SM3_IMM2:
 	  reg_type = REG_TYPE_V;
 	vector_reg_index:
 	  reg = aarch64_reg_parse (&str, reg_type, &vectype);
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 222de5f49ab794852c73ff505c91556099a250d5..30087f5fe3c4703253abe285f78108b68e86fc33 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -987,7 +987,6 @@ enum aarch64_opnd
   AARCH64_OPND_SME_ZT0_INDEX_MUL_VL,/* ZT0[<imm>], bits [13:12].  */
   AARCH64_OPND_SME_ZT0_LIST,	/* { zt0/ZT0 } (not encoded).  */
   AARCH64_OPND_TME_UIMM16,	/* TME unsigned 16-bit immediate.  */
-  AARCH64_OPND_SM3_IMM2,	/* SM3 encodes lane in bits [13, 14].  */
   AARCH64_OPND_MOPS_ADDR_Rd,	/* [Rd]!, in bits [0, 4].  */
   AARCH64_OPND_MOPS_ADDR_Rs,	/* [Rs]!, in bits [16, 20].  */
   AARCH64_OPND_MOPS_WB_Rn,	/* Rn!, in bits [5, 9].  */
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index a5533c43421cefe8095a22a2f4756e98ae180393..d2e302e610022056eb174344b610a7aedebe85da 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -866,7 +866,6 @@ aarch64_insert_operand (const aarch64_operand *self,
     case AARCH64_OPND_Em:
     case AARCH64_OPND_Em16:
     case AARCH64_OPND_Em8:
-    case AARCH64_OPND_SM3_IMM2:
       return aarch64_ins_reglane (self, info, code, inst, errors);
     case AARCH64_OPND_Em_INDEX1_14:
     case AARCH64_OPND_Em_INDEX2_13:
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 69bf6f9056404f1dac99ca86367ac8d6f006ff6c..3cbf33db77cd2540ef5298364b7deb18b05575b1 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -37851,7 +37851,6 @@ aarch64_extract_operand (const aarch64_operand *self,
     case AARCH64_OPND_Em:
     case AARCH64_OPND_Em16:
     case AARCH64_OPND_Em8:
-    case AARCH64_OPND_SM3_IMM2:
       return aarch64_ext_reglane (self, info, code, inst, errors);
     case AARCH64_OPND_Em_INDEX1_14:
     case AARCH64_OPND_Em_INDEX2_13:
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index fb8f664d1957a081f397af0db23786d5d5e00087..8a2c560e53f45592b13daf6d18a9631a3e08a2be 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -365,7 +365,6 @@ const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_IMMEDIATE, "SME_ZT0_INDEX_MUL_VL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm3_12}, "a ZT0 index"},
   {AARCH64_OPND_CLASS_SYSTEM, "SME_ZT0_LIST", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "{ ZT0 }"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_5}, "a 16-bit unsigned immediate for TME tcancel"},
-  {AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"},
   {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a register destination address with writeback"},
   {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "a register source address with writeback"},
   {AARCH64_OPND_CLASS_INT_REG, "MOPS_WB_Rn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register with writeback"},
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 3beecc00fe32efa17e7c8ccd5cf4ded727aec2b6..fb4213e44b240cf7f72b8ec4fd73a860aab06278 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -4311,7 +4311,6 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
     case AARCH64_OPND_Em:
     case AARCH64_OPND_Em16:
     case AARCH64_OPND_Em8:
-    case AARCH64_OPND_SM3_IMM2:
       snprintf (buf, size, "%s[%s]",
 		style_reg (styler, "v%d.%s", opnd->reglane.regno,
 			   aarch64_get_qualifier_name (opnd->qualifier)),
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index fc57f83b120630b91717be5384a421befd44fce8..a6913b8073f9b99eb32ccda0a3274b8516ff6121 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -8674,8 +8674,6 @@ const struct aarch64_opcode aarch64_opcode_table[] =
     Y(SYSTEM, none, "SME_ZT0_LIST", 0, F (), "{ ZT0 }")			\
     Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16_5),			\
       "a 16-bit unsigned immediate for TME tcancel")			\
-    Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2),		\
-      "an indexed SM3 vector immediate")				\
     /* These next two are really register fields; the [...] notation	\
        is just syntactic sugar.  */					\
     Y(INT_REG, x0_to_x30, "MOPS_ADDR_Rd", 0, F(FLD_Rd),			\