[RFC 2/2] RISC-V: Add Zvbdota extension support

[Jeffrey Law]

On 6/9/2026 9:38 AM, Jiawei wrote:
> This patch supports the RISC-V Zvbdota family of batched dot-product
> extensions [1].
>
> Compared to the non-batched Zvdota family, Zvbdota computes up to eight
> dot products at a time.  These instructions use an EMUL=8 `vs2` vector
> register group and a scaled-by-8 `ci` immediate encoded in `vs2[2:0]`.
> This patch adds assembler/disassembler support for those additional
> operand constraints.
>
> The Zvbdota extension family includes the following extensions:
>
> * Zvqwbdota8i: batched dot product of 8-bit integers with 32-bit
>    accumulation.
> * Zvqwbdota16i: batched dot product of 16-bit integers with 64-bit
>    accumulation.
> * Zvfwbdota16bf: batched dot product of bfloat16 floating-point numbers
>    with 32-bit accumulation.
> * Zvfqwbdota8f: batched dot product of 8-bit floating-point numbers with
>    32-bit accumulation.
> * Zvfbdota32f: batched dot product of 32-bit single-precision
>    floating-point numbers with 32-bit accumulation.
>
> [1] https://github.com/riscv/riscv-isa-manual/blob/zvbdot/src/zvdota.adoc
>
>
> bfd/ChangeLog:
>
> 	* elfxx-riscv.c (riscv_implicit_subsets): New implies.
> 	(riscv_supported_std_z_ext): New extensions.
> 	(riscv_multi_subset_supports): Ditto.
> 	(riscv_multi_subset_supports_ext): Ditto.
>
> gas/ChangeLog:
>
> 	* NEWS: Add zvqwbdota8i, zvqwbdota16i, zvfwbdota16bf,
> 	zvfqwbdota8f and zvfbdota32f extensions.
> 	* config/tc-riscv.c (validate_riscv_insn): Add Zvbdota operand
> 	type 'q' and 'r' bits validation.
> 	(riscv_vtype_altfmt_supported): Add Zvbdota extensions.
> 	(my_getVsetvliExpression): Update altfmt error message.
> 	(riscv_ip): Add 'q' operand for VS2 EMUL=8 alignment check
> 	and 'r' operand for ci immediate.
> 	* testsuite/gas/riscv/march-help.l: Ditto.
> 	* testsuite/gas/riscv/zvbdota.d: New test.
> 	* testsuite/gas/riscv/zvbdota.s: Ditto.
> 	* testsuite/gas/riscv/zvbdota-operands-fail.d: Ditto.
> 	* testsuite/gas/riscv/zvbdota-operands-fail.l: Ditto.
> 	* testsuite/gas/riscv/zvbdota-operands-fail.s: Ditto.
> 	* testsuite/gas/riscv/zvbdota-zvqwbdota16i.d: Ditto.
> 	* testsuite/gas/riscv/zvbdota-zvqwbdota16i.s: Ditto.
>
> include/ChangeLog:
>
> 	* opcode/riscv-opc.h (MATCH_VQWBDOTAU_VV, MASK_VQWBDOTAU_VV):
> 	New encoding.
> 	(MATCH_VQWBDOTAS_VV, MASK_VQWBDOTAS_VV): Ditto.
> 	(MATCH_VFWBDOTA_VV, MASK_VFWBDOTA_VV): Ditto.
> 	(MATCH_VFQWBDOTA_VV, MASK_VFQWBDOTA_VV): Ditto.
> 	(MATCH_VFQWBDOTA_ALT_VV, MASK_VFQWBDOTA_ALT_VV): Ditto.
> 	(MATCH_VFBDOTA_VV, MASK_VFBDOTA_VV): Ditto.
> 	(DECLARE_INSN): New declarations.
> 	* opcode/riscv.h (enum riscv_insn_class): New extension classes.
>
> opcodes/ChangeLog:
>
> 	* riscv-dis.c (print_insn_args): Add 'q' and 'r' operand types
> 	for Zvbdota.
> 	* riscv-opc.c (riscv_opcodes): New instructions.
>
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 7714e5dcd49..afe7073ddb7 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1234,8 +1234,13 @@ static const struct riscv_implicit_subset riscv_implicit_subsets[] =
>     {"zvfhmin", "+zve32f", check_implicit_always},
>     {"zvfbfwma", "+zve32f,+zfbfmin", check_implicit_always},
>     {"zvfbfmin", "+zve32f", check_implicit_always},
> +  {"zvfbdota32f", "+zve32f", check_implicit_always},
> +  {"zvfqwbdota8f", "+zve32f", check_implicit_always},
>     {"zvfqwdota8f", "+zve32f", check_implicit_always},
> +  {"zvfwbdota16bf", "+zve32f", check_implicit_always},
>     {"zvfwdota16bf", "+zve32f", check_implicit_always},
> +  {"zvqwbdota8i", "+zve32x", check_implicit_always},
> +  {"zvqwbdota16i", "+zve64x", check_implicit_always},
>     {"zvqwdota8i", "+zve32x", check_implicit_always},
>     {"zvqwdota16i", "+zve64x", check_implicit_always},
>     {"zve64d", "+d,+zve64f", check_implicit_always},
So again, double check the implicit subset stuff.


> diff --git a/gas/NEWS b/gas/NEWS
> index ddb7983aea0..253f25a4691 100644
> --- a/gas/NEWS
> +++ b/gas/NEWS
> @@ -1,7 +1,8 @@
>   -*- text -*-
>   
> -* Add support for RISC-V standard extensions:
> -  zvqwdota8i, zvqwdota16i, zvfwdota16bf and zvfqwdota8f v1.0.
> +* Add support for RISC-V extensions:
> +  zvqwdota8i, zvqwdota16i, zvfwdota16bf, zvfqwdota8f, zvqwbdota8i,
> +  zvqwbdota16i, zvfwbdota16bf, zvfqwbdota8f and zvfbdota32f v1.0.
>   
>   Changes in 2.46:
And this will need updating too.

So, basically same issues to double-check/update as in the first patch 
in this series.  And like the first in this series, I'd like to include 
it in the upcoming release, so if you can turn around any updates, I can 
push it into the trunk.

Thanks!

jeff