[RFC 1/2] RISC-V: Add Zvdota extension classes

[Jeffrey Law]

On 6/9/2026 9:38 AM, Jiawei wrote:
> This patch adds assembler/disassembler support for the RISC-V Zvdota
> family of extensions [1], which compute a dot product between two vector
> register groups.
>
> The Zvdota extension family includes the following extensions:
>
> Zvqwdota8i: dot product of 8-bit integers with 32-bit accumulation.
> Zvqwdota16i: dot product of 16-bit integers with 64-bit accumulation.
> Zvfwdota16bf: dot product of bfloat16 floating-point numbers with
> 32-bit accumulation.
> Zvfqwdota8f: dot product of 8-bit floating-point numbers with
> 32-bit accumulation.
>
> Zvdota also uses the vtype alternative format bit, altfmt, which is bit 8
> of the vtype CSR. This patch adds symbolic e8alt and e16alt vsew
> constants for vsetvli/vsetivli so that assembly code can select the
> alternative element formats required by these dot-product instructions.
>
> [1] https://github.com/riscv/riscv-isa-manual/blob/zvbdot/src/zvdota.adoc
>
> bfd/ChangeLog:
>
> 	* elfxx-riscv.c (riscv_implicit_subsets): New implies.
> 	(riscv_supported_std_z_ext): New extensions.
> 	(riscv_multi_subset_supports): Ditto.
> 	(riscv_multi_subset_supports_ext): Ditto.
>
> gas/ChangeLog:
>
> 	* NEWS: Add zvqwdota8i, zvqwdota16i, zvfwdota16bf and
> 	zvfqwdota8f extensions.
> 	* config/tc-riscv.c (riscv_vsew_altfmt): New vsew altfmt
> 	constants array for e8alt and e16alt.
> 	(riscv_vtype_altfmt_supported): New function.
> 	(my_getVsetvliExpression): Ditto.
> 	* testsuite/gas/riscv/march-help.l: New test.
> 	* testsuite/gas/riscv/vector-vtype-altfmt.d: Ditto.
> 	* testsuite/gas/riscv/vector-vtype-altfmt.s: Ditto.
> 	* testsuite/gas/riscv/zvdota.d: Ditto.
> 	* testsuite/gas/riscv/zvdota.s: Ditto.
>
> include/ChangeLog:
>
> 	* opcode/riscv-opc.h (MATCH_VQWDOTAU_VV, MASK_VQWDOTAU_VV): New
> 	encoding.
> 	(MATCH_VQWDOTAS_VV, MASK_VQWDOTAS_VV): Ditto.
> 	(MATCH_VFWDOTA_VV, MASK_VFWDOTA_VV): Ditto.
> 	(MATCH_VFQWDOTA_VV, MASK_VFQWDOTA_VV): Ditto.
> 	(MATCH_VFQWDOTA_ALT_VV, MASK_VFQWDOTA_ALT_VV): Ditto.
> 	(DECLARE_INSN): New declarations.
> 	* opcode/riscv.h (OP_MASK_VTYPE_ALTFMT, OP_SH_VTYPE_ALTFMT):
> 	New vtype altfmt.
> 	(enum riscv_insn_class): New extension classes.
>
> opcodes/ChangeLog:
>
> 	* riscv-dis.c (print_insn_args): Add altfmt support.
> 	* riscv-opc.c (riscv_opcodes): New instructions.
Overall this looks pretty sensible.


> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 67fbf0f72ca..7714e5dcd49 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1234,6 +1234,10 @@ static const struct riscv_implicit_subset riscv_implicit_subsets[] =
>     {"zvfhmin", "+zve32f", check_implicit_always},
>     {"zvfbfwma", "+zve32f,+zfbfmin", check_implicit_always},
>     {"zvfbfmin", "+zve32f", check_implicit_always},
> +  {"zvfqwdota8f", "+zve32f", check_implicit_always},
> +  {"zvfwdota16bf", "+zve32f", check_implicit_always},
> +  {"zvqwdota8i", "+zve32x", check_implicit_always},
> +  {"zvqwdota16i", "+zve64x", check_implicit_always},
I'd double-check the zvfwdota16bf entry. I haven't looked real closely 
and it's just a bit odd looking that the 16i case is +zve64x, but the 16 
case is ust +zve32f rather than +zve64f.
> diff --git a/gas/NEWS b/gas/NEWS
> index e384d1135c0..ddb7983aea0 100644
> --- a/gas/NEWS
> +++ b/gas/NEWS
> @@ -1,5 +1,8 @@
>   -*- text -*-
>   
> +* Add support for RISC-V standard extensions:
> +  zvqwdota8i, zvqwdota16i, zvfwdota16bf and zvfqwdota8f v1.0.
> +
>   Changes in 2.46:
>   
>   * Add support for AMD Zen6 processor.
The NEWS entry probably needs updating given the other changes that have 
gone in recently.

I'd like to include this in the upcoming release, so please double-check 
that one entry noted above and adjust the NEWS file. With those changes 
this is OK.  I can handle pushing the final version.

Jeff