[PATCH 2/3] aarch64: warn if the TME feature is used during assembly.

[Richard Earnshaw (foss)]

On 25/06/2026 15:58, Jan Beulich wrote:
> On 25.06.2026 16:36, Richard Earnshaw wrote:
>> --- a/gas/NEWS
>> +++ b/gas/NEWS
>> @@ -1,5 +1,9 @@
>>  -*- text -*-
>>  
>> +* Arm has obsoleted the TME feature from the architecture because no
>> +  implementations were ever produced.  The assembler will now warn if
>> +  instructions from this extension are detected during assembly.
> 
> The only reference to which targets are affected is "Arm" at the start of
> the sentence. Yet it's not arm*-*-* that this talks about. May I ask for
> clarifying this here?
> 

Fair point.  Will clarify.

>> --- a/gas/config/tc-aarch64.c
>> +++ b/gas/config/tc-aarch64.c
>> @@ -8775,7 +8775,7 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
>>      case ldstnapair_offs:
>>      case ldstpair_indexed:
>>        /* Loading/storing the base register is unpredictable if writeback.  */
>> -      if ((aarch64_get_operand_class (opnds[0].type)
>> +       if ((aarch64_get_operand_class (opnds[0].type)
>>  	   == AARCH64_OPND_CLASS_INT_REG)
>>  	  && (opnds[0].reg.regno == opnds[2].addr.base_regno
>>  	    || opnds[1].reg.regno == opnds[2].addr.base_regno)
> 
> Stray change?

Yep. Not sure how that happened, it certainly wasn't deliberate.

> 
>> @@ -8841,6 +8841,25 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
>>      }
>>  }
>>  
>> +static void
>> +warn_deprecated (aarch64_instruction *instr, char *str)
> 
> Mind me suggesting to use, in new code, proper pointer-to-const wherever
> possible?
> 
I was templating it on the function immediately above it, which is defined identically.

I'll have a look though.

>> +{
>> +  aarch64_inst *base = &instr->base;
> 
> I.e. also here then.
> 
>> --- a/opcodes/aarch64-tbl.h
>> +++ b/opcodes/aarch64-tbl.h
>> @@ -3374,7 +3374,7 @@ static const aarch64_feature_set aarch64_feature_mpamv2 =
>>  #define MEMTAG_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
>>    { NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
>>  #define _TME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
>> -  { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
>> +  { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1 | F_DEPRECATED_INSN, 0, 0, NULL }
>>  #define SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
>>    { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
>>      FLAGS | F_INVALID_IMM_SYMS_2, 0, TIED, NULL }
>> @@ -5154,10 +5154,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =
>>    CORE_INSN ("adr",  0x10000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_PCREL21), QL_ADRP, 0),
>>    CORE_INSN ("adrp", 0x90000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_ADRP), QL_ADRP, 0),
>>    /* TME Instructions.  */
>> -  _TME_INSN ("tstart", 0xd5233060, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
>> -  _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, 0, 0, OP0 (), QL_0, 0),
>> -  _TME_INSN ("ttest", 0xd5233160, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
>> -  _TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, 0, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0),
>> +  _TME_INSN ("tstart", 0xd5233060, 0xffffffe0, tme, 0, OP1 (Rd), QL_I1X, 0),
>> +  _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, tme, 0, OP0 (), QL_0, 0),
>> +  _TME_INSN ("ttest", 0xd5233160, 0xffffffe0, tme, 0, OP1 (Rd), QL_I1X, 0),
>> +  _TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, tme, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0),
>>    /* SME instructions (aliases for MSR <sysreg> operations.  */
>>    SME_INSN ("smstart", 0xd503477f, 0xffffffff, sme_start, 0, OP0 (), QL_0, F_SYS_WRITE, 0),
>>    SME_INSN ("smstop",  0xd503467f, 0xffffffff, sme_stop,  0, OP0 (), QL_0, F_SYS_WRITE, 0),
> 
> Couldn't _TME_INSN() take care of setting the (uniform) class?

Possibly, but I'm not sure it's worth it.

> 
> As per what the cover letter says, later you may mean to remove support
> altogether. Might it make sense to remove support only from the
> assembler, but keep the disassembler recognize the encodings (unless they
> are intended to be re-used for other purposes)?
> 

There never were any physical implementations of either of the features that have been dropped.  At most some software emulators might have supported it, but I'd be quite surprised if they did (and even more surpised if they still do).  There's no guarantee that the opcodes won't get re-allocated, but I don't know if there are any plans for that.

Whilst they are deprecated in the assembler, the instructions will continue to disassemble.  The sysregs (in the other patch) now disassemble as their raw encodings, without the special names - that seems to have been a deliberate choice when the F_DEPRECATED flag was implemented for sysregs.
> Jan

R.