[PATCH v3 04/13] bfd/RISC-V: Zv{b,k}* imply Zve32x

[Jiawei]

Hi Jan,

I checked this locally with current binutils using as-new/readelf.

For the ordering question, the canonical order does not seem to come 
from the
order in riscv_supported_std_z_ext[]. riscv_compare_subsets() compares Z
extensions by the character after 'z' and then by a case-insensitive suffix
comparison. For Zv* extensions, this means the current canonical order is
roughly:

zvbb, zvbc, zve32x, zvkb, zvkg, zvkn*, zvks*

The assembler/readelf tests confirm this. For example, both

-march=rv32i_zvbc_zve32x
-march=rv32i_zve32x_zvbc

are canonicalized with zvbc before zve32x, while zvkb/zvkg/zvkn*/zvks* are
placed after zve32x. So the ordering in the updated imply.d output looks
consistent with the current canonicalization rule.

However, while testing the implied-dependency change, I noticed another
possible issue. With the new implicit rows, an input such as

-march=rv32i_zvbc

is canonicalized as:

rv32i2p1_zvbc1p0_zve32x1p0

whereas explicitly specifying zve32x, for example

-march=rv32i_zvbc_zve32x

produces:

rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zvl32b1p0

So adding zve32x through the new Zv{b,k}* implication does not seem to 
trigger
the further dependencies normally implied by zve32x. This looks like it may
come from the implicit-subset processing order / single forward scan.

Therefore, I think the canonical placement of zve32x in the test is correct
for the current ordering rule, but we may need to clarify whether the 
implied
dependency should also pull in the full zve32x dependency closure.

BR,
Jiawei

On 2026/6/19 19:48, Jan Beulich wrote:
> The specification is quite explicit about this.
> ---
> Is the placement of "zve32x" after "zvbb" / "zvbc" actually correct? While
> riscv_compare_subsets() indeed does a mere strcasecmp() past "zv", it
> seems unlikely to be mere chance that Zve* come ahead of all other Zv* in
> riscv_supported_std_z_ext[].
> ---
> v3: New.
>
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1306,6 +1306,15 @@ static const struct riscv_implicit_subse
>     {"zvksc", "+zvks,+zvbc", check_implicit_always},
>     {"zvks", "+zvksed,+zvksh,+zvkb,+zvkt", check_implicit_always},
>   
> +  {"zvbc", "+zve32x", check_implicit_always},
> +  {"zvkb", "+zve32x", check_implicit_always},
> +  {"zvkg", "+zve32x", check_implicit_always},
> +  {"zvkned", "+zve32x", check_implicit_always},
> +  {"zvknha", "+zve32x", check_implicit_always},
> +  {"zvknhb", "+zve32x", check_implicit_always},
> +  {"zvksed", "+zve32x", check_implicit_always},
> +  {"zvksh", "+zve32x", check_implicit_always},
> +
>     {"sdtrig", "+zicsr", check_implicit_always},
>   
>     {"smaia", "+ssaia", check_implicit_always},
> --- a/gas/testsuite/gas/riscv/imply.d
> +++ b/gas/testsuite/gas/riscv/imply.d
> @@ -87,13 +87,13 @@ SYMBOL TABLE:
>   [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0
>   [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0
>   [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0
> -[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvbb1p0_zvkb1p0
> -[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0
> -[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvbc1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0
> -[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0
> -[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0
> -[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvbc1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0
> -[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0
> +[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvbb1p0_zve32x1p0_zvkb1p0
> +[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zve32x1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0
> +[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvbc1p0_zve32x1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0
> +[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zve32x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0
> +[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zve32x1p0_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0
> +[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvbc1p0_zve32x1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0
> +[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zve32x1p0_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0
>   [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_sdtrig1p0
>   [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_smaia1p0_ssaia1p0
>   [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_smcdeleg1p0_ssccfg1p0_sscsrind1p0