[PATCH] x86-64: Intel64 adjustments for conditional jumps
Jan Beulich
jbeulich@suse.com
Fri Jun 5 11:52:59 GMT 2026
Just like for unconditional direct JMP (and CALL), AMD and Intel differ
in their handling. Mirror JMP handling to Jcc (thus also better resolving
ambiguities outside of 64-bit mode).
---
It's really not clear why the original change was done for JMP (and CALL),
but not Jcc.
Just like the earlier change (for JMP, but not CALL), this results in the
disassembler, in -Msuffix mode, emitting insn forms the assembler wouldn't
accept.
--- a/gas/testsuite/gas/i386/opcode-suffix.d
+++ b/gas/testsuite/gas/i386/opcode-suffix.d
@@ -305,22 +305,22 @@ Disassembly of section .text:
*[0-9a-f]+: 0f 77[ ]+emms
*[0-9a-f]+: 0f 7e 90 90 90 90 90[ ]+movd[ ]+%mm2,-0x6f6f6f70\(%eax\)
*[0-9a-f]+: 0f 7f 90 90 90 90 90[ ]+movq[ ]+%mm2,-0x6f6f6f70\(%eax\)
- *[0-9a-f]+: 0f 80 90 90 90 90[ ]+jo[ ]+909094e2 <foo\+0x909094e2>
- *[0-9a-f]+: 0f 81 90 90 90 90[ ]+jno[ ]+909094e8 <foo\+0x909094e8>
- *[0-9a-f]+: 0f 82 90 90 90 90[ ]+jb[ ]+909094ee <foo\+0x909094ee>
- *[0-9a-f]+: 0f 83 90 90 90 90[ ]+jae[ ]+909094f4 <foo\+0x909094f4>
- *[0-9a-f]+: 0f 84 90 90 90 90[ ]+je[ ]+909094fa <foo\+0x909094fa>
- *[0-9a-f]+: 0f 85 90 90 90 90[ ]+jne[ ]+90909500 <foo\+0x90909500>
- *[0-9a-f]+: 0f 86 90 90 90 90[ ]+jbe[ ]+90909506 <foo\+0x90909506>
- *[0-9a-f]+: 0f 87 90 90 90 90[ ]+ja[ ]+9090950c <foo\+0x9090950c>
- *[0-9a-f]+: 0f 88 90 90 90 90[ ]+js[ ]+90909512 <foo\+0x90909512>
- *[0-9a-f]+: 0f 89 90 90 90 90[ ]+jns[ ]+90909518 <foo\+0x90909518>
- *[0-9a-f]+: 0f 8a 90 90 90 90[ ]+jp[ ]+9090951e <foo\+0x9090951e>
- *[0-9a-f]+: 0f 8b 90 90 90 90[ ]+jnp[ ]+90909524 <foo\+0x90909524>
- *[0-9a-f]+: 0f 8c 90 90 90 90[ ]+jl[ ]+9090952a <foo\+0x9090952a>
- *[0-9a-f]+: 0f 8d 90 90 90 90[ ]+jge[ ]+90909530 <foo\+0x90909530>
- *[0-9a-f]+: 0f 8e 90 90 90 90[ ]+jle[ ]+90909536 <foo\+0x90909536>
- *[0-9a-f]+: 0f 8f 90 90 90 90[ ]+jg[ ]+9090953c <foo\+0x9090953c>
+ *[0-9a-f]+: 0f 80 90 90 90 90[ ]+jol[ ]+909094e2 <foo\+0x909094e2>
+ *[0-9a-f]+: 0f 81 90 90 90 90[ ]+jnol[ ]+909094e8 <foo\+0x909094e8>
+ *[0-9a-f]+: 0f 82 90 90 90 90[ ]+jbl[ ]+909094ee <foo\+0x909094ee>
+ *[0-9a-f]+: 0f 83 90 90 90 90[ ]+jael[ ]+909094f4 <foo\+0x909094f4>
+ *[0-9a-f]+: 0f 84 90 90 90 90[ ]+jel[ ]+909094fa <foo\+0x909094fa>
+ *[0-9a-f]+: 0f 85 90 90 90 90[ ]+jnel[ ]+90909500 <foo\+0x90909500>
+ *[0-9a-f]+: 0f 86 90 90 90 90[ ]+jbel[ ]+90909506 <foo\+0x90909506>
+ *[0-9a-f]+: 0f 87 90 90 90 90[ ]+jal[ ]+9090950c <foo\+0x9090950c>
+ *[0-9a-f]+: 0f 88 90 90 90 90[ ]+jsl[ ]+90909512 <foo\+0x90909512>
+ *[0-9a-f]+: 0f 89 90 90 90 90[ ]+jnsl[ ]+90909518 <foo\+0x90909518>
+ *[0-9a-f]+: 0f 8a 90 90 90 90[ ]+jpl[ ]+9090951e <foo\+0x9090951e>
+ *[0-9a-f]+: 0f 8b 90 90 90 90[ ]+jnpl[ ]+90909524 <foo\+0x90909524>
+ *[0-9a-f]+: 0f 8c 90 90 90 90[ ]+jll[ ]+9090952a <foo\+0x9090952a>
+ *[0-9a-f]+: 0f 8d 90 90 90 90[ ]+jgel[ ]+90909530 <foo\+0x90909530>
+ *[0-9a-f]+: 0f 8e 90 90 90 90[ ]+jlel[ ]+90909536 <foo\+0x90909536>
+ *[0-9a-f]+: 0f 8f 90 90 90 90[ ]+jgl[ ]+9090953c <foo\+0x9090953c>
*[0-9a-f]+: 0f 90 80 90 90 90 90[ ]+seto[ ]+-0x6f6f6f70\(%eax\)
*[0-9a-f]+: 0f 91 80 90 90 90 90[ ]+setno[ ]+-0x6f6f6f70\(%eax\)
*[0-9a-f]+: 0f 92 80 90 90 90 90[ ]+setb[ ]+-0x6f6f6f70\(%eax\)
--- a/gas/testsuite/gas/i386/x86-64-branch-2.d
+++ b/gas/testsuite/gas/i386/x86-64-branch-2.d
@@ -17,4 +17,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 48 e8 00 00 00 00 data16 rex\.W call 18 <bar\+0xd> 14: R_X86_64_PLT32 foo-0x4
[ ]*[a-f0-9]+: 66 c3 retw
[ ]*[a-f0-9]+: 66 c2 08 00 retw \$0x8
+[ ]*[a-f0-9]+: 66 0f 84 00 00 jew 23 <bar\+0x18> 21: R_X86_64_PC16 foo-0x2
+[ ]*[a-f0-9]+: 66 48 0f 85 00 00 00 00 data16 rex\.W jne 2b <bar\+0x20> 27: R_X86_64_PLT32 foo-0x4
#pass
--- a/gas/testsuite/gas/i386/x86-64-branch-2.s
+++ b/gas/testsuite/gas/i386/x86-64-branch-2.s
@@ -10,3 +10,6 @@ bar:
retw
retw $8
+
+ data16 je foo
+ data16 rex.w jne foo
--- a/gas/testsuite/gas/i386/x86-64-branch-3.d
+++ b/gas/testsuite/gas/i386/x86-64-branch-3.d
@@ -19,4 +19,6 @@ Disassembly of section .text:
[ ]*[a-f0-9]+: 66 48 c7 f8 00 00 00 00 data16 rex\.W xbegin 29 <bar\+0x1c> 25: R_X86_64_PLT32 foo-0x4
[ ]*[a-f0-9]+: 48 ff 18 lcallq \*\(%rax\)
[ ]*[a-f0-9]+: 48 ff 29 ljmpq \*\(%rcx\)
+[ ]*[a-f0-9]+: 66 0f 84 00 00 00 00 data16 je 36 <bar\+0x29> 32: R_X86_64_PLT32 foo-0x4
+[ ]*[a-f0-9]+: 66 48 0f 85 00 00 00 00 data16 rex\.W jne 3e <bar\+0x31> 3a: R_X86_64_PLT32 foo-0x4
#pass
--- a/gas/testsuite/gas/i386/x86-64-branch-3.s
+++ b/gas/testsuite/gas/i386/x86-64-branch-3.s
@@ -13,3 +13,6 @@ bar:
lcallq *(%rax)
ljmpq *(%rcx)
+
+ data16 je foo
+ data16 rex.w jne foo
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -2405,23 +2405,23 @@ static const struct dis386 dis386_twobyt
{ PREFIX_TABLE (PREFIX_0F7E) },
{ PREFIX_TABLE (PREFIX_0F7F) },
/* 80 */
- { "joH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
- { "jnoH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
- { "jbH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
- { "jaeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
- { "jeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
- { "jneH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
- { "jbeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
- { "jaH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+ { "jo@H", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+ { "jno@H", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+ { "jb@H", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+ { "jae@H", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+ { "je@H", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+ { "jne@H", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+ { "jbe@H", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+ { "ja@H", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
/* 88 */
- { "jsH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
- { "jnsH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
- { "jpH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
- { "jnpH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
- { "jlH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
- { "jgeH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
- { "jleH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
- { "jgH", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+ { "js@H", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+ { "jns@H", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+ { "jp@H", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+ { "jnp@H", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+ { "jl@H", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+ { "jge@H", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+ { "jle@H", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+ { "jg@H", { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
/* 90 */
{ "seto", { Eb }, 0 },
{ "setno", { Eb }, 0 },
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -537,7 +537,8 @@ leave, 0xc9, x64, ImplicitStackOp|Defaul
s:8, ns:9, p:a, pe:a, np:b, po:b, l:c, nge:c, nl:d, ge:d, le:e, ng:e, nle:f, g:f>
// Conditional jumps.
-j<cc>, 0x7<cc:opc>, 0, Jump|NoSuf|BNDPrefixOk, { Disp8|Disp16|Disp32 }
+j<cc>, 0x7<cc:opc>, 0, Amd64|Jump|NoSuf|BNDPrefixOk, { Disp8|Disp16|Disp32 }
+j<cc>, 0x7<cc:opc>, x64, Intel64|Jump|NoSuf|BNDPrefixOk, { Disp8|Disp32 }
// jcxz vs. jecxz is chosen on the basis of the address size prefix.
jcxz, 0xe3, No64, JumpByte|Size16|NoSuf, { Disp8 }
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