From haochen.jiang@intel.com  Mon Jun  1 06:24:46 2026
From: haochen.jiang@intel.com (Haochen Jiang)
Date: Mon,  1 Jun 2026 14:24:46 +0800
Subject: [PATCH] x86: Support BHI_CTRL instruction
Message-ID: <20260601062446.2367458-1-haochen.jiang@intel.com>

Hi all,

The following patch aimed to add BHI_CTRL. The ISA has been published in a
separate tech paper last year and still missing its assembler/disassembler
support.

One tricky thing is that it utilized part of the nops encoding and we need
to keep the same behavior for the not touched one, i.e., repz nop. That is
why I added a Fixup for now since I did not have a better idea for that.
Discussions are welcomed on this.

Ok for trunk?

Thx,
Haochen

---

BHI_CTRL is an ISA with only one instruction ibhf. The following tech paper
is published in May, 2025:

https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/branch-history-injection.html#ibhf

As shown in the paper, The encoding is F3 48 0F 1E F8.

I added a Fixup for disassembler since we need to keep the same behavior
for "repz nop" encodings.

gas/ChangeLog:

	* NEWS: Mention BHI_CTRL.
	* config/tc-i386.c: Add .bhi_ctrl.
	* testsuite/gas/i386/x86-64.exp: Add BHI_CTRL tests.
	* testsuite/gas/i386/x86-64-bhi-ctrl-intel.d: New test.
	* testsuite/gas/i386/x86-64-bhi-ctrl.d: Ditto.
	* testsuite/gas/i386/x86-64-bhi-ctrl.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c: (RM_0F1E_P_1_MOD_3_REG_7): Adjust for ibhf.
	(IBHF_Fixup): New. Revert mnemonic back to repz nop for ~REX_W.
	* i386-gen.c: (isa_dependencies): Add BHI_CTRL.
	(cpu_flags): Ditto.
	* i386-opc.h (enum i386_cpu): Ditto.
	(i386_cpu_flags): Ditto.
	* i386-opc.tbl: Add BHI_CTRL instruction.
	* i386-init.h: Regenerated.
	* i386-mnem.h: Ditto.
	* i386-tbl.h: Ditto.
---
 gas/NEWS                                      |    2 +
 gas/config/tc-i386.c                          |    1 +
 .../gas/i386/x86-64-bhi-ctrl-intel.d          |   12 +
 gas/testsuite/gas/i386/x86-64-bhi-ctrl.d      |   10 +
 gas/testsuite/gas/i386/x86-64-bhi-ctrl.s      |    9 +
 gas/testsuite/gas/i386/x86-64.exp             |    2 +
 opcodes/i386-dis.c                            |   21 +-
 opcodes/i386-gen.c                            |    3 +
 opcodes/i386-init.h                           |  995 ++++---
 opcodes/i386-mnem.h                           | 2639 +++++++++--------
 opcodes/i386-opc.h                            |    3 +
 opcodes/i386-opc.tbl                          |    6 +
 opcodes/i386-tbl.h                            | 1241 ++++----
 13 files changed, 2516 insertions(+), 2428 deletions(-)
 create mode 100644 gas/testsuite/gas/i386/x86-64-bhi-ctrl-intel.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-bhi-ctrl.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-bhi-ctrl.s

diff --git a/gas/NEWS b/gas/NEWS
index e384d1135c0..0687fd4adfc 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
 -*- text -*-
 
+* Add support for the x86 BHI_CTRL instruction.
+
 Changes in 2.46:
 
 * Add support for AMD Zen6 processor.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 365c2ee95f5..b67606d13ad 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1260,6 +1260,7 @@ static const arch_entry cpu_arch[] =
   SUBARCH (padlockphe2, PADLOCKPHE2, PADLOCKPHE2, false),
   SUBARCH (padlockxmodx, PADLOCKXMODX, PADLOCKXMODX, false),
   SUBARCH (movrs, MOVRS, MOVRS, false),
+  SUBARCH (bhi_ctrl, BHI_CTRL, BHI_CTRL, false),
 };
 
 #undef SUBARCH
diff --git a/gas/testsuite/gas/i386/x86-64-bhi-ctrl-intel.d b/gas/testsuite/gas/i386/x86-64-bhi-ctrl-intel.d
new file mode 100644
index 00000000000..adc9f87a62a
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-bhi-ctrl-intel.d
@@ -0,0 +1,12 @@
+#objdump: -dw
+#name: x86_64 BHI_CTRL insns (Intel disassembly)
+#source: x86-64-bhi-ctrl.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+#...
+[a-f0-9]+ <_intel>:
+\s*[a-f0-9]+:\s*f3 48 0f 1e f8\s+ibhf
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-bhi-ctrl.d b/gas/testsuite/gas/i386/x86-64-bhi-ctrl.d
new file mode 100644
index 00000000000..164ae5e8839
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-bhi-ctrl.d
@@ -0,0 +1,10 @@
+#objdump: -dw
+#name: x86_64 BHI_CTRL insns
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*f3 48 0f 1e f8\s+ibhf
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-bhi-ctrl.s b/gas/testsuite/gas/i386/x86-64-bhi-ctrl.s
new file mode 100644
index 00000000000..41beb4210d6
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-bhi-ctrl.s
@@ -0,0 +1,9 @@
+# Check 64bit BHI_CTRL instructions
+
+	.text
+_start:
+	ibhf
+
+_intel:
+	.intel_syntax noprefix
+	ibhf
diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp
index 8ddf05481a5..cb2334fbe75 100644
--- a/gas/testsuite/gas/i386/x86-64.exp
+++ b/gas/testsuite/gas/i386/x86-64.exp
@@ -550,6 +550,8 @@ run_dump_test "x86-64-movrs-avx10_2-512"
 run_dump_test "x86-64-movrs-avx10_2-512-intel"
 run_dump_test "x86-64-movrs-avx10_2-256"
 run_dump_test "x86-64-movrs-avx10_2-256-intel"
+run_dump_test "x86-64-bhi-ctrl"
+run_dump_test "x86-64-bhi-ctrl-intel"
 run_dump_test "x86-64-clzero"
 run_dump_test "x86-64-mwaitx-bdver4"
 run_list_test "x86-64-mwaitx-reg"
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index db1e4f7a7d5..ecf74840eee 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -109,6 +109,7 @@ static bool PREFETCHI_Fixup (instr_info *, int, int);
 static bool PUSH2_POP2_Fixup (instr_info *, int, int);
 static bool JMPABS_Fixup (instr_info *, int, int);
 static bool CFCMOV_Fixup (instr_info *, int, int);
+static bool IBHF_Fixup (instr_info *, int, int);
 
 static void ATTRIBUTE_PRINTF_3 i386_dis_printf (const disassemble_info *,
 						enum disassembler_style,
@@ -8750,7 +8751,7 @@ static const struct dis386 rm_table[][8] = {
   },
   {
     /* RM_0F1E_P_1_MOD_3_REG_7 */
-    { "nopQ",		{ Ev }, PREFIX_IGNORED },
+    { "ibhf",		{ IBHF_Fixup }, 0 },
     { "nopQ",		{ Ev }, PREFIX_IGNORED },
     { "endbr64",	{ Skip_MODRM }, 0 },
     { "endbr32",	{ Skip_MODRM }, 0 },
@@ -14671,3 +14672,21 @@ CFCMOV_Fixup (instr_info *ins, int opnd, int sizeflag)
     return OP_G (ins, v_mode, sizeflag);
   return OP_E (ins, v_mode, sizeflag);
 }
+
+static bool
+IBHF_Fixup (instr_info *ins, int bytemode, int sizeflag)
+{
+  if (!(ins->rex & REX_W))
+    {
+      ins->mnemonicendp = stpcpy (ins->obuf, "repz nop");
+      return OP_E (ins, v_mode, sizeflag);
+    }
+  else
+    {
+      USED_REX (REX_W);
+      MODRM_CHECK;
+      ins->codep++;
+      ins->has_skipped_modrm = true;
+      return true;
+    }
+}
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index be580d48a18..7033517e777 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -319,6 +319,8 @@ static const dependency isa_dependencies[] =
     "PadLock" },
   { "PadLockXMODX",
     "PadLock" },
+  { "BHI_CTRL",
+    "64" },
 };
 
 /* This array is populated as process_i386_initializers() walks cpu_flags[].  */
@@ -451,6 +453,7 @@ static bitfield cpu_flags[] =
   BITFIELD (APX_F),
   BITFIELD (AVX10_2),
   BITFIELD (MOVRS),
+  BITFIELD (BHI_CTRL),
   BITFIELD (MWAITX),
   BITFIELD (CLZERO),
   BITFIELD (OSPKE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 54038f90761..97eaf085dbd 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -241,6 +241,8 @@ enum i386_cpu
   CpuMSR_IMM,
   /* Intel MOVRS Instructions support required.  */
   CpuMOVRS,
+  /* Intel BHI_CTRL instruction support required.  */
+  CpuBHI_CTRL,
   /* mwaitx instruction required */
   CpuMWAITX,
   /* Clzero instruction required */
@@ -523,6 +525,7 @@ typedef union i386_cpu_flags
       unsigned int cpuuser_msr:1;
       unsigned int cpumsr_imm:1;
       unsigned int cpumovrs:1;
+      unsigned int cpubhi_ctrl:1;
       unsigned int cpumwaitx:1;
       unsigned int cpuclzero:1;
       unsigned int cpuospke:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 5797a634de3..827d4b54906 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3630,3 +3630,9 @@ vmovrs<bw>, 0xf26f, AVX10_2&MOVRS&x64, Modrm|Masking|Map5|<bw:vexw>|Disp8ShiftVL
 vmovrs<dq>, 0xf36f, AVX10_2&MOVRS&x64, Modrm|Masking|Map5|<dq:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { Xmmword|Ymmword|Zmmword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
 
 // MOVRS instructions end.
+
+// BHI_CTRL insructions.
+
+ibhf, 0xf30f1ef8, BHI_CTRL, NoSuf|Size64, {}
+
+// BHI_CTRL insructions end.
-- 
2.31.1


From gopi@sankhya.com  Mon Jun  1 06:30:16 2026
From: gopi@sankhya.com (Gopi Kumar Bulusu)
Date: Mon, 1 Jun 2026 12:00:16 +0530
Subject: [PATCH] gdb/MicroBlaze: Add support for native linux gdb
In-Reply-To: <6838cb4f-838c-49ee-bb08-5b16b8eea8c5@simark.ca>
References: <CAL1P33wvSyEkqa5KC8QH3KRN1hGGn2-H6sE59rRjsrLibprvKg@mail.gmail.com>
 <874ijq5knu.fsf@tromey.com> <6838cb4f-838c-49ee-bb08-5b16b8eea8c5@simark.ca>
Message-ID: <CAL1P33y6tENo=gaf9-5GVQE-YuTruLN4ny=jNtbYrP1YwR8Cjw@mail.gmail.com>

On Fri, May 29, 2026 at 8:31?PM Simon Marchi <simark@simark.ca> wrote:
>
> On 5/29/26 10:56 AM, Tom Tromey wrote:
> >>>>>> Gopi Kumar Bulusu <gopi@sankhya.com> writes:
> >
> >> Attached is a patch to add native linux support for gdb including
> >> cache target support.
> >
> > Thanks for the patch.
> >
> > I read through it and have some nits.  There's nothing very serious
> > except this:
> >
> >> The original sources for the patch come from Xilinx/AMD Yocto git
> >> repository (2025.2)
> >
> > Who wrote them and are they covered by the copyright assignment?
> >
> > This is the most important consideration, the patch can't land without
> > this being clear.
>
> This was the situation for the previous gdbserver submission:
>
> https://inbox.sourceware.org/gdb-patches/dd63d676-f390-460a-8b80-55df3285575a@simark.ca/
>
> Gopi, is the situation the same for this code?

Thank you Simon.  Yes, it is. This work is being done under a contract
with Xilinx/AMD.

dhanyavaadaaha
gopi

>
> Simon

From gopi@sankhya.com  Mon Jun  1 06:38:46 2026
From: gopi@sankhya.com (Gopi Kumar Bulusu)
Date: Mon, 1 Jun 2026 12:08:46 +0530
Subject: [PATCH] gdb/MicroBlaze: Add support for native linux gdb
In-Reply-To: <874ijq5knu.fsf@tromey.com>
References: <CAL1P33wvSyEkqa5KC8QH3KRN1hGGn2-H6sE59rRjsrLibprvKg@mail.gmail.com>
 <874ijq5knu.fsf@tromey.com>
Message-ID: <CAL1P33xHUSaXLnKbph89ev0-Fr+izVcAEBU62sUPJ8ujHKdjbw@mail.gmail.com>

On Fri, May 29, 2026 at 8:26?PM Tom Tromey <tom@tromey.com> wrote:
>
> >>>>> Gopi Kumar Bulusu <gopi@sankhya.com> writes:
>
> > Attached is a patch to add native linux support for gdb including
> > cache target support.
>
> Thanks for the patch.
>
> I read through it and have some nits.  There's nothing very serious
> except this:
>
> > The original sources for the patch come from Xilinx/AMD Yocto git
> > repository (2025.2)
>
> Who wrote them and are they covered by the copyright assignment?
>
> This is the most important consideration, the patch can't land without
> this being clear.

This work is being performed under a contract with Xilinx/AMD as
confirmed in a different response to
Simon and therefore covered by the copyright assignment.

I will make the changes as described below and retest.

Approved for commit ?

dhanyavaadaaha
gopi

>
> > From a3328b4cdfc58783b5f290f22255b36e26a6fb14 Mon Sep 17 00:00:00 2001
> > From: Gopi Kumar Bulusu <gopi@sankhya.com>
> > Date: Thu, 7 May 2026 17:47:40 +0530
> > Subject: [PATCH] gdb/MicroBlaze: Add support for native linux gdb
>
> It's best to just git send-email rather than using an attachment.
>
> >     bfd/ChangeLog:
>
> >     * elf32-microblaze.c (microblaze_elf_grok_prstatus): New function.
> >       (microblaze_elf_grok_psinfo): Likewise.
>
> >     gdb/ChangeLog:
>
> >     * Makefile.in (HFILES_NO_SRCDIR): Add microblaze-linux-tdep.h
> >       ALLDEPFILES: Add microblaze-linux-nat.c
>
> gdb doesn't use ChangeLogs any more and this text should all be removed.
>
> > +#define MICROBLAZE_TARGET_HAS_GETREGS 0
> > +#define MICROBLAZE_TARGET_HAS_SETREGS 0
>
> This seems weird:
>
> > +/* Wrapper function around ptrace.  */
> > +
> > +static void
> > +fetch_target_gp_regs (int tid, elf_gregset_t *gregs)
> > +{
> > +  elf_greg_t *gregp = *gregs;
> > +
> > +#if MICROBLAZE_TARGET_HAS_GETREGS
> > +  if (ptrace (PTRACE_GETREGS, tid, 0, (long) gregp) < 0)
> > +    {
> > +      perror_with_name (_("Couldn't get registers"));
> > +      return;
> > +    }
> > +#error "this configuration did not work during testing"
>
> Normally we don't put new dead code into gdb.
>
> I think this and the defines could just be replaced with a comment
> explaining that PTRACE_GETREGS doesn't work on this platform.
>
> > +++ b/gdb/microblaze-linux-tdep.h
> > @@ -0,0 +1,24 @@
> > +/* Target-dependent code for GNU/Linux on MicroBlaze.
> > +
> > +   Copyright (C) 2021-2026 Free Software Foundation, Inc.
> > +
> > +   This file is part of GDB.
> > +
> > +   This program is free software; you can redistribute it and/or modify
> > +   it under the terms of the GNU General Public License as published by
> > +   the Free Software Foundation; either version 3 of the License, or
> > +   (at your option) any later version.
> > +
> > +   This program is distributed in the hope that it will be useful,
> > +   but WITHOUT ANY WARRANTY; without even the implied warranty of
> > +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > +   GNU General Public License for more details.
> > +
> > +   You should have received a copy of the GNU General Public License
> > +   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
> > +#ifndef MICROBLAZE_LINUX_TDEP_H
> > +#define MICROBLAZE_LINUX_TDEP_H
> > + /* Target descriptions.  */
> > + extern struct target_desc *tdesc_microblaze_linux;
>
> Blank line between the #define and the comment.
>
> Also this define should have a slightly different name, see
> check-include-guards.py.
>
> >         non_stack_instruction_found = 0;
> > +          cache->register_offsets[rd] = -imm;
> >         continue;
>
> Indentation looks wrong, probably not using tabs.
>
> > @@ -399,8 +400,7 @@ microblaze_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
> >      {
> >        sal = find_sal_for_pc (func_start, 0);
>
> > -      if (sal.end < func_end
> > -       && start_pc <= sal.end)
> > +      if (sal.line != 0 && sal.end <= func_end  && start_pc <= sal.end)
> >       start_pc = sal.end;
>
> No objection from me but this seems somewhat unrelated.
>
>
> >    /* Call for side effects.  */
> > -  get_frame_func (next_frame);
> > +  cache->pc = get_frame_func (next_frame);
>
> Please remove that comment as it is now wrong.
>
> > +  if (regnum == MICROBLAZE_SP_REGNUM)
> > +        regnum = 1;
>
> Wrong indentation.
>
> > +  if (regnum == -1) {
> > +    int i;
> > +
> > +    for (i = 0; i < MICROBLAZE_REDR_REGNUM; i++) {
> > +      regcache->raw_supply (i, regs + i * MICROBLAZE_REGISTER_SIZE);
> > +    }
>
> Wrong brace placement in this hunk.
>
> > +  cb (".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL,
> > +      cb_data);
>
> Normally in new code we're using 'nullptr' now.  Best would be to go
> through the whole patch and check for this.  You don't have to fix
> pre-existing code that is using NULL though.
>
> >    gdbarch *gdbarch
> >      = gdbarch_alloc (&info, gdbarch_tdep_up (new microblaze_gdbarch_tdep));
>
> > +  microblaze_gdbarch_tdep *tdep
> > +    = gdbarch_tdep<microblaze_gdbarch_tdep> (gdbarch);
> > +
> > +  tdep->gregset = NULL;
> > +  tdep->sizeof_gregset = 0;
> > +  tdep->fpregset = NULL;
> > +  tdep->sizeof_fpregset = 0;
>
> Here it would be better to just add inline initializers to the new
> fields in microblaze_gdbarch_tdep.  Then they'll automatically be
> initialized by the 'new'.
>
> Tom

From amodra@gmail.com  Mon Jun  1 07:27:34 2026
From: amodra@gmail.com (Alan Modra)
Date: Mon, 1 Jun 2026 16:57:34 +0930
Subject: buffer overflow in parse_stab_array_type
Message-ID: <ah00Zp_R1A6q4bNQ@squeak.grove.modra.org>

Fix oss-fuzz induced damage.

	stabs.c (parse_stab_type): Don't access beyond end of stab
	with bad type.
	(parse_stab_array_type): Don't duplicate "bad stab" message.

diff --git a/binutils/stabs.c b/binutils/stabs.c
index 81068a4bf7c..27d49376b97 100644
--- a/binutils/stabs.c
+++ b/binutils/stabs.c
@@ -1293,6 +1293,12 @@ parse_stab_type (void *                dhandle,
 	}
     }
 
+  if (*pp >= p_end)
+    {
+      bad_stab (orig);
+      return DEBUG_TYPE_NULL;
+    }
+
   descriptor = **pp;
   ++*pp;
 
@@ -3219,11 +3225,7 @@ parse_stab_array_type (void *dhandle,
     {
       index_type = debug_find_named_type (dhandle, "int");
       if (index_type == DEBUG_TYPE_NULL)
-	{
-	  index_type = debug_make_int_type (dhandle, 4, false);
-	  if (index_type == DEBUG_TYPE_NULL)
-	    return DEBUG_TYPE_NULL;
-	}
+	index_type = debug_make_int_type (dhandle, 4, false);
       *pp = p;
     }
   else
@@ -3231,6 +3233,8 @@ parse_stab_array_type (void *dhandle,
       index_type = parse_stab_type (dhandle, info, (const char *) NULL, pp,
 				    (debug_type **) NULL, p_end);
     }
+  if (index_type == DEBUG_TYPE_NULL)
+    return DEBUG_TYPE_NULL;
 
   if (**pp != ';')
     {

-- 
Alan Modra

From ktkachov@nvidia.com  Mon Jun  1 09:44:45 2026
From: ktkachov@nvidia.com (Kyrylo Tkachov)
Date: Mon, 1 Jun 2026 09:44:45 +0000
Subject: [PATCH] AArch64 gas: Block section relative symbols in GOT
 relocations [PR30788]
In-Reply-To: <PAWPR08MB8982EA96A85A9846678CCFB5830B2@PAWPR08MB8982.eurprd08.prod.outlook.com>
References: <PAWPR08MB8982EA96A85A9846678CCFB5830B2@PAWPR08MB8982.eurprd08.prod.outlook.com>
Message-ID: <B8AA39BD-C3A7-40D4-A26B-6E12ED0DD7EE@nvidia.com>



> On 26 May 2026, at 20:37, Wilco Dijkstra <Wilco.Dijkstra@arm.com> wrote:
> 
> 
> By default, GAS changes GOT relocations of local symbols into section relative.
> This is incorrect since GOT relocations do not support offsets.  Update
> aarch64_fix_adjustable() to explicitly disallow this for GOT relocations.
> This fixes PR30788.

Thanks for the patch.
I believe this patch should also address a regression we saw with GCC?s recent -mcmodel=large changes.
So I?d like to see it in trunk and on the release branch if possible so users can pick it up.

Kyrill

> 
> ---
> 
> diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
> index fb58bcca9b1059e5d4d831a0a8ea9a33d05deaba..9632a5b2a015b38f2d35fa2f569093b9b52790f9 100644
> --- a/gas/config/tc-aarch64.c
> +++ b/gas/config/tc-aarch64.c
> @@ -10389,6 +10389,19 @@ aarch64_fix_adjustable (fixS *fixp)
>   if (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION)
>     return false;
> 
> +  /* GOT relocations cannot have an offset or use section-relative symbols.  */
> +  if (fixp->fx_r_type == BFD_RELOC_AARCH64_ADR_GOT_PAGE
> +      || fixp->fx_r_type == BFD_RELOC_AARCH64_GOT_LD_PREL19
> +      || fixp->fx_r_type == BFD_RELOC_AARCH64_LD_GOT_LO12_NC
> +      || fixp->fx_r_type == BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
> +      || fixp->fx_r_type == BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
> +      || fixp->fx_r_type == BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
> +      || fixp->fx_r_type == BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
> +      || fixp->fx_r_type == BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
> +      || fixp->fx_r_type == BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
> +      || fixp->fx_r_type == BFD_RELOC_AARCH64_MOVW_GOTOFF_G1)
> +    return false;
> +
>   return true;
> }
> 
> diff --git a/gas/testsuite/gas/aarch64/reloc-insn.d b/gas/testsuite/gas/aarch64/reloc-insn.d
> index dc73bd2832a2e802fa93b99f733752ee453d9826..3fcb28dce3c2b864643f5a189b8cd4fadb91b64f 100644
> --- a/gas/testsuite/gas/aarch64/reloc-insn.d
> +++ b/gas/testsuite/gas/aarch64/reloc-insn.d
> @@ -159,9 +159,9 @@ Disassembly of section \.text:
>  18c: 39400001 ldrb w1, \[x0\]
>  190: d65f03c0 ret
>  194: f94001bc ldr x28, \[x13\]
> - 194: R_AARCH64_LD64_GOTPAGE_LO15 \.data
> + 194: R_AARCH64_LD64_GOTPAGE_LO15 dummy
>  198: f9400000 ldr x0, \[x0\]
> - 198: R_AARCH64_LD64_GOTOFF_LO15 .data
> + 198: R_AARCH64_LD64_GOTOFF_LO15 dummy
> 
> 000000000000019c <llit>:
>  19c: deadf00d \.word 0xdeadf00d
> 


From amodra@gmail.com  Mon Jun  1 10:39:11 2026
From: amodra@gmail.com (Alan Modra)
Date: Mon, 1 Jun 2026 20:09:11 +0930
Subject: [PATCH 3/3] ld/testsuite: Add comprehensive PE COFF weak
 external tests
In-Reply-To: <20260530191522.57144-4-peter0x44@disroot.org>
References: <20260530191522.57144-1-peter0x44@disroot.org>
 <20260530191522.57144-4-peter0x44@disroot.org>
Message-ID: <ah1hT8vkse-L4QqG@squeak.grove.modra.org>

On Sat, May 30, 2026 at 03:15:22PM -0400, Peter Damianov wrote:
> Add tests covering the full matrix of weak/strong symbol interactions
> for PE COFF weak externals, based on testcases by Martin Storsjo.

On a cross build of x86_64-w64-mingw32 from x86_64-linux with gcc
13.2.0-6ubuntu1+26.1 installed, I see
x86_64-w64-mingw32  +FAIL: weak external: strong undef + weak def (link)
x86_64-w64-mingw32  +FAIL: weak external: duplicate weak defs (link)

-- 
Alan Modra

From evgeny.karpov@arm.com  Mon Jun  1 17:02:53 2026
From: evgeny.karpov@arm.com (Evgeny Karpov)
Date: Mon, 1 Jun 2026 19:02:53 +0200
Subject: [PATCH] ld: Drop pep-dll-{aarch64,x86_64}.c
In-Reply-To: <20260531141745.1339572-1-jon.turney@dronecode.org.uk>
References: <20260531141745.1339572-1-jon.turney@dronecode.org.uk>
Message-ID: <ah27PbY5dE5Rn9XK@arm.com>

On Sun, 31 May 2026, Jon Turney wrote:
> I can't see anything in pe{,p}-dll.c which depends on the
> COFF_WITH_peAArch64 or COFF_WITH_pex64 defines, so just remove all this.

> Cc'ed Evgeny (Hi!), because I think this crosses with not-yet-submitted
> patches of his which do add some code conditional on COFF_WITH_peAArch64.
> 
> I imagine it's possible in code which *does* need to depend on the
> output target to replace build time checks of COFF_WITH_pe{AArch64,x64}
> with a runtime check of the output architecture (via
> pe_details->pe_arch?).

Hi Jon, 

Thank you for noticing not-yet-upstreamed patches that introduce 
COFF_WITH_peAArch64 in pe-dll.c. The change looks reasonable, and impacted
patches will be updated with necessary declarations.

LGTM for aarch64-w64-mingw32 target.

Regards,
Evgeny
 

From eager@eagerm.com  Tue Jun  2 00:28:19 2026
From: eager@eagerm.com (Michael Eager)
Date: Mon, 1 Jun 2026 17:28:19 -0700
Subject: [PATCH] gdb/MicroBlaze: Add support for native linux gdb
In-Reply-To: <CAL1P33xHUSaXLnKbph89ev0-Fr+izVcAEBU62sUPJ8ujHKdjbw@mail.gmail.com>
References: <CAL1P33wvSyEkqa5KC8QH3KRN1hGGn2-H6sE59rRjsrLibprvKg@mail.gmail.com>
 <874ijq5knu.fsf@tromey.com>
 <CAL1P33xHUSaXLnKbph89ev0-Fr+izVcAEBU62sUPJ8ujHKdjbw@mail.gmail.com>
Message-ID: <e8675182-6e41-431b-8f1a-4c867ab38e33@eagerm.com>

Please post an updated patch for review.

On 5/31/26 11:38 PM, Gopi Kumar Bulusu wrote:
> On Fri, May 29, 2026 at 8:26?PM Tom Tromey <tom@tromey.com> wrote:
>>
>>>>>>> Gopi Kumar Bulusu <gopi@sankhya.com> writes:
>>
>>> Attached is a patch to add native linux support for gdb including
>>> cache target support.
>>
>> Thanks for the patch.
>>
>> I read through it and have some nits.  There's nothing very serious
>> except this:
>>
>>> The original sources for the patch come from Xilinx/AMD Yocto git
>>> repository (2025.2)
>>
>> Who wrote them and are they covered by the copyright assignment?
>>
>> This is the most important consideration, the patch can't land without
>> this being clear.
> 
> This work is being performed under a contract with Xilinx/AMD as
> confirmed in a different response to
> Simon and therefore covered by the copyright assignment.
> 
> I will make the changes as described below and retest.
> 
> Approved for commit ?
> 
> dhanyavaadaaha
> gopi
> 
>>
>>>  From a3328b4cdfc58783b5f290f22255b36e26a6fb14 Mon Sep 17 00:00:00 2001
>>> From: Gopi Kumar Bulusu <gopi@sankhya.com>
>>> Date: Thu, 7 May 2026 17:47:40 +0530
>>> Subject: [PATCH] gdb/MicroBlaze: Add support for native linux gdb
>>
>> It's best to just git send-email rather than using an attachment.
>>
>>>      bfd/ChangeLog:
>>
>>>      * elf32-microblaze.c (microblaze_elf_grok_prstatus): New function.
>>>        (microblaze_elf_grok_psinfo): Likewise.
>>
>>>      gdb/ChangeLog:
>>
>>>      * Makefile.in (HFILES_NO_SRCDIR): Add microblaze-linux-tdep.h
>>>        ALLDEPFILES: Add microblaze-linux-nat.c
>>
>> gdb doesn't use ChangeLogs any more and this text should all be removed.
>>
>>> +#define MICROBLAZE_TARGET_HAS_GETREGS 0
>>> +#define MICROBLAZE_TARGET_HAS_SETREGS 0
>>
>> This seems weird:
>>
>>> +/* Wrapper function around ptrace.  */
>>> +
>>> +static void
>>> +fetch_target_gp_regs (int tid, elf_gregset_t *gregs)
>>> +{
>>> +  elf_greg_t *gregp = *gregs;
>>> +
>>> +#if MICROBLAZE_TARGET_HAS_GETREGS
>>> +  if (ptrace (PTRACE_GETREGS, tid, 0, (long) gregp) < 0)
>>> +    {
>>> +      perror_with_name (_("Couldn't get registers"));
>>> +      return;
>>> +    }
>>> +#error "this configuration did not work during testing"
>>
>> Normally we don't put new dead code into gdb.
>>
>> I think this and the defines could just be replaced with a comment
>> explaining that PTRACE_GETREGS doesn't work on this platform.
>>
>>> +++ b/gdb/microblaze-linux-tdep.h
>>> @@ -0,0 +1,24 @@
>>> +/* Target-dependent code for GNU/Linux on MicroBlaze.
>>> +
>>> +   Copyright (C) 2021-2026 Free Software Foundation, Inc.
>>> +
>>> +   This file is part of GDB.
>>> +
>>> +   This program is free software; you can redistribute it and/or modify
>>> +   it under the terms of the GNU General Public License as published by
>>> +   the Free Software Foundation; either version 3 of the License, or
>>> +   (at your option) any later version.
>>> +
>>> +   This program is distributed in the hope that it will be useful,
>>> +   but WITHOUT ANY WARRANTY; without even the implied warranty of
>>> +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>> +   GNU General Public License for more details.
>>> +
>>> +   You should have received a copy of the GNU General Public License
>>> +   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
>>> +#ifndef MICROBLAZE_LINUX_TDEP_H
>>> +#define MICROBLAZE_LINUX_TDEP_H
>>> + /* Target descriptions.  */
>>> + extern struct target_desc *tdesc_microblaze_linux;
>>
>> Blank line between the #define and the comment.
>>
>> Also this define should have a slightly different name, see
>> check-include-guards.py.
>>
>>>          non_stack_instruction_found = 0;
>>> +          cache->register_offsets[rd] = -imm;
>>>          continue;
>>
>> Indentation looks wrong, probably not using tabs.
>>
>>> @@ -399,8 +400,7 @@ microblaze_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
>>>       {
>>>         sal = find_sal_for_pc (func_start, 0);
>>
>>> -      if (sal.end < func_end
>>> -       && start_pc <= sal.end)
>>> +      if (sal.line != 0 && sal.end <= func_end  && start_pc <= sal.end)
>>>        start_pc = sal.end;
>>
>> No objection from me but this seems somewhat unrelated.
>>
>>
>>>     /* Call for side effects.  */
>>> -  get_frame_func (next_frame);
>>> +  cache->pc = get_frame_func (next_frame);
>>
>> Please remove that comment as it is now wrong.
>>
>>> +  if (regnum == MICROBLAZE_SP_REGNUM)
>>> +        regnum = 1;
>>
>> Wrong indentation.
>>
>>> +  if (regnum == -1) {
>>> +    int i;
>>> +
>>> +    for (i = 0; i < MICROBLAZE_REDR_REGNUM; i++) {
>>> +      regcache->raw_supply (i, regs + i * MICROBLAZE_REGISTER_SIZE);
>>> +    }
>>
>> Wrong brace placement in this hunk.
>>
>>> +  cb (".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL,
>>> +      cb_data);
>>
>> Normally in new code we're using 'nullptr' now.  Best would be to go
>> through the whole patch and check for this.  You don't have to fix
>> pre-existing code that is using NULL though.
>>
>>>     gdbarch *gdbarch
>>>       = gdbarch_alloc (&info, gdbarch_tdep_up (new microblaze_gdbarch_tdep));
>>
>>> +  microblaze_gdbarch_tdep *tdep
>>> +    = gdbarch_tdep<microblaze_gdbarch_tdep> (gdbarch);
>>> +
>>> +  tdep->gregset = NULL;
>>> +  tdep->sizeof_gregset = 0;
>>> +  tdep->fpregset = NULL;
>>> +  tdep->sizeof_fpregset = 0;
>>
>> Here it would be better to just add inline initializers to the new
>> fields in microblaze_gdbarch_tdep.  Then they'll automatically be
>> initialized by the 'new'.
>>
>> Tom
> 


From gopi@sankhya.com  Tue Jun  2 05:05:00 2026
From: gopi@sankhya.com (Gopi Kumar Bulusu)
Date: Tue, 2 Jun 2026 10:35:00 +0530
Subject: [PATCH v2] gdb/MicroBlaze: Add support for native linux gdb
In-Reply-To: <e8675182-6e41-431b-8f1a-4c867ab38e33@eagerm.com>
References: <CAL1P33wvSyEkqa5KC8QH3KRN1hGGn2-H6sE59rRjsrLibprvKg@mail.gmail.com>
 <874ijq5knu.fsf@tromey.com>
 <CAL1P33xHUSaXLnKbph89ev0-Fr+izVcAEBU62sUPJ8ujHKdjbw@mail.gmail.com>
 <e8675182-6e41-431b-8f1a-4c867ab38e33@eagerm.com>
Message-ID: <CAL1P33xEtR7-N8XCN61oCrx-WPmgHJj1qJ7x3ksiLivdr_J9FA@mail.gmail.com>

namaskaaram

Attached is the updated patch. All the changes suggested on PATCH v1
have been made and tested.

I did not remove the (sal.line != 0) check as it seemed trivial.
However, I can make that a separate patch if necessary.

Our sysadm In the process of setting up a git compatible email - the
process may take more time; until then appreciate your patience with
the attachments.

Important Note:

1) gdb appears to have an elaborate scheme to handle C++ exceptions
and "tunnel" them through exception unaware C code. This code is with
readline. Anytime
an error is discovered (even a syntax error) by a module,
gdb_exception_error() thrown is tunneled through readline using the
TRY_SJLJ/CATCH_SJLJ macros
implemented using setjmp/longjmp.

2) There is an issue that I came across while testing; native gdb goes
into an infinite loop when handling errors. I analyzed it and found it
to be an obvious glibc
sysdeps/unix/sysv/linux/microblaze/____longjmp_chk.S issue and
reported it to AMD. It is possible I missed out a glibc patch; At this
time - this is not a gdb issue.

3) Plan to follow through [2] and ensure a gcc/glibc defect report is
created if needed.

dhanyavaadaaha
gopi

On Tue, Jun 2, 2026 at 5:58?AM Michael Eager <eager@eagerm.com> wrote:
>
> Please post an updated patch for review.
>
> On 5/31/26 11:38 PM, Gopi Kumar Bulusu wrote:
> > On Fri, May 29, 2026 at 8:26?PM Tom Tromey <tom@tromey.com> wrote:
> >>
> >>>>>>> Gopi Kumar Bulusu <gopi@sankhya.com> writes:
> >>
> >>> Attached is a patch to add native linux support for gdb including
> >>> cache target support..
> >>
> >> Thanks for the patch.
> >>
> >> I read through it and have some nits.  There's nothing very serious
> >> except this:
> >>
> >>> The original sources for the patch come from Xilinx/AMD Yocto git
> >>> repository (2025.2)
> >>
> >> Who wrote them and are they covered by the copyright assignment?
> >>
> >> This is the most important consideration, the patch can't land without
> >> this being clear.
> >
> > This work is being performed under a contract with Xilinx/AMD as
> > confirmed in a different response to
> > Simon and therefore covered by the copyright assignment.
> >
> > I will make the changes as described below and retest.
> >
> > Approved for commit ?
> >
> > dhanyavaadaaha
> > gopi
> >
> >>
> >>>  From a3328b4cdfc58783b5f290f22255b36e26a6fb14 Mon Sep 17 00:00:00 2001
> >>> From: Gopi Kumar Bulusu <gopi@sankhya.com>
> >>> Date: Thu, 7 May 2026 17:47:40 +0530
> >>> Subject: [PATCH] gdb/MicroBlaze: Add support for native linux gdb
> >>
> >> It's best to just git send-email rather than using an attachment.
> >>
> >>>      bfd/ChangeLog:
> >>
> >>>      * elf32-microblaze.c (microblaze_elf_grok_prstatus): New function.
> >>>        (microblaze_elf_grok_psinfo): Likewise.
> >>
> >>>      gdb/ChangeLog:
> >>
> >>>      * Makefile.in (HFILES_NO_SRCDIR): Add microblaze-linux-tdep.h
> >>>        ALLDEPFILES: Add microblaze-linux-nat.c
> >>
> >> gdb doesn't use ChangeLogs any more and this text should all be removed.
> >>
> >>> +#define MICROBLAZE_TARGET_HAS_GETREGS 0
> >>> +#define MICROBLAZE_TARGET_HAS_SETREGS 0
> >>
> >> This seems weird:
> >>
> >>> +/* Wrapper function around ptrace.  */
> >>> +
> >>> +static void
> >>> +fetch_target_gp_regs (int tid, elf_gregset_t *gregs)
> >>> +{
> >>> +  elf_greg_t *gregp = *gregs;
> >>> +
> >>> +#if MICROBLAZE_TARGET_HAS_GETREGS
> >>> +  if (ptrace (PTRACE_GETREGS, tid, 0, (long) gregp) < 0)
> >>> +    {
> >>> +      perror_with_name (_("Couldn't get registers"));
> >>> +      return;
> >>> +    }
> >>> +#error "this configuration did not work during testing"
> >>
> >> Normally we don't put new dead code into gdb.
> >>
> >> I think this and the defines could just be replaced with a comment
> >> explaining that PTRACE_GETREGS doesn't work on this platform.
> >>
> >>> +++ b/gdb/microblaze-linux-tdep.h
> >>> @@ -0,0 +1,24 @@
> >>> +/* Target-dependent code for GNU/Linux on MicroBlaze.
> >>> +
> >>> +   Copyright (C) 2021-2026 Free Software Foundation, Inc.
> >>> +
> >>> +   This file is part of GDB.
> >>> +
> >>> +   This program is free software; you can redistribute it and/or modify
> >>> +   it under the terms of the GNU General Public License as published by
> >>> +   the Free Software Foundation; either version 3 of the License, or
> >>> +   (at your option) any later version.
> >>> +
> >>> +   This program is distributed in the hope that it will be useful,
> >>> +   but WITHOUT ANY WARRANTY; without even the implied warranty of
> >>> +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> >>> +   GNU General Public License for more details.
> >>> +
> >>> +   You should have received a copy of the GNU General Public License
> >>> +   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
> >>> +#ifndef MICROBLAZE_LINUX_TDEP_H
> >>> +#define MICROBLAZE_LINUX_TDEP_H
> >>> + /* Target descriptions.  */
> >>> + extern struct target_desc *tdesc_microblaze_linux;
> >>
> >> Blank line between the #define and the comment.
> >>
> >> Also this define should have a slightly different name, see
> >> check-include-guards.py.
> >>
> >>>          non_stack_instruction_found = 0;
> >>> +          cache->register_offsets[rd] = -imm;
> >>>          continue;
> >>
> >> Indentation looks wrong, probably not using tabs.
> >>
> >>> @@ -399,8 +400,7 @@ microblaze_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
> >>>       {
> >>>         sal = find_sal_for_pc (func_start, 0);
> >>
> >>> -      if (sal.end < func_end
> >>> -       && start_pc <= sal.end)
> >>> +      if (sal.line != 0 && sal.end <= func_end  && start_pc <= sal.end)
> >>>        start_pc = sal.end;
> >>
> >> No objection from me but this seems somewhat unrelated.
> >>
> >>
> >>>     /* Call for side effects.  */
> >>> -  get_frame_func (next_frame);
> >>> +  cache->pc = get_frame_func (next_frame);
> >>
> >> Please remove that comment as it is now wrong.
> >>
> >>> +  if (regnum == MICROBLAZE_SP_REGNUM)
> >>> +        regnum = 1;
> >>
> >> Wrong indentation.
> >>
> >>> +  if (regnum == -1) {
> >>> +    int i;
> >>> +
> >>> +    for (i = 0; i < MICROBLAZE_REDR_REGNUM; i++) {
> >>> +      regcache->raw_supply (i, regs + i * MICROBLAZE_REGISTER_SIZE);
> >>> +    }
> >>
> >> Wrong brace placement in this hunk.
> >>
> >>> +  cb (".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL,
> >>> +      cb_data);
> >>
> >> Normally in new code we're using 'nullptr' now.  Best would be to go
> >> through the whole patch and check for this.  You don't have to fix
> >> pre-existing code that is using NULL though.
> >>
> >>>     gdbarch *gdbarch
> >>>       = gdbarch_alloc (&info, gdbarch_tdep_up (new microblaze_gdbarch_tdep));
> >>
> >>> +  microblaze_gdbarch_tdep *tdep
> >>> +    = gdbarch_tdep<microblaze_gdbarch_tdep> (gdbarch);
> >>> +
> >>> +  tdep->gregset = NULL;
> >>> +  tdep->sizeof_gregset = 0;
> >>> +  tdep->fpregset = NULL;
> >>> +  tdep->sizeof_fpregset = 0;
> >>
> >> Here it would be better to just add inline initializers to the new
> >> fields in microblaze_gdbarch_tdep.  Then they'll automatically be
> >> initialized by the 'new'.
> >>
> >> Tom
> >
>
-------------- next part --------------
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From jbeulich@suse.com  Tue Jun  2 05:31:36 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Tue, 2 Jun 2026 07:31:36 +0200
Subject: [PATCH 1/3] PE-COFF: Fix weak external symbol resolution when
 strong undef is seen first
In-Reply-To: <20260530191522.57144-2-peter0x44@disroot.org>
References: <20260530191522.57144-1-peter0x44@disroot.org>
 <20260530191522.57144-2-peter0x44@disroot.org>
Message-ID: <ab2ce945-606c-40dd-8645-c1399a64068c@suse.com>

On 30.05.2026 21:15, Peter Damianov wrote:
> When linking PE-COFF objects, a weak external symbol (C_NT_WEAK with an
> aux record specifying a fallback alias) may fail to resolve if a strong
> undefined reference to the same symbol is encountered before the weak
> definition.  This causes "undefined reference" errors for symbols like
> operator new or personality routines that GCC emits as weak externals
> with a fallback to a default implementation.
> 
> There are two problems:
> 
> 1. In coff_link_add_symbols, when the generic linker resolves a weak
>    undefined against an existing strong undefined (NOACT in the action
>    table), the COFF-specific symbol_class and aux record were not stored
>    because the existing hash entry already had non-null class/type from
>    the first (strong) object file.
> 
> 2. In _bfd_coff_generic_relocate_section, the weak alias fallback only
>    triggered for bfd_link_hash_undefweak symbols.  When a strong undef
>    is seen first, the hash type stays bfd_link_hash_undefined (the
>    generic linker does not downgrade it), so the fallback was skipped.

For both of these, where is it written down what the required behavior
is? From your description it sounds as if you're moving from one extreme
("strong" as the overall result) to the other ("weak" as the overall
result), when it kind of feels as if the type of reference may need to
be retained per incoming object file. (Or else "strong" being the
overall result would look to be more likely to be correct.)

Jan

From jbeulich@suse.com  Tue Jun  2 05:42:04 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Tue, 2 Jun 2026 07:42:04 +0200
Subject: [PATCH] x86: Pass "%s" to i386_dis_printf as the format string
In-Reply-To: <CAMe9rOqXyFZFe1Z5fpUfGKtFJW_fFh26MrPHzDZR41LQzLFxug@mail.gmail.com>
References: <9a6fd40f-1081-41e3-8050-e000ba78fcfb@suse.com>
 <916dde10-59ed-4180-86e6-a42677b90c20@suse.com>
 <CAMe9rOoif-2+zZoR1=Vbr3pcGBoCnBhDW84Xy=pJ9agBvQUn6g@mail.gmail.com>
 <0aba1c01-8f9a-42f6-a00e-da139577b45a@suse.com>
 <CAMe9rOqXyFZFe1Z5fpUfGKtFJW_fFh26MrPHzDZR41LQzLFxug@mail.gmail.com>
Message-ID: <2238304c-72b5-4a8b-996d-e52c928a91c7@suse.com>

On 25.05.2026 00:31, H.J. Lu wrote:
> On Sun, May 24, 2026 at 11:11?PM Jan Beulich <jbeulich@suse.com> wrote:
>>
>> On 24.05.2026 02:09, H.J. Lu wrote:
>>> On Fri, May 15, 2026 at 9:08?PM Jan Beulich <jbeulich@suse.com> wrote:
>>>>
>>>> Model this after operand handling, such that comments can be emitted in
>>>> the same order as operands. %rip-relative address comments remain
>>>> separate for now. While there correct style for the symbols associated
>>>> with immediates: These aren't "comment starts", but symbol names.
>>>> ---
>>>> As long as we want to continue to use the ->print_address_func() hook,
>>>> properly unifying %rip-relative comments with others won't be possible.
>>>> That, however, is in line with direct addresses also getting printed
>>>> specially, similarly by using ->print_address_func().
>>>>
>>>> Was it really intended for the original -Mannotate test to be run only for
>>>> Linux targets? It certainly isn't intended here, yet I'd like the new
>>>> tests to be in the same directory as the original one. x86-64.exp,
>>>> however, bails right away for non-Linux (and remote hosts). I guess at
>>>> least the *.d based testing loop should be moved up. Tests truly only
>>>> working for Linux can easily be constrained in the *.d files themselves.
>>>>
>>>> --- /dev/null
>>>> +++ b/binutils/testsuite/binutils-all/x86-64/comments.d
>>>> @@ -0,0 +1,14 @@
>>>> +#name: disassembly comments (AT&T)
>>>> +#ld:
>>>> +#objdump: -dwMannotate,att
>>>> +
>>>> +.*: +file format .*
>>>> +
>>>> +
>>>> +Disassembly of section .text:
>>>> +
>>>> +[0-9a-f]+ <_start>:
>>>> +[      ]*[0-9a-f]+:    48 c7 05 [0-9a-f ]+     movq   \$0x[0-9a-f]+,0x[0-9a-f]+\(%rip\) +# \[_start\], [0-9a-f]+ <fptr>
>>>> +[      ]*[0-9a-f]+:    31 c0                   xor    %eax,%eax
>>>> +[      ]*[0-9a-f]+:    c3                      ret
>>>> +#pass
>>>> --- /dev/null
>>>> +++ b/binutils/testsuite/binutils-all/x86-64/comments.s
>>>> @@ -0,0 +1,9 @@
>>>> +       .text
>>>> +       .global _start
>>>> +_start:
>>>> +       movq    $_start, fptr(%rip)
>>>> +       xor     %eax, %eax
>>>> +       ret
>>>> +
>>>> +       .data
>>>> +fptr:  .quad   -1
>>>> --- /dev/null
>>>> +++ b/binutils/testsuite/binutils-all/x86-64/comments-intel.d
>>>> @@ -0,0 +1,14 @@
>>>> +#name: disassembly comments (Intel)
>>>> +#source: comments.s
>>>> +#ld:
>>>> +#objdump: -dwMannotate,intel
>>>> +
>>>> +.*: +file format .*
>>>> +
>>>> +
>>>> +Disassembly of section .text:
>>>> +
>>>> +[0-9a-f]+ <_start>:
>>>> +[      ]*[0-9a-f]+:    48 c7 05 [0-9a-f ]+     mov    QWORD PTR \[rip\+0x[0-9a-f]+\],0x[0-9a-f]+ +# [0-9a-f]+ <fptr>, \[_start\]
>>>> +[      ]*[0-9a-f]+:    31 c0                   xor    eax,eax
>>>> +[      ]*[0-9a-f]+:    c3                      ret
>>>> --- a/opcodes/i386-dis.c
>>>> +++ b/opcodes/i386-dis.c
>>>> @@ -179,8 +179,7 @@ struct instr_info
>>>>
>>>>    char obuf[MAX_OPERAND_BUFFER_SIZE];
>>>>    char *obufp;
>>>> -  char cbuf[COMMENT_BUFFER_SIZE];
>>>> -  char * cbufp;
>>>> +  char *cbufp;
>>>>    char *mnemonicendp;
>>>>    const uint8_t *start_codep;
>>>>    uint8_t *codep;
>>>> @@ -258,6 +257,7 @@ struct instr_info
>>>>    signed char op_index[MAX_OPERANDS];
>>>>    bool op_riprel[MAX_OPERANDS];
>>>>    char *op_out[MAX_OPERANDS];
>>>> +  char *cm_out[MAX_OPERANDS];
>>>>    bfd_vma op_address[MAX_OPERANDS];
>>>>    bfd_vma start_pc;
>>>>
>>>> @@ -9749,7 +9749,6 @@ print_insn (bfd_vma pc, disassemble_info
>>>>      .start_codep = priv.the_buffer,
>>>>      .codep = priv.the_buffer,
>>>>      .obufp = ins.obuf,
>>>> -    .cbufp = ins.cbuf,
>>>>      .last_lock_prefix = -1,
>>>>      .last_repz_prefix = -1,
>>>>      .last_repnz_prefix = -1,
>>>> @@ -9761,6 +9760,7 @@ print_insn (bfd_vma pc, disassemble_info
>>>>      .fwait_prefix = -1,
>>>>    };
>>>>    char op_out[MAX_OPERANDS][MAX_OPERAND_BUFFER_SIZE];
>>>> +  char cm_out[MAX_OPERANDS][COMMENT_BUFFER_SIZE];
>>>>
>>>>    priv.orig_sizeflag = AFLAG | DFLAG;
>>>>    if ((info->mach & bfd_mach_i386_i386) != 0)
>>>> @@ -9874,6 +9874,8 @@ print_insn (bfd_vma pc, disassemble_info
>>>>      {
>>>>        op_out[i][0] = 0;
>>>>        ins.op_out[i] = op_out[i];
>>>> +      cm_out[i][0] = 0;
>>>> +      ins.cm_out[i] = cm_out[i];
>>>>      }
>>>>
>>>>    sizeflag = priv.orig_sizeflag;
>>>> @@ -9992,6 +9994,7 @@ print_insn (bfd_vma pc, disassemble_info
>>>>           for (i = 0; i < MAX_OPERANDS; ++i)
>>>>             {
>>>>               ins.obufp = ins.op_out[i];
>>>> +             ins.cbufp = ins.cm_out[i];
>>>>               ins.op_ad = MAX_OPERANDS - 1 - i;
>>>>               if (dp->op[i].rtn
>>>>                   && !dp->op[i].rtn (&ins, dp->op[i].bytemode, sizeflag))
>>>> @@ -10317,6 +10320,10 @@ print_insn (bfd_vma pc, disassemble_info
>>>>           riprel = ins.op_riprel[i];
>>>>           ins.op_riprel[i] = ins.op_riprel[MAX_OPERANDS - 1 - i];
>>>>           ins.op_riprel[MAX_OPERANDS - 1 - i] = riprel;
>>>> +
>>>> +         char *tmp = ins.cm_out[i];
>>>> +         ins.cm_out[i] = ins.cm_out[MAX_OPERANDS - 1 - i];
>>>> +         ins.cm_out[MAX_OPERANDS - 1 - i] = tmp;
>>>>         }
>>>>      }
>>>>    else
>>>> @@ -10364,22 +10371,23 @@ print_insn (bfd_vma pc, disassemble_info
>>>>         needcomma = 1;
>>>>        }
>>>>
>>>> +  const char *sep = "        # ";
>>>>    for (i = 0; i < MAX_OPERANDS; i++)
>>>>      if (ins.op_index[i] != -1 && ins.op_riprel[i])
>>>>        {
>>>> -       i386_dis_printf (info, dis_style_comment_start, "        # ");
>>>> +       i386_dis_printf (info, dis_style_comment_start, sep);
>>>> +       sep = ", ";
>>>>         (*info->print_address_func)
>>>>           ((bfd_vma)(ins.start_pc + (ins.codep - ins.start_codep)
>>>>                      + ins.op_address[ins.op_index[i]]),
>>>> -         info);
>>>> -       break;
>>>> +          info);
>>>> +      }
>>>> +    else if (*ins.cm_out[i])
>>>> +      {
>>>> +       i386_dis_printf (info, dis_style_comment_start, sep);
>>>> +       sep = ", ";
>>>> +       i386_dis_printf (info, dis_style_symbol, "%s", ins.cm_out[i]);
>>>>        }
>>>> -  if (ins.cbufp != ins.cbuf)
>>>> -    {
>>>> -      if (i == MAX_OPERANDS)
>>>> -       i386_dis_printf (info, dis_style_comment_start, "        # ");
>>>> -      i386_dis_printf (info, dis_style_comment_start, "%s", ins.cbuf);
>>>> -    }
>>>>
>>>>    ret = ins.codep - priv.the_buffer;
>>>>   out:
>>>> @@ -10760,6 +10768,7 @@ dofloat (instr_info *ins, int sizeflag)
>>>
>>> commit aeced13ee0cd570d78cb37ab1f9bba840958515a
>>> Author: Jan Beulich <jbeulich@suse.com>
>>> Date:   Fri May 22 08:49:12 2026 +0200
>>>
>>>     x86/disasm: rework comment handling
>>>
>>> caused:
>>>
>>> libtool: compile:  gcc -DHAVE_CONFIG_H -I. -I../../opcodes -I.
>>> -I../../opcodes -I../bfd -I../../opcodes/../include
>>> -I../../opcodes/../bfd -W -Wall -Wstrict-prototypes
>>> -Wmissing-prototypes -Wshadow -Wstack-usage=262144 -O2 -flto=auto
>>> -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall
>>> -Wno-complain-wrong-lang -Werror=format-security
>>> -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS
>>> -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1
>>> -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1
>>> -m32 -march=i686 -mtune=generic -msse2 -mfpmath=sse -mstackrealign
>>> -fasynchronous-unwind-tables -fstack-clash-protection
>>> -mtls-dialect=gnu -flto=8 -std=gnu11 -fprofile-generate
>>> -flto=jobserver -ffat-lto-objects -MT i386-dis.lo -MD -MP -MF
>>> .deps/i386-dis.Tpo -c ../../opcodes/i386-dis.c  -fPIC -DPIC -o
>>> .libs/i386-dis.o
>>> ../../opcodes/i386-dis.c: In function ?print_insn?:
>>> ../../opcodes/i386-dis.c:10378:9: error: format not a string literal
>>> and no format arguments [-Werror=format-security]
>>> 10378 |         i386_dis_printf (info, dis_style_comment_start, sep);
>>>       |         ^~~~~~~~~~~~~~~
>>> ../../opcodes/i386-dis.c:10387:9: error: format not a string literal
>>> and no format arguments [-Werror=format-security]
>>> 10387 |         i386_dis_printf (info, dis_style_comment_start, sep);
>>>       |         ^~~~~~~~~~~~~~~
>>> cc1: some warnings being treated as errors
>>> make[4]: *** [Makefile:1076: i386-dis.lo] Error 1
>>>
>>> Since i386_dis_printf is declared as
>>>
>>> static void ATTRIBUTE_PRINTF_3 i386_dis_printf (const disassemble_info *,
>>>                                                 enum disassembler_style,
>>>                                                 const char *, ...);
>>>
>>> the 3rd argument should be a string literal as the format string.  Pass
>>> "%s" to i386_dis_printf as the format string to fix the regression.
>>
>> What exactly does "should" here mean? I.e. what exactly is wrong with the
>> format string not being a literal? Unless that can be explained, it feels as
>> if first of all a gcc bug wants opening. That would then want referencing
>> here.
>>
>> Jan
> 
> Binutils may be compiled with -Werror=format-security:
> 
> ?-Wformat-security?
>      If ?-Wformat? is specified, also warn about uses of format
>      functions that represent possible security problems.  At present,
>      this warns about calls to ?printf? and ?scanf? functions where the
>      format string is not a string literal and there are no format
>      arguments, as in ?printf (foo);?.  This may be a security hole if
>      the format string came from untrusted input and contains ?%n?.
>      (This is currently a subset of what ?-Wformat-nonliteral? warns
>      about, but in future warnings may be added to ?-Wformat-security?
>      that are not included in ?-Wformat-nonliteral?.)
> 
> Your commit breaks it.

It breaks the overly strong requirements by the compiler warning, but it
doesn't break anything in reality, nor does it break any standard C
requirements. Hence "should" is ambiguous / potentially misleading.

Jan

From jbeulich@suse.com  Tue Jun  2 05:46:49 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Tue, 2 Jun 2026 07:46:49 +0200
Subject: macho gas support
In-Reply-To: <ahQX5TBTuLWWgw_n@squeak.grove.modra.org>
References: <ahQX5TBTuLWWgw_n@squeak.grove.modra.org>
Message-ID: <4a0e0a9d-ae07-455f-ace2-e43d8ce65ff5@suse.com>

On 25.05.2026 11:35, Alan Modra wrote:
> ix86-darwin is the only remaining macho target supported by gas.  I'm
> not sure how much it is used nowadays, and judging by the number of
> x86 tests and mach-o tests that fail, it seems no one is actively
> maintaining the code.  So it's quite possible this series of patches I
> made fixing some issues was wasted time.  My interest in the port
> started with seeing a regression from commit cc28c46227cd.  Fixing
> that led to finding more problems.

I actively ignored these, much like I actively ignore other new failures
for Darwin due to the overly many pre-existing ones. I did raise the
question of Mach-O support status on the second to last Cauldron, yet no
real resolution came forward. Imo, unless a new maintainer shows up, we
might be better off ripping out that largely broken (and far from
complete) support (not just from gas, but also from in particular bfd).

Jan

From jbeulich@suse.com  Tue Jun  2 08:04:08 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Tue, 2 Jun 2026 10:04:08 +0200
Subject: [PATCH v2] riscv: Ignore attributes in input file with empty code
 section
In-Reply-To: <CAMe9rOq9Rf=4OfnXgaTo1X-pSychr6ikCRd9oh0fwx2K-ZGqCQ@mail.gmail.com>
References: <CAMe9rOpM413U8i5oFK=Um4d3ns3+bAyYWf3EAqq7gSMFaXjHhA@mail.gmail.com>
 <CAMe9rOq9Rf=4OfnXgaTo1X-pSychr6ikCRd9oh0fwx2K-ZGqCQ@mail.gmail.com>
Message-ID: <6f9f2818-590f-4d15-814d-cb2fb9372ac3@suse.com>

On 28.05.2026 23:45, H.J. Lu wrote:
> On Thu, May 28, 2026 at 5:29?PM H.J. Lu <hjl.tools@gmail.com> wrote:
>>
>> Ignore empty and .note.gnu.build-id sections when merging attributes.
>> The following linker tests now pass for riscv:
>>
>> FAIL: Diagnostics - Wrong magic number mixed with valid CTF sections
>> FAIL: --gc-sections with --defsym
>> FAIL: --gc-sections with KEEP
>> FAIL: --gc-sections with __start_SECTIONNAME
>> FAIL: ld-plugin/lto-10r
>> FAIL: ld-plugin/lto-3r
>> FAIL: ld-plugin/lto-4r-a
>> FAIL: ld-plugin/lto-4r-b
>> FAIL: ld-plugin/lto-4r-c
>> FAIL: ld-plugin/lto-4r-d
>> FAIL: ld-plugin/lto-5r
>> FAIL: PR ld/19317 (2)
>> FAIL: PR ld/19317 (3)
>>
>> PR ld/34185
>> * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Ignore
>> attributes in empty input file
> 
> Here is the v2 patch to ignore attributes in input file with empty code section
> when merging attributes.

I'm not sure if this is correct: Attributes may have a meaning even if there are
only empty code sections (or none at all). RISC-V folks will need to comment
here.

Jan

From jbeulich@suse.com  Tue Jun  2 08:26:47 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Tue, 2 Jun 2026 10:26:47 +0200
Subject: [PATCH] x86: Support BHI_CTRL instruction
In-Reply-To: <20260601062446.2367458-1-haochen.jiang@intel.com>
References: <20260601062446.2367458-1-haochen.jiang@intel.com>
Message-ID: <982f780d-c653-4a4d-bfa8-19bed76b1277@suse.com>

On 01.06.2026 08:24, Haochen Jiang wrote:
> The following patch aimed to add BHI_CTRL. The ISA has been published in a
> separate tech paper last year and still missing its assembler/disassembler
> support.
> 
> One tricky thing is that it utilized part of the nops encoding and we need
> to keep the same behavior for the not touched one, i.e., repz nop. That is
> why I added a Fixup for now since I did not have a better idea for that.
> Discussions are welcomed on this.

Instead of this, add a decode step through prefix_table[]?

> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -3630,3 +3630,9 @@ vmovrs<bw>, 0xf26f, AVX10_2&MOVRS&x64, Modrm|Masking|Map5|<bw:vexw>|Disp8ShiftVL
>  vmovrs<dq>, 0xf36f, AVX10_2&MOVRS&x64, Modrm|Masking|Map5|<dq:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf, { Xmmword|Ymmword|Zmmword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
>  
>  // MOVRS instructions end.
> +
> +// BHI_CTRL insructions.
> +
> +ibhf, 0xf30f1ef8, BHI_CTRL, NoSuf|Size64, {}

So Size64 is here to have REX.W emitted. The whitepaper isn't clear about APX
at all, though: Would REX2.W also have the same effect? (Whichever way it is,
this then perhaps also wants covering in the testsuite.)

In any event, I don't think we want the i386-gen.c change; instead we want
x64&BHI_CTRL here: Aiui BHI_CTRL itself isn't 64-bit only, it's only this new
insn which is.

Jan

From jbeulich@suse.com  Tue Jun  2 08:29:27 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Tue, 2 Jun 2026 10:29:27 +0200
Subject: [PATCH] x86: Support BHI_CTRL instruction
In-Reply-To: <982f780d-c653-4a4d-bfa8-19bed76b1277@suse.com>
References: <20260601062446.2367458-1-haochen.jiang@intel.com>
 <982f780d-c653-4a4d-bfa8-19bed76b1277@suse.com>
Message-ID: <4779390d-d1d4-4e83-9c00-09bb63139d6f@suse.com>

On 02.06.2026 10:26, Jan Beulich wrote:
> On 01.06.2026 08:24, Haochen Jiang wrote:
>> The following patch aimed to add BHI_CTRL. The ISA has been published in a
>> separate tech paper last year and still missing its assembler/disassembler
>> support.
>>
>> One tricky thing is that it utilized part of the nops encoding and we need
>> to keep the same behavior for the not touched one, i.e., repz nop. That is
>> why I added a Fixup for now since I did not have a better idea for that.
>> Discussions are welcomed on this.
> 
> Instead of this, add a decode step through prefix_table[]?

Oh, wait - that's already in place. The problem is the REX.W aspect. For that
a fixup likely is indeed best.

Jan

From jbeulich@suse.com  Tue Jun  2 08:43:35 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Tue, 2 Jun 2026 10:43:35 +0200
Subject: [PATCH] ld/testsuite: enable build-id for ELF platforms
In-Reply-To: <CAJ307EiVn0ms5jOJcXz7mQZX2S06E4p-Ko6uzuha6RTpdCJaFQ@mail.gmail.com>
References: <20260529133254.1429717-1-chigot@adacore.com>
 <CAJ307EiVn0ms5jOJcXz7mQZX2S06E4p-Ko6uzuha6RTpdCJaFQ@mail.gmail.com>
Message-ID: <1090b1ad-b63a-43e9-b83a-af5bdcae1618@suse.com>

On 29.05.2026 15:45, Cl?ment Chigot wrote:
> On Fri, May 29, 2026 at 3:33?PM Cl?ment Chigot <chigot@adacore.com> wrote:
>>
>> --build-id is defined within elf.em and thus should be available for
>> all platforms matching "is_elf_format".
> 
> @Alan Modra I've tested a couple of ELF platforms internally. But I
> don't know if there is a way to trigger this test for all ELF
> emulations ? `--enable-targets=all` doesn't seem to be enough.

While that's enough to make the linker capable of linking for such targets,
it indeed isn't sufficient to have those cases covered by the testsuite. The
way the testsuite presently is written, you won't get around testing a build
for every one such target.

Jan

From martin@martin.st  Tue Jun  2 09:01:33 2026
From: martin@martin.st (=?ISO-8859-15?Q?Martin_Storsj=F6?=)
Date: Tue, 2 Jun 2026 12:01:33 +0300 (EEST)
Subject: [PATCH 1/3] PE-COFF: Fix weak external symbol resolution when
 strong undef is seen first
In-Reply-To: <ab2ce945-606c-40dd-8645-c1399a64068c@suse.com>
References: <20260530191522.57144-1-peter0x44@disroot.org>
 <20260530191522.57144-2-peter0x44@disroot.org>
 <ab2ce945-606c-40dd-8645-c1399a64068c@suse.com>
Message-ID: <36d8562c-a8a8-f12e-c0cb-e66f0da00c4e@martin.st>

On Tue, 2 Jun 2026, Jan Beulich wrote:

>> 1. In coff_link_add_symbols, when the generic linker resolves a weak
>>    undefined against an existing strong undefined (NOACT in the action
>>    table), the COFF-specific symbol_class and aux record were not stored
>>    because the existing hash entry already had non-null class/type from
>>    the first (strong) object file.
>>
>> 2. In _bfd_coff_generic_relocate_section, the weak alias fallback only
>>    triggered for bfd_link_hash_undefweak symbols.  When a strong undef
>>    is seen first, the hash type stays bfd_link_hash_undefined (the
>>    generic linker does not downgrade it), so the fallback was skipped.
>
> For both of these, where is it written down what the required behavior
> is? From your description it sounds as if you're moving from one extreme
> ("strong" as the overall result) to the other ("weak" as the overall
> result), when it kind of feels as if the type of reference may need to
> be retained per incoming object file. (Or else "strong" being the
> overall result would look to be more likely to be correct.)

This stems from how the COFF weak external symbols work - they are quite 
different from ELF weak symbols - but with these changes, they can provide 
mostly the same user facing behaviour.

In COFF, a "weak external" symbol is an undefined symbol (section number 
0, which means undefined symbol, but storage class 
IMAGE_SYM_CLASS_WEAK_EXTERNAL instead of IMAGE_SYM_CLASS_EXTERNAL), which 
contains an AUX symbol entry, pointing at another symbol (which may be 
defined in the same object file, or undefined, meant to be resolved in 
another object file). If there is no other definition available of that 
symbol, the linker should use the symbol pointed to by the weak external 
instead.

This mechanism works for both cases of weak symbols:

- For a weak declaration (where we reference a symbol which may or may not 
exist elsewhere), we have a weak external pointing at a null symbol. So if 
nothing else provides a definition of it, we don't fail the link with an 
undefined symbol, but we instead redirect uses of it towards the null 
symbol. This works with uses like this:

void __attribute__((weak)) maybe_exists(void);

void call(void) {
     if (maybe_exists)
         maybe_exists();
}

- For a weak definition, we have the COFF weak external point at the 
concrete symbol definition instead. If there's a strong definition of it 
elsewhere, that should be used, but if there is none, then the weak 
external, pointing at the fallback function implementation, should be used 
instead.


So if the linker already has seen a regular (strong) undefined symbol, and 
sees a weak external of the same symbol from another object file (which on 
the object file level is an "undefined weak external", with a reference to 
another symbol), that weak external serves as a potential definition of 
that symbol, which should be retained and used, in case there's no other 
(non-weak) definition of the symbol.

// Martin


From martin@martin.st  Tue Jun  2 09:01:33 2026
From: martin@martin.st (=?ISO-8859-15?Q?Martin_Storsj=F6?=)
Date: Tue, 2 Jun 2026 12:01:33 +0300 (EEST)
Subject: [PATCH 1/3] PE-COFF: Fix weak external symbol resolution when
 strong undef is seen first
In-Reply-To: <ab2ce945-606c-40dd-8645-c1399a64068c@suse.com>
References: <20260530191522.57144-1-peter0x44@disroot.org>
 <20260530191522.57144-2-peter0x44@disroot.org>
 <ab2ce945-606c-40dd-8645-c1399a64068c@suse.com>
Message-ID: <36d8562c-a8a8-f12e-c0cb-e66f0da00c4e@martin.st>

On Tue, 2 Jun 2026, Jan Beulich wrote:

>> 1. In coff_link_add_symbols, when the generic linker resolves a weak
>>    undefined against an existing strong undefined (NOACT in the action
>>    table), the COFF-specific symbol_class and aux record were not stored
>>    because the existing hash entry already had non-null class/type from
>>    the first (strong) object file.
>>
>> 2. In _bfd_coff_generic_relocate_section, the weak alias fallback only
>>    triggered for bfd_link_hash_undefweak symbols.  When a strong undef
>>    is seen first, the hash type stays bfd_link_hash_undefined (the
>>    generic linker does not downgrade it), so the fallback was skipped.
>
> For both of these, where is it written down what the required behavior
> is? From your description it sounds as if you're moving from one extreme
> ("strong" as the overall result) to the other ("weak" as the overall
> result), when it kind of feels as if the type of reference may need to
> be retained per incoming object file. (Or else "strong" being the
> overall result would look to be more likely to be correct.)

This stems from how the COFF weak external symbols work - they are quite 
different from ELF weak symbols - but with these changes, they can provide 
mostly the same user facing behaviour.

In COFF, a "weak external" symbol is an undefined symbol (section number 
0, which means undefined symbol, but storage class 
IMAGE_SYM_CLASS_WEAK_EXTERNAL instead of IMAGE_SYM_CLASS_EXTERNAL), which 
contains an AUX symbol entry, pointing at another symbol (which may be 
defined in the same object file, or undefined, meant to be resolved in 
another object file). If there is no other definition available of that 
symbol, the linker should use the symbol pointed to by the weak external 
instead.

This mechanism works for both cases of weak symbols:

- For a weak declaration (where we reference a symbol which may or may not 
exist elsewhere), we have a weak external pointing at a null symbol. So if 
nothing else provides a definition of it, we don't fail the link with an 
undefined symbol, but we instead redirect uses of it towards the null 
symbol. This works with uses like this:

void __attribute__((weak)) maybe_exists(void);

void call(void) {
     if (maybe_exists)
         maybe_exists();
}

- For a weak definition, we have the COFF weak external point at the 
concrete symbol definition instead. If there's a strong definition of it 
elsewhere, that should be used, but if there is none, then the weak 
external, pointing at the fallback function implementation, should be used 
instead.


So if the linker already has seen a regular (strong) undefined symbol, and 
sees a weak external of the same symbol from another object file (which on 
the object file level is an "undefined weak external", with a reference to 
another symbol), that weak external serves as a potential definition of 
that symbol, which should be retained and used, in case there's no other 
(non-weak) definition of the symbol.

// Martin


From amodra@gmail.com  Tue Jun  2 09:08:01 2026
From: amodra@gmail.com (Alan Modra)
Date: Tue, 2 Jun 2026 18:38:01 +0930
Subject: [PATCH] ld/testsuite: enable build-id for ELF platforms
In-Reply-To: <20260529133254.1429717-1-chigot@adacore.com>
References: <20260529133254.1429717-1-chigot@adacore.com>
Message-ID: <ah6dcRsZzoyq1Si9@squeak.grove.modra.org>

On Fri, May 29, 2026 at 03:32:54PM +0200, Cl?ment Chigot wrote:
> --build-id is defined within elf.em and thus should be available for
> all platforms matching "is_elf_format".

No, there are ELF targets that don't use elf.em.  See lib/ld-lib.exp
uses_genelf.  I think the test should be using

if { ![is_elf_format] || [uses_genelf] } {
    return
}

and no other exclusions.  I'll see if that is correct.

-- 
Alan Modra

From jbeulich@suse.com  Tue Jun  2 09:12:51 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Tue, 2 Jun 2026 11:12:51 +0200
Subject: [PATCH 1/2] RISC-V: Add ARC-V APEX assembler support
In-Reply-To: <20260525133052.1885254-2-luiss@synopsys.com>
References: <20260525133052.1885254-1-luiss@synopsys.com>
 <20260525133052.1885254-2-luiss@synopsys.com>
Message-ID: <38e416b6-76b6-4c26-8f8b-25c4def56d8a@suse.com>

On 25.05.2026 15:30, Luis Silva wrote:
> --- a/gas/doc/c-riscv.texi
> +++ b/gas/doc/c-riscv.texi
> @@ -265,6 +265,59 @@ Floating point constructors for the bfloat16 type, example usage:
>  	.bfloat16 0b:ffc1
>  @end smallexample
>  
> +@cindex @code{.extInstruction} directive, RISC-V

To me this directive is too long. .extinsn perhaps, or even one of .einsn or
.xinsn? Otoh ...

> +@cindex ARC-V APEX instructions
> +@item .extInstruction @var{name}, @var{opcode}, @var{attrs}@dots{}
> +Define a dynamic APEX instruction that uses the Custom-0 encoding space.

... the ARC-V / APEX aspect isn't encoded at all in the directive name. Some
other vendor could come up with some different scheme. So maybe .apexinsn?
Or one of the earlier suggested names, but with a first operand required to
be "apex" for this variant?

> +The @var{name} is the mnemonic used in subsequent assembly.  The
> +@var{opcode} is the function code (sub-opcode) whose valid range depends
> +on the format.  The @var{attrs} are a comma-separated list drawn from:
> +
> +@table @code
> +@item XD
> +XD format (3 register operands, 8-bit sub-opcode, range 0--255).
> +@item XS
> +XS format (2 registers + 8-bit signed immediate, 6-bit sub-opcode,
> +range 0--63).
> +@item XI
> +XI format (1 register + 12-bit signed immediate, 5-bit sub-opcode,
> +range 0--31).
> +@item XC
> +XC format (1 register acting as both destination and source +
> +12-bit signed immediate, 5-bit sub-opcode, range 0--31).

What's the difference between XI and XC? The description says "compressed"
for the latter, but the encoding space needed (without the major opcode)
is 5 + 12 + 5 = 22, i.e. way beyond 16 bits. That's really no different
from XI. What am I missing?

> +@item void
> +Omit the destination register from the operand list.
> +@item no_src0
> +Omit the first source register from the operand list.
> +@item no_src1
> +Omit the second source register (or immediate) from the operand list.
> +@end table
> +
> +Exactly one of @code{XD}, @code{XS}, @code{XI}, or @code{XC} must be
> +specified.  @code{XS} and @code{XC} may be combined;

This contradicts the first sentence. That earlier sentence would better be
written to avoid such a contradiction, e.g. "With one exception, eaxctly
one ...".

> in that case the
> +assembler uses the XS encoding when the destination and source registers
> +differ (and the immediate fits in 8 bits), and the XC encoding when the
> +registers are the same or the immediate requires 12 bits.

This can't be correct: XC, as per what's said elsewhere, requires RD == RS1,
and hence the form can't be used when the immediate requires 12 bits but the
two registers don't match.

> +Examples:
> +
> +@smallexample
> +	.extInstruction myalu, 1, XD
> +	myalu a0, a1, a2
> +
> +	.extInstruction myimm, 5, XS
> +	myimm a0, a1, 42
> +
> +	.extInstruction myflex, 3, XS, XC
> +	myflex a0, a1, 10
> +	myflex a0, a0, 1000
> +@end smallexample
> +
> +The assembler emits metadata about each @code{.extInstruction} into
> +ELF sections named @code{.riscvapex.@var{fmt}.@var{custom0}.@var{opcode}},
> +which the disassembler reads to reconstruct instruction names and
> +operand formats.

So these sections exist solely for the disassembler's convenience? I.e.
them getting stripped (or them not being understood) isn't a functional
issue?

Jan

From amodra@gmail.com  Tue Jun  2 10:45:46 2026
From: amodra@gmail.com (Alan Modra)
Date: Tue, 2 Jun 2026 20:15:46 +0930
Subject: [PATCH] ld/testsuite: enable build-id for ELF platforms
In-Reply-To: <ah6dcRsZzoyq1Si9@squeak.grove.modra.org>
References: <20260529133254.1429717-1-chigot@adacore.com>
 <ah6dcRsZzoyq1Si9@squeak.grove.modra.org>
Message-ID: <ah60Wj6R6Gfpd-dO@squeak.grove.modra.org>

On Tue, Jun 02, 2026 at 06:38:01PM +0930, Alan Modra wrote:
> On Fri, May 29, 2026 at 03:32:54PM +0200, Cl?ment Chigot wrote:
> > --build-id is defined within elf.em and thus should be available for
> > all platforms matching "is_elf_format".
> 
> No, there are ELF targets that don't use elf.em.  See lib/ld-lib.exp
> uses_genelf.  I think the test should be using
> 
> if { ![is_elf_format] || [uses_genelf] } {
>     return
> }
> 
> and no other exclusions.  I'll see if that is correct.

I'll apply the following.  spu-elf fails the tests due to a readelf
complaint:
Displaying notes found in: .note.spu_name
readelf: Warning: Corrupt note: alignment 16, expecting 4 or 8

diff --git a/ld/testsuite/ld-elf/build-id.exp b/ld/testsuite/ld-elf/build-id.exp
index cabbcbd289a..6899cdbf2a2 100644
--- a/ld/testsuite/ld-elf/build-id.exp
+++ b/ld/testsuite/ld-elf/build-id.exp
@@ -19,23 +19,10 @@
 # MA 02110-1301, USA.
 #
 
-# Exclude non-ELF targets.
-
-if ![is_elf_format] {
-    return
-}
-
-if { [istarget frv-*-*] || [istarget lm32-*-*] } {
+if { ![is_elf_format] || [uses_genelf] } {
     return
 }
 
-if { !([istarget *-*-linux*]
-       || [istarget arm*-*-uclinuxfdpiceabi]
-       || [istarget *-*-gnu*]) } then {
-    return
-}
-
-
 set stylelist {"" "--build-id" "--build-id=none" "--build-id=md5"
     "--build-id=sha1" "--build-id=guid" "--build-id=0xdeadbeef"}
 


-- 
Alan Modra

From chigot@adacore.com  Tue Jun  2 11:22:35 2026
From: chigot@adacore.com (=?UTF-8?Q?Cl=C3=A9ment_Chigot?=)
Date: Tue, 2 Jun 2026 13:22:35 +0200
Subject: [PATCH] ld/testsuite: enable build-id for ELF platforms
In-Reply-To: <ah60Wj6R6Gfpd-dO@squeak.grove.modra.org>
References: <20260529133254.1429717-1-chigot@adacore.com>
 <ah6dcRsZzoyq1Si9@squeak.grove.modra.org>
 <ah60Wj6R6Gfpd-dO@squeak.grove.modra.org>
Message-ID: <CAJ307EgzcXR43meeh3SrHTaXTmnpaqHwqDr0Es3mzWF=Z=SF1w@mail.gmail.com>

On Tue, Jun 2, 2026 at 12:45?PM Alan Modra <amodra@gmail.com> wrote:
>
> On Tue, Jun 02, 2026 at 06:38:01PM +0930, Alan Modra wrote:
> > On Fri, May 29, 2026 at 03:32:54PM +0200, Cl?ment Chigot wrote:
> > > --build-id is defined within elf.em and thus should be available for
> > > all platforms matching "is_elf_format".
> >
> > No, there are ELF targets that don't use elf.em.  See lib/ld-lib.exp
> > uses_genelf.  I think the test should be using
> >
> > if { ![is_elf_format] || [uses_genelf] } {
> >     return
> > }
> >
> > and no other exclusions.  I'll see if that is correct.
>
> I'll apply the following.  spu-elf fails the tests due to a readelf
> complaint:
> Displaying notes found in: .note.spu_name
> readelf: Warning: Corrupt note: alignment 16, expecting 4 or 8

Perfect. Thanks a lot.
Cl?ment

> diff --git a/ld/testsuite/ld-elf/build-id.exp b/ld/testsuite/ld-elf/build-id.exp
> index cabbcbd289a..6899cdbf2a2 100644
> --- a/ld/testsuite/ld-elf/build-id.exp
> +++ b/ld/testsuite/ld-elf/build-id.exp
> @@ -19,23 +19,10 @@
>  # MA 02110-1301, USA.
>  #
>
> -# Exclude non-ELF targets.
> -
> -if ![is_elf_format] {
> -    return
> -}
> -
> -if { [istarget frv-*-*] || [istarget lm32-*-*] } {
> +if { ![is_elf_format] || [uses_genelf] } {
>      return
>  }
>
> -if { !([istarget *-*-linux*]
> -       || [istarget arm*-*-uclinuxfdpiceabi]
> -       || [istarget *-*-gnu*]) } then {
> -    return
> -}
> -
> -
>  set stylelist {"" "--build-id" "--build-id=none" "--build-id=md5"
>      "--build-id=sha1" "--build-id=guid" "--build-id=0xdeadbeef"}
>
>
>
> --
> Alan Modra

From josmyers@redhat.com  Tue Jun  2 17:06:10 2026
From: josmyers@redhat.com (Joseph Myers)
Date: Tue, 2 Jun 2026 17:06:10 +0000 (UTC)
Subject: [PATCH 1/3] bfd: fix 2 more -Wdiscarded-qualifiers errors
In-Reply-To: <20260223132805.3186869-2-simon.marchi@polymtl.ca>
References: <20260223132805.3186869-1-simon.marchi@polymtl.ca>
 <20260223132805.3186869-2-simon.marchi@polymtl.ca>
Message-ID: <454d3c9f-eea1-da66-6557-ac64469d00ac@redhat.com>

Could we backport the -Wdiscarded-qualifiers fixes, at least commits 
b3679b82926dd525e17a9b48114e96e95f0f6444 and 
36974d77e95efb1b640e8005a6bea6a6bed64aa7 (but probably others as well), to 
binutils 2.46 branch?  I'm seeing binutils build failures with my glibc 
bot that uses release branches of GCC and binutils since the system the 
bot runs on was updated to newer glibc.

https://sourceware.org/pipermail/libc-testresults/2026q2/014698.html

-- 
Joseph S. Myers
josmyers@redhat.com


From sam@gentoo.org  Tue Jun  2 17:28:46 2026
From: sam@gentoo.org (Sam James)
Date: Tue, 02 Jun 2026 18:28:46 +0100
Subject: [PATCH 1/3] bfd: fix 2 more -Wdiscarded-qualifiers errors
In-Reply-To: <454d3c9f-eea1-da66-6557-ac64469d00ac@redhat.com>
References: <20260223132805.3186869-1-simon.marchi@polymtl.ca>
 <20260223132805.3186869-2-simon.marchi@polymtl.ca>
 <454d3c9f-eea1-da66-6557-ac64469d00ac@redhat.com>
Message-ID: <874ijkonqp.fsf@gentoo.org>

Joseph Myers <josmyers@redhat.com> writes:

> Could we backport the -Wdiscarded-qualifiers fixes, at least commits 
> b3679b82926dd525e17a9b48114e96e95f0f6444 and 
> 36974d77e95efb1b640e8005a6bea6a6bed64aa7 (but probably others as well), to 
> binutils 2.46 branch?  I'm seeing binutils build failures with my glibc 
> bot that uses release branches of GCC and binutils since the system the 
> bot runs on was updated to newer glibc.
>
> https://sourceware.org/pipermail/libc-testresults/2026q2/014698.html

I've pushed these. We already have a bunch of them on the branch and I
thought we had them all. I'll look for others before I cut the point release.
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From josmyers@redhat.com  Tue Jun  2 17:47:31 2026
From: josmyers@redhat.com (Joseph Myers)
Date: Tue, 2 Jun 2026 17:47:31 +0000 (UTC)
Subject: [PATCH 1/3] bfd: fix 2 more -Wdiscarded-qualifiers errors
In-Reply-To: <874ijkonqp.fsf@gentoo.org>
References: <20260223132805.3186869-1-simon.marchi@polymtl.ca>
 <20260223132805.3186869-2-simon.marchi@polymtl.ca>
 <454d3c9f-eea1-da66-6557-ac64469d00ac@redhat.com> <874ijkonqp.fsf@gentoo.org>
Message-ID: <21ff7dc8-d48d-c41e-a70a-6be3a9598483@redhat.com>

On Tue, 2 Jun 2026, Sam James wrote:

> Joseph Myers <josmyers@redhat.com> writes:
> 
> > Could we backport the -Wdiscarded-qualifiers fixes, at least commits 
> > b3679b82926dd525e17a9b48114e96e95f0f6444 and 
> > 36974d77e95efb1b640e8005a6bea6a6bed64aa7 (but probably others as well), to 
> > binutils 2.46 branch?  I'm seeing binutils build failures with my glibc 
> > bot that uses release branches of GCC and binutils since the system the 
> > bot runs on was updated to newer glibc.
> >
> > https://sourceware.org/pipermail/libc-testresults/2026q2/014698.html
> 
> I've pushed these. We already have a bunch of them on the branch and I
> thought we had them all. I'll look for others before I cut the point release.

Thanks.  This fixes the binutils build for the target architectures where 
I saw problems with my glibc bot.

-- 
Joseph S. Myers
josmyers@redhat.com


From ludloff@gmail.com  Tue Jun  2 18:04:41 2026
From: ludloff@gmail.com (Christian Ludloff)
Date: Tue, 2 Jun 2026 11:04:41 -0700
Subject: [PATCH] x86: Support BHI_CTRL instruction
Message-ID: <CAKSQd8Vs+uLhKnnyCSaudbBu5CW2H3DYtHgibZmCC-sfsZ+JnA@mail.gmail.com>

> +ibhf, 0xf30f1ef8, BHI_CTRL, NoSuf|Size64, {}
>
> So Size64 is here to have REX.W emitted. The whitepaper isn't clear about APX
> at all, though: Would REX2.W also have the same effect? (Whichever way it is,
> this then perhaps also wants covering in the testsuite.)

I asked Intel for clarification when IBHF got published.

Their unofficial reply was to only use F3 48 0F 1E F8.

Not REX2.
Not EVEX.

Whenever this makes it into the SDM, Intel can clarify.

--
C.

From jeffrey.law@oss.qualcomm.com  Tue Jun  2 19:04:38 2026
From: jeffrey.law@oss.qualcomm.com (Jeffrey Law)
Date: Tue, 2 Jun 2026 13:04:38 -0600
Subject: [PATCH] RISC-V: Support Zvabd extension instructions.
In-Reply-To: <20260528100602.475331-1-jiawei@iscas.ac.cn>
References: <20260528100602.475331-1-jiawei@iscas.ac.cn>
Message-ID: <fa55bd86-ff4e-492c-9a68-8a2921802bde@oss.qualcomm.com>



On 5/28/2026 4:06 AM, Jiawei wrote:
> This patch adds support for the Zvabd extension instructions:
> https://github.com/riscv/integer-vector-absolute-difference
>
> The Zvabd extension provides RISC-V vector integer absolute difference
> operations.
>
> The widening accumulate mnemonics follow the current frozen specification
> are vwabda.vv and vwabdau.vv.
>
> bfd/ChangeLog:
>
> 	* elfxx-riscv.c (riscv_multi_subset_supports): Add Zvabd implication
>    of zve32x.
> 	(riscv_multi_subset_supports_ext): Add Zvabd.
>
> gas/ChangeLog:
>
> 	* NEWS:
> 	* testsuite/gas/riscv/march-help.l: Add Zvabd.
> 	* testsuite/gas/riscv/zvabd.d: New test.
> 	* testsuite/gas/riscv/zvabd.s: New test.
>
> include/ChangeLog:
>
> 	* opcode/riscv-opc.h (MATCH_VABS_V): New macro.
> 	(MASK_VABS_V): Ditto.
> 	(MATCH_VABD_VV): Ditto.
> 	(MASK_VABD_VV): Ditto.
> 	(MATCH_VABDU_VV): Ditto.
> 	(MASK_VABDU_VV): Ditto.
> 	(MATCH_VWABDA_VV): Ditto.
> 	(MASK_VWABDA_VV): Ditto.
> 	(MATCH_VWABDAU_VV): Ditto.
> 	(MASK_VWABDAU_VV): Ditto.
> 	* opcode/riscv.h (enum riscv_insn_class): New extension.
>
> opcodes/ChangeLog:
>
> 	* riscv-opc.c: New instructions.
OK.? Thanks for taking care of this.

jeff

From haochen.jiang@intel.com  Wed Jun  3 02:37:39 2026
From: haochen.jiang@intel.com (Jiang, Haochen)
Date: Wed, 3 Jun 2026 02:37:39 +0000
Subject: [PATCH] x86: Support BHI_CTRL instruction
In-Reply-To: <982f780d-c653-4a4d-bfa8-19bed76b1277@suse.com>
References: <20260601062446.2367458-1-haochen.jiang@intel.com>
 <982f780d-c653-4a4d-bfa8-19bed76b1277@suse.com>
Message-ID: <IA4PR11MB9009997D9669A4442CFF024DEC132@IA4PR11MB9009.namprd11.prod.outlook.com>

> From: Jan Beulich <jbeulich@suse.com>
> Sent: Tuesday, June 2, 2026 4:27 PM
> 
> On 01.06.2026 08:24, Haochen Jiang wrote:
> 
> > --- a/opcodes/i386-opc.tbl
> > +++ b/opcodes/i386-opc.tbl
> > @@ -3630,3 +3630,9 @@ vmovrs<bw>, 0xf26f, AVX10_2&MOVRS&x64,
> Modrm|Masking|Map5|<bw:vexw>|Disp8ShiftVL
> >  vmovrs<dq>, 0xf36f, AVX10_2&MOVRS&x64,
> Modrm|Masking|Map5|<dq:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf,
> { Xmmword|Ymmword|Zmmword|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM }
> >
> >  // MOVRS instructions end.
> > +
> > +// BHI_CTRL insructions.
> > +
> > +ibhf, 0xf30f1ef8, BHI_CTRL, NoSuf|Size64, {}
> 
> So Size64 is here to have REX.W emitted. The whitepaper isn't clear about APX
> at all, though: Would REX2.W also have the same effect? (Whichever way it is,
> this then perhaps also wants covering in the testsuite.)

No, it won't. The encoding is fixed. But a testcase is welcomed here to clarify.

> 
> In any event, I don't think we want the i386-gen.c change; instead we want
> x64&BHI_CTRL here: Aiui BHI_CTRL itself isn't 64-bit only, it's only this new
> insn which is.

I am okay with both solutions. But, yes, if we have a new inst in this ISA
(although very low probability) that supports both 32 and 64 bit, then the
current implementation will need re-do. And your point also stands.

Thus, I will change to x64&BHI_CTRL.

Thx,
Haochen

From jiawei@iscas.ac.cn  Wed Jun  3 06:52:08 2026
From: jiawei@iscas.ac.cn (Jiawei)
Date: Wed, 3 Jun 2026 14:52:08 +0800
Subject: [PATCH v6 1/2] RISC-V: Add SpacemiT vendor extension xsmtvdot
In-Reply-To: <20260525082008.1219171-2-zhuangqiubin@linux.spacemit.com>
References: <e066f12c-6e51-4d5f-ad2a-2955e99b5008@iscas.ac.cn>
 <20260525082008.1219171-1-zhuangqiubin@linux.spacemit.com>
 <20260525082008.1219171-2-zhuangqiubin@linux.spacemit.com>
Message-ID: <b9da157e-9a4d-4988-8478-487cad3850d9@iscas.ac.cn>

LGTM.

? 2026/5/25 16:20, Mark Zhuang ??:
> From: Mark Zhuang <mark.zhuang@spacemit.com>
>
> SpacemiT defines Intrinsic Matrix Extension (IME) specification [1].
> SpacemiT X60 implements version 1.0 of the SpacemiT Vector Dot Product
> Extension (XsmtVdot v1.0) [2], a subset of the full IME specification.
>
> [1] https://github.com/spacemit-com/riscv-ime-extension-spec/releases/download/v1.0/spacemit-ime-asciidoc.pdf
> [2] https://github.com/spacemit-com/docs-ai/blob/main/en/architecture/ime_extension.md
> ---
>   bfd/elfxx-riscv.c                         |  7 ++
>   gas/NEWS                                  |  3 +
>   gas/config/tc-riscv.c                     | 81 +++++++++++++++++++++++
>   gas/doc/c-riscv.texi                      |  8 +++
>   gas/testsuite/gas/riscv/march-help.l      |  1 +
>   gas/testsuite/gas/riscv/x-smt-vdot-fail.d |  3 +
>   gas/testsuite/gas/riscv/x-smt-vdot-fail.l | 73 ++++++++++++++++++++
>   gas/testsuite/gas/riscv/x-smt-vdot-fail.s | 50 ++++++++++++++
>   gas/testsuite/gas/riscv/x-smt-vdot.d      | 41 ++++++++++++
>   gas/testsuite/gas/riscv/x-smt-vdot.s      | 33 +++++++++
>   include/opcode/riscv-opc.h                | 38 +++++++++++
>   include/opcode/riscv.h                    |  9 +++
>   opcodes/riscv-dis.c                       | 33 +++++++++
>   opcodes/riscv-opc.c                       | 23 +++++++
>   14 files changed, 403 insertions(+)
>   create mode 100644 gas/testsuite/gas/riscv/x-smt-vdot-fail.d
>   create mode 100644 gas/testsuite/gas/riscv/x-smt-vdot-fail.l
>   create mode 100644 gas/testsuite/gas/riscv/x-smt-vdot-fail.s
>   create mode 100644 gas/testsuite/gas/riscv/x-smt-vdot.d
>   create mode 100644 gas/testsuite/gas/riscv/x-smt-vdot.s
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 83134f81c96..5fdbc1698af 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1229,6 +1229,8 @@ static const struct riscv_implicit_subset riscv_implicit_subsets[] =
>     {"xtheadvector", "+zicsr", check_implicit_always},
>     {"xtheadzvamo", "+zaamo", check_implicit_always},
>   
> +  {"xsmtvdot", "+zve32x", check_implicit_always},
> +
>     {"v", "+zve64d,+zvl128b", check_implicit_always},
>     {"zvfh", "+zvfhmin,+zfhmin", check_implicit_always},
>     {"zvfhmin", "+zve32f", check_implicit_always},
> @@ -1644,6 +1646,7 @@ static const struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
>     {"xmipscmov",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
>     {"xmipsexectl",	ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
>     {"xmipslsp",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
> +  {"xsmtvdot",		ISA_SPEC_CLASS_DRAFT,	1, 0, 0 },
>     {NULL, 0, 0, 0, 0}
>   };
>   
> @@ -3062,6 +3065,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
>         return riscv_subset_supports (rps, "xmipsexectl");
>       case INSN_CLASS_XMIPSLSP:
>         return riscv_subset_supports (rps, "xmipslsp");
> +    case INSN_CLASS_XSMTVDOT:
> +      return riscv_subset_supports (rps, "xsmtvdot");
>       default:
>         rps->error_handler
>           (_("internal: unreachable INSN_CLASS_*"));
> @@ -3365,6 +3370,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
>         return "xsfvqmaccdod";
>       case INSN_CLASS_XSFVFNRCLIPXFQF:
>         return "xsfvfnrclipxfqf";
> +    case INSN_CLASS_XSMTVDOT:
> +      return "xsmtvdot";
>       default:
>         rps->error_handler
>           (_("internal: unreachable INSN_CLASS_*"));
> diff --git a/gas/NEWS b/gas/NEWS
> index e384d1135c0..e47d55b05dc 100644
> --- a/gas/NEWS
> +++ b/gas/NEWS
> @@ -1,5 +1,8 @@
>   -*- text -*-
>   
> +* Add support for RISC-V vendor extensions:
> +  SpacemiT: xsmtvdot v1.0.
> +
>   Changes in 2.46:
>   
>   * Add support for AMD Zen6 processor.
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index b00b530b0bd..9c062ad3521 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -1770,6 +1770,30 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
>   		    goto unknown_validate_operand;
>   		}
>   		break;
> +	    case 'p': /* Vendor-specific (SpacemiT) operands.  */
> +	      switch (*++oparg)
> +		{
> +		case 'V':
> +		  switch (*++oparg)
> +		    {
> +		    case 'd':
> +		      USE_BITS (OP_MASK_SPACEMIT_IME_VD, OP_SH_SPACEMIT_IME_VD);
> +		      break;
> +		    case 's':
> +		      USE_BITS (OP_MASK_SPACEMIT_IME_VS1,
> +				OP_SH_SPACEMIT_IME_VS1);
> +		      break;
> +		    default:
> +		      goto unknown_validate_operand;
> +		    }
> +		  break;
> +		case 'w':
> +		  USE_BITS (OP_MASK_SPACEMIT_IME_WI, OP_SH_SPACEMIT_IME_WI);
> +		  break;
> +		default:
> +		  goto unknown_validate_operand;
> +		}
> +	      break;
>   	    default:
>   	      goto unknown_validate_operand;
>   	    }
> @@ -4286,6 +4310,63 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
>   		    }
>   		  break;
>   
> +		case 'p': /* Vendor-specific (SpacemiT) operands.  */
> +		  switch (*++oparg)
> +		    {
> +		    case 'V':
> +		      switch (*++oparg)
> +			{
> +			case 'd':
> +			  if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
> +			    break;
> +			  if ((regno & 0x1) != 0)
> +			    {
> +			      error.msg
> +				= _("illegal operands (vd must be even)");
> +			      error.missing_ext = NULL;
> +			      goto out;
> +			    }
> +			  INSERT_OPERAND (SPACEMIT_IME_VD, *ip, regno>>1);
> +			  continue;
> +			case 's':
> +			  if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
> +			    break;
> +			  if ((regno & 0x1) != 0)
> +			    {
> +			      error.msg
> +				= _("illegal operands (vs1 must be even)");
> +			      error.missing_ext = NULL;
> +			      goto out;
> +			    }
> +			  INSERT_OPERAND (SPACEMIT_IME_VS1, *ip, regno>>1);
> +			  continue;
> +			default:
> +			  goto unknown_riscv_ip_operand;
> +			}
> +		      break;
> +		    case 'w':
> +		      /* Xpw: optional data-width suffix, i8 only (WI=3).
> +			 If omitted, defaults to i8.  */
> +		      if (*asarg == ',')
> +			{
> +			  if (strcmp (asarg + 1, "i8") != 0)
> +			    {
> +			      error.msg
> +				= _("illegal operands (invalid data type)");
> +			      error.missing_ext = NULL;
> +			      goto out;
> +			    }
> +			  asarg += 3;
> +			}
> +		      else if (*asarg != '\0')
> +			goto unknown_riscv_ip_operand;
> +		      regno = 3;
> +		      INSERT_OPERAND (SPACEMIT_IME_WI, *ip, regno);
> +		      continue;
> +		    default:
> +		      goto unknown_riscv_ip_operand;
> +		    }
> +		  break;
>   		default:
>   		  goto unknown_riscv_ip_operand;
>   		}
> diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
> index c6c4081c204..d28744f4547 100644
> --- a/gas/doc/c-riscv.texi
> +++ b/gas/doc/c-riscv.texi
> @@ -918,4 +918,12 @@ The XMipsSlsp extension provides instructions mips.ldp, mips.lwp, mips.sdp and m
>   
>   It is documented in @url{https://mips.com/wp-content/uploads/2025/03/P8700-F_Programmers_Reference_Manual_Rev1.82_3-19-2025.pdf}.
>   
> +@item XSmtVdot
> +The XSmtVdot extension provides instructions for vector dot.
> +
> +SpacemiT defines Intrinsic Matrix Extension (IME) specification,
> +documented in @url{https://github.com/spacemit-com/riscv-ime-extension-spec/releases/download/v1.0/spacemit-ime-asciidoc.pdf}.
> +SpacemiT X60 implements version 1.0 of the SpacemiT Vector Dot Product Extension (XsmtVdot v1.0), a subset of the full IME specification,
> +documented in @url{https://github.com/spacemit-com/docs-ai/blob/main/en/architecture/ime_extension.md}.
> +
>   @end table
> diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
> index 0ce2f896735..6e52669e9a4 100644
> --- a/gas/testsuite/gas/riscv/march-help.l
> +++ b/gas/testsuite/gas/riscv/march-help.l
> @@ -186,3 +186,4 @@ All available -march extensions for RISC-V:
>   	xmipscmov                               1.0
>   	xmipsexectl                             1.0
>   	xmipslsp                                1.0
> +	xsmtvdot                                1.0
> diff --git a/gas/testsuite/gas/riscv/x-smt-vdot-fail.d b/gas/testsuite/gas/riscv/x-smt-vdot-fail.d
> new file mode 100644
> index 00000000000..bf8fb0f87ac
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/x-smt-vdot-fail.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv64gcv_xsmtvdot -I$srcdir/$subdir/
> +#source: x-smt-vdot-fail.s
> +#error_output: x-smt-vdot-fail.l
> diff --git a/gas/testsuite/gas/riscv/x-smt-vdot-fail.l b/gas/testsuite/gas/riscv/x-smt-vdot-fail.l
> new file mode 100644
> index 00000000000..77511d45296
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/x-smt-vdot-fail.l
> @@ -0,0 +1,73 @@
> +.*: Assembler messages:
> +.*:3: Error: illegal operands \(vd must be even\) `smt.vmadot v1,v3,v4'
> +.*:4: Error: illegal operands \(vd must be even\) `smt.vmadotu v1,v3,v4'
> +.*:5: Error: illegal operands \(vd must be even\) `smt.vmadotsu v1,v3,v4'
> +.*:6: Error: illegal operands \(vd must be even\) `smt.vmadotus v1,v3,v4'
> +.*:7: Error: illegal operands \(vd must be even\) `smt.vmadot1u v1,v4,v5'
> +.*:8: Error: illegal operands \(vd must be even\) `smt.vmadot1 v1,v4,v5'
> +.*:9: Error: illegal operands \(vd must be even\) `smt.vmadot1su v1,v4,v5'
> +.*:10: Error: illegal operands \(vd must be even\) `smt.vmadot1us v1,v4,v5'
> +.*:11: Error: illegal operands \(vd must be even\) `smt.vmadot2u v1,v4,v5'
> +.*:12: Error: illegal operands \(vd must be even\) `smt.vmadot2 v1,v4,v5'
> +.*:13: Error: illegal operands \(vd must be even\) `smt.vmadot2su v1,v4,v5'
> +.*:14: Error: illegal operands \(vd must be even\) `smt.vmadot2us v1,v4,v5'
> +.*:15: Error: illegal operands \(vd must be even\) `smt.vmadot3u v1,v4,v5'
> +.*:16: Error: illegal operands \(vd must be even\) `smt.vmadot3 v1,v4,v5'
> +.*:17: Error: illegal operands \(vd must be even\) `smt.vmadot3su v1,v4,v5'
> +.*:18: Error: illegal operands \(vd must be even\) `smt.vmadot3us v1,v4,v5'
> +.*:20: Error: illegal operands \(vs1 must be even\) `smt.vmadot1u v2,v3,v5'
> +.*:21: Error: illegal operands \(vs1 must be even\) `smt.vmadot1 v2,v3,v5'
> +.*:22: Error: illegal operands \(vs1 must be even\) `smt.vmadot1su v2,v3,v5'
> +.*:23: Error: illegal operands \(vs1 must be even\) `smt.vmadot1us v2,v3,v5'
> +.*:24: Error: illegal operands \(vs1 must be even\) `smt.vmadot2u v2,v3,v5'
> +.*:25: Error: illegal operands \(vs1 must be even\) `smt.vmadot2 v2,v3,v5'
> +.*:26: Error: illegal operands \(vs1 must be even\) `smt.vmadot2su v2,v3,v5'
> +.*:27: Error: illegal operands \(vs1 must be even\) `smt.vmadot2us v2,v3,v5'
> +.*:28: Error: illegal operands \(vs1 must be even\) `smt.vmadot3u v2,v3,v5'
> +.*:29: Error: illegal operands \(vs1 must be even\) `smt.vmadot3 v2,v3,v5'
> +.*:30: Error: illegal operands \(vs1 must be even\) `smt.vmadot3su v2,v3,v5'
> +.*:31: Error: illegal operands \(vs1 must be even\) `smt.vmadot3us v2,v3,v5'
> +.*:33: Error: illegal operands \(invalid data type\) `smt.vmadot v2,v3,v4,i1'
> +.*:34: Error: illegal operands \(invalid data type\) `smt.vmadot v2,v3,v4,i2'
> +.*:35: Error: illegal operands \(invalid data type\) `smt.vmadot v2,v3,v4,i3'
> +.*:36: Error: illegal operands \(invalid data type\) `smt.vmadot v2,v3,v4,i4'
> +.*:37: Error: illegal operands \(invalid data type\) `smt.vmadot v2,v3,v4,i5'
> +.*:38: Error: illegal operands \(invalid data type\) `smt.vmadot v2,v3,v4,i7'
> +.*:39: Error: illegal operands \(invalid data type\) `smt.vmadot v2,v3,v4,i16'
> +.*:40: Error: illegal operands \(invalid data type\) `smt.vmadot v2,v3,v4,i32'
> +.*:41: Error: illegal operands \(invalid data type\) `smt.vmadot v2,v3,v4,i64'
> +.*:42: Error: illegal operands \(invalid data type\) `smt.vmadot1u v2,v4,v5,i2'
> +.*:43: Error: illegal operands \(invalid data type\) `smt.vmadot2u v2,v4,v5,i4'
> +.*:44: Error: illegal operands \(invalid data type\) `smt.vmadot3u v2,v4,v5,i16'
> +.*:2: Error: unrecognized opcode `smt.vmadot v2,v3,v4', extension `xsmtvdot' required
> +.*:3: Error: unrecognized opcode `smt.vmadotu v2,v3,v4', extension `xsmtvdot' required
> +.*:4: Error: unrecognized opcode `smt.vmadotsu v2,v3,v4', extension `xsmtvdot' required
> +.*:5: Error: unrecognized opcode `smt.vmadotus v2,v3,v4', extension `xsmtvdot' required
> +.*:6: Error: unrecognized opcode `smt.vmadot1u v2,v4,v5', extension `xsmtvdot' required
> +.*:7: Error: unrecognized opcode `smt.vmadot1 v2,v4,v5', extension `xsmtvdot' required
> +.*:8: Error: unrecognized opcode `smt.vmadot1su v2,v4,v5', extension `xsmtvdot' required
> +.*:9: Error: unrecognized opcode `smt.vmadot1us v2,v4,v5', extension `xsmtvdot' required
> +.*:10: Error: unrecognized opcode `smt.vmadot2u v2,v4,v5', extension `xsmtvdot' required
> +.*:11: Error: unrecognized opcode `smt.vmadot2 v2,v4,v5', extension `xsmtvdot' required
> +.*:12: Error: unrecognized opcode `smt.vmadot2su v2,v4,v5', extension `xsmtvdot' required
> +.*:13: Error: unrecognized opcode `smt.vmadot2us v2,v4,v5', extension `xsmtvdot' required
> +.*:14: Error: unrecognized opcode `smt.vmadot3u v2,v4,v5', extension `xsmtvdot' required
> +.*:15: Error: unrecognized opcode `smt.vmadot3 v2,v4,v5', extension `xsmtvdot' required
> +.*:16: Error: unrecognized opcode `smt.vmadot3su v2,v4,v5', extension `xsmtvdot' required
> +.*:17: Error: unrecognized opcode `smt.vmadot3us v2,v4,v5', extension `xsmtvdot' required
> +.*:18: Error: unrecognized opcode `smt.vmadot v2,v3,v4,i8', extension `xsmtvdot' required
> +.*:19: Error: unrecognized opcode `smt.vmadotu v2,v3,v4,i8', extension `xsmtvdot' required
> +.*:20: Error: unrecognized opcode `smt.vmadotsu v2,v3,v4,i8', extension `xsmtvdot' required
> +.*:21: Error: unrecognized opcode `smt.vmadotus v2,v3,v4,i8', extension `xsmtvdot' required
> +.*:22: Error: unrecognized opcode `smt.vmadot1u v2,v4,v5,i8', extension `xsmtvdot' required
> +.*:23: Error: unrecognized opcode `smt.vmadot1 v2,v4,v5,i8', extension `xsmtvdot' required
> +.*:24: Error: unrecognized opcode `smt.vmadot1su v2,v4,v5,i8', extension `xsmtvdot' required
> +.*:25: Error: unrecognized opcode `smt.vmadot1us v2,v4,v5,i8', extension `xsmtvdot' required
> +.*:26: Error: unrecognized opcode `smt.vmadot2u v2,v4,v5,i8', extension `xsmtvdot' required
> +.*:27: Error: unrecognized opcode `smt.vmadot2 v2,v4,v5,i8', extension `xsmtvdot' required
> +.*:28: Error: unrecognized opcode `smt.vmadot2su v2,v4,v5,i8', extension `xsmtvdot' required
> +.*:29: Error: unrecognized opcode `smt.vmadot2us v2,v4,v5,i8', extension `xsmtvdot' required
> +.*:30: Error: unrecognized opcode `smt.vmadot3u v2,v4,v5,i8', extension `xsmtvdot' required
> +.*:31: Error: unrecognized opcode `smt.vmadot3 v2,v4,v5,i8', extension `xsmtvdot' required
> +.*:32: Error: unrecognized opcode `smt.vmadot3su v2,v4,v5,i8', extension `xsmtvdot' required
> +.*:33: Error: unrecognized opcode `smt.vmadot3us v2,v4,v5,i8', extension `xsmtvdot' required
> diff --git a/gas/testsuite/gas/riscv/x-smt-vdot-fail.s b/gas/testsuite/gas/riscv/x-smt-vdot-fail.s
> new file mode 100644
> index 00000000000..af33b693e54
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/x-smt-vdot-fail.s
> @@ -0,0 +1,50 @@
> +target:
> +	# vmadot/vmadot1/2/3: vd must be even
> +	smt.vmadot v1, v3, v4
> +	smt.vmadotu v1, v3, v4
> +	smt.vmadotsu v1, v3, v4
> +	smt.vmadotus v1, v3, v4
> +	smt.vmadot1u v1, v4, v5
> +	smt.vmadot1 v1, v4, v5
> +	smt.vmadot1su v1, v4, v5
> +	smt.vmadot1us v1, v4, v5
> +	smt.vmadot2u v1, v4, v5
> +	smt.vmadot2 v1, v4, v5
> +	smt.vmadot2su v1, v4, v5
> +	smt.vmadot2us v1, v4, v5
> +	smt.vmadot3u v1, v4, v5
> +	smt.vmadot3 v1, v4, v5
> +	smt.vmadot3su v1, v4, v5
> +	smt.vmadot3us v1, v4, v5
> +	# vmadot1/2/3: vs1 must be even
> +	smt.vmadot1u v2, v3, v5
> +	smt.vmadot1 v2, v3, v5
> +	smt.vmadot1su v2, v3, v5
> +	smt.vmadot1us v2, v3, v5
> +	smt.vmadot2u v2, v3, v5
> +	smt.vmadot2 v2, v3, v5
> +	smt.vmadot2su v2, v3, v5
> +	smt.vmadot2us v2, v3, v5
> +	smt.vmadot3u v2, v3, v5
> +	smt.vmadot3 v2, v3, v5
> +	smt.vmadot3su v2, v3, v5
> +	smt.vmadot3us v2, v3, v5
> +	# vmadot/vmadot1/2/3: invalid data type
> +	smt.vmadot v2, v3, v4, i1
> +	smt.vmadot v2, v3, v4, i2
> +	smt.vmadot v2, v3, v4, i3
> +	smt.vmadot v2, v3, v4, i4
> +	smt.vmadot v2, v3, v4, i5
> +	smt.vmadot v2, v3, v4, i7
> +	smt.vmadot v2, v3, v4, i16
> +	smt.vmadot v2, v3, v4, i32
> +	smt.vmadot v2, v3, v4, i64
> +	smt.vmadot1u v2, v4, v5, i2
> +	smt.vmadot2u v2, v4, v5, i4
> +	smt.vmadot3u v2, v4, v5, i16
> +
> +	# xsmtvdot - extension required
> +	.option push
> +	.option arch, rv64gcv
> +	.include "x-smt-vdot.s"
> +	.option pop
> diff --git a/gas/testsuite/gas/riscv/x-smt-vdot.d b/gas/testsuite/gas/riscv/x-smt-vdot.d
> new file mode 100644
> index 00000000000..6f86236785d
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/x-smt-vdot.d
> @@ -0,0 +1,41 @@
> +#as: -march=rv64gcv_xsmtvdot
> +#objdump: -dr
> +
> +.*:[ 	]+file format .*
> +
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ 	]+[0-9a-f]+:[ 	]+e241b12b[ 	]+smt.vmadot[ 	]+v2,v3,v4
> +[ 	]+[0-9a-f]+:[ 	]+e241812b[ 	]+smt.vmadotu[ 	]+v2,v3,v4
> +[ 	]+[0-9a-f]+:[ 	]+e241a12b[ 	]+smt.vmadotsu[ 	]+v2,v3,v4
> +[ 	]+[0-9a-f]+:[ 	]+e241912b[ 	]+smt.vmadotus[ 	]+v2,v3,v4
> +[ 	]+[0-9a-f]+:[ 	]+e652012b[ 	]+smt.vmadot1u[ 	]+v2,v4,v5
> +[ 	]+[0-9a-f]+:[ 	]+e652312b[ 	]+smt.vmadot1[ 	]+v2,v4,v5
> +[ 	]+[0-9a-f]+:[ 	]+e652212b[ 	]+smt.vmadot1su[ 	]+v2,v4,v5
> +[ 	]+[0-9a-f]+:[ 	]+e652112b[ 	]+smt.vmadot1us[ 	]+v2,v4,v5
> +[ 	]+[0-9a-f]+:[ 	]+e652412b[ 	]+smt.vmadot2u[ 	]+v2,v4,v5
> +[ 	]+[0-9a-f]+:[ 	]+e652712b[ 	]+smt.vmadot2[ 	]+v2,v4,v5
> +[ 	]+[0-9a-f]+:[ 	]+e652612b[ 	]+smt.vmadot2su[ 	]+v2,v4,v5
> +[ 	]+[0-9a-f]+:[ 	]+e652512b[ 	]+smt.vmadot2us[ 	]+v2,v4,v5
> +[ 	]+[0-9a-f]+:[ 	]+e652812b[ 	]+smt.vmadot3u[ 	]+v2,v4,v5
> +[ 	]+[0-9a-f]+:[ 	]+e652b12b[ 	]+smt.vmadot3[ 	]+v2,v4,v5
> +[ 	]+[0-9a-f]+:[ 	]+e652a12b[ 	]+smt.vmadot3su[ 	]+v2,v4,v5
> +[ 	]+[0-9a-f]+:[ 	]+e652912b[ 	]+smt.vmadot3us[ 	]+v2,v4,v5
> +[ 	]+[0-9a-f]+:[ 	]+e241b12b[ 	]+smt.vmadot[ 	]+v2,v3,v4
> +[ 	]+[0-9a-f]+:[ 	]+e241812b[ 	]+smt.vmadotu[ 	]+v2,v3,v4
> +[ 	]+[0-9a-f]+:[ 	]+e241a12b[ 	]+smt.vmadotsu[ 	]+v2,v3,v4
> +[ 	]+[0-9a-f]+:[ 	]+e241912b[ 	]+smt.vmadotus[ 	]+v2,v3,v4
> +[ 	]+[0-9a-f]+:[ 	]+e652012b[ 	]+smt.vmadot1u[ 	]+v2,v4,v5
> +[ 	]+[0-9a-f]+:[ 	]+e652312b[ 	]+smt.vmadot1[ 	]+v2,v4,v5
> +[ 	]+[0-9a-f]+:[ 	]+e652212b[ 	]+smt.vmadot1su[ 	]+v2,v4,v5
> +[ 	]+[0-9a-f]+:[ 	]+e652112b[ 	]+smt.vmadot1us[ 	]+v2,v4,v5
> +[ 	]+[0-9a-f]+:[ 	]+e652412b[ 	]+smt.vmadot2u[ 	]+v2,v4,v5
> +[ 	]+[0-9a-f]+:[ 	]+e652712b[ 	]+smt.vmadot2[ 	]+v2,v4,v5
> +[ 	]+[0-9a-f]+:[ 	]+e652612b[ 	]+smt.vmadot2su[ 	]+v2,v4,v5
> +[ 	]+[0-9a-f]+:[ 	]+e652512b[ 	]+smt.vmadot2us[ 	]+v2,v4,v5
> +[ 	]+[0-9a-f]+:[ 	]+e652812b[ 	]+smt.vmadot3u[ 	]+v2,v4,v5
> +[ 	]+[0-9a-f]+:[ 	]+e652b12b[ 	]+smt.vmadot3[ 	]+v2,v4,v5
> +[ 	]+[0-9a-f]+:[ 	]+e652a12b[ 	]+smt.vmadot3su[ 	]+v2,v4,v5
> +[ 	]+[0-9a-f]+:[ 	]+e652912b[ 	]+smt.vmadot3us[ 	]+v2,v4,v5
> diff --git a/gas/testsuite/gas/riscv/x-smt-vdot.s b/gas/testsuite/gas/riscv/x-smt-vdot.s
> new file mode 100644
> index 00000000000..a9991de4fc3
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/x-smt-vdot.s
> @@ -0,0 +1,33 @@
> +target:
> +	smt.vmadot v2, v3, v4
> +	smt.vmadotu v2, v3, v4
> +	smt.vmadotsu v2, v3, v4
> +	smt.vmadotus v2, v3, v4
> +	smt.vmadot1u v2, v4, v5
> +	smt.vmadot1 v2, v4, v5
> +	smt.vmadot1su v2, v4, v5
> +	smt.vmadot1us v2, v4, v5
> +	smt.vmadot2u v2, v4, v5
> +	smt.vmadot2 v2, v4, v5
> +	smt.vmadot2su v2, v4, v5
> +	smt.vmadot2us v2, v4, v5
> +	smt.vmadot3u v2, v4, v5
> +	smt.vmadot3 v2, v4, v5
> +	smt.vmadot3su v2, v4, v5
> +	smt.vmadot3us v2, v4, v5
> +	smt.vmadot v2, v3, v4, i8
> +	smt.vmadotu v2, v3, v4, i8
> +	smt.vmadotsu v2, v3, v4, i8
> +	smt.vmadotus v2, v3, v4, i8
> +	smt.vmadot1u v2, v4, v5, i8
> +	smt.vmadot1 v2, v4, v5, i8
> +	smt.vmadot1su v2, v4, v5, i8
> +	smt.vmadot1us v2, v4, v5, i8
> +	smt.vmadot2u v2, v4, v5, i8
> +	smt.vmadot2 v2, v4, v5, i8
> +	smt.vmadot2su v2, v4, v5, i8
> +	smt.vmadot2us v2, v4, v5, i8
> +	smt.vmadot3u v2, v4, v5, i8
> +	smt.vmadot3 v2, v4, v5, i8
> +	smt.vmadot3su v2, v4, v5, i8
> +	smt.vmadot3us v2, v4, v5, i8
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index 6f2775c6152..31b7e7a06a7 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -3852,6 +3852,44 @@
>   #define MASK_MIPS_PAUSE  0xffffffff
>   #define MATCH_MIPS_PREF 0x0000000b
>   #define MASK_MIPS_PREF 0xe000707f
> +/* SpacemiT custom instruction.  */
> +/* Int Matrix Multiplicative Accumulation.  */
> +#define MATCH_SMT_VMADOT   0x8200302b
> +#define MASK_SMT_VMADOT    0x9e0070ff
> +#define MATCH_SMT_VMADOTU  0x8200002b
> +#define MASK_SMT_VMADOTU   0x9e0070ff
> +#define MATCH_SMT_VMADOTSU 0x8200202b
> +#define MASK_SMT_VMADOTSU  0x9e0070ff
> +#define MATCH_SMT_VMADOTUS 0x8200102b
> +#define MASK_SMT_VMADOTUS  0x9e0070ff
> +/* Int Sliding Window Multiplicative Accumulation.  */
> +/* Sliding Value = 1.  */
> +#define MATCH_SMT_VMADOT1U 0x8600002b
> +#define MASK_SMT_VMADOT1U  0x9e00f0ff
> +#define MATCH_SMT_VMADOT1  0x8600302b
> +#define MASK_SMT_VMADOT1   0x9e00f0ff
> +#define MATCH_SMT_VMADOT1SU 0x8600202b
> +#define MASK_SMT_VMADOT1SU 0x9e00f0ff
> +#define MATCH_SMT_VMADOT1US 0x8600102b
> +#define MASK_SMT_VMADOT1US 0x9e00f0ff
> +/* Sliding Value = 2.  */
> +#define MATCH_SMT_VMADOT2U 0x8600402b
> +#define MASK_SMT_VMADOT2U 0x9e00f0ff
> +#define MATCH_SMT_VMADOT2 0x8600702b
> +#define MASK_SMT_VMADOT2 0x9e00f0ff
> +#define MATCH_SMT_VMADOT2SU 0x8600602b
> +#define MASK_SMT_VMADOT2SU 0x9e00f0ff
> +#define MATCH_SMT_VMADOT2US 0x8600502b
> +#define MASK_SMT_VMADOT2US 0x9e00f0ff
> +/* Sliding Value = 3.  */
> +#define MATCH_SMT_VMADOT3U 0x8600802b
> +#define MASK_SMT_VMADOT3U 0x9e00f0ff
> +#define MATCH_SMT_VMADOT3 0x8600b02b
> +#define MASK_SMT_VMADOT3 0x9e00f0ff
> +#define MATCH_SMT_VMADOT3SU 0x8600a02b
> +#define MASK_SMT_VMADOT3SU 0x9e00f0ff
> +#define MATCH_SMT_VMADOT3US 0x8600902b
> +#define MASK_SMT_VMADOT3US 0x9e00f0ff
>   /* Unprivileged Counter/Timers CSR addresses.  */
>   #define CSR_CYCLE 0xc00
>   #define CSR_TIME 0xc01
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index de105f5df8b..3a32abfcf3c 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -419,6 +419,14 @@ static inline unsigned int riscv_insn_length (insn_t insn)
>   #define OP_MASK_MIPS_SDP_OFFSET25   0x3
>   #define OP_SH_MIPS_SDP_OFFSET25     25
>   
> +/* SpacemiT fields.  */
> +#define OP_MASK_SPACEMIT_IME_VD		0xf
> +#define OP_SH_SPACEMIT_IME_VD		8
> +#define OP_MASK_SPACEMIT_IME_VS1	0xf
> +#define OP_SH_SPACEMIT_IME_VS1		16
> +#define OP_MASK_SPACEMIT_IME_WI		0x3
> +#define OP_SH_SPACEMIT_IME_WI		29
> +
>   /* ABI names for selected x-registers.  */
>   
>   #define X_ZERO 0
> @@ -606,6 +614,7 @@ enum riscv_insn_class
>     INSN_CLASS_XMIPSCMOV,
>     INSN_CLASS_XMIPSEXECTL,
>     INSN_CLASS_XMIPSLSP,
> +  INSN_CLASS_XSMTVDOT,
>   };
>   
>   /* This structure holds information for a particular instruction.  */
> diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> index eda802ff420..93d41343772 100644
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -917,6 +917,39 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
>   		  goto undefined_modifier;
>   		}
>   	      break;
> +	    case 'p': /* Vendor-specific (SpacemiT) operands.  */
> +	      switch (*++oparg)
> +		{
> +		case 'V':
> +		  switch (*++oparg)
> +		    {
> +		    case 'd':
> +		      unsigned vd = EXTRACT_OPERAND (SPACEMIT_IME_VD, l) * 2;
> +		      print (info->stream, dis_style_register, "%s",
> +			     riscv_vecr_names_numeric[vd]);
> +		      break;
> +		    case 's':
> +		      unsigned vs = EXTRACT_OPERAND (SPACEMIT_IME_VS1, l) * 2;
> +		      print (info->stream, dis_style_register, "%s",
> +			     riscv_vecr_names_numeric[vs]);
> +		      break;
> +		    default:
> +		      goto undefined_modifier;
> +		    }
> +		  break;
> +		case 'w':
> +		  /* Xpw: optional data-width suffix, i8 only.  WI==3 (i8)
> +		     is the default and is omitted from the output.  */
> +		  {
> +		    unsigned wi = EXTRACT_OPERAND (SPACEMIT_IME_WI, l);
> +		    if (wi != 3)
> +		      goto undefined_modifier;
> +		  }
> +		  break;
> +		default:
> +		  goto undefined_modifier;
> +		}
> +	      break;
>   	    default:
>   	      goto undefined_modifier;
>   	    }
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index 54887c97880..417918bb6f6 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -3579,6 +3579,29 @@ const struct riscv_opcode riscv_opcodes[] =
>   {"mips.sdp", 0, INSN_CLASS_XMIPSLSP, "t,r,Xm^(s)", MATCH_MIPS_SDP, MASK_MIPS_SDP, match_opcode, 0 },
>   {"mips.swp", 0, INSN_CLASS_XMIPSLSP, "t,r,Xm&(s)", MATCH_MIPS_SWP, MASK_MIPS_SWP, match_opcode, 0 },
>   
> +/* SpacemiT custom instructions.  */
> +/* Int Matrix Multi-Accumulation.  */
> +{"smt.vmadot",   0, INSN_CLASS_XSMTVDOT, "XpVd,Vs,VtXpw", MATCH_SMT_VMADOT, MASK_SMT_VMADOT, match_opcode, 0 },
> +{"smt.vmadotu",  0, INSN_CLASS_XSMTVDOT, "XpVd,Vs,VtXpw", MATCH_SMT_VMADOTU, MASK_SMT_VMADOTU, match_opcode, 0 },
> +{"smt.vmadotsu", 0, INSN_CLASS_XSMTVDOT, "XpVd,Vs,VtXpw", MATCH_SMT_VMADOTSU, MASK_SMT_VMADOTSU, match_opcode, 0 },
> +{"smt.vmadotus", 0, INSN_CLASS_XSMTVDOT, "XpVd,Vs,VtXpw", MATCH_SMT_VMADOTUS, MASK_SMT_VMADOTUS, match_opcode, 0 },
> +/* Int Sliding Window Multi-Accumulation.  */
> +/* Sliding Value = 1.  */
> +{"smt.vmadot1u",  0, INSN_CLASS_XSMTVDOT, "XpVd,XpVs,VtXpw", MATCH_SMT_VMADOT1U, MASK_SMT_VMADOT1U, match_opcode, 0 },
> +{"smt.vmadot1",   0, INSN_CLASS_XSMTVDOT, "XpVd,XpVs,VtXpw", MATCH_SMT_VMADOT1, MASK_SMT_VMADOT1, match_opcode, 0 },
> +{"smt.vmadot1su", 0, INSN_CLASS_XSMTVDOT, "XpVd,XpVs,VtXpw", MATCH_SMT_VMADOT1SU, MASK_SMT_VMADOT1SU, match_opcode, 0 },
> +{"smt.vmadot1us", 0, INSN_CLASS_XSMTVDOT, "XpVd,XpVs,VtXpw", MATCH_SMT_VMADOT1US, MASK_SMT_VMADOT1US, match_opcode, 0 },
> +/* Sliding Value = 2.  */
> +{"smt.vmadot2u",  0, INSN_CLASS_XSMTVDOT, "XpVd,XpVs,VtXpw", MATCH_SMT_VMADOT2U, MASK_SMT_VMADOT2U, match_opcode, 0 },
> +{"smt.vmadot2",   0, INSN_CLASS_XSMTVDOT, "XpVd,XpVs,VtXpw", MATCH_SMT_VMADOT2, MASK_SMT_VMADOT2, match_opcode, 0 },
> +{"smt.vmadot2su", 0, INSN_CLASS_XSMTVDOT, "XpVd,XpVs,VtXpw", MATCH_SMT_VMADOT2SU, MASK_SMT_VMADOT2SU, match_opcode, 0 },
> +{"smt.vmadot2us", 0, INSN_CLASS_XSMTVDOT, "XpVd,XpVs,VtXpw", MATCH_SMT_VMADOT2US, MASK_SMT_VMADOT2US, match_opcode, 0 },
> +/* Sliding Value = 3.  */
> +{"smt.vmadot3u",  0, INSN_CLASS_XSMTVDOT, "XpVd,XpVs,VtXpw", MATCH_SMT_VMADOT3U, MASK_SMT_VMADOT3U, match_opcode, 0 },
> +{"smt.vmadot3",   0, INSN_CLASS_XSMTVDOT, "XpVd,XpVs,VtXpw", MATCH_SMT_VMADOT3, MASK_SMT_VMADOT3, match_opcode, 0 },
> +{"smt.vmadot3su", 0, INSN_CLASS_XSMTVDOT, "XpVd,XpVs,VtXpw", MATCH_SMT_VMADOT3SU, MASK_SMT_VMADOT3SU, match_opcode, 0 },
> +{"smt.vmadot3us", 0, INSN_CLASS_XSMTVDOT, "XpVd,XpVs,VtXpw", MATCH_SMT_VMADOT3US, MASK_SMT_VMADOT3US, match_opcode, 0 },
> +
>   /* Terminate the list.  */
>   {0, 0, INSN_CLASS_NONE, 0, 0, 0, 0, 0}
>   };

Reviewed-by: Jiawei <jiawei@iscas.ac.cn>


From haochen.jiang@intel.com  Wed Jun  3 07:47:06 2026
From: haochen.jiang@intel.com (Jiang, Haochen)
Date: Wed, 3 Jun 2026 07:47:06 +0000
Subject: [PATCH] x86: Support BHI_CTRL instruction
In-Reply-To: <IA4PR11MB9009997D9669A4442CFF024DEC132@IA4PR11MB9009.namprd11.prod.outlook.com>
References: <20260601062446.2367458-1-haochen.jiang@intel.com>
 <982f780d-c653-4a4d-bfa8-19bed76b1277@suse.com>
 <IA4PR11MB9009997D9669A4442CFF024DEC132@IA4PR11MB9009.namprd11.prod.outlook.com>
Message-ID: <SJ5PPF77D28E3C27FBB50DC50A27FB579D4EC132@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>

> From: Jiang, Haochen
> Sent: Wednesday, June 3, 2026 10:38 AM
> To: 'Jan Beulich' <jbeulich@suse.com>
> 
> > From: Jan Beulich <jbeulich@suse.com>
> > Sent: Tuesday, June 2, 2026 4:27 PM
> >
> > On 01.06.2026 08:24, Haochen Jiang wrote:
> >
> > > --- a/opcodes/i386-opc.tbl
> > > +++ b/opcodes/i386-opc.tbl
> > > @@ -3630,3 +3630,9 @@ vmovrs<bw>, 0xf26f, AVX10_2&MOVRS&x64,
> > Modrm|Masking|Map5|<bw:vexw>|Disp8ShiftVL
> > >  vmovrs<dq>, 0xf36f, AVX10_2&MOVRS&x64,
> >
> Modrm|Masking|Map5|<dq:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf,
> > { Xmmword|Ymmword|Zmmword|Unspecified|BaseIndex,
> > RegXMM|RegYMM|RegZMM }
> > >
> > >  // MOVRS instructions end.
> > > +
> > > +// BHI_CTRL insructions.
> > > +
> > > +ibhf, 0xf30f1ef8, BHI_CTRL, NoSuf|Size64, {}
> >
> > So Size64 is here to have REX.W emitted. The whitepaper isn't clear about
> APX
> > at all, though: Would REX2.W also have the same effect? (Whichever way it
> is,
> > this then perhaps also wants covering in the testsuite.)
> 
> No, it won't. The encoding is fixed. But a testcase is welcomed here to clarify.
> 

But you had a good point here, the current disassembler won't "reject" rex2.w
(i.e., not taking this back to nop from my understanding) and take it as rex.w.

This let me further wonder if a user input something like "{rex2} ibhf", should we
accept that? Let me double check that.

Thx,
Haochen

From jbeulich@suse.com  Wed Jun  3 08:08:21 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Wed, 3 Jun 2026 10:08:21 +0200
Subject: [PATCH] x86: Support BHI_CTRL instruction
In-Reply-To: <SJ5PPF77D28E3C27FBB50DC50A27FB579D4EC132@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>
References: <20260601062446.2367458-1-haochen.jiang@intel.com>
 <982f780d-c653-4a4d-bfa8-19bed76b1277@suse.com>
 <IA4PR11MB9009997D9669A4442CFF024DEC132@IA4PR11MB9009.namprd11.prod.outlook.com>
 <SJ5PPF77D28E3C27FBB50DC50A27FB579D4EC132@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>
Message-ID: <7b3974e9-d03e-4492-8663-8abb9e1ea5c8@suse.com>

On 03.06.2026 09:47, Jiang, Haochen wrote:
>> From: Jiang, Haochen
>> Sent: Wednesday, June 3, 2026 10:38 AM
>> To: 'Jan Beulich' <jbeulich@suse.com>
>>
>>> From: Jan Beulich <jbeulich@suse.com>
>>> Sent: Tuesday, June 2, 2026 4:27 PM
>>>
>>> On 01.06.2026 08:24, Haochen Jiang wrote:
>>>
>>>> --- a/opcodes/i386-opc.tbl
>>>> +++ b/opcodes/i386-opc.tbl
>>>> @@ -3630,3 +3630,9 @@ vmovrs<bw>, 0xf26f, AVX10_2&MOVRS&x64,
>>> Modrm|Masking|Map5|<bw:vexw>|Disp8ShiftVL
>>>>  vmovrs<dq>, 0xf36f, AVX10_2&MOVRS&x64,
>>>
>> Modrm|Masking|Map5|<dq:vexw>|Disp8ShiftVL|CheckOperandSize|NoSuf,
>>> { Xmmword|Ymmword|Zmmword|Unspecified|BaseIndex,
>>> RegXMM|RegYMM|RegZMM }
>>>>
>>>>  // MOVRS instructions end.
>>>> +
>>>> +// BHI_CTRL insructions.
>>>> +
>>>> +ibhf, 0xf30f1ef8, BHI_CTRL, NoSuf|Size64, {}
>>>
>>> So Size64 is here to have REX.W emitted. The whitepaper isn't clear about
>> APX
>>> at all, though: Would REX2.W also have the same effect? (Whichever way it
>> is,
>>> this then perhaps also wants covering in the testsuite.)
>>
>> No, it won't. The encoding is fixed. But a testcase is welcomed here to clarify.
> 
> But you had a good point here, the current disassembler won't "reject" rex2.w
> (i.e., not taking this back to nop from my understanding) and take it as rex.w.
> 
> This let me further wonder if a user input something like "{rex2} ibhf", should we
> accept that? Let me double check that.

We should accept it if the resulting encoding does what is intended / written.
According to Christian's reply REX2.W doesn't have the same effect, but I wonder
if it's really sensible that way. The W bits, whether encoded in REX or REX2,
really ought to have the same meaning as per the APX spec. Unless of course this
is indeed meant to be another special case besides PUSHP/POPP (when imo it would
be really nice if special cases were avoided whenever possible).

Jan

From haochen.jiang@intel.com  Wed Jun  3 08:16:10 2026
From: haochen.jiang@intel.com (Jiang, Haochen)
Date: Wed, 3 Jun 2026 08:16:10 +0000
Subject: [PATCH] x86: Support BHI_CTRL instruction
In-Reply-To: <7b3974e9-d03e-4492-8663-8abb9e1ea5c8@suse.com>
References: <20260601062446.2367458-1-haochen.jiang@intel.com>
 <982f780d-c653-4a4d-bfa8-19bed76b1277@suse.com>
 <IA4PR11MB9009997D9669A4442CFF024DEC132@IA4PR11MB9009.namprd11.prod.outlook.com>
 <SJ5PPF77D28E3C27FBB50DC50A27FB579D4EC132@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>
 <7b3974e9-d03e-4492-8663-8abb9e1ea5c8@suse.com>
Message-ID: <SJ5PPF77D28E3C295448A06B5215A8D0CCAEC132@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>

> From: Jan Beulich <jbeulich@suse.com>
> Sent: Wednesday, June 3, 2026 4:08 PM
> 
> On 03.06.2026 09:47, Jiang, Haochen wrote:
> >> From: Jiang, Haochen
> >> Sent: Wednesday, June 3, 2026 10:38 AM
> >> To: 'Jan Beulich' <jbeulich@suse.com>
> >>
> >>> From: Jan Beulich <jbeulich@suse.com>
> >>> Sent: Tuesday, June 2, 2026 4:27 PM
> >>>
> >>> So Size64 is here to have REX.W emitted. The whitepaper isn't clear about
> >> APX
> >>> at all, though: Would REX2.W also have the same effect? (Whichever way it
> >> is,
> >>> this then perhaps also wants covering in the testsuite.)
> >>
> >> No, it won't. The encoding is fixed. But a testcase is welcomed here to clarify.
> >
> > But you had a good point here, the current disassembler won't "reject" rex2.w
> > (i.e., not taking this back to nop from my understanding) and take it as rex.w.
> >
> > This let me further wonder if a user input something like "{rex2} ibhf", should we
> > accept that? Let me double check that.
> 
> We should accept it if the resulting encoding does what is intended / written.
> According to Christian's reply REX2.W doesn't have the same effect, but I wonder
> if it's really sensible that way. The W bits, whether encoded in REX or REX2,
> really ought to have the same meaning as per the APX spec. Unless of course this
> is indeed meant to be another special case besides PUSHP/POPP (when imo it
> would be really nice if special cases were avoided whenever possible).

I am confirming with arch team for these issues. This instruction seems to me
the first instruction we only borrowed W1 with no effect, other using REX.W1
at least implied operand size. This definitely needs some clarification.

Will come back to you all after I get a clear answer.

Thx,
Haochen

From amodra@gmail.com  Wed Jun  3 12:50:31 2026
From: amodra@gmail.com (Alan Modra)
Date: Wed, 3 Jun 2026 22:20:31 +0930
Subject: spu: .note.spu_name
Message-ID: <aiAjF5eqIvsEqZIg@squeak.grove.modra.org>

This fixes a bug with the .note.spu_name section flags, which were
made SEC_LOAD without SEC_ALLOC.  That combination doesn't really make
sense and led to odd layout behaviour.  In addition .note.spu_name
now uses the normal note alignment, with some tweaks to keep its file
offset 16 byte aligned.  This tends to work better in the testsuite
when the standard scripts are not used and the note is merged with
other notes.

bfd/
	* elf32-spu.c (spu_elf_create_sections): Remove SEC_LOAD from
	.note.spu_name, and align to 4 bytes.
	(spu_elf_fake_sections): Tweak .note.spu_name output section
	alignment for layout.
	(spu_elf_final_write_processing): New function.
	(elf_backend_final_write_processing): Define.
binutils/
	* testsuite/binutils-all/objcopy.exp (pr25662): Don't xfail spu.
ld/
	* testsuite/ld-elf/orphan-region.d: Don't xfail spu.
	* testsuite/ld-elf/pr23658-1e.d: Likewise.
	* testsuite/ld-scripts/provide-8.d: Likewise.
	* testsuite/ld-spu/ovl.d: Remove commented out old matches.
	Adjust expected overlay file offset.
	* testsuite/ld-spu/ovl2.d: Likewise.

diff --git a/bfd/elf32-spu.c b/bfd/elf32-spu.c
index 5f547b65443..9a9d3a0401c 100644
--- a/bfd/elf32-spu.c
+++ b/bfd/elf32-spu.c
@@ -583,10 +583,10 @@ spu_elf_create_sections (struct bfd_link_info *info)
       ibfd = info->input_bfds;
       /* This should really be SEC_LINKER_CREATED, but then we'd need
 	 to write out the section ourselves.  */
-      flags = SEC_LOAD | SEC_READONLY | SEC_HAS_CONTENTS | SEC_IN_MEMORY;
+      flags = SEC_READONLY | SEC_HAS_CONTENTS | SEC_IN_MEMORY;
       s = bfd_make_section_anyway_with_flags (ibfd, SPU_PTNOTE_SPUNAME, flags);
       if (s == NULL
-	  || !bfd_set_section_alignment (s, 4))
+	  || !bfd_set_section_alignment (s, 2))
 	return false;
       /* Because we didn't set SEC_LINKER_CREATED we need to set the
 	 proper section type.  */
@@ -5342,10 +5342,32 @@ spu_elf_fake_sections (bfd *obfd ATTRIBUTE_UNUSED,
 		       asection *sec)
 {
   if (strcmp (sec->name, SPU_PTNOTE_SPUNAME) == 0)
-    hdr->sh_type = SHT_NOTE;
+    {
+      hdr->sh_type = SHT_NOTE;
+      hdr->sh_addralign = 16;
+    }
   return true;
 }
 
+/* .note.spu_name is read by the PPU from the object, and possibly
+   needs the file offset to be aligned to 16 bytes.  We used to simply
+   call bfd_set_section_alignment to set the alignment to 16, but if
+   left like that it triggers a readelf warning.  Now for layout we
+   tweak the alignment to 16 in spu_elf_fake_sections, and restore it
+   to 4 here.  */
+
+static bool
+spu_elf_final_write_processing (bfd *abfd)
+{
+  asection *sec = bfd_get_section_by_name (abfd, SPU_PTNOTE_SPUNAME);
+  if (sec != NULL)
+    {
+      struct bfd_elf_section_data *esd = elf_section_data (sec);
+      esd->this_hdr.sh_addralign = 4;
+    }
+  return _bfd_elf_final_write_processing (abfd);
+}
+
 /* Tweak phdrs before writing them out.  */
 
 static bool
@@ -5539,6 +5561,7 @@ spu_elf_size_sections (bfd *obfd ATTRIBUTE_UNUSED, struct bfd_link_info *info)
 #define elf_backend_modify_headers		spu_elf_modify_headers
 #define elf_backend_init_file_header		spu_elf_init_file_header
 #define elf_backend_fake_sections		spu_elf_fake_sections
+#define elf_backend_final_write_processing	spu_elf_final_write_processing
 #define elf_backend_special_sections		spu_elf_special_sections
 #define bfd_elf32_bfd_final_link		spu_elf_final_link
 
diff --git a/binutils/testsuite/binutils-all/objcopy.exp b/binutils/testsuite/binutils-all/objcopy.exp
index c11b911df67..25e2a440967 100644
--- a/binutils/testsuite/binutils-all/objcopy.exp
+++ b/binutils/testsuite/binutils-all/objcopy.exp
@@ -1556,7 +1556,6 @@ run_dump_test "pr23633"
 run_dump_test "set-section-alignment"
 
 setup_xfail "hppa*-*-*"
-setup_xfail "spu-*-*"
 clear_xfail "hppa*64*-*-hpux*" "hppa*-*-linux*" "hppa*-*-lites*"
 clear_xfail "hppa*-*-*n*bsd*" "hppa*-*-*elf*"
 if { [istarget pdp11-*-*] } {
diff --git a/ld/testsuite/ld-elf/orphan-region.d b/ld/testsuite/ld-elf/orphan-region.d
index 13fb31fff9f..7be708ddcf6 100644
--- a/ld/testsuite/ld-elf/orphan-region.d
+++ b/ld/testsuite/ld-elf/orphan-region.d
@@ -1,9 +1,9 @@
 #source: orphan-region.s
 #ld: -T orphan-region.ld -N -z stack-size=0 --no-warn-rwx-segments
 #readelf: -S -l --wide
-#xfail: [uses_genelf] hppa*64*-*-hpux* spu-*-*
+#xfail: [uses_genelf] hppa*64*-*-hpux*
 # if not using elf.em, you don't get fancy orphan handling
-# spu twiddles LOAD range, hppa64 adds PHDR
+# hppa64 adds PHDR
 
 #...
   \[[ 0-9]+\] \.text[ \t]+PROGBITS[ \t]+0*40000000[ \t]+.*
diff --git a/ld/testsuite/ld-elf/pr23658-1e.d b/ld/testsuite/ld-elf/pr23658-1e.d
index dbb05e6293e..c331aa7c902 100644
--- a/ld/testsuite/ld-elf/pr23658-1e.d
+++ b/ld/testsuite/ld-elf/pr23658-1e.d
@@ -14,7 +14,7 @@
 #xfail: cr16-* crx-* visium-*
 # The following targets place .note.gnu.build-id in unusual places.
 #xfail: *-*-hpux*
-#xfail: arc*-* avr-* m68hc1*-* microblaze*-* nds32*-* spu-*-* xstormy16-*-*
+#xfail: arc*-* avr-* m68hc1*-* microblaze*-* nds32*-* xstormy16-*-*
 #noxfail: microblaze*-linux*
 
 #...
diff --git a/ld/testsuite/ld-scripts/provide-8.d b/ld/testsuite/ld-scripts/provide-8.d
index 250b0441479..a6136ad52d7 100644
--- a/ld/testsuite/ld-scripts/provide-8.d
+++ b/ld/testsuite/ld-scripts/provide-8.d
@@ -1,7 +1,7 @@
 #source: provide-5.s
 #ld: -T provide-8.t
 #nm: -B
-#xfail: mmix-*-* spu-*-*
+#xfail: mmix-*-*
 # Placing a symbol outside of the image isn't well-defined in PE.
 #notarget: *-*-pe *-*-mingw* *-*-cygwin
 
diff --git a/ld/testsuite/ld-spu/ovl.d b/ld/testsuite/ld-spu/ovl.d
index a0372a0e2fd..052a45fb074 100644
--- a/ld/testsuite/ld-spu/ovl.d
+++ b/ld/testsuite/ld-spu/ovl.d
@@ -70,30 +70,6 @@ Disassembly of section \.text:
 .*	ila	\$79,1076	# 434
 .*	bra?	.* <__ovly_load>.*
 
-#00000330 <00000000\.ovl_call\.f1_a1>:
-#.*	bra?sl	\$75,.* <__ovly_load>.*
-#.*00 04 04 00.*
-#
-#00000338 <00000000\.ovl_call\.f2_a1>:
-#.*	bra?sl	\$75,.* <__ovly_load>.*
-#.*00 04 04 04.*
-#
-#00000340 <00000000\.ovl_call\.f1_a2>:
-#.*	bra?sl	\$75,.* <__ovly_load>.*
-#.*00 08 04 00.*
-#
-#00000348 <00000000\.ovl_call\.f2_a2>:
-#.*	bra?sl	\$75,.* <__ovly_load>.*
-#.*00 08 04 24.*
-#
-#00000350 <00000000\.ovl_call\.f4_a1>:
-#.*	bra?sl	\$75,.* <__ovly_load>.*
-#.*00 04 04 10.*
-#
-#00000358 <00000000.ovl_call.14:8>:
-#.*	bra?sl	\$75,.* <__ovly_load>.*
-#.*00 08 04 34.*
-
 Disassembly of section \.ov_a1:
 
 00000400 <f1_a1>:
@@ -150,13 +126,11 @@ Disassembly of section .data:
 00000450 <_ovly_table>:
  450:	00 00 04 00 .*
  454:	00 00 00 20 .*
-# 458:	00 00 03 40 .*
- 458:	00 00 01 00 .*
+ 458:	00 00 00 e0 .*
  45c:	00 00 00 01 .*
  460:	00 00 04 00 .*
  464:	00 00 00 40 .*
-# 468:	00 00 03 60 .*
- 468:	00 00 01 20 .*
+ 468:	00 00 01 00 .*
  46c:	00 00 00 01 .*
 
 00000470 <_ovly_buf_table>:
diff --git a/ld/testsuite/ld-spu/ovl2.d b/ld/testsuite/ld-spu/ovl2.d
index b8570c069d1..a0921828907 100644
--- a/ld/testsuite/ld-spu/ovl2.d
+++ b/ld/testsuite/ld-spu/ovl2.d
@@ -103,13 +103,11 @@ Disassembly of section \.data:
 00000430 <_ovly_table>:
 .*00 00 04 00 .*
 .*00 00 00 20 .*
-#.*00 00 03 10 .*
-.*00 00 01 00 .*
+.*00 00 00 e0 .*
 .*00 00 00 01 .*
 .*00 00 04 00 .*
 .*00 00 00 20 .*
-#.*00 00 03 20 .*
-.*00 00 01 20 .*
+.*00 00 01 00 .*
 .*00 00 00 01 .*
 
 00000450 <_ovly_buf_table>:

-- 
Alan Modra

From ludloff@gmail.com  Wed Jun  3 20:07:15 2026
From: ludloff@gmail.com (Christian Ludloff)
Date: Wed, 3 Jun 2026 13:07:15 -0700
Subject: [PATCH] x86: Support BHI_CTRL instruction
In-Reply-To: <SJ5PPF77D28E3C295448A06B5215A8D0CCAEC132@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>
References: <20260601062446.2367458-1-haochen.jiang@intel.com>
 <982f780d-c653-4a4d-bfa8-19bed76b1277@suse.com>
 <IA4PR11MB9009997D9669A4442CFF024DEC132@IA4PR11MB9009.namprd11.prod.outlook.com>
 <SJ5PPF77D28E3C27FBB50DC50A27FB579D4EC132@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>
 <7b3974e9-d03e-4492-8663-8abb9e1ea5c8@suse.com>
 <SJ5PPF77D28E3C295448A06B5215A8D0CCAEC132@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>
Message-ID: <CAKSQd8VsEd9UD=bqc8w+HFs3LsySFOjrf+AmLV384cC_9pXwbg@mail.gmail.com>

On Wed, Jun 3, 2026 at 1:16?AM Jiang, Haochen <haochen.jiang@intel.com> wrote:
> I am confirming with arch team for these issues. This instruction seems to me
> the first instruction we only borrowed W1 with no effect, other using REX.W1
> at least implied operand size. This definitely needs some clarification.
>
> Will come back to you all after I get a clear answer.

Arguably RDSSP{D,Q} is a litmus test ? can it REX2 or EVEX?

--
C.

From amodra@gmail.com  Wed Jun  3 22:25:38 2026
From: amodra@gmail.com (Alan Modra)
Date: Thu, 4 Jun 2026 07:55:38 +0930
Subject: elflink.c: rename abfd and bed
Message-ID: <aiCp4lAJAByOOV_T@squeak.grove.modra.org>

This renames "abfd" function parameters to "obfd" when that parameter
is always the output bfd, and to "dynobj" when it is always the input
object used to attach dynamic sections.  "bed" variables which are set
to the output bfd or dynobj backend data are renamed to "obed".  (The
dynobj xvec must be the same as the output xvec, or bad things
happen.)  The idea is to make the use of bfd* parameter a little more
obvious when reading the source.

diff --git a/bfd/elflink.c b/bfd/elflink.c
index 100f13227c8..8d092266b88 100644
--- a/bfd/elflink.c
+++ b/bfd/elflink.c
@@ -60,8 +60,8 @@ _bfd_elf_link_keep_memory (struct bfd_link_info *info)
      https://sourceware.org/bugzilla/show_bug.cgi?id=31458
 
      this is opt-in by each backend.  */
-  elf_backend_data *bed = get_elf_backend_data (info->output_bfd);
-  if (bed != NULL && bed->use_mmap)
+  elf_backend_data *obed = get_elf_backend_data (info->output_bfd);
+  if (obed->use_mmap)
     return false;
 #endif
   bfd *abfd;
@@ -185,14 +185,14 @@ _bfd_elf_section_for_symbol (struct elf_reloc_cookie *cookie,
 /* Define a symbol in a dynamic linkage section.  */
 
 struct elf_link_hash_entry *
-_bfd_elf_define_linkage_sym (bfd *abfd,
+_bfd_elf_define_linkage_sym (bfd *dynobj,
 			     struct bfd_link_info *info,
 			     asection *sec,
 			     const char *name)
 {
   struct elf_link_hash_entry *h;
   struct bfd_link_hash_entry *bh;
-  elf_backend_data *bed;
+  elf_backend_data *obed;
 
   h = elf_link_hash_lookup (elf_hash_table (info), name, false, false, false);
   if (h != NULL)
@@ -207,9 +207,9 @@ _bfd_elf_define_linkage_sym (bfd *abfd,
   else
     bh = NULL;
 
-  bed = get_elf_backend_data (abfd);
-  if (!_bfd_generic_link_add_one_symbol (info, abfd, name, BSF_GLOBAL,
-					 sec, 0, NULL, false, bed->collect,
+  obed = get_elf_backend_data (dynobj);
+  if (!_bfd_generic_link_add_one_symbol (info, dynobj, name, BSF_GLOBAL,
+					 sec, 0, NULL, false, obed->collect,
 					 &bh))
     return NULL;
   h = (struct elf_link_hash_entry *) bh;
@@ -221,62 +221,62 @@ _bfd_elf_define_linkage_sym (bfd *abfd,
   if (ELF_ST_VISIBILITY (h->other) != STV_INTERNAL)
     h->other = (h->other & ~ELF_ST_VISIBILITY (-1)) | STV_HIDDEN;
 
-  (*bed->elf_backend_hide_symbol) (info, h, true);
+  obed->elf_backend_hide_symbol (info, h, true);
   return h;
 }
 
 bool
-_bfd_elf_create_got_section (bfd *abfd, struct bfd_link_info *info)
+_bfd_elf_create_got_section (bfd *dynobj, struct bfd_link_info *info)
 {
   flagword flags;
   asection *s;
   struct elf_link_hash_entry *h;
-  elf_backend_data *bed = get_elf_backend_data (abfd);
+  elf_backend_data *obed = get_elf_backend_data (dynobj);
   struct elf_link_hash_table *htab = elf_hash_table (info);
 
   /* This function may be called more than once.  */
   if (htab->sgot != NULL)
     return true;
 
-  flags = bed->dynamic_sec_flags;
+  flags = obed->dynamic_sec_flags;
 
-  s = bfd_make_section_anyway_with_flags (abfd, ".got", flags);
+  s = bfd_make_section_anyway_with_flags (dynobj, ".got", flags);
   if (s == NULL
-      || !bfd_set_section_alignment (s, bed->s->log_file_align))
+      || !bfd_set_section_alignment (s, obed->s->log_file_align))
     return false;
   htab->sgot = s;
 
-  if (bed->want_got_plt)
+  if (obed->want_got_plt)
     {
-      s = bfd_make_section_anyway_with_flags (abfd, ".got.plt", flags);
+      s = bfd_make_section_anyway_with_flags (dynobj, ".got.plt", flags);
       if (s == NULL
-	  || !bfd_set_section_alignment (s, bed->s->log_file_align))
+	  || !bfd_set_section_alignment (s, obed->s->log_file_align))
 	return false;
       htab->sgotplt = s;
     }
 
   /* The first bit of the global offset table is the header.  */
-  s->size += bed->got_header_size;
+  s->size += obed->got_header_size;
 
-  if (bed->want_got_sym)
+  if (obed->want_got_sym)
     {
       /* Define the symbol _GLOBAL_OFFSET_TABLE_ at the start of the .got
 	 (or .got.plt) section.  We don't do this in the linker script
 	 because we don't want to define the symbol if we are not creating
 	 a global offset table.  */
-      h = _bfd_elf_define_linkage_sym (abfd, info, s,
+      h = _bfd_elf_define_linkage_sym (dynobj, info, s,
 				       "_GLOBAL_OFFSET_TABLE_");
       elf_hash_table (info)->hgot = h;
       if (h == NULL)
 	return false;
     }
 
-  s = bfd_make_section_anyway_with_flags (abfd,
-					  (bed->rela_plts_and_copies_p
+  s = bfd_make_section_anyway_with_flags (dynobj,
+					  (obed->rela_plts_and_copies_p
 					   ? ".rela.got" : ".rel.got"),
 					  flags | SEC_READONLY);
   if (s == NULL
-      || !bfd_set_section_alignment (s, bed->s->log_file_align))
+      || !bfd_set_section_alignment (s, obed->s->log_file_align))
     return false;
   htab->srelgot = s;
 
@@ -336,7 +336,8 @@ bfd_elf_link_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info)
 {
   flagword flags;
   asection *s;
-  elf_backend_data *bed;
+  bfd *dynobj;
+  elf_backend_data *obed;
   struct elf_link_hash_entry *h;
 
   if (! is_elf_hash_table (info->hash))
@@ -348,16 +349,16 @@ bfd_elf_link_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info)
   if (!_bfd_elf_link_create_dynstrtab (abfd, info))
     return false;
 
-  abfd = elf_hash_table (info)->dynobj;
-  bed = get_elf_backend_data (abfd);
+  dynobj = elf_hash_table (info)->dynobj;
+  obed = get_elf_backend_data (dynobj);
 
-  flags = bed->dynamic_sec_flags;
+  flags = obed->dynamic_sec_flags;
 
   /* A dynamically linked executable has a .interp section, but a
      shared library does not.  */
   if (bfd_link_executable (info) && !info->nointerp)
     {
-      s = bfd_make_section_anyway_with_flags (abfd, ".interp",
+      s = bfd_make_section_anyway_with_flags (dynobj, ".interp",
 					      flags | SEC_READONLY);
       if (s == NULL)
 	return false;
@@ -366,39 +367,39 @@ bfd_elf_link_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info)
 
   /* Create sections to hold version informations.  These are removed
      if they are not needed.  */
-  s = bfd_make_section_anyway_with_flags (abfd, ".gnu.version_d",
+  s = bfd_make_section_anyway_with_flags (dynobj, ".gnu.version_d",
 					  flags | SEC_READONLY);
   if (s == NULL
-      || !bfd_set_section_alignment (s, bed->s->log_file_align))
+      || !bfd_set_section_alignment (s, obed->s->log_file_align))
     return false;
 
-  s = bfd_make_section_anyway_with_flags (abfd, ".gnu.version",
+  s = bfd_make_section_anyway_with_flags (dynobj, ".gnu.version",
 					  flags | SEC_READONLY);
   if (s == NULL
       || !bfd_set_section_alignment (s, 1))
     return false;
 
-  s = bfd_make_section_anyway_with_flags (abfd, ".gnu.version_r",
+  s = bfd_make_section_anyway_with_flags (dynobj, ".gnu.version_r",
 					  flags | SEC_READONLY);
   if (s == NULL
-      || !bfd_set_section_alignment (s, bed->s->log_file_align))
+      || !bfd_set_section_alignment (s, obed->s->log_file_align))
     return false;
 
-  s = bfd_make_section_anyway_with_flags (abfd, ".dynsym",
+  s = bfd_make_section_anyway_with_flags (dynobj, ".dynsym",
 					  flags | SEC_READONLY);
   if (s == NULL
-      || !bfd_set_section_alignment (s, bed->s->log_file_align))
+      || !bfd_set_section_alignment (s, obed->s->log_file_align))
     return false;
   elf_hash_table (info)->dynsym = s;
 
-  s = bfd_make_section_anyway_with_flags (abfd, ".dynstr",
+  s = bfd_make_section_anyway_with_flags (dynobj, ".dynstr",
 					  flags | SEC_READONLY);
   if (s == NULL)
     return false;
 
-  s = bfd_make_section_anyway_with_flags (abfd, ".dynamic", flags);
+  s = bfd_make_section_anyway_with_flags (dynobj, ".dynamic", flags);
   if (s == NULL
-      || !bfd_set_section_alignment (s, bed->s->log_file_align))
+      || !bfd_set_section_alignment (s, obed->s->log_file_align))
     return false;
   elf_hash_table (info)->dynamic = s;
 
@@ -408,32 +409,32 @@ bfd_elf_link_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info)
      section.  We don't want to define it if there is no .dynamic
      section, since on some ELF platforms the start up code examines it
      to decide how to initialize the process.  */
-  h = _bfd_elf_define_linkage_sym (abfd, info, s, "_DYNAMIC");
+  h = _bfd_elf_define_linkage_sym (dynobj, info, s, "_DYNAMIC");
   elf_hash_table (info)->hdynamic = h;
   if (h == NULL)
     return false;
 
   if (info->emit_hash)
     {
-      s = bfd_make_section_anyway_with_flags (abfd, ".hash",
+      s = bfd_make_section_anyway_with_flags (dynobj, ".hash",
 					      flags | SEC_READONLY);
       if (s == NULL
-	  || !bfd_set_section_alignment (s, bed->s->log_file_align))
+	  || !bfd_set_section_alignment (s, obed->s->log_file_align))
 	return false;
-      elf_section_data (s)->this_hdr.sh_entsize = bed->s->sizeof_hash_entry;
+      elf_section_data (s)->this_hdr.sh_entsize = obed->s->sizeof_hash_entry;
     }
 
-  if (info->emit_gnu_hash && bed->record_xhash_symbol == NULL)
+  if (info->emit_gnu_hash && obed->record_xhash_symbol == NULL)
     {
-      s = bfd_make_section_anyway_with_flags (abfd, ".gnu.hash",
+      s = bfd_make_section_anyway_with_flags (dynobj, ".gnu.hash",
 					      flags | SEC_READONLY);
       if (s == NULL
-	  || !bfd_set_section_alignment (s, bed->s->log_file_align))
+	  || !bfd_set_section_alignment (s, obed->s->log_file_align))
 	return false;
       /* For 64-bit ELF, .gnu.hash is a non-uniform entity size section:
 	 4 32-bit words followed by variable count of 64-bit words, then
 	 variable count of 32-bit words.  */
-      if (bed->s->arch_size == 64)
+      if (obed->s->arch_size == 64)
 	elf_section_data (s)->this_hdr.sh_entsize = 0;
       else
 	elf_section_data (s)->this_hdr.sh_entsize = 4;
@@ -441,10 +442,10 @@ bfd_elf_link_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info)
 
   if (info->enable_dt_relr)
     {
-      s = bfd_make_section_anyway_with_flags (abfd, ".relr.dyn",
+      s = bfd_make_section_anyway_with_flags (dynobj, ".relr.dyn",
 					      flags | SEC_READONLY);
       if (s == NULL
-	  || !bfd_set_section_alignment (s, bed->s->log_file_align))
+	  || !bfd_set_section_alignment (s, obed->s->log_file_align))
 	return false;
       elf_hash_table (info)->srelrdyn = s;
     }
@@ -452,8 +453,8 @@ bfd_elf_link_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info)
   /* Let the backend create the rest of the sections.  This lets the
      backend set the right flags.  The backend will normally create
      the .got and .plt sections.  */
-  if (bed->elf_backend_create_dynamic_sections == NULL
-      || ! (*bed->elf_backend_create_dynamic_sections) (abfd, info))
+  if (obed->elf_backend_create_dynamic_sections == NULL
+      || !obed->elf_backend_create_dynamic_sections (dynobj, info))
     return false;
 
   elf_hash_table (info)->dynamic_sections_created = true;
@@ -464,59 +465,59 @@ bfd_elf_link_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info)
 /* Create dynamic sections when linking against a dynamic object.  */
 
 bool
-_bfd_elf_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info)
+_bfd_elf_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
 {
   flagword flags, pltflags;
   struct elf_link_hash_entry *h;
   asection *s;
-  elf_backend_data *bed = get_elf_backend_data (abfd);
+  elf_backend_data *obed = get_elf_backend_data (dynobj);
   struct elf_link_hash_table *htab = elf_hash_table (info);
 
   /* We need to create .plt, .rel[a].plt, .got, .got.plt, .dynbss, and
      .rel[a].bss sections.  */
-  flags = bed->dynamic_sec_flags;
+  flags = obed->dynamic_sec_flags;
 
   pltflags = flags;
-  if (bed->plt_not_loaded)
+  if (obed->plt_not_loaded)
     /* We do not clear SEC_ALLOC here because we still want the OS to
        allocate space for the section; it's just that there's nothing
        to read in from the object file.  */
     pltflags &= ~ (SEC_CODE | SEC_LOAD | SEC_HAS_CONTENTS);
   else
     pltflags |= SEC_ALLOC | SEC_CODE | SEC_LOAD;
-  if (bed->plt_readonly)
+  if (obed->plt_readonly)
     pltflags |= SEC_READONLY;
 
-  s = bfd_make_section_anyway_with_flags (abfd, ".plt", pltflags);
+  s = bfd_make_section_anyway_with_flags (dynobj, ".plt", pltflags);
   if (s == NULL
-      || !bfd_set_section_alignment (s, bed->plt_alignment))
+      || !bfd_set_section_alignment (s, obed->plt_alignment))
     return false;
   htab->splt = s;
 
   /* Define the symbol _PROCEDURE_LINKAGE_TABLE_ at the start of the
      .plt section.  */
-  if (bed->want_plt_sym)
+  if (obed->want_plt_sym)
     {
-      h = _bfd_elf_define_linkage_sym (abfd, info, s,
+      h = _bfd_elf_define_linkage_sym (dynobj, info, s,
 				       "_PROCEDURE_LINKAGE_TABLE_");
       elf_hash_table (info)->hplt = h;
       if (h == NULL)
 	return false;
     }
 
-  s = bfd_make_section_anyway_with_flags (abfd,
-					  (bed->rela_plts_and_copies_p
+  s = bfd_make_section_anyway_with_flags (dynobj,
+					  (obed->rela_plts_and_copies_p
 					   ? ".rela.plt" : ".rel.plt"),
 					  flags | SEC_READONLY);
   if (s == NULL
-      || !bfd_set_section_alignment (s, bed->s->log_file_align))
+      || !bfd_set_section_alignment (s, obed->s->log_file_align))
     return false;
   htab->srelplt = s;
 
-  if (! _bfd_elf_create_got_section (abfd, info))
+  if (! _bfd_elf_create_got_section (dynobj, info))
     return false;
 
-  if (bed->want_dynbss)
+  if (obed->want_dynbss)
     {
       /* The .dynbss section is a place to put symbols which are defined
 	 by dynamic objects, are referenced by regular objects, and are
@@ -524,18 +525,18 @@ _bfd_elf_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info)
 	 image and use a R_*_COPY reloc to tell the dynamic linker to
 	 initialize them at run time.  The linker script puts the .dynbss
 	 section into the .bss section of the final image.  */
-      s = bfd_make_section_anyway_with_flags (abfd, ".dynbss",
+      s = bfd_make_section_anyway_with_flags (dynobj, ".dynbss",
 					      SEC_ALLOC | SEC_LINKER_CREATED);
       if (s == NULL)
 	return false;
       htab->sdynbss = s;
 
-      if (bed->want_dynrelro)
+      if (obed->want_dynrelro)
 	{
 	  /* Similarly, but for symbols that were originally in read-only
 	     sections.  This section doesn't really need to have contents,
 	     but make it like other .data.rel.ro sections.  */
-	  s = bfd_make_section_anyway_with_flags (abfd, ".data.rel.ro",
+	  s = bfd_make_section_anyway_with_flags (dynobj, ".data.rel.ro",
 						  flags);
 	  if (s == NULL)
 	    return false;
@@ -555,23 +556,23 @@ _bfd_elf_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info)
 	 copy relocs.  */
       if (bfd_link_executable (info))
 	{
-	  s = bfd_make_section_anyway_with_flags (abfd,
-						  (bed->rela_plts_and_copies_p
+	  s = bfd_make_section_anyway_with_flags (dynobj,
+						  (obed->rela_plts_and_copies_p
 						   ? ".rela.bss" : ".rel.bss"),
 						  flags | SEC_READONLY);
 	  if (s == NULL
-	      || !bfd_set_section_alignment (s, bed->s->log_file_align))
+	      || !bfd_set_section_alignment (s, obed->s->log_file_align))
 	    return false;
 	  htab->srelbss = s;
 
-	  if (bed->want_dynrelro)
+	  if (obed->want_dynrelro)
 	    {
 	      s = (bfd_make_section_anyway_with_flags
-		   (abfd, (bed->rela_plts_and_copies_p
-			   ? ".rela.data.rel.ro" : ".rel.data.rel.ro"),
+		   (dynobj, (obed->rela_plts_and_copies_p
+			     ? ".rela.data.rel.ro" : ".rel.data.rel.ro"),
 		    flags | SEC_READONLY));
 	      if (s == NULL
-		  || !bfd_set_section_alignment (s, bed->s->log_file_align))
+		  || !bfd_set_section_alignment (s, obed->s->log_file_align))
 		return false;
 	      htab->sreldynrelro = s;
 	    }
@@ -712,7 +713,7 @@ bfd_elf_record_link_assignment (bfd *output_bfd,
 {
   struct elf_link_hash_entry *h, *hv;
   struct elf_link_hash_table *htab;
-  elf_backend_data *bed;
+  elf_backend_data *obed;
 
   if (!is_elf_hash_table (info->hash))
     return true;
@@ -766,7 +767,7 @@ bfd_elf_record_link_assignment (bfd *output_bfd,
     case bfd_link_hash_indirect:
       /* We had a versioned symbol in a dynamic library.  We make the
 	 the versioned symbol point to this one.  */
-      bed = get_elf_backend_data (output_bfd);
+      obed = get_elf_backend_data (output_bfd);
       hv = h;
       while (hv->root.type == bfd_link_hash_indirect
 	     || hv->root.type == bfd_link_hash_warning)
@@ -776,7 +777,7 @@ bfd_elf_record_link_assignment (bfd *output_bfd,
       h->root.type = bfd_link_hash_undefined;
       hv->root.type = bfd_link_hash_indirect;
       hv->root.u.i.link = (struct bfd_link_hash_entry *) h;
-      (*bed->elf_backend_copy_indirect_symbol) (info, h, hv);
+      obed->elf_backend_copy_indirect_symbol (info, h, hv);
       break;
     default:
       BFD_FAIL ();
@@ -806,10 +807,10 @@ bfd_elf_record_link_assignment (bfd *output_bfd,
 
   if (hidden)
     {
-      bed = get_elf_backend_data (output_bfd);
+      obed = get_elf_backend_data (output_bfd);
       if (ELF_ST_VISIBILITY (h->other) != STV_INTERNAL)
 	h->other = (h->other & ~ELF_ST_VISIBILITY (-1)) | STV_HIDDEN;
-      (*bed->elf_backend_hide_symbol) (info, h, true);
+      obed->elf_backend_hide_symbol (info, h, true);
     }
 
   /* STV_HIDDEN and STV_INTERNAL symbols must be STB_LOCAL in shared objects
@@ -1048,13 +1049,13 @@ _bfd_elf_link_renumber_dynsyms (bfd *output_bfd,
   if (bfd_link_pic (info)
       || elf_hash_table (info)->is_relocatable_executable)
     {
-      elf_backend_data *bed = get_elf_backend_data (output_bfd);
+      elf_backend_data *obed = get_elf_backend_data (output_bfd);
       asection *p;
       for (p = output_bfd->sections; p ; p = p->next)
 	if ((p->flags & SEC_EXCLUDE) == 0
 	    && (p->flags & SEC_ALLOC) != 0
 	    && elf_hash_table (info)->dynamic_relocs
-	    && !(*bed->elf_backend_omit_section_dynsym) (output_bfd, info, p))
+	    && !obed->elf_backend_omit_section_dynsym (output_bfd, info, p))
 	  {
 	    ++dynsymcount;
 	    if (do_sec)
@@ -1964,7 +1965,7 @@ _bfd_elf_add_default_symbol (bfd *abfd,
   char *shortname;
   struct elf_link_hash_entry *hi;
   struct bfd_link_hash_entry *bh;
-  elf_backend_data *bed;
+  elf_backend_data *obed;
   bool collect;
   bool dynamic;
   bfd *override;
@@ -2007,8 +2008,8 @@ _bfd_elf_add_default_symbol (bfd *abfd,
 	return true;
     }
 
-  bed = get_elf_backend_data (info->output_bfd);
-  collect = bed->collect;
+  obed = get_elf_backend_data (info->output_bfd);
+  collect = obed->collect;
   dynamic = (abfd->flags & DYNAMIC) != 0;
 
   shortlen = p - name;
@@ -2050,7 +2051,7 @@ _bfd_elf_add_default_symbol (bfd *abfd,
 					hi->root.root.string, &hide);
 	  if (hi->verinfo.vertree != NULL && hide)
 	    {
-	      (*bed->elf_backend_hide_symbol) (info, hi, true);
+	      obed->elf_backend_hide_symbol (info, hi, true);
 	      goto nondefault;
 	    }
 	}
@@ -2139,7 +2140,7 @@ _bfd_elf_add_default_symbol (bfd *abfd,
       struct elf_link_hash_entry *ht;
 
       ht = (struct elf_link_hash_entry *) hi->root.u.i.link;
-      (*bed->elf_backend_copy_indirect_symbol) (info, ht, hi);
+      obed->elf_backend_copy_indirect_symbol (info, ht, hi);
 
       /* If we first saw a reference to SHORTNAME with non-default
 	 visibility, merge that visibility to the @@VER symbol.  */
@@ -2238,7 +2239,7 @@ _bfd_elf_add_default_symbol (bfd *abfd,
      to the user in that case.  */
   if (hi->root.type == bfd_link_hash_indirect)
     {
-      (*bed->elf_backend_copy_indirect_symbol) (info, h, hi);
+      obed->elf_backend_copy_indirect_symbol (info, h, hi);
       h->ref_dynamic_nonweak |= hi->ref_dynamic_nonweak;
       hi->dynamic_def |= h->dynamic_def;
 
@@ -2605,7 +2606,7 @@ _bfd_elf_link_hide_sym_by_version (struct bfd_link_info *info,
 {
   const char *p;
   bool hide = false;
-  elf_backend_data *bed = get_elf_backend_data (info->output_bfd);
+  elf_backend_data *obed = get_elf_backend_data (info->output_bfd);
 
   /* Version script only hides symbols defined in regular objects.  */
   if (!h->def_regular && !ELF_COMMON_DEF_P (h))
@@ -2625,7 +2626,7 @@ _bfd_elf_link_hide_sym_by_version (struct bfd_link_info *info,
 	  && hide)
 	{
 	  if (hide)
-	    (*bed->elf_backend_hide_symbol) (info, h, true);
+	    obed->elf_backend_hide_symbol (info, h, true);
 	  return true;
 	}
     }
@@ -2639,7 +2640,7 @@ _bfd_elf_link_hide_sym_by_version (struct bfd_link_info *info,
 				    h->root.root.string, &hide);
       if (h->verinfo.vertree != NULL && hide)
 	{
-	  (*bed->elf_backend_hide_symbol) (info, h, true);
+	  obed->elf_backend_hide_symbol (info, h, true);
 	  return true;
 	}
     }
@@ -2657,7 +2658,7 @@ _bfd_elf_link_assign_sym_version (struct elf_link_hash_entry *h, void *data)
 {
   struct elf_info_failed *sinfo;
   struct bfd_link_info *info;
-  elf_backend_data *bed;
+  elf_backend_data *obed;
   struct elf_info_failed eif;
   const char *p;
   bool hide;
@@ -2675,7 +2676,7 @@ _bfd_elf_link_assign_sym_version (struct elf_link_hash_entry *h, void *data)
       return false;
     }
 
-  bed = get_elf_backend_data (info->output_bfd);
+  obed = get_elf_backend_data (info->output_bfd);
 
   /* We only need version numbers for symbols defined in regular
      objects.  */
@@ -2685,7 +2686,7 @@ _bfd_elf_link_assign_sym_version (struct elf_link_hash_entry *h, void *data)
       if ((h->root.type == bfd_link_hash_defined
 	   || h->root.type == bfd_link_hash_defweak)
 	  && discarded_section (h->root.u.def.section))
-	(*bed->elf_backend_hide_symbol) (info, h, true);
+	obed->elf_backend_hide_symbol (info, h, true);
       return true;
     }
 
@@ -2710,7 +2711,7 @@ _bfd_elf_link_assign_sym_version (struct elf_link_hash_entry *h, void *data)
 	}
 
       if (hide)
-	(*bed->elf_backend_hide_symbol) (info, h, true);
+	obed->elf_backend_hide_symbol (info, h, true);
 
       /* If we are building an application, we need to create a
 	 version node for this version.  */
@@ -2775,7 +2776,7 @@ _bfd_elf_link_assign_sym_version (struct elf_link_hash_entry *h, void *data)
 	= bfd_find_version_for_sym (sinfo->info->version_info,
 				    h->root.root.string, &hide);
       if (h->verinfo.vertree != NULL && hide)
-	(*bed->elf_backend_hide_symbol) (info, h, true);
+	obed->elf_backend_hide_symbol (info, h, true);
     }
 
   return true;
@@ -2984,7 +2985,7 @@ _bfd_elf_link_read_relocs (bfd *abfd,
    section header for a section containing relocations for O.  */
 
 static bool
-_bfd_elf_link_size_reloc_section (bfd *abfd,
+_bfd_elf_link_size_reloc_section (bfd *obfd,
 				  struct bfd_elf_section_reloc_data *reldata)
 {
   Elf_Internal_Shdr *rel_hdr = reldata->hdr;
@@ -2996,7 +2997,7 @@ _bfd_elf_link_size_reloc_section (bfd *abfd,
      allocate it with bfd_alloc rather than malloc.  Also since we
      cannot be sure that the contents will actually be filled in,
      we zero the allocated space.  */
-  rel_hdr->contents = (unsigned char *) bfd_zalloc (abfd, rel_hdr->sh_size);
+  rel_hdr->contents = bfd_zalloc (obfd, rel_hdr->sh_size);
   if (rel_hdr->contents == NULL && rel_hdr->sh_size != 0)
     return false;
 
@@ -3004,8 +3005,7 @@ _bfd_elf_link_size_reloc_section (bfd *abfd,
     {
       struct elf_link_hash_entry **p;
 
-      p = ((struct elf_link_hash_entry **)
-	   bfd_zmalloc (reldata->count * sizeof (*p)));
+      p = bfd_zmalloc (reldata->count * sizeof (*p));
       if (p == NULL)
 	return false;
 
@@ -3031,24 +3031,24 @@ _bfd_elf_link_output_relocs (bfd *output_bfd,
   bfd_byte *erel;
   struct bfd_elf_section_reloc_data *output_reldata;
   asection *output_section;
-  elf_backend_data *bed;
+  elf_backend_data *obed;
   void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
   struct bfd_elf_section_data *esdo;
 
   output_section = input_section->output_section;
 
-  bed = get_elf_backend_data (output_bfd);
+  obed = get_elf_backend_data (output_bfd);
   esdo = elf_section_data (output_section);
   if (esdo->rel.hdr && esdo->rel.hdr->sh_entsize == input_rel_hdr->sh_entsize)
     {
       output_reldata = &esdo->rel;
-      swap_out = bed->s->swap_reloc_out;
+      swap_out = obed->s->swap_reloc_out;
     }
   else if (esdo->rela.hdr
 	   && esdo->rela.hdr->sh_entsize == input_rel_hdr->sh_entsize)
     {
       output_reldata = &esdo->rela;
-      swap_out = bed->s->swap_reloca_out;
+      swap_out = obed->s->swap_reloca_out;
     }
   else
     {
@@ -3064,13 +3064,13 @@ _bfd_elf_link_output_relocs (bfd *output_bfd,
   erel += output_reldata->count * input_rel_hdr->sh_entsize;
   irela = internal_relocs;
   irelaend = irela + (NUM_SHDR_ENTRIES (input_rel_hdr)
-		      * bed->s->int_rels_per_ext_rel);
+		      * obed->s->int_rels_per_ext_rel);
   while (irela < irelaend)
     {
       if (rel_hash && *rel_hash)
 	(*rel_hash)->has_reloc = 1;
       (*swap_out) (output_bfd, irela, erel);
-      irela += bed->s->int_rels_per_ext_rel;
+      irela += obed->s->int_rels_per_ext_rel;
       erel += input_rel_hdr->sh_entsize;
       if (rel_hash)
 	rel_hash++;
@@ -3107,7 +3107,7 @@ static bool
 _bfd_elf_fix_symbol_flags (struct elf_link_hash_entry *h,
 			   struct elf_info_failed *eif)
 {
-  elf_backend_data *bed;
+  elf_backend_data *obed;
 
   /* If this symbol was mentioned in a non-ELF file, try to set
      DEF_REGULAR and REF_REGULAR correctly.  This is the only way to
@@ -3168,9 +3168,9 @@ _bfd_elf_fix_symbol_flags (struct elf_link_hash_entry *h,
     }
 
   /* Backend specific symbol fixup.  */
-  bed = get_elf_backend_data (eif->info->output_bfd);
-  if (bed->elf_backend_fixup_symbol
-      && !(*bed->elf_backend_fixup_symbol) (eif->info, h))
+  obed = get_elf_backend_data (eif->info->output_bfd);
+  if (obed->elf_backend_fixup_symbol
+      && !obed->elf_backend_fixup_symbol (eif->info, h))
     return false;
 
   /* If this is a final link, and the symbol was defined as a common
@@ -3187,13 +3187,13 @@ _bfd_elf_fix_symbol_flags (struct elf_link_hash_entry *h,
 
   /* Symbols defined in discarded sections shouldn't be dynamic.  */
   if (h->root.type == bfd_link_hash_undefined && h->indx == -3)
-    (*bed->elf_backend_hide_symbol) (eif->info, h, true);
+    obed->elf_backend_hide_symbol (eif->info, h, true);
 
   /* If a weak undefined symbol has non-default visibility, we also
      hide it from the dynamic linker.  */
   else if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
 	   && h->root.type == bfd_link_hash_undefweak)
-    (*bed->elf_backend_hide_symbol) (eif->info, h, true);
+    obed->elf_backend_hide_symbol (eif->info, h, true);
 
   /* A hidden versioned symbol in executable should be forced local if
      it is is locally defined, not referenced by shared library and not
@@ -3204,7 +3204,7 @@ _bfd_elf_fix_symbol_flags (struct elf_link_hash_entry *h,
 	   && !h->dynamic
 	   && !h->ref_dynamic
 	   && h->def_regular)
-    (*bed->elf_backend_hide_symbol) (eif->info, h, true);
+    obed->elf_backend_hide_symbol (eif->info, h, true);
 
   /* If -Bsymbolic was used (which means to bind references to global
      symbols to the definition within the shared object), and this
@@ -3223,7 +3223,7 @@ _bfd_elf_fix_symbol_flags (struct elf_link_hash_entry *h,
 
       force_local = (ELF_ST_VISIBILITY (h->other) == STV_INTERNAL
 		     || ELF_ST_VISIBILITY (h->other) == STV_HIDDEN);
-      (*bed->elf_backend_hide_symbol) (eif->info, h, force_local);
+      obed->elf_backend_hide_symbol (eif->info, h, force_local);
     }
 
   /* If this is a weak defined symbol in a dynamic object, and we know
@@ -3257,7 +3257,7 @@ _bfd_elf_fix_symbol_flags (struct elf_link_hash_entry *h,
 	  BFD_ASSERT (h->root.type == bfd_link_hash_defined
 		      || h->root.type == bfd_link_hash_defweak);
 	  BFD_ASSERT (def->def_dynamic);
-	  (*bed->elf_backend_copy_indirect_symbol) (eif->info, def, h);
+	  obed->elf_backend_copy_indirect_symbol (eif->info, def, h);
 	}
     }
 
@@ -3273,7 +3273,7 @@ _bfd_elf_adjust_dynamic_symbol (struct elf_link_hash_entry *h, void *data)
 {
   struct elf_info_failed *eif = (struct elf_info_failed *) data;
   struct elf_link_hash_table *htab;
-  elf_backend_data *bed;
+  elf_backend_data *obed;
 
   if (! is_elf_hash_table (eif->info->hash))
     return false;
@@ -3290,12 +3290,12 @@ _bfd_elf_adjust_dynamic_symbol (struct elf_link_hash_entry *h, void *data)
   if (! _bfd_elf_fix_symbol_flags (h, eif))
     return false;
 
-  bed = get_elf_backend_data (htab->dynobj);
+  obed = get_elf_backend_data (htab->dynobj);
 
   if (h->root.type == bfd_link_hash_undefweak)
     {
       if (eif->info->dynamic_undefined_weak == 0)
-	(*bed->elf_backend_hide_symbol) (eif->info, h, true);
+	obed->elf_backend_hide_symbol (eif->info, h, true);
       else if (eif->info->dynamic_undefined_weak > 0
 	       && h->ref_regular
 	       && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
@@ -3393,7 +3393,7 @@ _bfd_elf_adjust_dynamic_symbol (struct elf_link_hash_entry *h, void *data)
       (_("warning: type and size of dynamic symbol `%s' are not defined"),
        h->root.root.string);
 
-  if (! (*bed->elf_backend_adjust_dynamic_symbol) (eif->info, h))
+  if (!obed->elf_backend_adjust_dynamic_symbol (eif->info, h))
     {
       eif->failed = true;
       return false;
@@ -3487,7 +3487,7 @@ _bfd_elf_dynamic_symbol_p (struct elf_link_hash_entry *h,
 			   bool not_local_protected)
 {
   bool binding_stays_local_p;
-  elf_backend_data *bed;
+  elf_backend_data *obed;
   struct elf_link_hash_table *hash_table;
 
   if (h == NULL)
@@ -3519,12 +3519,12 @@ _bfd_elf_dynamic_symbol_p (struct elf_link_hash_entry *h,
       if (!is_elf_hash_table (&hash_table->root))
 	return false;
 
-      bed = get_elf_backend_data (hash_table->dynobj);
+      obed = get_elf_backend_data (hash_table->dynobj);
 
       /* Proper resolution for function pointer equality may require
 	 that these symbols perhaps be resolved dynamically, even though
 	 we should be resolving them to the current module.  */
-      if (!not_local_protected || !bed->is_function_type (h->type))
+      if (!not_local_protected || !obed->is_function_type (h->type))
 	binding_stays_local_p = true;
       break;
 
@@ -3559,7 +3559,7 @@ _bfd_elf_symbol_refs_local_p (struct elf_link_hash_entry *h,
 			      struct bfd_link_info *info,
 			      bool local_protected)
 {
-  elf_backend_data *bed;
+  elf_backend_data *obed;
   struct elf_link_hash_table *hash_table;
 
   /* If it's a local sym, of course we resolve locally.  */
@@ -3607,14 +3607,14 @@ _bfd_elf_symbol_refs_local_p (struct elf_link_hash_entry *h,
   if (info->indirect_extern_access > 0)
     return true;
 
-  bed = get_elf_backend_data (hash_table->dynobj);
+  obed = get_elf_backend_data (hash_table->dynobj);
 
   /* If extern_protected_data is false, STV_PROTECTED non-function
      symbols are local.  */
   if ((!info->extern_protected_data
        || (info->extern_protected_data < 0
-	   && !bed->extern_protected_data))
-      && !bed->is_function_type (h->type))
+	   && !obed->extern_protected_data))
+      && !obed->is_function_type (h->type))
     return true;
 
   /* Function pointer equality tests may require that STV_PROTECTED
@@ -3655,7 +3655,7 @@ bfd_elf_tls_setup (bfd *obfd, struct bfd_link_info *info)
 
 /* Return TRUE iff this is a non-common, definition of a non-function symbol.  */
 static bool
-is_global_data_symbol_definition (bfd *abfd ATTRIBUTE_UNUSED,
+is_global_data_symbol_definition (bfd *abfd,
 				  Elf_Internal_Sym *sym)
 {
   elf_backend_data *bed;
@@ -3798,7 +3798,7 @@ _bfd_elf_add_dynamic_entry (struct bfd_link_info *info,
 			    bfd_vma val)
 {
   struct elf_link_hash_table *hash_table;
-  elf_backend_data *bed;
+  elf_backend_data *obed;
   asection *s;
   bfd_size_type newsize;
   bfd_byte *newcontents;
@@ -3811,18 +3811,18 @@ _bfd_elf_add_dynamic_entry (struct bfd_link_info *info,
   if (tag == DT_RELA || tag == DT_REL)
     hash_table->dynamic_relocs = true;
 
-  bed = get_elf_backend_data (hash_table->dynobj);
+  obed = get_elf_backend_data (hash_table->dynobj);
   s = hash_table->dynamic;
   BFD_ASSERT (s != NULL);
 
-  newsize = s->size + bed->s->sizeof_dyn;
+  newsize = s->size + obed->s->sizeof_dyn;
   newcontents = (bfd_byte *) bfd_realloc (s->contents, newsize);
   if (newcontents == NULL)
     return false;
 
   dyn.d_tag = tag;
   dyn.d_un.d_val = val;
-  bed->s->swap_dyn_out (hash_table->dynobj, &dyn, newcontents + s->size);
+  obed->s->swap_dyn_out (hash_table->dynobj, &dyn, newcontents + s->size);
 
   s->size = newsize;
   s->contents = newcontents;
@@ -3836,7 +3836,7 @@ bool
 _bfd_elf_strip_zero_sized_dynamic_sections (struct bfd_link_info *info)
 {
   struct elf_link_hash_table *hash_table;
-  elf_backend_data *bed;
+  elf_backend_data *obed;
   asection *s, *sdynamic, **pp;
   asection *rela_dyn, *rel_dyn;
   Elf_Internal_Dyn dyn;
@@ -3859,8 +3859,8 @@ _bfd_elf_strip_zero_sized_dynamic_sections (struct bfd_link_info *info)
   if (!sdynamic)
     return true;
 
-  bed = get_elf_backend_data (hash_table->dynobj);
-  swap_dyn_in = bed->s->swap_dyn_in;
+  obed = get_elf_backend_data (hash_table->dynobj);
+  swap_dyn_in = obed->s->swap_dyn_in;
 
   strip_zero_sized = false;
   strip_zero_sized_plt = false;
@@ -3900,7 +3900,7 @@ _bfd_elf_strip_zero_sized_dynamic_sections (struct bfd_link_info *info)
 	 extdyn < sdynamic->contents + sdynamic->size;
 	 extdyn = next)
       {
-	next = extdyn + bed->s->sizeof_dyn;
+	next = extdyn + obed->s->sizeof_dyn;
 	swap_dyn_in (hash_table->dynobj, extdyn, &dyn);
 	switch (dyn.d_tag)
 	  {
@@ -3950,19 +3950,19 @@ bfd_elf_add_dt_needed_tag (bfd *abfd, struct bfd_link_info *info)
   if (_bfd_elf_strtab_refcount (hash_table->dynstr, strindex) != 1)
     {
       asection *sdyn;
-      elf_backend_data *bed;
+      elf_backend_data *obed;
       bfd_byte *extdyn;
 
-      bed = get_elf_backend_data (hash_table->dynobj);
+      obed = get_elf_backend_data (hash_table->dynobj);
       sdyn = hash_table->dynamic;
       if (sdyn != NULL && sdyn->size != 0)
 	for (extdyn = sdyn->contents;
 	     extdyn < sdyn->contents + sdyn->size;
-	     extdyn += bed->s->sizeof_dyn)
+	     extdyn += obed->s->sizeof_dyn)
 	  {
 	    Elf_Internal_Dyn dyn;
 
-	    bed->s->swap_dyn_in (hash_table->dynobj, extdyn, &dyn);
+	    obed->s->swap_dyn_in (hash_table->dynobj, extdyn, &dyn);
 	    if (dyn.d_tag == DT_NEEDED
 		&& dyn.d_un.d_val == strindex)
 	      {
@@ -4087,7 +4087,7 @@ elf_finalize_dynstr (bfd *output_bfd, struct bfd_link_info *info)
   bfd *dynobj = hash_table->dynobj;
   asection *sdyn;
   bfd_size_type size;
-  elf_backend_data *bed;
+  elf_backend_data *obed;
   bfd_byte *extdyn;
 
   _bfd_elf_strtab_finalize (dynstr);
@@ -4098,18 +4098,18 @@ elf_finalize_dynstr (bfd *output_bfd, struct bfd_link_info *info)
   if (info->callbacks->examine_strtab)
     info->callbacks->examine_strtab (dynstr);
 
-  bed = get_elf_backend_data (dynobj);
+  obed = get_elf_backend_data (dynobj);
   sdyn = hash_table->dynamic;
   BFD_ASSERT (sdyn != NULL);
 
   /* Update all .dynamic entries referencing .dynstr strings.  */
   for (extdyn = sdyn->contents;
        extdyn < PTR_ADD (sdyn->contents, sdyn->size);
-       extdyn += bed->s->sizeof_dyn)
+       extdyn += obed->s->sizeof_dyn)
     {
       Elf_Internal_Dyn dyn;
 
-      bed->s->swap_dyn_in (dynobj, extdyn, &dyn);
+      obed->s->swap_dyn_in (dynobj, extdyn, &dyn);
       switch (dyn.d_tag)
 	{
 	case DT_STRSZ:
@@ -4128,7 +4128,7 @@ elf_finalize_dynstr (bfd *output_bfd, struct bfd_link_info *info)
 	default:
 	  continue;
 	}
-      bed->s->swap_dyn_out (dynobj, &dyn, extdyn);
+      obed->s->swap_dyn_out (dynobj, &dyn, extdyn);
     }
 
   /* Now update local dynamic symbols.  */
@@ -6702,7 +6702,7 @@ compute_bucket_count (struct bfd_link_info *info ATTRIBUTE_UNUSED,
       uint64_t best_chlen = ~((uint64_t) 0);
       bfd *dynobj = elf_hash_table (info)->dynobj;
       size_t dynsymcount = elf_hash_table (info)->dynsymcount;
-      elf_backend_data *bed = get_elf_backend_data (dynobj);
+      elf_backend_data *obed = get_elf_backend_data (dynobj);
       unsigned long int *counts;
       bfd_size_type amt;
       unsigned int no_improvement_count = 0;
@@ -6760,7 +6760,7 @@ compute_bucket_count (struct bfd_link_info *info ATTRIBUTE_UNUSED,
 
 	  /* We in any case need 2 + DYNSYMCOUNT entries for the size values
 	     and the chains.  */
-	  max = (2 + dynsymcount) * bed->s->sizeof_hash_entry;
+	  max = (2 + dynsymcount) * obed->s->sizeof_hash_entry;
 
 # if 1
 	  /* Variant 1: optimize for short chains.  We add the squares
@@ -6770,7 +6770,7 @@ compute_bucket_count (struct bfd_link_info *info ATTRIBUTE_UNUSED,
 	    max += counts[j] * counts[j];
 
 	  /* This adds penalties for the overall size of the table.  */
-	  fact = i / (BFD_TARGET_PAGESIZE / bed->s->sizeof_hash_entry) + 1;
+	  fact = i / (BFD_TARGET_PAGESIZE / obed->s->sizeof_hash_entry) + 1;
 	  max *= fact * fact;
 # else
 	  /* Variant 2: Optimize a lot more for small table.  Here we
@@ -6781,7 +6781,7 @@ compute_bucket_count (struct bfd_link_info *info ATTRIBUTE_UNUSED,
 
 	  /* The overall size of the table is considered, but not as
 	     strong as in variant 1, where it is squared.  */
-	  fact = i / (BFD_TARGET_PAGESIZE / bed->s->sizeof_hash_entry) + 1;
+	  fact = i / (BFD_TARGET_PAGESIZE / obed->s->sizeof_hash_entry) + 1;
 	  max *= fact;
 # endif
 
@@ -6942,7 +6942,7 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
 			       asection **sinterpptr)
 {
   bfd *dynobj;
-  elf_backend_data *bed;
+  elf_backend_data *obed;
 
   *sinterpptr = NULL;
 
@@ -6956,12 +6956,12 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
   elf_hash_table (info)->init_plt_refcount
     = elf_hash_table (info)->init_plt_offset;
 
-  bed = get_elf_backend_data (output_bfd);
+  obed = get_elf_backend_data (output_bfd);
 
   /* The backend may have to create some sections regardless of whether
      we're dynamic or not.  */
-  if (bed->elf_backend_early_size_sections
-      && !bed->elf_backend_early_size_sections (output_bfd, info))
+  if (obed->elf_backend_early_size_sections
+      && !obed->elf_backend_early_size_sections (output_bfd, info))
     return false;
 
   dynobj = elf_hash_table (info)->dynobj;
@@ -7323,14 +7323,14 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
 	}
     }
 
-  if (info->gc_sections && bed->can_gc_sections)
+  if (info->gc_sections && obed->can_gc_sections)
     {
       struct elf_gc_sweep_symbol_info sweep_info;
 
       /* Remove the symbols that were in the swept sections from the
 	 dynamic symbol table.  */
       sweep_info.info = info;
-      sweep_info.hide_symbol = bed->elf_backend_hide_symbol;
+      sweep_info.hide_symbol = obed->elf_backend_hide_symbol;
       elf_link_hash_traverse (elf_hash_table (info), elf_gc_sweep_symbol,
 			      &sweep_info);
     }
@@ -7357,7 +7357,7 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
       if (sinfo.failed)
 	return false;
 
-      bed->elf_backend_add_glibc_version_dependency (&sinfo);
+      obed->elf_backend_add_glibc_version_dependency (&sinfo);
       if (sinfo.failed)
 	return false;
 
@@ -7511,7 +7511,7 @@ warning: enabling an executable stack because of -z execstack command line optio
 		  break;
 		}
 	    }
-	  else if (bed->default_execstack && info->default_execstack)
+	  else if (obed->default_execstack && info->default_execstack)
 	    {
 	      exec = PF_X;
 	      emptyobj = inputobj;
@@ -7750,13 +7750,13 @@ NOTE: This behaviour is deprecated and will be removed in a future version of th
 	  if ((info->emit_hash
 	       && !_bfd_elf_add_dynamic_entry (info, DT_HASH, 0))
 	      || (info->emit_gnu_hash
-		  && (bed->record_xhash_symbol == NULL
+		  && (obed->record_xhash_symbol == NULL
 		      && !_bfd_elf_add_dynamic_entry (info, DT_GNU_HASH, 0)))
 	      || !_bfd_elf_add_dynamic_entry (info, DT_STRTAB, 0)
 	      || !_bfd_elf_add_dynamic_entry (info, DT_SYMTAB, 0)
 	      || !_bfd_elf_add_dynamic_entry (info, DT_STRSZ, strsize)
 	      || !_bfd_elf_add_dynamic_entry (info, DT_SYMENT,
-					      bed->s->sizeof_sym)
+					      obed->s->sizeof_sym)
 	      || (info->gnu_flags_1
 		  && !_bfd_elf_add_dynamic_entry (info, DT_GNU_FLAGS_1,
 						  info->gnu_flags_1)))
@@ -7769,8 +7769,8 @@ NOTE: This behaviour is deprecated and will be removed in a future version of th
 
   /* The backend must work out the sizes of all the other dynamic
      sections.  */
-  if (bed->elf_backend_late_size_sections != NULL
-      && !bed->elf_backend_late_size_sections (output_bfd, info))
+  if (obed->elf_backend_late_size_sections != NULL
+      && !obed->elf_backend_late_size_sections (output_bfd, info))
     return false;
 
   if (dynobj != NULL && elf_hash_table (info)->dynamic_sections_created)
@@ -7884,15 +7884,15 @@ _bfd_elf_init_2_index_sections (bfd *output_bfd, struct bfd_link_info *info)
 bool
 bfd_elf_size_dynsym_hash_dynstr (bfd *output_bfd, struct bfd_link_info *info)
 {
-  elf_backend_data *bed;
+  elf_backend_data *obed;
   unsigned long section_sym_count;
   bfd_size_type dynsymcount = 0;
 
   if (!is_elf_hash_table (info->hash))
     return true;
 
-  bed = get_elf_backend_data (output_bfd);
-  (*bed->elf_backend_init_index_section) (output_bfd, info);
+  obed = get_elf_backend_data (output_bfd);
+  obed->elf_backend_init_index_section (output_bfd, info);
 
   /* Assign dynsym indices.  In a shared library we generate a section
      symbol for each output section, which come first.  Next come all
@@ -7906,7 +7906,7 @@ bfd_elf_size_dynsym_hash_dynstr (bfd *output_bfd, struct bfd_link_info *info)
      data in that case, to satisfy those relocations).  */
 
   if (elf_hash_table (info)->dynamic_sections_created
-      || bed->always_renumber_dynsyms)
+      || obed->always_renumber_dynsyms)
     dynsymcount = _bfd_elf_link_renumber_dynsyms (output_bfd, info,
 						  &section_sym_count);
 
@@ -7941,7 +7941,7 @@ bfd_elf_size_dynsym_hash_dynstr (bfd *output_bfd, struct bfd_link_info *info)
 	 section as we went along in elf_link_add_object_symbols.  */
       s = elf_hash_table (info)->dynsym;
       BFD_ASSERT (s != NULL);
-      s->size = dynsymcount * bed->s->sizeof_sym;
+      s->size = dynsymcount * obed->s->sizeof_sym;
 
       s->contents = (unsigned char *) bfd_alloc (output_bfd, s->size);
       if (s->contents == NULL)
@@ -7951,7 +7951,7 @@ bfd_elf_size_dynsym_hash_dynstr (bfd *output_bfd, struct bfd_link_info *info)
       /* The first entry in .dynsym is a dummy symbol.  Clear all the
 	 section syms, in case we don't output them all.  */
       ++section_sym_count;
-      memset (s->contents, 0, section_sym_count * bed->s->sizeof_sym);
+      memset (s->contents, 0, section_sym_count * obed->s->sizeof_sym);
 
       elf_hash_table (info)->bucketcount = 0;
 
@@ -8030,7 +8030,7 @@ bfd_elf_size_dynsym_hash_dynstr (bfd *output_bfd, struct bfd_link_info *info)
 	  cinfo.hashval = cinfo.hashcodes + dynsymcount;
 	  cinfo.min_dynindx = -1;
 	  cinfo.output_bfd = output_bfd;
-	  cinfo.bed = bed;
+	  cinfo.bed = obed;
 
 	  /* Put all hash values in HASHCODES.  */
 	  elf_link_hash_traverse (elf_hash_table (info),
@@ -8050,7 +8050,7 @@ bfd_elf_size_dynsym_hash_dynstr (bfd *output_bfd, struct bfd_link_info *info)
 	      return false;
 	    }
 
-	  s = bfd_get_linker_section (dynobj, GNU_HASH_SECTION_NAME (bed));
+	  s = bfd_get_linker_section (dynobj, GNU_HASH_SECTION_NAME (obed));
 	  BFD_ASSERT (s != NULL);
 
 	  if (cinfo.nsyms == 0)
@@ -8058,7 +8058,7 @@ bfd_elf_size_dynsym_hash_dynstr (bfd *output_bfd, struct bfd_link_info *info)
 	      /* Empty .gnu.hash or .MIPS.xhash section is special.  */
 	      BFD_ASSERT (cinfo.min_dynindx == -1);
 	      free (cinfo.hashcodes);
-	      s->size = 5 * 4 + bed->s->arch_size / 8;
+	      s->size = 5 * 4 + obed->s->arch_size / 8;
 	      contents = (unsigned char *) bfd_zalloc (output_bfd, s->size);
 	      if (contents == NULL)
 		return false;
@@ -8073,10 +8073,10 @@ bfd_elf_size_dynsym_hash_dynstr (bfd *output_bfd, struct bfd_link_info *info)
 	      /* Only hash fn bloom filter.  */
 	      bfd_put_32 (output_bfd, 0, contents + 12);
 	      /* No hashes are valid - empty bitmask.  */
-	      bfd_put (bed->s->arch_size, output_bfd, 0, contents + 16);
+	      bfd_put (obed->s->arch_size, output_bfd, 0, contents + 16);
 	      /* No hashes in the only bucket.  */
 	      bfd_put_32 (output_bfd, 0,
-			  contents + 16 + bed->s->arch_size / 8);
+			  contents + 16 + obed->s->arch_size / 8);
 	    }
 	  else
 	    {
@@ -8093,7 +8093,7 @@ bfd_elf_size_dynsym_hash_dynstr (bfd *output_bfd, struct bfd_link_info *info)
 		maskbitslog2 = maskbitslog2 + 3;
 	      else
 		maskbitslog2 = maskbitslog2 + 2;
-	      if (bed->s->arch_size == 64)
+	      if (obed->s->arch_size == 64)
 		{
 		  if (maskbitslog2 == 5)
 		    maskbitslog2 = 6;
@@ -8136,7 +8136,7 @@ bfd_elf_size_dynsym_hash_dynstr (bfd *output_bfd, struct bfd_link_info *info)
 
 	      s->size = (4 + bucketcount + cinfo.nsyms) * 4;
 	      s->size += cinfo.maskbits / 8;
-	      if (bed->record_xhash_symbol != NULL)
+	      if (obed->record_xhash_symbol != NULL)
 		s->size += cinfo.nsyms * 4;
 	      contents = (unsigned char *) bfd_zalloc (output_bfd, s->size);
 	      if (contents == NULL)
@@ -8189,9 +8189,9 @@ bfd_elf_size_dynsym_hash_dynstr (bfd *output_bfd, struct bfd_link_info *info)
 	      contents = s->contents + 16;
 	      for (i = 0; i < maskwords; ++i)
 		{
-		  bfd_put (bed->s->arch_size, output_bfd, cinfo.bitmask[i],
+		  bfd_put (obed->s->arch_size, output_bfd, cinfo.bitmask[i],
 			   contents);
-		  contents += bed->s->arch_size / 8;
+		  contents += obed->s->arch_size / 8;
 		}
 
 	      free (cinfo.bitmask);
@@ -8373,12 +8373,12 @@ _bfd_elf_link_hide_symbol (bfd *output_bfd,
 {
   if (is_elf_hash_table (info->hash))
     {
-      elf_backend_data *bed = get_elf_backend_data (output_bfd);
+      elf_backend_data *obed = get_elf_backend_data (output_bfd);
       struct elf_link_hash_entry *eh = (struct elf_link_hash_entry *) h;
       eh->def_dynamic = 0;
       eh->ref_dynamic = 0;
       eh->dynamic_def = 0;
-      bed->elf_backend_hide_symbol (info, eh, true);
+      obed->elf_backend_hide_symbol (info, eh, true);
     }
 }
 
@@ -8388,15 +8388,15 @@ _bfd_elf_link_hide_symbol (bfd *output_bfd,
 bool
 _bfd_elf_link_hash_table_init
   (struct elf_link_hash_table *table,
-   bfd *abfd,
+   bfd *obfd,
    struct bfd_hash_entry *(*newfunc) (struct bfd_hash_entry *,
 				      struct bfd_hash_table *,
 				      const char *),
    unsigned int entsize)
 {
   bool ret;
-  elf_backend_data *bed = get_elf_backend_data (abfd);
-  int can_refcount = bed->can_refcount;
+  elf_backend_data *obed = get_elf_backend_data (obfd);
+  int can_refcount = obed->can_refcount;
 
   table->init_got_refcount.refcount = can_refcount - 1;
   table->init_plt_refcount.refcount = can_refcount - 1;
@@ -8405,11 +8405,11 @@ _bfd_elf_link_hash_table_init
   /* The first dynamic symbol is a dummy.  */
   table->dynsymcount = 1;
 
-  ret = _bfd_link_hash_table_init (&table->root, abfd, newfunc, entsize);
+  ret = _bfd_link_hash_table_init (&table->root, obfd, newfunc, entsize);
 
   table->root.type = bfd_link_elf_hash_table;
-  table->hash_table_id = bed->target_id;
-  table->target_os = bed->target_os;
+  table->hash_table_id = obed->target_id;
+  table->target_os = obed->target_os;
   table->root.hash_table_free = _bfd_elf_link_hash_table_free;
 
   return ret;
@@ -8418,7 +8418,7 @@ _bfd_elf_link_hash_table_init
 /* Create an ELF linker hash table.  */
 
 struct bfd_link_hash_table *
-_bfd_elf_link_hash_table_create (bfd *abfd)
+_bfd_elf_link_hash_table_create (bfd *obfd)
 {
   struct elf_link_hash_table *ret;
   size_t amt = sizeof (struct elf_link_hash_table);
@@ -8427,7 +8427,7 @@ _bfd_elf_link_hash_table_create (bfd *abfd)
   if (ret == NULL)
     return NULL;
 
-  if (! _bfd_elf_link_hash_table_init (ret, abfd, _bfd_elf_link_hash_newfunc,
+  if (! _bfd_elf_link_hash_table_init (ret, obfd, _bfd_elf_link_hash_newfunc,
 				       sizeof (struct elf_link_hash_entry)))
     {
       free (ret);
@@ -8471,11 +8471,11 @@ _bfd_elf_link_hash_table_free (bfd *obfd)
    entry for a dynamic object.  */
 
 void
-bfd_elf_set_dt_needed_name (bfd *abfd, const char *name)
+bfd_elf_set_dt_needed_name (bfd *obfd, const char *name)
 {
-  if (bfd_get_flavour (abfd) == bfd_target_elf_flavour
-      && bfd_get_format (abfd) == bfd_object)
-    elf_dt_name (abfd) = name;
+  if (bfd_get_flavour (obfd) == bfd_target_elf_flavour
+      && bfd_get_format (obfd) == bfd_object)
+    elf_dt_name (obfd) = name;
 }
 
 int
@@ -8502,7 +8502,7 @@ bfd_elf_set_dyn_lib_class (bfd *abfd, enum dynamic_lib_link_class lib_class)
    the linker ELF emulation code.  */
 
 struct bfd_link_needed_list *
-bfd_elf_get_needed_list (bfd *abfd ATTRIBUTE_UNUSED,
+bfd_elf_get_needed_list (bfd *obfd ATTRIBUTE_UNUSED,
 			 struct bfd_link_info *info)
 {
   if (! is_elf_hash_table (info->hash))
@@ -8514,7 +8514,7 @@ bfd_elf_get_needed_list (bfd *abfd ATTRIBUTE_UNUSED,
    hook for the linker ELF emulation code.  */
 
 struct bfd_link_needed_list *
-bfd_elf_get_runpath_list (bfd *abfd ATTRIBUTE_UNUSED,
+bfd_elf_get_runpath_list (bfd *obfd ATTRIBUTE_UNUSED,
 			  struct bfd_link_info *info)
 {
   if (! is_elf_hash_table (info->hash))
@@ -10029,7 +10029,7 @@ elf_link_sort_cmp2 (const void *A, const void *B)
 }
 
 static size_t
-elf_link_sort_relocs (bfd *abfd, struct bfd_link_info *info, asection **psec)
+elf_link_sort_relocs (bfd *obfd, struct bfd_link_info *info, asection **psec)
 {
   asection *dynamic_relocs;
   asection *rela_dyn;
@@ -10038,9 +10038,9 @@ elf_link_sort_relocs (bfd *abfd, struct bfd_link_info *info, asection **psec)
   size_t i, ret, sort_elt, ext_size;
   bfd_byte *sort, *s_non_relative, *p;
   struct elf_link_sort_rela *sq;
-  elf_backend_data *bed = get_elf_backend_data (abfd);
-  int i2e = bed->s->int_rels_per_ext_rel;
-  unsigned int opb = bfd_octets_per_byte (abfd, NULL);
+  elf_backend_data *obed = get_elf_backend_data (obfd);
+  int i2e = obed->s->int_rels_per_ext_rel;
+  unsigned int opb = bfd_octets_per_byte (obfd, NULL);
   void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
   void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
   struct bfd_link_order *lo;
@@ -10048,8 +10048,8 @@ elf_link_sort_relocs (bfd *abfd, struct bfd_link_info *info, asection **psec)
   bool use_rela;
 
   /* Find a dynamic reloc section.  */
-  rela_dyn = bfd_get_section_by_name (abfd, ".rela.dyn");
-  rel_dyn  = bfd_get_section_by_name (abfd, ".rel.dyn");
+  rela_dyn = bfd_get_section_by_name (obfd, ".rela.dyn");
+  rel_dyn  = bfd_get_section_by_name (obfd, ".rel.dyn");
   if (rela_dyn != NULL && rela_dyn->size > 0
       && rel_dyn != NULL && rel_dyn->size > 0)
     {
@@ -10066,9 +10066,9 @@ elf_link_sort_relocs (bfd *abfd, struct bfd_link_info *info, asection **psec)
 	  {
 	    asection *o = lo->u.indirect.section;
 
-	    if ((o->size % bed->s->sizeof_rela) == 0)
+	    if ((o->size % obed->s->sizeof_rela) == 0)
 	      {
-		if ((o->size % bed->s->sizeof_rel) == 0)
+		if ((o->size % obed->s->sizeof_rel) == 0)
 		  /* Section size is divisible by both rel and rela sizes.
 		     It is of no help to us.  */
 		  ;
@@ -10079,7 +10079,7 @@ elf_link_sort_relocs (bfd *abfd, struct bfd_link_info *info, asection **psec)
 		      {
 			_bfd_error_handler (_("%pB: unable to sort relocs - "
 					      "they are in more than one size"),
-					    abfd);
+					    obfd);
 			bfd_set_error (bfd_error_invalid_operation);
 			return 0;
 		      }
@@ -10090,14 +10090,14 @@ elf_link_sort_relocs (bfd *abfd, struct bfd_link_info *info, asection **psec)
 		      }
 		  }
 	      }
-	    else if ((o->size % bed->s->sizeof_rel) == 0)
+	    else if ((o->size % obed->s->sizeof_rel) == 0)
 	      {
 		/* Section size is only divisible by rel.  */
 		if (use_rela_initialised && use_rela)
 		  {
 		    _bfd_error_handler (_("%pB: unable to sort relocs - "
 					  "they are in more than one size"),
-					abfd);
+					obfd);
 		    bfd_set_error (bfd_error_invalid_operation);
 		    return 0;
 		  }
@@ -10112,7 +10112,7 @@ elf_link_sort_relocs (bfd *abfd, struct bfd_link_info *info, asection **psec)
 		/* The section size is not divisible by either -
 		   something is wrong.  */
 		_bfd_error_handler (_("%pB: unable to sort relocs - "
-				      "they are of an unknown size"), abfd);
+				      "they are of an unknown size"), obfd);
 		bfd_set_error (bfd_error_invalid_operation);
 		return 0;
 	      }
@@ -10123,9 +10123,9 @@ elf_link_sort_relocs (bfd *abfd, struct bfd_link_info *info, asection **psec)
 	  {
 	    asection *o = lo->u.indirect.section;
 
-	    if ((o->size % bed->s->sizeof_rela) == 0)
+	    if ((o->size % obed->s->sizeof_rela) == 0)
 	      {
-		if ((o->size % bed->s->sizeof_rel) == 0)
+		if ((o->size % obed->s->sizeof_rel) == 0)
 		  /* Section size is divisible by both rel and rela sizes.
 		     It is of no help to us.  */
 		  ;
@@ -10136,7 +10136,7 @@ elf_link_sort_relocs (bfd *abfd, struct bfd_link_info *info, asection **psec)
 		      {
 			_bfd_error_handler (_("%pB: unable to sort relocs - "
 					      "they are in more than one size"),
-					    abfd);
+					    obfd);
 			bfd_set_error (bfd_error_invalid_operation);
 			return 0;
 		      }
@@ -10147,14 +10147,14 @@ elf_link_sort_relocs (bfd *abfd, struct bfd_link_info *info, asection **psec)
 		      }
 		  }
 	      }
-	    else if ((o->size % bed->s->sizeof_rel) == 0)
+	    else if ((o->size % obed->s->sizeof_rel) == 0)
 	      {
 		/* Section size is only divisible by rel.  */
 		if (use_rela_initialised && use_rela)
 		  {
 		    _bfd_error_handler (_("%pB: unable to sort relocs - "
 					  "they are in more than one size"),
-					abfd);
+					obfd);
 		    bfd_set_error (bfd_error_invalid_operation);
 		    return 0;
 		  }
@@ -10169,7 +10169,7 @@ elf_link_sort_relocs (bfd *abfd, struct bfd_link_info *info, asection **psec)
 		/* The section size is not divisible by either -
 		   something is wrong.  */
 		_bfd_error_handler (_("%pB: unable to sort relocs - "
-				      "they are of an unknown size"), abfd);
+				      "they are of an unknown size"), obfd);
 		bfd_set_error (bfd_error_invalid_operation);
 		return 0;
 	      }
@@ -10189,16 +10189,16 @@ elf_link_sort_relocs (bfd *abfd, struct bfd_link_info *info, asection **psec)
   if (use_rela)
     {
       dynamic_relocs = rela_dyn;
-      ext_size = bed->s->sizeof_rela;
-      swap_in = bed->s->swap_reloca_in;
-      swap_out = bed->s->swap_reloca_out;
+      ext_size = obed->s->sizeof_rela;
+      swap_in = obed->s->swap_reloca_in;
+      swap_out = obed->s->swap_reloca_out;
     }
   else
     {
       dynamic_relocs = rel_dyn;
-      ext_size = bed->s->sizeof_rel;
-      swap_in = bed->s->swap_reloc_in;
-      swap_out = bed->s->swap_reloc_out;
+      ext_size = obed->s->sizeof_rel;
+      swap_in = obed->s->swap_reloc_in;
+      swap_out = obed->s->swap_reloc_out;
     }
 
   size = 0;
@@ -10220,11 +10220,11 @@ elf_link_sort_relocs (bfd *abfd, struct bfd_link_info *info, asection **psec)
   if (sort == NULL)
     {
       (*info->callbacks->warning)
-	(info, _("not enough memory to sort relocations"), 0, abfd, 0, 0);
+	(info, _("not enough memory to sort relocations"), 0, obfd, 0, 0);
       return 0;
     }
 
-  if (bed->s->arch_size == 32)
+  if (obed->s->arch_size == 32)
     r_sym_mask = ~(bfd_vma) 0xff;
   else
     r_sym_mask = ~(bfd_vma) 0xffffffff;
@@ -10251,8 +10251,8 @@ elf_link_sort_relocs (bfd *abfd, struct bfd_link_info *info, asection **psec)
 	  {
 	    struct elf_link_sort_rela *s = (struct elf_link_sort_rela *) p;
 
-	    (*swap_in) (abfd, erel, s->rela);
-	    s->type = (*bed->elf_backend_reloc_type_class) (info, o, s->rela);
+	    (*swap_in) (obfd, erel, s->rela);
+	    s->type = obed->elf_backend_reloc_type_class (info, o, s->rela);
 	    s->u.sym_mask = r_sym_mask;
 	    p += sort_elt;
 	    erel += ext_size;
@@ -10322,7 +10322,7 @@ elf_link_sort_relocs (bfd *abfd, struct bfd_link_info *info, asection **psec)
 	while (erel < erelend)
 	  {
 	    struct elf_link_sort_rela *s = (struct elf_link_sort_rela *) p;
-	    (*swap_out) (abfd, s->rela, erel);
+	    (*swap_out) (obfd, s->rela, erel);
 	    p += sort_elt;
 	    erel += ext_size;
 	  }
@@ -10542,10 +10542,10 @@ elf_link_swap_symbols_out (struct elf_final_link_info *flinfo)
   return ret;
 }
 
-/* Return TRUE if the dynamic symbol SYM in ABFD is supported.  */
+/* Return TRUE if the dynamic symbol SYM in OBFD is supported.  */
 
 static bool
-check_dynsym (bfd *abfd, Elf_Internal_Sym *sym)
+check_dynsym (bfd *obfd, Elf_Internal_Sym *sym)
 {
   if (sym->st_shndx >= (SHN_LORESERVE & 0xffff)
       && sym->st_shndx < SHN_LORESERVE)
@@ -10555,7 +10555,7 @@ check_dynsym (bfd *abfd, Elf_Internal_Sym *sym)
       _bfd_error_handler
 	/* xgettext:c-format */
 	(_("%pB: too many sections: %d (>= %d)"),
-	 abfd, bfd_count_sections (abfd), SHN_LORESERVE & 0xffff);
+	 obfd, bfd_count_sections (obfd), SHN_LORESERVE & 0xffff);
       bfd_set_error (bfd_error_nonrepresentable_section);
       return false;
     }
@@ -12501,15 +12501,15 @@ elf_reloc_link_order (bfd *output_bfd,
   return true;
 }
 
-/* Generate an import library in INFO->implib_bfd from symbols in ABFD.
+/* Generate an import library in INFO->implib_bfd from symbols in OBFD.
    Returns TRUE upon success, FALSE otherwise.  */
 
 static bool
-elf_output_implib (bfd *abfd, struct bfd_link_info *info)
+elf_output_implib (bfd *obfd, struct bfd_link_info *info)
 {
   bool ret = false;
   bfd *implib_bfd;
-  elf_backend_data *bed;
+  elf_backend_data *obed;
   flagword flags;
   enum bfd_architecture arch;
   unsigned int mach;
@@ -12521,28 +12521,28 @@ elf_output_implib (bfd *abfd, struct bfd_link_info *info)
   size_t amt;
 
   implib_bfd = info->out_implib_bfd;
-  bed = get_elf_backend_data (abfd);
+  obed = get_elf_backend_data (obfd);
 
   if (!bfd_set_format (implib_bfd, bfd_object))
     return false;
 
   /* Use flag from executable but make it a relocatable object.  */
-  flags = bfd_get_file_flags (abfd);
+  flags = bfd_get_file_flags (obfd);
   flags &= ~HAS_RELOC;
   if (!bfd_set_start_address (implib_bfd, 0)
       || !bfd_set_file_flags (implib_bfd, flags & ~EXEC_P))
     return false;
 
   /* Copy architecture of output file to import library file.  */
-  arch = bfd_get_arch (abfd);
-  mach = bfd_get_mach (abfd);
+  arch = bfd_get_arch (obfd);
+  mach = bfd_get_mach (obfd);
   if (!bfd_set_arch_mach (implib_bfd, arch, mach)
-      && (abfd->target_defaulted
-	  || bfd_get_arch (abfd) != bfd_get_arch (implib_bfd)))
+      && (obfd->target_defaulted
+	  || bfd_get_arch (obfd) != bfd_get_arch (implib_bfd)))
     return false;
 
   /* Get symbol table size.  */
-  symsize = bfd_get_symtab_upper_bound (abfd);
+  symsize = bfd_get_symtab_upper_bound (obfd);
   if (symsize < 0)
     return false;
 
@@ -12551,21 +12551,21 @@ elf_output_implib (bfd *abfd, struct bfd_link_info *info)
   if (sympp == NULL)
     return false;
 
-  symcount = bfd_canonicalize_symtab (abfd, sympp);
+  symcount = bfd_canonicalize_symtab (obfd, sympp);
   if (symcount < 0)
     goto free_sym_buf;
 
   /* Allow the BFD backend to copy any private header data it
      understands from the output BFD to the import library BFD.  */
-  if (! bfd_copy_private_header_data (abfd, implib_bfd))
+  if (! bfd_copy_private_header_data (obfd, implib_bfd))
     goto free_sym_buf;
 
   /* Filter symbols to appear in the import library.  */
-  if (bed->elf_backend_filter_implib_symbols)
-    symcount = bed->elf_backend_filter_implib_symbols (abfd, info, sympp,
-						       symcount);
+  if (obed->elf_backend_filter_implib_symbols)
+    symcount = obed->elf_backend_filter_implib_symbols (obfd, info, sympp,
+							symcount);
   else
-    symcount = _bfd_elf_filter_global_symbols (abfd, info, sympp, symcount);
+    symcount = _bfd_elf_filter_global_symbols (obfd, info, sympp, symcount);
   if (symcount == 0)
     {
       bfd_set_error (bfd_error_no_symbols);
@@ -12598,7 +12598,7 @@ elf_output_implib (bfd *abfd, struct bfd_link_info *info)
   /* Allow the BFD backend to copy any private data it understands
      from the output BFD to the import library BFD.  This is done last
      to permit the routine to look at the filtered symbol table.  */
-  if (! bfd_copy_private_bfd_data (abfd, implib_bfd))
+  if (! bfd_copy_private_bfd_data (obfd, implib_bfd))
     goto free_sym_buf;
 
   if (!bfd_close (implib_bfd))
@@ -12639,7 +12639,7 @@ elf_final_link_free (bfd *obfd, struct elf_final_link_info *flinfo)
 /* Do the final step of an ELF link.  */
 
 bool
-_bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
+_bfd_elf_final_link (bfd *obfd, struct bfd_link_info *info)
 {
   bool dynamic;
   bool emit_relocs;
@@ -12657,7 +12657,7 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
   unsigned int i;
   Elf_Internal_Shdr *symtab_hdr;
   Elf_Internal_Shdr *symtab_shndx_hdr;
-  elf_backend_data *bed = get_elf_backend_data (abfd);
+  elf_backend_data *obed = get_elf_backend_data (obfd);
   struct elf_outext_info eoinfo;
   bool merged;
   size_t relativecount;
@@ -12671,7 +12671,7 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
     return false;
 
   if (bfd_link_pic (info))
-    abfd->flags |= DYNAMIC;
+    obfd->flags |= DYNAMIC;
 
   dynamic = htab->dynamic_sections_created;
   dynobj = htab->dynobj;
@@ -12681,7 +12681,7 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 
   memset (&flinfo, 0, sizeof (flinfo));
   flinfo.info = info;
-  flinfo.output_bfd = abfd;
+  flinfo.output_bfd = obfd;
   flinfo.symstrtab = _bfd_elf_strtab_init ();
   if (flinfo.symstrtab == NULL)
     return false;
@@ -12710,9 +12710,9 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
      section.  */
   sections_removed = false;
 #ifdef OBJ_MAYBE_ELF_ATTRIBUTES
-  const char *obj_attrs_section = get_elf_backend_data (abfd)->obj_attrs_section;
+  const char *obj_attrs_section = get_elf_backend_data (obfd)->obj_attrs_section;
 #endif
-  for (o = abfd->sections; o != NULL; o = o->next)
+  for (o = obfd->sections; o != NULL; o = o->next)
     {
       bool remove_section = false;
 
@@ -12735,13 +12735,13 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 	  /* Skip this section later on.  */
 	  o->map_head.link_order = NULL;
 
-	  bfd_vma attr_size = bfd_elf_obj_attr_size (abfd);
+	  bfd_vma attr_size = bfd_elf_obj_attr_size (obfd);
 	  /* Once ELF headers have been written, the size of a section is
 	     frozen. We need to set the size of the attribute section before
 	     _bfd_elf_compute_section_file_positions.  */
 	  bfd_set_section_size (o, attr_size);
 	  if (attr_size > 0)
-	    elf_obj_object_attributes (abfd) = o;
+	    elf_obj_object_attributes (obfd) = o;
 	  else
 	    remove_section = true;
 	}
@@ -12755,8 +12755,8 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
       if (remove_section)
 	{
 	  o->flags |= SEC_EXCLUDE;
-	  bfd_section_list_remove (abfd, o);
-	  abfd->section_count--;
+	  bfd_section_list_remove (obfd, o);
+	  obfd->section_count--;
 	  sections_removed = true;
 	}
     }
@@ -12767,7 +12767,7 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
      section, so that we know the sizes of the reloc sections.  We
      also figure out some maximum sizes.  */
 #ifdef USE_MMAP
-  if (bed->use_mmap)
+  if (obed->use_mmap)
     {
       /* Mmap is used only if section size >= the minimum mmap section
 	 size.  The initial max_contents_size value covers all sections
@@ -12788,7 +12788,7 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
   max_sym_count = 0;
   max_sym_shndx_count = 0;
   merged = false;
-  for (o = abfd->sections; o != NULL; o = o->next)
+  for (o = obfd->sections; o != NULL; o = o->next)
     {
       struct bfd_elf_section_data *esdo = elf_section_data (o);
       bfd_size_type size_align = 1;
@@ -12798,7 +12798,7 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 	  /* eh_frame editing can extend last FDE to cover padding
 	     between one section and the next.  */
 	  size_align = (((bfd_size_type) 1 << o->alignment_power)
-			* bfd_octets_per_byte (abfd, o));
+			* bfd_octets_per_byte (obfd, o));
 	}
 
       o->reloc_count = 0;
@@ -12830,7 +12830,7 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 #ifdef USE_MMAP
 	      /* Mmap is used only on non-compressed, non-linker created
 		 sections whose rawsize == size.  */
-	      if (!bed->use_mmap
+	      if (!obed->use_mmap
 		  || sec->compress_status != COMPRESS_SECTION_NONE
 		  || (sec->flags & SEC_LINKER_CREATED) != 0
 		  || sec->rawsize != sec->size)
@@ -12852,7 +12852,7 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 		     symbols.  */
 		  if (elf_bad_symtab (sec->owner))
 		    sym_count = (elf_symtab_hdr (sec->owner).sh_size
-				 / bed->s->sizeof_sym);
+				 / obed->s->sizeof_sym);
 		  else
 		    sym_count = elf_symtab_hdr (sec->owner).sh_info;
 
@@ -12874,20 +12874,20 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 		  else if (emit_relocs)
 		    {
 		      reloc_count = sec->reloc_count;
-		      if (bed->elf_backend_count_additional_relocs)
+		      if (obed->elf_backend_count_additional_relocs)
 			{
 			  int c;
-			  c = (*bed->elf_backend_count_additional_relocs) (sec);
+			  c = obed->elf_backend_count_additional_relocs (sec);
 			  additional_reloc_count += c;
 			}
 		    }
-		  else if (bed->elf_backend_count_relocs)
-		    reloc_count = (*bed->elf_backend_count_relocs) (info, sec);
+		  else if (obed->elf_backend_count_relocs)
+		    reloc_count = obed->elf_backend_count_relocs (info, sec);
 
 		  if ((sec->flags & SEC_RELOC) != 0)
 		    {
 #ifdef USE_MMAP
-		      if (!bed->use_mmap)
+		      if (!obed->use_mmap)
 #endif
 			{
 			  size_t ext_size = 0;
@@ -12954,28 +12954,28 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
     }
 
   if (! bfd_link_relocatable (info) && merged)
-    elf_link_hash_traverse (htab, _bfd_elf_link_sec_merge_syms, abfd);
+    elf_link_hash_traverse (htab, _bfd_elf_link_sec_merge_syms, obfd);
 
   /* Figure out the file positions for everything but the symbol table
      and the relocs.  We set symcount to force assign_section_numbers
      to create a symbol table.  */
-  abfd->symcount = info->strip != strip_all || emit_relocs;
-  BFD_ASSERT (! abfd->output_has_begun);
-  if (! _bfd_elf_compute_section_file_positions (abfd, info))
+  obfd->symcount = info->strip != strip_all || emit_relocs;
+  BFD_ASSERT (! obfd->output_has_begun);
+  if (! _bfd_elf_compute_section_file_positions (obfd, info))
     goto error_return;
 
   /* Set sizes, and assign file positions for reloc sections.  */
-  for (o = abfd->sections; o != NULL; o = o->next)
+  for (o = obfd->sections; o != NULL; o = o->next)
     {
       struct bfd_elf_section_data *esdo = elf_section_data (o);
       if ((o->flags & SEC_RELOC) != 0)
 	{
 	  if (esdo->rel.hdr
-	      && !(_bfd_elf_link_size_reloc_section (abfd, &esdo->rel)))
+	      && !(_bfd_elf_link_size_reloc_section (obfd, &esdo->rel)))
 	    goto error_return;
 
 	  if (esdo->rela.hdr
-	      && !(_bfd_elf_link_size_reloc_section (abfd, &esdo->rela)))
+	      && !(_bfd_elf_link_size_reloc_section (obfd, &esdo->rela)))
 	    goto error_return;
 	}
 
@@ -13009,16 +13009,16 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
      .strtab, and non-loaded reloc and compressed debugging sections.  We start
      the .symtab section at the current file position, and write directly to it.
      We build the .strtab section in memory.  */
-  abfd->symcount = 0;
-  symtab_hdr = &elf_symtab_hdr (abfd);
+  obfd->symcount = 0;
+  symtab_hdr = &elf_symtab_hdr (obfd);
   /* sh_name is set in prep_headers.  */
   symtab_hdr->sh_type = SHT_SYMTAB;
   /* sh_flags, sh_addr and sh_size all start off zero.  */
-  symtab_hdr->sh_entsize = bed->s->sizeof_sym;
+  symtab_hdr->sh_entsize = obed->s->sizeof_sym;
   /* sh_link is set in assign_section_numbers.  */
   /* sh_info is set below.  */
   /* sh_offset is set just below.  */
-  symtab_hdr->sh_addralign = (bfd_vma) 1 << bed->s->log_file_align;
+  symtab_hdr->sh_addralign = (bfd_vma) 1 << obed->s->log_file_align;
 
   if (max_sym_count < 20)
     max_sym_count = 20;
@@ -13029,16 +13029,16 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
     goto error_return;
   /* The real buffer will be allocated in elf_link_swap_symbols_out.  */
   flinfo.symshndxbuf
-    = (elf_numsections (abfd) > (SHN_LORESERVE & 0xFFFF)
+    = (elf_numsections (obfd) > (SHN_LORESERVE & 0xFFFF)
        ? (Elf_External_Sym_Shndx *) -1 : NULL);
 
   if (info->strip != strip_all || emit_relocs)
     {
-      file_ptr off = elf_next_file_pos (abfd);
+      file_ptr off = elf_next_file_pos (obfd);
 
       _bfd_elf_assign_file_position_for_section (symtab_hdr, off, true, 0);
 
-      /* Note that at this point elf_next_file_pos (abfd) is
+      /* Note that at this point elf_next_file_pos (obfd) is
 	 incorrect.  We do not yet know the size of the .symtab section.
 	 We correct next_file_pos below, after we do know the size.  */
 
@@ -13059,11 +13059,11 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 	 index of each one in the index field of the section, so that
 	 we can find it again when outputting relocs.  */
 
-      if (bfd_keep_unused_section_symbols (abfd) || emit_relocs)
+      if (bfd_keep_unused_section_symbols (obfd) || emit_relocs)
 	{
 	  bool name_local_sections
-	    = (bed->elf_backend_name_local_section_symbols
-	       && bed->elf_backend_name_local_section_symbols (abfd));
+	    = (obed->elf_backend_name_local_section_symbols
+	       && obed->elf_backend_name_local_section_symbols (obfd));
 	  const char *name = NULL;
 
 	  elfsym.st_size = 0;
@@ -13071,12 +13071,12 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 	  elfsym.st_other = 0;
 	  elfsym.st_value = 0;
 	  elfsym.st_target_internal = 0;
-	  for (i = 1; i < elf_numsections (abfd); i++)
+	  for (i = 1; i < elf_numsections (obfd); i++)
 	    {
-	      o = bfd_section_from_elf_index (abfd, i);
+	      o = bfd_section_from_elf_index (obfd, i);
 	      if (o != NULL)
 		{
-		  o->target_index = bfd_get_symcount (abfd);
+		  o->target_index = bfd_get_symcount (obfd);
 		  elfsym.st_shndx = i;
 		  if (!bfd_link_relocatable (info))
 		    elfsym.st_value = o->vma;
@@ -13093,9 +13093,9 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
   /* On some targets like Irix 5 the symbol split between local and global
      ones recorded in the sh_info field needs to be done between section
      and all other symbols.  */
-  if (bed->elf_backend_elfsym_local_is_section
-      && bed->elf_backend_elfsym_local_is_section (abfd))
-    symtab_hdr->sh_info = bfd_get_symcount (abfd);
+  if (obed->elf_backend_elfsym_local_is_section
+      && obed->elf_backend_elfsym_local_is_section (obfd))
+    symtab_hdr->sh_info = bfd_get_symcount (obfd);
 
   /* Allocate some memory to hold information read in from the input
      files.  */
@@ -13123,7 +13123,7 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 
   if (max_sym_count != 0)
     {
-      amt = max_sym_count * bed->s->sizeof_sym;
+      amt = max_sym_count * obed->s->sizeof_sym;
       flinfo.external_syms = (bfd_byte *) bfd_malloc (amt);
       if (flinfo.external_syms == NULL)
 	goto error_return;
@@ -13162,7 +13162,7 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 	   sec = sec->next)
 	{
 	  bfd_size_type size = sec->size;
-	  unsigned int opb = bfd_octets_per_byte (abfd, sec);
+	  unsigned int opb = bfd_octets_per_byte (obfd, sec);
 
 	  if (size == 0
 	      && (sec->flags & SEC_HAS_CONTENTS) == 0)
@@ -13177,7 +13177,7 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
       base = htab->tls_sec->vma;
       /* Only align end of TLS section if static TLS doesn't have special
 	 alignment requirements.  */
-      if (bed->static_tls_alignment == 1)
+      if (obed->static_tls_alignment == 1)
 	end = align_power (end, htab->tls_sec->alignment_power);
       htab->tls_size = end - base;
     }
@@ -13188,10 +13188,10 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
   /* Finish relative relocations here after regular symbol processing
      is finished if DT_RELR is enabled.  */
   if (info->enable_dt_relr
-      && bed->finish_relative_relocs
-      && !bed->finish_relative_relocs (info))
+      && obed->finish_relative_relocs
+      && !obed->finish_relative_relocs (info))
     info->callbacks->fatal
-      (_("%P: %pB: failed to finish relative relocations\n"), abfd);
+      (_("%P: %pB: failed to finish relative relocations\n"), obfd);
 
   /* Since ELF permits relocations to be against local symbols, we
      must have the local symbols available when we do the relocations.
@@ -13215,14 +13215,14 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 
   for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
     sub->output_has_begun = false;
-  for (o = abfd->sections; o != NULL; o = o->next)
+  for (o = obfd->sections; o != NULL; o = o->next)
     {
       for (p = o->map_head.link_order; p != NULL; p = p->next)
 	{
 	  if (p->type == bfd_indirect_link_order
 	      && (bfd_get_flavour ((sub = p->u.indirect.section->owner))
 		  == bfd_target_elf_flavour)
-	      && elf_elfheader (sub)->e_ident[EI_CLASS] == bed->s->elfclass)
+	      && elf_elfheader (sub)->e_ident[EI_CLASS] == obed->s->elfclass)
 	    {
 	      if (! sub->output_has_begun)
 		{
@@ -13234,22 +13234,22 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 	  else if (p->type == bfd_section_reloc_link_order
 		   || p->type == bfd_symbol_reloc_link_order)
 	    {
-	      if (! elf_reloc_link_order (abfd, info, o, p))
+	      if (! elf_reloc_link_order (obfd, info, o, p))
 		goto error_return;
 	    }
 	  else
 	    {
-	      if (! _bfd_default_link_order (abfd, info, o, p))
+	      if (! _bfd_default_link_order (obfd, info, o, p))
 		{
 		  if (p->type == bfd_indirect_link_order
 		      && (bfd_get_flavour (sub)
 			  == bfd_target_elf_flavour)
 		      && (elf_elfheader (sub)->e_ident[EI_CLASS]
-			  != bed->s->elfclass))
+			  != obed->s->elfclass))
 		    {
 		      const char *iclass, *oclass;
 
-		      switch (bed->s->elfclass)
+		      switch (obed->s->elfclass)
 			{
 			case ELFCLASS64: oclass = "ELFCLASS64"; break;
 			case ELFCLASS32: oclass = "ELFCLASS32"; break;
@@ -13307,10 +13307,10 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 
   /* If backend needs to output some local symbols not present in the hash
      table, do it now.  */
-  if (bed->elf_backend_output_arch_local_syms)
+  if (obed->elf_backend_output_arch_local_syms)
     {
-      if (! ((*bed->elf_backend_output_arch_local_syms)
-	     (abfd, info, &flinfo, elf_link_output_symstrtab)))
+      if (!obed->elf_backend_output_arch_local_syms (obfd, info, &flinfo,
+						     elf_link_output_symstrtab))
 	goto error_return;
     }
 
@@ -13321,7 +13321,7 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 
   /* The sh_info field records the index of the first non local symbol.  */
   if (!symtab_hdr->sh_info)
-    symtab_hdr->sh_info = bfd_get_symcount (abfd);
+    symtab_hdr->sh_info = bfd_get_symcount (obfd);
 
   if (dynamic
       && htab->dynsym != NULL
@@ -13345,7 +13345,7 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 	  sym.st_other = 0;
 	  sym.st_target_internal = 0;
 
-	  for (s = abfd->sections; s != NULL; s = s->next)
+	  for (s = obfd->sections; s != NULL; s = s->next)
 	    {
 	      int indx;
 	      bfd_byte *dest;
@@ -13357,17 +13357,17 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 	      indx = elf_section_data (s)->this_idx;
 	      BFD_ASSERT (indx > 0);
 	      sym.st_shndx = indx;
-	      if (! check_dynsym (abfd, &sym))
+	      if (! check_dynsym (obfd, &sym))
 		goto error_return;
 	      sym.st_value = s->vma;
-	      dest = dynsym + dynindx * bed->s->sizeof_sym;
+	      dest = dynsym + dynindx * obed->s->sizeof_sym;
 
 	      /* Inform the linker of the addition of this symbol.  */
 
 	      if (info->callbacks->ctf_new_dynsym)
 		info->callbacks->ctf_new_dynsym (dynindx, &sym);
 
-	      bed->s->swap_symbol_out (abfd, &sym, dest, 0);
+	      obed->s->swap_symbol_out (obfd, &sym, dest, 0);
 	    }
 	}
 
@@ -13395,7 +13395,7 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 		{
 		  sym.st_shndx =
 		    elf_section_data (s->output_section)->this_idx;
-		  if (! check_dynsym (abfd, &sym))
+		  if (! check_dynsym (obfd, &sym))
 		    goto error_return;
 		  sym.st_value = (s->output_section->vma
 				  + s->output_offset
@@ -13407,8 +13407,8 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 	      if (info->callbacks->ctf_new_dynsym)
 		info->callbacks->ctf_new_dynsym (e->dynindx, &sym);
 
-	      dest = dynsym + e->dynindx * bed->s->sizeof_sym;
-	      bed->s->swap_symbol_out (abfd, &sym, dest, 0);
+	      dest = dynsym + e->dynindx * obed->s->sizeof_sym;
+	      obed->s->swap_symbol_out (obfd, &sym, dest, 0);
 	    }
 	}
     }
@@ -13434,11 +13434,11 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 
   /* If backend needs to output some symbols not present in the hash
      table, do it now.  */
-  if (bed->elf_backend_output_arch_syms
+  if (obed->elf_backend_output_arch_syms
       && (info->strip != strip_all || emit_relocs))
     {
-      if (! ((*bed->elf_backend_output_arch_syms)
-	     (abfd, info, &flinfo, elf_link_output_symstrtab)))
+      if (!obed->elf_backend_output_arch_syms (obfd, info, &flinfo,
+					       elf_link_output_symstrtab))
 	goto error_return;
     }
 
@@ -13452,49 +13452,49 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
   htab->strtab = NULL;
 
   /* Now we know the size of the symtab section.  */
-  if (bfd_get_symcount (abfd) > 0)
+  if (bfd_get_symcount (obfd) > 0)
     {
       /* Finish up and write out the symbol string table (.strtab)
 	 section.  */
       Elf_Internal_Shdr *symstrtab_hdr = NULL;
       file_ptr off = symtab_hdr->sh_offset + symtab_hdr->sh_size;
 
-      if (elf_symtab_shndx_list (abfd))
+      if (elf_symtab_shndx_list (obfd))
 	{
-	  symtab_shndx_hdr = & elf_symtab_shndx_list (abfd)->hdr;
+	  symtab_shndx_hdr = & elf_symtab_shndx_list (obfd)->hdr;
 
 	  if (symtab_shndx_hdr != NULL && symtab_shndx_hdr->sh_name != 0)
 	    {
 	      symtab_shndx_hdr->sh_type = SHT_SYMTAB_SHNDX;
 	      symtab_shndx_hdr->sh_entsize = sizeof (Elf_External_Sym_Shndx);
 	      symtab_shndx_hdr->sh_addralign = sizeof (Elf_External_Sym_Shndx);
-	      amt = bfd_get_symcount (abfd) * sizeof (Elf_External_Sym_Shndx);
+	      amt = bfd_get_symcount (obfd) * sizeof (Elf_External_Sym_Shndx);
 	      symtab_shndx_hdr->sh_size = amt;
 
 	      off = _bfd_elf_assign_file_position_for_section (symtab_shndx_hdr,
 							       off, true, 0);
 
-	      if (bfd_seek (abfd, symtab_shndx_hdr->sh_offset, SEEK_SET) != 0
-		  || (bfd_write (flinfo.symshndxbuf, amt, abfd) != amt))
+	      if (bfd_seek (obfd, symtab_shndx_hdr->sh_offset, SEEK_SET) != 0
+		  || (bfd_write (flinfo.symshndxbuf, amt, obfd) != amt))
 		goto error_return;
 	    }
 	}
 
-      symstrtab_hdr = &elf_tdata (abfd)->strtab_hdr;
+      symstrtab_hdr = &elf_tdata (obfd)->strtab_hdr;
       symstrtab_hdr->sh_type = SHT_STRTAB;
       symstrtab_hdr->sh_size = _bfd_elf_strtab_size (flinfo.symstrtab);
       symstrtab_hdr->sh_addralign = 1;
 
       off = _bfd_elf_assign_file_position_for_section (symstrtab_hdr,
 						       off, true, 0);
-      elf_next_file_pos (abfd) = off;
+      elf_next_file_pos (obfd) = off;
 
-      if (bfd_seek (abfd, symstrtab_hdr->sh_offset, SEEK_SET) != 0
-	  || ! _bfd_elf_strtab_emit (abfd, flinfo.symstrtab))
+      if (bfd_seek (obfd, symstrtab_hdr->sh_offset, SEEK_SET) != 0
+	  || ! _bfd_elf_strtab_emit (obfd, flinfo.symstrtab))
 	goto error_return;
     }
 
-  if (info->out_implib_bfd && !elf_output_implib (abfd, info))
+  if (info->out_implib_bfd && !elf_output_implib (obfd, info))
     {
       _bfd_error_handler (_("%pB: failed to generate import library"),
 			  info->out_implib_bfd);
@@ -13502,7 +13502,7 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
     }
 
   /* Adjust the relocs to have the correct symbol indices.  */
-  for (o = abfd->sections; o != NULL; o = o->next)
+  for (o = obfd->sections; o != NULL; o = o->next)
     {
       struct bfd_elf_section_data *esdo = elf_section_data (o);
       bool sort;
@@ -13510,12 +13510,12 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
       if ((o->flags & SEC_RELOC) == 0)
 	continue;
 
-      sort = bed->sort_relocs_p == NULL || (*bed->sort_relocs_p) (o);
+      sort = obed->sort_relocs_p == NULL || obed->sort_relocs_p (o);
       if (esdo->rel.hdr != NULL
-	  && !elf_link_adjust_relocs (abfd, o, &esdo->rel, sort, info))
+	  && !elf_link_adjust_relocs (obfd, o, &esdo->rel, sort, info))
 	goto error_return;
       if (esdo->rela.hdr != NULL
-	  && !elf_link_adjust_relocs (abfd, o, &esdo->rela, sort, info))
+	  && !elf_link_adjust_relocs (obfd, o, &esdo->rela, sort, info))
 	goto error_return;
 
       /* Set the reloc_count field to 0 to prevent write_relocs from
@@ -13525,7 +13525,7 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 
   relativecount = 0;
   if (dynamic && info->combreloc && dynobj != NULL)
-    relativecount = elf_link_sort_relocs (abfd, info, &reldyn);
+    relativecount = elf_link_sort_relocs (obfd, info, &reldyn);
 
   relr_entsize = 0;
   if (htab->srelrdyn != NULL
@@ -13536,7 +13536,7 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
       relr_entsize = elf_section_data (s)->this_hdr.sh_entsize;
       if (relr_entsize == 0)
 	{
-	  relr_entsize = bed->s->arch_size / 8;
+	  relr_entsize = obed->s->arch_size / 8;
 	  elf_section_data (s)->this_hdr.sh_entsize = relr_entsize;
 	}
     }
@@ -13553,7 +13553,7 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 
       dyncon = o->contents;
       dynconend = PTR_ADD (o->contents, o->size);
-      for (; dyncon < dynconend; dyncon += bed->s->sizeof_dyn)
+      for (; dyncon < dynconend; dyncon += obed->s->sizeof_dyn)
 	{
 	  Elf_Internal_Dyn dyn;
 	  const char *name;
@@ -13561,7 +13561,7 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 	  bfd_size_type sh_size;
 	  bfd_vma sh_addr;
 
-	  bed->s->swap_dyn_in (dynobj, dyncon, &dyn);
+	  obed->s->swap_dyn_in (dynobj, dyncon, &dyn);
 
 	  switch (dyn.d_tag)
 	    {
@@ -13576,7 +13576,7 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 		    case SHT_RELA: dyn.d_tag = DT_RELACOUNT; break;
 		    }
 		  if (dyn.d_tag != DT_NULL
-		      && dynconend - dyncon >= bed->s->sizeof_dyn)
+		      && dynconend - dyncon >= obed->s->sizeof_dyn)
 		    {
 		      dyn.d_un.d_val = relativecount;
 		      relativecount = 0;
@@ -13586,19 +13586,19 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 		}
 	      if (relr_entsize != 0)
 		{
-		  if (dynconend - dyncon >= 3 * bed->s->sizeof_dyn)
+		  if (dynconend - dyncon >= 3 * obed->s->sizeof_dyn)
 		    {
 		      asection *s = htab->srelrdyn;
 		      dyn.d_tag = DT_RELR;
 		      dyn.d_un.d_ptr
 			= s->output_section->vma + s->output_offset;
-		      bed->s->swap_dyn_out (dynobj, &dyn, dyncon);
-		      dyncon += bed->s->sizeof_dyn;
+		      obed->s->swap_dyn_out (dynobj, &dyn, dyncon);
+		      dyncon += obed->s->sizeof_dyn;
 
 		      dyn.d_tag = DT_RELRSZ;
 		      dyn.d_un.d_val = s->size;
-		      bed->s->swap_dyn_out (dynobj, &dyn, dyncon);
-		      dyncon += bed->s->sizeof_dyn;
+		      obed->s->swap_dyn_out (dynobj, &dyn, dyncon);
+		      dyncon += obed->s->sizeof_dyn;
 
 		      dyn.d_tag = DT_RELRENT;
 		      dyn.d_un.d_val = relr_entsize;
@@ -13648,7 +13648,7 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 	    case DT_FINI_ARRAYSZ:
 	      name = ".fini_array";
 	    get_out_size:
-	      o = bfd_get_section_by_name (abfd, name);
+	      o = bfd_get_section_by_name (obfd, name);
 	      if (o == NULL)
 		{
 		  _bfd_error_handler
@@ -13670,7 +13670,7 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 	    case DT_FINI_ARRAY:
 	      name = ".fini_array";
 	    get_out_vma:
-	      o = bfd_get_section_by_name (abfd, name);
+	      o = bfd_get_section_by_name (obfd, name);
 	      goto do_vma;
 
 	    case DT_HASH:
@@ -13722,11 +13722,11 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 		type = SHT_RELA;
 	      sh_size = 0;
 	      sh_addr = 0;
-	      for (i = 1; i < elf_numsections (abfd); i++)
+	      for (i = 1; i < elf_numsections (obfd); i++)
 		{
 		  Elf_Internal_Shdr *hdr;
 
-		  hdr = elf_elfsections (abfd)[i];
+		  hdr = elf_elfsections (obfd)[i];
 		  if (hdr->sh_type == type
 		      && (hdr->sh_flags & SHF_ALLOC) != 0)
 		    {
@@ -13737,9 +13737,9 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 		    }
 		}
 
-	      if (bed->dtrel_excludes_plt && htab->srelplt != NULL)
+	      if (obed->dtrel_excludes_plt && htab->srelplt != NULL)
 		{
-		  unsigned int opb = bfd_octets_per_byte (abfd, o);
+		  unsigned int opb = bfd_octets_per_byte (obfd, o);
 
 		  /* Don't count procedure linkage table relocs in the
 		     overall reloc count.  */
@@ -13770,15 +13770,15 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 		dyn.d_un.d_ptr = sh_addr;
 	      break;
 	    }
-	  bed->s->swap_dyn_out (dynobj, &dyn, dyncon);
+	  obed->s->swap_dyn_out (dynobj, &dyn, dyncon);
 	}
     }
 
   /* If we have created any dynamic sections, then output them.  */
   if (dynobj != NULL)
     {
-      if (! (*bed->elf_backend_finish_dynamic_sections) (abfd, info,
-							 flinfo.contents))
+      if (!obed->elf_backend_finish_dynamic_sections (obfd, info,
+						      flinfo.contents))
 	goto error_return;
 
       /* Check for DT_TEXTREL (late, in case the backend removes it).  */
@@ -13790,11 +13790,11 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 
 	  dyncon = o->contents;
 	  dynconend = o->contents + o->size;
-	  for (; dyncon < dynconend; dyncon += bed->s->sizeof_dyn)
+	  for (; dyncon < dynconend; dyncon += obed->s->sizeof_dyn)
 	    {
 	      Elf_Internal_Dyn dyn;
 
-	      bed->s->swap_dyn_in (dynobj, dyncon, &dyn);
+	      obed->s->swap_dyn_in (dynobj, dyncon, &dyn);
 
 	      if (dyn.d_tag == DT_TEXTREL)
 		{
@@ -13834,8 +13834,8 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 	  if (strcmp (o->name, ".dynstr") != 0)
 	    {
 	      bfd_size_type octets = ((file_ptr) o->output_offset
-				      * bfd_octets_per_byte (abfd, o));
-	      if (!bfd_set_section_contents (abfd, o->output_section,
+				      * bfd_octets_per_byte (obfd, o));
+	      if (!bfd_set_section_contents (obfd, o->output_section,
 					     o->contents, octets, o->size))
 		goto error_return;
 	    }
@@ -13846,8 +13846,8 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
 	      file_ptr off;
 
 	      off = elf_section_data (o->output_section)->this_hdr.sh_offset;
-	      if (bfd_seek (abfd, off, SEEK_SET) != 0
-		  || !_bfd_elf_strtab_emit (abfd, htab->dynstr))
+	      if (bfd_seek (obfd, off, SEEK_SET) != 0
+		  || !_bfd_elf_strtab_emit (obfd, htab->dynstr))
 		goto error_return;
 	    }
 	}
@@ -13858,7 +13858,7 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
       bool failed = false;
 
       BFD_ASSERT (bfd_link_relocatable (info));
-      bfd_map_over_sections (abfd, bfd_elf_set_group_contents, &failed);
+      bfd_map_over_sections (obfd, bfd_elf_set_group_contents, &failed);
       if (failed)
 	goto error_return;
     }
@@ -13866,23 +13866,23 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
   /* If we have optimized stabs strings, output them.  */
   if (htab->stab_info.stabstr != NULL)
     {
-      if (!_bfd_write_stab_strings (abfd, &htab->stab_info))
+      if (!_bfd_write_stab_strings (obfd, &htab->stab_info))
 	goto error_return;
     }
 
-  if (! _bfd_elf_write_section_eh_frame_hdr (abfd, info))
+  if (! _bfd_elf_write_section_eh_frame_hdr (obfd, info))
     goto error_return;
 
-  if (! _bfd_elf_write_section_sframe (abfd, info))
+  if (! _bfd_elf_write_section_sframe (obfd, info))
     goto error_return;
 
-  if (! _bfd_elf_write_section_object_attributes (abfd, info))
+  if (! _bfd_elf_write_section_object_attributes (obfd, info))
     goto error_ret2;
 
   if (info->callbacks->emit_ctf)
       info->callbacks->emit_ctf ();
 
-  elf_final_link_free (abfd, &flinfo);
+  elf_final_link_free (obfd, &flinfo);
 
   if (info->unique_symbol)
     bfd_hash_table_free (&flinfo.local_hash_table);
@@ -13891,7 +13891,7 @@ _bfd_elf_final_link (bfd *abfd, struct bfd_link_info *info)
  error_return:
   free (htab->strtab);
   htab->strtab = NULL;
-  elf_final_link_free (abfd, &flinfo);
+  elf_final_link_free (obfd, &flinfo);
  error_ret2:
   if (info->unique_symbol)
     bfd_hash_table_free (&flinfo.local_hash_table);
@@ -14414,10 +14414,10 @@ _bfd_elf_gc_mark_extra_sections (struct bfd_link_info *info,
 }
 
 static bool
-elf_gc_sweep (bfd *abfd, struct bfd_link_info *info)
+elf_gc_sweep (bfd *obfd, struct bfd_link_info *info)
 {
   bfd *sub;
-  elf_backend_data *bed = get_elf_backend_data (abfd);
+  elf_backend_data *obed = get_elf_backend_data (obfd);
 
   for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
     {
@@ -14425,7 +14425,7 @@ elf_gc_sweep (bfd *abfd, struct bfd_link_info *info)
 
       if (bfd_get_flavour (sub) != bfd_target_elf_flavour
 	  || elf_object_id (sub) != elf_hash_table_id (elf_hash_table (info))
-	  || !(*bed->relocs_compatible) (sub->xvec, abfd->xvec))
+	  || !obed->relocs_compatible (sub->xvec, obfd->xvec))
 	continue;
       o = sub->sections;
       if (o == NULL || o->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
@@ -14640,7 +14640,7 @@ _bfd_elf_gc_keep (struct bfd_link_info *info)
 }
 
 bool
-bfd_elf_parse_eh_frame_entries (bfd *abfd ATTRIBUTE_UNUSED,
+bfd_elf_parse_eh_frame_entries (bfd *obfd ATTRIBUTE_UNUSED,
 				struct bfd_link_info *info)
 {
   bfd *ibfd = info->input_bfds;
@@ -14676,23 +14676,23 @@ bfd_elf_parse_eh_frame_entries (bfd *abfd ATTRIBUTE_UNUSED,
 /* Do mark and sweep of unused sections.  */
 
 bool
-bfd_elf_gc_sections (bfd *abfd, struct bfd_link_info *info)
+bfd_elf_gc_sections (bfd *obfd, struct bfd_link_info *info)
 {
   bool ok = true;
   bfd *sub;
   elf_gc_mark_hook_fn gc_mark_hook;
-  elf_backend_data *bed = get_elf_backend_data (abfd);
+  elf_backend_data *obed = get_elf_backend_data (obfd);
   struct elf_link_hash_table *htab;
   struct link_info_ok info_ok;
 
-  if (!bed->can_gc_sections
+  if (!obed->can_gc_sections
       || !is_elf_hash_table (info->hash))
     {
       _bfd_error_handler(_("warning: gc-sections option ignored"));
       return true;
     }
 
-  bed->gc_keep (info);
+  obed->gc_keep (info);
   htab = elf_hash_table (info);
 
   /* Try to parse each bfd's .eh_frame section.  Point elf_eh_frame_section
@@ -14751,17 +14751,17 @@ bfd_elf_gc_sections (bfd *abfd, struct bfd_link_info *info)
 
   /* Mark dynamically referenced symbols.  */
   if (htab->dynamic_sections_created || info->gc_keep_exported)
-    elf_link_hash_traverse (htab, bed->gc_mark_dynamic_ref, info);
+    elf_link_hash_traverse (htab, obed->gc_mark_dynamic_ref, info);
 
   /* Grovel through relocs to find out who stays ...  */
-  gc_mark_hook = bed->gc_mark_hook;
+  gc_mark_hook = obed->gc_mark_hook;
   for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
     {
       asection *o;
 
       if (bfd_get_flavour (sub) != bfd_target_elf_flavour
 	  || elf_object_id (sub) != elf_hash_table_id (htab)
-	  || !(*bed->relocs_compatible) (sub->xvec, abfd->xvec))
+	  || !obed->relocs_compatible (sub->xvec, obfd->xvec))
 	continue;
 
       o = sub->sections;
@@ -14795,10 +14795,10 @@ bfd_elf_gc_sections (bfd *abfd, struct bfd_link_info *info)
     }
 
   /* Allow the backend to mark additional target specific sections.  */
-  bed->gc_mark_extra_sections (info, gc_mark_hook);
+  obed->gc_mark_extra_sections (info, gc_mark_hook);
 
   /* ... and mark SEC_EXCLUDE for those that go.  */
-  return elf_gc_sweep (abfd, info);
+  return elf_gc_sweep (obfd, info);
 }
 
 /* Called from check_relocs to record the existence of a VTINHERIT reloc.  */
@@ -14981,7 +14981,7 @@ bfd_elf_lookup_section_flags (struct bfd_link_info *info,
   if (!flaginfo->flags_initialized)
     {
       bfd *obfd = info->output_bfd;
-      elf_backend_data *bed = get_elf_backend_data (obfd);
+      elf_backend_data *obed = get_elf_backend_data (obfd);
       struct flag_info_list *tf = flaginfo->flag_list;
       int with_hex = 0;
       int without_hex = 0;
@@ -14991,7 +14991,7 @@ bfd_elf_lookup_section_flags (struct bfd_link_info *info,
 	  unsigned i;
 	  flagword (*lookup) (char *);
 
-	  lookup = bed->elf_backend_lookup_section_flags_hook;
+	  lookup = obed->elf_backend_lookup_section_flags_hook;
 	  if (lookup != NULL)
 	    {
 	      flagword hexval = (*lookup) ((char *) tf->name);
@@ -15052,12 +15052,12 @@ elf_gc_allocate_got_offsets (struct elf_link_hash_entry *h, void *arg)
 {
   struct alloc_got_off_arg *gofarg = (struct alloc_got_off_arg *) arg;
   bfd *obfd = gofarg->info->output_bfd;
-  elf_backend_data *bed = get_elf_backend_data (obfd);
+  elf_backend_data *obed = get_elf_backend_data (obfd);
 
   if (h->got.refcount > 0)
     {
       h->got.offset = gofarg->gotoff;
-      gofarg->gotoff += bed->got_elt_size (obfd, gofarg->info, h, NULL, 0);
+      gofarg->gotoff += obed->got_elt_size (obfd, gofarg->info, h, NULL, 0);
     }
   else
     h->got.offset = (bfd_vma) -1;
@@ -15069,25 +15069,25 @@ elf_gc_allocate_got_offsets (struct elf_link_hash_entry *h, void *arg)
    we're done.  Should be called from final_link.  */
 
 bool
-bfd_elf_gc_common_finalize_got_offsets (bfd *abfd,
+bfd_elf_gc_common_finalize_got_offsets (bfd *obfd,
 					struct bfd_link_info *info)
 {
   bfd *i;
-  elf_backend_data *bed = get_elf_backend_data (abfd);
+  elf_backend_data *obed = get_elf_backend_data (obfd);
   bfd_vma gotoff;
   struct alloc_got_off_arg gofarg;
 
-  BFD_ASSERT (abfd == info->output_bfd);
+  BFD_ASSERT (obfd == info->output_bfd);
 
   if (! is_elf_hash_table (info->hash))
     return false;
 
   /* The GOT offset is relative to the .got section, but the GOT header is
      put into the .got.plt section, if the backend uses it.  */
-  if (bed->want_got_plt)
+  if (obed->want_got_plt)
     gotoff = 0;
   else
-    gotoff = bed->got_header_size;
+    gotoff = obed->got_header_size;
 
   /* Do the local .got entries first.  */
   for (i = info->input_bfds; i; i = i->link.next)
@@ -15105,7 +15105,7 @@ bfd_elf_gc_common_finalize_got_offsets (bfd *abfd,
 
       symtab_hdr = &elf_symtab_hdr (i);
       if (elf_bad_symtab (i))
-	locsymcount = symtab_hdr->sh_size / bed->s->sizeof_sym;
+	locsymcount = symtab_hdr->sh_size / obed->s->sizeof_sym;
       else
 	locsymcount = symtab_hdr->sh_info;
 
@@ -15114,7 +15114,7 @@ bfd_elf_gc_common_finalize_got_offsets (bfd *abfd,
 	  if (local_got[j] > 0)
 	    {
 	      local_got[j] = gotoff;
-	      gotoff += bed->got_elt_size (abfd, info, NULL, i, j);
+	      gotoff += obed->got_elt_size (obfd, info, NULL, i, j);
 	    }
 	  else
 	    local_got[j] = (bfd_vma) -1;
@@ -15135,13 +15135,13 @@ bfd_elf_gc_common_finalize_got_offsets (bfd *abfd,
    got entry reference counting is enabled.  */
 
 bool
-_bfd_elf_gc_common_final_link (bfd *abfd, struct bfd_link_info *info)
+_bfd_elf_gc_common_final_link (bfd *obfd, struct bfd_link_info *info)
 {
-  if (!bfd_elf_gc_common_finalize_got_offsets (abfd, info))
+  if (!bfd_elf_gc_common_finalize_got_offsets (obfd, info))
     return false;
 
   /* Invoke the regular ELF backend linker to do all the work.  */
-  return _bfd_elf_final_link (abfd, info);
+  return _bfd_elf_final_link (obfd, info);
 }
 
 bool
@@ -15554,14 +15554,14 @@ _bfd_elf_common_section (asection *sec ATTRIBUTE_UNUSED)
 }
 
 bfd_vma
-_bfd_elf_default_got_elt_size (bfd *abfd,
+_bfd_elf_default_got_elt_size (bfd *obfd,
 			       struct bfd_link_info *info ATTRIBUTE_UNUSED,
 			       struct elf_link_hash_entry *h ATTRIBUTE_UNUSED,
 			       bfd *ibfd ATTRIBUTE_UNUSED,
 			       unsigned long symndx ATTRIBUTE_UNUSED)
 {
-  elf_backend_data *bed = get_elf_backend_data (abfd);
-  return bed->s->arch_size / 8;
+  elf_backend_data *obed = get_elf_backend_data (obfd);
+  return obed->s->arch_size / 8;
 }
 
 /* Routines to support the creation of dynamic relocs.  */
@@ -15645,7 +15645,7 @@ _bfd_elf_make_dynamic_reloc_section (asection *sec,
    if we found a strong non-dynamic definition for HDEST (except that
    ld ignores multiple definition errors).  */
 void
-_bfd_elf_copy_link_hash_symbol_type (bfd *abfd,
+_bfd_elf_copy_link_hash_symbol_type (bfd *obfd,
 				     struct bfd_link_hash_entry *hdest,
 				     struct bfd_link_hash_entry *hsrc)
 {
@@ -15657,29 +15657,29 @@ _bfd_elf_copy_link_hash_symbol_type (bfd *abfd,
   ehdest->target_internal = ehsrc->target_internal;
 
   isym.st_other = ehsrc->other;
-  elf_merge_st_other (abfd, ehdest, isym.st_other, NULL, true, false);
+  elf_merge_st_other (obfd, ehdest, isym.st_other, NULL, true, false);
 }
 
-/* Append a RELA relocation REL to section S in BFD.  */
+/* Append a RELA relocation REL to section S.  */
 
 void
-_bfd_elf_append_rela (bfd *abfd, asection *s, Elf_Internal_Rela *rel)
+_bfd_elf_append_rela (bfd *obfd, asection *s, Elf_Internal_Rela *rel)
 {
-  elf_backend_data *bed = get_elf_backend_data (abfd);
-  bfd_byte *loc = s->contents + (s->reloc_count++ * bed->s->sizeof_rela);
-  BFD_ASSERT (loc + bed->s->sizeof_rela <= s->contents + s->size);
-  bed->s->swap_reloca_out (abfd, rel, loc);
+  elf_backend_data *obed = get_elf_backend_data (obfd);
+  bfd_byte *loc = s->contents + (s->reloc_count++ * obed->s->sizeof_rela);
+  BFD_ASSERT (loc + obed->s->sizeof_rela <= s->contents + s->size);
+  obed->s->swap_reloca_out (obfd, rel, loc);
 }
 
-/* Append a REL relocation REL to section S in BFD.  */
+/* Append a REL relocation REL to section S.  */
 
 void
-_bfd_elf_append_rel (bfd *abfd, asection *s, Elf_Internal_Rela *rel)
+_bfd_elf_append_rel (bfd *obfd, asection *s, Elf_Internal_Rela *rel)
 {
-  elf_backend_data *bed = get_elf_backend_data (abfd);
-  bfd_byte *loc = s->contents + (s->reloc_count++ * bed->s->sizeof_rel);
-  BFD_ASSERT (loc + bed->s->sizeof_rel <= s->contents + s->size);
-  bed->s->swap_reloc_out (abfd, rel, loc);
+  elf_backend_data *obed = get_elf_backend_data (obfd);
+  bfd_byte *loc = s->contents + (s->reloc_count++ * obed->s->sizeof_rel);
+  BFD_ASSERT (loc + obed->s->sizeof_rel <= s->contents + s->size);
+  obed->s->swap_reloc_out (obfd, rel, loc);
 }
 
 /* Define __start, __stop, .startof. or .sizeof. symbol.  */
@@ -15713,8 +15713,8 @@ bfd_elf_define_start_stop (struct bfd_link_info *info,
       if (symbol[0] == '.')
 	{
 	  /* .startof. and .sizeof. symbols are local.  */
-	  elf_backend_data *bed = get_elf_backend_data (info->output_bfd);
-	  (*bed->elf_backend_hide_symbol) (info, h, true);
+	  elf_backend_data *obed = get_elf_backend_data (info->output_bfd);
+	  obed->elf_backend_hide_symbol (info, h, true);
 	}
       else
 	{
@@ -15798,7 +15798,7 @@ _bfd_elf_add_dynamic_tags (bfd *output_bfd, struct bfd_link_info *info,
 #define add_dynamic_entry(TAG, VAL) \
   _bfd_elf_add_dynamic_entry (info, TAG, VAL)
 
-      elf_backend_data *bed = get_elf_backend_data (output_bfd);
+      elf_backend_data *obed = get_elf_backend_data (output_bfd);
 
       if (bfd_link_executable (info))
 	{
@@ -15818,7 +15818,7 @@ _bfd_elf_add_dynamic_tags (bfd *output_bfd, struct bfd_link_info *info,
 	{
 	  if (!add_dynamic_entry (DT_PLTRELSZ, 0)
 	      || !add_dynamic_entry (DT_PLTREL,
-				     (bed->rela_plts_and_copies_p
+				     (obed->rela_plts_and_copies_p
 				      ? DT_RELA : DT_REL))
 	      || !add_dynamic_entry (DT_JMPREL, 0))
 	    return false;
@@ -15831,12 +15831,12 @@ _bfd_elf_add_dynamic_tags (bfd *output_bfd, struct bfd_link_info *info,
 
       if (need_dynamic_reloc)
 	{
-	  if (bed->rela_plts_and_copies_p)
+	  if (obed->rela_plts_and_copies_p)
 	    {
 	      if (!add_dynamic_entry (DT_RELA, 0)
 		  || !add_dynamic_entry (DT_RELASZ, 0)
 		  || !add_dynamic_entry (DT_RELAENT,
-					 bed->s->sizeof_rela))
+					 obed->s->sizeof_rela))
 		return false;
 	    }
 	  else
@@ -15844,7 +15844,7 @@ _bfd_elf_add_dynamic_tags (bfd *output_bfd, struct bfd_link_info *info,
 	      if (!add_dynamic_entry (DT_REL, 0)
 		  || !add_dynamic_entry (DT_RELSZ, 0)
 		  || !add_dynamic_entry (DT_RELENT,
-					 bed->s->sizeof_rel))
+					 obed->s->sizeof_rel))
 		return false;
 	    }
 

-- 
Alan Modra

From amodra@gmail.com  Wed Jun  3 22:26:50 2026
From: amodra@gmail.com (Alan Modra)
Date: Thu, 4 Jun 2026 07:56:50 +0930
Subject: elf_merge_st_other
Message-ID: <aiCqKvnf6L--wX6e@squeak.grove.modra.org>

This fixes a potential problem with merging non-visibility bits in
st_other.  Non-visibilty bits in st_other have an architecture
dependent meaning, so they cannot just be copied from a foreign ELF
object file.  I think the safest thing to do in this situation is
ignore non-visibility st_other bits.  That's what this patch does.

	PR 34062
	* elflink.c (elf_merge_st_other): Replace abfd param with
	obfd and ibfd parameters.  Do not call
	elf_backend_merge_symbol_attribute when input xvec differs
	from output xvec.
	(_bfd_elf_merge_symbol, _bfd_elf_add_default_symbol),
	(elf_link_add_object_symbols),
	(_bfd_elf_copy_link_hash_symbol_type): Pass both output bfd
	and input bfd to elf_merge_st_other.

diff --git a/bfd/elflink.c b/bfd/elflink.c
index 8d092266b88..e35a105ac4c 100644
--- a/bfd/elflink.c
+++ b/bfd/elflink.c
@@ -1094,20 +1094,28 @@ _bfd_elf_link_renumber_dynsyms (bfd *output_bfd,
   return dynsymcount;
 }
 
-/* Merge st_other field.  */
+/* Merge st_other field.  Both the input bfd and output bfd are given
+   with IBFD reflecting where the ST_OTHER bits came from.  If they
+   were from a symbol already in the linker hash table then the proper
+   IBFD is the output bfd since symbols in the linker hash table
+   interpret their st_other bits according to OBFD.  */
 
 static void
-elf_merge_st_other (bfd *abfd, struct elf_link_hash_entry *h,
+elf_merge_st_other (bfd *obfd, bfd *ibfd,
+		    struct elf_link_hash_entry *h,
 		    unsigned int st_other, asection *sec,
 		    bool definition, bool dynamic)
 {
-  elf_backend_data *bed = get_elf_backend_data (abfd);
+  if (ibfd->xvec == obfd->xvec)
+    {
+      elf_backend_data *obed = get_elf_backend_data (obfd);
 
-  /* If st_other has a processor-specific meaning, specific
-     code might be needed here.  */
-  if (bed->elf_backend_merge_symbol_attribute)
-    (*bed->elf_backend_merge_symbol_attribute) (h, st_other, definition,
-						dynamic);
+      /* If st_other has a processor-specific meaning, specific
+	 code might be needed here.  */
+      if (obed->elf_backend_merge_symbol_attribute)
+	obed->elf_backend_merge_symbol_attribute (h, st_other,
+						  definition, dynamic);
+    }
 
   if (!dynamic)
     {
@@ -1815,7 +1823,8 @@ _bfd_elf_merge_symbol (bfd *abfd,
       /* Merge st_other.  If the symbol already has a dynamic index,
 	 but visibility says it should not be visible, turn it into a
 	 local symbol.  */
-      elf_merge_st_other (abfd, h, sym->st_other, sec, newdef, newdyn);
+      elf_merge_st_other (info->output_bfd, abfd, h, sym->st_other,
+			  sec, newdef, newdyn);
       if (h->dynindx != -1)
 	switch (ELF_ST_VISIBILITY (h->other))
 	  {
@@ -2144,7 +2153,8 @@ _bfd_elf_add_default_symbol (bfd *abfd,
 
       /* If we first saw a reference to SHORTNAME with non-default
 	 visibility, merge that visibility to the @@VER symbol.  */
-      elf_merge_st_other (abfd, ht, hi->other, sec, true, dynamic);
+      elf_merge_st_other (info->output_bfd, info->output_bfd, ht, hi->other,
+			  sec, true, dynamic);
 
       /* A reference to the SHORTNAME symbol from a dynamic library
 	 will be satisfied by the versioned symbol at runtime.  In
@@ -2246,7 +2256,8 @@ _bfd_elf_add_default_symbol (bfd *abfd,
       /* If we first saw a reference to @VER symbol with
 	 non-default visibility, merge that visibility to the
 	 @@VER symbol.  */
-      elf_merge_st_other (abfd, h, hi->other, sec, true, dynamic);
+      elf_merge_st_other (info->output_bfd, info->output_bfd, h, hi->other,
+			  sec, true, dynamic);
 
       /* See if the new flags lead us to realize that the symbol
 	 must be dynamic.  */
@@ -5640,8 +5651,8 @@ elf_link_add_object_symbols (bfd *abfd, struct bfd_link_info *info)
 	    }
 
 	  /* Merge st_other field.  */
-	  elf_merge_st_other (abfd, h, isym->st_other, sec,
-			      definition, dynamic);
+	  elf_merge_st_other (info->output_bfd, abfd, h, isym->st_other,
+			      sec, definition, dynamic);
 
 	  /* We don't want to make debug symbol dynamic.  */
 	  if (definition
@@ -15651,13 +15662,12 @@ _bfd_elf_copy_link_hash_symbol_type (bfd *obfd,
 {
   struct elf_link_hash_entry *ehdest = (struct elf_link_hash_entry *) hdest;
   struct elf_link_hash_entry *ehsrc = (struct elf_link_hash_entry *) hsrc;
-  Elf_Internal_Sym isym;
 
   ehdest->type = ehsrc->type;
   ehdest->target_internal = ehsrc->target_internal;
 
-  isym.st_other = ehsrc->other;
-  elf_merge_st_other (obfd, ehdest, isym.st_other, NULL, true, false);
+  elf_merge_st_other (obfd, obfd, ehdest, ehsrc->other, NULL,
+		      true, false);
 }
 
 /* Append a RELA relocation REL to section S.  */

-- 
Alan Modra

From haochen.jiang@intel.com  Thu Jun  4 07:38:38 2026
From: haochen.jiang@intel.com (Jiang, Haochen)
Date: Thu, 4 Jun 2026 07:38:38 +0000
Subject: [PATCH] x86: Support BHI_CTRL instruction
In-Reply-To: <CAKSQd8VsEd9UD=bqc8w+HFs3LsySFOjrf+AmLV384cC_9pXwbg@mail.gmail.com>
References: <20260601062446.2367458-1-haochen.jiang@intel.com>
 <982f780d-c653-4a4d-bfa8-19bed76b1277@suse.com>
 <IA4PR11MB9009997D9669A4442CFF024DEC132@IA4PR11MB9009.namprd11.prod.outlook.com>
 <SJ5PPF77D28E3C27FBB50DC50A27FB579D4EC132@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>
 <7b3974e9-d03e-4492-8663-8abb9e1ea5c8@suse.com>
 <SJ5PPF77D28E3C295448A06B5215A8D0CCAEC132@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>
 <CAKSQd8VsEd9UD=bqc8w+HFs3LsySFOjrf+AmLV384cC_9pXwbg@mail.gmail.com>
Message-ID: <SJ5PPF77D28E3C23853EA1BFBF81CCC55ECEC102@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>

> From: Christian Ludloff <ludloff@gmail.com>
> Sent: Thursday, June 4, 2026 4:07 AM
> 
> On Wed, Jun 3, 2026 at 1:16?AM Jiang, Haochen <haochen.jiang@intel.com>
> wrote:
> > I am confirming with arch team for these issues. This instruction seems to me
> > the first instruction we only borrowed W1 with no effect, other using
> REX.W1
> > at least implied operand size. This definitely needs some clarification.
> >
> > Will come back to you all after I get a clear answer.
> 
> Arguably RDSSP{D,Q} is a litmus test ? can it REX2 or EVEX?

I suppose it should be a REX2, not EVEX MAP4. Its opcode is in those
REX2 permitted opcode.

Thx,
Haochen

From jon.turney@dronecode.org.uk  Thu Jun  4 12:37:37 2026
From: jon.turney@dronecode.org.uk (Jon Turney)
Date: Thu, 4 Jun 2026 13:37:37 +0100
Subject: [PATCH] ld: Drop pep-dll-{aarch64,x86_64}.c
In-Reply-To: <ahyz-aLSlj0_XpOR@squeak.grove.modra.org>
References: <20260531141745.1339572-1-jon.turney@dronecode.org.uk>
 <ahyz-aLSlj0_XpOR@squeak.grove.modra.org>
Message-ID: <cdf02762-ed6a-44a4-9f47-d081b1a8956d@dronecode.org.uk>

On 31/05/2026 23:19, Alan Modra wrote:
> On Sun, May 31, 2026 at 03:17:45PM +0100, Jon Turney wrote:
>> I can't see anything in pe{,p}-dll.c which depends on the
>> COFF_WITH_peAArch64 or COFF_WITH_pex64 defines, so just remove all this.
> 
> Yes, and it's not just pe-dll.c but all of its headers.  As evidenced
> by the fact that compiling pep-dll.c with either of those defines on
> the command line gives the same object as compiling pep-dll.c.

Thanks for double checking!

(In fact, I think COFF_WITH_pe{AArch674,x64} are only used in pep.em, 
which I guess is the only place it makes sense to use them, given my 
vague memory of the preprocessing gymnastics that go on there...)

>> (Neither pep-dll-aarch64.o or pep-dll-x86_64.o are listed in
>> ALL_EMUL_EXTRA_OFILES, so this multiple definition problem doesn't show
>> up when configured --enable-targets=all', but this seems like another
>> source of subtle bugs if those defines did do anything here...)
> 
> True.
> 
>> Cc'ed Evgeny (Hi!), because I think this crosses with not-yet-submitted
>> patches of his which do add some code conditional on COFF_WITH_peAArch64.
>>
>> I imagine it's possible in code which *does* need to depend on the
>> output target to replace build time checks of COFF_WITH_pe{AArch64,x64}
>> with a runtime check of the output architecture (via
>> pe_details->pe_arch?).
>>
>> Cc: Evgeny Karpov <evgeny.karpov@arm.com>
>> Fixes: c60b3806799a ("aarch64-pe support for LD, GAS and BFD")
>> Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
>>
>> 2026-05-29  Jon Turney  <jon.turney@dronecode.org.uk>
>>
>> 	* Makefile.am (EXTRA_ld_new_SOURCES): Update.
>> 	* Makefile.in: Regenerate.
>> 	* configure.tgt (tar_extra_ofiles): Update.
>> 	* pep-dll-aarch64.c: Remove.
>> 	* pep-dll-x86_64.c: Remove.
> 
> OK.

Thanks, applied.


From jon.turney@dronecode.org.uk  Thu Jun  4 13:22:37 2026
From: jon.turney@dronecode.org.uk (Jon Turney)
Date: Thu,  4 Jun 2026 14:22:37 +0100
Subject: [PATCH] ld: doc: Use consistent language for 'PE target'-only options
Message-ID: <20260604132237.5508-1-jon.turney@dronecode.org.uk>

It seems like the 'i386 PE targeted' phrasing probably predates x86_64
PE support in binutils, and should have been touched when that was
added.

Even loosely interpreting that phrase to mean 'those two Intel
architectures, you know what I mean', this is less than helpful now that
PE aarch64 is a possibility.

Change the use of various phrases like '[This is an i386 PE specific
option]' to conistently use '[This option is specific to PE targeted
ports of the linker]' nearly everywhere.

The only options that really are specific in this way are
'--large-address-aware' (PE only) and '--high-entropy-va' (PE+ only), so
annotate those appropriately.

Do an editing pass of the various other mentions of 'PE'.

Also, add the 'PE only' annotation to the description of
'--leading-underscore' in the 'Options Specific to PE Targets' section,
to be consistent with all the others.

Also, since we've already mentioned that all the DllCharacteristics
flags are PE-specific, don't awkwardly mention it (again) as part of the
note about what Windows version support for that flag was introduced in.

Future work: the phrase 'PE targeted port of the linker' seems a bit
off, since cross-tools are a thing. Should it just be 'PE targeted linker'?

2026-06-01  Jon Turney  <jon.turney@dronecode.org.uk>

	* ld.texi (Options): Use consistent language for 'PE target'-only
	options.
---
 ld/ld.texi | 92 ++++++++++++++++++++++++++++--------------------------
 1 file changed, 47 insertions(+), 45 deletions(-)

diff --git a/ld/ld.texi b/ld/ld.texi
index 23fcfb2e63d..9d6618a4307 100644
--- a/ld/ld.texi
+++ b/ld/ld.texi
@@ -540,8 +540,8 @@ and/or the trailing stdcall @samp{@@number} when applicable).
 Specifies a list of archive libraries from which symbols should not be automatically
 exported.  The library names may be delimited by commas or colons.  Specifying
 @code{--exclude-libs ALL} excludes symbols in all archive libraries from
-automatic export.  This option is available only for the i386 PE targeted
-port of the linker and for ELF targeted ports.  For i386 PE, symbols
+automatic export.  This option is available only for ELF and PE targeted
+ports of the linker.  For PE targets, symbols
 explicitly listed in a .def file are still exported, regardless of this
 option.  For ELF targeted ports, symbols affected by this option will
 be treated as hidden.
@@ -555,9 +555,9 @@ may be delimited by commas or colons, and must match exactly the filenames
 used by @command{ld} to open the files; for archive members, this is simply
 the member name, but for object files the name listed must include and
 match precisely any path used to specify the input file on the linker's
-command-line.  This option is available only for the i386 PE targeted port
-of the linker.  Symbols explicitly listed in a .def file are still exported,
+command-line. Symbols explicitly listed in a .def file are still exported,
 regardless of this option.
+[This option is specific to PE targeted ports of the linker]
 
 @cindex dynamic symbol table
 @kindex -E
@@ -2454,7 +2454,7 @@ library (which should be called @code{*.dll.a} or @code{*.a} for DLLs)
 may be used to link clients against the generated executable; this
 behaviour makes it possible to skip a separate import library creation
 step (eg. @code{dlltool} for DLLs).  This option is only available for
-the i386 PE and ELF targetted ports of the linker.
+the PE and ELF targetted ports of the linker.
 
 @kindex -pie
 @kindex --pic-executable
@@ -3447,11 +3447,11 @@ will be validated.
 
 @c man end
 
-@subsection Options Specific to i386 PE Targets
+@subsection Options Specific to PE Targets
 
 @c man begin OPTIONS
 
-The i386 PE linker supports the @option{-shared} option, which causes
+The PE linker supports the @option{-shared} option, which causes
 the output to be a dynamically linked library (DLL) instead of a
 normal executable.  You should name the output @code{*.dll} when you
 use this option.  In addition, the linker fully supports the standard
@@ -3460,8 +3460,8 @@ like an object file (in fact, it should precede archives it exports
 symbols from, to ensure that they get linked in, just like a normal
 object file).
 
-In addition to the options common to all targets, the i386 PE linker
-support additional command-line options that are specific to the i386
+In addition to the options common to all targets, the PE linker
+supports additional command-line options that are specific to the
 PE target.  Options that take values may be separated from their
 values by either a space or an equals sign.
 
@@ -3471,21 +3471,21 @@ values by either a space or an equals sign.
 @item --add-stdcall-alias
 If given, symbols with a stdcall suffix (@@@var{nn}) will be exported
 as-is and also with the suffix stripped.
-[This option is specific to the i386 PE targeted port of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 @kindex --base-file
 @item --base-file @var{file}
 Use @var{file} as the name of a file in which to save the base
 addresses of all the relocations needed for generating DLLs with
 @file{dlltool}.
-[This is an i386 PE specific option]
+[This option is specific to PE targeted ports of the linker]
 
 @kindex --dll
 @item --dll
 Create a DLL instead of a regular executable.  You may also use
 @option{-shared} or specify a @code{LIBRARY} in a given @code{.def}
 file.
-[This option is specific to the i386 PE targeted port of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 @kindex --enable-long-section-names
 @kindex --disable-long-section-names
@@ -3507,7 +3507,7 @@ option is specified on the command-line, @command{ld} will enable long
 section names, overriding the default and technically correct behaviour,
 when it finds the presence of debug information while linking an executable
 image and not stripping symbols.
-[This option is valid for all PE targeted ports of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 @kindex --enable-stdcall-fixup
 @kindex --disable-stdcall-fixup
@@ -3526,7 +3526,7 @@ to be usable.  If you specify @option{--enable-stdcall-fixup}, this
 feature is fully enabled and warnings are not printed.  If you specify
 @option{--disable-stdcall-fixup}, this feature is disabled and such
 mismatches are considered to be errors.
-[This option is specific to the i386 PE targeted port of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 @kindex --leading-underscore
 @kindex --no-leading-underscore
@@ -3535,6 +3535,7 @@ mismatches are considered to be errors.
 For most targets default symbol-prefix is an underscore and is defined
 in target's description. By this option it is possible to
 disable/enable the default underscore symbol-prefix.
+[This option is specific to PE targeted ports of the linker]
 
 @cindex DLLs, creating
 @kindex --export-all-symbols
@@ -3561,25 +3562,25 @@ These cygwin-excludes are: @code{_cygwin_dll_entry@@12},
 @code{_fmode}, @code{_impure_ptr}, @code{cygwin_attach_dll},
 @code{cygwin_premain0}, @code{cygwin_premain1}, @code{cygwin_premain2},
 @code{cygwin_premain3}, and @code{environ}.
-[This option is specific to the i386 PE targeted port of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 @kindex --exclude-symbols
 @item --exclude-symbols @var{symbol},@var{symbol},...
 Specifies a list of symbols which should not be automatically
 exported.  The symbol names may be delimited by commas or colons.
-[This option is specific to the i386 PE targeted port of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 @kindex --exclude-all-symbols
 @item --exclude-all-symbols
 Specifies no symbols should be automatically exported.
-[This option is specific to the i386 PE targeted port of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 @kindex --file-alignment
 @item --file-alignment
 Specify the file alignment.  Sections in the file will always begin at
 file offsets which are multiples of this number.  This defaults to
 512.
-[This option is specific to the i386 PE targeted port of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 @cindex heap size
 @kindex --heap
@@ -3588,13 +3589,13 @@ file offsets which are multiples of this number.  This defaults to
 Specify the number of bytes of memory to reserve (and optionally commit)
 to be used as heap for this program.  The default is 1MB reserved, 4K
 committed.
-[This option is specific to the i386 PE targeted port of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 @kindex --kill-at
 @item --kill-at
 If given, the stdcall suffixes (@@@var{nn}) will be stripped from
 symbols before they are exported.
-[This option is specific to the i386 PE targeted port of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 @kindex --large-address-aware
 @item --large-address-aware
@@ -3603,7 +3604,7 @@ header is set to indicate that this executable supports virtual addresses
 greater than 2 gigabytes.  This should be used in conjunction with the /3GB
 or /USERVA=@var{value} megabytes switch in the ``[operating systems]''
 section of the BOOT.INI.  Otherwise, this bit has no effect.
-[This option is specific to PE targeted ports of the linker]
+[This option is specific to the i386 PE targeted port of the linker]
 
 @kindex --disable-large-address-aware
 @item --disable-large-address-aware
@@ -3611,37 +3612,37 @@ Reverts the effect of a previous @samp{--large-address-aware} option.
 This is useful if @samp{--large-address-aware} is always set by the compiler
 driver (e.g. Cygwin gcc) and the executable does not support virtual
 addresses greater than 2 gigabytes.
-[This option is specific to PE targeted ports of the linker]
+[This option is specific to the i386 PE targeted port of the linker]
 
 @kindex --major-image-version
 @item --major-image-version @var{value}
 Sets the major number of the ``image version''.  Defaults to 1.
-[This option is specific to the i386 PE targeted port of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 @kindex --major-os-version
 @item --major-os-version @var{value}
 Sets the major number of the ``os version''.  Defaults to 4.
-[This option is specific to the i386 PE targeted port of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 @kindex --major-subsystem-version
 @item --major-subsystem-version @var{value}
 Sets the major number of the ``subsystem version''.  Defaults to 4.
-[This option is specific to the i386 PE targeted port of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 @kindex --minor-image-version
 @item --minor-image-version @var{value}
 Sets the minor number of the ``image version''.  Defaults to 0.
-[This option is specific to the i386 PE targeted port of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 @kindex --minor-os-version
 @item --minor-os-version @var{value}
 Sets the minor number of the ``os version''.  Defaults to 0.
-[This option is specific to the i386 PE targeted port of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 @kindex --minor-subsystem-version
 @item --minor-subsystem-version @var{value}
 Sets the minor number of the ``subsystem version''.  Defaults to 0.
-[This option is specific to the i386 PE targeted port of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 @cindex DEF files, creating
 @cindex DLLs, creating
@@ -3652,7 +3653,7 @@ file corresponding to the DLL the linker is generating.  This DEF file
 (which should be called @code{*.def}) may be used to create an import
 library with @code{dlltool} or may be used as a reference to
 automatically or implicitly exported symbols.
-[This option is specific to the i386 PE targeted port of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 @cindex DLLs, creating
 @kindex --enable-auto-image-base
@@ -3663,14 +3664,14 @@ Automatically choose the image base for DLLs, optionally starting with base
 By using a hash generated from the dllname to create unique image bases
 for each DLL, in-memory collisions and relocations which can delay program
 execution are avoided.
-[This option is specific to the i386 PE targeted port of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 @kindex --disable-auto-image-base
 @item --disable-auto-image-base
 Do not automatically generate a unique image base.  If there is no
 user-specified image base (@code{--image-base}) then use the platform
 default.
-[This option is specific to the i386 PE targeted port of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 @cindex DLLs, linking to
 @kindex --dll-search-prefix
@@ -3681,14 +3682,14 @@ search for @code{<string><basename>.dll} in preference to
 between DLLs built for the various "subplatforms": native, cygwin,
 uwin, pw, etc.  For instance, cygwin DLLs typically use
 @code{--dll-search-prefix=cyg}.
-[This option is specific to the i386 PE targeted port of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 @kindex --enable-auto-import
 @item --enable-auto-import
 Do sophisticated linking of @code{_symbol} to @code{__imp__symbol} for
 DATA imports from DLLs, thus making it possible to bypass the dllimport
 mechanism on the user side and to reference unmangled symbol names.
-[This option is specific to the i386 PE targeted port of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 The following remarks pertain to the original implementation of the
 feature and are obsolete nowadays for Cygwin and MinGW targets.
@@ -3822,7 +3823,7 @@ functions).
 @item --disable-auto-import
 Do not attempt to do sophisticated linking of @code{_symbol} to
 @code{__imp__symbol} for DATA imports from DLLs.
-[This option is specific to the i386 PE targeted port of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 @kindex --enable-runtime-pseudo-reloc
 @item --enable-runtime-pseudo-reloc
@@ -3830,23 +3831,23 @@ If your code contains expressions described in --enable-auto-import section,
 that is, DATA imports from DLL with non-zero offset, this switch will create
 a vector of 'runtime pseudo relocations' which can be used by runtime
 environment to adjust references to such data in your client code.
-[This option is specific to the i386 PE targeted port of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 @kindex --disable-runtime-pseudo-reloc
 @item --disable-runtime-pseudo-reloc
 Do not create pseudo relocations for non-zero offset DATA imports from DLLs.
-[This option is specific to the i386 PE targeted port of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 @kindex --enable-extra-pe-debug
 @item --enable-extra-pe-debug
 Show additional debug info related to auto-import symbol thunking.
-[This option is specific to the i386 PE targeted port of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 @kindex --section-alignment
 @item --section-alignment
 Sets the section alignment.  Sections in memory will always begin at
 addresses which are a multiple of this number.  Defaults to 0x1000.
-[This option is specific to the i386 PE targeted port of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 @cindex stack size
 @kindex --stack
@@ -3855,7 +3856,7 @@ addresses which are a multiple of this number.  Defaults to 0x1000.
 Specify the number of bytes of memory to reserve (and optionally commit)
 to be used as stack for this program.  The default is 2MB reserved, 4K
 committed.
-[This option is specific to the i386 PE targeted port of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 @kindex --subsystem
 @item --subsystem @var{which}
@@ -3866,7 +3867,7 @@ legal values for @var{which} are @code{native}, @code{windows},
 @code{console}, @code{posix}, and @code{xbox}.  You may optionally set
 the subsystem version also.  Numeric values are also accepted for
 @var{which}.
-[This option is specific to the i386 PE targeted port of the linker]
+[This option is specific to PE targeted ports of the linker]
 
 The following options set flags in the @code{DllCharacteristics} field
 of the PE file header:
@@ -3881,15 +3882,16 @@ MinGW targets.
 
 This option also implies @option{--dynamicbase} and
 @option{--enable-reloc-section}.
+[This options is specific to 64-bit PE targeted ports of the linker]
 
 @kindex --dynamicbase
 @item --dynamicbase
 @itemx --disable-dynamicbase
 The image base address may be relocated using address space layout
 randomization (ASLR).  This feature was introduced with MS Windows
-Vista for i386 PE targets.  This option is enabled by default for MinGW
-targets but can be disabled via the @option{--disable-dynamicbase}
-option. This option also implies @option{--enable-reloc-section}.
+Vista.  This option is enabled by default for MinGW targets but can be
+disabled via the @option{--disable-dynamicbase} option. This option
+also implies @option{--enable-reloc-section}.
 
 @kindex --forceinteg
 @item --forceinteg
@@ -3901,8 +3903,8 @@ default.
 @item --nxcompat
 @item --disable-nxcompat
 The image is compatible with the Data Execution Prevention.
-This feature was introduced with MS Windows XP SP2 for i386 PE
-targets.  The option is enabled by default for MinGW targets.
+This feature was introduced with MS Windows XP SP2. The option is
+enabled by default for MinGW targets.
 
 @kindex --no-isolation
 @item --no-isolation
-- 
2.51.0


From ludloff@gmail.com  Thu Jun  4 16:45:47 2026
From: ludloff@gmail.com (Christian Ludloff)
Date: Thu, 4 Jun 2026 09:45:47 -0700
Subject: [PATCH] x86: Support BHI_CTRL instruction
In-Reply-To: <SJ5PPF77D28E3C23853EA1BFBF81CCC55ECEC102@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>
References: <20260601062446.2367458-1-haochen.jiang@intel.com>
 <982f780d-c653-4a4d-bfa8-19bed76b1277@suse.com>
 <IA4PR11MB9009997D9669A4442CFF024DEC132@IA4PR11MB9009.namprd11.prod.outlook.com>
 <SJ5PPF77D28E3C27FBB50DC50A27FB579D4EC132@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>
 <7b3974e9-d03e-4492-8663-8abb9e1ea5c8@suse.com>
 <SJ5PPF77D28E3C295448A06B5215A8D0CCAEC132@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>
 <CAKSQd8VsEd9UD=bqc8w+HFs3LsySFOjrf+AmLV384cC_9pXwbg@mail.gmail.com>
 <SJ5PPF77D28E3C23853EA1BFBF81CCC55ECEC102@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>
Message-ID: <CAKSQd8WEYdY+vHFhr2N1W-dydg0y9rg9=WBOBXCqugznU7TZRQ@mail.gmail.com>

On Thu, Jun 4, 2026 at 12:39?AM Jiang, Haochen <haochen.jiang@intel.com> wrote:
> > From: Christian Ludloff <ludloff@gmail.com>
> > Arguably RDSSP{D,Q} is a litmus test ? can it REX2 or EVEX?
>
> I suppose it should be a REX2, not EVEX MAP4.

>From the perspective of the ISA, the W for D-vs-Q
can come from REX or REX2 or EVEX ? it should
not matter which of the three encodings gets used
for RDSSP. If that is not the case, then please get
it documented too, together with IBHF behavior.

--
C.

From rsaxvc@gmail.com  Thu Jun  4 21:14:16 2026
From: rsaxvc@gmail.com (Richard Allen)
Date: Thu, 4 Jun 2026 16:14:16 -0500
Subject: [PATCH] gprof: fix disappearing inlined functions
In-Reply-To: <CAENJYHq9c16aJo1vgZ7ugXfAN+ALGz_Z3pHbOYKPPm5RsvY_gA@mail.gmail.com>
References: <20260528022134.133959-2-rsaxvc@gmail.com>
 <CAMe9rOq5gAF0cHKuO_R6KJ2rto9etdY_2c4awXeYyiNBavqPow@mail.gmail.com>
 <CAENJYHq9c16aJo1vgZ7ugXfAN+ALGz_Z3pHbOYKPPm5RsvY_gA@mail.gmail.com>
Message-ID: <CAENJYHo37F+uMqidJAr2+OziwTmR=3gM7zW3ORzC=o=XSF9iig@mail.gmail.com>

There's a little more too this - I also need to handle optimizing compilers
interleaving instructions between inclined functions. Currently seems to
create multiple symbols with the same function name when that happens.

For testing, would it be ok to check in a small executable and gmon?
Otherwise we'd need to rerun it which will vary the results.
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From calc84maniac@gmail.com  Thu Jun  4 22:43:12 2026
From: calc84maniac@gmail.com (Brendan Fletcher)
Date: Thu,  4 Jun 2026 18:43:12 -0400
Subject: [PATCH] gas: Fix support for AL condition in Thumb-2 IT instruction
Message-ID: <20260604224311.423747-2-calc84maniac@gmail.com>

Using the AL condition in the IT instruction is designed to allow
encoding unconditional 16-bit instructions which do not affect flags.
GAS currently allows specifying the AL condition, but rejects any
following unconditional instructions because they are not considered
to be part of an IT block.

This change makes unconditional instructions allowed inside a
manually-specified IT AL block. Note, implicit IT AL blocks are still
intentionally never emitted.

This change also emits an error if any Else conditions are specified
in an IT AL, which would be an illegal encoding.

Signed-off-by: Brendan Fletcher <calc84maniac@gmail.com>
---
 gas/config/tc-arm.c                          | 14 +++--
 gas/testsuite/gas/arm/thumb2_it_always.d     | 62 ++++++++++++++++++
 gas/testsuite/gas/arm/thumb2_it_always.s     | 66 ++++++++++++++++++++
 gas/testsuite/gas/arm/thumb2_it_bad_always.d |  3 +
 gas/testsuite/gas/arm/thumb2_it_bad_always.l | 18 ++++++
 gas/testsuite/gas/arm/thumb2_it_bad_always.s | 32 ++++++++++
 6 files changed, 190 insertions(+), 5 deletions(-)
 create mode 100644 gas/testsuite/gas/arm/thumb2_it_always.d
 create mode 100644 gas/testsuite/gas/arm/thumb2_it_always.s
 create mode 100644 gas/testsuite/gas/arm/thumb2_it_bad_always.d
 create mode 100644 gas/testsuite/gas/arm/thumb2_it_bad_always.l
 create mode 100644 gas/testsuite/gas/arm/thumb2_it_bad_always.s

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 3ff29542411..8e1b8327db9 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -12232,9 +12232,10 @@ static void
 do_t_it (void)
 {
   unsigned int cond = inst.operands[0].imm;
+  unsigned int mask = inst.instruction & 0x000f;
 
   set_pred_insn_type (IT_INSN);
-  now_pred.mask = (inst.instruction & 0xf) | 0x10;
+  now_pred.mask = mask | 0x10;
   now_pred.cc = cond;
   now_pred.warn_deprecated = false;
   now_pred.type = SCALAR_PRED;
@@ -12242,8 +12243,6 @@ do_t_it (void)
   /* If the condition is a negative condition, invert the mask.  */
   if ((cond & 0x1) == 0x0)
     {
-      unsigned int mask = inst.instruction & 0x000f;
-
       if ((mask & 0x7) == 0)
 	{
 	  /* No conversion needed.  */
@@ -12270,6 +12269,10 @@ do_t_it (void)
     }
 
   inst.instruction |= cond << 4;
+
+  /* If unconditional, negative conditions are illegal. */
+  if (cond == COND_ALWAYS && (mask & (mask - 1)) != 0)
+    inst.error = BAD_IT_COND;
 }
 
 /* Helper function used for both push/pop and ldm/stm.  */
@@ -22727,8 +22730,9 @@ now_pred_add_mask (int cond)
 static void
 it_fsm_pre_encode (void)
 {
-  if (inst.cond != COND_ALWAYS)
-    inst.pred_insn_type =  INSIDE_IT_INSN;
+  if (inst.cond != COND_ALWAYS
+      || (now_pred.state == MANUAL_PRED_BLOCK && now_pred.cc == COND_ALWAYS))
+    inst.pred_insn_type = INSIDE_IT_INSN;
   else
     inst.pred_insn_type = OUTSIDE_PRED_INSN;
 
diff --git a/gas/testsuite/gas/arm/thumb2_it_always.d b/gas/testsuite/gas/arm/thumb2_it_always.d
new file mode 100644
index 00000000000..bb220f51e68
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb2_it_always.d
@@ -0,0 +1,62 @@
+# name: 16-bit Thumb unconditional instructions without flag-setting
+# as: -march=armv6kt2
+# objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0+000 <[^>]+> bfe1      	itttt	al
+0+002 <[^>]+> 1880      	addal	r0, r0, r2
+0+004 <[^>]+> 4440      	addal	r0, r8
+0+006 <[^>]+> 1888      	addal	r0, r1, r2
+0+008 <[^>]+> eb11 0002 	addsal.w	r0, r1, r2
+0+00c <[^>]+> 4410      	add	r0, r2
+0+00e <[^>]+> 4440      	add	r0, r8
+0+010 <[^>]+> 1880      	adds	r0, r0, r2
+0+012 <[^>]+> eb10 0008 	adds.w	r0, r0, r8
+0+016 <[^>]+> 1888      	adds	r0, r1, r2
+0+018 <[^>]+> bfe2      	ittt	al
+0+01a <[^>]+> 4310      	orral	r0, r2
+0+01c <[^>]+> ea40 0008 	orral.w	r0, r0, r8
+0+020 <[^>]+> ea50 0002 	orrsal.w	r0, r0, r2
+0+024 <[^>]+> ea40 0002 	orr.w	r0, r0, r2
+0+028 <[^>]+> ea40 0008 	orr.w	r0, r0, r8
+0+02c <[^>]+> 4310      	orrs	r0, r2
+0+02e <[^>]+> bfe1      	itttt	al
+0+030 <[^>]+> 4090      	lslal	r0, r2
+0+032 <[^>]+> fa00 f008 	lslal.w	r0, r0, r8
+0+036 <[^>]+> fa01 f002 	lslal.w	r0, r1, r2
+0+03a <[^>]+> fa10 f002 	lslsal.w	r0, r0, r2
+0+03e <[^>]+> bfe2      	ittt	al
+0+040 <[^>]+> 0048      	lslal	r0, r1, #1
+0+042 <[^>]+> ea4f 0048 	moval.w	r0, r8, lsl #1
+0+046 <[^>]+> ea5f 0040 	movsal.w	r0, r0, lsl #1
+0+04a <[^>]+> fa00 f002 	lsl.w	r0, r0, r2
+0+04e <[^>]+> 4090      	lsls	r0, r2
+0+050 <[^>]+> ea4f 0041 	mov.w	r0, r1, lsl #1
+0+054 <[^>]+> 0048      	lsls	r0, r1, #1
+0+056 <[^>]+> bfe1      	itttt	al
+0+058 <[^>]+> 4288      	cmpal	r0, r1
+0+05a <[^>]+> 4540      	cmpal	r0, r8
+0+05c <[^>]+> 4608      	moval	r0, r1
+0+05e <[^>]+> ea5f 0001 	movsal.w	r0, r1
+0+062 <[^>]+> bfe8      	it	al
+0+064 <[^>]+> 4640      	moval	r0, r8
+0+066 <[^>]+> 4608      	mov	r0, r1
+0+068 <[^>]+> 0008      	movs	r0, r1
+0+06a <[^>]+> ea5f 0008 	movs.w	r0, r8
+0+06e <[^>]+> bfe1      	itttt	al
+0+070 <[^>]+> 43c8      	mvnal	r0, r1
+0+072 <[^>]+> ea6f 0008 	mvnal.w	r0, r8
+0+076 <[^>]+> ea7f 0001 	mvnsal.w	r0, r1
+0+07a <[^>]+> 42c8      	cmnal	r0, r1
+0+07c <[^>]+> ea6f 0001 	mvn.w	r0, r1
+0+080 <[^>]+> 43c8      	mvns	r0, r1
+0+082 <[^>]+> bfe2      	ittt	al
+0+084 <[^>]+> 4248      	negal	r0, r1
+0+086 <[^>]+> f1c8 0000 	rsbal	r0, r8, #0
+0+08a <[^>]+> f1d1 0000 	rsbsal	r0, r1, #0
+0+08e <[^>]+> f1c1 0000 	rsb	r0, r1, #0
+0+092 <[^>]+> 4248      	negs	r0, r1
+0+094 <[^>]+> bfe8      	it	al
+0+096 <[^>]+> 4360      	mulal	r0, r4
diff --git a/gas/testsuite/gas/arm/thumb2_it_always.s b/gas/testsuite/gas/arm/thumb2_it_always.s
new file mode 100644
index 00000000000..ba25c1ac2c3
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb2_it_always.s
@@ -0,0 +1,66 @@
+	.text
+	.thumb
+	.syntax unified
+	.thumb_func
+foo:
+	itttt al
+	add r0, r0, r2
+	add r0, r0, r8
+	add r0, r1, r2
+	adds r0, r1, r2
+	add r0, r0, r2
+	add r0, r0, r8
+	adds r0, r0, r2
+	adds r0, r0, r8
+	adds r0, r1, r2
+
+	ittt al
+	orr r0, r0, r2
+	orr r0, r0, r8
+	orrs r0, r0, r2
+	orr r0, r0, r2
+	orr r0, r0, r8
+	orrs r0, r0, r2
+
+	itttt al
+	lsl r0, r0, r2
+	lsl r0, r0, r8
+	lsl r0, r1, r2
+	lsls r0, r0, r2
+	ittt al
+	lsl r0, r1, #1
+	lsl r0, r8, #1
+	lsls r0, r0, #1
+	lsl r0, r0, r2
+	lsls r0, r0, r2
+	lsl r0, r1, #1
+	lsls r0, r1, #1
+
+	itttt al
+	cmp r0, r1
+	cmp r0, r8
+	mov r0, r1
+	movs r0, r1
+	it al
+	mov r0, r8
+	mov r0, r1
+	movs r0, r1
+	movs r0, r8
+
+	itttt al
+	mvn r0, r1
+	mvn r0, r8
+	mvns r0, r1
+	cmn r0, r1
+	mvn r0, r1
+	mvns r0, r1
+
+	ittt al
+	neg r0, r1
+	neg r0, r8
+	negs r0, r1
+	neg r0, r1
+	negs r0, r1
+
+	it al
+	mul.n r0, r4
diff --git a/gas/testsuite/gas/arm/thumb2_it_bad_always.d b/gas/testsuite/gas/arm/thumb2_it_bad_always.d
new file mode 100644
index 00000000000..4d412d1b482
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb2_it_bad_always.d
@@ -0,0 +1,3 @@
+#name: Invalid unconditional IT instructions
+#as:
+#error_output: thumb2_it_bad_always.l
diff --git a/gas/testsuite/gas/arm/thumb2_it_bad_always.l b/gas/testsuite/gas/arm/thumb2_it_bad_always.l
new file mode 100644
index 00000000000..8e0b86cb556
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb2_it_bad_always.l
@@ -0,0 +1,18 @@
+[^:]*: Assembler messages:
+[^:]*:8: Error: branch must be last instruction in IT block -- `b foo'
+[^:]*:9: Error: branch must be last instruction in IT block -- `bl foo'
+[^:]*:10: Error: branch must be last instruction in IT block -- `blx r0'
+[^:]*:11: Error: instruction not allowed in IT block -- `cbz r0,foo'
+[^:]*:13: Error: branch must be last instruction in IT block -- `bx r0'
+[^:]*:14: Error: branch must be last instruction in IT block -- `tbb \[r0,r1\]'
+[^:]*:15: Error: instruction not allowed in IT block -- `cpsie f'
+[^:]*:17: Error: instruction not allowed in IT block -- `cps #0x10'
+[^:]*:20: Error: instruction not allowed in IT block -- `setend le'
+[^:]*:22: Error: IT falling in the range of a previous IT block -- `ital al'
+[^:]*:25: Error: instruction not allowed in IT block -- `csdb'
+[^:]*:26: Error: instruction not allowed in IT block -- `ssbb'
+[^:]*:27: Error: instruction not allowed in IT block -- `pssbb'
+[^:]*:28: Error: incorrect condition in IT block -- `itet al'
+[^:]*:29: Error: Thumb-2 MUL must not set flags -- `muls r0,r1'
+[^:]*:30: Error: incorrect condition in IT block -- `mul.n r0,r1'
+[^:]*:31: Error: cannot honor width suffix -- `movs.n r0,r1'
diff --git a/gas/testsuite/gas/arm/thumb2_it_bad_always.s b/gas/testsuite/gas/arm/thumb2_it_bad_always.s
new file mode 100644
index 00000000000..356f1ca5ca8
--- /dev/null
+++ b/gas/testsuite/gas/arm/thumb2_it_bad_always.s
@@ -0,0 +1,32 @@
+	.text
+	.syntax unified
+	.arch armv7a
+	.thumb
+	.thumb_func
+thumb2_it_bad:
+	itttt	al
+	b	foo
+	bl	foo
+	blx	r0
+	cbz	r0, foo
+	ittt	al
+	bx	r0
+	tbb	[r0, r1]
+	cpsie	f
+	it	al
+	cps	#0x10
+	itt	al
+	bkpt	0
+	setend	le
+	it	al
+	ital	al
+	nop
+	ittt	al
+	csdb
+	ssbb
+	pssbb
+	itet	al
+	muls	r0, r1
+	mul.n	r0, r1
+	movs.n	r0, r1
+foo:
-- 
2.43.0


From hjl.tools@gmail.com  Thu Jun  4 23:03:09 2026
From: hjl.tools@gmail.com (H.J. Lu)
Date: Fri, 5 Jun 2026 07:03:09 +0800
Subject: [PATCH] gprof: fix disappearing inlined functions
In-Reply-To: <CAENJYHo37F+uMqidJAr2+OziwTmR=3gM7zW3ORzC=o=XSF9iig@mail.gmail.com>
References: <20260528022134.133959-2-rsaxvc@gmail.com>
 <CAMe9rOq5gAF0cHKuO_R6KJ2rto9etdY_2c4awXeYyiNBavqPow@mail.gmail.com>
 <CAENJYHq9c16aJo1vgZ7ugXfAN+ALGz_Z3pHbOYKPPm5RsvY_gA@mail.gmail.com>
 <CAENJYHo37F+uMqidJAr2+OziwTmR=3gM7zW3ORzC=o=XSF9iig@mail.gmail.com>
Message-ID: <CAMe9rOo7YFp_GHTDMpiAwXumv4QqXW0SxomKUSzSOx88wc1Yhg@mail.gmail.com>

On Fri, Jun 5, 2026, 5:14?AM Richard Allen <rsaxvc@gmail.com> wrote:

> There's a little more too this - I also need to handle optimizing
> compilers interleaving instructions between inclined functions. Currently
> seems to create multiple symbols with the same function name when that
> happens.
>
> For testing, would it be ok to check in a small executable and gmon?
> Otherwise we'd need to rerun it which will vary the results.
>

We need a test which fails without your patch.
-------------- next part --------------
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From haochen.jiang@intel.com  Fri Jun  5 06:02:25 2026
From: haochen.jiang@intel.com (Jiang, Haochen)
Date: Fri, 5 Jun 2026 06:02:25 +0000
Subject: [PATCH] x86: Support BHI_CTRL instruction
In-Reply-To: <CAKSQd8WEYdY+vHFhr2N1W-dydg0y9rg9=WBOBXCqugznU7TZRQ@mail.gmail.com>
References: <20260601062446.2367458-1-haochen.jiang@intel.com>
 <982f780d-c653-4a4d-bfa8-19bed76b1277@suse.com>
 <IA4PR11MB9009997D9669A4442CFF024DEC132@IA4PR11MB9009.namprd11.prod.outlook.com>
 <SJ5PPF77D28E3C27FBB50DC50A27FB579D4EC132@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>
 <7b3974e9-d03e-4492-8663-8abb9e1ea5c8@suse.com>
 <SJ5PPF77D28E3C295448A06B5215A8D0CCAEC132@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>
 <CAKSQd8VsEd9UD=bqc8w+HFs3LsySFOjrf+AmLV384cC_9pXwbg@mail.gmail.com>
 <SJ5PPF77D28E3C23853EA1BFBF81CCC55ECEC102@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>
 <CAKSQd8WEYdY+vHFhr2N1W-dydg0y9rg9=WBOBXCqugznU7TZRQ@mail.gmail.com>
Message-ID: <SJ5PPF77D28E3C23A2D5CE91FB0A7591A7DEC112@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>

> From: Christian Ludloff <ludloff@gmail.com>
> Sent: Friday, June 5, 2026 12:46 AM
> 
> On Thu, Jun 4, 2026 at 12:39?AM Jiang, Haochen <haochen.jiang@intel.com>
> wrote:
> > > From: Christian Ludloff <ludloff@gmail.com>
> > > Arguably RDSSP{D,Q} is a litmus test ? can it REX2 or EVEX?
> >
> > I suppose it should be a REX2, not EVEX MAP4.
> 
> From the perspective of the ISA, the W for D-vs-Q
> can come from REX or REX2 or EVEX ? it should
> not matter which of the three encodings gets used
> for RDSSP. If that is not the case, then please get
> it documented too, together with IBHF behavior.
> 

APX documentation has mentioned which instructions could be
promoted to EVEX MAP4. Only the inst mentioned in chart could
use EVEX MAP4. Actually, those EVEX MAP4 insts are all listed
one by one in EAS since the encoding are quite different.

Thx,
Haochen 

From ludloff@gmail.com  Fri Jun  5 06:25:26 2026
From: ludloff@gmail.com (Christian Ludloff)
Date: Thu, 4 Jun 2026 23:25:26 -0700
Subject: [PATCH] x86: Support BHI_CTRL instruction
In-Reply-To: <SJ5PPF77D28E3C23A2D5CE91FB0A7591A7DEC112@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>
References: <20260601062446.2367458-1-haochen.jiang@intel.com>
 <982f780d-c653-4a4d-bfa8-19bed76b1277@suse.com>
 <IA4PR11MB9009997D9669A4442CFF024DEC132@IA4PR11MB9009.namprd11.prod.outlook.com>
 <SJ5PPF77D28E3C27FBB50DC50A27FB579D4EC132@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>
 <7b3974e9-d03e-4492-8663-8abb9e1ea5c8@suse.com>
 <SJ5PPF77D28E3C295448A06B5215A8D0CCAEC132@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>
 <CAKSQd8VsEd9UD=bqc8w+HFs3LsySFOjrf+AmLV384cC_9pXwbg@mail.gmail.com>
 <SJ5PPF77D28E3C23853EA1BFBF81CCC55ECEC102@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>
 <CAKSQd8WEYdY+vHFhr2N1W-dydg0y9rg9=WBOBXCqugznU7TZRQ@mail.gmail.com>
 <SJ5PPF77D28E3C23A2D5CE91FB0A7591A7DEC112@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>
Message-ID: <CAKSQd8UHSibHQjBnVYAuNrcaUXDL+Awv=hwi7W9b4yGsQZ_P7Q@mail.gmail.com>

On Thu, Jun 4, 2026 at 11:02?PM Jiang, Haochen <haochen.jiang@intel.com> wrote:
> > > > Arguably RDSSP{D,Q} is a litmus test ? can it REX2 or EVEX?
> > >
> > > I suppose it should be a REX2, not EVEX MAP4.
> >
> > From the perspective of the ISA, the W for D-vs-Q
> > can come from REX or REX2 or EVEX ? it should
> > not matter which of the three encodings gets used
> > for RDSSP. If that is not the case, then please get
> > it documented too, together with IBHF behavior.
>
> APX documentation has mentioned which instructions could be
> promoted to EVEX MAP4. Only the inst mentioned in chart could
> use EVEX MAP4. Actually, those EVEX MAP4 insts are all listed
> one by one in EAS since the encoding are quite different.

Sure, MAP4 is documented as a "no".

But MAP1 otoh...  :-)

0x62,0xF9,0x7E,0x08,0x1E,0xC8
0x62,0xF9,0xFE,0x08,0x1E,0xC8

--
C.

From haochen.jiang@intel.com  Fri Jun  5 06:35:35 2026
From: haochen.jiang@intel.com (Jiang, Haochen)
Date: Fri, 5 Jun 2026 06:35:35 +0000
Subject: [PATCH] x86: Support BHI_CTRL instruction
In-Reply-To: <CAKSQd8UHSibHQjBnVYAuNrcaUXDL+Awv=hwi7W9b4yGsQZ_P7Q@mail.gmail.com>
References: <20260601062446.2367458-1-haochen.jiang@intel.com>
 <982f780d-c653-4a4d-bfa8-19bed76b1277@suse.com>
 <IA4PR11MB9009997D9669A4442CFF024DEC132@IA4PR11MB9009.namprd11.prod.outlook.com>
 <SJ5PPF77D28E3C27FBB50DC50A27FB579D4EC132@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>
 <7b3974e9-d03e-4492-8663-8abb9e1ea5c8@suse.com>
 <SJ5PPF77D28E3C295448A06B5215A8D0CCAEC132@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>
 <CAKSQd8VsEd9UD=bqc8w+HFs3LsySFOjrf+AmLV384cC_9pXwbg@mail.gmail.com>
 <SJ5PPF77D28E3C23853EA1BFBF81CCC55ECEC102@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>
 <CAKSQd8WEYdY+vHFhr2N1W-dydg0y9rg9=WBOBXCqugznU7TZRQ@mail.gmail.com>
 <SJ5PPF77D28E3C23A2D5CE91FB0A7591A7DEC112@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>
 <CAKSQd8UHSibHQjBnVYAuNrcaUXDL+Awv=hwi7W9b4yGsQZ_P7Q@mail.gmail.com>
Message-ID: <SJ5PPF77D28E3C2B6FA022307D54B93CB6BEC112@SJ5PPF77D28E3C2.namprd11.prod.outlook.com>

> From: Christian Ludloff <ludloff@gmail.com>
> Sent: Friday, June 5, 2026 2:25 PM
> To: Jiang, Haochen <haochen.jiang@intel.com>
> Cc: Beulich, Jan <JBeulich@suse.com>; hjl.tools@gmail.com;
> binutils@sourceware.org
> Subject: Re: [PATCH] x86: Support BHI_CTRL instruction
> 
> On Thu, Jun 4, 2026 at 11:02?PM Jiang, Haochen <haochen.jiang@intel.com>
> wrote:
> > > > > Arguably RDSSP{D,Q} is a litmus test ? can it REX2 or EVEX?
> > > >
> > > > I suppose it should be a REX2, not EVEX MAP4.
> > >
> > > From the perspective of the ISA, the W for D-vs-Q
> > > can come from REX or REX2 or EVEX ? it should
> > > not matter which of the three encodings gets used
> > > for RDSSP. If that is not the case, then please get
> > > it documented too, together with IBHF behavior.
> >
> > APX documentation has mentioned which instructions could be
> > promoted to EVEX MAP4. Only the inst mentioned in chart could
> > use EVEX MAP4. Actually, those EVEX MAP4 insts are all listed
> > one by one in EAS since the encoding are quite different.
> 
> Sure, MAP4 is documented as a "no".
> 
> But MAP1 otoh...  :-)
> 
> 0x62,0xF9,0x7E,0x08,0x1E,0xC8
> 0x62,0xF9,0xFE,0x08,0x1E,0xC8
> 

RDSSP{D,Q} are only legacy encodings, they have nothing to do with
EVEX encoding. So, they should obey legacy space rule, not EVEX space
rule in APX. Those rules are quite clear in documentation. I did not quite
get your confusion here.

Thx,
Haochen


From mengqinggang@loongson.cn  Fri Jun  5 06:41:07 2026
From: mengqinggang@loongson.cn (mengqinggang)
Date: Fri, 5 Jun 2026 14:41:07 +0800
Subject: [PATCH v1] LoongArch: Fix relaxation alignment with ld -r (PR
 33236)
In-Reply-To: <20260529074340.943231-1-mengqinggang@loongson.cn>
References: <20260529074340.943231-1-mengqinggang@loongson.cn>
Message-ID: <d22fb9e3-c526-4fed-966e-5489f438f56e@loongson.cn>

Gentle ping.


? 2026/5/29 15:43, mengqinggang ??:
> LoongArch has the same issue as RISC-V for PR 33236 [1].
>
> Section alignment can't be adjusted for objects generated by ld -r.
> If previous sections are relaxed, the subsequent section maybe misaligned.
>
> To fix this, add an align section and an align relocation before each section
> when ld -r. And disabling the default section start address calculation.
>
> ld.lld has fixed this issue in the following two patches [2] [3].
>
> [1] https://sourceware.org/bugzilla/show_bug.cgi?id=33236
> [2] https://github.com/llvm/llvm-project/pull/151639
> [3] https://github.com/llvm/llvm-project/pull/198147
> ---
>   bfd/elfnn-loongarch.c                         | 152 +++++++++++++++
>   bfd/elfxx-loongarch.h                         |  10 +
>   ld/emultempl/loongarchelf.em                  | 182 ++++++++++++++++++
>   ld/ldlang.c                                   |   8 +-
>   .../ld-loongarch-elf/relax-align-ld-r.d       |   9 +
>   .../ld-loongarch-elf/relax-align-ld-r.s       |  12 ++
>   ld/testsuite/ld-loongarch-elf/relax.exp       |   4 +
>   7 files changed, 376 insertions(+), 1 deletion(-)
>   create mode 100644 ld/testsuite/ld-loongarch-elf/relax-align-ld-r.d
>   create mode 100644 ld/testsuite/ld-loongarch-elf/relax-align-ld-r.s
>
> diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c
> index 8f8ec3b0789..ddd321d896f 100644
> --- a/bfd/elfnn-loongarch.c
> +++ b/bfd/elfnn-loongarch.c
> @@ -7067,6 +7067,158 @@ elf_loongarch64_hash_symbol (struct elf_link_hash_entry *h)
>     return _bfd_elf_hash_symbol (h);
>   }
>   
> +/* Write nops to align section.  */
> +
> +static bool
> +loongarch_build_align_nops (asection *section, asection *align_section)
> +{
> +  if (section->output_section == NULL
> +      || align_section->output_section == NULL)
> +    {
> +      _bfd_error_handler (_("Could not assign to an output section."));
> +      return false;
> +    }
> +
> +  bfd_byte *loc = align_section->contents;
> +  for (bfd_size_type i = 0; i < (align_section->size / 4); i++)
> +    {
> +      bfd_putl32 (LARCH_NOP, loc);
> +      loc += 4;
> +    }
> +
> +  return true;
> +}
> +
> +/* Emit an align relocation and a related undefined symbol.  */
> +
> +static bool
> +loongarch_add_align_relocs (asection *sec,
> +			    asection *align_sec,
> +			    bfd* align_bfd)
> +{
> +  elf_backend_data *bed = get_elf_backend_data (align_bfd);
> +
> +  if (elf_section_data (align_sec)->relocs == NULL)
> +    {
> +      align_sec->reloc_count = 1;
> +      align_sec->flags |= SEC_RELOC;
> +
> +      Elf_Internal_Rela *rela = (Elf_Internal_Rela *)
> +	bfd_malloc (sizeof (Elf_Internal_Rela));
> +      if (rela == NULL)
> +	return false;
> +
> +      rela->r_offset = 0;
> +      rela->r_addend = (1 << sec->alignment_power) - 4;
> +      rela->r_info = ELFNN_R_INFO (0, R_LARCH_ALIGN);
> +      elf_section_data (align_sec)->relocs = rela;
> +
> +      Elf_Internal_Shdr *rela_hdr = (Elf_Internal_Shdr *)
> +	bfd_zalloc (align_bfd, sizeof (Elf_Internal_Shdr));
> +      if (rela_hdr == NULL)
> +       return false;
> +
> +      rela_hdr->sh_size = sizeof (Elf_Internal_Rela);
> +      rela_hdr->sh_entsize = sizeof (Elf_Internal_Rela);
> +      rela_hdr->sh_type = SHT_RELA;
> +      rela_hdr->sh_addralign = (bfd_vma) 1 << bed->s->log_file_align;
> +      elf_section_data (align_sec)->rela.hdr = rela_hdr;
> +    }
> +
> +  /* Used in loongarch_elf_relax_section for align relocations.  */
> +  Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (align_bfd);
> +  if (symtab_hdr->contents == NULL)
> +    {
> +      Elf_Internal_Sym *sym = (Elf_Internal_Sym *)
> +	bfd_zmalloc (sizeof (Elf_Internal_Sym));
> +      if (sym == NULL)
> +	return false;
> +
> +      /* Match if (r_symndx < symtab_hdr->sh_info) branch in
> +	 loongarch_elf_relocate_section to avoid find link failed.  */
> +      symtab_hdr->sh_info = 1;
> +//      symtab_hdr->sh_size = sizeof (Elf_Internal_Sym);
> +//      symtab_hdr->sh_entsize = sizeof (Elf_Internal_Sym);
> +//      symtab_hdr->sh_type = SHT_SYMTAB;
> +//      symtab_hdr->sh_addralign = (bfd_vma) 1 << bed->s->log_file_align;
> +      symtab_hdr->contents = (unsigned char *) sym;
> +    }
> +
> +  return true;
> +}
> +
> +/* Section name for aligns is the associated section name plus this
> +   string.  */
> +#define ALIGN_SUFFIX ".align"
> +
> +/* Determine and set the size of the align section for a final link.  */
> +
> +bool
> +elfNN_loongarch_size_aligns (bfd *output_bfd,
> +			     bfd *align_bfd,
> +			     struct bfd_link_info *info,
> +			     asection * (*add_align_section)
> +					  (const char *, asection *),
> +			     void (*layout_sections_again) (void))
> +{
> +  bool need_laying_out = false;
> +  for (bfd *input_bfd = info->input_bfds; input_bfd != NULL;
> +       input_bfd = input_bfd->link.next)
> +    {
> +      asection *sec;
> +      asection *align_sec;
> +
> +      if (!is_loongarch_elf (input_bfd)
> +	  || (input_bfd->flags & BFD_LINKER_CREATED) != 0)
> +	continue;
> +
> +      for (sec = input_bfd->sections; sec != NULL; sec = sec->next)
> +	{
> +	  /* If this section is not a code section, do nothing.  */
> +	  if ((sec->flags & SEC_CODE) == 0)
> +	    continue;
> +
> +	  /* If this section is a link-once section that will be
> +	     discarded, then don't create any stubs.  */
> +	  if (sec->output_section == NULL
> +	      || sec->output_section->owner != output_bfd)
> +	    continue;
> +
> +	  if (sec->alignment_power > 2)
> +	    {
> +	      char *s_name;
> +	      size_t namelen;
> +	      bfd_size_type len;
> +	      namelen = strlen (sec->name);
> +	      len = namelen + sizeof (ALIGN_SUFFIX);
> +	      s_name = bfd_alloc (align_bfd, len);
> +	      if (s_name == NULL)
> +		return false;
> +	      memcpy (s_name, sec->name, namelen);
> +	      memcpy (s_name + namelen, ALIGN_SUFFIX, sizeof (ALIGN_SUFFIX));
> +
> +	      align_sec = add_align_section (s_name, sec);
> +
> +	      if (align_sec == NULL)
> +		return false;
> +
> +	      if (! loongarch_build_align_nops (sec, align_sec))
> +		return false;
> +
> +	      if (! loongarch_add_align_relocs (sec, align_sec, align_bfd))
> +		return false;
> +
> +	      need_laying_out = true;
> +	    }
> +	}
> +    }
> +
> +  if (need_laying_out)
> +    layout_sections_again ();
> +
> +  return true;
> +}
> +
>   #define TARGET_LITTLE_SYM loongarch_elfNN_vec
>   #define TARGET_LITTLE_NAME "elfNN-loongarch"
>   #define ELF_ARCH bfd_arch_loongarch
> diff --git a/bfd/elfxx-loongarch.h b/bfd/elfxx-loongarch.h
> index 400b7377ccd..b295b7a9070 100644
> --- a/bfd/elfxx-loongarch.h
> +++ b/bfd/elfxx-loongarch.h
> @@ -45,6 +45,16 @@ bfd_elf64_loongarch_set_data_segment_info (struct bfd_link_info *, int *);
>   bfd_byte *
>   loongarch_write_unsigned_leb128 (bfd_byte *, size_t, bfd_vma) ATTRIBUTE_HIDDEN;
>   
> +extern bool elf64_loongarch_size_aligns
> +  (bfd *, bfd *, struct bfd_link_info *,
> +   struct bfd_section * (*) (const char *, struct bfd_section *),
> +   void (*) (void));
> +
> +extern bool elf32_loongarch_size_aligns
> +  (bfd *, bfd *, struct bfd_link_info *,
> +   struct bfd_section * (*) (const char *, struct bfd_section *),
> +   void (*) (void));
> +
>   /* TRUE if this is a PLT reference to a local IFUNC.  */
>   #define PLT_LOCAL_IFUNC_P(INFO, H) \
>     ((H)->dynindx == -1 \
> diff --git a/ld/emultempl/loongarchelf.em b/ld/emultempl/loongarchelf.em
> index 5f9d4106629..bbb9c378781 100644
> --- a/ld/emultempl/loongarchelf.em
> +++ b/ld/emultempl/loongarchelf.em
> @@ -41,6 +41,10 @@ PARSE_AND_LIST_ARGS_CASES=${PARSE_AND_LIST_ARGS_CASES}'
>   '
>   
>   fragment <<EOF
> +
> +/* Fake input file for align.  */
> +static lang_input_statement_type *align_file;
> +
>   static void
>   larch_elf_before_allocation (void)
>   {
> @@ -61,6 +65,136 @@ larch_elf_before_allocation (void)
>     link_info.relax_pass = 3;
>   }
>   
> +/* Traverse the linker tree to insert the align section
> +   before input section.  */
> +
> +static bool
> +hook_in_align (lang_statement_list_type add,
> +	       asection *input_section,
> +	       lang_statement_union_type **lp)
> +{
> +  bool ret;
> +  lang_statement_union_type *l;
> +
> +  for (; (l = *lp) != NULL; lp = &l->header.next)
> +    {
> +      switch (l->header.type)
> +	{
> +	case lang_constructors_statement_enum:
> +	  ret = hook_in_align (add, input_section, &constructor_list.head);
> +	  if (ret)
> +	    return ret;
> +	  break;
> +
> +	case lang_output_section_statement_enum:
> +	  ret = hook_in_align (add, input_section,
> +			       &l->output_section_statement.children.head);
> +	  if (ret)
> +	    return ret;
> +	  break;
> +
> +	case lang_wild_statement_enum:
> +	  ret = hook_in_align (add, input_section,
> +			       &l->wild_statement.children.head);
> +	  if (ret)
> +	    return ret;
> +	  break;
> +
> +	case lang_group_statement_enum:
> +	  ret = hook_in_align (add, input_section,
> +			       &l->group_statement.children.head);
> +	  if (ret)
> +	    return ret;
> +	  break;
> +
> +	case lang_input_section_enum:
> +	  if (l->input_section.section == input_section)
> +	    {
> +	      /* We've found our section.  Insert the align immediately
> +		 before its associated input section.  */
> +	      //*(add.tail) = l->header.next;
> +	      //l->header.next = add.head;
> +	      *lp = add.head;
> +	      add.head->header.next = l;
> +	      return true;
> +	    }
> +	  break;
> +
> +	case lang_data_statement_enum:
> +	case lang_reloc_statement_enum:
> +	case lang_object_symbols_statement_enum:
> +	case lang_output_statement_enum:
> +	case lang_target_statement_enum:
> +	case lang_input_statement_enum:
> +	case lang_assignment_statement_enum:
> +	case lang_padding_statement_enum:
> +	case lang_address_statement_enum:
> +	case lang_fill_statement_enum:
> +	  break;
> +
> +	default:
> +	  FAIL ();
> +	  break;
> +	}
> +    }
> +
> +  return false;
> +}
> +
> +/* Create a new align section, and arrange for it to be linked
> +   immediately before INPUT_SECTION.  */
> +
> +static asection *
> +elf${ELFSIZE}_loongarch_add_align_section (const char *align_sec_name,
> +					   asection *input_section)
> +{
> +  flagword flags;
> +  asection *align_sec;
> +  asection *output_section;
> +  lang_statement_list_type add_child;
> +  lang_output_section_statement_type *os;
> +
> +  flags = (SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
> +	   | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY | SEC_KEEP);
> +  align_sec = bfd_make_section_anyway_with_flags (align_file->the_bfd,
> +						  align_sec_name, flags);
> +  if (align_sec == NULL)
> +    goto err_ret;
> +
> +  align_sec->veneer = 1;
> +  bfd_set_section_alignment (align_sec, 2);
> +
> +  output_section = input_section->output_section;
> +  os = lang_output_section_get (output_section);
> +
> +  lang_list_init (&add_child);
> +  lang_add_section (&add_child, align_sec, NULL, NULL, os);
> +
> +  if (add_child.head == NULL)
> +    goto err_ret;
> +
> +  align_sec->size = (1 << input_section->alignment_power) - 4;
> +  align_sec->contents = bfd_alloc (align_file->the_bfd, align_sec->size);
> +  if (align_sec->contents == NULL && align_sec->size != 0)
> +    goto err_ret;
> +  align_sec->alloced = 1;
> +
> +  if (hook_in_align (add_child, input_section, &os->children.head))
> +    return align_sec;
> +
> + err_ret:
> +  einfo (_("%X%P: can not make align section: %E\n"));
> +  return NULL;
> +}
> +
> +static void
> +gldloongarch_layout_sections_again (void)
> +{
> +  /* If we have changed sizes of the align sections, then we need
> +     to recalculate all the section offsets.  */
> +  ldelf_map_segments (true);
> +}
> +
>   static void
>   gld${EMULATION_NAME}_after_allocation (void)
>   {
> @@ -78,6 +212,21 @@ gld${EMULATION_NAME}_after_allocation (void)
>   	}
>       }
>   
> +  /* If generating a relocatable output file, we have to add align
> +     at the start of sections.  */
> +  if (align_file != NULL && bfd_link_relocatable (&link_info))
> +    {
> +      if (! elf${ELFSIZE}_loongarch_size_aligns (link_info.output_bfd,
> +			align_file->the_bfd,
> +			&link_info,
> +			&elf${ELFSIZE}_loongarch_add_align_section,
> +			&gldloongarch_layout_sections_again))
> +	{
> +	  einfo (_("%X%P: can not size align section: %E\n"));
> +	  return;
> +	}
> +    }
> +
>     /* The program header size of executable file may increase.  */
>     if (bfd_get_flavour (link_info.output_bfd) == bfd_target_elf_flavour
>         && !bfd_link_relocatable (&link_info))
> @@ -101,7 +250,40 @@ gld${EMULATION_NAME}_after_allocation (void)
>     ldelf_map_segments (need_layout);
>   }
>   
> +/* This is called before the input files are opened.  We create a new
> +   fake input file to hold the align sections.  */
> +
> +static void
> +loongarch_elf_create_output_section_statements (void)
> +{
> +  if (! bfd_link_relocatable (&link_info))
> +    return;
> +
> +  align_file = lang_add_input_file ("linker aligns",
> +				    lang_input_file_is_fake_enum,
> +				    NULL);
> +  align_file->the_bfd = bfd_create ("linker aligns",
> +				    link_info.output_bfd);
> +  if (align_file->the_bfd == NULL
> +      || ! bfd_set_arch_mach (align_file->the_bfd,
> +			      bfd_get_arch (link_info.output_bfd),
> +			      bfd_get_mach (link_info.output_bfd)))
> +    {
> +      fatal (_("%P: can not create BFD: %E\n"));
> +      return;
> +    }
> +
> +  align_file->the_bfd->flags |= BFD_LINKER_CREATED;
> +
> +  Elf_Internal_Ehdr *ehdr = elf_elfheader (align_file->the_bfd);
> +  elf_backend_data *bed = get_elf_backend_data (link_info.output_bfd);
> +  ehdr->e_ident[EI_CLASS] = bed->s->elfclass;
> +
> +  ldlang_add_file (align_file);
> +}
> +
>   EOF
>   
>   LDEMUL_BEFORE_ALLOCATION=larch_elf_before_allocation
>   LDEMUL_AFTER_ALLOCATION=gld${EMULATION_NAME}_after_allocation
> +LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS=loongarch_elf_create_output_section_statements
> diff --git a/ld/ldlang.c b/ld/ldlang.c
> index 48dd33a49bb..8c3c287a3a0 100644
> --- a/ld/ldlang.c
> +++ b/ld/ldlang.c
> @@ -5769,6 +5769,10 @@ size_input_section
>       {
>         bfd_size_type alignment_needed;
>   
> +      bool synthesize_align = bfd_link_relocatable (&link_info)
> +			      && (i->flags & SEC_CODE) != 0
> +			      && bfd_get_arch (i->owner) == bfd_arch_loongarch;
> +
>         /* Align this section first to the input sections requirement,
>   	 then to the output section's requirement.  If this alignment
>   	 is greater than any seen before, then record it too.  Perform
> @@ -5788,7 +5792,9 @@ size_input_section
>   
>         alignment_needed = align_power (dot, i->alignment_power) - dot;
>   
> -      if (alignment_needed != 0)
> +      /* If synthesized ALIGN may be needed, add one align section
> +	 and one align relocation and disable the default handling.  */
> +      if (alignment_needed != 0 && ! synthesize_align)
>   	{
>   	  insert_pad (this_ptr, fill, TO_SIZE (alignment_needed), o, dot);
>   	  dot += alignment_needed;
> diff --git a/ld/testsuite/ld-loongarch-elf/relax-align-ld-r.d b/ld/testsuite/ld-loongarch-elf/relax-align-ld-r.d
> new file mode 100644
> index 00000000000..a2d19734a59
> --- /dev/null
> +++ b/ld/testsuite/ld-loongarch-elf/relax-align-ld-r.d
> @@ -0,0 +1,9 @@
> +#as:
> +#ld: -r
> +#objdump: -Dr
> +
> +#...
> +.*R_LARCH_ALIGN.*
> +#...
> +.*R_LARCH_ALIGN.*
> +#...
> diff --git a/ld/testsuite/ld-loongarch-elf/relax-align-ld-r.s b/ld/testsuite/ld-loongarch-elf/relax-align-ld-r.s
> new file mode 100644
> index 00000000000..19555a7148e
> --- /dev/null
> +++ b/ld/testsuite/ld-loongarch-elf/relax-align-ld-r.s
> @@ -0,0 +1,12 @@
> +# Add an align section before text section when ld -r.
> +# There will be two R_LARCH_ALIGN relocations after ld -r.
> +.text
> +  addi.d $a0, $a0, 1
> +  call36 func
> +  .align 3
> +func:
> +  addi.d $a0, $a0, 1
> +
> +# Only add a align section for code section.
> +.data
> +  .4byte 0x1234
> diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp
> index 7c32a65244c..066f1893042 100644
> --- a/ld/testsuite/ld-loongarch-elf/relax.exp
> +++ b/ld/testsuite/ld-loongarch-elf/relax.exp
> @@ -46,6 +46,10 @@ proc run_partial_linking_align_test {} {
>     }
>   }
>   
> +if [istarget loongarch*-*-*] {
> +  run_dump_test "relax-align-ld-r"
> +}
> +
>   if [istarget loongarch64-*-*] {
>     if [isbuild loongarch64-*-*] {
>       run_dump_test "relax-align-ignore-start"


From jbeulich@suse.com  Fri Jun  5 09:27:55 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 5 Jun 2026 11:27:55 +0200
Subject: [PATCH v2 00/16] RISC-V: assorted fixes and (hopefully)
 improvements
In-Reply-To: <c32643f7-c8b2-4a0e-9eeb-4ba00369b147@suse.com>
References: <c32643f7-c8b2-4a0e-9eeb-4ba00369b147@suse.com>
Message-ID: <f6c4fecf-57ff-4510-8a02-fca12ba22b75@suse.com>

On 15.05.2026 15:27, Jan Beulich wrote:
> There may not be many dependencies among the patches, but the issues
> were all noticed more or less together (i.e. while addressing one,
> the next one popped up). I've not made an attempt at sorting the V vs
> Z?inx issue, as per Andrew's request.
> 
> Quite a few further points are made in remarks in individual patches.
> Input there is very welcome.
> 
> Jiawei kindly reviewed v1, and I committed a few patches from there
> which I assumed were pretty sure to be uncontroversial. For the others
> I'd prefer RISC-V maintainer approval, yet I'm not going to wait
> indefinitely.
> 
> There aren't many changes in v2, the most prominent perhaps being the
> new 1st patch. See individual changes for what changed, if anything.
> 
> 01: rename operand descriptor O4
> 02: RISC-V: fold redundant code in riscv_ip()
> 03: RISC-V: add dedicated vector arithmetic .insn forms
> 04: RISC-V: match_*() improvements
> 05: RISC-V: EEW64 checking
> 06: bfd/RISC-V: Zvfbfwma implies Zvfbfmin
> 07: RISC-V: drop FCVT.Q.L{,U} forms with rounding mode operand
> 08: RISC-V: make FP rounding mode an optional argument
> 09: RISC-V: check operands for Zdinx in RV32
> 10: RISC-V: riscv_set_arch() can fail
> 11: RISC-V: riscv_parse_subset_t's isa_spec is only parser input
> 12: RISC-V: error handling for subset parsing
> 13: RISC-V: avoid buffer underrun in subset parsing
> 14: RISC-V: drop dead code from subset parsing
> 15: bfd/RISC-V: move _bfd_riscv_elf_merge_private_bfd_data()
> 16: RISC-V/gas: .attribute vs .insn

And some follow-on-s to observations noted in some of the above:

17: warn about non-boolean unaligned-access attribute
18: warn about non-power-of-2 stack-align attribute
19: check operands for Zqinx

Jan

From jbeulich@suse.com  Fri Jun  5 09:29:08 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 5 Jun 2026 11:29:08 +0200
Subject: [PATCH v2 17/16] RISC-V: warn about non-boolean unaligned-access
 attribute
In-Reply-To: <f6c4fecf-57ff-4510-8a02-fca12ba22b75@suse.com>
References: <c32643f7-c8b2-4a0e-9eeb-4ba00369b147@suse.com>
 <f6c4fecf-57ff-4510-8a02-fca12ba22b75@suse.com>
Message-ID: <fedefae5-cf7c-44ee-9ce1-8525678c816e@suse.com>

The attribute being a boolean one, values should be solely 0 or 1.
---
Should libbfd's riscv_merge_attributes() also emit a warning?

Shouldn't settings accumulate, much like what riscv_merge_attributes()
does?
---
v2: New.

--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -5859,14 +5859,13 @@ s_riscv_attribute (int ignored ATTRIBUTE
 {
   obj_attr_tag_t tag = obj_attr_process_attribute (OBJ_ATTR_PROC);
   unsigned old_xlen;
-  obj_attribute *attr;
+  const obj_attribute *attr = elf_known_obj_attributes_proc (stdoutput);
 
   explicit_attr = true;
   switch (tag)
     {
     case Tag_RISCV_arch:
       old_xlen = xlen;
-      attr = elf_known_obj_attributes_proc (stdoutput);
       if (!start_assemble)
 	riscv_set_arch (attr[Tag_RISCV_arch].s);
       else
@@ -5892,6 +5891,11 @@ s_riscv_attribute (int ignored ATTRIBUTE
 		   "any instructions"));
       break;
 
+    case Tag_RISCV_unaligned_access:
+      if (attr[Tag_RISCV_unaligned_access].i > 1)
+	as_warn (_("`unaligned_access' attribute with non-boolean value"));
+      break;
+
     default:
       break;
     }
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-warn.d
@@ -0,0 +1,7 @@
+#as: -march-attr
+#readelf: -A
+#warning_output: attribute-warn.l
+
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: [a-zA-Z0-9_\"].*
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-warn.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*:2: Warning: `unaligned_access' attribute with non-boolean value
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-warn.s
@@ -0,0 +1,3 @@
+	.attribute unaligned_access, 1
+	.attribute unaligned_access, 0x1234
+	.attribute unaligned_access, 0


From jbeulich@suse.com  Fri Jun  5 09:29:30 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 5 Jun 2026 11:29:30 +0200
Subject: [PATCH v2 18/16] RISC-V: warn about non-power-of-2 stack-align
 attribute
In-Reply-To: <f6c4fecf-57ff-4510-8a02-fca12ba22b75@suse.com>
References: <c32643f7-c8b2-4a0e-9eeb-4ba00369b147@suse.com>
 <f6c4fecf-57ff-4510-8a02-fca12ba22b75@suse.com>
Message-ID: <c47d3248-b5e3-4c60-9c87-0d5c7705a8d6@suse.com>

Only power-of-2 values are sensible for alignment.
---
Should libbfd's riscv_merge_attributes() also emit a warning?

Should we reject changing an already set non-zero value, like
riscv_merge_attributes() does?

Should we permit 0 as an explicit indication of "attribute not set"?
---
v2: New.

--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -5891,6 +5891,13 @@ s_riscv_attribute (int ignored ATTRIBUTE
 		   "any instructions"));
       break;
 
+    case Tag_RISCV_stack_align:
+      if (!attr[Tag_RISCV_stack_align].i
+	  || (attr[Tag_RISCV_stack_align].i &
+	      (attr[Tag_RISCV_stack_align].i - 1)))
+	as_warn (_("`stack_align' attribute with non-power-of-2 value"));
+      break;
+
     case Tag_RISCV_unaligned_access:
       if (attr[Tag_RISCV_unaligned_access].i > 1)
 	as_warn (_("`unaligned_access' attribute with non-boolean value"));
--- a/gas/testsuite/gas/riscv/attribute-warn.d
+++ b/gas/testsuite/gas/riscv/attribute-warn.d
@@ -4,4 +4,5 @@
 
 Attribute Section: riscv
 File Attributes
+  Tag_RISCV_stack_align: 65536-bytes
   Tag_RISCV_arch: [a-zA-Z0-9_\"].*
--- a/gas/testsuite/gas/riscv/attribute-warn.l
+++ b/gas/testsuite/gas/riscv/attribute-warn.l
@@ -1,2 +1,4 @@
 .*: Assembler messages:
 .*:2: Warning: `unaligned_access' attribute with non-boolean value
+.*:5: Warning: `stack_align' attribute with non-power-of-2 value
+.*:6: Warning: `stack_align' attribute with non-power-of-2 value
--- a/gas/testsuite/gas/riscv/attribute-warn.s
+++ b/gas/testsuite/gas/riscv/attribute-warn.s
@@ -1,3 +1,7 @@
 	.attribute unaligned_access, 1
 	.attribute unaligned_access, 0x1234
 	.attribute unaligned_access, 0
+
+	.attribute stack_align, 0
+	.attribute stack_align, 0x4444
+	.attribute stack_align, 0x10000


From jbeulich@suse.com  Fri Jun  5 09:30:06 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 5 Jun 2026 11:30:06 +0200
Subject: [PATCH v2 19/16] RISC-V: check operands for Zqinx
In-Reply-To: <f6c4fecf-57ff-4510-8a02-fca12ba22b75@suse.com>
References: <c32643f7-c8b2-4a0e-9eeb-4ba00369b147@suse.com>
 <f6c4fecf-57ff-4510-8a02-fca12ba22b75@suse.com>
Message-ID: <dc1fac23-a06d-4353-8e3d-1e66fb18946d@suse.com>

By analogy to Zdinx on RV32, register pair operands are presumably (there
not being any formal spec afaict) required to be encoded with the low bit
clear in RV64; in RV32 the low two bits need to be clear. Since match
functions don't have XLEN available, introduce respective flags, to be
used explicitly in assembler and disassembler.
---
Does Zqinx actually make much sense in RV32? Function argument passing,
for example, ends up odd: a0..a3 aren't suitable to hold an argument.
Hence only a single argument can be passed in registers (a2..a5).

No similar checking is easily possible for scalar vector insns, as element
width there isn't encoded in the insn. (Plus V and Zqinx can't be enabled
together right now anyway.)
---
v2: New.

--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -2934,6 +2934,12 @@ riscv_ip (char *str, struct riscv_cl_ins
    || (rclass) != RCLASS_GPR                     \
    || !((regno) & 1))
 
+#define RV64_EVEN_CHECK(form, rclass, regno)     \
+  (!(ip->insn_mo->pinfo & INSN_RV64_EVEN_##form) \
+   || xlen > 64                                  \
+   || (rclass) != RCLASS_GPR                     \
+   || !((regno) & (xlen == 32 ? 3 : 1)))
+
       for (oparg = insn->args;; ++oparg)
 	{
 	  opargStart = oparg;
@@ -3593,12 +3599,14 @@ riscv_ip (char *str, struct riscv_cl_ins
 		  switch (c)
 		    {
 		    case 'D':
-		      if (!RV32_EVEN_CHECK (D, rclass, regno))
+		      if (!RV32_EVEN_CHECK (D, rclass, regno)
+			  || !RV64_EVEN_CHECK (D, rclass, regno))
 			break;
 		      INSERT_OPERAND (RD, *ip, regno);
 		      continue;
 		    case 'S':
-		      if (!RV32_EVEN_CHECK (S, rclass, regno))
+		      if (!RV32_EVEN_CHECK (S, rclass, regno)
+			  || !RV64_EVEN_CHECK (S, rclass, regno))
 			break;
 		      INSERT_OPERAND (RS1, *ip, regno);
 		      continue;
@@ -3606,12 +3614,14 @@ riscv_ip (char *str, struct riscv_cl_ins
 		      INSERT_OPERAND (RS1, *ip, regno);
 		      /* Fall through.  */
 		    case 'T':
-		      if (!RV32_EVEN_CHECK (T, rclass, regno))
+		      if (!RV32_EVEN_CHECK (T, rclass, regno)
+			  || !RV64_EVEN_CHECK (T, rclass, regno))
 			break;
 		      INSERT_OPERAND (RS2, *ip, regno);
 		      continue;
 		    case 'R':
-		      if (!RV32_EVEN_CHECK (R, rclass, regno))
+		      if (!RV32_EVEN_CHECK (R, rclass, regno)
+			  || !RV64_EVEN_CHECK (R, rclass, regno))
 			break;
 		      INSERT_OPERAND (RS3, *ip, regno);
 		      continue;
@@ -4312,6 +4322,7 @@ riscv_ip (char *str, struct riscv_cl_ins
     }
 
 #undef RV32_EVEN_CHECK
+#undef RV64_EVEN_CHECK
 
  out:
   /* Restore the character we might have clobbered above.  */
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-rv32.d
@@ -0,0 +1,52 @@
+#as: -march=rv32i_zqinx
+#objdump: -dwr
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+078a7453[ 	]+fadd\.q[ 	]+s0,s4,s8
+[ 	]+[0-9a-f]+:[ 	]+078a0453[ 	]+fadd\.q[ 	]+s0,s4,s8,rne
+[ 	]+[0-9a-f]+:[ 	]+0f8a7453[ 	]+fsub\.q[ 	]+s0,s4,s8
+[ 	]+[0-9a-f]+:[ 	]+0f8a0453[ 	]+fsub\.q[ 	]+s0,s4,s8,rne
+[ 	]+[0-9a-f]+:[ 	]+178a7453[ 	]+fmul\.q[ 	]+s0,s4,s8
+[ 	]+[0-9a-f]+:[ 	]+178a0453[ 	]+fmul\.q[ 	]+s0,s4,s8,rne
+[ 	]+[0-9a-f]+:[ 	]+1f8a7453[ 	]+fdiv\.q[ 	]+s0,s4,s8
+[ 	]+[0-9a-f]+:[ 	]+1f8a0453[ 	]+fdiv\.q[ 	]+s0,s4,s8,rne
+[ 	]+[0-9a-f]+:[ 	]+5e0a7453[ 	]+fsqrt\.q[ 	]+s0,s4
+[ 	]+[0-9a-f]+:[ 	]+5e0a0453[ 	]+fsqrt\.q[ 	]+s0,s4,rne
+[ 	]+[0-9a-f]+:[ 	]+2f8a0453[ 	]+fmin\.q[ 	]+s0,s4,s8
+[ 	]+[0-9a-f]+:[ 	]+2f8a1453[ 	]+fmax\.q[ 	]+s0,s4,s8
+[ 	]+[0-9a-f]+:[ 	]+678a7443[ 	]+fmadd\.q[ 	]+s0,s4,s8,a2
+[ 	]+[0-9a-f]+:[ 	]+678a0443[ 	]+fmadd\.q[ 	]+s0,s4,s8,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+678a744f[ 	]+fnmadd\.q[ 	]+s0,s4,s8,a2
+[ 	]+[0-9a-f]+:[ 	]+678a044f[ 	]+fnmadd\.q[ 	]+s0,s4,s8,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+678a7447[ 	]+fmsub\.q[ 	]+s0,s4,s8,a2
+[ 	]+[0-9a-f]+:[ 	]+678a0447[ 	]+fmsub\.q[ 	]+s0,s4,s8,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+678a744b[ 	]+fnmsub\.q[ 	]+s0,s4,s8,a2
+[ 	]+[0-9a-f]+:[ 	]+678a044b[ 	]+fnmsub\.q[ 	]+s0,s4,s8,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+c60a75d3[ 	]+fcvt\.w\.q[ 	]+a1,s4
+[ 	]+[0-9a-f]+:[ 	]+c60a05d3[ 	]+fcvt\.w\.q[ 	]+a1,s4,rne
+[ 	]+[0-9a-f]+:[ 	]+c61a75d3[ 	]+fcvt\.wu\.q[ 	]+a1,s4
+[ 	]+[0-9a-f]+:[ 	]+c61a05d3[ 	]+fcvt\.wu\.q[ 	]+a1,s4,rne
+[ 	]+[0-9a-f]+:[ 	]+d6058453[ 	]+fcvt\.q\.w[ 	]+s0,a1
+[ 	]+[0-9a-f]+:[ 	]+d6158453[ 	]+fcvt\.q\.wu[ 	]+s0,a1
+[ 	]+[0-9a-f]+:[ 	]+46058453[ 	]+fcvt\.q\.s[ 	]+s0,a1
+[ 	]+[0-9a-f]+:[ 	]+403a75d3[ 	]+fcvt\.s\.q[ 	]+a1,s4
+[ 	]+[0-9a-f]+:[ 	]+403a05d3[ 	]+fcvt\.s\.q[ 	]+a1,s4,rne
+[ 	]+[0-9a-f]+:[ 	]+46150453[ 	]+fcvt\.q\.d[ 	]+s0,a0
+[ 	]+[0-9a-f]+:[ 	]+423a7553[ 	]+fcvt\.d\.q[ 	]+a0,s4
+[ 	]+[0-9a-f]+:[ 	]+423a0553[ 	]+fcvt\.d\.q[ 	]+a0,s4,rne
+[ 	]+[0-9a-f]+:[ 	]+46258453[ 	]+fcvt\.q\.h[ 	]+s0,a1
+[ 	]+[0-9a-f]+:[ 	]+443a75d3[ 	]+fcvt\.h\.q[ 	]+a1,s4
+[ 	]+[0-9a-f]+:[ 	]+443a05d3[ 	]+fcvt\.h\.q[ 	]+a1,s4,rne
+[ 	]+[0-9a-f]+:[ 	]+278a0453[ 	]+fsgnj\.q[ 	]+s0,s4,s8
+[ 	]+[0-9a-f]+:[ 	]+278a1453[ 	]+fsgnjn\.q[ 	]+s0,s4,s8
+[ 	]+[0-9a-f]+:[ 	]+278a2453[ 	]+fsgnjx\.q[ 	]+s0,s4,s8
+[ 	]+[0-9a-f]+:[ 	]+a78a25d3[ 	]+feq\.q[ 	]+a1,s4,s8
+[ 	]+[0-9a-f]+:[ 	]+a78a15d3[ 	]+flt\.q[ 	]+a1,s4,s8
+[ 	]+[0-9a-f]+:[ 	]+a78a05d3[ 	]+fle\.q[ 	]+a1,s4,s8
+[ 	]+[0-9a-f]+:[ 	]+a74c15d3[ 	]+flt\.q[ 	]+a1,s8,s4
+[ 	]+[0-9a-f]+:[ 	]+a74c05d3[ 	]+fle\.q[ 	]+a1,s8,s4
+[ 	]+[0-9a-f]+:[ 	]+274a0453[ 	]+fmv\.q[ 	]+s0,s4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-rv32.s
@@ -0,0 +1,54 @@
+target:
+	fadd.q		s0, s4, s8
+	fadd.q		s0, s4, s8, rne
+	fsub.q		s0, s4, s8
+	fsub.q		s0, s4, s8, rne
+	fmul.q		s0, s4, s8
+	fmul.q		s0, s4, s8, rne
+	fdiv.q		s0, s4, s8
+	fdiv.q		s0, s4, s8, rne
+	fsqrt.q		s0, s4
+	fsqrt.q		s0, s4, rne
+	fmin.q		s0, s4, s8
+	fmax.q		s0, s4, s8
+	fmadd.q		s0, s4, s8, a2
+	fmadd.q		s0, s4, s8, a2, rne
+	fnmadd.q	s0, s4, s8, a2
+	fnmadd.q	s0, s4, s8, a2, rne
+	fmsub.q		s0, s4, s8, a2
+	fmsub.q		s0, s4, s8, a2, rne
+	fnmsub.q	s0, s4, s8, a2
+	fnmsub.q	s0, s4, s8, a2, rne
+
+	fcvt.w.q	a1, s4
+	fcvt.w.q	a1, s4, rne
+	fcvt.wu.q	a1, s4
+	fcvt.wu.q	a1, s4, rne
+	fcvt.q.w	s0, a1
+	fcvt.q.wu	s0, a1
+
+	fcvt.q.s	s0, a1
+	fcvt.s.q	a1, s4
+	fcvt.s.q	a1, s4, rne
+
+	fcvt.q.d	s0, a0
+	fcvt.d.q	a0, s4
+	fcvt.d.q	a0, s4, rne
+
+	.option push
+	.option arch, +zhinxmin
+	fcvt.q.h	s0, a1
+	fcvt.h.q	a1, s4
+	fcvt.h.q	a1, s4, rne
+	.option pop
+
+	fsgnj.q		s0, s4, s8
+	fsgnjn.q	s0, s4, s8
+	fsgnjx.q	s0, s4, s8
+	feq.q		a1, s4, s8
+	flt.q		a1, s4, s8
+	fle.q		a1, s4, s8
+	fgt.q		a1, s4, s8
+	fge.q		a1, s4, s8
+
+	fmv.q		s0, s4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-rv32-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_zqinx
+#source: zqinx.s
+#error_output: zqinx-rv32-fail.l
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-rv32-fail.l
@@ -0,0 +1,42 @@
+.*: Assembler messages:
+.*: Error: illegal operands `fadd\.q .*'
+.*: Error: illegal operands `fadd\.q .*'
+.*: Error: illegal operands `fsub\.q .*'
+.*: Error: illegal operands `fsub\.q .*'
+.*: Error: illegal operands `fmul\.q .*'
+.*: Error: illegal operands `fmul\.q .*'
+.*: Error: illegal operands `fdiv\.q .*'
+.*: Error: illegal operands `fdiv\.q .*'
+.*: Error: illegal operands `fsqrt\.q .*'
+.*: Error: illegal operands `fsqrt\.q .*'
+.*: Error: illegal operands `fmin\.q .*'
+.*: Error: illegal operands `fmax\.q .*'
+.*: Error: illegal operands `fmadd\.q .*'
+.*: Error: illegal operands `fmadd\.q .*'
+.*: Error: illegal operands `fnmadd\.q .*'
+.*: Error: illegal operands `fnmadd\.q .*'
+.*: Error: illegal operands `fmsub\.q .*'
+.*: Error: illegal operands `fmsub\.q .*'
+.*: Error: illegal operands `fnmsub\.q .*'
+.*: Error: illegal operands `fnmsub\.q .*'
+.*: Error: unrecognized opcode `fcvt\.l\.q .*'
+.*: Error: unrecognized opcode `fcvt\.l\.q .*'
+.*: Error: unrecognized opcode `fcvt\.lu\.q .*'
+.*: Error: unrecognized opcode `fcvt\.lu\.q .*'
+.*: Error: illegal operands `fcvt\.q\.w .*'
+.*: Error: illegal operands `fcvt\.q\.wu .*'
+.*: Error: unrecognized opcode `fcvt\.q\.l .*'
+.*: Error: unrecognized opcode `fcvt\.q\.lu .*'
+.*: Error: illegal operands `fcvt\.q\.s .*'
+.*: Error: illegal operands `fcvt\.q\.d .*'
+.*: Error: illegal operands `fsgnj\.q .*'
+.*: Error: illegal operands `fsgnjn\.q .*'
+.*: Error: illegal operands `fsgnjx\.q .*'
+.*: Error: illegal operands `feq\.q .*'
+.*: Error: illegal operands `flt\.q .*'
+.*: Error: illegal operands `fle\.q .*'
+.*: Error: illegal operands `fgt\.q .*'
+.*: Error: illegal operands `fge\.q .*'
+.*: Error: illegal operands `fmv\.q .*'
+.*: Error: illegal operands `fneg\.q .*'
+.*: Error: illegal operands `fabs\.q .*'
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-rv64-fail.d
@@ -0,0 +1,2 @@
+#as: -march=rv64i_zqinx
+#error_output: zqinx-rv64-fail.l
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-rv64-fail.l
@@ -0,0 +1,62 @@
+.*: Assembler messages:
+.*: Error: illegal operands `fadd\.q .*'
+.*: Error: illegal operands `fadd\.q .*'
+.*: Error: illegal operands `fadd\.q .*'
+.*: Error: illegal operands `fsub\.q .*'
+.*: Error: illegal operands `fsub\.q .*'
+.*: Error: illegal operands `fsub\.q .*'
+.*: Error: illegal operands `fmul\.q .*'
+.*: Error: illegal operands `fmul\.q .*'
+.*: Error: illegal operands `fmul\.q .*'
+.*: Error: illegal operands `fdiv\.q .*'
+.*: Error: illegal operands `fdiv\.q .*'
+.*: Error: illegal operands `fdiv\.q .*'
+.*: Error: illegal operands `fsqrt\.q .*'
+.*: Error: illegal operands `fsqrt\.q .*'
+.*: Error: illegal operands `fmin\.q .*'
+.*: Error: illegal operands `fmin\.q .*'
+.*: Error: illegal operands `fmin\.q .*'
+.*: Error: illegal operands `fmax\.q .*'
+.*: Error: illegal operands `fmax\.q .*'
+.*: Error: illegal operands `fmax\.q .*'
+.*: Error: illegal operands `fmadd\.q .*'
+.*: Error: illegal operands `fmadd\.q .*'
+.*: Error: illegal operands `fmadd\.q .*'
+.*: Error: illegal operands `fmadd\.q .*'
+.*: Error: illegal operands `fnmadd\.q .*'
+.*: Error: illegal operands `fnmadd\.q .*'
+.*: Error: illegal operands `fnmadd\.q .*'
+.*: Error: illegal operands `fnmadd\.q .*'
+.*: Error: illegal operands `fmsub\.q .*'
+.*: Error: illegal operands `fmsub\.q .*'
+.*: Error: illegal operands `fmsub\.q .*'
+.*: Error: illegal operands `fmsub\.q .*'
+.*: Error: illegal operands `fnmsub\.q .*'
+.*: Error: illegal operands `fnmsub\.q .*'
+.*: Error: illegal operands `fnmsub\.q .*'
+.*: Error: illegal operands `fnmsub\.q .*'
+.*: Error: illegal operands `fcvt\.w\.q .*'
+.*: Error: illegal operands `fcvt\.wu\.q .*'
+.*: Error: illegal operands `fcvt\.q\.w .*'
+.*: Error: illegal operands `fcvt\.q\.wu .*'
+.*: Error: illegal operands `fcvt\.q\.s .*'
+.*: Error: illegal operands `fcvt\.s\.q .*'
+.*: Error: illegal operands `fcvt\.q\.d .*'
+.*: Error: illegal operands `fcvt\.d\.q .*'
+.*: Error: illegal operands `fcvt\.q\.h .*'
+.*: Error: illegal operands `fcvt\.h\.q .*'
+.*: Error: illegal operands `fsgnj\.q .*'
+.*: Error: illegal operands `fsgnjn\.q .*'
+.*: Error: illegal operands `fsgnjx\.q .*'
+.*: Error: illegal operands `feq\.q .*'
+.*: Error: illegal operands `flt\.q .*'
+.*: Error: illegal operands `fle\.q .*'
+.*: Error: illegal operands `fgt\.q .*'
+.*: Error: illegal operands `fge\.q .*'
+.*: Error: illegal operands `fmv\.q .*'
+.*: Error: illegal operands `fmv\.q .*'
+.*: Error: illegal operands `fneg\.q .*'
+.*: Error: illegal operands `fneg\.q .*'
+.*: Error: illegal operands `fabs\.q .*'
+.*: Error: illegal operands `fabs\.q .*'
+.*: Error: illegal operands `fclass\.q .*'
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-rv64-fail.s
@@ -0,0 +1,70 @@
+target:
+	fadd.q		s1, s4, s8
+	fadd.q		s0, s5, s8
+	fadd.q		s0, s4, s9
+	fsub.q		s1, s4, s8
+	fsub.q		s0, s5, s8
+	fsub.q		s0, s4, s9
+	fmul.q		s1, s4, s8
+	fmul.q		s0, s5, s8
+	fmul.q		s0, s4, s9
+	fdiv.q		s1, s4, s8
+	fdiv.q		s0, s5, s8
+	fdiv.q		s0, s4, s9
+	fsqrt.q		s1, s4
+	fsqrt.q		s0, s5
+	fmin.q		s1, s4, s8
+	fmin.q		s0, s5, s8
+	fmin.q		s0, s4, s9
+	fmax.q		s1, s4, s8
+	fmax.q		s0, s5, s8
+	fmax.q		s0, s4, s9
+	fmadd.q		s1, s4, s8, a2
+	fmadd.q		s0, s5, s8, a2
+	fmadd.q		s0, s4, s9, a2
+	fmadd.q		s0, s4, s8, a3
+	fnmadd.q	s1, s4, s8, a2
+	fnmadd.q	s0, s5, s8, a2
+	fnmadd.q	s0, s4, s9, a2
+	fnmadd.q	s0, s4, s8, a3
+	fmsub.q		s1, s4, s8, a2
+	fmsub.q		s0, s5, s8, a2
+	fmsub.q		s0, s4, s9, a2
+	fmsub.q		s0, s4, s8, a3
+	fnmsub.q	s1, s4, s8, a2
+	fnmsub.q	s0, s5, s8, a2
+	fnmsub.q	s0, s4, s9, a2
+	fnmsub.q	s0, s4, s8, a3
+
+	fcvt.w.q	a0, s5
+	fcvt.wu.q	a0, s5
+	fcvt.q.w	s1, a0
+	fcvt.q.wu	s1, a0
+
+	fcvt.q.s	s1, a0
+	fcvt.s.q	a0, s5
+
+	fcvt.q.d	s1, a0
+	fcvt.d.q	a0, s5
+
+	.option push
+	.option arch, +zhinxmin
+	fcvt.q.h	s1, a0
+	fcvt.h.q	a0, s5
+	.option pop
+
+	fsgnj.q		s1, s4, s8
+	fsgnjn.q	s0, s5, s8
+	fsgnjx.q	s0, s4, s9
+	feq.q		a0, s5, s8
+	flt.q		a0, s4, s9
+	fle.q		a0, s5, s8
+	fgt.q		a0, s4, s9
+	fge.q		a0, s5, s8
+	fmv.q		s1, s4
+	fmv.q		s0, s5
+	fneg.q		s1, s4
+	fneg.q		s0, s5
+	fabs.q		s1, s4
+	fabs.q		s0, s5
+	fclass.q	a0, s5
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -691,6 +691,19 @@ struct riscv_opcode
 #define INSN_RV32_EVEN_DU	(INSN_RV32_EVEN_D   | INSN_RV32_EVEN_T)
 #define INSN_RV32_EVEN_ST	(INSN_RV32_EVEN_S   | INSN_RV32_EVEN_T)
 
+/* Operands required to be an even-numbered register (pair) in RV64, and one
+   divisble by 4 on RV32.  */
+#define INSN_RV64_EVEN_D	0x00001000
+#define INSN_RV64_EVEN_S	0x00002000
+#define INSN_RV64_EVEN_T	0x00004000 /* Also covering U.  */
+#define INSN_RV64_EVEN_R	0x00008000
+/* Shorthands for combinations of the above.  */
+#define INSN_RV64_EVEN_DS	(INSN_RV64_EVEN_D   | INSN_RV64_EVEN_S)
+#define INSN_RV64_EVEN_DST	(INSN_RV64_EVEN_DS  | INSN_RV64_EVEN_T)
+#define INSN_RV64_EVEN_DSTR	(INSN_RV64_EVEN_DST | INSN_RV64_EVEN_R)
+#define INSN_RV64_EVEN_DU	(INSN_RV64_EVEN_D   | INSN_RV64_EVEN_T)
+#define INSN_RV64_EVEN_ST	(INSN_RV64_EVEN_S   | INSN_RV64_EVEN_T)
+
 /* Instruction is actually a macro.  It should be ignored by the
    disassembler, and requires special treatment by the assembler.  */
 #define INSN_MACRO		0xffffffff
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -1049,6 +1049,25 @@ riscv_disassemble_insn (bfd_vma memaddr,
 		      && (word & (1u << OP_SH_RS3)))
 		    continue;
 		}
+
+	      if (pd->xlen <= 64
+		  && riscv_subset_supports (&pd->riscv_rps_dis, "zqinx"))
+		{
+		  unsigned int mask = pd->xlen == 32 ? 3 : 1;
+
+		  if ((op->pinfo & INSN_RV64_EVEN_D)
+		      && (word & (mask << OP_SH_RD)))
+		    continue;
+		  if ((op->pinfo & INSN_RV64_EVEN_S)
+		      && (word & (mask << OP_SH_RS1)))
+		    continue;
+		  if ((op->pinfo & INSN_RV64_EVEN_T)
+		      && (word & (mask << OP_SH_RS2)))
+		    continue;
+		  if ((op->pinfo & INSN_RV64_EVEN_R)
+		      && (word & (mask << OP_SH_RS3)))
+		    continue;
+		}
 	    }
 
 	  /* It's a match.  */
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -932,10 +932,10 @@ const struct riscv_opcode riscv_opcodes[
 {"fcvt.h.wu",  0, INSN_CLASS_ZFH_INX,  "D,sm",      MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 },
 {"fcvt.s.h",   0, INSN_CLASS_ZFHMIN_INX, "D,S",     MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 },
 {"fcvt.d.h",   0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,S", MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, INSN_RV32_EVEN_D },
-{"fcvt.q.h",   0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 },
+{"fcvt.q.h",   0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, INSN_RV64_EVEN_D },
 {"fcvt.h.s",   0, INSN_CLASS_ZFHMIN_INX, "D,Sm",    MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 },
 {"fcvt.h.d",   0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,Sm", MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, INSN_RV32_EVEN_S },
-{"fcvt.h.q",   0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,Sm", MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 },
+{"fcvt.h.q",   0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,Sm", MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, INSN_RV64_EVEN_S },
 {"fclass.h",   0, INSN_CLASS_ZFH_INX,   "d,S",       MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 },
 {"feq.h",      0, INSN_CLASS_ZFH_INX,   "d,S,T",     MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 },
 {"flt.h",      0, INSN_CLASS_ZFH_INX,   "d,S,T",     MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
@@ -1062,41 +1062,41 @@ const struct riscv_opcode riscv_opcodes[
 {"flq",        0, INSN_CLASS_Q,   "D,A,s",     0, (int) M_FLx, match_rs1_nonzero, INSN_MACRO },
 {"fsq",        0, INSN_CLASS_Q,   "T,q(s)",    MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE },
 {"fsq",        0, INSN_CLASS_Q,   "T,A,s",     0, (int) M_Sx_FSx, match_rs1_nonzero, INSN_MACRO },
-{"fmv.q",      0, INSN_CLASS_Q_INX,   "D,U",       MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS },
-{"fneg.q",     0, INSN_CLASS_Q_INX,   "D,U",       MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS },
-{"fabs.q",     0, INSN_CLASS_Q_INX,   "D,U",       MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS },
-{"fsgnj.q",    0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 },
-{"fsgnjn.q",   0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 },
-{"fsgnjx.q",   0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 },
-{"fadd.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 },
-{"fsub.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 },
-{"fmul.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 },
-{"fdiv.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 },
-{"fsqrt.q",    0, INSN_CLASS_Q_INX,   "D,Sm",      MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 },
-{"fmin.q",     0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 },
-{"fmax.q",     0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 },
-{"fmadd.q",    0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 },
-{"fnmadd.q",   0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 },
-{"fmsub.q",    0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 },
-{"fnmsub.q",   0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 },
-{"fcvt.w.q",   0, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 },
-{"fcvt.wu.q",  0, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 },
-{"fcvt.q.w",   0, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 },
-{"fcvt.q.wu",  0, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 },
-{"fcvt.q.s",   0, INSN_CLASS_Q_INX,   "D,S",       MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 },
-{"fcvt.q.d",   0, INSN_CLASS_Q_INX,   "D,S",       MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 },
-{"fcvt.s.q",   0, INSN_CLASS_Q_INX,   "D,Sm",      MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 },
-{"fcvt.d.q",   0, INSN_CLASS_Q_INX,   "D,Sm",      MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 },
-{"fclass.q",   0, INSN_CLASS_Q_INX,   "d,S",       MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 },
-{"feq.q",      0, INSN_CLASS_Q_INX,   "d,S,T",     MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 },
-{"flt.q",      0, INSN_CLASS_Q_INX,   "d,S,T",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
-{"fle.q",      0, INSN_CLASS_Q_INX,   "d,S,T",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
-{"fgt.q",      0, INSN_CLASS_Q_INX,   "d,T,S",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_ALIAS },
-{"fge.q",      0, INSN_CLASS_Q_INX,   "d,T,S",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_ALIAS },
-{"fcvt.l.q",  64, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 },
-{"fcvt.lu.q", 64, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 },
-{"fcvt.q.l",  64, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
-{"fcvt.q.lu", 64, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 },
+{"fmv.q",      0, INSN_CLASS_Q_INX,   "D,U",       MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_RV64_EVEN_DU },
+{"fneg.q",     0, INSN_CLASS_Q_INX,   "D,U",       MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_RV64_EVEN_DU },
+{"fabs.q",     0, INSN_CLASS_Q_INX,   "D,U",       MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_RV64_EVEN_DU },
+{"fsgnj.q",    0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, INSN_RV64_EVEN_DST },
+{"fsgnjn.q",   0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, INSN_RV64_EVEN_DST },
+{"fsgnjx.q",   0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, INSN_RV64_EVEN_DST },
+{"fadd.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FADD_Q, MASK_FADD_Q, match_opcode, INSN_RV64_EVEN_DST },
+{"fsub.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, INSN_RV64_EVEN_DST },
+{"fmul.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, INSN_RV64_EVEN_DST },
+{"fdiv.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, INSN_RV64_EVEN_DST },
+{"fsqrt.q",    0, INSN_CLASS_Q_INX,   "D,Sm",      MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, INSN_RV64_EVEN_DS },
+{"fmin.q",     0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, INSN_RV64_EVEN_DST },
+{"fmax.q",     0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, INSN_RV64_EVEN_DST },
+{"fmadd.q",    0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, INSN_RV64_EVEN_DSTR },
+{"fnmadd.q",   0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, INSN_RV64_EVEN_DSTR },
+{"fmsub.q",    0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, INSN_RV64_EVEN_DSTR },
+{"fnmsub.q",   0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, INSN_RV64_EVEN_DSTR },
+{"fcvt.w.q",   0, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, INSN_RV64_EVEN_S },
+{"fcvt.wu.q",  0, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, INSN_RV64_EVEN_S },
+{"fcvt.q.w",   0, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, INSN_RV64_EVEN_D },
+{"fcvt.q.wu",  0, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, INSN_RV64_EVEN_D },
+{"fcvt.q.s",   0, INSN_CLASS_Q_INX,   "D,S",       MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, INSN_RV64_EVEN_D },
+{"fcvt.q.d",   0, INSN_CLASS_Q_INX,   "D,S",       MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, INSN_RV64_EVEN_D|INSN_RV32_EVEN_S },
+{"fcvt.s.q",   0, INSN_CLASS_Q_INX,   "D,Sm",      MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, INSN_RV64_EVEN_S },
+{"fcvt.d.q",   0, INSN_CLASS_Q_INX,   "D,Sm",      MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, INSN_RV32_EVEN_D|INSN_RV64_EVEN_S },
+{"fclass.q",   0, INSN_CLASS_Q_INX,   "d,S",       MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, INSN_RV64_EVEN_S },
+{"feq.q",      0, INSN_CLASS_Q_INX,   "d,S,T",     MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, INSN_RV64_EVEN_ST },
+{"flt.q",      0, INSN_CLASS_Q_INX,   "d,S,T",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_RV64_EVEN_ST },
+{"fle.q",      0, INSN_CLASS_Q_INX,   "d,S,T",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_RV64_EVEN_ST },
+{"fgt.q",      0, INSN_CLASS_Q_INX,   "d,T,S",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_ALIAS|INSN_RV64_EVEN_ST },
+{"fge.q",      0, INSN_CLASS_Q_INX,   "d,T,S",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_ALIAS|INSN_RV64_EVEN_ST },
+{"fcvt.l.q",  64, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, INSN_RV64_EVEN_S },
+{"fcvt.lu.q", 64, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, INSN_RV64_EVEN_S },
+{"fcvt.q.l",  64, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, INSN_RV64_EVEN_D },
+{"fcvt.q.lu", 64, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, INSN_RV64_EVEN_D },
 
 /* Compressed instructions.  */
 {"c.unimp",    0, INSN_CLASS_ZCA,   "",          0, 0xffffU,  match_opcode, 0 },


From jbeulich@suse.com  Fri Jun  5 09:33:30 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 5 Jun 2026 11:33:30 +0200
Subject: [PATCH 0/2] x86: optimize XCHG and XADD for same-register forms
Message-ID: <a1d0420a-9f46-4a7e-a6a9-f71cd7ea3e71@suse.com>

1: optimize XCHG to MOV for same-register forms
2: optimize XADD to ADD for same-register forms

Jan

From jbeulich@suse.com  Fri Jun  5 09:34:27 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 5 Jun 2026 11:34:27 +0200
Subject: [PATCH 1/2] x86: optimize XCHG to MOV for same-register forms
In-Reply-To: <a1d0420a-9f46-4a7e-a6a9-f71cd7ea3e71@suse.com>
References: <a1d0420a-9f46-4a7e-a6a9-f71cd7ea3e71@suse.com>
Message-ID: <1ef40cfc-55eb-4dfa-a2db-e8f2d6d3be03@suse.com>

MOV requires far less execution resources.
---
Should we go further and optimize to NOP (unless of course it's a 32-bit
insn in 64-bit mode)? If so, obviously we'd then want to do this also for
MOV itself.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -5176,6 +5176,17 @@ optimize_encoding (void)
       i.seg[0] = NULL;
     }
 
+  if (!optimize_for_space
+      && i.tm.mnem_off == MN_xchg
+      && i.reg_operands == 2
+      && i.op[0].regs == i.op[1].regs)
+    {
+      /* Optimize: -O:
+	   xchg %rN, %rN     -> mov %rN, %rN
+       */
+      i.tm.base_opcode = pp.dir_encoding == dir_encoding_load ? 0x8a : 0x88;
+    }
+
   if (((i.tm.opcode_space == SPACE_0F
         && (i.tm.base_opcode | 1) == 0xbf
         && (i.types[0].bitfield.byte
--- a/gas/testsuite/gas/i386/optimize-2.d
+++ b/gas/testsuite/gas/i386/optimize-2.d
@@ -24,6 +24,9 @@ Disassembly of section .text:
  +[a-f0-9]+:	09 f6                	or     %esi,%esi
  +[a-f0-9]+:	87 0a                	xchg   %ecx,\(%edx\)
  +[a-f0-9]+:	87 11                	xchg   %edx,\(%ecx\)
+ +[a-f0-9]+:	86 c9                	xchg   %cl,%cl
+ +[a-f0-9]+:	66 87 d2             	xchg   %dx,%dx
+ +[a-f0-9]+:	87 ff                	xchg   %edi,%edi
  +[a-f0-9]+:	66 98                	cbtw
  +[a-f0-9]+:	66 98                	cbtw
  +[a-f0-9]+:	98                   	cwtl
--- a/gas/testsuite/gas/i386/optimize-2.s
+++ b/gas/testsuite/gas/i386/optimize-2.s
@@ -22,6 +22,10 @@ _start:
 	lock xchg %ecx, (%edx)
 	lock xchg (%ecx), %edx
 
+	xchg	%cl, %cl
+	{load} xchg %dx, %dx
+	xchg	%edi, %edi
+
 	movsb	%al, %ax
 	movsbw	%al, %ax
 
--- a/gas/testsuite/gas/i386/optimize-2b.d
+++ b/gas/testsuite/gas/i386/optimize-2b.d
@@ -25,6 +25,9 @@ Disassembly of section .text:
  +[a-f0-9]+:	85 f6                	test   %esi,%esi
  +[a-f0-9]+:	87 0a                	xchg   %ecx,\(%edx\)
  +[a-f0-9]+:	87 11                	xchg   %edx,\(%ecx\)
+ +[a-f0-9]+:	88 c9                	mov    %cl,%cl
+ +[a-f0-9]+:	66 8b d2             	mov    %dx,%dx
+ +[a-f0-9]+:	89 ff                	mov    %edi,%edi
  +[a-f0-9]+:	66 98                	cbtw
  +[a-f0-9]+:	66 98                	cbtw
  +[a-f0-9]+:	98                   	cwtl
--- a/gas/testsuite/gas/i386/x86-64-optimize-3.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-3.d
@@ -80,6 +80,10 @@ Disassembly of section .text:
  +[a-f0-9]+:	66 09 f6             	or     %si,%si
  +[a-f0-9]+:	09 ff                	or     %edi,%edi
  +[a-f0-9]+:	4d 09 c0             	or     %r8,%r8
+ +[a-f0-9]+:	d5 50 86 c9          	xchg   %r17b,%r17b
+ +[a-f0-9]+:	66 45 87 c0          	xchg   %r8w,%r8w
+ +[a-f0-9]+:	87 c0                	xchg   %eax,%eax
+ +[a-f0-9]+:	4d 87 ff             	xchg   %r15,%r15
  +[a-f0-9]+:	66 98                	cbtw
  +[a-f0-9]+:	66 98                	cbtw
  +[a-f0-9]+:	98                   	cwtl
--- a/gas/testsuite/gas/i386/x86-64-optimize-3.s
+++ b/gas/testsuite/gas/i386/x86-64-optimize-3.s
@@ -39,6 +39,11 @@ _start:
 	or	%edi, %edi
 	or	%r8, %r8
 
+	xchg	%r17b, %r17b
+	{load} xchg %r8w, %r8w
+	xchg	%eax, %eax
+	xchg	%r15, %r15
+
 	movsb	%al, %ax
 	movsbw	%al, %ax
 
--- a/gas/testsuite/gas/i386/x86-64-optimize-3b.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-3b.d
@@ -81,6 +81,10 @@ Disassembly of section .text:
  +[a-f0-9]+:	66 85 f6             	test   %si,%si
  +[a-f0-9]+:	09 ff                	or     %edi,%edi
  +[a-f0-9]+:	4d 85 c0             	test   %r8,%r8
+ +[a-f0-9]+:	d5 50 88 c9          	mov    %r17b,%r17b
+ +[a-f0-9]+:	66 45 8b c0          	mov    %r8w,%r8w
+ +[a-f0-9]+:	89 c0                	mov    %eax,%eax
+ +[a-f0-9]+:	4d 89 ff             	mov    %r15,%r15
  +[a-f0-9]+:	66 98                	cbtw
  +[a-f0-9]+:	66 98                	cbtw
  +[a-f0-9]+:	98                   	cwtl
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -269,7 +269,7 @@ popa, 0x61, i186&No64, ImplicitStackOp|D
 
 // In the 64bit code, xchg rax, rax is reused for new nop instruction.
 xchg, 0x90, 0, D|C|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64, Acc|Word|Dword|Qword }
-xchg, 0x86, 0, D|W|C|CheckOperandSize|Modrm|No_sSuf|HLEPrefixAny, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+xchg, 0x86, 0, D|W|C|CheckOperandSize|Modrm|No_sSuf|HLEPrefixAny|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 
 // In/out from ports.
 in, 0xe4, 0, W|No_sSuf|No_qSuf, { Imm8, Acc|Byte|Word|Dword }


From jbeulich@suse.com  Fri Jun  5 09:34:57 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 5 Jun 2026 11:34:57 +0200
Subject: [PATCH 2/2] x86: optimize XADD to ADD for same-register forms
In-Reply-To: <a1d0420a-9f46-4a7e-a6a9-f71cd7ea3e71@suse.com>
References: <a1d0420a-9f46-4a7e-a6a9-f71cd7ea3e71@suse.com>
Message-ID: <4c948ec5-cbec-4841-9849-bb5a0916ccf6@suse.com>

ADD requires less execution resources and is shorter to encode.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -5187,6 +5187,17 @@ optimize_encoding (void)
       i.tm.base_opcode = pp.dir_encoding == dir_encoding_load ? 0x8a : 0x88;
     }
 
+  if (i.tm.mnem_off == MN_xadd
+      && i.reg_operands == 2
+      && i.op[0].regs == i.op[1].regs)
+    {
+      /* Optimize: -O:
+	   xadd %rN, %rN     -> add %rN, %rN
+       */
+      i.tm.opcode_space = SPACE_BASE;
+      i.tm.base_opcode = 0x00;
+    }
+
   if (((i.tm.opcode_space == SPACE_0F
         && (i.tm.base_opcode | 1) == 0xbf
         && (i.types[0].bitfield.byte
--- a/gas/testsuite/gas/i386/optimize-2.d
+++ b/gas/testsuite/gas/i386/optimize-2.d
@@ -48,6 +48,9 @@ Disassembly of section .text:
  +[a-f0-9]+:	66 d1 e2             	shl    \$1,%dx
  +[a-f0-9]+:	d1 e2                	shl    \$1,%edx
  +[a-f0-9]+:	d1 e2                	shl    \$1,%edx
+ +[a-f0-9]+:	00 c9                	add    %cl,%cl
+ +[a-f0-9]+:	66 01 d2             	add    %dx,%dx
+ +[a-f0-9]+:	01 ff                	add    %edi,%edi
  +[a-f0-9]+:	c5 f1 55 e9          	vandnpd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	c5 f9 6f d1          	vmovdqa %xmm1,%xmm2
  +[a-f0-9]+:	c5 f9 6f d1          	vmovdqa %xmm1,%xmm2
--- a/gas/testsuite/gas/i386/optimize-2.s
+++ b/gas/testsuite/gas/i386/optimize-2.s
@@ -59,6 +59,10 @@ _start:
 	sal	$1, %edx
 	sal	%edx
 
+	xadd	%cl, %cl
+	xadd	%dx, %dx
+	xadd	%edi, %edi
+
 	vandnpd	%zmm1, %zmm1, %zmm5
 
 	vmovdqa32	%xmm1, %xmm2
--- a/gas/testsuite/gas/i386/optimize-2b.d
+++ b/gas/testsuite/gas/i386/optimize-2b.d
@@ -49,6 +49,9 @@ Disassembly of section .text:
  +[a-f0-9]+:	66 01 d2             	add    %dx,%dx
  +[a-f0-9]+:	01 d2                	add    %edx,%edx
  +[a-f0-9]+:	01 d2                	add    %edx,%edx
+ +[a-f0-9]+:	00 c9                	add    %cl,%cl
+ +[a-f0-9]+:	66 01 d2             	add    %dx,%dx
+ +[a-f0-9]+:	01 ff                	add    %edi,%edi
  +[a-f0-9]+:	c5 f1 55 e9          	vandnpd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	c5 f9 6f d1          	vmovdqa %xmm1,%xmm2
  +[a-f0-9]+:	c5 f9 6f d1          	vmovdqa %xmm1,%xmm2
--- a/gas/testsuite/gas/i386/x86-64-optimize-3.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-3.d
@@ -94,6 +94,10 @@ Disassembly of section .text:
  +[a-f0-9]+:	66 98                	cbtw
  +[a-f0-9]+:	98                   	cwtl
  +[a-f0-9]+:	48 98                	cltq
+ +[a-f0-9]+:	d5 50 00 c9          	add    %r17b,%r17b
+ +[a-f0-9]+:	66 45 01 c0          	add    %r8w,%r8w
+ +[a-f0-9]+:	01 c0                	add    %eax,%eax
+ +[a-f0-9]+:	4d 01 ff             	add    %r15,%r15
  +[a-f0-9]+:	c5 f1 55 e9          	vandnpd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	c5 f9 6f d1          	vmovdqa %xmm1,%xmm2
  +[a-f0-9]+:	c5 f9 6f d1          	vmovdqa %xmm1,%xmm2
--- a/gas/testsuite/gas/i386/x86-64-optimize-3.s
+++ b/gas/testsuite/gas/i386/x86-64-optimize-3.s
@@ -60,6 +60,11 @@ _start:
 	movsx	rax, eax
 	.att_syntax prefix
 
+	xadd	%r17b, %r17b
+	xadd	%r8w, %r8w
+	xadd	%eax, %eax
+	xadd	%r15, %r15
+
 	vandnpd	%zmm1, %zmm1, %zmm5
 
 	vmovdqa32	%xmm1, %xmm2
--- a/gas/testsuite/gas/i386/x86-64-optimize-3b.d
+++ b/gas/testsuite/gas/i386/x86-64-optimize-3b.d
@@ -95,6 +95,10 @@ Disassembly of section .text:
  +[a-f0-9]+:	66 98                	cbtw
  +[a-f0-9]+:	98                   	cwtl
  +[a-f0-9]+:	48 98                	cltq
+ +[a-f0-9]+:	d5 50 00 c9          	add    %r17b,%r17b
+ +[a-f0-9]+:	66 45 01 c0          	add    %r8w,%r8w
+ +[a-f0-9]+:	01 c0                	add    %eax,%eax
+ +[a-f0-9]+:	4d 01 ff             	add    %r15,%r15
  +[a-f0-9]+:	c5 f1 55 e9          	vandnpd %xmm1,%xmm1,%xmm5
  +[a-f0-9]+:	c5 f9 6f d1          	vmovdqa %xmm1,%xmm2
  +[a-f0-9]+:	c5 f9 6f d1          	vmovdqa %xmm1,%xmm2
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -957,7 +957,7 @@ rex.wrxb, 0x4f, x64, NoSuf|IsPrefix, {}
 
 // 486 extensions (BSWAP moved elsewhere).
 
-xadd, 0xfc0, i486, W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
+xadd, 0xfc0, i486, W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock|Optimize, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 cmpxchg, 0xfb0, i486, W|CheckOperandSize|Modrm|No_sSuf|HLEPrefixLock, { Reg8|Reg16|Reg32|Reg64, Reg8|Reg16|Reg32|Reg64|Unspecified|BaseIndex }
 invd, 0xf08, i486, NoSuf, {}
 wbinvd, 0xf09, i486, NoSuf, {}


From xry111@xry111.site  Fri Jun  5 09:56:43 2026
From: xry111@xry111.site (Xi Ruoyao)
Date: Fri, 05 Jun 2026 17:56:43 +0800
Subject: [PATCH v1] LoongArch: Fix relaxation alignment with ld -r (PR
 33236)
In-Reply-To: <20260529074340.943231-1-mengqinggang@loongson.cn>
References: <20260529074340.943231-1-mengqinggang@loongson.cn>
Message-ID: <f81eec0a90a521f390848bf8104043d52ba15afb.camel@xry111.site>

On Fri, 2026-05-29 at 15:43 +0800, mengqinggang wrote:
> +????? /* Match if (r_symndx < symtab_hdr->sh_info) branch in
> +	 loongarch_elf_relocate_section to avoid find link failed.? */
> +????? symtab_hdr->sh_info = 1;
> +//????? symtab_hdr->sh_size = sizeof (Elf_Internal_Sym);
> +//????? symtab_hdr->sh_entsize = sizeof (Elf_Internal_Sym);
> +//????? symtab_hdr->sh_type = SHT_SYMTAB;
> +//????? symtab_hdr->sh_addralign = (bfd_vma) 1 << bed->s->log_file_align;

Hmm, just remove them?

> +????? symtab_hdr->contents = (unsigned char *) sym;

I'll test if the change will break Linux kernel module this weekend.

-- 
Xi Ruoyao <xry111@xry111.site>

From jbeulich@suse.com  Fri Jun  5 11:52:59 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 5 Jun 2026 13:52:59 +0200
Subject: [PATCH] x86-64: Intel64 adjustments for conditional jumps
Message-ID: <1e5f7d97-d50f-4a09-83b8-1285a5587d91@suse.com>

Just like for unconditional direct JMP (and CALL), AMD and Intel differ
in their handling. Mirror JMP handling to Jcc (thus also better resolving
ambiguities outside of 64-bit mode).
---
It's really not clear why the original change was done for JMP (and CALL),
but not Jcc.

Just like the earlier change (for JMP, but not CALL), this results in the
disassembler, in -Msuffix mode, emitting insn forms the assembler wouldn't
accept.

--- a/gas/testsuite/gas/i386/opcode-suffix.d
+++ b/gas/testsuite/gas/i386/opcode-suffix.d
@@ -305,22 +305,22 @@ Disassembly of section .text:
  *[0-9a-f]+:	0f 77[ 	]+emms
  *[0-9a-f]+:	0f 7e 90 90 90 90 90[ 	]+movd[ 	]+%mm2,-0x6f6f6f70\(%eax\)
  *[0-9a-f]+:	0f 7f 90 90 90 90 90[ 	]+movq[ 	]+%mm2,-0x6f6f6f70\(%eax\)
- *[0-9a-f]+:	0f 80 90 90 90 90[ 	]+jo[ 	]+909094e2 <foo\+0x909094e2>
- *[0-9a-f]+:	0f 81 90 90 90 90[ 	]+jno[ 	]+909094e8 <foo\+0x909094e8>
- *[0-9a-f]+:	0f 82 90 90 90 90[ 	]+jb[ 	]+909094ee <foo\+0x909094ee>
- *[0-9a-f]+:	0f 83 90 90 90 90[ 	]+jae[ 	]+909094f4 <foo\+0x909094f4>
- *[0-9a-f]+:	0f 84 90 90 90 90[ 	]+je[ 	]+909094fa <foo\+0x909094fa>
- *[0-9a-f]+:	0f 85 90 90 90 90[ 	]+jne[ 	]+90909500 <foo\+0x90909500>
- *[0-9a-f]+:	0f 86 90 90 90 90[ 	]+jbe[ 	]+90909506 <foo\+0x90909506>
- *[0-9a-f]+:	0f 87 90 90 90 90[ 	]+ja[ 	]+9090950c <foo\+0x9090950c>
- *[0-9a-f]+:	0f 88 90 90 90 90[ 	]+js[ 	]+90909512 <foo\+0x90909512>
- *[0-9a-f]+:	0f 89 90 90 90 90[ 	]+jns[ 	]+90909518 <foo\+0x90909518>
- *[0-9a-f]+:	0f 8a 90 90 90 90[ 	]+jp[ 	]+9090951e <foo\+0x9090951e>
- *[0-9a-f]+:	0f 8b 90 90 90 90[ 	]+jnp[ 	]+90909524 <foo\+0x90909524>
- *[0-9a-f]+:	0f 8c 90 90 90 90[ 	]+jl[ 	]+9090952a <foo\+0x9090952a>
- *[0-9a-f]+:	0f 8d 90 90 90 90[ 	]+jge[ 	]+90909530 <foo\+0x90909530>
- *[0-9a-f]+:	0f 8e 90 90 90 90[ 	]+jle[ 	]+90909536 <foo\+0x90909536>
- *[0-9a-f]+:	0f 8f 90 90 90 90[ 	]+jg[ 	]+9090953c <foo\+0x9090953c>
+ *[0-9a-f]+:	0f 80 90 90 90 90[ 	]+jol[ 	]+909094e2 <foo\+0x909094e2>
+ *[0-9a-f]+:	0f 81 90 90 90 90[ 	]+jnol[ 	]+909094e8 <foo\+0x909094e8>
+ *[0-9a-f]+:	0f 82 90 90 90 90[ 	]+jbl[ 	]+909094ee <foo\+0x909094ee>
+ *[0-9a-f]+:	0f 83 90 90 90 90[ 	]+jael[ 	]+909094f4 <foo\+0x909094f4>
+ *[0-9a-f]+:	0f 84 90 90 90 90[ 	]+jel[ 	]+909094fa <foo\+0x909094fa>
+ *[0-9a-f]+:	0f 85 90 90 90 90[ 	]+jnel[ 	]+90909500 <foo\+0x90909500>
+ *[0-9a-f]+:	0f 86 90 90 90 90[ 	]+jbel[ 	]+90909506 <foo\+0x90909506>
+ *[0-9a-f]+:	0f 87 90 90 90 90[ 	]+jal[ 	]+9090950c <foo\+0x9090950c>
+ *[0-9a-f]+:	0f 88 90 90 90 90[ 	]+jsl[ 	]+90909512 <foo\+0x90909512>
+ *[0-9a-f]+:	0f 89 90 90 90 90[ 	]+jnsl[ 	]+90909518 <foo\+0x90909518>
+ *[0-9a-f]+:	0f 8a 90 90 90 90[ 	]+jpl[ 	]+9090951e <foo\+0x9090951e>
+ *[0-9a-f]+:	0f 8b 90 90 90 90[ 	]+jnpl[ 	]+90909524 <foo\+0x90909524>
+ *[0-9a-f]+:	0f 8c 90 90 90 90[ 	]+jll[ 	]+9090952a <foo\+0x9090952a>
+ *[0-9a-f]+:	0f 8d 90 90 90 90[ 	]+jgel[ 	]+90909530 <foo\+0x90909530>
+ *[0-9a-f]+:	0f 8e 90 90 90 90[ 	]+jlel[ 	]+90909536 <foo\+0x90909536>
+ *[0-9a-f]+:	0f 8f 90 90 90 90[ 	]+jgl[ 	]+9090953c <foo\+0x9090953c>
  *[0-9a-f]+:	0f 90 80 90 90 90 90[ 	]+seto[ 	]+-0x6f6f6f70\(%eax\)
  *[0-9a-f]+:	0f 91 80 90 90 90 90[ 	]+setno[ 	]+-0x6f6f6f70\(%eax\)
  *[0-9a-f]+:	0f 92 80 90 90 90 90[ 	]+setb[ 	]+-0x6f6f6f70\(%eax\)
--- a/gas/testsuite/gas/i386/x86-64-branch-2.d
+++ b/gas/testsuite/gas/i386/x86-64-branch-2.d
@@ -17,4 +17,6 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	66 48 e8 00 00 00 00 	data16 rex\.W call 18 <bar\+0xd>	14: R_X86_64_PLT32	foo-0x4
 [ 	]*[a-f0-9]+:	66 c3                	retw
 [ 	]*[a-f0-9]+:	66 c2 08 00          	retw   \$0x8
+[ 	]*[a-f0-9]+:	66 0f 84 00 00       	jew    23 <bar\+0x18>	21: R_X86_64_PC16	foo-0x2
+[ 	]*[a-f0-9]+:	66 48 0f 85 00 00 00 00 	data16 rex\.W jne 2b <bar\+0x20>	27: R_X86_64_PLT32	foo-0x4
 #pass
--- a/gas/testsuite/gas/i386/x86-64-branch-2.s
+++ b/gas/testsuite/gas/i386/x86-64-branch-2.s
@@ -10,3 +10,6 @@ bar:
 
 	retw
 	retw $8
+
+	data16 je foo
+	data16 rex.w jne foo
--- a/gas/testsuite/gas/i386/x86-64-branch-3.d
+++ b/gas/testsuite/gas/i386/x86-64-branch-3.d
@@ -19,4 +19,6 @@ Disassembly of section .text:
 [ 	]*[a-f0-9]+:	66 48 c7 f8 00 00 00 00 	data16 rex\.W xbegin 29 <bar\+0x1c>	25: R_X86_64_PLT32	foo-0x4
 [ 	]*[a-f0-9]+:	48 ff 18             	lcallq \*\(%rax\)
 [ 	]*[a-f0-9]+:	48 ff 29             	ljmpq  \*\(%rcx\)
+[ 	]*[a-f0-9]+:	66 0f 84 00 00 00 00 	data16 je 36 <bar\+0x29>	32: R_X86_64_PLT32	foo-0x4
+[ 	]*[a-f0-9]+:	66 48 0f 85 00 00 00 00 	data16 rex\.W jne 3e <bar\+0x31>	3a: R_X86_64_PLT32	foo-0x4
 #pass
--- a/gas/testsuite/gas/i386/x86-64-branch-3.s
+++ b/gas/testsuite/gas/i386/x86-64-branch-3.s
@@ -13,3 +13,6 @@ bar:
 
 	lcallq *(%rax)
 	ljmpq *(%rcx)
+
+	data16 je foo
+	data16 rex.w jne foo
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -2405,23 +2405,23 @@ static const struct dis386 dis386_twobyt
   { PREFIX_TABLE (PREFIX_0F7E) },
   { PREFIX_TABLE (PREFIX_0F7F) },
   /* 80 */
-  { "joH",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
-  { "jnoH",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
-  { "jbH",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
-  { "jaeH",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
-  { "jeH",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
-  { "jneH",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
-  { "jbeH",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
-  { "jaH",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+  { "jo@H",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+  { "jno@H",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+  { "jb@H",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+  { "jae@H",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+  { "je@H",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+  { "jne@H",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+  { "jbe@H",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+  { "ja@H",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
   /* 88 */
-  { "jsH",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
-  { "jnsH",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
-  { "jpH",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
-  { "jnpH",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
-  { "jlH",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
-  { "jgeH",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
-  { "jleH",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
-  { "jgH",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+  { "js@H",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+  { "jns@H",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+  { "jp@H",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+  { "jnp@H",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+  { "jl@H",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+  { "jge@H",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+  { "jle@H",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
+  { "jg@H",		{ Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
   /* 90 */
   { "seto",		{ Eb }, 0 },
   { "setno",		{ Eb }, 0 },
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -537,7 +537,8 @@ leave, 0xc9, x64, ImplicitStackOp|Defaul
          s:8, ns:9, p:a, pe:a, np:b, po:b, l:c, nge:c, nl:d, ge:d, le:e, ng:e, nle:f, g:f>
 
 // Conditional jumps.
-j<cc>, 0x7<cc:opc>, 0, Jump|NoSuf|BNDPrefixOk, { Disp8|Disp16|Disp32 }
+j<cc>, 0x7<cc:opc>, 0, Amd64|Jump|NoSuf|BNDPrefixOk, { Disp8|Disp16|Disp32 }
+j<cc>, 0x7<cc:opc>, x64, Intel64|Jump|NoSuf|BNDPrefixOk, { Disp8|Disp32 }
 
 // jcxz vs. jecxz is chosen on the basis of the address size prefix.
 jcxz, 0xe3, No64, JumpByte|Size16|NoSuf, { Disp8 }

From luis.silva@globalfoundries.com  Fri Jun  5 15:54:05 2026
From: luis.silva@globalfoundries.com (Silva, Luis)
Date: Fri, 5 Jun 2026 15:54:05 +0000
Subject: [PATCH 1/2] RISC-V: Add ARC-V APEX assembler support
In-Reply-To: <38e416b6-76b6-4c26-8f8b-25c4def56d8a@suse.com>
References: <20260525133052.1885254-1-luiss@synopsys.com>
 <20260525133052.1885254-2-luiss@synopsys.com>
 <38e416b6-76b6-4c26-8f8b-25c4def56d8a@suse.com>
Message-ID: <DB9PR10MB7217F1488A2B7AEAB4C6265289112@DB9PR10MB7217.EURPRD10.PROD.OUTLOOK.COM>

>> --- a/gas/doc/c-riscv.texi
>> +++ b/gas/doc/c-riscv.texi
>> @@ -265,6 +265,59 @@ Floating point constructors for the bfloat16 type, example usage:
>>       .bfloat16 0b:ffc1
>>  @end smallexample
>>
>> +@cindex @code{.extInstruction} directive, RISC-V

> To me this directive is too long. .extinsn perhaps, or even one of .einsn or
> .xinsn? Otoh ...

>> +@cindex ARC-V APEX instructions
>> +@item .extInstruction @var{name}, @var{opcode}, @var{attrs}@dots{}
>> +Define a dynamic APEX instruction that uses the Custom-0 encoding space.

> ... the ARC-V / APEX aspect isn't encoded at all in the directive name. Some
> other vendor could come up with some different scheme. So maybe .apexinsn?
> Or one of the earlier suggested names, but with a first operand required to
> be "apex" for this variant?

The existing ARC support in binutils already has a comparable mechanism in place
that serves the same purpose, so this directive name isn?t new.

>> +The @var{name} is the mnemonic used in subsequent assembly.  The
>> +@var{opcode} is the function code (sub-opcode) whose valid range depends
>> +on the format.  The @var{attrs} are a comma-separated list drawn from:
>> +
>> +@table @code
>> +@item XD
>> +XD format (3 register operands, 8-bit sub-opcode, range 0--255).
>> +@item XS
>> +XS format (2 registers + 8-bit signed immediate, 6-bit sub-opcode,
>> +range 0--63).
>> +@item XI
>> +XI format (1 register + 12-bit signed immediate, 5-bit sub-opcode,
>> +range 0--31).
>> +@item XC
>> +XC format (1 register acting as both destination and source +
>> +12-bit signed immediate, 5-bit sub-opcode, range 0--31).

> What's the difference between XI and XC? The description says "compressed"
> for the latter, but the encoding space needed (without the major opcode)
> is 5 + 12 + 5 = 22, i.e. way beyond 16 bits. That's really no different
> from XI. What am I missing?

Indeed, "compressed" was the wrong term here; XC is not a 16-bit compressed
instruction.

The difference is that XI has no source register, while XC uses the destination
register as an implicit source register.  Therefore XI has 2 operands
(`rd`, `imm`), whereas XC behaves as 3 operands (`rd/rs1`, `imm`).

>> +@item void
>> +Omit the destination register from the operand list.
>> +@item no_src0
>> +Omit the first source register from the operand list.
>> +@item no_src1
>> +Omit the second source register (or immediate) from the operand list.
>> +@end table
>> +
>> +Exactly one of @code{XD}, @code{XS}, @code{XI}, or @code{XC} must be
>> +specified.  @code{XS} and @code{XC} may be combined;

> This contradicts the first sentence. That earlier sentence would better be
> written to avoid such a contradiction, e.g. "With one exception, eaxctly
> one ...".

Good point. The current wording is contradictory: "Exactly one" conflicts with
the later statement that XS and XC may be combined.  I'll rephrase it to make the
exception explicit.

>> in that case the
>> +assembler uses the XS encoding when the destination and source registers
>> +differ (and the immediate fits in 8 bits), and the XC encoding when the
>> +registers are the same or the immediate requires 12 bits.

> This can't be correct: XC, as per what's said elsewhere, requires RD == RS1,
> and hence the form can't be used when the immediate requires 12 bits but the
> two registers don't match.

You're right, my wording is incorrect.

XC is only valid when RD == RS1.  The intention was to describe selection between
XS and XC based on both register equality and immediate range, but the current
sentence incorrectly suggests XC could be chosen based solely on immediate size.

I'll rephrase this to make the register constraint explicit and ensure XC is
only used when RD == RS1.

>> +Examples:
>> +
>> +@smallexample
>> +     .extInstruction myalu, 1, XD
>> +     myalu a0, a1, a2
>> +
>> +     .extInstruction myimm, 5, XS
>> +     myimm a0, a1, 42
>> +
>> +     .extInstruction myflex, 3, XS, XC
>> +     myflex a0, a1, 10
>> +     myflex a0, a0, 1000
>> +@end smallexample
>> +
>> +The assembler emits metadata about each @code{.extInstruction} into
>> +ELF sections named @code{.riscvapex.@var{fmt}.@var{custom0}.@var{opcode}},
>> +which the disassembler reads to reconstruct instruction names and
>> +operand formats.

> So these sections exist solely for the disassembler's convenience? I.e.
> them getting stripped (or them not being understood) isn't a functional
> issue?

Yes, the metadata is for disassembler/debugger use.  Without it,
execution is unaffected; only recognition of the dynamically defined
instructions is lost.

Regards,
Luis
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From builder@sourceware.org  Sat Jun  6 00:47:00 2026
From: builder@sourceware.org (builder@sourceware.org)
Date: Sat, 06 Jun 2026 00:47:00 +0000
Subject: =?utf-8?q?=E2=98=BA_Buildbot_=28Sourceware=29=3A_binutils-gdb_-_build_successful_=28master=29?=
Message-ID: <20260606004701.025034BA2E06@sourceware.org>

A restored build has been detected on builder binutils-fedora-ppc64le while building binutils-gdb.

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Revision: f690b305d643b050b90fe75db462d5f7c608476e
Worker: fedora-ppc64le
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From builder@sourceware.org  Sat Jun  6 00:53:39 2026
From: builder@sourceware.org (builder@sourceware.org)
Date: Sat, 06 Jun 2026 00:53:39 +0000
Subject: =?utf-8?q?=E2=98=BA_Buildbot_=28Sourceware=29=3A_binutils-gdb_-_build_successful_=28master=29?=
Message-ID: <20260606005339.35C8C4BA2E06@sourceware.org>

A restored build has been detected on builder binutils-fedora-x86_64 while building binutils-gdb.

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Revision: f690b305d643b050b90fe75db462d5f7c608476e
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From builder@sourceware.org  Sat Jun  6 00:59:26 2026
From: builder@sourceware.org (builder@sourceware.org)
Date: Sat, 06 Jun 2026 00:59:26 +0000
Subject: =?utf-8?q?=E2=98=9D_Buildbot_=28Sourceware=29=3A_binutils-gdb_-_retry_lost_connection_compile_=28retry=29_=28master=29?=
Message-ID: <20260606005926.3AD014BA543C@sourceware.org>

A retry build has been detected on builder binutils-solaris11-sparc while building binutils-gdb.

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Build state: retry lost connection compile (retry)
Revision: f690b305d643b050b90fe75db462d5f7c608476e
Worker: solaris11-sparcv9
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Blamelist: GDB Administrator <gdbadmin@sourceware.org>

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- 4: make ( retry )
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        - cancelled: https://builder.sourceware.org/buildbot/#/builders/365/builds/2/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-sparc while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/365/builds/3

Build state: retry lost connection compile (retry)
Revision: f690b305d643b050b90fe75db462d5f7c608476e
Worker: solaris11-sparcv9
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- 4: make ( retry )
    Logs:
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A cancelled build has been detected on builder binutils-solaris11-sparc while building binutils-gdb.

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Build state: cancelled (no reason) configure (cancelled)
Revision: f690b305d643b050b90fe75db462d5f7c608476e
Worker: solaris11-sparcv9
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        - cancelled: https://builder.sourceware.org/buildbot/#/builders/365/builds/4/steps/3/logs/cancelled


From builder@sourceware.org  Sat Jun  6 01:07:44 2026
From: builder@sourceware.org (builder@sourceware.org)
Date: Sat, 06 Jun 2026 01:07:44 +0000
Subject: =?utf-8?q?=E2=98=BA_Buildbot_=28Sourceware=29=3A_binutils-gdb_-_build_successful_=28master=29?=
Message-ID: <20260606010744.7BD594BA543C@sourceware.org>

A restored build has been detected on builder binutils-debian-amd64 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/68/builds/7734

Build state: build successful
Revision: f690b305d643b050b90fe75db462d5f7c608476e
Worker: sw3bb2
Build Reason: (unknown)
Blamelist: GDB Administrator <gdbadmin@sourceware.org>, Tom Tromey <tromey@adacore.com>, Tom de Vries <tdevries@suse.de>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
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- 2: rm -rf binutils-build ( success )
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- 3: configure ( success )
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- 4: make ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7734/steps/4/logs/stdio
        - warnings (25): https://builder.sourceware.org/buildbot/#/builders/68/builds/7734/steps/4/logs/warnings__25_

- 5: make check ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7734/steps/5/logs/stdio
        - ld.sum: https://builder.sourceware.org/buildbot/#/builders/68/builds/7734/steps/5/logs/ld_sum
        - ld.log: https://builder.sourceware.org/buildbot/#/builders/68/builds/7734/steps/5/logs/ld_log
        - gas.sum: https://builder.sourceware.org/buildbot/#/builders/68/builds/7734/steps/5/logs/gas_sum
        - gas.log: https://builder.sourceware.org/buildbot/#/builders/68/builds/7734/steps/5/logs/gas_log
        - gprof.log: https://builder.sourceware.org/buildbot/#/builders/68/builds/7734/steps/5/logs/gprof_log
        - binutils.sum: https://builder.sourceware.org/buildbot/#/builders/68/builds/7734/steps/5/logs/binutils_sum
        - binutils.log: https://builder.sourceware.org/buildbot/#/builders/68/builds/7734/steps/5/logs/binutils_log
        - libsframe.sum: https://builder.sourceware.org/buildbot/#/builders/68/builds/7734/steps/5/logs/libsframe_sum
        - libsframe.log: https://builder.sourceware.org/buildbot/#/builders/68/builds/7734/steps/5/logs/libsframe_log
        - libctf.sum: https://builder.sourceware.org/buildbot/#/builders/68/builds/7734/steps/5/logs/libctf_sum
        - libctf.log: https://builder.sourceware.org/buildbot/#/builders/68/builds/7734/steps/5/logs/libctf_log
        - warnings (10): https://builder.sourceware.org/buildbot/#/builders/68/builds/7734/steps/5/logs/warnings__10_

- 6: prep ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7734/steps/6/logs/stdio

- 7: collect system versions ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7734/steps/7/logs/stdio

- 8: fetch .bunsen.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7734/steps/8/logs/stdio

- 9: build bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7734/steps/9/logs/stdio

- 10: fetch bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7734/steps/10/logs/stdio

- 11: unpack bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7734/steps/11/logs/stdio

- 12: pass .bunsen.source.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7734/steps/12/logs/stdio

- 13: upload to bunsen ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7734/steps/13/logs/stdio

- 14: clean up ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7734/steps/14/logs/stdio

- 15: rm -rf binutils-build_1 ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7734/steps/15/logs/stdio


From amodra@gmail.com  Sat Jun  6 01:22:06 2026
From: amodra@gmail.com (Alan Modra)
Date: Sat, 6 Jun 2026 10:52:06 +0930
Subject: gas s_comm_internal uninitialised access
Message-ID: <aiN2Pm9k6Qa1WuAk@squeak.grove.modra.org>

After elf_common_parse calls ignore_rest_of_line on some errors,
s_comm_internal calls demand_empty_rest_of_line.  These functions
cannot be both called, as they consume the end_of_stmt char in the
input buffer and the second call then consumes the next line of input,
which may not even be in the input buffer.

	* config/obj-elf.c (elf_common_parse): Don't call
	ignore_rest_of_line here.
	* read.c (ignore_rest_of_line): Expand comment.

diff --git a/gas/config/obj-elf.c b/gas/config/obj-elf.c
index 7b120ff8eeb..09a224147e9 100644
--- a/gas/config/obj-elf.c
+++ b/gas/config/obj-elf.c
@@ -275,7 +275,6 @@ elf_common_parse (int ignore ATTRIBUTE_UNUSED, symbolS *symbolP, addressT size)
 	      *input_line_pointer = '\0';
 	      as_bad (_("bad .common segment %s"), p);
 	      *input_line_pointer = c;
-	      ignore_rest_of_line ();
 	      return NULL;
 	    }
 	  /* ??? Don't ask me why these are always global.  */
diff --git a/gas/read.c b/gas/read.c
index 7a0c73abc5c..5b6a3c115a0 100644
--- a/gas/read.c
+++ b/gas/read.c
@@ -4101,8 +4101,10 @@ demand_empty_rest_of_line (void)
 /* Silently advance to the end of a statement.  Use this after already having
    issued an error about something bad.  Like demand_empty_rest_of_line,
    this function may leave input_line_pointer one after buffer_limit;
-   Don't call it from within expression parsing code in an attempt to
-   silence further errors.  */
+   Don't call it twice, and don't call both ignore_rest_of_line and
+   demand_empty_rest_of_line as that will consume two lines of input.
+   This rule leads to:  Don't call it from within expression parsing
+   code in an attempt to silence further errors.  */
 
 void
 ignore_rest_of_line (void)

-- 
Alan Modra

From builder@sourceware.org  Sat Jun  6 01:30:34 2026
From: builder@sourceware.org (builder@sourceware.org)
Date: Sat, 06 Jun 2026 01:30:34 +0000
Subject: =?utf-8?q?=E2=98=A0_Buildbot_=28Sourceware=29=3A_binutils-gdb_-_failed_configure_=28failure=29_=28master=29?=
Message-ID: <20260606013034.56C984BA2E07@sourceware.org>

A new failure has been detected on builder binutils-debian-amd64 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/68/builds/7733

Build state: failed configure (failure)
Revision: f690b305d643b050b90fe75db462d5f7c608476e
Worker: sw3bb1
Build Reason: (unknown)
Blamelist: GDB Administrator <gdbadmin@sourceware.org>, Tom Tromey <tromey@adacore.com>, Tom de Vries <tdevries@suse.de>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/3/logs/config_log

- 4: make ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/4/logs/stdio
        - warnings (25): https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/4/logs/warnings__25_

- 5: make check ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/5/logs/stdio
        - ld.sum: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/5/logs/ld_sum
        - ld.log: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/5/logs/ld_log
        - gas.sum: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/5/logs/gas_sum
        - gas.log: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/5/logs/gas_log
        - gprof.log: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/5/logs/gprof_log
        - binutils.sum: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/5/logs/binutils_sum
        - binutils.log: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/5/logs/binutils_log
        - libsframe.sum: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/5/logs/libsframe_sum
        - libsframe.log: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/5/logs/libsframe_log
        - libctf.sum: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/5/logs/libctf_sum
        - libctf.log: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/5/logs/libctf_log
        - warnings (10): https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/5/logs/warnings__10_

- 6: prep ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/6/logs/stdio

- 7: collect system versions ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/7/logs/stdio

- 8: fetch .bunsen.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/8/logs/stdio

- 9: build bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/9/logs/stdio

- 10: fetch bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/10/logs/stdio

- 11: unpack bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/11/logs/stdio

- 12: pass .bunsen.source.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/12/logs/stdio

- 13: upload to bunsen ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/13/logs/stdio

- 14: clean up ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/14/logs/stdio

- 15: rm -rf binutils-build_1 ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/15/logs/stdio

- 16: git checkout_1 ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/16/logs/stdio

- 17: rm -rf binutils-build_2 ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/17/logs/stdio

- 18: configure_1 ( failure )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/18/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/68/builds/7733/steps/18/logs/config_log

A new failure has been detected on builder binutils-fedora-x86_64 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/77/builds/7736

Build state: failed configure (failure)
Revision: f690b305d643b050b90fe75db462d5f7c608476e
Worker: sw3bb2
Build Reason: (unknown)
Blamelist: GDB Administrator <gdbadmin@sourceware.org>, Tom Tromey <tromey@adacore.com>, Tom de Vries <tdevries@suse.de>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/3/logs/config_log

- 4: make ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/4/logs/stdio
        - warnings (47): https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/4/logs/warnings__47_

- 5: make check ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/5/logs/stdio
        - ld.sum: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/5/logs/ld_sum
        - ld.log: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/5/logs/ld_log
        - gas.sum: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/5/logs/gas_sum
        - gas.log: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/5/logs/gas_log
        - gprof.log: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/5/logs/gprof_log
        - binutils.sum: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/5/logs/binutils_sum
        - binutils.log: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/5/logs/binutils_log
        - libsframe.sum: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/5/logs/libsframe_sum
        - libsframe.log: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/5/logs/libsframe_log
        - libctf.sum: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/5/logs/libctf_sum
        - libctf.log: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/5/logs/libctf_log
        - warnings (15): https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/5/logs/warnings__15_

- 6: prep ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/6/logs/stdio

- 7: collect system versions ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/7/logs/stdio

- 8: fetch .bunsen.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/8/logs/stdio

- 9: build bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/9/logs/stdio

- 10: fetch bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/10/logs/stdio

- 11: unpack bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/11/logs/stdio

- 12: pass .bunsen.source.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/12/logs/stdio

- 13: upload to bunsen ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/13/logs/stdio

- 14: clean up ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/14/logs/stdio

- 15: rm -rf binutils-build_1 ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/15/logs/stdio

- 16: git checkout_1 ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/16/logs/stdio

- 17: rm -rf binutils-build_2 ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/17/logs/stdio

- 18: configure_1 ( failure )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/18/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/77/builds/7736/steps/18/logs/config_log

A new failure has been detected on builder binutils-fedora-ppc64le while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/86/builds/5738

Build state: failed configure (failure)
Revision: f690b305d643b050b90fe75db462d5f7c608476e
Worker: fedora-ppc64le
Build Reason: (unknown)
Blamelist: GDB Administrator <gdbadmin@sourceware.org>, Tom Tromey <tromey@adacore.com>, Tom de Vries <tdevries@suse.de>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/3/logs/config_log

- 4: make ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/4/logs/stdio
        - warnings (31): https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/4/logs/warnings__31_

- 5: make check ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/5/logs/stdio
        - ld.sum: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/5/logs/ld_sum
        - ld.log: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/5/logs/ld_log
        - gas.sum: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/5/logs/gas_sum
        - gas.log: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/5/logs/gas_log
        - gprof.log: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/5/logs/gprof_log
        - binutils.sum: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/5/logs/binutils_sum
        - binutils.log: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/5/logs/binutils_log
        - libsframe.sum: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/5/logs/libsframe_sum
        - libsframe.log: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/5/logs/libsframe_log
        - libctf.sum: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/5/logs/libctf_sum
        - libctf.log: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/5/logs/libctf_log
        - warnings (15): https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/5/logs/warnings__15_

- 6: prep ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/6/logs/stdio

- 7: collect system versions ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/7/logs/stdio

- 8: fetch .bunsen.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/8/logs/stdio

- 9: build bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/9/logs/stdio

- 10: fetch bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/10/logs/stdio

- 11: unpack bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/11/logs/stdio

- 12: pass .bunsen.source.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/12/logs/stdio

- 13: upload to bunsen ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/13/logs/stdio

- 14: clean up ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/14/logs/stdio

- 15: rm -rf binutils-build_1 ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/15/logs/stdio

- 16: git checkout_1 ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/16/logs/stdio

- 17: rm -rf binutils-build_2 ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/17/logs/stdio

- 18: configure_1 ( failure )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/18/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/86/builds/5738/steps/18/logs/config_log


From builder@sourceware.org  Sat Jun  6 01:36:23 2026
From: builder@sourceware.org (builder@sourceware.org)
Date: Sat, 06 Jun 2026 01:36:23 +0000
Subject: =?utf-8?q?=E2=98=9D_Buildbot_=28Sourceware=29=3A_binutils-gdb_-_retry_lost_connection_compile_=28retry=29_=28master=29?=
Message-ID: <20260606013623.66C304BA540B@sourceware.org>

A retry build has been detected on builder binutils-solaris11-sparcv9 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/370/builds/2

Build state: retry lost connection compile (retry)
Revision: f690b305d643b050b90fe75db462d5f7c608476e
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: GDB Administrator <gdbadmin@sourceware.org>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/2/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/2/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/2/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/370/builds/2/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/2/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/370/builds/2/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-sparcv9 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/370/builds/3

Build state: retry lost connection compile (retry)
Revision: f690b305d643b050b90fe75db462d5f7c608476e
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: GDB Administrator <gdbadmin@sourceware.org>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/3/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/3/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/3/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/370/builds/3/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/3/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/370/builds/3/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-sparcv9 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/370/builds/4

Build state: retry lost connection compile (retry)
Revision: f690b305d643b050b90fe75db462d5f7c608476e
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: GDB Administrator <gdbadmin@sourceware.org>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/4/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/4/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/4/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/370/builds/4/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/4/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/370/builds/4/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-sparcv9 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/370/builds/5

Build state: retry lost connection compile (retry)
Revision: f690b305d643b050b90fe75db462d5f7c608476e
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: GDB Administrator <gdbadmin@sourceware.org>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/5/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/5/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/5/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/370/builds/5/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/5/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/370/builds/5/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-sparcv9 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/370/builds/6

Build state: retry lost connection compile (retry)
Revision: f690b305d643b050b90fe75db462d5f7c608476e
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: GDB Administrator <gdbadmin@sourceware.org>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/6/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/6/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/6/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/370/builds/6/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/6/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/370/builds/6/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-sparcv9 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/370/builds/7

Build state: retry lost connection compile (retry)
Revision: f690b305d643b050b90fe75db462d5f7c608476e
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: GDB Administrator <gdbadmin@sourceware.org>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/7/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/7/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/7/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/370/builds/7/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/7/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/370/builds/7/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-sparcv9 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/370/builds/8

Build state: retry lost connection compile (retry)
Revision: f690b305d643b050b90fe75db462d5f7c608476e
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: GDB Administrator <gdbadmin@sourceware.org>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/8/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/8/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/8/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/370/builds/8/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/8/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/370/builds/8/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-sparcv9 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/370/builds/9

Build state: retry lost connection compile (retry)
Revision: f690b305d643b050b90fe75db462d5f7c608476e
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: GDB Administrator <gdbadmin@sourceware.org>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/9/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/9/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/9/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/370/builds/9/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/9/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/370/builds/9/steps/4/logs/cancelled

A cancelled build has been detected on builder binutils-solaris11-sparcv9 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/370/builds/10

Build state: cancelled (no reason) compile (cancelled)
Revision: f690b305d643b050b90fe75db462d5f7c608476e
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: GDB Administrator <gdbadmin@sourceware.org>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/10/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/10/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/10/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/370/builds/10/steps/3/logs/config_log

- 4: make ( cancelled )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/10/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/370/builds/10/steps/4/logs/cancelled
        - warnings (14): https://builder.sourceware.org/buildbot/#/builders/370/builds/10/steps/4/logs/warnings__14_


From amodra@gmail.com  Sat Jun  6 01:41:56 2026
From: amodra@gmail.com (Alan Modra)
Date: Sat, 6 Jun 2026 11:11:56 +0930
Subject: filter_implib_symbols
Message-ID: <aiN65NCEdRxFzn_f@squeak.grove.modra.org>

This tidies filter_implib_symbols implementations, which I noticed
returned unsigned int but took long symbol counts.  While unsigned int
is very likely sufficient, size_t is better.

_bfd_elf_filter_global_symbols is a linker-only function so really
should be moved to elflink.c, but I left it in elf.c as it calls
sym_is_global, a static function in elf.c.

	* elf-bfd.h (struct elf_backend_data): Take size_t symcount
	and return a size_t from elf_backend_filter_implib_symbols.
	(_bfd_elf_filter_implib_symbols): Likewise.  Rename from
	_bfd_elf_filter_global_symbols.
	* elf.c (_bfd_elf_filter_implib_symbols): Likewise.  Use
	size_t vars too, and avoid unnecessary casts.
	* elf32-arm.c (elf32_arm_filter_cmse_symbols): Likewise.
	(elf32_arm_filter_implib_symbols): Likewise.
	* elflink.c (elf_output_implib): Avoid unneccesary casts.
	Call elf_backend_filter_implib_symbols uncontitionally.
	* elfxx-target.h (elf_backend_filter_implib_symbols): Define
	fallback as _bfd_elf_filter_implib_symbols.

diff --git a/bfd/elf-bfd.h b/bfd/elf-bfd.h
index 879dd62dbd6..88d35925987 100644
--- a/bfd/elf-bfd.h
+++ b/bfd/elf-bfd.h
@@ -1400,8 +1400,8 @@ struct elf_backend_data
 
   /* Filter what symbols of the output file to include in the import
      library if one is created.  */
-  unsigned int (*elf_backend_filter_implib_symbols)
-    (struct bfd_link_info *, asymbol **, long);
+  size_t (*elf_backend_filter_implib_symbols)
+    (struct bfd_link_info *, asymbol **, size_t);
 
   /* Copy any information related to dynamic linking from a pre-existing
      symbol to a newly created symbol.  Also called to copy flags and
@@ -2459,8 +2459,8 @@ extern bool _bfd_elf_section_already_linked
   (bfd *, asection *, struct bfd_link_info *) ATTRIBUTE_HIDDEN;
 extern void bfd_elf_set_group_contents
   (bfd *, asection *, void *);
-extern unsigned int _bfd_elf_filter_global_symbols
-  (struct bfd_link_info *, asymbol **, long) ATTRIBUTE_HIDDEN;
+extern size_t _bfd_elf_filter_implib_symbols
+  (struct bfd_link_info *, asymbol **, size_t) ATTRIBUTE_HIDDEN;
 extern asection *_bfd_elf_check_kept_section
   (asection *, struct bfd_link_info *) ATTRIBUTE_HIDDEN;
 #define _bfd_elf_link_just_syms _bfd_generic_link_just_syms
diff --git a/bfd/elf.c b/bfd/elf.c
index 1e1f09c8bbc..c9a68404e9d 100644
--- a/bfd/elf.c
+++ b/bfd/elf.c
@@ -4462,16 +4462,16 @@ sym_is_global (bfd *abfd, asymbol *sym)
 
    Returns the number of symbols to keep.  */
 
-unsigned int
-_bfd_elf_filter_global_symbols (struct bfd_link_info *info,
-				asymbol **syms, long symcount)
+size_t
+_bfd_elf_filter_implib_symbols (struct bfd_link_info *info,
+				asymbol **syms, size_t symcount)
 {
-  long src_count, dst_count = 0;
+  size_t src_count, dst_count = 0;
 
   for (src_count = 0; src_count < symcount; src_count++)
     {
       asymbol *sym = syms[src_count];
-      char *name = (char *) bfd_asymbol_name (sym);
+      const char *name = bfd_asymbol_name (sym);
       struct bfd_link_hash_entry *h;
 
       if (!sym_is_global (info->output_bfd, sym))
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index 63b908462b1..e27aff48411 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -18250,13 +18250,13 @@ elf32_arm_output_arch_local_syms (struct bfd_link_info *info,
 
    Returns the number of symbols to keep.  */
 
-static unsigned int
+static size_t
 elf32_arm_filter_cmse_symbols (struct bfd_link_info *info,
-			       asymbol **syms, long symcount)
+			       asymbol **syms, size_t symcount)
 {
   size_t maxnamelen;
   char *cmse_name;
-  long src_count, dst_count = 0;
+  size_t src_count, dst_count = 0;
   struct elf32_arm_link_hash_table *htab;
 
   htab = elf32_arm_hash_table (info);
@@ -18264,7 +18264,7 @@ elf32_arm_filter_cmse_symbols (struct bfd_link_info *info,
     symcount = 0;
 
   maxnamelen = 128;
-  cmse_name = (char *) bfd_malloc (maxnamelen);
+  cmse_name = bfd_malloc (maxnamelen);
   BFD_ASSERT (cmse_name);
 
   for (src_count = 0; src_count < symcount; src_count++)
@@ -18272,12 +18272,12 @@ elf32_arm_filter_cmse_symbols (struct bfd_link_info *info,
       struct elf32_arm_link_hash_entry *cmse_hash;
       asymbol *sym;
       flagword flags;
-      char *name;
+      const char *name;
       size_t namelen;
 
       sym = syms[src_count];
       flags = sym->flags;
-      name = (char *) bfd_asymbol_name (sym);
+      name = bfd_asymbol_name (sym);
 
       if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
 	continue;
@@ -18287,8 +18287,7 @@ elf32_arm_filter_cmse_symbols (struct bfd_link_info *info,
       namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
       if (namelen > maxnamelen)
 	{
-	  cmse_name = (char *)
-	    bfd_realloc (cmse_name, namelen);
+	  cmse_name = bfd_realloc (cmse_name, namelen);
 	  maxnamelen = namelen;
 	}
       snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
@@ -18317,9 +18316,9 @@ elf32_arm_filter_cmse_symbols (struct bfd_link_info *info,
 
    Returns the number of symbols to keep.  */
 
-static unsigned int
+static size_t
 elf32_arm_filter_implib_symbols (struct bfd_link_info *info,
-				 asymbol **syms, long symcount)
+				 asymbol **syms, size_t symcount)
 {
   struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
 
@@ -18330,7 +18329,7 @@ elf32_arm_filter_implib_symbols (struct bfd_link_info *info,
   if (globals->cmse_implib)
     return elf32_arm_filter_cmse_symbols (info, syms, symcount);
   else
-    return _bfd_elf_filter_global_symbols (info, syms, symcount);
+    return _bfd_elf_filter_implib_symbols (info, syms, symcount);
 }
 
 /* Allocate target specific section data.  */
diff --git a/bfd/elflink.c b/bfd/elflink.c
index 502c8068847..3c4332b549a 100644
--- a/bfd/elflink.c
+++ b/bfd/elflink.c
@@ -12525,7 +12525,6 @@ elf_output_implib (bfd *obfd, struct bfd_link_info *info)
   long symcount;
   long src_count;
   elf_symbol_type *osymbuf;
-  size_t amt;
 
   implib_bfd = info->out_implib_bfd;
   obed = get_elf_backend_data (obfd);
@@ -12554,7 +12553,7 @@ elf_output_implib (bfd *obfd, struct bfd_link_info *info)
     return false;
 
   /* Read in the symbol table.  */
-  sympp = (asymbol **) bfd_malloc (symsize);
+  sympp = bfd_malloc (symsize);
   if (sympp == NULL)
     return false;
 
@@ -12568,10 +12567,7 @@ elf_output_implib (bfd *obfd, struct bfd_link_info *info)
     goto free_sym_buf;
 
   /* Filter symbols to appear in the import library.  */
-  if (obed->elf_backend_filter_implib_symbols)
-    symcount = obed->elf_backend_filter_implib_symbols (info, sympp, symcount);
-  else
-    symcount = _bfd_elf_filter_global_symbols (info, sympp, symcount);
+  symcount = obed->elf_backend_filter_implib_symbols (info, sympp, symcount);
   if (symcount == 0)
     {
       bfd_set_error (bfd_error_no_symbols);
@@ -12580,17 +12576,14 @@ elf_output_implib (bfd *obfd, struct bfd_link_info *info)
       goto free_sym_buf;
     }
 
-
   /* Make symbols absolute.  */
-  amt = symcount * sizeof (*osymbuf);
-  osymbuf = (elf_symbol_type *) bfd_alloc (implib_bfd, amt);
+  osymbuf = bfd_alloc (implib_bfd, symcount * sizeof (*osymbuf));
   if (osymbuf == NULL)
     goto free_sym_buf;
 
   for (src_count = 0; src_count < symcount; src_count++)
     {
-      memcpy (&osymbuf[src_count], (elf_symbol_type *) sympp[src_count],
-	      sizeof (*osymbuf));
+      memcpy (&osymbuf[src_count], sympp[src_count], sizeof (*osymbuf));
       osymbuf[src_count].symbol.section = bfd_abs_section_ptr;
       osymbuf[src_count].internal_elf_sym.st_shndx = SHN_ABS;
       osymbuf[src_count].symbol.value += sympp[src_count]->section->vma;
diff --git a/bfd/elfxx-target.h b/bfd/elfxx-target.h
index b6dfc108f27..03689f68ea3 100644
--- a/bfd/elfxx-target.h
+++ b/bfd/elfxx-target.h
@@ -620,7 +620,7 @@
 #define elf_backend_output_arch_syms		NULL
 #endif
 #ifndef elf_backend_filter_implib_symbols
-#define elf_backend_filter_implib_symbols	NULL
+#define elf_backend_filter_implib_symbols	_bfd_elf_filter_implib_symbols
 #endif
 #ifndef elf_backend_copy_indirect_symbol
 #define elf_backend_copy_indirect_symbol	_bfd_elf_link_hash_copy_indirect

-- 
Alan Modra

From builder@sourceware.org  Sat Jun  6 06:47:14 2026
From: builder@sourceware.org (builder@sourceware.org)
Date: Sat, 06 Jun 2026 06:47:14 +0000
Subject: =?utf-8?q?=E2=98=9D_Buildbot_=28Sourceware=29=3A_binutils-gdb_-_retry_lost_connection_compile_=28retry=29_=28master=29?=
Message-ID: <20260606064714.6438F4BCA437@sourceware.org>

A retry build has been detected on builder binutils-solaris11-i386 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/364/builds/2

Build state: retry lost connection compile (retry)
Revision: f690b305d643b050b90fe75db462d5f7c608476e
Worker: solaris11-amd64
Build Reason: (unknown)
Blamelist: GDB Administrator <gdbadmin@sourceware.org>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/2/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/2/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/2/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/364/builds/2/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/2/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/364/builds/2/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-i386 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/364/builds/3

Build state: retry lost connection compile (retry)
Revision: f690b305d643b050b90fe75db462d5f7c608476e
Worker: solaris11-amd64
Build Reason: (unknown)
Blamelist: GDB Administrator <gdbadmin@sourceware.org>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/3/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/3/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/3/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/364/builds/3/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/3/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/364/builds/3/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-i386 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/364/builds/4

Build state: retry lost connection compile (retry)
Revision: f690b305d643b050b90fe75db462d5f7c608476e
Worker: solaris11-amd64
Build Reason: (unknown)
Blamelist: GDB Administrator <gdbadmin@sourceware.org>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/4/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/4/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/4/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/364/builds/4/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/4/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/364/builds/4/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-i386 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/364/builds/5

Build state: retry lost connection compile (retry)
Revision: f690b305d643b050b90fe75db462d5f7c608476e
Worker: solaris11-amd64
Build Reason: (unknown)
Blamelist: GDB Administrator <gdbadmin@sourceware.org>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/5/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/5/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/5/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/364/builds/5/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/5/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/364/builds/5/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-i386 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/364/builds/6

Build state: retry lost connection compile (retry)
Revision: f690b305d643b050b90fe75db462d5f7c608476e
Worker: solaris11-amd64
Build Reason: (unknown)
Blamelist: GDB Administrator <gdbadmin@sourceware.org>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/6/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/6/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/6/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/364/builds/6/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/6/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/364/builds/6/steps/4/logs/cancelled

A new failure has been detected on builder binutils-solaris11-i386 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/364/builds/7

Build state: failed test (failure)
Revision: f690b305d643b050b90fe75db462d5f7c608476e
Worker: solaris11-amd64
Build Reason: (unknown)
Blamelist: GDB Administrator <gdbadmin@sourceware.org>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/3/logs/config_log

- 4: make ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/4/logs/stdio
        - warnings (33): https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/4/logs/warnings__33_

- 5: make check ( failure )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/5/logs/stdio
        - ld.sum: https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/5/logs/ld_sum
        - ld.log: https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/5/logs/ld_log
        - gas.sum: https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/5/logs/gas_sum
        - gas.log: https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/5/logs/gas_log
        - gprof.log: https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/5/logs/gprof_log
        - binutils.sum: https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/5/logs/binutils_sum
        - binutils.log: https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/5/logs/binutils_log
        - libsframe.sum: https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/5/logs/libsframe_sum
        - libsframe.log: https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/5/logs/libsframe_log
        - libctf.sum: https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/5/logs/libctf_sum
        - libctf.log: https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/5/logs/libctf_log
        - warnings (9): https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/5/logs/warnings__9_

- 6: prep ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/6/logs/stdio

- 7: collect system versions ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/7/logs/stdio

- 8: fetch .bunsen.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/8/logs/stdio

- 9: build bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/9/logs/stdio

- 10: fetch bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/10/logs/stdio

- 11: unpack bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/11/logs/stdio

- 12: pass .bunsen.source.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/12/logs/stdio

- 13: upload to bunsen ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/13/logs/stdio

- 14: clean up ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/14/logs/stdio

- 15: rm -rf binutils-build_1 ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/7/steps/15/logs/stdio


From builder@sourceware.org  Sat Jun  6 06:51:39 2026
From: builder@sourceware.org (builder@sourceware.org)
Date: Sat, 06 Jun 2026 06:51:39 +0000
Subject: =?utf-8?q?=E2=98=A0_Buildbot_=28Sourceware=29=3A_binutils-gdb_-_failed_configure_=28failure=29_=28master=29?=
Message-ID: <20260606065139.D15F14BA5435@sourceware.org>

A new failure has been detected on builder binutils-solaris11-amd64 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/369/builds/2

Build state: failed configure (failure)
Revision: f690b305d643b050b90fe75db462d5f7c608476e
Worker: solaris11-amd64
Build Reason: (unknown)
Blamelist: GDB Administrator <gdbadmin@sourceware.org>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/2/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/2/steps/2/logs/stdio

- 3: configure ( failure )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/2/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/369/builds/2/steps/3/logs/config_log


From builder@sourceware.org  Sat Jun  6 06:57:55 2026
From: builder@sourceware.org (builder@sourceware.org)
Date: Sat, 06 Jun 2026 06:57:55 +0000
Subject: =?utf-8?q?=E2=98=9D_Buildbot_=28Sourceware=29=3A_binutils-gdb_-_retry_lost_connection_compile_=28retry=29_=28master=29?=
Message-ID: <20260606065755.F23774BA540B@sourceware.org>

A retry build has been detected on builder binutils-solaris11-sparc while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/365/builds/5

Build state: retry lost connection compile (retry)
Revision: 8a676181f7b8e520c205c10b82d6b24a3a9cf431
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/5/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/5/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/5/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/5/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/5/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/365/builds/5/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-sparc while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/365/builds/6

Build state: retry lost connection compile (retry)
Revision: 8a676181f7b8e520c205c10b82d6b24a3a9cf431
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/6/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/6/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/6/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/6/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/6/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/365/builds/6/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-sparc while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/365/builds/7

Build state: retry lost connection compile (retry)
Revision: 8a676181f7b8e520c205c10b82d6b24a3a9cf431
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/7/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/7/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/7/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/7/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/7/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/365/builds/7/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-sparc while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/365/builds/8

Build state: retry lost connection compile (retry)
Revision: 8a676181f7b8e520c205c10b82d6b24a3a9cf431
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/8/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/8/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/8/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/8/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/8/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/365/builds/8/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-sparc while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/365/builds/9

Build state: retry lost connection compile (retry)
Revision: 8a676181f7b8e520c205c10b82d6b24a3a9cf431
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/9/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/9/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/9/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/9/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/9/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/365/builds/9/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-sparc while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/365/builds/10

Build state: retry lost connection compile (retry)
Revision: 8a676181f7b8e520c205c10b82d6b24a3a9cf431
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/10/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/10/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/10/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/10/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/10/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/365/builds/10/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-sparc while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/365/builds/11

Build state: retry lost connection compile (retry)
Revision: 8a676181f7b8e520c205c10b82d6b24a3a9cf431
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/11/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/11/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/11/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/11/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/11/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/365/builds/11/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-sparc while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/365/builds/12

Build state: retry lost connection compile (retry)
Revision: 8a676181f7b8e520c205c10b82d6b24a3a9cf431
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/12/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/12/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/12/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/12/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/12/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/365/builds/12/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-sparc while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/365/builds/13

Build state: retry lost connection compile (retry)
Revision: 8a676181f7b8e520c205c10b82d6b24a3a9cf431
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/13/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/13/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/13/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/13/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/13/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/365/builds/13/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-sparc while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/365/builds/14

Build state: retry lost connection compile (retry)
Revision: 8a676181f7b8e520c205c10b82d6b24a3a9cf431
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/14/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/14/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/14/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/14/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/14/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/365/builds/14/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-sparc while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/365/builds/15

Build state: retry lost connection compile (retry)
Revision: 8a676181f7b8e520c205c10b82d6b24a3a9cf431
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/15/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/15/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/15/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/15/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/15/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/365/builds/15/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-sparc while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/365/builds/16

Build state: retry lost connection compile (retry)
Revision: 8a676181f7b8e520c205c10b82d6b24a3a9cf431
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/16/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/16/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/16/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/16/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/16/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/365/builds/16/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-sparc while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/365/builds/17

Build state: retry lost connection compile (retry)
Revision: 8a676181f7b8e520c205c10b82d6b24a3a9cf431
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/17/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/17/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/17/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/17/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/17/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/365/builds/17/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-sparc while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/365/builds/18

Build state: retry lost connection compile (retry)
Revision: 8a676181f7b8e520c205c10b82d6b24a3a9cf431
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/18/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/18/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/18/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/18/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/18/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/365/builds/18/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-sparc while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/365/builds/19

Build state: retry (no reason) lost connection compile (retry)
Revision: 8a676181f7b8e520c205c10b82d6b24a3a9cf431
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/19/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/19/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/19/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/19/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/19/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/365/builds/19/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-sparcv9 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/370/builds/11

Build state: retry lost connection compile (retry)
Revision: 8a676181f7b8e520c205c10b82d6b24a3a9cf431
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/11/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/11/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/11/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/370/builds/11/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/11/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/370/builds/11/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-sparcv9 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/370/builds/12

Build state: retry lost connection compile (retry)
Revision: 8a676181f7b8e520c205c10b82d6b24a3a9cf431
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/12/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/12/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/12/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/370/builds/12/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/12/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/370/builds/12/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-sparcv9 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/370/builds/13

Build state: retry lost connection compile (retry)
Revision: 8a676181f7b8e520c205c10b82d6b24a3a9cf431
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/13/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/13/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/13/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/370/builds/13/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/13/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/370/builds/13/steps/4/logs/cancelled

A retry build has been detected on builder binutils-solaris11-sparcv9 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/370/builds/14

Build state: retry lost connection compile (retry)
Revision: 8a676181f7b8e520c205c10b82d6b24a3a9cf431
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/14/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/14/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/14/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/370/builds/14/steps/3/logs/config_log

- 4: make ( retry )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/14/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/370/builds/14/steps/4/logs/cancelled


From amodra@gmail.com  Sat Jun  6 01:41:30 2026
From: amodra@gmail.com (Alan Modra)
Date: Sat, 6 Jun 2026 11:11:30 +0930
Subject: Drop output bfd param from many elf linker functions
Message-ID: <aiN6yhnvoiLTTyV8@squeak.grove.modra.org>

Functions that are always passed a non-NULL bfd_link_info* and are not
called by BFD_SEND using the output bfd, need not pass the output bfd
as a parameter.  It can be accessed via info->output_bfd.  Removing
the excess parameters result in a small code size reduction on
x86_64-linux --enable-targets=all ld built with a static libbfd, from
9896133 to 9893805 bytes.

diff --git a/bfd/elf-bfd.h b/bfd/elf-bfd.h
index 12ac3f362c0..879dd62dbd6 100644
--- a/bfd/elf-bfd.h
+++ b/bfd/elf-bfd.h
@@ -1179,7 +1179,7 @@ struct elf_backend_data
   /* When creating a shared library, determine whether to omit the
      dynamic symbol for the section.  */
   bool (*elf_backend_omit_section_dynsym)
-    (bfd *output_bfd, struct bfd_link_info *info, asection *osec);
+    (struct bfd_link_info *info, asection *osec);
 
   /* Return TRUE if relocations of targets are compatible to the extent
      that CHECK_RELOCS will properly process them.  PR 4424.  */
@@ -1251,9 +1251,9 @@ struct elf_backend_data
      Besides those, these functions must handle the .interp section
      and any other sections created by CREATE_DYNAMIC_SECTIONS.  */
   bool (*elf_backend_early_size_sections)
-    (bfd *output_bfd, struct bfd_link_info *info);
+    (struct bfd_link_info *info);
   bool (*elf_backend_late_size_sections)
-    (bfd *output_bfd, struct bfd_link_info *info);
+    (struct bfd_link_info *info);
 
   /* The STRIP_ZERO_SIZED_DYNAMIC_SECTIONS function is called by the
      ELF backend linker to strip zero-sized dynamic sections after
@@ -1264,7 +1264,7 @@ struct elf_backend_data
   /* Set TEXT_INDEX_SECTION and DATA_INDEX_SECTION, the output sections
      we keep to use as a base for relocs and symbols.  */
   void (*elf_backend_init_index_section)
-    (bfd *output_bfd, struct bfd_link_info *info);
+    (struct bfd_link_info *info);
 
   /* The RELOCATE_SECTION function is called by the ELF backend linker
      to handle the relocations for a section.
@@ -1298,7 +1298,7 @@ struct elf_backend_data
      Returns FALSE on error, TRUE on success, 2 if successful and
      relocations should be written for this section.  */
   int (*elf_backend_relocate_section)
-    (bfd *output_bfd, struct bfd_link_info *info, bfd *input_bfd,
+    (struct bfd_link_info *info, bfd *input_bfd,
      asection *input_section, bfd_byte *contents, Elf_Internal_Rela *relocs,
      Elf_Internal_Sym *local_syms, asection **local_sections);
 
@@ -1310,7 +1310,7 @@ struct elf_backend_data
      all .dynsym symbols, while ADJUST_DYNAMIC_SYMBOL is only called
      on those symbols which are defined by a dynamic object.  */
   bool (*elf_backend_finish_dynamic_symbol)
-    (bfd *output_bfd, struct bfd_link_info *info,
+    (struct bfd_link_info *info,
      struct elf_link_hash_entry *h, Elf_Internal_Sym *sym);
 
   /* The FINISH_DYNAMIC_SECTIONS function is called by the ELF backend
@@ -1318,7 +1318,7 @@ struct elf_backend_data
      output file.  The FINISH_DYNAMIC_SYMBOL will have been called on
      all dynamic symbols.  */
   bool (*elf_backend_finish_dynamic_sections)
-    (bfd *output_bfd, struct bfd_link_info *info, bfd_byte *);
+    (struct bfd_link_info *info, bfd_byte *);
 
   /* A function to do any beginning processing needed for the ELF file
      before building the ELF headers and computing file positions.  */
@@ -1386,7 +1386,7 @@ struct elf_backend_data
      section.  It allows the backend to emit special local symbols
      not handled in the hash table.  */
   bool (*elf_backend_output_arch_local_syms)
-    (bfd *, struct bfd_link_info *, void *,
+    (struct bfd_link_info *, void *,
      int (*) (void *, const char *, Elf_Internal_Sym *, asection *,
 	      struct elf_link_hash_entry *));
 
@@ -1394,14 +1394,14 @@ struct elf_backend_data
      into the symtab section.  It allows the backend to emit special
      global symbols not handled in the hash table.  */
   bool (*elf_backend_output_arch_syms)
-    (bfd *, struct bfd_link_info *, void *,
+    (struct bfd_link_info *, void *,
      int (*) (void *, const char *, Elf_Internal_Sym *, asection *,
 	      struct elf_link_hash_entry *));
 
   /* Filter what symbols of the output file to include in the import
      library if one is created.  */
   unsigned int (*elf_backend_filter_implib_symbols)
-    (bfd *, struct bfd_link_info *, asymbol **, long);
+    (struct bfd_link_info *, asymbol **, long);
 
   /* Copy any information related to dynamic linking from a pre-existing
      symbol to a newly created symbol.  Also called to copy flags and
@@ -1641,9 +1641,10 @@ struct elf_backend_data
 
   /* The size of the GOT entry for the symbol pointed to by H if non-NULL,
      otherwise by the local symbol with index SYMNDX in IBFD.  */
-  bfd_vma (*got_elt_size) (bfd *, struct bfd_link_info *,
+  bfd_vma (*got_elt_size) (struct bfd_link_info *,
 			   struct elf_link_hash_entry *h,
-			   bfd *ibfd, unsigned long symndx);
+			   bfd *ibfd,
+			   unsigned long symndx);
 
   /* The vendor name to use for a processor-standard attributes section.  */
   const char *obj_attrs_vendor;
@@ -2459,7 +2460,7 @@ extern bool _bfd_elf_section_already_linked
 extern void bfd_elf_set_group_contents
   (bfd *, asection *, void *);
 extern unsigned int _bfd_elf_filter_global_symbols
-  (bfd *, struct bfd_link_info *, asymbol **, long) ATTRIBUTE_HIDDEN;
+  (struct bfd_link_info *, asymbol **, long) ATTRIBUTE_HIDDEN;
 extern asection *_bfd_elf_check_kept_section
   (asection *, struct bfd_link_info *) ATTRIBUTE_HIDDEN;
 #define _bfd_elf_link_just_syms _bfd_generic_link_just_syms
@@ -2593,7 +2594,7 @@ extern void _bfd_elf_strtab_finalize
   (struct elf_strtab_hash *) ATTRIBUTE_HIDDEN;
 
 extern bool bfd_elf_parse_eh_frame_entries
-  (bfd *, struct bfd_link_info *);
+  (struct bfd_link_info *);
 extern bool _bfd_elf_parse_eh_frame_entry
   (struct bfd_link_info *, asection *, struct elf_reloc_cookie *)
   ATTRIBUTE_HIDDEN;
@@ -2701,19 +2702,18 @@ extern bool _bfd_elf_validate_reloc
   (bfd *, arelent *) ATTRIBUTE_HIDDEN;
 
 extern bool bfd_elf_record_link_assignment
-  (bfd *, struct bfd_link_info *, const char *, bool,
-   bool);
-extern bool bfd_elf_stack_segment_size (bfd *, struct bfd_link_info *,
+  (struct bfd_link_info *, const char *, bool, bool);
+extern bool bfd_elf_stack_segment_size (struct bfd_link_info *,
 					const char *, bfd_vma);
 extern bool bfd_elf_size_dynamic_sections
-  (bfd *, const char *, const char *, const char *, const char *, const char *,
-   const char * const *, struct bfd_link_info *, struct bfd_section **);
+  (struct bfd_link_info *, const char *, const char *, const char *,
+   const char *, const char *, const char * const *, struct bfd_section **);
 extern bool bfd_elf_size_dynsym_hash_dynstr
-  (bfd *, struct bfd_link_info *);
+  (struct bfd_link_info *);
 extern bool bfd_elf_get_bfd_needed_list
   (bfd *, struct bfd_link_needed_list **);
 extern struct bfd_link_needed_list *bfd_elf_get_needed_list
-  (bfd *, struct bfd_link_info *);
+  (struct bfd_link_info *);
 extern void bfd_elf_set_dt_needed_name
   (bfd *, const char *);
 extern const char *bfd_elf_get_dt_soname
@@ -2723,20 +2723,20 @@ extern void bfd_elf_set_dyn_lib_class
 extern int bfd_elf_get_dyn_lib_class
   (bfd *);
 extern struct bfd_link_needed_list *bfd_elf_get_runpath_list
-  (bfd *, struct bfd_link_info *);
+  (struct bfd_link_info *);
 extern int bfd_elf_discard_info
-  (bfd *, struct bfd_link_info *);
+  (struct bfd_link_info *);
 extern unsigned int _bfd_elf_default_action_discarded
   (struct bfd_section *) ATTRIBUTE_HIDDEN;
 extern struct bfd_section *bfd_elf_tls_setup
-  (bfd *, struct bfd_link_info *);
+  (struct bfd_link_info *);
 
 extern bool bfd_elf_link_create_dynamic_sections
   (bfd *, struct bfd_link_info *);
 extern bool _bfd_elf_omit_section_dynsym_default
-  (bfd *, struct bfd_link_info *, asection *) ATTRIBUTE_HIDDEN;
+  (struct bfd_link_info *, asection *) ATTRIBUTE_HIDDEN;
 extern bool _bfd_elf_omit_section_dynsym_all
-  (bfd *, struct bfd_link_info *, asection *) ATTRIBUTE_HIDDEN;
+  (struct bfd_link_info *, asection *) ATTRIBUTE_HIDDEN;
 extern bool _bfd_elf_create_dynamic_sections
   (bfd *, struct bfd_link_info *) ATTRIBUTE_HIDDEN;
 extern bool _bfd_elf_create_got_section
@@ -2745,10 +2745,12 @@ extern asection *_bfd_elf_section_for_symbol
   (struct elf_reloc_cookie *, unsigned long) ATTRIBUTE_HIDDEN;
 extern struct elf_link_hash_entry *_bfd_elf_define_linkage_sym
   (bfd *, struct bfd_link_info *, asection *, const char *) ATTRIBUTE_HIDDEN;
+extern void _bfd_elf_init_0_index_sections
+  (struct bfd_link_info *) ATTRIBUTE_HIDDEN;
 extern void _bfd_elf_init_1_index_section
-  (bfd *, struct bfd_link_info *) ATTRIBUTE_HIDDEN;
+  (struct bfd_link_info *) ATTRIBUTE_HIDDEN;
 extern void _bfd_elf_init_2_index_sections
-  (bfd *, struct bfd_link_info *) ATTRIBUTE_HIDDEN;
+  (struct bfd_link_info *) ATTRIBUTE_HIDDEN;
 
 extern bool _bfd_elfcore_make_pseudosection
   (bfd *, char *, size_t, ufile_ptr) ATTRIBUTE_HIDDEN;
@@ -2942,7 +2944,7 @@ extern asection *_bfd_elf_common_section
   (asection *) ATTRIBUTE_HIDDEN;
 
 extern bfd_vma _bfd_elf_default_got_elt_size
-  (bfd *, struct bfd_link_info *, struct elf_link_hash_entry *, bfd *,
+  (struct bfd_link_info *, struct elf_link_hash_entry *, bfd *,
    unsigned long) ATTRIBUTE_HIDDEN;
 
 extern bfd_reloc_status_type _bfd_elf_rel_vtable_reloc_fn
@@ -2989,9 +2991,6 @@ extern bool _bfd_elf_gc_mark
 extern bool _bfd_elf_gc_mark_extra_sections
   (struct bfd_link_info *, elf_gc_mark_hook_fn) ATTRIBUTE_HIDDEN;
 
-extern bool bfd_elf_gc_common_finalize_got_offsets
-  (bfd *, struct bfd_link_info *);
-
 extern bool _bfd_elf_gc_common_final_link
   (bfd *, struct bfd_link_info *) ATTRIBUTE_HIDDEN;
 
@@ -3387,7 +3386,7 @@ extern bool _bfd_elf_maybe_set_textrel
   (struct elf_link_hash_entry *, void *) ATTRIBUTE_HIDDEN;
 
 extern bool _bfd_elf_add_dynamic_tags
-  (bfd *, struct bfd_link_info *, bool) ATTRIBUTE_HIDDEN;
+  (struct bfd_link_info *, bool) ATTRIBUTE_HIDDEN;
 
 extern bool _bfd_elf_mmap_section_contents
   (bfd *abfd, asection *section, bfd_byte **buf) ATTRIBUTE_HIDDEN;
diff --git a/bfd/elf-m10200.c b/bfd/elf-m10200.c
index b5b4bae99f4..e8b3b5178ca 100644
--- a/bfd/elf-m10200.c
+++ b/bfd/elf-m10200.c
@@ -336,8 +336,7 @@ mn10200_elf_final_link_relocate (reloc_howto_type *howto,
 
 /* Relocate an MN10200 ELF section.  */
 static int
-mn10200_elf_relocate_section (bfd *output_bfd,
-			      struct bfd_link_info *info,
+mn10200_elf_relocate_section (struct bfd_link_info *info,
 			      bfd *input_bfd,
 			      asection *input_section,
 			      bfd_byte *contents,
@@ -376,7 +375,8 @@ mn10200_elf_relocate_section (bfd *output_bfd,
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections[r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 	}
       else
 	{
@@ -396,7 +396,7 @@ mn10200_elf_relocate_section (bfd *output_bfd,
       if (bfd_link_relocatable (info))
 	continue;
 
-      r = mn10200_elf_final_link_relocate (howto, input_bfd, output_bfd,
+      r = mn10200_elf_final_link_relocate (howto, input_bfd, info->output_bfd,
 					   input_section,
 					   contents, rel->r_offset,
 					   relocation, rel->r_addend,
@@ -1349,9 +1349,9 @@ mn10200_elf_get_relocated_section_contents (bfd *output_bfd,
 	  *secpp = isec;
 	}
 
-      if (! mn10200_elf_relocate_section (output_bfd, link_info, input_bfd,
-				     input_section, data, internal_relocs,
-				     isymbuf, sections))
+      if (! mn10200_elf_relocate_section (link_info, input_bfd,
+					  input_section, data, internal_relocs,
+					  isymbuf, sections))
 	goto error_return;
 
       free (sections);
diff --git a/bfd/elf-m10300.c b/bfd/elf-m10300.c
index 0740a26c219..04cf702a067 100644
--- a/bfd/elf-m10300.c
+++ b/bfd/elf-m10300.c
@@ -1959,8 +1959,7 @@ mn10300_elf_final_link_relocate (reloc_howto_type *howto,
 /* Relocate an MN10300 ELF section.  */
 
 static int
-mn10300_elf_relocate_section (bfd *output_bfd,
-			      struct bfd_link_info *info,
+mn10300_elf_relocate_section (struct bfd_link_info *info,
 			      bfd *input_bfd,
 			      asection *input_section,
 			      bfd_byte *contents,
@@ -2039,7 +2038,8 @@ mn10300_elf_relocate_section (bfd *output_bfd,
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections[r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 	}
       else
 	{
@@ -2080,7 +2080,8 @@ mn10300_elf_relocate_section (bfd *output_bfd,
 	    relocation = 0;
 
 	  else if (!bfd_link_relocatable (info) && unresolved_reloc
-		   && _bfd_elf_section_offset (output_bfd, info, input_section,
+		   && _bfd_elf_section_offset (info->output_bfd, info,
+					       input_section,
 					       rel->r_offset) != (bfd_vma) -1)
 
 	    _bfd_error_handler
@@ -2102,7 +2103,7 @@ mn10300_elf_relocate_section (bfd *output_bfd,
       if (bfd_link_relocatable (info))
 	continue;
 
-      r = mn10300_elf_final_link_relocate (howto, input_bfd, output_bfd,
+      r = mn10300_elf_final_link_relocate (howto, input_bfd, info->output_bfd,
 					   input_section,
 					   contents, rel->r_offset,
 					   relocation, rel->r_addend,
@@ -4485,7 +4486,7 @@ mn10300_elf_get_relocated_section_contents (bfd *output_bfd,
 	  *secpp = isec;
 	}
 
-      if (! mn10300_elf_relocate_section (output_bfd, link_info, input_bfd,
+      if (! mn10300_elf_relocate_section (link_info, input_bfd,
 					  input_section, data, internal_relocs,
 					  isymbuf, sections))
 	goto error_return;
@@ -5007,8 +5008,7 @@ _bfd_mn10300_elf_adjust_dynamic_symbol (struct bfd_link_info * info,
 /* Set the sizes of the dynamic sections.  */
 
 static bool
-_bfd_mn10300_elf_late_size_sections (bfd * output_bfd,
-				     struct bfd_link_info * info)
+_bfd_mn10300_elf_late_size_sections (struct bfd_link_info *info)
 {
   struct elf32_mn10300_link_hash_table *htab = elf32_mn10300_hash_table (info);
   bfd * dynobj;
@@ -5118,15 +5118,14 @@ _bfd_mn10300_elf_late_size_sections (bfd * output_bfd,
       s->alloced = 1;
     }
 
-  return _bfd_elf_add_dynamic_tags (output_bfd, info, relocs);
+  return _bfd_elf_add_dynamic_tags (info, relocs);
 }
 
 /* Finish up dynamic symbol handling.  We set the contents of various
    dynamic sections here.  */
 
 static bool
-_bfd_mn10300_elf_finish_dynamic_symbol (bfd * output_bfd,
-					struct bfd_link_info * info,
+_bfd_mn10300_elf_finish_dynamic_symbol (struct bfd_link_info * info,
 					struct elf_link_hash_entry * h,
 					Elf_Internal_Sym * sym)
 {
@@ -5171,14 +5170,14 @@ _bfd_mn10300_elf_finish_dynamic_symbol (bfd * output_bfd,
 	{
 	  memcpy (splt->contents + h->plt.offset, elf_mn10300_plt_entry,
 		  elf_mn10300_sizeof_plt (info));
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 		      (sgot->output_section->vma
 		       + sgot->output_offset
 		       + got_offset),
 		      (splt->contents + h->plt.offset
 		       + elf_mn10300_plt_symbol_offset (info)));
 
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 		      (1 - h->plt.offset - elf_mn10300_plt_plt0_offset (info)),
 		      (splt->contents + h->plt.offset
 		       + elf_mn10300_plt_plt0_offset (info)));
@@ -5188,17 +5187,17 @@ _bfd_mn10300_elf_finish_dynamic_symbol (bfd * output_bfd,
 	  memcpy (splt->contents + h->plt.offset, elf_mn10300_pic_plt_entry,
 		  elf_mn10300_sizeof_plt (info));
 
-	  bfd_put_32 (output_bfd, got_offset,
+	  bfd_put_32 (info->output_bfd, got_offset,
 		      (splt->contents + h->plt.offset
 		       + elf_mn10300_plt_symbol_offset (info)));
 	}
 
-      bfd_put_32 (output_bfd, plt_index * sizeof (Elf32_External_Rela),
+      bfd_put_32 (info->output_bfd, plt_index * sizeof (Elf32_External_Rela),
 		  (splt->contents + h->plt.offset
 		   + elf_mn10300_plt_reloc_offset (info)));
 
       /* Fill in the entry in the global offset table.  */
-      bfd_put_32 (output_bfd,
+      bfd_put_32 (info->output_bfd,
 		  (splt->output_section->vma
 		   + splt->output_offset
 		   + h->plt.offset
@@ -5211,7 +5210,7 @@ _bfd_mn10300_elf_finish_dynamic_symbol (bfd * output_bfd,
 		      + got_offset);
       rel.r_info = ELF32_R_INFO (h->dynindx, R_MN10300_JMP_SLOT);
       rel.r_addend = 0;
-      bfd_elf32_swap_reloca_out (output_bfd, &rel,
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rel,
 				 (bfd_byte *) ((Elf32_External_Rela *) srel->contents
 					       + plt_index));
 
@@ -5239,11 +5238,11 @@ _bfd_mn10300_elf_finish_dynamic_symbol (bfd * output_bfd,
       switch (elf_mn10300_hash_entry (h)->tls_type)
 	{
 	case GOT_TLS_GD:
-	  bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + h->got.offset);
-	  bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + h->got.offset + 4);
+	  bfd_put_32 (info->output_bfd, 0, sgot->contents + h->got.offset);
+	  bfd_put_32 (info->output_bfd, 0, sgot->contents + h->got.offset + 4);
 	  rel.r_info = ELF32_R_INFO (h->dynindx, R_MN10300_TLS_DTPMOD);
 	  rel.r_addend = 0;
-	  bfd_elf32_swap_reloca_out (output_bfd, & rel,
+	  bfd_elf32_swap_reloca_out (info->output_bfd, & rel,
 				     (bfd_byte *) ((Elf32_External_Rela *) srel->contents
 						   + srel->reloc_count));
 	  ++ srel->reloc_count;
@@ -5256,8 +5255,9 @@ _bfd_mn10300_elf_finish_dynamic_symbol (bfd * output_bfd,
 	  /* We originally stored the addend in the GOT, but at this
 	     point, we want to move it to the reloc instead as that's
 	     where the dynamic linker wants it.  */
-	  rel.r_addend = bfd_get_32 (output_bfd, sgot->contents + h->got.offset);
-	  bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + h->got.offset);
+	  rel.r_addend = bfd_get_32 (info->output_bfd,
+				     sgot->contents + h->got.offset);
+	  bfd_put_32 (info->output_bfd, 0, sgot->contents + h->got.offset);
 	  if (h->dynindx == -1)
 	    rel.r_info = ELF32_R_INFO (0, R_MN10300_TLS_TPOFF);
 	  else
@@ -5281,7 +5281,7 @@ _bfd_mn10300_elf_finish_dynamic_symbol (bfd * output_bfd,
 	    }
 	  else
 	    {
-	      bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + h->got.offset);
+	      bfd_put_32 (info->output_bfd, 0, sgot->contents + h->got.offset);
 	      rel.r_info = ELF32_R_INFO (h->dynindx, R_MN10300_GLOB_DAT);
 	      rel.r_addend = 0;
 	    }
@@ -5289,7 +5289,7 @@ _bfd_mn10300_elf_finish_dynamic_symbol (bfd * output_bfd,
 
       if (ELF32_R_TYPE (rel.r_info) != R_MN10300_NONE)
 	{
-	  bfd_elf32_swap_reloca_out (output_bfd, &rel,
+	  bfd_elf32_swap_reloca_out (info->output_bfd, &rel,
 				     (bfd_byte *) ((Elf32_External_Rela *) srel->contents
 						   + srel->reloc_count));
 	  ++ srel->reloc_count;
@@ -5314,7 +5314,7 @@ _bfd_mn10300_elf_finish_dynamic_symbol (bfd * output_bfd,
 		      + h->root.u.def.section->output_offset);
       rel.r_info = ELF32_R_INFO (h->dynindx, R_MN10300_COPY);
       rel.r_addend = 0;
-      bfd_elf32_swap_reloca_out (output_bfd, & rel,
+      bfd_elf32_swap_reloca_out (info->output_bfd, & rel,
 				 (bfd_byte *) ((Elf32_External_Rela *) s->contents
 					       + s->reloc_count));
       ++ s->reloc_count;
@@ -5331,8 +5331,7 @@ _bfd_mn10300_elf_finish_dynamic_symbol (bfd * output_bfd,
 /* Finish up the dynamic sections.  */
 
 static bool
-_bfd_mn10300_elf_finish_dynamic_sections (bfd *output_bfd,
-					  struct bfd_link_info *info,
+_bfd_mn10300_elf_finish_dynamic_sections (struct bfd_link_info *info,
 					  bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   bfd *      dynobj;
@@ -5376,13 +5375,13 @@ _bfd_mn10300_elf_finish_dynamic_sections (bfd *output_bfd,
 	      s = htab->root.srelplt;
 	    get_vma:
 	      dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    case DT_PLTRELSZ:
 	      s = htab->root.srelplt;
 	      dyn.d_un.d_val = s->size;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 	    }
 	}
@@ -5399,10 +5398,10 @@ _bfd_mn10300_elf_finish_dynamic_sections (bfd *output_bfd,
 	  else
 	    {
 	      memcpy (splt->contents, elf_mn10300_plt0_entry, PLT0_ENTRY_SIZE);
-	      bfd_put_32 (output_bfd,
+	      bfd_put_32 (info->output_bfd,
 			  sgot->output_section->vma + sgot->output_offset + 4,
 			  splt->contents + elf_mn10300_plt0_gotid_offset (info));
-	      bfd_put_32 (output_bfd,
+	      bfd_put_32 (info->output_bfd,
 			  sgot->output_section->vma + sgot->output_offset + 8,
 			  splt->contents + elf_mn10300_plt0_linker_offset (info));
 	    }
@@ -5425,13 +5424,13 @@ _bfd_mn10300_elf_finish_dynamic_sections (bfd *output_bfd,
   if (sgot->size > 0)
     {
       if (sdyn == NULL)
-	bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
+	bfd_put_32 (info->output_bfd, 0, sgot->contents);
       else
-	bfd_put_32 (output_bfd,
+	bfd_put_32 (info->output_bfd,
 		    sdyn->output_section->vma + sdyn->output_offset,
 		    sgot->contents);
-      bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
-      bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
+      bfd_put_32 (info->output_bfd, 0, sgot->contents + 4);
+      bfd_put_32 (info->output_bfd, 0, sgot->contents + 8);
     }
 
   elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
diff --git a/bfd/elf-vxworks.c b/bfd/elf-vxworks.c
index e77cd9cc305..8266030805d 100644
--- a/bfd/elf-vxworks.c
+++ b/bfd/elf-vxworks.c
@@ -240,16 +240,16 @@ elf_vxworks_final_write_processing (bfd *abfd)
    tls sections.  */
 
 bool
-elf_vxworks_add_dynamic_entries (bfd *output_bfd, struct bfd_link_info *info)
+elf_vxworks_add_dynamic_entries (struct bfd_link_info *info)
 {
-  if (bfd_get_section_by_name (output_bfd, ".tls_data"))
+  if (bfd_get_section_by_name (info->output_bfd, ".tls_data"))
     {
       if (!_bfd_elf_add_dynamic_entry (info, DT_VX_WRS_TLS_DATA_START, 0)
 	  || !_bfd_elf_add_dynamic_entry (info, DT_VX_WRS_TLS_DATA_SIZE, 0)
 	  || !_bfd_elf_add_dynamic_entry (info, DT_VX_WRS_TLS_DATA_ALIGN, 0))
 	return false;
     }
-  if (bfd_get_section_by_name (output_bfd, ".tls_vars"))
+  if (bfd_get_section_by_name (info->output_bfd, ".tls_vars"))
     {
       if (!_bfd_elf_add_dynamic_entry (info, DT_VX_WRS_TLS_VARS_START, 0)
 	  || !_bfd_elf_add_dynamic_entry (info, DT_VX_WRS_TLS_VARS_SIZE, 0))
@@ -302,14 +302,12 @@ elf_vxworks_finish_dynamic_entry (bfd *output_bfd, Elf_Internal_Dyn *dyn)
 /* Add dynamic tags.  */
 
 bool
-_bfd_elf_maybe_vxworks_add_dynamic_tags (bfd *output_bfd,
-					 struct bfd_link_info *info,
+_bfd_elf_maybe_vxworks_add_dynamic_tags (struct bfd_link_info *info,
 					 bool need_dynamic_reloc)
 {
   struct elf_link_hash_table *htab = elf_hash_table (info);
-  return (_bfd_elf_add_dynamic_tags (output_bfd, info,
-				     need_dynamic_reloc)
+  return (_bfd_elf_add_dynamic_tags (info, need_dynamic_reloc)
 	  && (!htab->dynamic_sections_created
 	      || htab->target_os != is_vxworks
-	      || elf_vxworks_add_dynamic_entries (output_bfd, info)));
+	      || elf_vxworks_add_dynamic_entries (info)));
 }
diff --git a/bfd/elf-vxworks.h b/bfd/elf-vxworks.h
index bcf55bcfdf4..992e238f132 100644
--- a/bfd/elf-vxworks.h
+++ b/bfd/elf-vxworks.h
@@ -35,16 +35,16 @@ bool elf_vxworks_final_write_processing
 bool elf_vxworks_create_dynamic_sections
   (bfd *, struct bfd_link_info *, asection **) ATTRIBUTE_HIDDEN;
 bool elf_vxworks_add_dynamic_entries
-  (bfd *, struct bfd_link_info *) ATTRIBUTE_HIDDEN;
+  (struct bfd_link_info *) ATTRIBUTE_HIDDEN;
 bool elf_vxworks_finish_dynamic_entry
   (bfd *, Elf_Internal_Dyn *) ATTRIBUTE_HIDDEN;
 bool _bfd_elf_maybe_vxworks_add_dynamic_tags
-  (bfd *, struct bfd_link_info *, bool) ATTRIBUTE_HIDDEN;
+  (struct bfd_link_info *, bool) ATTRIBUTE_HIDDEN;
 
 #else /* !OBJ_MAYBE_ELF_VXWORKS */
 
 static inline bool _bfd_elf_maybe_vxworks_add_dynamic_tags (
-  bfd *output_bfd, struct bfd_link_info *info, bool need_dynamic_reloc)
-{ return _bfd_elf_add_dynamic_tags (output_bfd, info, need_dynamic_reloc); }
+  struct bfd_link_info *info, bool need_dynamic_reloc)
+{ return _bfd_elf_add_dynamic_tags (info, need_dynamic_reloc); }
 
 #endif /* OBJ_MAYBE_ELF_VXWORKS */
diff --git a/bfd/elf.c b/bfd/elf.c
index 1c88c379ea0..1e1f09c8bbc 100644
--- a/bfd/elf.c
+++ b/bfd/elf.c
@@ -4455,15 +4455,15 @@ sym_is_global (bfd *abfd, asymbol *sym)
 	  || bfd_is_com_section (bfd_asymbol_section (sym)));
 }
 
-/* Filter global symbols of ABFD to include in the import library.  All
-   SYMCOUNT symbols of ABFD can be examined from their pointers in
+/* Filter global symbols of INFO->OUTPUT_BFD to include in the import
+   library.  SYMCOUNT symbols can be examined from their pointers in
    SYMS.  Pointers of symbols to keep should be stored contiguously at
    the beginning of that array.
 
    Returns the number of symbols to keep.  */
 
 unsigned int
-_bfd_elf_filter_global_symbols (bfd *abfd, struct bfd_link_info *info,
+_bfd_elf_filter_global_symbols (struct bfd_link_info *info,
 				asymbol **syms, long symcount)
 {
   long src_count, dst_count = 0;
@@ -4474,7 +4474,7 @@ _bfd_elf_filter_global_symbols (bfd *abfd, struct bfd_link_info *info,
       char *name = (char *) bfd_asymbol_name (sym);
       struct bfd_link_hash_entry *h;
 
-      if (!sym_is_global (abfd, sym))
+      if (!sym_is_global (info->output_bfd, sym))
 	continue;
 
       h = bfd_link_hash_lookup (info->hash, name, false, false, false);
diff --git a/bfd/elf32-arc.c b/bfd/elf32-arc.c
index cf0bc662790..52037e06508 100644
--- a/bfd/elf32-arc.c
+++ b/bfd/elf32-arc.c
@@ -1432,8 +1432,7 @@ arc_do_relocation (bfd_byte * contents,
    Function : elf_arc_relocate_section
    Brief    : Relocate an arc section, by handling all the relocations
 	     appearing in that section.
-   Args     : output_bfd    : The bfd being written to.
-	      info	    : Link information.
+   Args     : info	    : Link information.
 	      input_bfd     : The input bfd.
 	      input_section : The section being relocated.
 	      contents	    : contents of the section being relocated.
@@ -1443,8 +1442,7 @@ arc_do_relocation (bfd_byte * contents,
 			      corresponding to the st_shndx field of each
 			      local symbol.  */
 static int
-elf_arc_relocate_section (bfd *			  output_bfd,
-			  struct bfd_link_info *  info,
+elf_arc_relocate_section (struct bfd_link_info *  info,
 			  bfd *			  input_bfd,
 			  asection *		  input_section,
 			  bfd_byte *		  contents,
@@ -1631,7 +1629,7 @@ elf_arc_relocate_section (bfd *			  output_bfd,
 	    {
 	      asection *msec;
 	      msec = sec;
-	      rel->r_addend = _bfd_elf_rel_local_sym (output_bfd, sym,
+	      rel->r_addend = _bfd_elf_rel_local_sym (info->output_bfd, sym,
 						      &msec, rel->r_addend);
 	      rel->r_addend -= (sec->output_section->vma
 				+ sec->output_offset
@@ -1697,7 +1695,7 @@ elf_arc_relocate_section (bfd *			  output_bfd,
 
 		  BFD_ASSERT (ah->got_ents);
 		  bfd_vma got_offset = ah->got_ents->offset;
-		  bfd_put_32 (output_bfd, relocation,
+		  bfd_put_32 (info->output_bfd, relocation,
 			      htab->sgot->contents + got_offset);
 		}
 	      if (is_reloc_for_PLT (howto) && h->plt.offset != (bfd_vma) -1)
@@ -1773,7 +1771,7 @@ elf_arc_relocate_section (bfd *			  output_bfd,
 	    = relocate_fix_got_relocs_for_got_info (list,
 						    tls_type_for_reloc (howto),
 						    info,
-						    output_bfd,
+						    info->output_bfd,
 						    r_symndx,
 						    local_syms,
 						    local_sections,
@@ -1784,8 +1782,8 @@ elf_arc_relocate_section (bfd *			  output_bfd,
 	    {
 	      create_got_dynrelocs_for_single_entry (
 		  got_entry_for_type (list,
-				arc_got_entry_type_for_reloc (howto)),
-		  output_bfd, info, NULL);
+				      arc_got_entry_type_for_reloc (howto)),
+		  info->output_bfd, info, NULL);
 	    }
 	}
 
@@ -1816,7 +1814,7 @@ elf_arc_relocate_section (bfd *			  output_bfd,
 
 		BFD_ASSERT (sreloc != NULL);
 
-		outrel.r_offset = _bfd_elf_section_offset (output_bfd,
+		outrel.r_offset = _bfd_elf_section_offset (info->output_bfd,
 							   info,
 							   input_section,
 							   rel->r_offset);
@@ -1872,7 +1870,7 @@ elf_arc_relocate_section (bfd *			  output_bfd,
 		loc += sreloc->reloc_count * sizeof (Elf32_External_Rela);
 		sreloc->reloc_count += 1;
 
-		bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+		bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 
 		if (!relocate)
 		  continue;
@@ -2469,14 +2467,13 @@ elf_arc_adjust_dynamic_symbol (struct bfd_link_info *info,
    Returns  : True/False as the return status.  */
 
 static bool
-elf_arc_finish_dynamic_symbol (bfd * output_bfd,
-			       struct bfd_link_info *info,
+elf_arc_finish_dynamic_symbol (struct bfd_link_info *info,
 			       struct elf_link_hash_entry *h,
 			       Elf_Internal_Sym * sym)
 {
   if (h->plt.offset != (bfd_vma) -1)
     {
-      relocate_plt_for_symbol (output_bfd, info, h);
+      relocate_plt_for_symbol (info->output_bfd, info, h);
 
       if (!h->def_regular)
 	{
@@ -2494,7 +2491,7 @@ elf_arc_finish_dynamic_symbol (bfd * output_bfd,
   struct elf_arc_link_hash_entry *ah =
     (struct elf_arc_link_hash_entry *) h;
   create_got_dynrelocs_for_got_info (&ah->got_ents,
-				     output_bfd,
+				     info->output_bfd,
 				     info,
 				     h);
 
@@ -2523,7 +2520,7 @@ elf_arc_finish_dynamic_symbol (bfd * output_bfd,
       BFD_ASSERT (h->dynindx != -1);
       rel.r_info = ELF32_R_INFO (h->dynindx, R_ARC_COPY);
 
-      bfd_elf32_swap_reloca_out (output_bfd, &rel, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rel, loc);
     }
 
   /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute.  */
@@ -2579,15 +2576,10 @@ arc_create_forced_local_got_entries_for_tls (struct bfd_hash_entry *bh,
 
 /* Function :  elf_arc_finish_dynamic_sections
    Brief    :  Finish up the dynamic sections handling.
-   Args     :  output_bfd :
-	       info	  :
-	       h	  :
-	       sym	  :
    Returns  : True/False as the return status.  */
 
 static bool
-elf_arc_finish_dynamic_sections (bfd * output_bfd,
-				 struct bfd_link_info *info,
+elf_arc_finish_dynamic_sections (struct bfd_link_info *info,
 				 bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   struct elf_link_hash_table *htab = elf_hash_table (info);
@@ -2673,12 +2665,12 @@ elf_arc_finish_dynamic_sections (bfd * output_bfd,
 	    }
 
 	  if (do_it)
-	    bfd_elf32_swap_dyn_out (output_bfd, &internal_dyn, dyncon);
+	    bfd_elf32_swap_dyn_out (info->output_bfd, &internal_dyn, dyncon);
 	}
 
       if (htab->splt->size > 0)
 	{
-	  relocate_plt_for_entry (output_bfd, info);
+	  relocate_plt_for_entry (info->output_bfd, info);
 	}
 
       /* TODO: Validate this.  */
@@ -2700,19 +2692,19 @@ elf_arc_finish_dynamic_sections (bfd * output_bfd,
 	  asection *sec = h->root.u.def.section;
 
 	  if (sdyn == NULL)
-	    bfd_put_32 (output_bfd, (bfd_vma) 0,
+	    bfd_put_32 (info->output_bfd, 0,
 			sec->contents);
 	  else
-	    bfd_put_32 (output_bfd,
+	    bfd_put_32 (info->output_bfd,
 			sdyn->output_section->vma + sdyn->output_offset,
 			sec->contents);
-	  bfd_put_32 (output_bfd, (bfd_vma) 0, sec->contents + 4);
-	  bfd_put_32 (output_bfd, (bfd_vma) 0, sec->contents + 8);
+	  bfd_put_32 (info->output_bfd, 0, sec->contents + 4);
+	  bfd_put_32 (info->output_bfd, 0, sec->contents + 8);
 	}
     }
 
   struct obfd_info_group group;
-  group.output_bfd = output_bfd;
+  group.output_bfd = info->output_bfd;
   group.info = info;
   bfd_hash_traverse (&info->hash->table,
 		     arc_create_forced_local_got_entries_for_tls, &group);
@@ -2729,8 +2721,7 @@ elf_arc_finish_dynamic_sections (bfd * output_bfd,
 
 /* Set the sizes of the dynamic sections.  */
 static bool
-elf_arc_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-			    struct bfd_link_info *info)
+elf_arc_late_size_sections (struct bfd_link_info *info)
 {
   bfd *dynobj;
   asection *s;
@@ -2819,7 +2810,7 @@ elf_arc_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
       s->alloced = 1;
     }
 
-  return _bfd_elf_add_dynamic_tags (output_bfd, info, relocs_exist);
+  return _bfd_elf_add_dynamic_tags (info, relocs_exist);
 }
 
 
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index 0447d60de7b..63b908462b1 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -13011,8 +13011,7 @@ arm_add_to_rel (bfd *		   abfd,
 /* Relocate an ARM ELF section.  */
 
 static int
-elf32_arm_relocate_section (bfd *		   output_bfd,
-			    struct bfd_link_info * info,
+elf32_arm_relocate_section (struct bfd_link_info * info,
 			    bfd *		   input_bfd,
 			    asection *		   input_section,
 			    bfd_byte *		   contents,
@@ -13152,9 +13151,9 @@ elf32_arm_relocate_section (bfd *		   output_bfd,
 		    }
 
 		  msec = sec;
-		  addend =
-		    _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
-		    - relocation;
+		  addend = (_bfd_elf_rel_local_sym (info->output_bfd,
+						    sym, &msec, addend)
+			    - relocation);
 		  addend += msec->output_section->vma + msec->output_offset;
 
 		  /* Cases here must match those in the preceding
@@ -13187,7 +13186,8 @@ elf32_arm_relocate_section (bfd *		   output_bfd,
 		}
 	    }
 	  else
-	    relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	    relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						  sym, &sec, rel);
 	}
       else
 	{
@@ -13279,7 +13279,7 @@ elf32_arm_relocate_section (bfd *		   output_bfd,
 	    h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
 	      : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
 
-	  r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
+	  r = elf32_arm_final_link_relocate (howto, input_bfd, info->output_bfd,
 					     input_section, contents, rel,
 					     relocation, info, sec, name,
 					     sym_type, branch_type, h,
@@ -13293,7 +13293,7 @@ elf32_arm_relocate_section (bfd *		   output_bfd,
       if (unresolved_reloc
 	  && !((input_section->flags & SEC_DEBUGGING) != 0
 	       && h->def_dynamic)
-	  && _bfd_elf_section_offset (output_bfd, info, input_section,
+	  && _bfd_elf_section_offset (info->output_bfd, info, input_section,
 				      rel->r_offset) != (bfd_vma) -1)
 	{
 	  _bfd_error_handler
@@ -16625,8 +16625,7 @@ bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
 /* Set the sizes of the dynamic sections.  */
 
 static bool
-elf32_arm_late_size_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
-			      struct bfd_link_info * info)
+elf32_arm_late_size_sections (struct bfd_link_info *info)
 {
   bfd * dynobj;
   asection * s;
@@ -16878,7 +16877,9 @@ elf32_arm_late_size_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
 		  && (local_iplt == NULL
 		      || local_iplt->arm.noncall_refcount == 0))
 		elf32_arm_allocate_irelocs (info, srel, 1);
-	      else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC || htab->fdpic_p)
+	      else if (bfd_link_pic (info)
+		       || (info->output_bfd->flags & DYNAMIC) != 0
+		       || htab->fdpic_p)
 		{
 		  if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC)))
 		    elf32_arm_allocate_dynrelocs (info, srel, 1);
@@ -17039,15 +17040,14 @@ elf32_arm_late_size_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
       s->alloced = 1;
     }
 
-  return _bfd_elf_maybe_vxworks_add_dynamic_tags (output_bfd, info,
-						  relocs);
+  return _bfd_elf_maybe_vxworks_add_dynamic_tags (info, relocs);
 }
 
 /* Size sections even though they're not dynamic.  We use it to setup
    _TLS_MODULE_BASE_, if needed.  */
 
 static bool
-elf32_arm_early_size_sections (bfd *output_bfd, struct bfd_link_info *info)
+elf32_arm_early_size_sections (struct bfd_link_info *info)
 {
   asection *tls_sec;
   struct elf32_arm_link_hash_table *htab;
@@ -17069,10 +17069,10 @@ elf32_arm_early_size_sections (bfd *output_bfd, struct bfd_link_info *info)
       if (tlsbase)
 	{
 	  struct bfd_link_hash_entry *bh = NULL;
-	  elf_backend_data *bed = get_elf_backend_data (output_bfd);
+	  elf_backend_data *bed = get_elf_backend_data (info->output_bfd);
 
 	  if (!(_bfd_generic_link_add_one_symbol
-		(info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
+		(info, info->output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
 		 tls_sec, 0, NULL, false,
 		 bed->collect, &bh)))
 	    return false;
@@ -17086,8 +17086,7 @@ elf32_arm_early_size_sections (bfd *output_bfd, struct bfd_link_info *info)
     }
 
   if (htab->fdpic_p && !bfd_link_relocatable (info)
-      && !bfd_elf_stack_segment_size (output_bfd, info,
-				      "__stacksize", DEFAULT_STACK_SIZE))
+      && !bfd_elf_stack_segment_size (info, "__stacksize", DEFAULT_STACK_SIZE))
     return false;
 
   return true;
@@ -17097,8 +17096,7 @@ elf32_arm_early_size_sections (bfd *output_bfd, struct bfd_link_info *info)
    dynamic sections here.  */
 
 static bool
-elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
-				 struct bfd_link_info * info,
+elf32_arm_finish_dynamic_symbol (struct bfd_link_info * info,
 				 struct elf_link_hash_entry * h,
 				 Elf_Internal_Sym * sym)
 {
@@ -17114,8 +17112,8 @@ elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
       if (!eh->is_iplt)
 	{
 	  BFD_ASSERT (h->dynindx != -1);
-	  if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
-					      h->dynindx, 0))
+	  if (! elf32_arm_populate_plt_entry (info->output_bfd, info, &h->plt,
+					      &eh->plt, h->dynindx, 0))
 	    return false;
 	}
 
@@ -17142,7 +17140,7 @@ elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
 	  sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
 	  ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
 	  sym->st_shndx = (_bfd_elf_section_from_bfd_section
-			   (output_bfd, htab->root.iplt->output_section));
+			   (info->output_bfd, htab->root.iplt->output_section));
 	  sym->st_value = (h->plt.offset
 			   + htab->root.iplt->output_section->vma
 			   + htab->root.iplt->output_offset);
@@ -17168,7 +17166,7 @@ elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
 	s = htab->root.sreldynrelro;
       else
 	s = htab->root.srelbss;
-      elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
+      elf32_arm_add_dynreloc (info->output_bfd, info, s, &rel);
     }
 
   /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute.  On VxWorks,
@@ -17204,7 +17202,7 @@ arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
 /* Finish up the dynamic sections.  */
 
 static bool
-elf32_arm_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
+elf32_arm_finish_dynamic_sections (struct bfd_link_info *info,
 				   bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   bfd * dynobj;
@@ -17250,8 +17248,8 @@ elf32_arm_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
 	    default:
 #ifdef OBJ_MAYBE_ELF_VXWORKS
 	      if (htab->root.target_os == is_vxworks
-		  && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
-		bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+		  && elf_vxworks_finish_dynamic_entry (info->output_bfd, &dyn))
+		bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 #endif /* OBJ_MAYBE_ELF_VXWORKS */
 	      break;
 
@@ -17278,14 +17276,14 @@ elf32_arm_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
 		  return false;
 		}
 	      dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    case DT_PLTRELSZ:
 	      s = htab->root.srelplt;
 	      BFD_ASSERT (s != NULL);
 	      dyn.d_un.d_val = s->size;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    case DT_RELSZ:
@@ -17298,14 +17296,14 @@ elf32_arm_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
 	      s = htab->root.splt;
 	      dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
 				+ htab->root.tlsdesc_plt);
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    case DT_TLSDESC_GOT:
 	      s = htab->root.sgot;
 	      dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
 				+ htab->root.tlsdesc_got);
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	      /* Set the bottom bit of DT_INIT/FINI if the
@@ -17329,7 +17327,7 @@ elf32_arm_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
 			 == ST_BRANCH_TO_THUMB)
 		    {
 		      dyn.d_un.d_val |= 1;
-		      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+		      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 		    }
 		}
 	      break;
@@ -17354,19 +17352,19 @@ elf32_arm_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
 	      Elf_Internal_Rela rel;
 
 	      plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
-	      put_arm_insn (htab, output_bfd, plt0_entry[0],
+	      put_arm_insn (htab, info->output_bfd, plt0_entry[0],
 			    splt->contents + 0);
-	      put_arm_insn (htab, output_bfd, plt0_entry[1],
+	      put_arm_insn (htab, info->output_bfd, plt0_entry[1],
 			    splt->contents + 4);
-	      put_arm_insn (htab, output_bfd, plt0_entry[2],
+	      put_arm_insn (htab, info->output_bfd, plt0_entry[2],
 			    splt->contents + 8);
-	      bfd_put_32 (output_bfd, got_address, splt->contents + 12);
+	      bfd_put_32 (info->output_bfd, got_address, splt->contents + 12);
 
 	      /* Generate a relocation for _GLOBAL_OFFSET_TABLE_.  */
 	      rel.r_offset = plt_address + 12;
 	      rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
 	      rel.r_addend = 0;
-	      SWAP_RELOC_OUT (htab) (output_bfd, &rel,
+	      SWAP_RELOC_OUT (htab) (info->output_bfd, &rel,
 				     htab->srelplt2->contents);
 	    }
 	  else if (using_thumb_only (htab))
@@ -17374,42 +17372,45 @@ elf32_arm_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
 	      got_displacement = got_address - (plt_address + 12);
 
 	      plt0_entry = elf32_thumb2_plt0_entry;
-	      put_arm_insn (htab, output_bfd, plt0_entry[0],
+	      put_arm_insn (htab, info->output_bfd, plt0_entry[0],
 			    splt->contents + 0);
-	      put_arm_insn (htab, output_bfd, plt0_entry[1],
+	      put_arm_insn (htab, info->output_bfd, plt0_entry[1],
 			    splt->contents + 4);
-	      put_arm_insn (htab, output_bfd, plt0_entry[2],
+	      put_arm_insn (htab, info->output_bfd, plt0_entry[2],
 			    splt->contents + 8);
 
-	      bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
+	      bfd_put_32 (info->output_bfd, got_displacement,
+			  splt->contents + 12);
 	    }
 	  else
 	    {
 	      got_displacement = got_address - (plt_address + 16);
 
 	      plt0_entry = elf32_arm_plt0_entry;
-	      put_arm_insn (htab, output_bfd, plt0_entry[0],
+	      put_arm_insn (htab, info->output_bfd, plt0_entry[0],
 			    splt->contents + 0);
-	      put_arm_insn (htab, output_bfd, plt0_entry[1],
+	      put_arm_insn (htab, info->output_bfd, plt0_entry[1],
 			    splt->contents + 4);
-	      put_arm_insn (htab, output_bfd, plt0_entry[2],
+	      put_arm_insn (htab, info->output_bfd, plt0_entry[2],
 			    splt->contents + 8);
-	      put_arm_insn (htab, output_bfd, plt0_entry[3],
+	      put_arm_insn (htab, info->output_bfd, plt0_entry[3],
 			    splt->contents + 12);
 
 #ifdef FOUR_WORD_PLT
 	      /* The displacement value goes in the otherwise-unused
 		 last word of the second entry.  */
-	      bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
+	      bfd_put_32 (info->output_bfd, got_displacement,
+			  splt->contents + 28);
 #else
-	      bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
+	      bfd_put_32 (info->output_bfd, got_displacement,
+			  splt->contents + 16);
 #endif
 	    }
 	}
 
       /* UnixWare sets the entsize of .plt to 4, although that doesn't
 	 really seem like the right value.  */
-      if (splt->output_section->owner == output_bfd)
+      if (splt->output_section->owner == info->output_bfd)
 	elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
 
       if (htab->root.tlsdesc_plt)
@@ -17421,16 +17422,16 @@ elf32_arm_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
 	  bfd_vma plt_address
 	    = splt->output_section->vma + splt->output_offset;
 
-	  arm_put_trampoline (htab, output_bfd,
+	  arm_put_trampoline (htab, info->output_bfd,
 			      splt->contents + htab->root.tlsdesc_plt,
 			      dl_tlsdesc_lazy_trampoline, 6);
 
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 		      gotplt_address + htab->root.tlsdesc_got
 		      - (plt_address + htab->root.tlsdesc_plt)
 		      - dl_tlsdesc_lazy_trampoline[6],
 		      splt->contents + htab->root.tlsdesc_plt + 24);
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 		      got_address - (plt_address + htab->root.tlsdesc_plt)
 		      - dl_tlsdesc_lazy_trampoline[7],
 		      splt->contents + htab->root.tlsdesc_plt + 24 + 4);
@@ -17438,11 +17439,11 @@ elf32_arm_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
 
       if (htab->tls_trampoline)
 	{
-	  arm_put_trampoline (htab, output_bfd,
+	  arm_put_trampoline (htab, info->output_bfd,
 			      splt->contents + htab->tls_trampoline,
 			      tls_trampoline, 3);
 #ifdef FOUR_WORD_PLT
-	  bfd_put_32 (output_bfd, 0x00000000,
+	  bfd_put_32 (info->output_bfd, 0x00000000,
 		      splt->contents + htab->tls_trampoline + 12);
 #endif
 	}
@@ -17464,14 +17465,14 @@ elf32_arm_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
 	    {
 	      Elf_Internal_Rela rel;
 
-	      SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
+	      SWAP_RELOC_IN (htab) (info->output_bfd, p, &rel);
 	      rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
-	      SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
+	      SWAP_RELOC_OUT (htab) (info->output_bfd, &rel, p);
 	      p += RELOC_SIZE (htab);
 
-	      SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
+	      SWAP_RELOC_IN (htab) (info->output_bfd, p, &rel);
 	      rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
-	      SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
+	      SWAP_RELOC_OUT (htab) (info->output_bfd, &rel, p);
 	      p += RELOC_SIZE (htab);
 	    }
 	}
@@ -17483,13 +17484,13 @@ elf32_arm_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
       if (sgot->size > 0)
 	{
 	  if (sdyn == NULL)
-	    bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
+	    bfd_put_32 (info->output_bfd, 0, sgot->contents);
 	  else
-	    bfd_put_32 (output_bfd,
+	    bfd_put_32 (info->output_bfd,
 			sdyn->output_section->vma + sdyn->output_offset,
 			sgot->contents);
-	  bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
-	  bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
+	  bfd_put_32 (info->output_bfd, 0, sgot->contents + 4);
+	  bfd_put_32 (info->output_bfd, 0, sgot->contents + 8);
 	}
 
       elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
@@ -17504,7 +17505,7 @@ elf32_arm_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
 	+ hgot->root.u.def.section->output_section->vma
 	+ hgot->root.u.def.section->output_offset;
 
-      arm_elf_add_rofixup (output_bfd, htab->srofixup, got_value);
+      arm_elf_add_rofixup (info->output_bfd, htab->srofixup, got_value);
 
       /* Make sure we allocated and generated the same number of fixups.  */
       BFD_ASSERT (htab->srofixup->reloc_count * 4 == htab->srofixup->size);
@@ -17572,7 +17573,7 @@ elf32_arm_init_file_header (bfd *abfd, struct bfd_link_info *link_info)
 }
 
 static enum elf_reloc_type_class
-elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
+elf32_arm_reloc_type_class (const struct bfd_link_info *info,
 			    const asection *rel_sec ATTRIBUTE_UNUSED,
 			    const Elf_Internal_Rela *rela)
 {
@@ -18010,8 +18011,7 @@ arm_map_one_stub (struct bfd_hash_entry * gen_entry,
    $d.  */
 
 static bool
-elf32_arm_output_arch_local_syms (bfd *output_bfd,
-				  struct bfd_link_info *info,
+elf32_arm_output_arch_local_syms (struct bfd_link_info *info,
 				  void *flaginfo,
 				  int (*func) (void *, const char *,
 					       Elf_Internal_Sym *,
@@ -18062,7 +18062,7 @@ elf32_arm_output_arch_local_syms (bfd *output_bfd,
 		&& (osi.sec->flags & SEC_EXCLUDE) == 0)
 	      {
 		osi.sec_shndx = _bfd_elf_section_from_bfd_section
-		  (output_bfd, osi.sec->output_section);
+		  (info->output_bfd, osi.sec->output_section);
 		if (osi.sec_shndx != (int)SHN_BAD)
 		  elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
 	      }
@@ -18076,7 +18076,7 @@ elf32_arm_output_arch_local_syms (bfd *output_bfd,
 					ARM2THUMB_GLUE_SECTION_NAME);
 
       osi.sec_shndx = _bfd_elf_section_from_bfd_section
-	  (output_bfd, osi.sec->output_section);
+	  (info->output_bfd, osi.sec->output_section);
       if (bfd_link_pic (info)
 	  || htab->pic_veneer)
 	size = ARM2THUMB_PIC_GLUE_SIZE;
@@ -18099,7 +18099,7 @@ elf32_arm_output_arch_local_syms (bfd *output_bfd,
 					THUMB2ARM_GLUE_SECTION_NAME);
 
       osi.sec_shndx = _bfd_elf_section_from_bfd_section
-	  (output_bfd, osi.sec->output_section);
+	  (info->output_bfd, osi.sec->output_section);
       size = THUMB2ARM_GLUE_SIZE;
 
       for (offset = 0; offset < htab->thumb_glue_size; offset += size)
@@ -18116,7 +18116,7 @@ elf32_arm_output_arch_local_syms (bfd *output_bfd,
 					ARM_BX_GLUE_SECTION_NAME);
 
       osi.sec_shndx = _bfd_elf_section_from_bfd_section
-	  (output_bfd, osi.sec->output_section);
+	  (info->output_bfd, osi.sec->output_section);
 
       elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
     }
@@ -18137,7 +18137,7 @@ elf32_arm_output_arch_local_syms (bfd *output_bfd,
 	  osi.sec = stub_sec;
 
 	  osi.sec_shndx = _bfd_elf_section_from_bfd_section
-	    (output_bfd, osi.sec->output_section);
+	    (info->output_bfd, osi.sec->output_section);
 
 	  bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
 	}
@@ -18148,7 +18148,7 @@ elf32_arm_output_arch_local_syms (bfd *output_bfd,
     {
       osi.sec = htab->root.splt;
       osi.sec_shndx = (_bfd_elf_section_from_bfd_section
-		       (output_bfd, osi.sec->output_section));
+		       (info->output_bfd, osi.sec->output_section));
 
       /* Output mapping symbols for the plt header.  */
       if (htab->root.target_os == is_vxworks)
@@ -18243,16 +18243,15 @@ elf32_arm_output_arch_local_syms (bfd *output_bfd,
   return true;
 }
 
-/* Filter normal symbols of CMSE entry functions of ABFD to include in
-   the import library.  All SYMCOUNT symbols of ABFD can be examined
-   from their pointers in SYMS.  Pointers of symbols to keep should be
-   stored continuously at the beginning of that array.
+/* Filter normal symbols of CMSE entry functions to include in the
+   import library.  SYMCOUNT symbols can be examined from their
+   pointers in SYMS.  Pointers of symbols to keep should be stored
+   continuously at the beginning of that array.
 
    Returns the number of symbols to keep.  */
 
 static unsigned int
-elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
-			       struct bfd_link_info *info,
+elf32_arm_filter_cmse_symbols (struct bfd_link_info *info,
 			       asymbol **syms, long symcount)
 {
   size_t maxnamelen;
@@ -18311,16 +18310,15 @@ elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
   return dst_count;
 }
 
-/* Filter symbols of ABFD to include in the import library.  All
-   SYMCOUNT symbols of ABFD can be examined from their pointers in
-   SYMS.  Pointers of symbols to keep should be stored continuously at
+/* Filter symbols of INFO->OUTPUT_BFD to include in the import library.
+   SYMCOUNT symbols can be examined from their pointers in SYMS.
+   Pointers of symbols to keep should be stored continuously at
    the beginning of that array.
 
    Returns the number of symbols to keep.  */
 
 static unsigned int
-elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
-				 struct bfd_link_info *info,
+elf32_arm_filter_implib_symbols (struct bfd_link_info *info,
 				 asymbol **syms, long symcount)
 {
   struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
@@ -18330,9 +18328,9 @@ elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
      library to be a relocatable object file.  */
   BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
   if (globals->cmse_implib)
-    return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
+    return elf32_arm_filter_cmse_symbols (info, syms, symcount);
   else
-    return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
+    return _bfd_elf_filter_global_symbols (info, syms, symcount);
 }
 
 /* Allocate target specific section data.  */
@@ -20294,10 +20292,9 @@ elf32_arm_fdpic_link_hash_table_create (bfd *abfd)
 /* We need dynamic symbols for every section, since segments can
    relocate independently.  */
 static bool
-elf32_arm_fdpic_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
-				    struct bfd_link_info *info
-				    ATTRIBUTE_UNUSED,
-				    asection *p ATTRIBUTE_UNUSED)
+elf32_arm_fdpic_omit_section_dynsym (struct bfd_link_info *info
+				     ATTRIBUTE_UNUSED,
+				     asection *p ATTRIBUTE_UNUSED)
 {
   switch (elf_section_data (p)->this_hdr.sh_type)
     {
diff --git a/bfd/elf32-avr.c b/bfd/elf32-avr.c
index c4118522601..ebdd19b4510 100644
--- a/bfd/elf32-avr.c
+++ b/bfd/elf32-avr.c
@@ -1409,8 +1409,7 @@ avr_final_link_relocate (reloc_howto_type *		    howto,
 /* Relocate an AVR ELF section.  */
 
 static int
-elf32_avr_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
-			    struct bfd_link_info *info,
+elf32_avr_relocate_section (struct bfd_link_info *info,
 			    bfd *input_bfd,
 			    asection *input_section,
 			    bfd_byte *contents,
@@ -1454,7 +1453,8 @@ elf32_avr_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections [r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 
 	  name = bfd_elf_string_from_elf_section
 	    (input_bfd, symtab_hdr->sh_link, sym->st_name);
@@ -3269,7 +3269,7 @@ elf32_avr_get_relocated_section_contents (bfd *output_bfd,
 	  *secpp = isec;
 	}
 
-      if (! elf32_avr_relocate_section (output_bfd, link_info, input_bfd,
+      if (! elf32_avr_relocate_section (link_info, input_bfd,
 					input_section, data, internal_relocs,
 					isymbuf, sections))
 	goto error_return;
diff --git a/bfd/elf32-bfin.c b/bfd/elf32-bfin.c
index 940fdc8c7a9..8be69ead976 100644
--- a/bfd/elf32-bfin.c
+++ b/bfd/elf32-bfin.c
@@ -1360,8 +1360,7 @@ bfin_final_link_relocate (Elf_Internal_Rela *rel, reloc_howto_type *howto,
 }
 
 static int
-bfin_relocate_section (bfd * output_bfd,
-		       struct bfd_link_info *info,
+bfin_relocate_section (struct bfd_link_info *info,
 		       bfd * input_bfd,
 		       asection * input_section,
 		       bfd_byte * contents,
@@ -1425,7 +1424,8 @@ bfin_relocate_section (bfd * output_bfd,
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections[r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 	}
       else
 	{
@@ -1506,7 +1506,7 @@ bfin_relocate_section (bfd * output_bfd,
 		      off &= ~1;
 		    else
 		      {
-			bfd_put_32 (output_bfd, relocation,
+			bfd_put_32 (info->output_bfd, relocation,
 				    sgot->contents + off);
 			h->got.offset |= 1;
 		      }
@@ -1527,7 +1527,8 @@ bfin_relocate_section (bfd * output_bfd,
 		  off &= ~1;
 		else
 		  {
-		    bfd_put_32 (output_bfd, relocation, sgot->contents + off);
+		    bfd_put_32 (info->output_bfd, relocation,
+				sgot->contents + off);
 
 		    if (bfd_link_pic (info))
 		      {
@@ -1546,7 +1547,8 @@ bfin_relocate_section (bfd * output_bfd,
 			loc = s->contents;
 			loc +=
 			  s->reloc_count++ * sizeof (Elf32_External_Rela);
-			bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+			bfd_elf32_swap_reloca_out (info->output_bfd,
+						   &outrel, loc);
 		      }
 
 		    local_got_offsets[r_symndx] |= 1;
@@ -1573,7 +1575,7 @@ bfin_relocate_section (bfd * output_bfd,
 	 not process them.  */
       if (unresolved_reloc
 	  && !((input_section->flags & SEC_DEBUGGING) != 0 && h->def_dynamic)
-	  && _bfd_elf_section_offset (output_bfd, info, input_section,
+	  && _bfd_elf_section_offset (info->output_bfd, info, input_section,
 				      rel->r_offset) != (bfd_vma) -1)
 	r = bfd_reloc_undefined;
 
@@ -2483,8 +2485,7 @@ _bfinfdpic_emit_got_relocs_plt_entries (struct bfinfdpic_relocs_info *entry,
    accordingly.  */
 
 static int
-bfinfdpic_relocate_section (bfd * output_bfd,
-			    struct bfd_link_info *info,
+bfinfdpic_relocate_section (struct bfd_link_info *info,
 			    bfd * input_bfd,
 			    asection * input_section,
 			    bfd_byte * contents,
@@ -2504,16 +2505,17 @@ bfinfdpic_relocate_section (bfd * output_bfd,
   sym_hashes = elf_sym_hashes (input_bfd);
   relend     = relocs + input_section->reloc_count;
 
-  isec_segment = _bfinfdpic_osec_to_segment (output_bfd,
+  isec_segment = _bfinfdpic_osec_to_segment (info->output_bfd,
 					     input_section->output_section);
-  if (IS_FDPIC (output_bfd) && bfinfdpic_got_section (info))
-    got_segment = _bfinfdpic_osec_to_segment (output_bfd,
+  if (IS_FDPIC (info->output_bfd) && bfinfdpic_got_section (info))
+    got_segment = _bfinfdpic_osec_to_segment (info->output_bfd,
 					      bfinfdpic_got_section (info)
 					      ->output_section);
   else
     got_segment = -1;
-  if (IS_FDPIC (output_bfd) && elf_hash_table (info)->dynamic_sections_created)
-    plt_segment = _bfinfdpic_osec_to_segment (output_bfd,
+  if (IS_FDPIC (info->output_bfd)
+      && elf_hash_table (info)->dynamic_sections_created)
+    plt_segment = _bfinfdpic_osec_to_segment (info->output_bfd,
 					      bfinfdpic_plt_section (info)
 					      ->output_section);
   else
@@ -2557,7 +2559,8 @@ bfinfdpic_relocate_section (bfd * output_bfd,
 	{
 	  sym = local_syms + r_symndx;
 	  osec = sec = local_sections [r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 
 	  name = bfd_elf_string_from_elf_section
 	    (input_bfd, symtab_hdr->sh_link, sym->st_name);
@@ -2597,7 +2600,7 @@ bfinfdpic_relocate_section (bfd * output_bfd,
 	case R_BFIN_PCREL24:
 	case R_BFIN_PCREL24_JUMP_L:
 	case R_BFIN_BYTE4_DATA:
-	  if (! IS_FDPIC (output_bfd))
+	  if (! IS_FDPIC (info->output_bfd))
 	    goto non_fdpic;
 	  /* Fall through.  */
 
@@ -2632,8 +2635,8 @@ bfinfdpic_relocate_section (bfd * output_bfd,
 	  if (! picrel)
 	    return false;
 
-	  if (!_bfinfdpic_emit_got_relocs_plt_entries (picrel, output_bfd, info,
-						       osec, sym,
+	  if (!_bfinfdpic_emit_got_relocs_plt_entries (picrel, info->output_bfd,
+						       info, osec, sym,
 						       rel->r_addend))
 	    {
 	      _bfd_error_handler
@@ -2651,7 +2654,7 @@ bfinfdpic_relocate_section (bfd * output_bfd,
 	non_fdpic:
 	  picrel = NULL;
 	  if (h && ! BFINFDPIC_SYM_LOCAL (info, h)
-	      && _bfd_elf_section_offset (output_bfd, info, input_section,
+	      && _bfd_elf_section_offset (info->output_bfd, info, input_section,
 					  rel->r_offset) != (bfd_vma) -1)
 	    {
 	      info->callbacks->warning
@@ -2667,7 +2670,7 @@ bfinfdpic_relocate_section (bfd * output_bfd,
 	case R_BFIN_PCREL24:
 	case R_BFIN_PCREL24_JUMP_L:
 	  check_segment[0] = isec_segment;
-	  if (! IS_FDPIC (output_bfd))
+	  if (! IS_FDPIC (info->output_bfd))
 	    check_segment[1] = isec_segment;
 	  else if (picrel->plt)
 	    {
@@ -2685,7 +2688,8 @@ bfinfdpic_relocate_section (bfd * output_bfd,
 	    check_segment[1] = check_segment[0];
 	  else
 	    check_segment[1] = sec
-	      ? _bfinfdpic_osec_to_segment (output_bfd, sec->output_section)
+	      ? _bfinfdpic_osec_to_segment (info->output_bfd,
+					    sec->output_section)
 	      : (unsigned)-1;
 	  break;
 
@@ -2711,7 +2715,7 @@ bfinfdpic_relocate_section (bfd * output_bfd,
 	    + bfinfdpic_got_initial_offset (info);
 	  check_segment[0] = got_segment;
 	  check_segment[1] = sec
-	    ? _bfinfdpic_osec_to_segment (output_bfd, sec->output_section)
+	    ? _bfinfdpic_osec_to_segment (info->output_bfd, sec->output_section)
 	    : (unsigned)-1;
 	  break;
 
@@ -2787,7 +2791,7 @@ bfinfdpic_relocate_section (bfd * output_bfd,
 		      if ((bfd_section_flags (input_section->output_section)
 			   & (SEC_ALLOC | SEC_LOAD)) == (SEC_ALLOC | SEC_LOAD))
 			{
-			  if (_bfinfdpic_osec_readonly_p (output_bfd,
+			  if (_bfinfdpic_osec_readonly_p (info->output_bfd,
 							  input_section
 							  ->output_section))
 			    {
@@ -2798,12 +2802,13 @@ bfinfdpic_relocate_section (bfd * output_bfd,
 			      return false;
 			    }
 
-			  offset = _bfd_elf_section_offset
-			    (output_bfd, info,
-			     input_section, rel->r_offset);
+			  offset = _bfd_elf_section_offset (info->output_bfd,
+							    info,
+							    input_section,
+							    rel->r_offset);
 
 			  if (offset != (bfd_vma)-1)
-			    _bfinfdpic_add_rofixup (output_bfd,
+			    _bfinfdpic_add_rofixup (info->output_bfd,
 						    bfinfdpic_gotfixup_section
 						    (info),
 						    offset + input_section
@@ -2817,7 +2822,7 @@ bfinfdpic_relocate_section (bfd * output_bfd,
 		    {
 		      bfd_vma offset;
 
-		      if (_bfinfdpic_osec_readonly_p (output_bfd,
+		      if (_bfinfdpic_osec_readonly_p (info->output_bfd,
 						      input_section
 						      ->output_section))
 			{
@@ -2827,11 +2832,12 @@ bfinfdpic_relocate_section (bfd * output_bfd,
 			     name, input_bfd, input_section, rel->r_offset);
 			  return false;
 			}
-		      offset = _bfd_elf_section_offset (output_bfd, info,
-							input_section, rel->r_offset);
+		      offset = _bfd_elf_section_offset (info->output_bfd, info,
+							input_section,
+							rel->r_offset);
 
 		      if (offset != (bfd_vma)-1)
-			_bfinfdpic_add_dyn_reloc (output_bfd,
+			_bfinfdpic_add_dyn_reloc (info->output_bfd,
 						  bfinfdpic_gotrel_section (info),
 						  offset + input_section
 						  ->output_section->vma
@@ -2852,7 +2858,7 @@ bfinfdpic_relocate_section (bfd * output_bfd,
 	  break;
 
 	case R_BFIN_BYTE4_DATA:
-	  if (! IS_FDPIC (output_bfd))
+	  if (! IS_FDPIC (info->output_bfd))
 	    {
 	      check_segment[0] = check_segment[1] = -1;
 	      break;
@@ -2863,7 +2869,7 @@ bfinfdpic_relocate_section (bfd * output_bfd,
 	    int dynindx;
 	    bfd_vma addend = rel->r_addend;
 	    bfd_vma offset;
-	    offset = _bfd_elf_section_offset (output_bfd, info,
+	    offset = _bfd_elf_section_offset (info->output_bfd, info,
 					      input_section, rel->r_offset);
 
 	    /* If the symbol is dynamic but binds locally, use
@@ -2908,7 +2914,7 @@ bfinfdpic_relocate_section (bfd * output_bfd,
 		    && (bfd_section_flags (input_section->output_section)
 			& (SEC_ALLOC | SEC_LOAD)) == (SEC_ALLOC | SEC_LOAD))
 		  {
-		    if (_bfinfdpic_osec_readonly_p (output_bfd,
+		    if (_bfinfdpic_osec_readonly_p (info->output_bfd,
 						   input_section
 						   ->output_section))
 		      {
@@ -2922,7 +2928,7 @@ bfinfdpic_relocate_section (bfd * output_bfd,
 		      {
 			if (offset != (bfd_vma)-1)
 			  {
-			    _bfinfdpic_add_rofixup (output_bfd,
+			    _bfinfdpic_add_rofixup (info->output_bfd,
 						    bfinfdpic_gotfixup_section
 						    (info),
 						    offset + input_section
@@ -2932,7 +2938,7 @@ bfinfdpic_relocate_section (bfd * output_bfd,
 
 			    if (r_type == R_BFIN_FUNCDESC_VALUE)
 			      _bfinfdpic_add_rofixup
-				(output_bfd,
+				(info->output_bfd,
 				 bfinfdpic_gotfixup_section (info),
 				 offset + input_section->output_section->vma
 				 + input_section->output_offset + 4, picrel);
@@ -2945,7 +2951,7 @@ bfinfdpic_relocate_section (bfd * output_bfd,
 		if ((bfd_section_flags (input_section->output_section)
 		     & (SEC_ALLOC | SEC_LOAD)) == (SEC_ALLOC | SEC_LOAD))
 		  {
-		    if (_bfinfdpic_osec_readonly_p (output_bfd,
+		    if (_bfinfdpic_osec_readonly_p (info->output_bfd,
 						   input_section
 						   ->output_section))
 		      {
@@ -2957,7 +2963,7 @@ bfinfdpic_relocate_section (bfd * output_bfd,
 		      }
 
 		    if (offset != (bfd_vma)-1)
-		      _bfinfdpic_add_dyn_reloc (output_bfd,
+		      _bfinfdpic_add_dyn_reloc (info->output_bfd,
 						bfinfdpic_gotrel_section (info),
 						offset
 						+ input_section->output_section->vma
@@ -2979,7 +2985,7 @@ bfinfdpic_relocate_section (bfd * output_bfd,
 		   GOT base offset.  */
 		if (bfd_link_pde (info)
 		    && (!h || BFINFDPIC_SYM_LOCAL (info, h)))
-		  bfd_put_32 (output_bfd,
+		  bfd_put_32 (info->output_bfd,
 			      bfinfdpic_got_section (info)->output_section->vma
 			      + bfinfdpic_got_section (info)->output_offset
 			      + bfinfdpic_got_initial_offset (info),
@@ -2991,10 +2997,10 @@ bfinfdpic_relocate_section (bfd * output_bfd,
 		     PLT entries are located, and the low word
 		     contains the offset of the lazy PLT entry entry
 		     point into that section.  */
-		  bfd_put_32 (output_bfd,
+		  bfd_put_32 (info->output_bfd,
 			      h && ! BFINFDPIC_SYM_LOCAL (info, h)
 			      ? 0
-			      : _bfinfdpic_osec_to_segment (output_bfd,
+			      : _bfinfdpic_osec_to_segment (info->output_bfd,
 							    sec
 							    ->output_section),
 			      contents + rel->r_offset + 4);
@@ -3006,12 +3012,12 @@ bfinfdpic_relocate_section (bfd * output_bfd,
 	default:
 	  check_segment[0] = isec_segment;
 	  check_segment[1] = sec
-	    ? _bfinfdpic_osec_to_segment (output_bfd, sec->output_section)
+	    ? _bfinfdpic_osec_to_segment (info->output_bfd, sec->output_section)
 	    : (unsigned)-1;
 	  break;
 	}
 
-      if (check_segment[0] != check_segment[1] && IS_FDPIC (output_bfd))
+      if (check_segment[0] != check_segment[1] && IS_FDPIC (info->output_bfd))
 	{
 #if 1 /* If you take this out, remove the #error from fdpic-static-6.d
 	 in the ld testsuite.  */
@@ -3041,7 +3047,7 @@ bfinfdpic_relocate_section (bfd * output_bfd,
 	       name, input_bfd, input_section, rel->r_offset);
 	  if (!silence_segment_error && bfd_link_pic (info))
 	    return false;
-	  elf_elfheader (output_bfd)->e_flags |= EF_BFIN_PIC;
+	  elf_elfheader (info->output_bfd)->e_flags |= EF_BFIN_PIC;
 	}
 
       switch (r_type)
@@ -3072,7 +3078,7 @@ bfinfdpic_relocate_section (bfd * output_bfd,
 	{
 	case R_BFIN_PCREL24:
 	case R_BFIN_PCREL24_JUMP_L:
-	  if (! IS_FDPIC (output_bfd) || ! picrel->plt)
+	  if (! IS_FDPIC (info->output_bfd) || ! picrel->plt)
 	    break;
 	  /* Fall through.  */
 
@@ -3152,9 +3158,8 @@ bfinfdpic_relocate_section (bfd * output_bfd,
 /* We need dynamic symbols for every section, since segments can
    relocate independently.  */
 static bool
-_bfinfdpic_link_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
-				    struct bfd_link_info *info ATTRIBUTE_UNUSED,
-				    asection *p)
+_bfinfdpic_link_omit_section_dynsym (struct bfd_link_info *info ATTRIBUTE_UNUSED,
+				     asection *p)
 {
   switch (elf_section_data (p)->this_hdr.sh_type)
     {
@@ -4026,8 +4031,7 @@ _bfinfdpic_size_got_plt (bfd *output_bfd,
 /* Set the sizes of the dynamic sections.  */
 
 static bool
-elf32_bfinfdpic_late_size_sections (bfd *output_bfd,
-				    struct bfd_link_info *info)
+elf32_bfinfdpic_late_size_sections (struct bfd_link_info *info)
 {
   struct elf_link_hash_table *htab;
   bfd *dynobj;
@@ -4072,7 +4076,7 @@ elf32_bfinfdpic_late_size_sections (bfd *output_bfd,
      use it if we're doing relaxations.  */
   bfinfdpic_dynamic_got_plt_info (info) = bfd_alloc (dynobj, sizeof (gpinfo.g));
 
-  if (!_bfinfdpic_size_got_plt (output_bfd, &gpinfo))
+  if (!_bfinfdpic_size_got_plt (info->output_bfd, &gpinfo))
       return false;
 
   s = bfd_get_linker_section (dynobj, ".dynbss");
@@ -4083,16 +4087,14 @@ elf32_bfinfdpic_late_size_sections (bfd *output_bfd,
   if (s && s->size == 0)
     s->flags |= SEC_EXCLUDE;
 
-  return _bfd_elf_add_dynamic_tags (output_bfd, info, true);
+  return _bfd_elf_add_dynamic_tags (info, true);
 }
 
 static bool
-elf32_bfinfdpic_early_size_sections (bfd *output_bfd,
-				     struct bfd_link_info *info)
+elf32_bfinfdpic_early_size_sections (struct bfd_link_info *info)
 {
   if (!bfd_link_relocatable (info)
-      && !bfd_elf_stack_segment_size (output_bfd, info,
-				      "__stacksize", DEFAULT_STACK_SIZE))
+      && !bfd_elf_stack_segment_size (info, "__stacksize", DEFAULT_STACK_SIZE))
     return false;
 
   return true;
@@ -4211,8 +4213,7 @@ bfinfdpic_elf_discard_info (bfd *ibfd,
 }
 
 static bool
-elf32_bfinfdpic_finish_dynamic_sections (bfd *output_bfd,
-					 struct bfd_link_info *info,
+elf32_bfinfdpic_finish_dynamic_sections (struct bfd_link_info *info,
 					 bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   bfd *dynobj;
@@ -4239,8 +4240,9 @@ elf32_bfinfdpic_finish_dynamic_sections (bfd *output_bfd,
 	    + hgot->root.u.def.section->output_section->vma
 	    + hgot->root.u.def.section->output_offset;
 
-	  _bfinfdpic_add_rofixup (output_bfd, bfinfdpic_gotfixup_section (info),
-				 got_value, 0);
+	  _bfinfdpic_add_rofixup (info->output_bfd,
+				  bfinfdpic_gotfixup_section (info),
+				  got_value, 0);
 
 	  if (bfinfdpic_gotfixup_section (info)->size
 	      != (bfinfdpic_gotfixup_section (info)->reloc_count * 4))
@@ -4285,19 +4287,19 @@ elf32_bfinfdpic_finish_dynamic_sections (bfd *output_bfd,
 	      dyn.d_un.d_ptr = bfinfdpic_got_section (info)->output_section->vma
 		+ bfinfdpic_got_section (info)->output_offset
 		+ bfinfdpic_got_initial_offset (info);
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    case DT_JMPREL:
 	      dyn.d_un.d_ptr = bfinfdpic_pltrel_section (info)
 		->output_section->vma
 		+ bfinfdpic_pltrel_section (info)->output_offset;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    case DT_PLTRELSZ:
 	      dyn.d_un.d_val = bfinfdpic_pltrel_section (info)->size;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 	    }
 	}
@@ -4342,8 +4344,7 @@ elf32_bfinfdpic_adjust_dynamic_symbol (struct bfd_link_info *info,
 
 static bool
 elf32_bfinfdpic_finish_dynamic_symbol
-(bfd *output_bfd ATTRIBUTE_UNUSED,
- struct bfd_link_info *info ATTRIBUTE_UNUSED,
+(struct bfd_link_info *info ATTRIBUTE_UNUSED,
  struct elf_link_hash_entry *h ATTRIBUTE_UNUSED,
  Elf_Internal_Sym *sym ATTRIBUTE_UNUSED)
 {
@@ -4855,8 +4856,7 @@ bfin_link_hash_table_create (bfd * abfd)
 /* Finish up the dynamic sections.  */
 
 static bool
-bfin_finish_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
-			      struct bfd_link_info *info,
+bfin_finish_dynamic_sections (struct bfd_link_info *info,
 			      bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   bfd *dynobj;
@@ -4890,8 +4890,7 @@ bfin_finish_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
    dynamic sections here.  */
 
 static bool
-bfin_finish_dynamic_symbol (bfd * output_bfd,
-			    struct bfd_link_info *info,
+bfin_finish_dynamic_symbol (struct bfd_link_info *info,
 			    struct elf_link_hash_entry *h,
 			    Elf_Internal_Sym * sym)
 {
@@ -4924,7 +4923,7 @@ bfin_finish_dynamic_symbol (bfd * output_bfd,
 	{
 	  _bfd_error_handler (_("*** check this relocation %s"), __func__);
 	  rela.r_info = ELF32_R_INFO (0, R_BFIN_PCREL24);
-	  rela.r_addend = bfd_get_signed_32 (output_bfd,
+	  rela.r_addend = bfd_get_signed_32 (info->output_bfd,
 					     (sgot->contents
 					      +
 					      (h->got.
@@ -4932,7 +4931,7 @@ bfin_finish_dynamic_symbol (bfd * output_bfd,
 	}
       else
 	{
-	  bfd_put_32 (output_bfd, (bfd_vma) 0,
+	  bfd_put_32 (info->output_bfd, 0,
 		      sgot->contents + (h->got.offset & ~(bfd_vma) 1));
 	  rela.r_info = ELF32_R_INFO (h->dynindx, R_BFIN_GOT);
 	  rela.r_addend = 0;
@@ -4940,7 +4939,7 @@ bfin_finish_dynamic_symbol (bfd * output_bfd,
 
       loc = srela->contents;
       loc += srela->reloc_count++ * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
     }
 
   if (h->needs_copy)
@@ -5125,8 +5124,7 @@ bfin_discard_copies (struct elf_link_hash_entry *h, void * inf)
 }
 
 static bool
-bfin_late_size_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
-			 struct bfd_link_info *info)
+bfin_late_size_sections (struct bfd_link_info *info)
 {
   bfd *dynobj;
   asection *s;
diff --git a/bfd/elf32-cr16.c b/bfd/elf32-cr16.c
index f405378761d..2aed75aacbe 100644
--- a/bfd/elf32-cr16.c
+++ b/bfd/elf32-cr16.c
@@ -1333,7 +1333,7 @@ elf32_cr16_relax_delete_bytes (struct bfd_link_info *link_info, bfd *abfd,
 /* Relocate a CR16 ELF section.  */
 
 static int
-elf32_cr16_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
+elf32_cr16_relocate_section (struct bfd_link_info *info,
 			     bfd *input_bfd, asection *input_section,
 			     bfd_byte *contents, Elf_Internal_Rela *relocs,
 			     Elf_Internal_Sym *local_syms,
@@ -1370,7 +1370,8 @@ elf32_cr16_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections[r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 	}
       else
 	{
@@ -1390,7 +1391,7 @@ elf32_cr16_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
       if (bfd_link_relocatable (info))
 	continue;
 
-      r = cr16_elf_final_link_relocate (howto, input_bfd, output_bfd,
+      r = cr16_elf_final_link_relocate (howto, input_bfd, info->output_bfd,
 					input_section,
 					contents, rel->r_offset,
 					relocation, rel->r_addend,
@@ -1539,7 +1540,7 @@ elf32_cr16_get_relocated_section_contents (bfd *output_bfd,
 	  *secpp = isec;
 	}
 
-      if (! elf32_cr16_relocate_section (output_bfd, link_info, input_bfd,
+      if (! elf32_cr16_relocate_section (link_info, input_bfd,
 					 input_section, data, internal_relocs,
 					 isymbuf, sections))
 	goto error_return;
@@ -2380,8 +2381,7 @@ _bfd_cr16_elf_adjust_dynamic_symbol (struct bfd_link_info * info,
 /* Set the sizes of the dynamic sections.  */
 
 static bool
-_bfd_cr16_elf_late_size_sections (bfd * output_bfd,
-				  struct bfd_link_info * info)
+_bfd_cr16_elf_late_size_sections (struct bfd_link_info *info)
 {
   bfd * dynobj;
   asection * s;
@@ -2485,15 +2485,14 @@ _bfd_cr16_elf_late_size_sections (bfd * output_bfd,
       s->alloced = 1;
     }
 
-  return _bfd_elf_add_dynamic_tags (output_bfd, info, relocs);
+  return _bfd_elf_add_dynamic_tags (info, relocs);
 }
 
 /* Finish up dynamic symbol handling.  We set the contents of various
    dynamic sections here.  */
 
 static bool
-_bfd_cr16_elf_finish_dynamic_symbol (bfd * output_bfd,
-				     struct bfd_link_info * info,
+_bfd_cr16_elf_finish_dynamic_symbol (struct bfd_link_info * info,
 				     struct elf_link_hash_entry * h,
 				     Elf_Internal_Sym * sym)
 {
@@ -2533,12 +2532,12 @@ _bfd_cr16_elf_finish_dynamic_symbol (bfd * output_bfd,
 	}
       else
 	{
-	  bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + h->got.offset);
+	  bfd_put_32 (info->output_bfd, 0, sgot->contents + h->got.offset);
 	  rel.r_info = ELF32_R_INFO (h->dynindx, R_CR16_GOT_REGREL20);
 	  rel.r_addend = 0;
 	}
 
-      bfd_elf32_swap_reloca_out (output_bfd, &rel,
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rel,
 				 (bfd_byte *) ((Elf32_External_Rela *) srel->contents
 					       + srel->reloc_count));
       ++ srel->reloc_count;
@@ -2562,7 +2561,7 @@ _bfd_cr16_elf_finish_dynamic_symbol (bfd * output_bfd,
 		      + h->root.u.def.section->output_offset);
       rel.r_info = ELF32_R_INFO (h->dynindx, R_CR16_GOT_REGREL20);
       rel.r_addend = 0;
-      bfd_elf32_swap_reloca_out (output_bfd, &rel,
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rel,
 				 (bfd_byte *) ((Elf32_External_Rela *) s->contents
 					       + s->reloc_count));
       ++ s->reloc_count;
@@ -2579,8 +2578,7 @@ _bfd_cr16_elf_finish_dynamic_symbol (bfd * output_bfd,
 /* Finish up the dynamic sections.  */
 
 static bool
-_bfd_cr16_elf_finish_dynamic_sections (bfd *output_bfd,
-				       struct bfd_link_info *info,
+_bfd_cr16_elf_finish_dynamic_sections (struct bfd_link_info *info,
 				       bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   bfd *      dynobj;
@@ -2623,13 +2621,13 @@ _bfd_cr16_elf_finish_dynamic_sections (bfd *output_bfd,
 	      s = elf_hash_table (info)->srelplt;
 	    get_vma:
 	      dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    case DT_PLTRELSZ:
 	      s = elf_hash_table (info)->srelplt;
 	      dyn.d_un.d_val = s->size;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 	    }
 	}
@@ -2640,9 +2638,9 @@ _bfd_cr16_elf_finish_dynamic_sections (bfd *output_bfd,
   if (sgot->size > 0)
     {
       if (sdyn == NULL)
-	bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
+	bfd_put_32 (info->output_bfd, 0, sgot->contents);
       else
-	bfd_put_32 (output_bfd,
+	bfd_put_32 (info->output_bfd,
 		    sdyn->output_section->vma + sdyn->output_offset,
 		    sgot->contents);
     }
diff --git a/bfd/elf32-cris.c b/bfd/elf32-cris.c
index cc27a68ea2c..aefd3db10f5 100644
--- a/bfd/elf32-cris.c
+++ b/bfd/elf32-cris.c
@@ -968,8 +968,7 @@ static int additional_relocation_error_msg_count = 10;
    copied, for further comments.  */
 
 static int
-cris_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
-			   struct bfd_link_info *info,
+cris_elf_relocate_section (struct bfd_link_info *info,
 			   bfd *input_bfd,
 			   asection *input_section,
 			   bfd_byte *contents,
@@ -1039,7 +1038,8 @@ cris_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections [r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 
 	  symname = (bfd_elf_string_from_elf_section
 		     (input_bfd, symtab_hdr->sh_link, sym->st_name));
@@ -1109,7 +1109,7 @@ cris_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 		      || r_type == R_CRIS_32_PCREL))
 		relocation = 0;
 	      else if (!bfd_link_relocatable (info) && unresolved_reloc
-		       && (_bfd_elf_section_offset (output_bfd, info,
+		       && (_bfd_elf_section_offset (info->output_bfd, info,
 						    input_section,
 						    rel->r_offset)
 			   != (bfd_vma) -1))
@@ -1255,7 +1255,7 @@ cris_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 		      off &= ~1;
 		    else
 		      {
-			bfd_put_32 (output_bfd, relocation,
+			bfd_put_32 (info->output_bfd, relocation,
 				    sgot->contents + off);
 			h->got.offset |= 1;
 		      }
@@ -1275,7 +1275,8 @@ cris_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 		  off &= ~1;
 		else
 		  {
-		    bfd_put_32 (output_bfd, relocation, sgot->contents + off);
+		    bfd_put_32 (info->output_bfd, relocation,
+				sgot->contents + off);
 
 		    if (bfd_link_pic (info))
 		      {
@@ -1292,7 +1293,8 @@ cris_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 			outrel.r_addend = relocation;
 			loc = srelgot->contents;
 			loc += srelgot->reloc_count++ * sizeof (Elf32_External_Rela);
-			bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+			bfd_elf32_swap_reloca_out (info->output_bfd,
+						   &outrel, loc);
 		      }
 
 		    local_got_offsets[r_symndx] |= 1;
@@ -1471,8 +1473,8 @@ cris_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 	      relocate = false;
 
 	      outrel.r_offset =
-		_bfd_elf_section_offset (output_bfd, info, input_section,
-					 rel->r_offset);
+		_bfd_elf_section_offset (info->output_bfd, info,
+					 input_section, rel->r_offset);
 	      if (outrel.r_offset == (bfd_vma) -1)
 		skip = true;
 	      else if (outrel.r_offset == (bfd_vma) -2
@@ -1546,7 +1548,7 @@ cris_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 
 	      loc = sreloc->contents;
 	      loc += sreloc->reloc_count++ * sizeof (Elf32_External_Rela);
-	      bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+	      bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 
 	      /* This reloc will be computed at runtime, so there's no
 		 need to do anything now, except for R_CRIS_32 relocations
@@ -1614,20 +1616,20 @@ cris_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 		  loc = srelgot->contents;
 		  loc += srelgot->reloc_count++ * sizeof (Elf32_External_Rela);
 
-		  bfd_put_32 (output_bfd, (bfd_vma) 0, sgotplt->contents + 12);
-		  bfd_put_32 (output_bfd, (bfd_vma) 0, sgotplt->contents + 16);
+		  bfd_put_32 (info->output_bfd, 0, sgotplt->contents + 12);
+		  bfd_put_32 (info->output_bfd, 0, sgotplt->contents + 16);
 		  outrel.r_offset = (sgotplt->output_section->vma
 				     + sgotplt->output_offset
 				     + 12);
 		  outrel.r_info = ELF32_R_INFO (0, R_CRIS_DTPMOD);
 		  outrel.r_addend = 0;
-		  bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+		  bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 		}
 	      else
 		{
 		  /* For an executable, the GOT entry contents is known.  */
-		  bfd_put_32 (output_bfd, (bfd_vma) 1, sgotplt->contents + 12);
-		  bfd_put_32 (output_bfd, (bfd_vma) 0, sgotplt->contents + 16);
+		  bfd_put_32 (info->output_bfd, 1, sgotplt->contents + 12);
+		  bfd_put_32 (info->output_bfd, 0, sgotplt->contents + 16);
 		}
 
 	      /* Reverse the sign to mark that we've emitted the
@@ -1709,8 +1711,9 @@ cris_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 		  else
 		    local_got_offsets[r_symndx] |= 2;
 
-		  bfd_put_32 (output_bfd, 1, sgot->contents + off);
-		  bfd_put_32 (output_bfd, relocation, sgot->contents + off + 4);
+		  bfd_put_32 (info->output_bfd, 1, sgot->contents + off);
+		  bfd_put_32 (info->output_bfd, relocation,
+			      sgot->contents + off + 4);
 		}
 	      else
 		off &= ~3;
@@ -1750,8 +1753,8 @@ cris_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 		  /* Clear the target contents of the GOT (just as a
 		     gesture; it's already cleared on allocation): this
 		     relocation is not like the other dynrelocs.  */
-		  bfd_put_32 (output_bfd, 0, sgot->contents + off);
-		  bfd_put_32 (output_bfd, 0, sgot->contents + off + 4);
+		  bfd_put_32 (info->output_bfd, 0, sgot->contents + off);
+		  bfd_put_32 (info->output_bfd, 0, sgot->contents + off + 4);
 
 		  srelgot = htab->root.srelgot;
 		  BFD_ASSERT (srelgot != NULL);
@@ -1779,7 +1782,7 @@ cris_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 
 		  /* NULL if we had an error.  */
 		  if (srelgot->contents != NULL)
-		    bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+		    bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 		}
 	      else
 		off &= ~3;
@@ -1854,7 +1857,8 @@ cris_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 		  else
 		    local_got_offsets[r_symndx] |= 1;
 
-		  bfd_put_32 (output_bfd, relocation, sgot->contents + off);
+		  bfd_put_32 (info->output_bfd, relocation,
+			      sgot->contents + off);
 		}
 	      else
 		off &= ~3;
@@ -1904,7 +1908,8 @@ cris_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 
 		  /* Just "define" the initial contents in some
 		     semi-logical way.  */
-		  bfd_put_32 (output_bfd, relocation, sgot->contents + off);
+		  bfd_put_32 (info->output_bfd, relocation,
+			      sgot->contents + off);
 
 		  outrel.r_offset = (sgot->output_section->vma
 				     + sgot->output_offset
@@ -1914,7 +1919,7 @@ cris_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 		  loc += srelgot->reloc_count++ * sizeof (Elf32_External_Rela);
 		  /* NULL if we had an error.  */
 		  if (srelgot->contents != NULL)
-		    bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+		    bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 		}
 	      else
 		off &= ~3;
@@ -2056,8 +2061,7 @@ cris_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
    dynamic sections here.  */
 
 static bool
-elf_cris_finish_dynamic_symbol (bfd *output_bfd,
-				struct bfd_link_info *info,
+elf_cris_finish_dynamic_symbol (struct bfd_link_info *info,
 				struct elf_link_hash_entry *h,
 				Elf_Internal_Sym *sym)
 {
@@ -2080,7 +2084,7 @@ elf_cris_finish_dynamic_symbol (bfd *output_bfd,
   htab = elf_cris_hash_table (info);
 
   /* Adjust the various PLT entry offsets.  */
-  if (bfd_get_mach (output_bfd) == bfd_mach_cris_v32)
+  if (bfd_get_mach (info->output_bfd) == bfd_mach_cris_v32)
     {
       plt_off2 = 14;
       plt_off3 = 20;
@@ -2148,14 +2152,14 @@ elf_cris_finish_dynamic_symbol (bfd *output_bfd,
 		  plt_entry_size);
 
 	  /* We need to enter the absolute address of the GOT entry here.  */
-	  bfd_put_32 (output_bfd, got_base + got_offset,
+	  bfd_put_32 (info->output_bfd, got_base + got_offset,
 		      splt->contents + h->plt.offset + plt_off1);
 	}
       else
 	{
 	  memcpy (splt->contents + h->plt.offset, plt_pic_entry,
 		  plt_entry_size);
-	  bfd_put_32 (output_bfd, got_offset,
+	  bfd_put_32 (info->output_bfd, got_offset,
 		      splt->contents + h->plt.offset + plt_off1);
 	}
 
@@ -2164,18 +2168,18 @@ elf_cris_finish_dynamic_symbol (bfd *output_bfd,
       if (has_gotplt)
 	{
 	  /* Fill in the offset to the reloc table.  */
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 		      rela_plt_index * sizeof (Elf32_External_Rela),
 		      splt->contents + h->plt.offset + plt_off2);
 
 	  /* Fill in the offset to the first PLT entry, where to "jump".  */
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 		      - (h->plt.offset + plt_off3 + plt_off3_value_bias),
 		      splt->contents + h->plt.offset + plt_off3);
 
 	  /* Fill in the entry in the global offset table with the address of
 	     the relocating stub.  */
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 		      (splt->output_section->vma
 		       + splt->output_offset
 		       + h->plt.offset
@@ -2189,7 +2193,7 @@ elf_cris_finish_dynamic_symbol (bfd *output_bfd,
 	  rela.r_info = ELF32_R_INFO (h->dynindx, R_CRIS_JUMP_SLOT);
 	  rela.r_addend = 0;
 	  loc = srela->contents + rela_plt_index * sizeof (Elf32_External_Rela);
-	  bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+	  bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
 	}
 
       if (!h->def_regular)
@@ -2252,18 +2256,18 @@ elf_cris_finish_dynamic_symbol (bfd *output_bfd,
 	      && h->def_regular))
 	{
 	  rela.r_info = ELF32_R_INFO (0, R_CRIS_RELATIVE);
-	  rela.r_addend = bfd_get_signed_32 (output_bfd, where);
+	  rela.r_addend = bfd_get_signed_32 (info->output_bfd, where);
 	}
       else
 	{
-	  bfd_put_32 (output_bfd, (bfd_vma) 0, where);
+	  bfd_put_32 (info->output_bfd, (bfd_vma) 0, where);
 	  rela.r_info = ELF32_R_INFO (h->dynindx, R_CRIS_GLOB_DAT);
 	  rela.r_addend = 0;
 	}
 
       loc = srela->contents;
       loc += srela->reloc_count++ * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
     }
 
   if (h->needs_copy)
@@ -2289,7 +2293,7 @@ elf_cris_finish_dynamic_symbol (bfd *output_bfd,
       rela.r_info = ELF32_R_INFO (h->dynindx, R_CRIS_COPY);
       rela.r_addend = 0;
       loc = s->contents + s->reloc_count++ * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
     }
 
   /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute.  */
@@ -2305,8 +2309,7 @@ elf_cris_finish_dynamic_symbol (bfd *output_bfd,
    computed.  */
 
 static bool
-elf_cris_finish_dynamic_sections (bfd *output_bfd,
-				  struct bfd_link_info *info,
+elf_cris_finish_dynamic_sections (struct bfd_link_info *info,
 				  bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   bfd *dynobj;
@@ -2343,7 +2346,7 @@ elf_cris_finish_dynamic_sections (bfd *output_bfd,
 
 	    case DT_PLTGOT:
 	      dyn.d_un.d_ptr = sgot->output_section->vma + sgot->output_offset;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    case DT_JMPREL:
@@ -2352,7 +2355,7 @@ elf_cris_finish_dynamic_sections (bfd *output_bfd,
 	      s = elf_hash_table (info)->srelplt;
 	      dyn.d_un.d_ptr = s != NULL ? (s->output_section->vma
 					    + s->output_offset) : 0;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    case DT_PLTRELSZ:
@@ -2361,7 +2364,7 @@ elf_cris_finish_dynamic_sections (bfd *output_bfd,
 		dyn.d_un.d_val = 0;
 	      else
 		dyn.d_un.d_val = s->size;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 	    }
 	}
@@ -2369,7 +2372,7 @@ elf_cris_finish_dynamic_sections (bfd *output_bfd,
       /* Fill in the first entry in the procedure linkage table.  */
       if (splt->size > 0)
 	{
-	  if (bfd_get_mach (output_bfd) == bfd_mach_cris_v32)
+	  if (bfd_get_mach (info->output_bfd) == bfd_mach_cris_v32)
 	    {
 	      if (bfd_link_pic (info))
 		memcpy (splt->contents, elf_cris_pic_plt0_entry_v32,
@@ -2378,7 +2381,7 @@ elf_cris_finish_dynamic_sections (bfd *output_bfd,
 		{
 		  memcpy (splt->contents, elf_cris_plt0_entry_v32,
 			  PLT_ENTRY_SIZE_V32);
-		  bfd_put_32 (output_bfd,
+		  bfd_put_32 (info->output_bfd,
 			      sgot->output_section->vma
 			      + sgot->output_offset + 4,
 			      splt->contents + 4);
@@ -2396,11 +2399,11 @@ elf_cris_finish_dynamic_sections (bfd *output_bfd,
 		{
 		  memcpy (splt->contents, elf_cris_plt0_entry,
 			  PLT_ENTRY_SIZE);
-		  bfd_put_32 (output_bfd,
+		  bfd_put_32 (info->output_bfd,
 			      sgot->output_section->vma
 			      + sgot->output_offset + 4,
 			      splt->contents + 6);
-		  bfd_put_32 (output_bfd,
+		  bfd_put_32 (info->output_bfd,
 			      sgot->output_section->vma
 			      + sgot->output_offset + 8,
 			      splt->contents + 14);
@@ -2416,13 +2419,13 @@ elf_cris_finish_dynamic_sections (bfd *output_bfd,
   if (sgot->size > 0)
     {
       if (sdyn == NULL)
-	bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
+	bfd_put_32 (info->output_bfd, 0, sgot->contents);
       else
-	bfd_put_32 (output_bfd,
+	bfd_put_32 (info->output_bfd,
 		    sdyn->output_section->vma + sdyn->output_offset,
 		    sgot->contents);
-      bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
-      bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
+      bfd_put_32 (info->output_bfd, 0, sgot->contents + 4);
+      bfd_put_32 (info->output_bfd, 0, sgot->contents + 8);
     }
 
   elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
@@ -3488,8 +3491,7 @@ cris_elf_check_relocs (bfd *abfd,
 /* Set the sizes of the dynamic sections.  */
 
 static bool
-elf_cris_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-			     struct bfd_link_info *info)
+elf_cris_late_size_sections (struct bfd_link_info *info)
 {
   struct elf_cris_link_hash_table * htab;
   bfd *dynobj;
@@ -3631,7 +3633,7 @@ elf_cris_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
       s->alloced = 1;
     }
 
-  return _bfd_elf_add_dynamic_tags (output_bfd, info, relocs);
+  return _bfd_elf_add_dynamic_tags (info, relocs);
 }
 
 /* This function is called via elf_cris_link_hash_traverse if we are
@@ -3971,8 +3973,7 @@ elf_cris_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
    machinery.  */
 
 static bfd_vma
-elf_cris_got_elt_size (bfd *abfd ATTRIBUTE_UNUSED,
-		       struct bfd_link_info *info ATTRIBUTE_UNUSED,
+elf_cris_got_elt_size (struct bfd_link_info *info ATTRIBUTE_UNUSED,
 		       struct elf_link_hash_entry *hr,
 		       bfd *ibfd,
 		       unsigned long symndx)
diff --git a/bfd/elf32-crx.c b/bfd/elf32-crx.c
index 55255c51dec..3e5184307a2 100644
--- a/bfd/elf32-crx.c
+++ b/bfd/elf32-crx.c
@@ -37,7 +37,7 @@ static bfd_reloc_status_type crx_elf_final_link_relocate
    bfd_byte *, bfd_vma, bfd_vma, bfd_vma,
    struct bfd_link_info *, asection *, int);
 static int elf32_crx_relocate_section
-  (bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *,
+  (struct bfd_link_info *, bfd *, asection *, bfd_byte *,
    Elf_Internal_Rela *, Elf_Internal_Sym *, asection **);
 static bool elf32_crx_relax_section
   (bfd *, asection *, struct bfd_link_info *, bool *);
@@ -800,9 +800,9 @@ elf32_crx_get_relocated_section_contents (bfd *output_bfd,
 	  *secpp = isec;
 	}
 
-      if (! elf32_crx_relocate_section (output_bfd, link_info, input_bfd,
-				     input_section, data, internal_relocs,
-				     isymbuf, sections))
+      if (!elf32_crx_relocate_section (link_info, input_bfd,
+				       input_section, data, internal_relocs,
+				       isymbuf, sections))
 	goto error_return;
 
       free (sections);
@@ -828,7 +828,7 @@ elf32_crx_get_relocated_section_contents (bfd *output_bfd,
 /* Relocate a CRX ELF section.  */
 
 static int
-elf32_crx_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
+elf32_crx_relocate_section (struct bfd_link_info *info,
 			    bfd *input_bfd, asection *input_section,
 			    bfd_byte *contents, Elf_Internal_Rela *relocs,
 			    Elf_Internal_Sym *local_syms,
@@ -865,7 +865,8 @@ elf32_crx_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections[r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 	}
       else
 	{
@@ -885,11 +886,11 @@ elf32_crx_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
       if (bfd_link_relocatable (info))
 	continue;
 
-      r = crx_elf_final_link_relocate (howto, input_bfd, output_bfd,
-					input_section,
-					contents, rel->r_offset,
-					relocation, rel->r_addend,
-					info, sec, h == NULL);
+      r = crx_elf_final_link_relocate (howto, input_bfd, info->output_bfd,
+				       input_section,
+				       contents, rel->r_offset,
+				       relocation, rel->r_addend,
+				       info, sec, h == NULL);
 
       if (r != bfd_reloc_ok)
 	{
diff --git a/bfd/elf32-csky.c b/bfd/elf32-csky.c
index a7c6f956923..877c6ee86d7 100644
--- a/bfd/elf32-csky.c
+++ b/bfd/elf32-csky.c
@@ -1891,8 +1891,7 @@ csky_allocate_dynrelocs (struct elf_link_hash_entry *h, void *inf)
 /* Set the sizes of the dynamic sections.  */
 
 static bool
-csky_elf_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-			     struct bfd_link_info *info)
+csky_elf_late_size_sections (struct bfd_link_info *info)
 {
   struct csky_elf_link_hash_table *htab;
   bfd *dynobj;
@@ -2090,15 +2089,14 @@ csky_elf_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
 
   if (htab->elf.dynamic_sections_created)
     htab->elf.dt_pltgot_required = htab->elf.sgot->size != 0;
-  return _bfd_elf_add_dynamic_tags (output_bfd, info, relocs);
+  return _bfd_elf_add_dynamic_tags (info, relocs);
 }
 
 /* Finish up dynamic symbol handling.  We set the contents of various
    dynamic sections here.  */
 
 static bool
-csky_elf_finish_dynamic_symbol (bfd *output_bfd,
-				struct bfd_link_info *info,
+csky_elf_finish_dynamic_symbol (struct bfd_link_info *info,
 				struct elf_link_hash_entry *h,
 				Elf_Internal_Sym *sym)
 {
@@ -2132,30 +2130,30 @@ csky_elf_finish_dynamic_symbol (bfd *output_bfd,
 		  || ((h->forced_local || bfd_link_executable (info))
 		      && h->def_regular));
       BFD_ASSERT (plt != NULL && gotplt != NULL && relplt != NULL);
-      if (bfd_csky_abi (output_bfd) == CSKY_ABI_V2)
+      if (bfd_csky_abi (info->output_bfd) == CSKY_ABI_V2)
 	plt_index = h->plt.offset / PLT_ENTRY_SIZE - 1;
       else
 	plt_index = h->plt.offset / PLT_ENTRY_SIZE_P - 1;
       got_offset = (plt_index + 3) * 4;
 
       /* Fill in the entry in the procedure linkage table.  */
-      if (bfd_csky_abi (output_bfd) == CSKY_ABI_V2)
+      if (bfd_csky_abi (info->output_bfd) == CSKY_ABI_V2)
 	{
-	  csky_put_insn_32 (output_bfd, csky_elf_plt_entry_v2[0],
+	  csky_put_insn_32 (info->output_bfd, csky_elf_plt_entry_v2[0],
 			    plt->contents + h->plt.offset);
-	  csky_put_insn_32 (output_bfd,
+	  csky_put_insn_32 (info->output_bfd,
 			    (csky_elf_plt_entry_v2[1] | plt_index),
 			    plt->contents + h->plt.offset + 4);
-	  csky_put_insn_32 (output_bfd, csky_elf_plt_entry_v2[2],
+	  csky_put_insn_32 (info->output_bfd, csky_elf_plt_entry_v2[2],
 			    plt->contents + h->plt.offset + 8);
 	}
       else
 	{
 	  int i;
 	  for (i = 0; i < 6; i++)
-	    bfd_put_16 (output_bfd, csky_elf_plt_entry_v1[i],
+	    bfd_put_16 (info->output_bfd, csky_elf_plt_entry_v1[i],
 			plt->contents + h->plt.offset + i * 2);
-	  bfd_put_32 (output_bfd, plt_index,
+	  bfd_put_32 (info->output_bfd, plt_index,
 		      plt->contents + h->plt.offset + i * 2);
 	}
 
@@ -2171,7 +2169,7 @@ csky_elf_finish_dynamic_symbol (bfd *output_bfd,
 	     + plt_index * sizeof (Elf32_External_Rela));
 
       if (loc != NULL)
-	bfd_elf32_swap_reloca_out (output_bfd, &rel, loc);
+	bfd_elf32_swap_reloca_out (info->output_bfd, &rel, loc);
       if (! h->def_regular)
 	{
 	  /* Mark the symbol as undefined, rather than as defined in
@@ -2222,7 +2220,7 @@ csky_elf_finish_dynamic_symbol (bfd *output_bfd,
       else
 	{
 	  BFD_ASSERT ((h->got.offset & 1) == 0);
-	  bfd_put_32 (output_bfd, (bfd_vma) 0,
+	  bfd_put_32 (info->output_bfd, 0,
 		      htab->elf.sgot->contents + h->got.offset);
 	  rel.r_info = ELF32_R_INFO (h->dynindx, R_CKCORE_GLOB_DAT);
 	  rel.r_addend = 0;
@@ -2232,7 +2230,7 @@ csky_elf_finish_dynamic_symbol (bfd *output_bfd,
       loc += htab->elf.srelgot->reloc_count++ * sizeof (Elf32_External_Rela);
 
       if (loc != NULL)
-	bfd_elf32_swap_reloca_out (output_bfd, &rel, loc);
+	bfd_elf32_swap_reloca_out (info->output_bfd, &rel, loc);
     }
 
   if (h->needs_copy)
@@ -2257,7 +2255,7 @@ csky_elf_finish_dynamic_symbol (bfd *output_bfd,
 	s = htab->elf.srelbss;
       BFD_ASSERT (s != NULL);
       loc = s->contents + s->reloc_count++ * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
     }
 
   /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute.  */
@@ -2271,8 +2269,7 @@ csky_elf_finish_dynamic_symbol (bfd *output_bfd,
 /* Finish up the dynamic sections.  */
 
 static bool
-csky_elf_finish_dynamic_sections (bfd *output_bfd,
-				  struct bfd_link_info *info,
+csky_elf_finish_dynamic_sections (struct bfd_link_info *info,
 				  bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   struct csky_elf_link_hash_table *htab;
@@ -2329,7 +2326,7 @@ csky_elf_finish_dynamic_sections (bfd *output_bfd,
 
 	  if (name != NULL)
 	    {
-	      asection *s = bfd_get_section_by_name (output_bfd, name);
+	      asection *s = bfd_get_section_by_name (info->output_bfd, name);
 
 	      if (s == NULL)
 		dyn.d_un.d_val = 0;
@@ -2338,7 +2335,7 @@ csky_elf_finish_dynamic_sections (bfd *output_bfd,
 	      else
 		dyn.d_un.d_val = s->size;
 	    }
-	  bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	  bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	}
     }
 
@@ -2351,12 +2348,12 @@ csky_elf_finish_dynamic_sections (bfd *output_bfd,
     {
       if (got_sec->size > 0)
 	{
-	  bfd_put_32 (output_bfd,
-		      (sdyn == NULL ? (bfd_vma) 0
+	  bfd_put_32 (info->output_bfd,
+		      (sdyn == NULL ? 0
 		       : sdyn->output_section->vma + sdyn->output_offset),
 		      got_sec->contents);
-	  bfd_put_32 (output_bfd, (bfd_vma) 0, got_sec->contents + 4);
-	  bfd_put_32 (output_bfd, (bfd_vma) 0, got_sec->contents + 8);
+	  bfd_put_32 (info->output_bfd, 0, got_sec->contents + 4);
+	  bfd_put_32 (info->output_bfd, 0, got_sec->contents + 8);
 	}
       elf_section_data (got_sec->output_section)->this_hdr.sh_entsize = 4;
     }
@@ -4272,8 +4269,7 @@ tpoff (struct bfd_link_info *info, bfd_vma address)
 /* Relocate a csky section.  */
 
 static int
-csky_elf_relocate_section (bfd *                  output_bfd,
-			   struct bfd_link_info * info,
+csky_elf_relocate_section (struct bfd_link_info * info,
 			   bfd *                  input_bfd,
 			   asection *             input_section,
 			   bfd_byte *             contents,
@@ -4346,7 +4342,8 @@ csky_elf_relocate_section (bfd *                  output_bfd,
 	  /* Get symbol table entry.  */
 	  sym = local_syms + r_symndx;
 	  sec = local_sections[r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 	  addend = (bfd_vma)rel->r_addend;
 	}
       else
@@ -4453,7 +4450,7 @@ csky_elf_relocate_section (bfd *                  output_bfd,
 		    off &= ~1;
 		  else
 		    {
-		      bfd_put_32 (output_bfd, relocation,
+		      bfd_put_32 (info->output_bfd, relocation,
 				  htab->elf.sgot->contents + off);
 		      h->got.offset |= 1;
 
@@ -4490,7 +4487,7 @@ csky_elf_relocate_section (bfd *                  output_bfd,
 		off &= ~1;
 	      else
 		{
-		  bfd_put_32 (output_bfd, relocation,
+		  bfd_put_32 (info->output_bfd, relocation,
 			      htab->elf.sgot->contents + off);
 		  local_got_offsets[r_symndx] |= 1;
 		  if (bfd_link_pic (info))
@@ -4514,7 +4511,7 @@ csky_elf_relocate_section (bfd *                  output_bfd,
 	      loc = srelgot->contents;
 	      loc += (srelgot->reloc_count++ * sizeof (Elf32_External_Rela));
 	      if (loc != NULL)
-		bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+		bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 	    }
 	  relocation = htab->elf.sgot->output_offset + off;
 	  break;
@@ -4546,21 +4543,24 @@ csky_elf_relocate_section (bfd *                  output_bfd,
 	case R_CKCORE_DOFFSET_IMM18BY2:
 	case R_CKCORE_DOFFSET_IMM18BY4:
 	  {
-	    asection *sdata = bfd_get_section_by_name (output_bfd, ".data");
+	    asection *sdata = bfd_get_section_by_name (info->output_bfd,
+						       ".data");
 	    relocation -= sdata->output_section->vma;
 	  }
 	  break;
 
 	case R_CKCORE_DOFFSET_LO16:
 	  {
-	    asection *sdata = bfd_get_section_by_name (output_bfd, ".data");
+	    asection *sdata = bfd_get_section_by_name (info->output_bfd,
+						       ".data");
 	    relocation -= sdata->output_section->vma;
 	  }
 	  break;
 
 	case R_CKCORE_TOFFSET_LO16:
 	  {
-	    asection *stext = bfd_get_section_by_name (output_bfd, ".text");
+	    asection *stext = bfd_get_section_by_name (info->output_bfd,
+						       ".text");
 	    if (stext)
 	      relocation -= stext->output_section->vma;
 	  }
@@ -4616,7 +4616,7 @@ csky_elf_relocate_section (bfd *                  output_bfd,
 			    relative_reloc = true;
 			}
 		    }
-		  bfd_put_32 (output_bfd, relocation,
+		  bfd_put_32 (info->output_bfd, relocation,
 			      htab->elf.sgot->contents + off);
 
 		  if (relative_reloc)
@@ -4637,14 +4637,15 @@ csky_elf_relocate_section (bfd *                  output_bfd,
 		      loc += (srelgot->reloc_count++
 			      * sizeof (Elf32_External_Rela));
 		      if (loc != NULL)
-			bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+			bfd_elf32_swap_reloca_out (info->output_bfd,
+						   &outrel, loc);
 		    }
 		  relocation = off + htab->elf.sgot->output_offset;
 		}
 	      break;
 	    }
 	  /* The relocation is the got offset.  */
-	  if (bfd_csky_abi (output_bfd) == CSKY_ABI_V2)
+	  if (bfd_csky_abi (info->output_bfd) == CSKY_ABI_V2)
 	    relocation = (h->plt.offset / PLT_ENTRY_SIZE + 2) * 4;
 	  else
 	    relocation = (h->plt.offset / PLT_ENTRY_SIZE_P + 2) * 4;
@@ -4716,7 +4717,7 @@ csky_elf_relocate_section (bfd *                  output_bfd,
 		      howto = &csky_elf_howto_table[R_CKCORE_PCREL_IMM26BY2];
 		      read_content_substitute = CSKY_INSN_BSR32;
 		    }
-		  else if (bfd_csky_arch (output_bfd) == CSKY_ARCH_810)
+		  else if (bfd_csky_arch (info->output_bfd) == CSKY_ARCH_810)
 		    /* if bsr32 cannot reach, generate
 		       "lrw r25, label; jsr r25" instead of
 		       jsri label.  */
@@ -4735,7 +4736,7 @@ csky_elf_relocate_section (bfd *                  output_bfd,
 	      break;
 	    } /* else if h == NULL...  */
 
-	  else if (bfd_csky_arch (output_bfd) == CSKY_ARCH_810
+	  else if (bfd_csky_arch (info->output_bfd) == CSKY_ARCH_810
 		   && (ELF32_R_TYPE (rel->r_info)
 		       == R_CKCORE_PCREL_JSR_IMM26BY2))
 	    {
@@ -4770,7 +4771,7 @@ csky_elf_relocate_section (bfd *                  output_bfd,
 	      relocate = false;
 
 	      outrel.r_offset =
-		_bfd_elf_section_offset (output_bfd, info, input_section,
+		_bfd_elf_section_offset (info->output_bfd, info, input_section,
 					 rel->r_offset);
 	      if (outrel.r_offset == (bfd_vma) -1)
 		skip = true;
@@ -4805,7 +4806,7 @@ csky_elf_relocate_section (bfd *                  output_bfd,
 		      * sizeof (Elf32_External_Rela));
 
 	      if (loc != NULL)
-		bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+		bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 
 	      /* If this reloc is against an external symbol, we do not
 		 want to diddle with the addend. Otherwise, we need to
@@ -4856,7 +4857,7 @@ csky_elf_relocate_section (bfd *                  output_bfd,
 	      relocate = false;
 
 	      outrel.r_offset =
-		_bfd_elf_section_offset (output_bfd, info, input_section,
+		_bfd_elf_section_offset (info->output_bfd, info, input_section,
 					 rel->r_offset);
 
 	      if (outrel.r_offset == (bfd_vma) -1)
@@ -4894,7 +4895,7 @@ csky_elf_relocate_section (bfd *                  output_bfd,
 		      * sizeof (Elf32_External_Rela));
 
 	      if (loc != NULL)
-		bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+		bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 
 	      /* If this reloc is against an external symbol, we do
 		 want to diddle with the addend. Otherwise, we need to
@@ -4929,17 +4930,17 @@ csky_elf_relocate_section (bfd *                  output_bfd,
 		    = (htab->elf.sgot->output_section->vma
 		       + htab->elf.sgot->output_offset + off);
 		  outrel.r_info = ELF32_R_INFO (0, R_CKCORE_TLS_DTPMOD32);
-		  bfd_put_32 (output_bfd, outrel.r_addend,
+		  bfd_put_32 (info->output_bfd, outrel.r_addend,
 			      htab->elf.sgot->contents + off);
 
 		  loc = htab->elf.srelgot->contents;
 		  loc += (htab->elf.srelgot->reloc_count++
 			  * sizeof (Elf32_External_Rela));
 		  if (loc)
-		    bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+		    bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 		}
 	      else
-		bfd_put_32 (output_bfd, 1,
+		bfd_put_32 (info->output_bfd, 1,
 			    htab->elf.sgot->contents + off);
 	      htab->tls_ldm_got.offset |= 1;
 	    }
@@ -5031,15 +5032,15 @@ csky_elf_relocate_section (bfd *                  output_bfd,
 			     + cur_off);
 			outrel.r_info
 			  = ELF32_R_INFO (indx, R_CKCORE_TLS_DTPMOD32);
-			bfd_put_32 (output_bfd, outrel.r_addend,
+			bfd_put_32 (info->output_bfd, outrel.r_addend,
 				    htab->elf.sgot->contents + cur_off);
 			if (loc)
-			  bfd_elf32_swap_reloca_out (output_bfd,
+			  bfd_elf32_swap_reloca_out (info->output_bfd,
 						     &outrel, loc);
 			loc += sizeof (Elf32_External_Rela);
 			htab->elf.srelgot->reloc_count++;
 			if (indx == 0)
-			  bfd_put_32 (output_bfd,
+			  bfd_put_32 (info->output_bfd,
 				      relocation - dtpoff_base (info),
 				      (htab->elf.sgot->contents
 				       + cur_off + 4));
@@ -5049,14 +5050,14 @@ csky_elf_relocate_section (bfd *                  output_bfd,
 			    outrel.r_info
 			      = ELF32_R_INFO (indx, R_CKCORE_TLS_DTPOFF32);
 			    outrel.r_offset += 4;
-			    bfd_put_32 (output_bfd, outrel.r_addend,
+			    bfd_put_32 (info->output_bfd, outrel.r_addend,
 					(htab->elf.sgot->contents
 					 + cur_off + 4));
 			    outrel.r_info =
 			      ELF32_R_INFO (indx,
 					    R_CKCORE_TLS_DTPOFF32);
 			    if (loc)
-			      bfd_elf32_swap_reloca_out (output_bfd,
+			      bfd_elf32_swap_reloca_out (info->output_bfd,
 							 &outrel,
 							 loc);
 			    htab->elf.srelgot->reloc_count++;
@@ -5071,9 +5072,9 @@ csky_elf_relocate_section (bfd *                  output_bfd,
 			   static link or an executable link with the
 			   symbol binding locally.  Mark it as belonging
 			   to module 1, the executable.  */
-			bfd_put_32 (output_bfd, 1,
+			bfd_put_32 (info->output_bfd, 1,
 				    htab->elf.sgot->contents + cur_off);
-			bfd_put_32 (output_bfd,
+			bfd_put_32 (info->output_bfd,
 				    relocation - dtpoff_base (info),
 				    htab->elf.sgot->contents
 				    + cur_off + 4);
@@ -5094,16 +5095,16 @@ csky_elf_relocate_section (bfd *                  output_bfd,
 			outrel.r_info
 			  = ELF32_R_INFO (indx, R_CKCORE_TLS_TPOFF32);
 
-			bfd_put_32 (output_bfd, outrel.r_addend,
+			bfd_put_32 (info->output_bfd, outrel.r_addend,
 				    htab->elf.sgot->contents + cur_off);
 			if (loc)
-			  bfd_elf32_swap_reloca_out (output_bfd,
+			  bfd_elf32_swap_reloca_out (info->output_bfd,
 						     &outrel, loc);
 			htab->elf.srelgot->reloc_count++;
 			loc += sizeof (Elf32_External_Rela);
 		      }
 		    else
-		      bfd_put_32 (output_bfd, tpoff (info, relocation),
+		      bfd_put_32 (info->output_bfd, tpoff (info, relocation),
 				  htab->elf.sgot->contents + cur_off);
 		  }
 		if (h != NULL)
diff --git a/bfd/elf32-d10v.c b/bfd/elf32-d10v.c
index 673743e0a0b..384162e23ff 100644
--- a/bfd/elf32-d10v.c
+++ b/bfd/elf32-d10v.c
@@ -387,8 +387,7 @@ insert_rel_addend (bfd *abfd,
 /* Relocate a D10V ELF section.  */
 
 static int
-elf32_d10v_relocate_section (bfd *output_bfd,
-			     struct bfd_link_info *info,
+elf32_d10v_relocate_section (struct bfd_link_info *info,
 			     bfd *input_bfd,
 			     asection *input_section,
 			     bfd_byte *contents,
@@ -450,8 +449,8 @@ elf32_d10v_relocate_section (bfd *output_bfd,
 	      else
 		{
 		  asection *msec = sec;
-		  addend = _bfd_elf_rel_local_sym (output_bfd, sym, &msec,
-						   addend);
+		  addend = _bfd_elf_rel_local_sym (info->output_bfd,
+						   sym, &msec, addend);
 		  addend -= relocation;
 		  addend += msec->output_section->vma + msec->output_offset;
 		}
diff --git a/bfd/elf32-epiphany.c b/bfd/elf32-epiphany.c
index 5bb97ade084..c35b4551d2c 100644
--- a/bfd/elf32-epiphany.c
+++ b/bfd/elf32-epiphany.c
@@ -470,8 +470,7 @@ epiphany_final_link_relocate (reloc_howto_type *  howto,
    accordingly.  */
 
 static int
-epiphany_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
-			       struct bfd_link_info *info,
+epiphany_elf_relocate_section (struct bfd_link_info *info,
 			       bfd *input_bfd,
 			       asection *input_section,
 			       bfd_byte *contents,
diff --git a/bfd/elf32-fr30.c b/bfd/elf32-fr30.c
index 75ec074d23b..0e158841082 100644
--- a/bfd/elf32-fr30.c
+++ b/bfd/elf32-fr30.c
@@ -487,8 +487,7 @@ fr30_final_link_relocate (reloc_howto_type *howto,
    accordingly.  */
 
 static int
-fr30_elf_relocate_section (bfd *output_bfd,
-			   struct bfd_link_info *info,
+fr30_elf_relocate_section (struct bfd_link_info *info,
 			   bfd *input_bfd,
 			   asection *input_section,
 			   bfd_byte *contents,
@@ -534,7 +533,8 @@ fr30_elf_relocate_section (bfd *output_bfd,
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections [r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 
 	  name = bfd_elf_string_from_elf_section
 	    (input_bfd, symtab_hdr->sh_link, sym->st_name);
diff --git a/bfd/elf32-frv.c b/bfd/elf32-frv.c
index d8a338bb98a..183a78f6049 100644
--- a/bfd/elf32-frv.c
+++ b/bfd/elf32-frv.c
@@ -2652,8 +2652,7 @@ frv_final_link_relocate (reloc_howto_type *howto,
    accordingly.  */
 
 static int
-elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
-			    struct bfd_link_info *info,
+elf32_frv_relocate_section (struct bfd_link_info *info,
 			    bfd *input_bfd,
 			    asection *input_section,
 			    bfd_byte *contents,
@@ -2674,28 +2673,28 @@ elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
   sym_hashes = elf_sym_hashes (input_bfd);
   relend     = relocs + input_section->reloc_count;
 
-  isec_segment = _frvfdpic_osec_to_segment (output_bfd,
+  isec_segment = _frvfdpic_osec_to_segment (info->output_bfd,
 					    input_section->output_section);
-  if (IS_FDPIC (output_bfd) && frvfdpic_got_section (info))
-    got_segment = _frvfdpic_osec_to_segment (output_bfd,
+  if (IS_FDPIC (info->output_bfd) && frvfdpic_got_section (info))
+    got_segment = _frvfdpic_osec_to_segment (info->output_bfd,
 					     frvfdpic_got_section (info)
 					     ->output_section);
   else
     got_segment = -1;
-  if (IS_FDPIC (output_bfd) && frvfdpic_gotfixup_section (info))
-    gprel_segment = _frvfdpic_osec_to_segment (output_bfd,
+  if (IS_FDPIC (info->output_bfd) && frvfdpic_gotfixup_section (info))
+    gprel_segment = _frvfdpic_osec_to_segment (info->output_bfd,
 					       frvfdpic_gotfixup_section (info)
 					       ->output_section);
   else
     gprel_segment = -1;
-  if (IS_FDPIC (output_bfd) && frvfdpic_plt_section (info))
-    plt_segment = _frvfdpic_osec_to_segment (output_bfd,
+  if (IS_FDPIC (info->output_bfd) && frvfdpic_plt_section (info))
+    plt_segment = _frvfdpic_osec_to_segment (info->output_bfd,
 					     frvfdpic_plt_section (info)
 					     ->output_section);
   else
     plt_segment = -1;
   if (elf_hash_table (info)->tls_sec)
-    tls_segment = _frvfdpic_osec_to_segment (output_bfd,
+    tls_segment = _frvfdpic_osec_to_segment (info->output_bfd,
 					     elf_hash_table (info)->tls_sec);
   else
     tls_segment = -1;
@@ -2731,7 +2730,8 @@ elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 	{
 	  sym = local_syms + r_symndx;
 	  osec = sec = local_sections [r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 
 	  name = bfd_elf_string_from_elf_section
 	    (input_bfd, symtab_hdr->sh_link, sym->st_name);
@@ -2773,7 +2773,7 @@ elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 	{
 	case R_FRV_LABEL24:
 	case R_FRV_32:
-	  if (! IS_FDPIC (output_bfd))
+	  if (! IS_FDPIC (info->output_bfd))
 	    goto non_fdpic;
 	  /* Fall through.  */
 
@@ -2824,7 +2824,8 @@ elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 	  if (! picrel)
 	    return false;
 
-	  if (!_frvfdpic_emit_got_relocs_plt_entries (picrel, output_bfd, info,
+	  if (!_frvfdpic_emit_got_relocs_plt_entries (picrel,
+						      info->output_bfd, info,
 						      osec, sym,
 						      rel->r_addend))
 	    {
@@ -2843,7 +2844,7 @@ elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 	  picrel = NULL;
 	  if (h
 	      && ! FRVFDPIC_SYM_LOCAL (info, h)
-	      && _bfd_elf_section_offset (output_bfd, info, input_section,
+	      && _bfd_elf_section_offset (info->output_bfd, info, input_section,
 					  rel->r_offset) != (bfd_vma) -1)
 	    {
 	      info->callbacks->einfo
@@ -3454,7 +3455,7 @@ elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 	{
 	case R_FRV_LABEL24:
 	  check_segment[0] = isec_segment;
-	  if (! IS_FDPIC (output_bfd))
+	  if (! IS_FDPIC (info->output_bfd))
 	    check_segment[1] = isec_segment;
 	  else if (picrel->plt)
 	    {
@@ -3472,7 +3473,7 @@ elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 	    check_segment[1] = check_segment[0];
 	  else
 	    check_segment[1] = sec
-	      ? _frvfdpic_osec_to_segment (output_bfd, sec->output_section)
+	      ? _frvfdpic_osec_to_segment (info->output_bfd, sec->output_section)
 	      : (unsigned)-1;
 	  break;
 
@@ -3498,7 +3499,7 @@ elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 	    + frvfdpic_got_initial_offset (info);
 	  check_segment[0] = got_segment;
 	  check_segment[1] = sec
-	    ? _frvfdpic_osec_to_segment (output_bfd, sec->output_section)
+	    ? _frvfdpic_osec_to_segment (info->output_bfd, sec->output_section)
 	    : (unsigned)-1;
 	  break;
 
@@ -3575,7 +3576,7 @@ elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 		      {
 			bfd_vma offset;
 
-			if (_frvfdpic_osec_readonly_p (output_bfd,
+			if (_frvfdpic_osec_readonly_p (info->output_bfd,
 						       input_section
 						       ->output_section))
 			  {
@@ -3587,11 +3588,11 @@ elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 			  }
 
 			offset = _bfd_elf_section_offset
-			  (output_bfd, info,
+			  (info->output_bfd, info,
 			   input_section, rel->r_offset);
 
 			if (offset != (bfd_vma)-1)
-			  _frvfdpic_add_rofixup (output_bfd,
+			  _frvfdpic_add_rofixup (info->output_bfd,
 						 frvfdpic_gotfixup_section
 						 (info),
 						 offset + input_section
@@ -3605,7 +3606,7 @@ elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 		  {
 		    bfd_vma offset;
 
-		    if (_frvfdpic_osec_readonly_p (output_bfd,
+		    if (_frvfdpic_osec_readonly_p (info->output_bfd,
 						   input_section
 						   ->output_section))
 		      {
@@ -3617,11 +3618,11 @@ elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 		      }
 
 		    offset = _bfd_elf_section_offset
-		      (output_bfd, info,
+		      (info->output_bfd, info,
 		       input_section, rel->r_offset);
 
 		    if (offset != (bfd_vma)-1)
-		      _frvfdpic_add_dyn_reloc (output_bfd,
+		      _frvfdpic_add_dyn_reloc (info->output_bfd,
 					       frvfdpic_gotrel_section (info),
 					       offset + input_section
 					       ->output_section->vma
@@ -3641,7 +3642,7 @@ elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 	  break;
 
 	case R_FRV_32:
-	  if (! IS_FDPIC (output_bfd))
+	  if (! IS_FDPIC (info->output_bfd))
 	    {
 	      check_segment[0] = check_segment[1] = -1;
 	      break;
@@ -3696,7 +3697,7 @@ elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 		    && (bfd_section_flags (input_section->output_section)
 			& (SEC_ALLOC | SEC_LOAD)) == (SEC_ALLOC | SEC_LOAD))
 		  {
-		    if (_frvfdpic_osec_readonly_p (output_bfd,
+		    if (_frvfdpic_osec_readonly_p (info->output_bfd,
 						   input_section
 						   ->output_section))
 		      {
@@ -3708,12 +3709,12 @@ elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 		    if (!h || h->root.type != bfd_link_hash_undefweak)
 		      {
 			bfd_vma offset = _bfd_elf_section_offset
-			  (output_bfd, info,
+			  (info->output_bfd, info,
 			   input_section, rel->r_offset);
 
 			if (offset != (bfd_vma)-1)
 			  {
-			    _frvfdpic_add_rofixup (output_bfd,
+			    _frvfdpic_add_rofixup (info->output_bfd,
 						   frvfdpic_gotfixup_section
 						   (info),
 						   offset + input_section
@@ -3722,7 +3723,7 @@ elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 						   picrel);
 			    if (r_type == R_FRV_FUNCDESC_VALUE)
 			      _frvfdpic_add_rofixup
-				(output_bfd,
+				(info->output_bfd,
 				 frvfdpic_gotfixup_section (info),
 				 offset
 				 + input_section->output_section->vma
@@ -3738,7 +3739,7 @@ elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 		  {
 		    bfd_vma offset;
 
-		    if (_frvfdpic_osec_readonly_p (output_bfd,
+		    if (_frvfdpic_osec_readonly_p (info->output_bfd,
 						   input_section
 						   ->output_section))
 		      {
@@ -3750,11 +3751,11 @@ elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 		      }
 
 		    offset = _bfd_elf_section_offset
-		      (output_bfd, info,
+		      (info->output_bfd, info,
 		       input_section, rel->r_offset);
 
 		    if (offset != (bfd_vma)-1)
-		      _frvfdpic_add_dyn_reloc (output_bfd,
+		      _frvfdpic_add_dyn_reloc (info->output_bfd,
 					       frvfdpic_gotrel_section (info),
 					       offset + input_section
 					       ->output_section->vma
@@ -3776,7 +3777,7 @@ elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 		   GOT base offset.  */
 		if (bfd_link_pde (info)
 		    && (!h || FRVFDPIC_SYM_LOCAL (info, h)))
-		  bfd_put_32 (output_bfd,
+		  bfd_put_32 (info->output_bfd,
 			      frvfdpic_got_section (info)->output_section->vma
 			      + frvfdpic_got_section (info)->output_offset
 			      + frvfdpic_got_initial_offset (info),
@@ -3788,10 +3789,10 @@ elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 		     PLT entries are located, and the low word
 		     contains the offset of the lazy PLT entry entry
 		     point into that section.  */
-		  bfd_put_32 (output_bfd,
+		  bfd_put_32 (info->output_bfd,
 			      h && ! FRVFDPIC_SYM_LOCAL (info, h)
 			      ? 0
-			      : _frvfdpic_osec_to_segment (output_bfd,
+			      : _frvfdpic_osec_to_segment (info->output_bfd,
 							   sec
 							   ->output_section),
 			      contents + rel->r_offset + 4);
@@ -3807,7 +3808,7 @@ elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 	case R_FRV_GPRELLO:
 	  check_segment[0] = gprel_segment;
 	  check_segment[1] = sec
-	    ? _frvfdpic_osec_to_segment (output_bfd, sec->output_section)
+	    ? _frvfdpic_osec_to_segment (info->output_bfd, sec->output_section)
 	    : (unsigned)-1;
 	  break;
 
@@ -3830,7 +3831,7 @@ elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 	  check_segment[1] = sec
 	    && ! bfd_is_abs_section (sec)
 	    && ! bfd_is_und_section (sec)
-	    ? _frvfdpic_osec_to_segment (output_bfd, sec->output_section)
+	    ? _frvfdpic_osec_to_segment (info->output_bfd, sec->output_section)
 	    : tls_segment;
 	  break;
 
@@ -3850,8 +3851,8 @@ elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 	  else if (sec->output_section)
 	    {
 	      relocation -= tls_biased_base (info);
-	      check_segment[1] =
-		_frvfdpic_osec_to_segment (output_bfd, sec->output_section);
+	      check_segment[1] = _frvfdpic_osec_to_segment (info->output_bfd,
+							    sec->output_section);
 	    }
 	  else
 	    check_segment[1] = -1;
@@ -3866,7 +3867,7 @@ elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 	  check_segment[1] = sec
 	    && ! bfd_is_abs_section (sec)
 	    && ! bfd_is_und_section (sec)
-	    ? _frvfdpic_osec_to_segment (output_bfd, sec->output_section)
+	    ? _frvfdpic_osec_to_segment (info->output_bfd, sec->output_section)
 	    : tls_segment;
 	  break;
 
@@ -3886,12 +3887,12 @@ elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 	default:
 	  check_segment[0] = isec_segment;
 	  check_segment[1] = sec
-	    ? _frvfdpic_osec_to_segment (output_bfd, sec->output_section)
+	    ? _frvfdpic_osec_to_segment (info->output_bfd, sec->output_section)
 	    : (unsigned)-1;
 	  break;
 	}
 
-      if (check_segment[0] != check_segment[1] && IS_FDPIC (output_bfd))
+      if (check_segment[0] != check_segment[1] && IS_FDPIC (info->output_bfd))
 	{
 	  /* If you take this out, remove the #error from fdpic-static-6.d
 	     in the ld testsuite.  */
@@ -3920,7 +3921,7 @@ elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 	    }
 	  if (!silence_segment_error && bfd_link_pic (info))
 	    return false;
-	  elf_elfheader (output_bfd)->e_flags |= EF_FRV_PIC;
+	  elf_elfheader (info->output_bfd)->e_flags |= EF_FRV_PIC;
 	}
 
       switch (r_type)
@@ -3956,7 +3957,7 @@ elf32_frv_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
       switch (r_type)
 	{
 	case R_FRV_LABEL24:
-	  if (! IS_FDPIC (output_bfd) || ! picrel->plt)
+	  if (! IS_FDPIC (info->output_bfd) || ! picrel->plt)
 	    break;
 	  /* Fall through.  */
 
@@ -4139,8 +4140,7 @@ elf32_frv_add_symbol_hook (bfd *abfd,
 /* We need dynamic symbols for every section, since segments can
    relocate independently.  */
 static bool
-_frvfdpic_link_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
-				    struct bfd_link_info *info
+_frvfdpic_link_omit_section_dynsym (struct bfd_link_info *info
 				    ATTRIBUTE_UNUSED,
 				    asection *p ATTRIBUTE_UNUSED)
 {
@@ -5428,8 +5428,7 @@ _frvfdpic_size_got_plt (bfd *output_bfd,
 /* Set the sizes of the dynamic sections.  */
 
 static bool
-elf32_frvfdpic_late_size_sections (bfd *output_bfd,
-				   struct bfd_link_info *info)
+elf32_frvfdpic_late_size_sections (struct bfd_link_info *info)
 {
   bfd *dynobj;
   asection *s;
@@ -5472,19 +5471,17 @@ elf32_frvfdpic_late_size_sections (bfd *output_bfd,
   dynobj = elf_hash_table (info)->dynobj;
   frvfdpic_dynamic_got_plt_info (info) = bfd_alloc (dynobj, sizeof (gpinfo.g));
 
-  if (!_frvfdpic_size_got_plt (output_bfd, &gpinfo))
+  if (!_frvfdpic_size_got_plt (info->output_bfd, &gpinfo))
     return false;
 
-  return _bfd_elf_add_dynamic_tags (output_bfd, info, true);
+  return _bfd_elf_add_dynamic_tags (info, true);
 }
 
 static bool
-elf32_frvfdpic_early_size_sections (bfd *output_bfd,
-				    struct bfd_link_info *info)
+elf32_frvfdpic_early_size_sections (struct bfd_link_info *info)
 {
   if (!bfd_link_relocatable (info)
-      && !bfd_elf_stack_segment_size (output_bfd, info,
-				      "__stacksize", DEFAULT_STACK_SIZE))
+      && !bfd_elf_stack_segment_size (info, "__stacksize", DEFAULT_STACK_SIZE))
     return false;
 
   return true;
@@ -5684,8 +5681,7 @@ elf32_frvfdpic_relax_section (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
 /* Fill in code and data in dynamic sections.  */
 
 static bool
-elf32_frv_finish_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-				   struct bfd_link_info *info ATTRIBUTE_UNUSED,
+elf32_frv_finish_dynamic_sections (struct bfd_link_info *info ATTRIBUTE_UNUSED,
 				   bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   /* Nothing to be done for non-FDPIC.  */
@@ -5693,8 +5689,7 @@ elf32_frv_finish_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
 }
 
 static bool
-elf32_frvfdpic_finish_dynamic_sections (bfd *output_bfd,
-					struct bfd_link_info *info,
+elf32_frvfdpic_finish_dynamic_sections (struct bfd_link_info *info,
 					bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   bfd *dynobj;
@@ -5720,7 +5715,8 @@ elf32_frvfdpic_finish_dynamic_sections (bfd *output_bfd,
 	    + hgot->root.u.def.section->output_offset;
 	  struct bfd_link_hash_entry *hend;
 
-	  _frvfdpic_add_rofixup (output_bfd, frvfdpic_gotfixup_section (info),
+	  _frvfdpic_add_rofixup (info->output_bfd,
+				 frvfdpic_gotfixup_section (info),
 				 got_value, 0);
 
 	  if (frvfdpic_gotfixup_section (info)->size
@@ -5786,19 +5782,19 @@ elf32_frvfdpic_finish_dynamic_sections (bfd *output_bfd,
 	      dyn.d_un.d_ptr = frvfdpic_got_section (info)->output_section->vma
 		+ frvfdpic_got_section (info)->output_offset
 		+ frvfdpic_got_initial_offset (info);
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    case DT_JMPREL:
 	      dyn.d_un.d_ptr = frvfdpic_pltrel_section (info)
 		->output_section->vma
 		+ frvfdpic_pltrel_section (info)->output_offset;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    case DT_PLTRELSZ:
 	      dyn.d_un.d_val = frvfdpic_pltrel_section (info)->size;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 	    }
 	}
@@ -5845,8 +5841,7 @@ elf32_frvfdpic_adjust_dynamic_symbol
 
 static bool
 elf32_frvfdpic_finish_dynamic_symbol
-(bfd *output_bfd ATTRIBUTE_UNUSED,
- struct bfd_link_info *info ATTRIBUTE_UNUSED,
+(struct bfd_link_info *info ATTRIBUTE_UNUSED,
  struct elf_link_hash_entry *h ATTRIBUTE_UNUSED,
  Elf_Internal_Sym *sym ATTRIBUTE_UNUSED)
 {
diff --git a/bfd/elf32-ft32.c b/bfd/elf32-ft32.c
index c95d2c8f3ef..f2892c266e4 100644
--- a/bfd/elf32-ft32.c
+++ b/bfd/elf32-ft32.c
@@ -342,14 +342,13 @@ ft32_info_to_howto_rela (bfd *abfd,
    accordingly.  */
 
 static int
-ft32_elf_relocate_section (bfd *output_bfd,
-			    struct bfd_link_info *info,
-			    bfd *input_bfd,
-			    asection *input_section,
-			    bfd_byte *contents,
-			    Elf_Internal_Rela *relocs,
-			    Elf_Internal_Sym *local_syms,
-			    asection **local_sections)
+ft32_elf_relocate_section (struct bfd_link_info *info,
+			   bfd *input_bfd,
+			   asection *input_section,
+			   bfd_byte *contents,
+			   Elf_Internal_Rela *relocs,
+			   Elf_Internal_Sym *local_syms,
+			   asection **local_sections)
 {
   Elf_Internal_Shdr *symtab_hdr;
   struct elf_link_hash_entry **sym_hashes;
@@ -383,7 +382,8 @@ ft32_elf_relocate_section (bfd *output_bfd,
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections [r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 
 	  name = bfd_elf_string_from_elf_section
 	    (input_bfd, symtab_hdr->sh_link, sym->st_name);
diff --git a/bfd/elf32-h8300.c b/bfd/elf32-h8300.c
index c690298758d..2ebeada9f52 100644
--- a/bfd/elf32-h8300.c
+++ b/bfd/elf32-h8300.c
@@ -47,10 +47,6 @@ static bfd_reloc_status_type elf32_h8_final_link_relocate
   (unsigned long, bfd *, bfd *, asection *,
    bfd_byte *, bfd_vma, bfd_vma, bfd_vma,
    struct bfd_link_info *, asection *, int);
-static int elf32_h8_relocate_section
-  (bfd *, struct bfd_link_info *, bfd *, asection *,
-   bfd_byte *, Elf_Internal_Rela *,
-   Elf_Internal_Sym *, asection **);
 static bfd_reloc_status_type special
   (bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **);
 
@@ -426,7 +422,7 @@ elf32_h8_final_link_relocate (unsigned long r_type, bfd *input_bfd,
 
 /* Relocate an H8 ELF section.  */
 static int
-elf32_h8_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
+elf32_h8_relocate_section (struct bfd_link_info *info,
 			   bfd *input_bfd, asection *input_section,
 			   bfd_byte *contents, Elf_Internal_Rela *relocs,
 			   Elf_Internal_Sym *local_syms,
@@ -466,7 +462,8 @@ elf32_h8_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections[r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 	}
       else
 	{
@@ -486,7 +483,7 @@ elf32_h8_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
       if (bfd_link_relocatable (info))
 	continue;
 
-      r = elf32_h8_final_link_relocate (r_type, input_bfd, output_bfd,
+      r = elf32_h8_final_link_relocate (r_type, input_bfd, info->output_bfd,
 					input_section,
 					contents, rel->r_offset,
 					relocation, rel->r_addend,
@@ -1681,7 +1678,7 @@ elf32_h8_get_relocated_section_contents (bfd *output_bfd,
 	  *secpp = isec;
 	}
 
-      if (! elf32_h8_relocate_section (output_bfd, link_info, input_bfd,
+      if (! elf32_h8_relocate_section (link_info, input_bfd,
 				       input_section, data, internal_relocs,
 				       isymbuf, sections))
 	goto error_return;
diff --git a/bfd/elf32-hppa.c b/bfd/elf32-hppa.c
index 6b837fe8496..8fb33bc10b8 100644
--- a/bfd/elf32-hppa.c
+++ b/bfd/elf32-hppa.c
@@ -2041,8 +2041,7 @@ clobber_millicode_symbols (struct elf_link_hash_entry *eh,
 /* Set the sizes of the dynamic sections.  */
 
 static bool
-elf32_hppa_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-			       struct bfd_link_info *info)
+elf32_hppa_late_size_sections (struct bfd_link_info *info)
 {
   struct elf32_hppa_link_hash_table *htab;
   bfd *dynobj;
@@ -2274,7 +2273,7 @@ elf32_hppa_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
       sec->alloced = 1;
     }
 
-  return _bfd_elf_add_dynamic_tags (output_bfd, info, relocs);
+  return _bfd_elf_add_dynamic_tags (info, relocs);
 }
 
 /* External entry points for sizing and building linker stubs.  */
@@ -3500,8 +3499,7 @@ final_link_relocate (asection *input_section,
 /* Relocate an HPPA ELF section.  */
 
 static int
-elf32_hppa_relocate_section (bfd *output_bfd,
-			     struct bfd_link_info *info,
+elf32_hppa_relocate_section (struct bfd_link_info *info,
 			     bfd *input_bfd,
 			     asection *input_section,
 			     bfd_byte *contents,
@@ -3559,7 +3557,8 @@ elf32_hppa_relocate_section (bfd *output_bfd,
 	  /* This is a local symbol, h defaults to NULL.  */
 	  sym = local_syms + r_symndx;
 	  sym_sec = local_sections[r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sym_sec, rela);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sym_sec, rela);
 	}
       else
 	{
@@ -3685,10 +3684,10 @@ elf32_hppa_relocate_section (bfd *output_bfd,
 		    outrel.r_addend = relocation;
 		    loc = sec->contents;
 		    loc += sec->reloc_count++ * sizeof (Elf32_External_Rela);
-		    bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+		    bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 		  }
 		else
-		  bfd_put_32 (output_bfd, relocation,
+		  bfd_put_32 (info->output_bfd, relocation,
 			      htab->etab.sgot->contents + off);
 	      }
 
@@ -3706,7 +3705,8 @@ elf32_hppa_relocate_section (bfd *output_bfd,
 	  /* If this is the first SEGREL relocation, then initialize
 	     the segment base values.  */
 	  if (htab->text_segment_base == (bfd_vma) -1)
-	    bfd_map_over_sections (output_bfd, hppa_record_segment_addr, htab);
+	    bfd_map_over_sections (info->output_bfd,
+				   hppa_record_segment_addr, htab);
 	  break;
 
 	case R_PARISC_PLABEL14R:
@@ -3776,14 +3776,14 @@ elf32_hppa_relocate_section (bfd *output_bfd,
 		      outrel.r_addend = relocation;
 		      loc = s->contents;
 		      loc += s->reloc_count++ * sizeof (Elf32_External_Rela);
-		      bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+		      bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 		    }
 		  else
 		    {
-		      bfd_put_32 (output_bfd,
+		      bfd_put_32 (info->output_bfd,
 				  relocation,
 				  htab->etab.splt->contents + off);
-		      bfd_put_32 (output_bfd,
+		      bfd_put_32 (info->output_bfd,
 				  elf_gp (htab->etab.splt->output_section->owner),
 				  htab->etab.splt->contents + off + 4);
 		    }
@@ -3842,7 +3842,7 @@ elf32_hppa_relocate_section (bfd *output_bfd,
 
 	      outrel.r_addend = rela->r_addend;
 	      outrel.r_offset =
-		_bfd_elf_section_offset (output_bfd, info, input_section,
+		_bfd_elf_section_offset (info->output_bfd, info, input_section,
 					 rela->r_offset);
 	      skip = (outrel.r_offset == (bfd_vma) -1
 		      || outrel.r_offset == (bfd_vma) -2);
@@ -3907,7 +3907,7 @@ elf32_hppa_relocate_section (bfd *output_bfd,
 
 	      loc = sreloc->contents;
 	      loc += sreloc->reloc_count++ * sizeof (Elf32_External_Rela);
-	      bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+	      bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 	    }
 	  break;
 
@@ -3932,7 +3932,7 @@ elf32_hppa_relocate_section (bfd *output_bfd,
 		loc = htab->etab.srelgot->contents;
 		loc += htab->etab.srelgot->reloc_count++ * sizeof (Elf32_External_Rela);
 
-		bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+		bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 		htab->tls_ldm_got.offset |= 1;
 	      }
 
@@ -4019,10 +4019,11 @@ elf32_hppa_relocate_section (bfd *output_bfd,
 			outrel.r_info
 			  = ELF32_R_INFO (indx, R_PARISC_TLS_DTPMOD32);
 			outrel.r_addend = 0;
-			bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+			bfd_elf32_swap_reloca_out (info->output_bfd,
+						   &outrel, loc);
 			htab->etab.srelgot->reloc_count++;
 			loc += sizeof (Elf32_External_Rela);
-			bfd_put_32 (output_bfd, 0,
+			bfd_put_32 (info->output_bfd, 0,
 				    htab->etab.sgot->contents + cur_off);
 		      }
 		    else
@@ -4031,7 +4032,7 @@ elf32_hppa_relocate_section (bfd *output_bfd,
 			 static link or an executable link with the
 			 symbol binding locally.  Mark it as belonging
 			 to module 1, the executable.  */
-		      bfd_put_32 (output_bfd, 1,
+		      bfd_put_32 (info->output_bfd, 1,
 				  htab->etab.sgot->contents + cur_off);
 
 		    if (indx != 0)
@@ -4039,14 +4040,16 @@ elf32_hppa_relocate_section (bfd *output_bfd,
 			outrel.r_info
 			  = ELF32_R_INFO (indx, R_PARISC_TLS_DTPOFF32);
 			outrel.r_offset += 4;
-			bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+			bfd_elf32_swap_reloca_out (info->output_bfd,
+						   &outrel, loc);
 			htab->etab.srelgot->reloc_count++;
 			loc += sizeof (Elf32_External_Rela);
-			bfd_put_32 (output_bfd, 0,
+			bfd_put_32 (info->output_bfd, 0,
 				    htab->etab.sgot->contents + cur_off + 4);
 		      }
 		    else
-		      bfd_put_32 (output_bfd, relocation - dtpoff_base (info),
+		      bfd_put_32 (info->output_bfd,
+				  relocation - dtpoff_base (info),
 				  htab->etab.sgot->contents + cur_off + 4);
 		    cur_off += 8;
 		  }
@@ -4067,12 +4070,13 @@ elf32_hppa_relocate_section (bfd *output_bfd,
 			  outrel.r_addend = relocation - dtpoff_base (info);
 			else
 			  outrel.r_addend = 0;
-			bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+			bfd_elf32_swap_reloca_out (info->output_bfd,
+						   &outrel, loc);
 			htab->etab.srelgot->reloc_count++;
 			loc += sizeof (Elf32_External_Rela);
 		      }
 		    else
-		      bfd_put_32 (output_bfd, tpoff (info, relocation),
+		      bfd_put_32 (info->output_bfd, tpoff (info, relocation),
 				  htab->etab.sgot->contents + cur_off);
 		    cur_off += 4;
 		  }
@@ -4187,8 +4191,7 @@ elf32_hppa_relocate_section (bfd *output_bfd,
    dynamic sections here.  */
 
 static bool
-elf32_hppa_finish_dynamic_symbol (bfd *output_bfd,
-				  struct bfd_link_info *info,
+elf32_hppa_finish_dynamic_symbol (struct bfd_link_info *info,
 				  struct elf_link_hash_entry *eh,
 				  Elf_Internal_Sym *sym)
 {
@@ -4286,7 +4289,7 @@ elf32_hppa_finish_dynamic_symbol (bfd *output_bfd,
 	      if ((eh->got.offset & 1) != 0)
 		abort ();
 
-	      bfd_put_32 (output_bfd, 0,
+	      bfd_put_32 (info->output_bfd, 0,
 			  htab->etab.sgot->contents + (eh->got.offset & ~1));
 	      rela.r_info = ELF32_R_INFO (eh->dynindx, R_PARISC_DIR32);
 	      rela.r_addend = 0;
@@ -4295,7 +4298,7 @@ elf32_hppa_finish_dynamic_symbol (bfd *output_bfd,
 	  loc = htab->etab.srelgot->contents;
 	  loc += (htab->etab.srelgot->reloc_count++
 		  * sizeof (Elf32_External_Rela));
-	  bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+	  bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
 	}
     }
 
@@ -4320,7 +4323,7 @@ elf32_hppa_finish_dynamic_symbol (bfd *output_bfd,
       else
 	sec = htab->etab.srelbss;
       loc = sec->contents + sec->reloc_count++ * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
     }
 
   /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute.  */
@@ -4368,8 +4371,7 @@ elf32_hppa_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
 /* Finish up the dynamic sections.  */
 
 static bool
-elf32_hppa_finish_dynamic_sections (bfd *output_bfd,
-				    struct bfd_link_info *info,
+elf32_hppa_finish_dynamic_sections (struct bfd_link_info *info,
 				    bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   bfd *dynobj;
@@ -4414,7 +4416,7 @@ elf32_hppa_finish_dynamic_sections (bfd *output_bfd,
 
 	    case DT_PLTGOT:
 	      /* Use PLTGOT to set the GOT register.  */
-	      dyn.d_un.d_ptr = elf_gp (output_bfd);
+	      dyn.d_un.d_ptr = elf_gp (info->output_bfd);
 	      break;
 
 	    case DT_JMPREL:
@@ -4428,7 +4430,7 @@ elf32_hppa_finish_dynamic_sections (bfd *output_bfd,
 	      break;
 	    }
 
-	  bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	  bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	}
     }
 
@@ -4436,7 +4438,7 @@ elf32_hppa_finish_dynamic_sections (bfd *output_bfd,
     {
       /* Fill in the first entry in the global offset table.
 	 We use it to point to our dynamic section, if we have one.  */
-      bfd_put_32 (output_bfd,
+      bfd_put_32 (info->output_bfd,
 		  sdyn ? sdyn->output_section->vma + sdyn->output_offset : 0,
 		  sgot->contents);
 
diff --git a/bfd/elf32-i386.c b/bfd/elf32-i386.c
index 9e27bed51c6..954803fcc3f 100644
--- a/bfd/elf32-i386.c
+++ b/bfd/elf32-i386.c
@@ -2035,7 +2035,7 @@ elf_i386_scan_relocs (bfd *abfd,
 }
 
 static bool
-elf_i386_early_size_sections (bfd *output_bfd, struct bfd_link_info *info)
+elf_i386_early_size_sections (struct bfd_link_info *info)
 {
   bfd *abfd;
 
@@ -2048,7 +2048,7 @@ elf_i386_early_size_sections (bfd *output_bfd, struct bfd_link_info *info)
 					     elf_i386_scan_relocs))
       return false;
 
-  return _bfd_x86_elf_early_size_sections (output_bfd, info);
+  return _bfd_x86_elf_early_size_sections (info);
 }
 
 /* Set the correct type for an x86 ELF section.  We do this by the
@@ -2107,8 +2107,7 @@ elf_i386_tpoff (struct bfd_link_info *info, bfd_vma address)
 /* Relocate an i386 ELF section.  */
 
 static int
-elf_i386_relocate_section (bfd *output_bfd,
-			   struct bfd_link_info *info,
+elf_i386_relocate_section (struct bfd_link_info *info,
 			   bfd *input_bfd,
 			   asection *input_section,
 			   bfd_byte *contents,
@@ -2249,7 +2248,7 @@ elf_i386_relocate_section (bfd *output_bfd,
 	      else
 		{
 		  asection *msec = sec;
-		  addend = _bfd_elf_rel_local_sym (output_bfd, sym, &msec,
+		  addend = _bfd_elf_rel_local_sym (info->output_bfd, sym, &msec,
 						   addend);
 		  addend -= relocation;
 		  addend += msec->output_section->vma + msec->output_offset;
@@ -2427,7 +2426,7 @@ elf_i386_relocate_section (bfd *output_bfd,
 			off &= ~1;
 		      else
 			{
-			  bfd_put_32 (output_bfd, relocation,
+			  bfd_put_32 (info->output_bfd, relocation,
 				      base_got->contents + off);
 			  h->got.offset |= 1;
 			}
@@ -2503,7 +2502,7 @@ elf_i386_relocate_section (bfd *output_bfd,
 		do_ifunc_pointer:
 		  /* Need a dynamic relocation to get the real function
 		     adddress.  */
-		  offset = _bfd_elf_section_offset (output_bfd,
+		  offset = _bfd_elf_section_offset (info->output_bfd,
 						    info,
 						    input_section,
 						    rel->r_offset);
@@ -2529,7 +2528,7 @@ elf_i386_relocate_section (bfd *output_bfd,
 			  (info, input_section, h, sym,
 			   "R_386_IRELATIVE", &outrel);
 
-		      bfd_put_32 (output_bfd,
+		      bfd_put_32 (info->output_bfd,
 				  (h->root.u.def.value
 				   + h->root.u.def.section->output_section->vma
 				   + h->root.u.def.section->output_offset),
@@ -2548,7 +2547,7 @@ elf_i386_relocate_section (bfd *output_bfd,
 		    sreloc = htab->elf.srelgot;
 		  else
 		    sreloc = htab->elf.irelplt;
-		  _bfd_elf_append_rel (output_bfd, sreloc, &outrel);
+		  _bfd_elf_append_rel (info->output_bfd, sreloc, &outrel);
 
 		  /* If this reloc is against an external symbol, we
 		     do not want to fiddle with the addend.  Otherwise,
@@ -2605,7 +2604,7 @@ elf_i386_relocate_section (bfd *output_bfd,
 		    off &= ~1;
 		  else
 		    {
-		      bfd_put_32 (output_bfd, relocation,
+		      bfd_put_32 (info->output_bfd, relocation,
 				  htab->elf.sgot->contents + off);
 		      h->got.offset |= 1;
 		      /* NB: Don't generate relative relocation here if
@@ -2637,7 +2636,7 @@ elf_i386_relocate_section (bfd *output_bfd,
 		off &= ~1;
 	      else
 		{
-		  bfd_put_32 (output_bfd, relocation,
+		  bfd_put_32 (info->output_bfd, relocation,
 			      htab->elf.sgot->contents + off);
 		  local_got_offsets[r_symndx] |= 1;
 
@@ -2667,7 +2666,7 @@ elf_i386_relocate_section (bfd *output_bfd,
 		  (info, input_section, h, sym, "R_386_RELATIVE",
 		   &outrel);
 
-	      _bfd_elf_append_rel (output_bfd, s, &outrel);
+	      _bfd_elf_append_rel (info->output_bfd, s, &outrel);
 	    }
 
 	  if (off >= (bfd_vma) -2)
@@ -2857,8 +2856,8 @@ elf_i386_relocate_section (bfd *output_bfd,
 	      relocate = false;
 
 	      outrel.r_offset =
-		_bfd_elf_section_offset (output_bfd, info, input_section,
-					 rel->r_offset);
+		_bfd_elf_section_offset (info->output_bfd, info,
+					 input_section, rel->r_offset);
 	      if (outrel.r_offset == (bfd_vma) -1)
 		skip = true;
 	      else if (outrel.r_offset == (bfd_vma) -2)
@@ -2899,7 +2898,7 @@ elf_i386_relocate_section (bfd *output_bfd,
 		      goto check_relocation_error;
 		    }
 
-		  _bfd_elf_append_rel (output_bfd, sreloc, &outrel);
+		  _bfd_elf_append_rel (info->output_bfd, sreloc, &outrel);
 		}
 
 	      /* If this reloc is against an external symbol, we do
@@ -2930,7 +2929,7 @@ elf_i386_relocate_section (bfd *output_bfd,
 	      sreloc = elf_section_data (input_section)->sreloc;
 	      if (sreloc == NULL)
 		abort ();
-	      _bfd_elf_append_rel (output_bfd, sreloc, &outrel);
+	      _bfd_elf_append_rel (info->output_bfd, sreloc, &outrel);
 	    }
 	  /* Fall through */
 
@@ -3002,7 +3001,8 @@ elf_i386_relocate_section (bfd *output_bfd,
 		    }
 		  memcpy (contents + roff - 8,
 			  "\x65\xa1\0\0\0\0\x81\xe8\0\0\0", 12);
-		  bfd_put_32 (output_bfd, elf_i386_tpoff (info, relocation),
+		  bfd_put_32 (info->output_bfd,
+			      elf_i386_tpoff (info, relocation),
 			      contents + roff);
 		  /* Skip R_386_PC32, R_386_PLT32 and R_386_GOT32X.  */
 		  rel++;
@@ -3028,9 +3028,10 @@ elf_i386_relocate_section (bfd *output_bfd,
 		  /* Now modify the instruction as appropriate.  */
 		  /* aoliva FIXME: remove the above and xor the byte
 		     below with 0x86.  */
-		  bfd_put_8 (output_bfd, val ^ 0x86,
+		  bfd_put_8 (info->output_bfd, val ^ 0x86,
 			     contents + roff - 1);
-		  bfd_put_32 (output_bfd, -elf_i386_tpoff (info, relocation),
+		  bfd_put_32 (info->output_bfd,
+			      -elf_i386_tpoff (info, relocation),
 			      contents + roff);
 		  continue;
 		}
@@ -3045,8 +3046,8 @@ elf_i386_relocate_section (bfd *output_bfd,
 		  bfd_vma roff;
 
 		  roff = rel->r_offset;
-		  bfd_put_8 (output_bfd, 0x66, contents + roff);
-		  bfd_put_8 (output_bfd, 0x90, contents + roff + 1);
+		  bfd_put_8 (info->output_bfd, 0x66, contents + roff);
+		  bfd_put_8 (info->output_bfd, 0x90, contents + roff + 1);
 		  continue;
 		}
 	      else if (r_type == R_386_TLS_IE)
@@ -3066,7 +3067,7 @@ elf_i386_relocate_section (bfd *output_bfd,
 		  if (val == 0xa1)
 		    {
 		      /* movl foo, %eax.  */
-		      bfd_put_8 (output_bfd, 0xb8,
+		      bfd_put_8 (info->output_bfd, 0xb8,
 				 contents + rel->r_offset - 1);
 		    }
 		  else
@@ -3079,17 +3080,17 @@ elf_i386_relocate_section (bfd *output_bfd,
 			{
 			case 0x8b:
 			  /* movl */
-			  bfd_put_8 (output_bfd, 0xc7,
+			  bfd_put_8 (info->output_bfd, 0xc7,
 				     contents + rel->r_offset - 2);
-			  bfd_put_8 (output_bfd,
+			  bfd_put_8 (info->output_bfd,
 				     0xc0 | ((val >> 3) & 7),
 				     contents + rel->r_offset - 1);
 			  break;
 			case 0x03:
 			  /* addl */
-			  bfd_put_8 (output_bfd, 0x81,
+			  bfd_put_8 (info->output_bfd, 0x81,
 				     contents + rel->r_offset - 2);
-			  bfd_put_8 (output_bfd,
+			  bfd_put_8 (info->output_bfd,
 				     0xc0 | ((val >> 3) & 7),
 				     contents + rel->r_offset - 1);
 			  break;
@@ -3098,7 +3099,8 @@ elf_i386_relocate_section (bfd *output_bfd,
 			  break;
 			}
 		    }
-		  bfd_put_32 (output_bfd, -elf_i386_tpoff (info, relocation),
+		  bfd_put_32 (info->output_bfd,
+			      -elf_i386_tpoff (info, relocation),
 			      contents + rel->r_offset);
 		  continue;
 		}
@@ -3120,34 +3122,36 @@ elf_i386_relocate_section (bfd *output_bfd,
 		  if (type == 0x8b)
 		    {
 		      /* movl */
-		      bfd_put_8 (output_bfd, 0xc7,
+		      bfd_put_8 (info->output_bfd, 0xc7,
 				 contents + rel->r_offset - 2);
-		      bfd_put_8 (output_bfd, 0xc0 | ((val >> 3) & 7),
+		      bfd_put_8 (info->output_bfd, 0xc0 | ((val >> 3) & 7),
 				 contents + rel->r_offset - 1);
 		    }
 		  else if (type == 0x2b)
 		    {
 		      /* subl */
-		      bfd_put_8 (output_bfd, 0x81,
+		      bfd_put_8 (info->output_bfd, 0x81,
 				 contents + rel->r_offset - 2);
-		      bfd_put_8 (output_bfd, 0xe8 | ((val >> 3) & 7),
+		      bfd_put_8 (info->output_bfd, 0xe8 | ((val >> 3) & 7),
 				 contents + rel->r_offset - 1);
 		    }
 		  else if (type == 0x03)
 		    {
 		      /* addl */
-		      bfd_put_8 (output_bfd, 0x81,
+		      bfd_put_8 (info->output_bfd, 0x81,
 				 contents + rel->r_offset - 2);
-		      bfd_put_8 (output_bfd, 0xc0 | ((val >> 3) & 7),
+		      bfd_put_8 (info->output_bfd, 0xc0 | ((val >> 3) & 7),
 				 contents + rel->r_offset - 1);
 		    }
 		  else
 		    BFD_FAIL ();
 		  if (r_type == R_386_TLS_GOTIE)
-		    bfd_put_32 (output_bfd, -elf_i386_tpoff (info, relocation),
+		    bfd_put_32 (info->output_bfd,
+				-elf_i386_tpoff (info, relocation),
 				contents + rel->r_offset);
 		  else
-		    bfd_put_32 (output_bfd, elf_i386_tpoff (info, relocation),
+		    bfd_put_32 (info->output_bfd,
+				elf_i386_tpoff (info, relocation),
 				contents + rel->r_offset);
 		  continue;
 		}
@@ -3193,18 +3197,18 @@ elf_i386_relocate_section (bfd *output_bfd,
 				     + offplt
 				     + htab->sgotplt_jump_table_size);
 		  sreloc = htab->rel_tls_desc;
-		  _bfd_elf_append_rel (output_bfd, sreloc, &outrel);
+		  _bfd_elf_append_rel (info->output_bfd, sreloc, &outrel);
 		  if (indx == 0)
 		    {
 		      BFD_ASSERT (! unresolved_reloc);
-		      bfd_put_32 (output_bfd,
+		      bfd_put_32 (info->output_bfd,
 				  relocation - _bfd_x86_elf_dtpoff_base (info),
 				  htab->elf.sgotplt->contents + offplt
 				  + htab->sgotplt_jump_table_size + 4);
 		    }
 		  else
 		    {
-		      bfd_put_32 (output_bfd, 0,
+		      bfd_put_32 (info->output_bfd, 0,
 				  htab->elf.sgotplt->contents + offplt
 				  + htab->sgotplt_jump_table_size + 4);
 		    }
@@ -3225,49 +3229,49 @@ elf_i386_relocate_section (bfd *output_bfd,
 		dr_type = R_386_TLS_TPOFF32;
 
 	      if (dr_type == R_386_TLS_TPOFF && indx == 0)
-		bfd_put_32 (output_bfd,
+		bfd_put_32 (info->output_bfd,
 			    relocation - _bfd_x86_elf_dtpoff_base (info),
 			    htab->elf.sgot->contents + off);
 	      else if (dr_type == R_386_TLS_TPOFF32 && indx == 0)
-		bfd_put_32 (output_bfd,
+		bfd_put_32 (info->output_bfd,
 			    _bfd_x86_elf_dtpoff_base (info) - relocation,
 			    htab->elf.sgot->contents + off);
 	      else if (dr_type != R_386_TLS_DESC)
-		bfd_put_32 (output_bfd, 0,
+		bfd_put_32 (info->output_bfd, 0,
 			    htab->elf.sgot->contents + off);
 	      outrel.r_info = ELF32_R_INFO (indx, dr_type);
 
-	      _bfd_elf_append_rel (output_bfd, sreloc, &outrel);
+	      _bfd_elf_append_rel (info->output_bfd, sreloc, &outrel);
 
 	      if (GOT_TLS_GD_P (tls_type))
 		{
 		  if (indx == 0)
 		    {
 		      BFD_ASSERT (! unresolved_reloc);
-		      bfd_put_32 (output_bfd,
+		      bfd_put_32 (info->output_bfd,
 				  relocation - _bfd_x86_elf_dtpoff_base (info),
 				  htab->elf.sgot->contents + off + 4);
 		    }
 		  else
 		    {
-		      bfd_put_32 (output_bfd, 0,
+		      bfd_put_32 (info->output_bfd, 0,
 				  htab->elf.sgot->contents + off + 4);
 		      outrel.r_info = ELF32_R_INFO (indx,
 						    R_386_TLS_DTPOFF32);
 		      outrel.r_offset += 4;
-		      _bfd_elf_append_rel (output_bfd, sreloc, &outrel);
+		      _bfd_elf_append_rel (info->output_bfd, sreloc, &outrel);
 		    }
 		}
 	      else if (tls_type == GOT_TLS_IE_BOTH)
 		{
-		  bfd_put_32 (output_bfd,
+		  bfd_put_32 (info->output_bfd,
 			      (indx == 0
 			       ? relocation - _bfd_x86_elf_dtpoff_base (info)
 			       : 0),
 			      htab->elf.sgot->contents + off + 4);
 		  outrel.r_info = ELF32_R_INFO (indx, R_386_TLS_TPOFF);
 		  outrel.r_offset += 4;
-		  _bfd_elf_append_rel (output_bfd, sreloc, &outrel);
+		  _bfd_elf_append_rel (info->output_bfd, sreloc, &outrel);
 		}
 
 	    dr_done:
@@ -3344,7 +3348,7 @@ elf_i386_relocate_section (bfd *output_bfd,
 		 addl $foo@gotntpoff(%reg), %eax.  */
 	      if (tls_type == GOT_TLS_IE_POS)
 		contents[roff + 6] = 0x03;
-	      bfd_put_32 (output_bfd,
+	      bfd_put_32 (info->output_bfd,
 			  htab->elf.sgot->output_section->vma
 			  + htab->elf.sgot->output_offset + off
 			  - htab->elf.sgotplt->output_section->vma
@@ -3381,12 +3385,12 @@ elf_i386_relocate_section (bfd *output_bfd,
 		 aoliva FIXME: should we decide to keep the leal, all
 		 we have to do is remove the statement below, and
 		 adjust the relaxation of R_386_TLS_DESC_CALL.  */
-	      bfd_put_8 (output_bfd, 0x8b, contents + roff - 2);
+	      bfd_put_8 (info->output_bfd, 0x8b, contents + roff - 2);
 
 	      if (tls_type == GOT_TLS_IE_BOTH)
 		off += 4;
 
-	      bfd_put_32 (output_bfd,
+	      bfd_put_32 (info->output_bfd,
 			  htab->elf.sgot->output_section->vma
 			  + htab->elf.sgot->output_offset + off
 			  - htab->elf.sgotplt->output_section->vma
@@ -3415,14 +3419,14 @@ elf_i386_relocate_section (bfd *output_bfd,
 	      if (tls_type != GOT_TLS_IE_NEG)
 		{
 		  /* xchg %ax,%ax */
-		  bfd_put_8 (output_bfd, 0x66, contents + roff);
-		  bfd_put_8 (output_bfd, 0x90, contents + roff + 1);
+		  bfd_put_8 (info->output_bfd, 0x66, contents + roff);
+		  bfd_put_8 (info->output_bfd, 0x90, contents + roff + 1);
 		}
 	      else
 		{
 		  /* negl %eax */
-		  bfd_put_8 (output_bfd, 0xf7, contents + roff);
-		  bfd_put_8 (output_bfd, 0xd8, contents + roff + 1);
+		  bfd_put_8 (info->output_bfd, 0xf7, contents + roff);
+		  bfd_put_8 (info->output_bfd, 0xd8, contents + roff + 1);
 		}
 
 	      continue;
@@ -3488,12 +3492,12 @@ elf_i386_relocate_section (bfd *output_bfd,
 	      outrel.r_offset = (htab->elf.sgot->output_section->vma
 				 + htab->elf.sgot->output_offset + off);
 
-	      bfd_put_32 (output_bfd, 0,
+	      bfd_put_32 (info->output_bfd, 0,
 			  htab->elf.sgot->contents + off);
-	      bfd_put_32 (output_bfd, 0,
+	      bfd_put_32 (info->output_bfd, 0,
 			  htab->elf.sgot->contents + off + 4);
 	      outrel.r_info = ELF32_R_INFO (0, R_386_TLS_DTPMOD32);
-	      _bfd_elf_append_rel (output_bfd, htab->elf.srelgot, &outrel);
+	      _bfd_elf_append_rel (info->output_bfd, htab->elf.srelgot, &outrel);
 	      htab->tls_ld_or_ldm_got.offset |= 1;
 	    }
 	  relocation = htab->elf.sgot->output_section->vma
@@ -3533,7 +3537,7 @@ elf_i386_relocate_section (bfd *output_bfd,
 	      sreloc = elf_section_data (input_section)->sreloc;
 	      if (sreloc == NULL)
 		abort ();
-	      _bfd_elf_append_rel (output_bfd, sreloc, &outrel);
+	      _bfd_elf_append_rel (info->output_bfd, sreloc, &outrel);
 	      if (indx)
 		continue;
 	      else if (r_type == R_386_TLS_LE_32)
@@ -3557,7 +3561,7 @@ elf_i386_relocate_section (bfd *output_bfd,
       if (unresolved_reloc
 	  && !((input_section->flags & SEC_DEBUGGING) != 0
 	       && h->def_dynamic)
-	  && _bfd_elf_section_offset (output_bfd, info, input_section,
+	  && _bfd_elf_section_offset (info->output_bfd, info, input_section,
 				      rel->r_offset) != (bfd_vma) -1)
 	{
 	  _bfd_error_handler
@@ -3632,8 +3636,7 @@ elf_i386_relocate_section (bfd *output_bfd,
    dynamic sections here.  */
 
 static bool
-elf_i386_finish_dynamic_symbol (bfd *output_bfd,
-				struct bfd_link_info *info,
+elf_i386_finish_dynamic_symbol (struct bfd_link_info *info,
 				struct elf_link_hash_entry *h,
 				Elf_Internal_Sym *sym)
 {
@@ -3733,7 +3736,7 @@ elf_i386_finish_dynamic_symbol (bfd *output_bfd,
 
       if (! bfd_link_pic (info))
 	{
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 		      (gotplt->output_section->vma
 		       + gotplt->output_offset
 		       + got_offset),
@@ -3765,7 +3768,7 @@ elf_i386_finish_dynamic_symbol (bfd *output_bfd,
 			      + plt->output_offset
 			      + h->plt.offset + 2),
 	      rel.r_info = ELF32_R_INFO (htab->elf.hgot->indx, R_386_32);
-	      bfd_elf32_swap_reloc_out (output_bfd, &rel, loc);
+	      bfd_elf32_swap_reloc_out (info->output_bfd, &rel, loc);
 
 	      /* Create the R_386_32 relocation referencing the beginning of
 		 the PLT for this GOT entry.  */
@@ -3773,13 +3776,13 @@ elf_i386_finish_dynamic_symbol (bfd *output_bfd,
 			      + htab->elf.sgotplt->output_offset
 			      + got_offset);
 	      rel.r_info = ELF32_R_INFO (htab->elf.hplt->indx, R_386_32);
-	      bfd_elf32_swap_reloc_out (output_bfd, &rel,
+	      bfd_elf32_swap_reloc_out (info->output_bfd, &rel,
 					loc + sizeof (Elf32_External_Rel));
 	    }
 	}
       else
 	{
-	  bfd_put_32 (output_bfd, got_offset,
+	  bfd_put_32 (info->output_bfd, got_offset,
 		      resolved_plt->contents + plt_offset
 		      + htab->plt.plt_got_offset);
 	}
@@ -3790,7 +3793,7 @@ elf_i386_finish_dynamic_symbol (bfd *output_bfd,
       if (!local_undefweak)
 	{
 	  if (htab->plt.has_plt0)
-	    bfd_put_32 (output_bfd,
+	    bfd_put_32 (info->output_bfd,
 			(plt->output_section->vma
 			 + plt->output_offset
 			 + h->plt.offset
@@ -3810,7 +3813,7 @@ elf_i386_finish_dynamic_symbol (bfd *output_bfd,
 	      /* If an STT_GNU_IFUNC symbol is locally defined, generate
 		 R_386_IRELATIVE instead of R_386_JUMP_SLOT.  Store addend
 		 in the .got.plt section.  */
-	      bfd_put_32 (output_bfd,
+	      bfd_put_32 (info->output_bfd,
 			  (h->root.u.def.value
 			   + h->root.u.def.section->output_section->vma
 			   + h->root.u.def.section->output_offset),
@@ -3831,17 +3834,17 @@ elf_i386_finish_dynamic_symbol (bfd *output_bfd,
 	    }
 
 	  loc = relplt->contents + plt_index * sizeof (Elf32_External_Rel);
-	  bfd_elf32_swap_reloc_out (output_bfd, &rel, loc);
+	  bfd_elf32_swap_reloc_out (info->output_bfd, &rel, loc);
 
 	  /* Don't fill the second and third slots in PLT entry for
 	     static executables nor without PLT0.  */
 	  if (plt == htab->elf.splt && htab->plt.has_plt0)
 	    {
-	      bfd_put_32 (output_bfd,
+	      bfd_put_32 (info->output_bfd,
 			  plt_index * sizeof (Elf32_External_Rel),
 			  plt->contents + h->plt.offset
 			  + htab->lazy_plt->plt_reloc_offset);
-	      bfd_put_32 (output_bfd,
+	      bfd_put_32 (info->output_bfd,
 			  - (h->plt.offset
 			     + htab->lazy_plt->plt_plt_offset + 4),
 			  (plt->contents + h->plt.offset
@@ -3885,7 +3888,7 @@ elf_i386_finish_dynamic_symbol (bfd *output_bfd,
       plt_offset = eh->plt_got.offset;
       memcpy (plt->contents + plt_offset, got_plt_entry,
 	      htab->non_lazy_plt->plt_entry_size);
-      bfd_put_32 (output_bfd, got_offset,
+      bfd_put_32 (info->output_bfd, got_offset,
 		  (plt->contents + plt_offset
 		   + htab->non_lazy_plt->plt_got_offset));
     }
@@ -3955,7 +3958,7 @@ elf_i386_finish_dynamic_symbol (bfd *output_bfd,
 					  h->root.root.string,
 					  h->root.u.def.section->owner);
 
-		  bfd_put_32 (output_bfd,
+		  bfd_put_32 (info->output_bfd,
 			      (h->root.u.def.value
 			       + h->root.u.def.section->output_section->vma
 			       + h->root.u.def.section->output_offset),
@@ -3992,7 +3995,7 @@ elf_i386_finish_dynamic_symbol (bfd *output_bfd,
 		  plt = htab->elf.splt ? htab->elf.splt : htab->elf.iplt;
 		  plt_offset = h->plt.offset;
 		}
-	      bfd_put_32 (output_bfd,
+	      bfd_put_32 (info->output_bfd,
 			  (plt->output_section->vma
 			   + plt->output_offset + plt_offset),
 			  htab->elf.sgot->contents + h->got.offset);
@@ -4015,7 +4018,7 @@ elf_i386_finish_dynamic_symbol (bfd *output_bfd,
 	{
 	  BFD_ASSERT((h->got.offset & 1) == 0);
 	do_glob_dat:
-	  bfd_put_32 (output_bfd, (bfd_vma) 0,
+	  bfd_put_32 (info->output_bfd, 0,
 		      htab->elf.sgot->contents + h->got.offset);
 	  rel.r_info = ELF32_R_INFO (h->dynindx, R_386_GLOB_DAT);
 	}
@@ -4027,7 +4030,7 @@ elf_i386_finish_dynamic_symbol (bfd *output_bfd,
 	    _bfd_x86_elf_link_report_relative_reloc
 	      (info, relgot, h, sym, relative_reloc_name, &rel);
 
-	  _bfd_elf_append_rel (output_bfd, relgot, &rel);
+	  _bfd_elf_append_rel (info->output_bfd, relgot, &rel);
 	}
     }
 
@@ -4047,7 +4050,7 @@ elf_i386_finish_dynamic_symbol (bfd *output_bfd,
 	s = htab->elf.sreldynrelro;
       else
 	s = htab->elf.srelbss;
-      _bfd_elf_append_rel (output_bfd, s, &rel);
+      _bfd_elf_append_rel (info->output_bfd, s, &rel);
     }
 
   return true;
@@ -4064,8 +4067,7 @@ elf_i386_finish_local_dynamic_symbol (void **slot, void *inf)
   struct bfd_link_info *info
     = (struct bfd_link_info *) inf;
 
-  return elf_i386_finish_dynamic_symbol (info->output_bfd, info,
-					 h, NULL);
+  return elf_i386_finish_dynamic_symbol (info, h, NULL);
 }
 
 /* Finish up undefined weak symbol handling in PIE.  Fill its PLT entry
@@ -4083,8 +4085,7 @@ elf_i386_pie_finish_undefweak_symbol (struct bfd_hash_entry *bh,
       || h->dynindx != -1)
     return true;
 
-  return elf_i386_finish_dynamic_symbol (info->output_bfd,
-					 info, h, NULL);
+  return elf_i386_finish_dynamic_symbol (info, h, NULL);
 }
 
 /* Used to decide how to sort relocs in an optimal manner for the
@@ -4137,13 +4138,12 @@ elf_i386_reloc_type_class (const struct bfd_link_info *info,
 /* Finish up the dynamic sections.  */
 
 static bool
-elf_i386_finish_dynamic_sections (bfd *output_bfd,
-				  struct bfd_link_info *info,
+elf_i386_finish_dynamic_sections (struct bfd_link_info *info,
 				  bfd_byte *buf)
 {
   struct elf_x86_link_hash_table *htab;
 
-  htab = _bfd_x86_elf_finish_dynamic_sections (output_bfd, info, buf);
+  htab = _bfd_x86_elf_finish_dynamic_sections (info, buf);
   if (htab == NULL)
     return false;
 
@@ -4176,13 +4176,13 @@ elf_i386_finish_dynamic_sections (bfd *output_bfd,
 		  htab->plt.plt_entry_size - htab->lazy_plt->plt0_entry_size);
 	  if (!bfd_link_pic (info))
 	    {
-	      bfd_put_32 (output_bfd,
+	      bfd_put_32 (info->output_bfd,
 			  (htab->elf.sgotplt->output_section->vma
 			   + htab->elf.sgotplt->output_offset
 			   + 4),
 			  htab->elf.splt->contents
 			  + htab->lazy_plt->plt0_got1_offset);
-	      bfd_put_32 (output_bfd,
+	      bfd_put_32 (info->output_bfd,
 			  (htab->elf.sgotplt->output_section->vma
 			   + htab->elf.sgotplt->output_offset
 			   + 8),
@@ -4205,7 +4205,7 @@ elf_i386_finish_dynamic_sections (bfd *output_bfd,
 				  + htab->lazy_plt->plt0_got1_offset);
 		  rel.r_info = ELF32_R_INFO (htab->elf.hgot->indx,
 					     R_386_32);
-		  bfd_elf32_swap_reloc_out (output_bfd, &rel,
+		  bfd_elf32_swap_reloc_out (info->output_bfd, &rel,
 					    srelplt2->contents);
 		  /* Generate a relocation for _GLOBAL_OFFSET_TABLE_
 		     + 8.  */
@@ -4214,7 +4214,7 @@ elf_i386_finish_dynamic_sections (bfd *output_bfd,
 				  + htab->lazy_plt->plt0_got2_offset);
 		  rel.r_info = ELF32_R_INFO (htab->elf.hgot->indx,
 					     R_386_32);
-		  bfd_elf32_swap_reloc_out (output_bfd, &rel,
+		  bfd_elf32_swap_reloc_out (info->output_bfd, &rel,
 					    srelplt2->contents +
 					    sizeof (Elf32_External_Rel));
 		  /* Correct the .rel.plt.unloaded relocations.  */
@@ -4226,16 +4226,16 @@ elf_i386_finish_dynamic_sections (bfd *output_bfd,
 
 		  for (; num_plts; num_plts--)
 		    {
-		      bfd_elf32_swap_reloc_in (output_bfd, p, &rel);
+		      bfd_elf32_swap_reloc_in (info->output_bfd, p, &rel);
 		      rel.r_info = ELF32_R_INFO (htab->elf.hgot->indx,
 						 R_386_32);
-		      bfd_elf32_swap_reloc_out (output_bfd, &rel, p);
+		      bfd_elf32_swap_reloc_out (info->output_bfd, &rel, p);
 		      p += sizeof (Elf32_External_Rel);
 
-		      bfd_elf32_swap_reloc_in (output_bfd, p, &rel);
+		      bfd_elf32_swap_reloc_in (info->output_bfd, p, &rel);
 		      rel.r_info = ELF32_R_INFO (htab->elf.hplt->indx,
 						 R_386_32);
-		      bfd_elf32_swap_reloc_out (output_bfd, &rel, p);
+		      bfd_elf32_swap_reloc_out (info->output_bfd, &rel, p);
 		      p += sizeof (Elf32_External_Rel);
 		    }
 		}
@@ -4259,8 +4259,7 @@ elf_i386_finish_dynamic_sections (bfd *output_bfd,
 
 static bool
 elf_i386_output_arch_local_syms
-  (bfd *output_bfd ATTRIBUTE_UNUSED,
-   struct bfd_link_info *info,
+  (struct bfd_link_info *info,
    void *flaginfo ATTRIBUTE_UNUSED,
    int (*func) (void *, const char *,
 		Elf_Internal_Sym *,
diff --git a/bfd/elf32-ip2k.c b/bfd/elf32-ip2k.c
index 6d62157225f..d050d679b72 100644
--- a/bfd/elf32-ip2k.c
+++ b/bfd/elf32-ip2k.c
@@ -1386,8 +1386,7 @@ ip2k_final_link_relocate (reloc_howto_type *  howto,
    accordingly.  */
 
 static int
-ip2k_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
-			   struct bfd_link_info *info,
+ip2k_elf_relocate_section (struct bfd_link_info *info,
 			   bfd *input_bfd,
 			   asection *input_section,
 			   bfd_byte *contents,
diff --git a/bfd/elf32-iq2000.c b/bfd/elf32-iq2000.c
index 56908098501..8daeca8c1bd 100644
--- a/bfd/elf32-iq2000.c
+++ b/bfd/elf32-iq2000.c
@@ -562,8 +562,7 @@ iq2000_elf_check_relocs (bfd *abfd,
    accordingly.	 */
 
 static int
-iq2000_elf_relocate_section (bfd *		     output_bfd ATTRIBUTE_UNUSED,
-			     struct bfd_link_info *  info,
+iq2000_elf_relocate_section (struct bfd_link_info *  info,
 			     bfd *		     input_bfd,
 			     asection *		     input_section,
 			     bfd_byte *		     contents,
@@ -616,8 +615,8 @@ iq2000_elf_relocate_section (bfd *		     output_bfd ATTRIBUTE_UNUSED,
 	    /* This relocation is relative to a section symbol that is
 	       going to be merged.  Change it so that it is relative
 	       to the merged section symbol.  */
-	    rel->r_addend = _bfd_elf_rel_local_sym (output_bfd, sym, &sec,
-						    rel->r_addend);
+	    rel->r_addend = _bfd_elf_rel_local_sym (info->output_bfd,
+						    sym, &sec, rel->r_addend);
 
 	  relocation = (sec->output_section->vma
 			+ sec->output_offset
diff --git a/bfd/elf32-lm32.c b/bfd/elf32-lm32.c
index ffb0e104be9..7014a522522 100644
--- a/bfd/elf32-lm32.c
+++ b/bfd/elf32-lm32.c
@@ -715,8 +715,7 @@ _lm32fdpic_osec_readonly_p (bfd *output_bfd, asection *osec)
 /* Relocate a section */
 
 static int
-lm32_elf_relocate_section (bfd *output_bfd,
-			   struct bfd_link_info *info,
+lm32_elf_relocate_section (struct bfd_link_info *info,
 			   bfd *input_bfd,
 			   asection *input_section,
 			   bfd_byte *contents,
@@ -774,7 +773,8 @@ lm32_elf_relocate_section (bfd *output_bfd,
 	  /* It's a local symbol.  */
 	  sym = local_syms + r_symndx;
 	  sec = local_sections[r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 	  name = bfd_elf_string_from_elf_section
 	    (input_bfd, symtab_hdr->sh_link, sym->st_name);
 	  name = name == NULL ? bfd_section_name (sec) : name;
@@ -820,7 +820,7 @@ lm32_elf_relocate_section (bfd *output_bfd,
 	  switch (howto->type)
 	    {
 	    case R_LM32_GPREL16:
-	      if (!lm32_elf_assign_gp (output_bfd, &gp))
+	      if (!lm32_elf_assign_gp (info->output_bfd, &gp))
 		r = bfd_reloc_dangerous;
 	      else
 		{
@@ -876,12 +876,13 @@ lm32_elf_relocate_section (bfd *output_bfd,
 		      else
 			{
 			  /* Write entry in GOT */
-			  bfd_put_32 (output_bfd, relocation,
+			  bfd_put_32 (info->output_bfd, relocation,
 				      sgot->contents + off);
 			  /* Create entry in .rofixup pointing to GOT entry.  */
-			   if (IS_FDPIC (output_bfd) && h->root.type != bfd_link_hash_undefweak)
+			   if (IS_FDPIC (info->output_bfd)
+			       && h->root.type != bfd_link_hash_undefweak)
 			     {
-			       _lm32fdpic_add_rofixup (output_bfd,
+			       _lm32fdpic_add_rofixup (info->output_bfd,
 						       lm32fdpic_fixup32_section
 							(info),
 						       sgot->output_section->vma
@@ -914,11 +915,12 @@ lm32_elf_relocate_section (bfd *output_bfd,
 		  else
 		    {
 		      /* Write entry in GOT.  */
-		      bfd_put_32 (output_bfd, relocation, sgot->contents + off);
+		      bfd_put_32 (info->output_bfd, relocation,
+				  sgot->contents + off);
 		      /* Create entry in .rofixup pointing to GOT entry.  */
-		      if (IS_FDPIC (output_bfd))
+		      if (IS_FDPIC (info->output_bfd))
 			{
-			  _lm32fdpic_add_rofixup (output_bfd,
+			  _lm32fdpic_add_rofixup (info->output_bfd,
 						  lm32fdpic_fixup32_section
 						   (info),
 						  sgot->output_section->vma
@@ -943,7 +945,8 @@ lm32_elf_relocate_section (bfd *output_bfd,
 			  outrel.r_addend = relocation;
 			  loc = srelgot->contents;
 			  loc += srelgot->reloc_count * sizeof (Elf32_External_Rela);
-			  bfd_elf32_swap_reloca_out (output_bfd, &outrel,loc);
+			  bfd_elf32_swap_reloca_out (info->output_bfd,
+						     &outrel,loc);
 			  ++srelgot->reloc_count;
 			}
 
@@ -988,7 +991,7 @@ lm32_elf_relocate_section (bfd *output_bfd,
 	      break;
 
 	    case R_LM32_32:
-	      if (IS_FDPIC (output_bfd))
+	      if (IS_FDPIC (info->output_bfd))
 		{
 		  if ((!h) || (h && h->root.type != bfd_link_hash_undefweak))
 		    {
@@ -998,7 +1001,7 @@ lm32_elf_relocate_section (bfd *output_bfd,
 
 			{
 			  /* Check address to be modified is writable.  */
-			  if (_lm32fdpic_osec_readonly_p (output_bfd,
+			  if (_lm32fdpic_osec_readonly_p (info->output_bfd,
 							  input_section
 							   ->output_section))
 			    {
@@ -1009,7 +1012,7 @@ lm32_elf_relocate_section (bfd *output_bfd,
 			       return false;
 			    }
 			  /* Create entry in .rofixup section.  */
-			  _lm32fdpic_add_rofixup (output_bfd,
+			  _lm32fdpic_add_rofixup (info->output_bfd,
 						  lm32fdpic_fixup32_section (info),
 						  input_section->output_section->vma
 						   + input_section->output_offset
@@ -1256,8 +1259,7 @@ lm32_elf_check_relocs (bfd *abfd,
 /* Finish up the dynamic sections.  */
 
 static bool
-lm32_elf_finish_dynamic_sections (bfd *output_bfd,
-				  struct bfd_link_info *info,
+lm32_elf_finish_dynamic_sections (struct bfd_link_info *info,
 				  bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   struct elf_lm32_link_hash_table *htab;
@@ -1303,13 +1305,13 @@ lm32_elf_finish_dynamic_sections (bfd *output_bfd,
 	      s = htab->root.srelplt;
 	    get_vma:
 	      dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    case DT_PLTRELSZ:
 	      s = htab->root.srelplt;
 	      dyn.d_un.d_val = s->size;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 	    }
 	}
@@ -1320,26 +1322,34 @@ lm32_elf_finish_dynamic_sections (bfd *output_bfd,
 	{
 	  if (bfd_link_pic (info))
 	    {
-	      bfd_put_32 (output_bfd, PLT0_PIC_ENTRY_WORD0, splt->contents);
-	      bfd_put_32 (output_bfd, PLT0_PIC_ENTRY_WORD1, splt->contents + 4);
-	      bfd_put_32 (output_bfd, PLT0_PIC_ENTRY_WORD2, splt->contents + 8);
-	      bfd_put_32 (output_bfd, PLT0_PIC_ENTRY_WORD3, splt->contents + 12);
-	      bfd_put_32 (output_bfd, PLT0_PIC_ENTRY_WORD4, splt->contents + 16);
+	      bfd_put_32 (info->output_bfd, PLT0_PIC_ENTRY_WORD0,
+			  splt->contents);
+	      bfd_put_32 (info->output_bfd, PLT0_PIC_ENTRY_WORD1,
+			  splt->contents + 4);
+	      bfd_put_32 (info->output_bfd, PLT0_PIC_ENTRY_WORD2,
+			  splt->contents + 8);
+	      bfd_put_32 (info->output_bfd, PLT0_PIC_ENTRY_WORD3,
+			  splt->contents + 12);
+	      bfd_put_32 (info->output_bfd, PLT0_PIC_ENTRY_WORD4,
+			  splt->contents + 16);
 	    }
 	  else
 	    {
 	      unsigned long addr;
 	      /* addr = .got + 4 */
 	      addr = sgot->output_section->vma + sgot->output_offset + 4;
-	      bfd_put_32 (output_bfd,
+	      bfd_put_32 (info->output_bfd,
 			  PLT0_ENTRY_WORD0 | ((addr >> 16) & 0xffff),
 			  splt->contents);
-	      bfd_put_32 (output_bfd,
+	      bfd_put_32 (info->output_bfd,
 			  PLT0_ENTRY_WORD1 | (addr & 0xffff),
 			  splt->contents + 4);
-	      bfd_put_32 (output_bfd, PLT0_ENTRY_WORD2, splt->contents + 8);
-	      bfd_put_32 (output_bfd, PLT0_ENTRY_WORD3, splt->contents + 12);
-	      bfd_put_32 (output_bfd, PLT0_ENTRY_WORD4, splt->contents + 16);
+	      bfd_put_32 (info->output_bfd, PLT0_ENTRY_WORD2,
+			  splt->contents + 8);
+	      bfd_put_32 (info->output_bfd, PLT0_ENTRY_WORD3,
+			  splt->contents + 12);
+	      bfd_put_32 (info->output_bfd, PLT0_ENTRY_WORD4,
+			  splt->contents + 16);
 	    }
 
 	  elf_section_data (splt->output_section)->this_hdr.sh_entsize =
@@ -1351,13 +1361,13 @@ lm32_elf_finish_dynamic_sections (bfd *output_bfd,
   if (sgot && sgot->size > 0)
     {
       if (sdyn == NULL)
-	bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
+	bfd_put_32 (info->output_bfd, 0, sgot->contents);
       else
-	bfd_put_32 (output_bfd,
+	bfd_put_32 (info->output_bfd,
 		    sdyn->output_section->vma + sdyn->output_offset,
 		    sgot->contents);
-      bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
-      bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
+      bfd_put_32 (info->output_bfd, 0, sgot->contents + 4);
+      bfd_put_32 (info->output_bfd, 0, sgot->contents + 8);
 
       /* FIXME:  This can be null if create_dynamic_sections wasn't called. */
       if (elf_section_data (sgot->output_section) != NULL)
@@ -1373,7 +1383,7 @@ lm32_elf_finish_dynamic_sections (bfd *output_bfd,
       struct bfd_link_hash_entry *hend;
 
       /* Last entry is pointer to GOT.  */
-      _lm32fdpic_add_rofixup (output_bfd, lm32fdpic_fixup32_section (info), got_value);
+      _lm32fdpic_add_rofixup (info->output_bfd, lm32fdpic_fixup32_section (info), got_value);
 
       /* Check we wrote enough entries.  */
       if (lm32fdpic_fixup32_section (info)->size
@@ -1419,8 +1429,7 @@ lm32_elf_finish_dynamic_sections (bfd *output_bfd,
    dynamic sections here.  */
 
 static bool
-lm32_elf_finish_dynamic_symbol (bfd *output_bfd,
-				struct bfd_link_info *info,
+lm32_elf_finish_dynamic_symbol (struct bfd_link_info *info,
 				struct elf_link_hash_entry *h,
 				Elf_Internal_Sym *sym)
 {
@@ -1470,7 +1479,7 @@ lm32_elf_finish_dynamic_symbol (bfd *output_bfd,
 	}
 
       /* Fill in the entry in the global offset table.  */
-      bfd_put_32 (output_bfd,
+      bfd_put_32 (info->output_bfd,
 		  (splt->output_section->vma
 		   + splt->output_offset
 		   + h->plt.offset
@@ -1485,7 +1494,7 @@ lm32_elf_finish_dynamic_symbol (bfd *output_bfd,
       rela.r_addend = 0;
       loc = srela->contents;
       loc += plt_index * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
 
       if (!h->def_regular)
 	{
@@ -1531,14 +1540,14 @@ lm32_elf_finish_dynamic_symbol (bfd *output_bfd,
       else
 	{
 	  BFD_ASSERT ((h->got.offset & 1) == 0);
-	  bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + h->got.offset);
+	  bfd_put_32 (info->output_bfd, 0, sgot->contents + h->got.offset);
 	  rela.r_info = ELF32_R_INFO (h->dynindx, R_LM32_GLOB_DAT);
 	  rela.r_addend = 0;
 	}
 
       loc = srela->contents;
       loc += srela->reloc_count * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
       ++srela->reloc_count;
     }
 
@@ -1562,7 +1571,7 @@ lm32_elf_finish_dynamic_symbol (bfd *output_bfd,
       rela.r_addend = 0;
       loc = s->contents;
       loc += s->reloc_count * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
       ++s->reloc_count;
     }
 
@@ -1905,8 +1914,7 @@ allocate_dynrelocs (struct elf_link_hash_entry *h, void * inf)
 /* Set the sizes of the dynamic sections.  */
 
 static bool
-lm32_elf_late_size_sections (bfd *output_bfd,
-			     struct bfd_link_info *info)
+lm32_elf_late_size_sections (struct bfd_link_info *info)
 {
   struct elf_lm32_link_hash_table *htab;
   bfd *dynobj;
@@ -2060,11 +2068,11 @@ lm32_elf_late_size_sections (bfd *output_bfd,
       s->alloced = 1;
     }
 
-  if (!_bfd_elf_add_dynamic_tags (output_bfd, info, relocs))
+  if (!_bfd_elf_add_dynamic_tags (info, relocs))
     return false;
 
   /* Allocate .rofixup section.  */
-  if (IS_FDPIC (output_bfd))
+  if (IS_FDPIC (info->output_bfd))
     {
       struct weak_symbol_list *list_start = NULL, *list_end = NULL;
       int rgot_weak_count = 0;
@@ -2308,15 +2316,14 @@ lm32_elf_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info)
 }
 
 static bool
-lm32_elf_early_size_sections (bfd *output_bfd, struct bfd_link_info *info)
+lm32_elf_early_size_sections (struct bfd_link_info *info)
 {
   if (!bfd_link_relocatable (info))
     {
-      if (!bfd_elf_stack_segment_size (output_bfd, info,
-				       "__stacksize", DEFAULT_STACK_SIZE))
+      if (!bfd_elf_stack_segment_size (info, "__stacksize", DEFAULT_STACK_SIZE))
 	return false;
 
-      asection *sec = bfd_get_section_by_name (output_bfd, ".stack");
+      asection *sec = bfd_get_section_by_name (info->output_bfd, ".stack");
       if (sec)
 	sec->size = info->stacksize >= 0 ? info->stacksize : 0;
     }
diff --git a/bfd/elf32-m32c.c b/bfd/elf32-m32c.c
index e1308eef58b..c8c95e89b94 100644
--- a/bfd/elf32-m32c.c
+++ b/bfd/elf32-m32c.c
@@ -31,7 +31,7 @@ static reloc_howto_type * m32c_reloc_type_lookup
 static bool m32c_info_to_howto_rela
   (bfd *, arelent *, Elf_Internal_Rela *);
 static int m32c_elf_relocate_section
-  (bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *, Elf_Internal_Rela *, Elf_Internal_Sym *, asection **);
+  (struct bfd_link_info *, bfd *, asection *, bfd_byte *, Elf_Internal_Rela *, Elf_Internal_Sym *, asection **);
 static bool m32c_elf_check_relocs
   (bfd *, struct bfd_link_info *, asection *, const Elf_Internal_Rela *);
 static bool m32c_elf_relax_delete_bytes (bfd *, asection *, bfd_vma, int);
@@ -390,8 +390,7 @@ static bfd_reloc_status_type m32c_apply_reloc_24 (bfd *abfd ATTRIBUTE_UNUSED,
 
 static int
 m32c_elf_relocate_section
-    (bfd *		     output_bfd ATTRIBUTE_UNUSED,
-     struct bfd_link_info *  info,
+    (struct bfd_link_info *  info,
      bfd *		     input_bfd,
      asection *		     input_section,
      bfd_byte *		     contents,
@@ -750,8 +749,7 @@ m32c_elf_check_relocs
 /* This must exist if dynobj is ever set.  */
 
 static bool
-m32c_elf_finish_dynamic_sections (bfd *abfd ATTRIBUTE_UNUSED,
-				  struct bfd_link_info *info,
+m32c_elf_finish_dynamic_sections (struct bfd_link_info *info,
 				  bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   bfd *dynobj = elf_hash_table (info)->dynobj;
@@ -775,8 +773,7 @@ m32c_elf_finish_dynamic_sections (bfd *abfd ATTRIBUTE_UNUSED,
 }
 
 static bool
-m32c_elf_early_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-			      struct bfd_link_info *info)
+m32c_elf_early_size_sections (struct bfd_link_info *info)
 {
   bfd *dynobj;
   asection *splt;
diff --git a/bfd/elf32-m32r.c b/bfd/elf32-m32r.c
index abba55a7d16..80a1b1eaa7a 100644
--- a/bfd/elf32-m32r.c
+++ b/bfd/elf32-m32r.c
@@ -2015,8 +2015,7 @@ allocate_dynrelocs (struct elf_link_hash_entry *h, void * inf)
 /* Set the sizes of the dynamic sections.  */
 
 static bool
-m32r_elf_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-			     struct bfd_link_info *info)
+m32r_elf_late_size_sections (struct bfd_link_info *info)
 {
   struct elf_link_hash_table *htab;
   bfd *dynobj;
@@ -2174,7 +2173,7 @@ m32r_elf_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
       s->alloced = 1;
     }
 
-  return _bfd_elf_add_dynamic_tags (output_bfd, info, relocs);
+  return _bfd_elf_add_dynamic_tags (info, relocs);
 }
 
 /* Relocate an M32R/D ELF section.
@@ -2211,8 +2210,7 @@ m32r_elf_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
    accordingly.  */
 
 static int
-m32r_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
-			   struct bfd_link_info *info,
+m32r_elf_relocate_section (struct bfd_link_info *info,
 			   bfd *input_bfd,
 			   asection *input_section,
 			   bfd_byte *contents,
@@ -2298,7 +2296,8 @@ m32r_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 
 	  if (!use_rel)
 	    {
-	      relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	      relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						    sym, &sec, rel);
 	      addend = rel->r_addend;
 	    }
 	  else
@@ -2380,7 +2379,7 @@ m32r_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 			      + sec->output_section->vma
 			      + sec->output_offset);
 	      else if (!bfd_link_relocatable (info)
-		       && (_bfd_elf_section_offset (output_bfd, info,
+		       && (_bfd_elf_section_offset (info->output_bfd, info,
 						    input_section,
 						    rel->r_offset)
 			   != (bfd_vma) -1))
@@ -2577,7 +2576,7 @@ m32r_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 			off &= ~1;
 		      else
 			{
-			  bfd_put_32 (output_bfd, relocation,
+			  bfd_put_32 (info->output_bfd, relocation,
 				      sgot->contents + off);
 			  h->got.offset |= 1;
 			}
@@ -2602,7 +2601,8 @@ m32r_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 		    off &= ~1;
 		  else
 		    {
-		      bfd_put_32 (output_bfd, relocation, sgot->contents + off);
+		      bfd_put_32 (info->output_bfd, relocation,
+				  sgot->contents + off);
 
 		      if (bfd_link_pic (info))
 			{
@@ -2621,7 +2621,8 @@ m32r_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 			  outrel.r_addend = relocation;
 			  loc = srelgot->contents;
 			  loc += srelgot->reloc_count * sizeof (Elf32_External_Rela);
-			  bfd_elf32_swap_reloca_out (output_bfd, &outrel,loc);
+			  bfd_elf32_swap_reloca_out (info->output_bfd,
+						     &outrel,loc);
 			  ++srelgot->reloc_count;
 			}
 
@@ -2700,7 +2701,7 @@ m32r_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 		  skip = false;
 		  relocate = false;
 
-		  outrel.r_offset = _bfd_elf_section_offset (output_bfd,
+		  outrel.r_offset = _bfd_elf_section_offset (info->output_bfd,
 							     info,
 							     input_section,
 							     rel->r_offset);
@@ -2744,7 +2745,7 @@ m32r_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 
 		  loc = sreloc->contents;
 		  loc += sreloc->reloc_count * sizeof (Elf32_External_Rela);
-		  bfd_elf32_swap_reloca_out (output_bfd, &outrel,loc);
+		  bfd_elf32_swap_reloca_out (info->output_bfd, &outrel,loc);
 		  ++sreloc->reloc_count;
 
 		  /* If this reloc is against an external symbol, we do
@@ -2916,8 +2917,7 @@ m32r_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
    dynamic sections here.  */
 
 static bool
-m32r_elf_finish_dynamic_symbol (bfd *output_bfd,
-				struct bfd_link_info *info,
+m32r_elf_finish_dynamic_symbol (struct bfd_link_info *info,
 				struct elf_link_hash_entry *h,
 				Elf_Internal_Sym *sym)
 {
@@ -2964,50 +2964,50 @@ m32r_elf_finish_dynamic_symbol (bfd *output_bfd,
       /* Fill in the entry in the procedure linkage table.  */
       if (! bfd_link_pic (info))
 	{
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 	      (PLT_ENTRY_WORD0b
 	       + (((sgot->output_section->vma
 		    + sgot->output_offset
 		    + got_offset) >> 16) & 0xffff)),
 	      splt->contents + h->plt.offset);
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 	      (PLT_ENTRY_WORD1b
 	       + ((sgot->output_section->vma
 		   + sgot->output_offset
 		   + got_offset) & 0xffff)),
 	      splt->contents + h->plt.offset + 4);
-	  bfd_put_32 (output_bfd, PLT_ENTRY_WORD2,
+	  bfd_put_32 (info->output_bfd, PLT_ENTRY_WORD2,
 	      splt->contents + h->plt.offset + 8);
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 	      (PLT_ENTRY_WORD3
 	       + plt_index * sizeof (Elf32_External_Rela)),
 	      splt->contents + h->plt.offset + 12);
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 	      (PLT_ENTRY_WORD4
 	       + (((unsigned int) ((- (h->plt.offset + 16)) >> 2)) & 0xffffff)),
 	      splt->contents + h->plt.offset + 16);
 	}
       else
 	{
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 	      PLT_ENTRY_WORD0 + got_offset,
 	      splt->contents + h->plt.offset);
-	  bfd_put_32 (output_bfd, PLT_ENTRY_WORD1,
+	  bfd_put_32 (info->output_bfd, PLT_ENTRY_WORD1,
 	      splt->contents + h->plt.offset + 4);
-	  bfd_put_32 (output_bfd, PLT_ENTRY_WORD2,
+	  bfd_put_32 (info->output_bfd, PLT_ENTRY_WORD2,
 	      splt->contents + h->plt.offset + 8);
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 	      (PLT_ENTRY_WORD3
 	       + plt_index * sizeof (Elf32_External_Rela)),
 	      splt->contents + h->plt.offset + 12);
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 	      (PLT_ENTRY_WORD4
 	       + (((unsigned int) ((- (h->plt.offset + 16)) >> 2)) & 0xffffff)),
 	      splt->contents + h->plt.offset + 16);
 	}
 
       /* Fill in the entry in the global offset table.  */
-      bfd_put_32 (output_bfd,
+      bfd_put_32 (info->output_bfd,
 		  (splt->output_section->vma
 		   + splt->output_offset
 		   + h->plt.offset
@@ -3022,7 +3022,7 @@ m32r_elf_finish_dynamic_symbol (bfd *output_bfd,
       rela.r_addend = 0;
       loc = srela->contents;
       loc += plt_index * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
 
       if (!h->def_regular)
 	{
@@ -3068,14 +3068,14 @@ m32r_elf_finish_dynamic_symbol (bfd *output_bfd,
       else
 	{
 	  BFD_ASSERT ((h->got.offset & 1) == 0);
-	  bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + h->got.offset);
+	  bfd_put_32 (info->output_bfd, 0, sgot->contents + h->got.offset);
 	  rela.r_info = ELF32_R_INFO (h->dynindx, R_M32R_GLOB_DAT);
 	  rela.r_addend = 0;
 	}
 
       loc = srela->contents;
       loc += srela->reloc_count * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
       ++srela->reloc_count;
     }
 
@@ -3100,7 +3100,7 @@ m32r_elf_finish_dynamic_symbol (bfd *output_bfd,
       rela.r_addend = 0;
       loc = s->contents;
       loc += s->reloc_count * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
       ++s->reloc_count;
     }
 
@@ -3115,8 +3115,7 @@ m32r_elf_finish_dynamic_symbol (bfd *output_bfd,
 /* Finish up the dynamic sections.  */
 
 static bool
-m32r_elf_finish_dynamic_sections (bfd *output_bfd,
-				  struct bfd_link_info *info,
+m32r_elf_finish_dynamic_sections (struct bfd_link_info *info,
 				  bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   struct elf_link_hash_table *htab;
@@ -3166,13 +3165,13 @@ m32r_elf_finish_dynamic_sections (bfd *output_bfd,
 	      s = htab->srelplt;
 	    get_vma:
 	      dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    case DT_PLTRELSZ:
 	      s = htab->srelplt;
 	      dyn.d_un.d_val = s->size;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 	    }
 	}
@@ -3183,26 +3182,34 @@ m32r_elf_finish_dynamic_sections (bfd *output_bfd,
 	{
 	  if (bfd_link_pic (info))
 	    {
-	      bfd_put_32 (output_bfd, PLT0_PIC_ENTRY_WORD0, splt->contents);
-	      bfd_put_32 (output_bfd, PLT0_PIC_ENTRY_WORD1, splt->contents + 4);
-	      bfd_put_32 (output_bfd, PLT0_PIC_ENTRY_WORD2, splt->contents + 8);
-	      bfd_put_32 (output_bfd, PLT0_PIC_ENTRY_WORD3, splt->contents + 12);
-	      bfd_put_32 (output_bfd, PLT0_PIC_ENTRY_WORD4, splt->contents + 16);
+	      bfd_put_32 (info->output_bfd, PLT0_PIC_ENTRY_WORD0,
+			  splt->contents);
+	      bfd_put_32 (info->output_bfd, PLT0_PIC_ENTRY_WORD1,
+			  splt->contents + 4);
+	      bfd_put_32 (info->output_bfd, PLT0_PIC_ENTRY_WORD2,
+			  splt->contents + 8);
+	      bfd_put_32 (info->output_bfd, PLT0_PIC_ENTRY_WORD3,
+			  splt->contents + 12);
+	      bfd_put_32 (info->output_bfd, PLT0_PIC_ENTRY_WORD4,
+			  splt->contents + 16);
 	    }
 	  else
 	    {
 	      unsigned long addr;
 	      /* addr = .got + 4 */
 	      addr = sgot->output_section->vma + sgot->output_offset + 4;
-	      bfd_put_32 (output_bfd,
+	      bfd_put_32 (info->output_bfd,
 			  PLT0_ENTRY_WORD0 | ((addr >> 16) & 0xffff),
 			  splt->contents);
-	      bfd_put_32 (output_bfd,
+	      bfd_put_32 (info->output_bfd,
 			  PLT0_ENTRY_WORD1 | (addr & 0xffff),
 			  splt->contents + 4);
-	      bfd_put_32 (output_bfd, PLT0_ENTRY_WORD2, splt->contents + 8);
-	      bfd_put_32 (output_bfd, PLT0_ENTRY_WORD3, splt->contents + 12);
-	      bfd_put_32 (output_bfd, PLT0_ENTRY_WORD4, splt->contents + 16);
+	      bfd_put_32 (info->output_bfd, PLT0_ENTRY_WORD2,
+			  splt->contents + 8);
+	      bfd_put_32 (info->output_bfd, PLT0_ENTRY_WORD3,
+			  splt->contents + 12);
+	      bfd_put_32 (info->output_bfd, PLT0_ENTRY_WORD4,
+			  splt->contents + 16);
 	    }
 
 	  elf_section_data (splt->output_section)->this_hdr.sh_entsize =
@@ -3214,13 +3221,13 @@ m32r_elf_finish_dynamic_sections (bfd *output_bfd,
   if (sgot && sgot->size > 0)
     {
       if (sdyn == NULL)
-	bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
+	bfd_put_32 (info->output_bfd, 0, sgot->contents);
       else
-	bfd_put_32 (output_bfd,
+	bfd_put_32 (info->output_bfd,
 		    sdyn->output_section->vma + sdyn->output_offset,
 		    sgot->contents);
-      bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
-      bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
+      bfd_put_32 (info->output_bfd, 0, sgot->contents + 4);
+      bfd_put_32 (info->output_bfd, 0, sgot->contents + 8);
 
       elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
     }
diff --git a/bfd/elf32-m68hc1x.c b/bfd/elf32-m68hc1x.c
index d1adb328c19..2b7c4500851 100644
--- a/bfd/elf32-m68hc1x.c
+++ b/bfd/elf32-m68hc1x.c
@@ -923,8 +923,7 @@ reloc_warning (struct bfd_link_info *info, const char *name, bfd *input_bfd,
 
 /* Relocate a 68hc11/68hc12 ELF section.  */
 int
-elf32_m68hc11_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
-				struct bfd_link_info *info,
+elf32_m68hc11_relocate_section (struct bfd_link_info *info,
 				bfd *input_bfd, asection *input_section,
 				bfd_byte *contents, Elf_Internal_Rela *relocs,
 				Elf_Internal_Sym *local_syms,
diff --git a/bfd/elf32-m68hc1x.h b/bfd/elf32-m68hc1x.h
index b7b0dfad7db..c4a1459f56b 100644
--- a/bfd/elf32-m68hc1x.h
+++ b/bfd/elf32-m68hc1x.h
@@ -167,7 +167,7 @@ bool elf32_m68hc11_check_relocs
   (bfd * abfd, struct bfd_link_info * info,
    asection * sec, const Elf_Internal_Rela * relocs) ATTRIBUTE_HIDDEN;
 int elf32_m68hc11_relocate_section
-  (bfd *output_bfd, struct bfd_link_info *info,
+  (struct bfd_link_info *info,
    bfd *input_bfd, asection *input_section,
    bfd_byte *contents, Elf_Internal_Rela *relocs,
    Elf_Internal_Sym *local_syms, asection **local_sections) ATTRIBUTE_HIDDEN;
diff --git a/bfd/elf32-m68k.c b/bfd/elf32-m68k.c
index e90ba086454..8ed7640ddf8 100644
--- a/bfd/elf32-m68k.c
+++ b/bfd/elf32-m68k.c
@@ -2932,14 +2932,14 @@ elf_m68k_get_plt_info (bfd *output_bfd)
    It's a convenient place to determine the PLT style.  */
 
 static bool
-elf_m68k_early_size_sections (bfd *output_bfd, struct bfd_link_info *info)
+elf_m68k_early_size_sections (struct bfd_link_info *info)
 {
   /* Bind input BFDs to GOTs and calculate sizes of .got and .rela.got
      sections.  */
   if (!elf_m68k_partition_multi_got (info))
     return false;
 
-  elf_m68k_hash_table (info)->plt_info = elf_m68k_get_plt_info (output_bfd);
+  elf_m68k_hash_table (info)->plt_info = elf_m68k_get_plt_info (info->output_bfd);
   return true;
 }
 
@@ -3105,8 +3105,7 @@ elf_m68k_adjust_dynamic_symbol (struct bfd_link_info *info,
 /* Set the sizes of the dynamic sections.  */
 
 static bool
-elf_m68k_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-			     struct bfd_link_info *info)
+elf_m68k_late_size_sections (struct bfd_link_info *info)
 {
   bfd *dynobj;
   asection *s;
@@ -3219,7 +3218,7 @@ elf_m68k_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
       s->alloced = 1;
     }
 
-  return _bfd_elf_add_dynamic_tags (output_bfd, info, relocs);
+  return _bfd_elf_add_dynamic_tags (info, relocs);
 }
 
 /* This function is called via elf_link_hash_traverse if we are
@@ -3422,8 +3421,7 @@ elf_m68k_init_got_entry_local_shared (struct bfd_link_info *info,
 /* Relocate an M68K ELF section.  */
 
 static int
-elf_m68k_relocate_section (bfd *output_bfd,
-			   struct bfd_link_info *info,
+elf_m68k_relocate_section (struct bfd_link_info *info,
 			   bfd *input_bfd,
 			   asection *input_section,
 			   bfd_byte *contents,
@@ -3485,7 +3483,8 @@ elf_m68k_relocate_section (bfd *output_bfd,
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections[r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 	}
       else
 	{
@@ -3647,7 +3646,7 @@ elf_m68k_relocate_section (bfd *output_bfd,
 			   is done in the finish_dynamic_symbol routine.  */
 
 			elf_m68k_init_got_entry_static (info,
-							output_bfd,
+							info->output_bfd,
 							r_type,
 							sgot,
 							off,
@@ -3665,7 +3664,7 @@ elf_m68k_relocate_section (bfd *output_bfd,
 		    BFD_ASSERT (srela != NULL);
 
 		    elf_m68k_init_got_entry_local_shared (info,
-							  output_bfd,
+							  info->output_bfd,
 							  r_type,
 							  sgot,
 							  off,
@@ -3677,7 +3676,7 @@ elf_m68k_relocate_section (bfd *output_bfd,
 		else /* h == NULL && !bfd_link_pic (info) */
 		  {
 		    elf_m68k_init_got_entry_static (info,
-						    output_bfd,
+						    info->output_bfd,
 						    r_type,
 						    sgot,
 						    off,
@@ -3821,7 +3820,7 @@ elf_m68k_relocate_section (bfd *output_bfd,
 	      relocate = false;
 
 	      outrel.r_offset =
-		_bfd_elf_section_offset (output_bfd, info, input_section,
+		_bfd_elf_section_offset (info->output_bfd, info, input_section,
 					 rel->r_offset);
 	      if (outrel.r_offset == (bfd_vma) -1)
 		skip = true;
@@ -3896,7 +3895,7 @@ elf_m68k_relocate_section (bfd *output_bfd,
 
 	      loc = sreloc->contents;
 	      loc += sreloc->reloc_count++ * sizeof (Elf32_External_Rela);
-	      bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+	      bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 
 	      /* This reloc will be computed at runtime, so there's no
 		 need to do anything now, except for R_68K_32
@@ -3923,7 +3922,7 @@ elf_m68k_relocate_section (bfd *output_bfd,
       if (unresolved_reloc
 	  && !((input_section->flags & SEC_DEBUGGING) != 0
 	       && h->def_dynamic)
-	  && _bfd_elf_section_offset (output_bfd, info, input_section,
+	  && _bfd_elf_section_offset (info->output_bfd, info, input_section,
 				      rel->r_offset) != (bfd_vma) -1)
 	{
 	  _bfd_error_handler
@@ -4035,8 +4034,7 @@ elf_m68k_install_pc32 (asection *sec, bfd_vma offset, bfd_vma value)
    dynamic sections here.  */
 
 static bool
-elf_m68k_finish_dynamic_symbol (bfd *output_bfd,
-				struct bfd_link_info *info,
+elf_m68k_finish_dynamic_symbol (struct bfd_link_info *info,
 				struct elf_link_hash_entry *h,
 				Elf_Internal_Sym *sym)
 {
@@ -4086,7 +4084,7 @@ elf_m68k_finish_dynamic_symbol (bfd *output_bfd,
 			      + sgot->output_offset
 			      + got_offset));
 
-      bfd_put_32 (output_bfd, plt_index * sizeof (Elf32_External_Rela),
+      bfd_put_32 (info->output_bfd, plt_index * sizeof (Elf32_External_Rela),
 		  splt->contents
 		  + h->plt.offset
 		  + plt_info->symbol_resolve_entry + 2);
@@ -4095,7 +4093,7 @@ elf_m68k_finish_dynamic_symbol (bfd *output_bfd,
 			     splt->output_section->vma);
 
       /* Fill in the entry in the global offset table.  */
-      bfd_put_32 (output_bfd,
+      bfd_put_32 (info->output_bfd,
 		  (splt->output_section->vma
 		   + splt->output_offset
 		   + h->plt.offset
@@ -4109,7 +4107,7 @@ elf_m68k_finish_dynamic_symbol (bfd *output_bfd,
       rela.r_info = ELF32_R_INFO (h->dynindx, R_68K_JMP_SLOT);
       rela.r_addend = 0;
       loc = srela->contents + plt_index * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
 
       if (!h->def_regular)
 	{
@@ -4152,7 +4150,7 @@ elf_m68k_finish_dynamic_symbol (bfd *output_bfd,
 	    {
 	      bfd_vma relocation;
 
-	      relocation = bfd_get_signed_32 (output_bfd,
+	      relocation = bfd_get_signed_32 (info->output_bfd,
 					      (sgot->contents
 					       + got_entry_offset));
 
@@ -4166,7 +4164,7 @@ elf_m68k_finish_dynamic_symbol (bfd *output_bfd,
 		case R_68K_TLS_GD32:
 		  /* The value for this relocation is actually put in
 		     the second GOT slot.  */
-		  relocation = bfd_get_signed_32 (output_bfd,
+		  relocation = bfd_get_signed_32 (info->output_bfd,
 						  (sgot->contents
 						   + got_entry_offset + 4));
 		  relocation += dtpoff_base (info);
@@ -4181,7 +4179,7 @@ elf_m68k_finish_dynamic_symbol (bfd *output_bfd,
 		}
 
 	      elf_m68k_init_got_entry_local_shared (info,
-						    output_bfd,
+						    info->output_bfd,
 						    r_type,
 						    sgot,
 						    got_entry_offset,
@@ -4199,7 +4197,7 @@ elf_m68k_finish_dynamic_symbol (bfd *output_bfd,
 
 		n_slots = elf_m68k_reloc_got_n_slots (got_entry->key_.type);
 		while (n_slots--)
-		  bfd_put_32 (output_bfd, (bfd_vma) 0,
+		  bfd_put_32 (info->output_bfd, 0,
 			      (sgot->contents + got_entry_offset
 			       + 4 * n_slots));
 	      }
@@ -4213,21 +4211,21 @@ elf_m68k_finish_dynamic_symbol (bfd *output_bfd,
 		{
 		case R_68K_GOT32O:
 		  rela.r_info = ELF32_R_INFO (h->dynindx, R_68K_GLOB_DAT);
-		  elf_m68k_install_rela (output_bfd, srela, &rela);
+		  elf_m68k_install_rela (info->output_bfd, srela, &rela);
 		  break;
 
 		case R_68K_TLS_GD32:
 		  rela.r_info = ELF32_R_INFO (h->dynindx, R_68K_TLS_DTPMOD32);
-		  elf_m68k_install_rela (output_bfd, srela, &rela);
+		  elf_m68k_install_rela (info->output_bfd, srela, &rela);
 
 		  rela.r_offset += 4;
 		  rela.r_info = ELF32_R_INFO (h->dynindx, R_68K_TLS_DTPREL32);
-		  elf_m68k_install_rela (output_bfd, srela, &rela);
+		  elf_m68k_install_rela (info->output_bfd, srela, &rela);
 		  break;
 
 		case R_68K_TLS_IE32:
 		  rela.r_info = ELF32_R_INFO (h->dynindx, R_68K_TLS_TPREL32);
-		  elf_m68k_install_rela (output_bfd, srela, &rela);
+		  elf_m68k_install_rela (info->output_bfd, srela, &rela);
 		  break;
 
 		default:
@@ -4261,7 +4259,7 @@ elf_m68k_finish_dynamic_symbol (bfd *output_bfd,
       rela.r_info = ELF32_R_INFO (h->dynindx, R_68K_COPY);
       rela.r_addend = 0;
       loc = s->contents + s->reloc_count++ * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
     }
 
   return true;
@@ -4270,7 +4268,7 @@ elf_m68k_finish_dynamic_symbol (bfd *output_bfd,
 /* Finish up the dynamic sections.  */
 
 static bool
-elf_m68k_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
+elf_m68k_finish_dynamic_sections (struct bfd_link_info *info,
 				  bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   bfd *dynobj;
@@ -4312,13 +4310,13 @@ elf_m68k_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
 	      s = elf_hash_table (info)->srelplt;
 	    get_vma:
 	      dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    case DT_PLTRELSZ:
 	      s = elf_hash_table (info)->srelplt;
 	      dyn.d_un.d_val = s->size;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 	    }
 	}
@@ -4350,13 +4348,13 @@ elf_m68k_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
   if (sgot->size > 0)
     {
       if (sdyn == NULL)
-	bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
+	bfd_put_32 (info->output_bfd, 0, sgot->contents);
       else
-	bfd_put_32 (output_bfd,
+	bfd_put_32 (info->output_bfd,
 		    sdyn->output_section->vma + sdyn->output_offset,
 		    sgot->contents);
-      bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
-      bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
+      bfd_put_32 (info->output_bfd, 0, sgot->contents + 4);
+      bfd_put_32 (info->output_bfd, 0, sgot->contents + 8);
     }
 
   elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
diff --git a/bfd/elf32-mcore.c b/bfd/elf32-mcore.c
index ddf29edaf6b..761ce7f17ce 100644
--- a/bfd/elf32-mcore.c
+++ b/bfd/elf32-mcore.c
@@ -390,8 +390,7 @@ mcore_elf_info_to_howto (bfd * abfd,
    accordingly.  */
 
 static int
-mcore_elf_relocate_section (bfd * output_bfd,
-			    struct bfd_link_info * info,
+mcore_elf_relocate_section (struct bfd_link_info * info,
 			    bfd * input_bfd,
 			    asection * input_section,
 			    bfd_byte * contents,
@@ -464,7 +463,8 @@ mcore_elf_relocate_section (bfd * output_bfd,
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections [r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 	  addend = rel->r_addend;
 	}
       else
diff --git a/bfd/elf32-mep.c b/bfd/elf32-mep.c
index 18b1be58888..9c47a416fec 100644
--- a/bfd/elf32-mep.c
+++ b/bfd/elf32-mep.c
@@ -426,8 +426,7 @@ mep_info_to_howto_rela (bfd *		    abfd,
 
 static int
 mep_elf_relocate_section
-    (bfd *		     output_bfd ATTRIBUTE_UNUSED,
-     struct bfd_link_info *  info,
+    (struct bfd_link_info *  info,
      bfd *		     input_bfd,
      asection *		     input_section,
      bfd_byte *		     contents,
@@ -469,7 +468,8 @@ mep_elf_relocate_section
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections [r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 
 	  name = bfd_elf_string_from_elf_section
 	    (input_bfd, symtab_hdr->sh_link, sym->st_name);
diff --git a/bfd/elf32-metag.c b/bfd/elf32-metag.c
index ee0d19b08b9..da7c5f1756b 100644
--- a/bfd/elf32-metag.c
+++ b/bfd/elf32-metag.c
@@ -1414,8 +1414,7 @@ section, which means that the addend must be adjusted
 accordingly.  */
 
 static int
-elf_metag_relocate_section (bfd *output_bfd,
-			    struct bfd_link_info *info,
+elf_metag_relocate_section (struct bfd_link_info *info,
 			    bfd *input_bfd,
 			    asection *input_section,
 			    bfd_byte *contents,
@@ -1470,7 +1469,8 @@ elf_metag_relocate_section (bfd *output_bfd,
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections [r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 
 	  name = bfd_elf_string_from_elf_section
 	    (input_bfd, symtab_hdr->sh_link, sym->st_name);
@@ -1533,7 +1533,7 @@ elf_metag_relocate_section (bfd *output_bfd,
 	      skip = false;
 	      relocate = false;
 
-	      outrel.r_offset = _bfd_elf_section_offset (output_bfd,
+	      outrel.r_offset = _bfd_elf_section_offset (info->output_bfd,
 							 info,
 							 input_section,
 							 rel->r_offset);
@@ -1577,7 +1577,7 @@ elf_metag_relocate_section (bfd *output_bfd,
 
 	      loc = sreloc->contents;
 	      loc += sreloc->reloc_count * sizeof(Elf32_External_Rela);
-	      bfd_elf32_swap_reloca_out (output_bfd, &outrel,loc);
+	      bfd_elf32_swap_reloca_out (info->output_bfd, &outrel,loc);
 	      ++sreloc->reloc_count;
 
 	      /* If this reloc is against an external symbol, we do
@@ -1701,10 +1701,10 @@ elf_metag_relocate_section (bfd *output_bfd,
 		    outrel.r_addend = relocation;
 		    loc = s->contents;
 		    loc += s->reloc_count++ * sizeof (Elf32_External_Rela);
-		    bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+		    bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 		  }
 		else
-		  bfd_put_32 (output_bfd, relocation,
+		  bfd_put_32 (info->output_bfd, relocation,
 			      htab->etab.sgot->contents + off);
 	      }
 
@@ -1789,23 +1789,25 @@ elf_metag_relocate_section (bfd *output_bfd,
 					   + htab->etab.sgot->output_offset);
 			outrel.r_info = ELF32_R_INFO (indx, R_METAG_TLS_DTPMOD);
 			outrel.r_addend = 0;
-			bfd_put_32 (output_bfd, 0, htab->etab.sgot->contents + cur_off);
+			bfd_put_32 (info->output_bfd, 0,
+				    htab->etab.sgot->contents + cur_off);
 
-			bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+			bfd_elf32_swap_reloca_out (info->output_bfd,
+						   &outrel, loc);
 			htab->etab.srelgot->reloc_count++;
 			loc += sizeof (Elf32_External_Rela);
 
 			if (indx == 0)
-			  bfd_put_32 (output_bfd, 0,
+			  bfd_put_32 (info->output_bfd, 0,
 				      htab->etab.sgot->contents + cur_off + 4);
 			else
 			  {
-			    bfd_put_32 (output_bfd, 0,
+			    bfd_put_32 (info->output_bfd, 0,
 					htab->etab.sgot->contents + cur_off + 4);
 			    outrel.r_info = ELF32_R_INFO (indx,
 						      R_METAG_TLS_DTPOFF);
 			    outrel.r_offset += 4;
-			    bfd_elf32_swap_reloca_out (output_bfd,
+			    bfd_elf32_swap_reloca_out (info->output_bfd,
 						       &outrel, loc);
 			    htab->etab.srelgot->reloc_count++;
 			    loc += sizeof (Elf32_External_Rela);
@@ -1841,12 +1843,13 @@ elf_metag_relocate_section (bfd *output_bfd,
 			else
 			  outrel.r_addend = 0;
 
-			bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+			bfd_elf32_swap_reloca_out (info->output_bfd,
+						   &outrel, loc);
 			htab->etab.srelgot->reloc_count++;
 			loc += sizeof (Elf32_External_Rela);
 		      }
 		    else
-		      bfd_put_32 (output_bfd, tpoff (info, relocation),
+		      bfd_put_32 (info->output_bfd, tpoff (info, relocation),
 				  htab->etab.sgot->contents + cur_off);
 
 		    cur_off += 4;
@@ -1910,7 +1913,7 @@ elf_metag_relocate_section (bfd *output_bfd,
 		outrel.r_info = ELF32_R_INFO (0, R_METAG_TLS_DTPMOD);
 		loc = htab->etab.srelgot->contents;
 		loc += htab->etab.srelgot->reloc_count++ * sizeof (Elf32_External_Rela);
-		bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+		bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 		htab->tls_ldm_got.offset |= 1;
 	      }
 
@@ -2679,8 +2682,7 @@ allocate_dynrelocs (struct elf_link_hash_entry *eh, void *inf)
 /* Set the sizes of the dynamic sections.  */
 
 static bool
-elf_metag_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-			      struct bfd_link_info *info)
+elf_metag_late_size_sections (struct bfd_link_info *info)
 {
   struct elf_metag_link_hash_table *htab;
   bfd *dynobj;
@@ -2865,15 +2867,14 @@ elf_metag_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
 	}
     }
 
-  return _bfd_elf_add_dynamic_tags (output_bfd, info, relocs);
+  return _bfd_elf_add_dynamic_tags (info, relocs);
 }
 
 /* Finish up dynamic symbol handling.  We set the contents of various
    dynamic sections here.  */
 
 static bool
-elf_metag_finish_dynamic_symbol (bfd *output_bfd,
-				 struct bfd_link_info *info,
+elf_metag_finish_dynamic_symbol (struct bfd_link_info *info,
 				 struct elf_link_hash_entry *eh,
 				 Elf_Internal_Sym *sym)
 {
@@ -2924,20 +2925,20 @@ elf_metag_finish_dynamic_symbol (bfd *output_bfd,
       /* Fill in the entry in the procedure linkage table.  */
       if (! bfd_link_pic (info))
 	{
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 		      (plt_entry[0]
 		       | (((got_entry >> 16) & 0xffff) << 3)),
 		      splt->contents + eh->plt.offset);
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 		      (plt_entry[1]
 		       | ((got_entry & 0xffff) << 3)),
 		      splt->contents + eh->plt.offset + 4);
-	  bfd_put_32 (output_bfd, plt_entry[2],
+	  bfd_put_32 (info->output_bfd, plt_entry[2],
 		      splt->contents + eh->plt.offset + 8);
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 		      (plt_entry[3] | (plt_index << 3)),
 		      splt->contents + eh->plt.offset + 12);
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 		      (plt_entry[4]
 		       | ((((unsigned int) ((- (eh->plt.offset + 16)) >> 2)) & 0x7ffff) << 5)),
 		      splt->contents + eh->plt.offset + 16);
@@ -2947,25 +2948,25 @@ elf_metag_finish_dynamic_symbol (bfd *output_bfd,
 	  bfd_vma addr = got_entry - (splt->output_section->vma +
 				      splt->output_offset + eh->plt.offset);
 
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 		      plt_pic_entry[0] | (((addr >> 16) & 0xffff) << 3),
 		      splt->contents + eh->plt.offset);
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 		      plt_pic_entry[1] | ((addr & 0xffff) << 3),
 		      splt->contents + eh->plt.offset + 4);
-	  bfd_put_32 (output_bfd, plt_pic_entry[2],
+	  bfd_put_32 (info->output_bfd, plt_pic_entry[2],
 		      splt->contents + eh->plt.offset + 8);
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 		      (plt_pic_entry[3] | (plt_index << 3)),
 		      splt->contents + eh->plt.offset + 12);
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 		      (plt_pic_entry[4]
 		       + ((((unsigned int) ((- (eh->plt.offset + 16)) >> 2)) & 0x7ffff) << 5)),
 		      splt->contents + eh->plt.offset + 16);
 	}
 
       /* Fill in the entry in the global offset table.  */
-      bfd_put_32 (output_bfd,
+      bfd_put_32 (info->output_bfd,
 		  (splt->output_section->vma
 		   + splt->output_offset
 		   + eh->plt.offset
@@ -2980,7 +2981,7 @@ elf_metag_finish_dynamic_symbol (bfd *output_bfd,
       rel.r_addend = 0;
       loc = htab->etab.srelplt->contents;
       loc += plt_index * sizeof(Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rel, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rel, loc);
 
       if (!eh->def_regular)
 	{
@@ -3019,14 +3020,15 @@ elf_metag_finish_dynamic_symbol (bfd *output_bfd,
 	{
 	  if ((eh->got.offset & 1) != 0)
 	    abort ();
-	  bfd_put_32 (output_bfd, 0, htab->etab.sgot->contents + eh->got.offset);
+	  bfd_put_32 (info->output_bfd, 0,
+		      htab->etab.sgot->contents + eh->got.offset);
 	  rel.r_info = ELF32_R_INFO (eh->dynindx, R_METAG_GLOB_DAT);
 	  rel.r_addend = 0;
 	}
 
       loc = htab->etab.srelgot->contents;
       loc += htab->etab.srelgot->reloc_count++ * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rel, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rel, loc);
     }
 
   if (eh->needs_copy)
@@ -3050,7 +3052,7 @@ elf_metag_finish_dynamic_symbol (bfd *output_bfd,
       else
 	s = htab->etab.srelbss;
       loc = s->contents + s->reloc_count++ * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rel, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rel, loc);
     }
 
   /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute.  */
@@ -3103,8 +3105,7 @@ elf_metag_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
 /* Finish up the dynamic sections.  */
 
 static bool
-elf_metag_finish_dynamic_sections (bfd *output_bfd,
-				   struct bfd_link_info *info,
+elf_metag_finish_dynamic_sections (struct bfd_link_info *info,
 				   bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   bfd *dynobj;
@@ -3141,19 +3142,19 @@ elf_metag_finish_dynamic_sections (bfd *output_bfd,
 	    case DT_PLTGOT:
 	      s = htab->etab.sgot;
 	      dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    case DT_JMPREL:
 	      s = htab->etab.srelplt;
 	      dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    case DT_PLTRELSZ:
 	      s = htab->etab.srelplt;
 	      dyn.d_un.d_val = s->size;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 	    }
 
@@ -3170,27 +3171,33 @@ elf_metag_finish_dynamic_sections (bfd *output_bfd,
 	  if (bfd_link_pic (info))
 	    {
 	      addr -= splt->output_section->vma + splt->output_offset;
-	      bfd_put_32 (output_bfd,
+	      bfd_put_32 (info->output_bfd,
 			  plt0_pic_entry[0] | (((addr >> 16) & 0xffff) << 3),
 			  splt->contents);
-	      bfd_put_32 (output_bfd,
+	      bfd_put_32 (info->output_bfd,
 			  plt0_pic_entry[1] | ((addr & 0xffff) << 3),
 			  splt->contents + 4);
-	      bfd_put_32 (output_bfd, plt0_pic_entry[2], splt->contents + 8);
-	      bfd_put_32 (output_bfd, plt0_pic_entry[3], splt->contents + 12);
-	      bfd_put_32 (output_bfd, plt0_pic_entry[4], splt->contents + 16);
+	      bfd_put_32 (info->output_bfd, plt0_pic_entry[2],
+			  splt->contents + 8);
+	      bfd_put_32 (info->output_bfd, plt0_pic_entry[3],
+			  splt->contents + 12);
+	      bfd_put_32 (info->output_bfd, plt0_pic_entry[4],
+			  splt->contents + 16);
 	    }
 	  else
 	    {
-	      bfd_put_32 (output_bfd,
+	      bfd_put_32 (info->output_bfd,
 			  plt0_entry[0] | (((addr >> 16) & 0xffff) << 3),
 			  splt->contents);
-	      bfd_put_32 (output_bfd,
+	      bfd_put_32 (info->output_bfd,
 			  plt0_entry[1] | ((addr & 0xffff) << 3),
 			  splt->contents + 4);
-	      bfd_put_32 (output_bfd, plt0_entry[2], splt->contents + 8);
-	      bfd_put_32 (output_bfd, plt0_entry[3], splt->contents + 12);
-	      bfd_put_32 (output_bfd, plt0_entry[4], splt->contents + 16);
+	      bfd_put_32 (info->output_bfd, plt0_entry[2],
+			  splt->contents + 8);
+	      bfd_put_32 (info->output_bfd, plt0_entry[3],
+			  splt->contents + 12);
+	      bfd_put_32 (info->output_bfd, plt0_entry[4],
+			  splt->contents + 16);
 	    }
 
 	  elf_section_data (splt->output_section)->this_hdr.sh_entsize =
@@ -3202,7 +3209,7 @@ elf_metag_finish_dynamic_sections (bfd *output_bfd,
     {
       /* Fill in the first entry in the global offset table.
 	 We use it to point to our dynamic section, if we have one.  */
-      bfd_put_32 (output_bfd,
+      bfd_put_32 (info->output_bfd,
 		  sdyn ? sdyn->output_section->vma + sdyn->output_offset : 0,
 		  htab->etab.sgot->contents);
 
diff --git a/bfd/elf32-microblaze.c b/bfd/elf32-microblaze.c
index 2f8167c4d9c..52c2b247dc8 100644
--- a/bfd/elf32-microblaze.c
+++ b/bfd/elf32-microblaze.c
@@ -957,8 +957,7 @@ microblaze_elf_output_dynamic_relocation (bfd *output_bfd,
    accordingly.  */
 
 static int
-microblaze_elf_relocate_section (bfd *output_bfd,
-				 struct bfd_link_info *info,
+microblaze_elf_relocate_section (struct bfd_link_info *info,
 				 bfd *input_bfd,
 				 asection *input_section,
 				 bfd_byte *contents,
@@ -970,7 +969,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
   Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (input_bfd);
   struct elf_link_hash_entry **sym_hashes = elf_sym_hashes (input_bfd);
   Elf_Internal_Rela *rel, *relend;
-  int endian = (bfd_little_endian (output_bfd)) ? 0 : 2;
+  int endian = (bfd_little_endian (info->output_bfd)) ? 0 : 2;
   /* Assume success.  */
   bool ret = true;
   asection *sreloc;
@@ -1080,7 +1079,8 @@ microblaze_elf_relocate_section (bfd *output_bfd,
 	      if (sec == 0)
 		continue;
 	      sym_name = "<local symbol>";
-	      relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	      relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						    sym, &sec, rel);
 	      /* r_addend may have changed if the reference section was
 		 a merge section.  */
 	      addend = rel->r_addend;
@@ -1357,11 +1357,11 @@ microblaze_elf_relocate_section (bfd *output_bfd,
 		    if (IS_TLS_LD(tls_type))
 		      {
 			if (! bfd_link_pic (info))
-			  bfd_put_32 (output_bfd, 1,
+			  bfd_put_32 (info->output_bfd, 1,
 				      htab->elf.sgot->contents + off);
 			else
 			  microblaze_elf_output_dynamic_relocation
-			    (output_bfd,
+			    (info->output_bfd,
 			     htab->elf.srelgot,
 			     htab->elf.srelgot->reloc_count++,
 			     /* symindex= */ 0, R_MICROBLAZE_TLSDTPMOD32,
@@ -1370,11 +1370,11 @@ microblaze_elf_relocate_section (bfd *output_bfd,
 		    else if (IS_TLS_GD(tls_type))
 		      {
 			if (! need_relocs)
-			  bfd_put_32 (output_bfd, 1,
+			  bfd_put_32 (info->output_bfd, 1,
 				      htab->elf.sgot->contents + off);
 			else
 			  microblaze_elf_output_dynamic_relocation
-			    (output_bfd,
+			    (info->output_bfd,
 			     htab->elf.srelgot,
 			     htab->elf.srelgot->reloc_count++,
 			     /* symindex= */ indx, R_MICROBLAZE_TLSDTPMOD32,
@@ -1392,7 +1392,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
 		      {
 			/* For LD, offset should be 0 */
 			*offp |= 1;
-			bfd_put_32 (output_bfd, 0,
+			bfd_put_32 (info->output_bfd, 0,
 				    htab->elf.sgot->contents + off2);
 		      }
 		    else if (IS_TLS_GD(tls_type))
@@ -1401,18 +1401,18 @@ microblaze_elf_relocate_section (bfd *output_bfd,
 			static_value -= dtprel_base(info);
 			if (need_relocs)
 			  microblaze_elf_output_dynamic_relocation
-			    (output_bfd,
+			    (info->output_bfd,
 			     htab->elf.srelgot,
 			     htab->elf.srelgot->reloc_count++,
 			     /* symindex= */ indx, R_MICROBLAZE_TLSDTPREL32,
 			     got_offset, indx ? 0 : static_value);
 			else
-			  bfd_put_32 (output_bfd, static_value,
+			  bfd_put_32 (info->output_bfd, static_value,
 				      htab->elf.sgot->contents + off2);
 		      }
 		    else
 		      {
-			bfd_put_32 (output_bfd, static_value,
+			bfd_put_32 (info->output_bfd, static_value,
 				    htab->elf.sgot->contents + off2);
 
 			/* Relocs for dyn symbols generated by
@@ -1421,7 +1421,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
 			  {
 			    *offp |= 1;
 			    microblaze_elf_output_dynamic_relocation
-			      (output_bfd,
+			      (info->output_bfd,
 			       htab->elf.srelgot,
 			       htab->elf.srelgot->reloc_count++,
 			       /* symindex= */ indx, R_MICROBLAZE_REL,
@@ -1555,8 +1555,8 @@ microblaze_elf_relocate_section (bfd *output_bfd,
 		    skip = false;
 
 		    outrel.r_offset =
-		      _bfd_elf_section_offset (output_bfd, info, input_section,
-					       rel->r_offset);
+		      _bfd_elf_section_offset (info->output_bfd, info,
+					       input_section, rel->r_offset);
 		    if (outrel.r_offset == (bfd_vma) -1)
 		      skip = true;
 		    else if (outrel.r_offset == (bfd_vma) -2)
@@ -1596,7 +1596,7 @@ microblaze_elf_relocate_section (bfd *output_bfd,
 
 		    loc = sreloc->contents;
 		    loc += sreloc->reloc_count++ * sizeof (Elf32_External_Rela);
-		    bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+		    bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 		    break;
 		  }
 		else
@@ -2955,8 +2955,7 @@ allocate_dynrelocs (struct elf_link_hash_entry *h, void * dat)
 /* Set the sizes of the dynamic sections.  */
 
 static bool
-microblaze_elf_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-				   struct bfd_link_info *info)
+microblaze_elf_late_size_sections (struct bfd_link_info *info)
 {
   struct elf32_mb_link_hash_table *htab;
   bfd *dynobj;
@@ -3143,15 +3142,14 @@ microblaze_elf_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
 
   /* ??? Force DF_BIND_NOW?  */
   info->flags |= DF_BIND_NOW;
-  return _bfd_elf_add_dynamic_tags (output_bfd, info, true);
+  return _bfd_elf_add_dynamic_tags (info, true);
 }
 
 /* Finish up dynamic symbol handling.  We set the contents of various
    dynamic sections here.  */
 
 static bool
-microblaze_elf_finish_dynamic_symbol (bfd *output_bfd,
-				      struct bfd_link_info *info,
+microblaze_elf_finish_dynamic_symbol (struct bfd_link_info *info,
 				      struct elf_link_hash_entry *h,
 				      Elf_Internal_Sym *sym)
 {
@@ -3189,21 +3187,21 @@ microblaze_elf_finish_dynamic_symbol (bfd *output_bfd,
 	got_addr += sgotplt->output_section->vma + sgotplt->output_offset;
 
       /* Fill in the entry in the procedure linkage table.  */
-      bfd_put_32 (output_bfd, PLT_ENTRY_WORD_0 + ((got_addr >> 16) & 0xffff),
+      bfd_put_32 (info->output_bfd, PLT_ENTRY_WORD_0 + ((got_addr >> 16) & 0xffff),
 		  splt->contents + h->plt.offset);
       if (bfd_link_pic (info))
-	bfd_put_32 (output_bfd, PLT_ENTRY_WORD_1 + (got_addr & 0xffff),
+	bfd_put_32 (info->output_bfd, PLT_ENTRY_WORD_1 + (got_addr & 0xffff),
 		    splt->contents + h->plt.offset + 4);
       else
-	bfd_put_32 (output_bfd, PLT_ENTRY_WORD_1_NOPIC + (got_addr & 0xffff),
+	bfd_put_32 (info->output_bfd, PLT_ENTRY_WORD_1_NOPIC + (got_addr & 0xffff),
 		    splt->contents + h->plt.offset + 4);
-      bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD_2,
+      bfd_put_32 (info->output_bfd, PLT_ENTRY_WORD_2,
 		  splt->contents + h->plt.offset + 8);
-      bfd_put_32 (output_bfd, (bfd_vma) PLT_ENTRY_WORD_3,
+      bfd_put_32 (info->output_bfd, PLT_ENTRY_WORD_3,
 		  splt->contents + h->plt.offset + 12);
 
       /* Any additions to the .got section??? */
-      /*      bfd_put_32 (output_bfd,
+      /*      bfd_put_32 (info->output_bfd,
 	      splt->output_section->vma + splt->output_offset + h->plt.offset + 4,
 	      sgotplt->contents + got_offset); */
 
@@ -3215,7 +3213,7 @@ microblaze_elf_finish_dynamic_symbol (bfd *output_bfd,
       rela.r_addend = 0;
       loc = srela->contents;
       loc += plt_index * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
 
       if (!h->def_regular)
 	{
@@ -3264,7 +3262,7 @@ microblaze_elf_finish_dynamic_symbol (bfd *output_bfd,
 	       it is too late to change our minds now...  */
 	    value += sec->output_section->vma + sec->output_offset;
 
-	  microblaze_elf_output_dynamic_relocation (output_bfd,
+	  microblaze_elf_output_dynamic_relocation (info->output_bfd,
 						    srela, srela->reloc_count++,
 						    /* symindex= */ 0,
 						    R_MICROBLAZE_REL, offset,
@@ -3272,14 +3270,14 @@ microblaze_elf_finish_dynamic_symbol (bfd *output_bfd,
 	}
       else
 	{
-	  microblaze_elf_output_dynamic_relocation (output_bfd,
+	  microblaze_elf_output_dynamic_relocation (info->output_bfd,
 						    srela, srela->reloc_count++,
 						    h->dynindx,
 						    R_MICROBLAZE_GLOB_DAT,
 						    offset, 0);
 	}
 
-      bfd_put_32 (output_bfd, (bfd_vma) 0,
+      bfd_put_32 (info->output_bfd, 0,
 		  sgot->contents + (h->got.offset &~ (bfd_vma) 1));
     }
 
@@ -3303,7 +3301,7 @@ microblaze_elf_finish_dynamic_symbol (bfd *output_bfd,
       else
 	s = htab->elf.srelbss;
       loc = s->contents + s->reloc_count++ * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
     }
 
   /* Mark some specially defined symbols as absolute.  */
@@ -3319,8 +3317,7 @@ microblaze_elf_finish_dynamic_symbol (bfd *output_bfd,
 /* Finish up the dynamic sections.  */
 
 static bool
-microblaze_elf_finish_dynamic_sections (bfd *output_bfd,
-					struct bfd_link_info *info,
+microblaze_elf_finish_dynamic_sections (struct bfd_link_info *info,
 					bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   bfd *dynobj;
@@ -3380,7 +3377,7 @@ microblaze_elf_finish_dynamic_sections (bfd *output_bfd,
 	      else
 		dyn.d_un.d_val = s->size;
 	    }
-	  bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	  bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	}
 
       splt = htab->elf.splt;
@@ -3391,7 +3388,7 @@ microblaze_elf_finish_dynamic_sections (bfd *output_bfd,
       if (splt->size > 0)
 	{
 	  memset (splt->contents, 0, PLT_ENTRY_SIZE);
-	  bfd_put_32 (output_bfd, (bfd_vma) 0x80000000 /* nop.  */,
+	  bfd_put_32 (info->output_bfd, 0x80000000 /* nop.  */,
 		      splt->contents + splt->size - 4);
 
 	  if (splt->output_section != bfd_abs_section_ptr)
@@ -3405,9 +3402,9 @@ microblaze_elf_finish_dynamic_sections (bfd *output_bfd,
   if (sgot && sgot->size > 0)
     {
       if (sdyn == NULL)
-	bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
+	bfd_put_32 (info->output_bfd, 0, sgot->contents);
       else
-	bfd_put_32 (output_bfd,
+	bfd_put_32 (info->output_bfd,
 		    sdyn->output_section->vma + sdyn->output_offset,
 		    sgot->contents);
       elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
diff --git a/bfd/elf32-moxie.c b/bfd/elf32-moxie.c
index cd2114b6944..18eb9c2124f 100644
--- a/bfd/elf32-moxie.c
+++ b/bfd/elf32-moxie.c
@@ -198,8 +198,7 @@ moxie_final_link_relocate (reloc_howto_type *howto,
    accordingly.  */
 
 static int
-moxie_elf_relocate_section (bfd *output_bfd,
-			    struct bfd_link_info *info,
+moxie_elf_relocate_section (struct bfd_link_info *info,
 			    bfd *input_bfd,
 			    asection *input_section,
 			    bfd_byte *contents,
@@ -239,7 +238,8 @@ moxie_elf_relocate_section (bfd *output_bfd,
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections [r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 
 	  name = bfd_elf_string_from_elf_section
 	    (input_bfd, symtab_hdr->sh_link, sym->st_name);
diff --git a/bfd/elf32-msp430.c b/bfd/elf32-msp430.c
index 065efc4fa83..add0a6826ae 100644
--- a/bfd/elf32-msp430.c
+++ b/bfd/elf32-msp430.c
@@ -1414,8 +1414,7 @@ msp430_final_link_relocate (reloc_howto_type *	   howto,
 /* Relocate an MSP430 ELF section.  */
 
 static int
-elf32_msp430_relocate_section (bfd * output_bfd ATTRIBUTE_UNUSED,
-			       struct bfd_link_info * info,
+elf32_msp430_relocate_section (struct bfd_link_info * info,
 			       bfd * input_bfd,
 			       asection * input_section,
 			       bfd_byte * contents,
@@ -1460,7 +1459,8 @@ elf32_msp430_relocate_section (bfd * output_bfd ATTRIBUTE_UNUSED,
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections[r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 
 	  name = bfd_elf_string_from_elf_section
 	      (input_bfd, symtab_hdr->sh_link, sym->st_name);
diff --git a/bfd/elf32-mt.c b/bfd/elf32-mt.c
index 6e81db3ea0b..0bd8f05bb2d 100644
--- a/bfd/elf32-mt.c
+++ b/bfd/elf32-mt.c
@@ -38,10 +38,6 @@ static bfd_reloc_status_type mt_final_link_relocate
   (reloc_howto_type *, bfd *, asection *, bfd_byte *,
    Elf_Internal_Rela *, bfd_vma);
 
-static int mt_elf_relocate_section
-  (bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *,
-   Elf_Internal_Rela *, Elf_Internal_Sym *, asection **);
-
 /* Relocation tables.  */
 static reloc_howto_type mt_elf_howto_table [] =
 {
@@ -299,8 +295,7 @@ mt_final_link_relocate
 
 static int
 mt_elf_relocate_section
-    (bfd *		     output_bfd ATTRIBUTE_UNUSED,
-     struct bfd_link_info *  info,
+    (struct bfd_link_info *  info,
      bfd *		     input_bfd,
      asection *		     input_section,
      bfd_byte *		     contents,
@@ -342,7 +337,8 @@ mt_elf_relocate_section
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections [r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 
 	  name = bfd_elf_string_from_elf_section
 	    (input_bfd, symtab_hdr->sh_link, sym->st_name);
diff --git a/bfd/elf32-nds32.c b/bfd/elf32-nds32.c
index 1912f94caa3..937ada25f05 100644
--- a/bfd/elf32-nds32.c
+++ b/bfd/elf32-nds32.c
@@ -4359,8 +4359,7 @@ elf32_nds32_add_dynreloc (bfd *output_bfd,
 /* Set the sizes of the dynamic sections.  */
 
 static bool
-nds32_elf_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-			      struct bfd_link_info *info)
+nds32_elf_late_size_sections (struct bfd_link_info *info)
 {
   struct elf_nds32_link_hash_table *htab;
   bfd *dynobj;
@@ -4587,7 +4586,7 @@ nds32_elf_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
       s->alloced = 1;
     }
 
-  return _bfd_elf_add_dynamic_tags (output_bfd, info, relocs);
+  return _bfd_elf_add_dynamic_tags (info, relocs);
 }
 
 static bfd_reloc_status_type
@@ -5045,8 +5044,7 @@ fls (register unsigned int x)
   (elf_nds32_tdata (bfd)->local_tlsdesc_gotent)
 
 static int
-nds32_elf_relocate_section (bfd *		   output_bfd ATTRIBUTE_UNUSED,
-			    struct bfd_link_info * info,
+nds32_elf_relocate_section (struct bfd_link_info * info,
 			    bfd *		   input_bfd,
 			    asection *		   input_section,
 			    bfd_byte *		   contents,
@@ -5096,7 +5094,7 @@ nds32_elf_relocate_section (bfd *		   output_bfd ATTRIBUTE_UNUSED,
   if ((!bfd_link_relocatable (info)))
     {
       is_SDA_BASE_set = 1;
-      r = nds32_elf_final_sda_base (output_bfd, info, &gp, true);
+      r = nds32_elf_final_sda_base (info->output_bfd, info, &gp, true);
       if (r != bfd_reloc_ok)
 	return false;
     }
@@ -5107,7 +5105,7 @@ nds32_elf_relocate_section (bfd *		   output_bfd ATTRIBUTE_UNUSED,
   /* Use gp as fp to prevent truncated fit.  Because in relaxation time
      the fp value is set as gp, and it has be reverted for instruction
      setting fp.  */
-  fpbase_addr = elf_gp (output_bfd);
+  fpbase_addr = elf_gp (info->output_bfd);
 
   /* Deal with (dynamic) relocations.  */
   for (rel = relocs; rel < relend; rel++)
@@ -5167,7 +5165,7 @@ nds32_elf_relocate_section (bfd *		   output_bfd ATTRIBUTE_UNUSED,
       else if (ELF32_R_TYPE (rel->r_info) == R_NDS32_RELAX_REGION_END
 	       && (rel->r_addend & R_NDS32_RELAX_REGION_OMIT_FP_FLAG))
 	{
-	  fpbase_addr = elf_gp (output_bfd);
+	  fpbase_addr = elf_gp (info->output_bfd);
 	}
 
       /* Skip the relocations used for relaxation.  */
@@ -5193,7 +5191,8 @@ nds32_elf_relocate_section (bfd *		   output_bfd ATTRIBUTE_UNUSED,
 	  sym = local_syms + r_symndx;
 	  sec = local_sections[r_symndx];
 
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 	  addend = rel->r_addend;
 
 	  /* keep symbol location for static TLS_IE GOT entry  */
@@ -5280,7 +5279,7 @@ nds32_elf_relocate_section (bfd *		   output_bfd ATTRIBUTE_UNUSED,
 	case R_NDS32_GOTOFF_LO19:
 	  BFD_ASSERT (sgot != NULL);
 
-	  relocation -= elf_gp (output_bfd);
+	  relocation -= elf_gp (info->output_bfd);
 	  break;
 
 	case R_NDS32_9_PLTREL:
@@ -5324,14 +5323,14 @@ nds32_elf_relocate_section (bfd *		   output_bfd ATTRIBUTE_UNUSED,
 		 using -Bsymbolic.  */
 	      if (h)
 		h->plt.offset = (bfd_vma) -1;   /* Cancel PLT trampoline.  */
-	      relocation -= elf_gp (output_bfd);
+	      relocation -= elf_gp (info->output_bfd);
 	      break;
 	    }
 
 	  relocation = (splt->output_section->vma
 			+ splt->output_offset + h->plt.offset);
 
-	  relocation -= elf_gp (output_bfd);
+	  relocation -= elf_gp (info->output_bfd);
 	  break;
 
 	case R_NDS32_PLTREL_HI20:
@@ -5370,7 +5369,7 @@ nds32_elf_relocate_section (bfd *		   output_bfd ATTRIBUTE_UNUSED,
 	case R_NDS32_GOTPC20:
 	  /* .got(_GLOBAL_OFFSET_TABLE_) - pc relocation
 	     ld24 rx,#_GLOBAL_OFFSET_TABLE_  */
-	  relocation = elf_gp (output_bfd);
+	  relocation = elf_gp (info->output_bfd);
 	  break;
 
 	case R_NDS32_GOTPC_HI20:
@@ -5383,7 +5382,7 @@ nds32_elf_relocate_section (bfd *		   output_bfd ATTRIBUTE_UNUSED,
 	     bl .+4
 	     seth rx,#shigh(_GLOBAL_OFFSET_TABLE_)
 	     add3 rx,rx,#low(_GLOBAL_OFFSET_TABLE_ +4)  */
-	  relocation = elf_gp (output_bfd);
+	  relocation = elf_gp (info->output_bfd);
 	  relocation -= (input_section->output_section->vma
 			 + input_section->output_offset + rel->r_offset);
 	  break;
@@ -5430,12 +5429,13 @@ nds32_elf_relocate_section (bfd *		   output_bfd ATTRIBUTE_UNUSED,
 		    off &= ~1;
 		  else
 		    {
-		      bfd_put_32 (output_bfd, relocation, sgot->contents + off);
+		      bfd_put_32 (info->output_bfd, relocation,
+				  sgot->contents + off);
 		      h->got.offset |= 1;
 		    }
 		}
 	      relocation = sgot->output_section->vma + sgot->output_offset + off
-			   - elf_gp (output_bfd);
+			   - elf_gp (info->output_bfd);
 	    }
 	  else
 	    {
@@ -5454,7 +5454,8 @@ nds32_elf_relocate_section (bfd *		   output_bfd ATTRIBUTE_UNUSED,
 		off &= ~1;
 	      else
 		{
-		  bfd_put_32 (output_bfd, relocation, sgot->contents + off);
+		  bfd_put_32 (info->output_bfd, relocation,
+			      sgot->contents + off);
 
 		  if (bfd_link_pic (info))
 		    {
@@ -5466,20 +5467,20 @@ nds32_elf_relocate_section (bfd *		   output_bfd ATTRIBUTE_UNUSED,
 		      srelgot = bfd_get_section_by_name (dynobj, ".rela.got");
 		      BFD_ASSERT (srelgot != NULL);
 
-		      outrel.r_offset = (elf_gp (output_bfd)
+		      outrel.r_offset = (elf_gp (info->output_bfd)
 					 + sgot->output_offset + off);
 		      outrel.r_info = ELF32_R_INFO (0, R_NDS32_RELATIVE);
 		      outrel.r_addend = relocation;
 		      loc = srelgot->contents;
 		      loc +=
 			srelgot->reloc_count * sizeof (Elf32_External_Rela);
-		      bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+		      bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 		      ++srelgot->reloc_count;
 		    }
 		  local_got_offsets[r_symndx] |= 1;
 		}
 	      relocation = sgot->output_section->vma + sgot->output_offset + off
-			   - elf_gp (output_bfd);
+			   - elf_gp (info->output_bfd);
 	    }
 
 	  break;
@@ -5546,7 +5547,7 @@ nds32_elf_relocate_section (bfd *		   output_bfd ATTRIBUTE_UNUSED,
 	      skip = false;
 	      relocate = false;
 
-	      outrel.r_offset = _bfd_elf_section_offset (output_bfd,
+	      outrel.r_offset = _bfd_elf_section_offset (info->output_bfd,
 							 info,
 							 input_section,
 							 rel->r_offset);
@@ -5590,7 +5591,7 @@ nds32_elf_relocate_section (bfd *		   output_bfd ATTRIBUTE_UNUSED,
 			  if (h->got.offset != (bfd_vma) -1
 			      && (h->got.offset & 1) == 0)
 			    {
-			      bfd_put_32 (output_bfd, outrel.r_addend,
+			      bfd_put_32 (info->output_bfd, outrel.r_addend,
 					  sgot->contents + h->got.offset);
 			    }
 			}
@@ -5614,7 +5615,7 @@ nds32_elf_relocate_section (bfd *		   output_bfd ATTRIBUTE_UNUSED,
 
 	      loc = sreloc->contents;
 	      loc += sreloc->reloc_count * sizeof (Elf32_External_Rela);
-	      bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+	      bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 	      ++sreloc->reloc_count;
 
 	      /* If this reloc is against an external symbol, we do
@@ -5702,7 +5703,7 @@ nds32_elf_relocate_section (bfd *		   output_bfd ATTRIBUTE_UNUSED,
 		    off &= ~1;
 		  else
 		    {
-		      bfd_put_32 (output_bfd, relocation,
+		      bfd_put_32 (info->output_bfd, relocation,
 				  sgot->contents + off);
 		      h->got.offset |= 1;
 		    }
@@ -5724,7 +5725,8 @@ nds32_elf_relocate_section (bfd *		   output_bfd ATTRIBUTE_UNUSED,
 		off &= ~1;
 	      else
 		{
-		  bfd_put_32 (output_bfd, relocation, sgot->contents + off);
+		  bfd_put_32 (info->output_bfd, relocation,
+			      sgot->contents + off);
 
 		  if (bfd_link_pic (info))
 		    {
@@ -5736,21 +5738,21 @@ nds32_elf_relocate_section (bfd *		   output_bfd ATTRIBUTE_UNUSED,
 		      srelgot = bfd_get_section_by_name (dynobj, ".rela.got");
 		      BFD_ASSERT (srelgot != NULL);
 
-		      outrel.r_offset = (elf_gp (output_bfd)
+		      outrel.r_offset = (elf_gp (info->output_bfd)
 					 + sgot->output_offset + off);
 		      outrel.r_info = ELF32_R_INFO (0, R_NDS32_RELATIVE);
 		      outrel.r_addend = relocation;
 		      loc = srelgot->contents;
 		      loc +=
 			srelgot->reloc_count * sizeof (Elf32_External_Rela);
-		      bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+		      bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 		      ++srelgot->reloc_count;
 		    }
 		  local_got_offsets[r_symndx] |= 1;
 		}
 	    }
 	  relocation = sgot->output_section->vma + sgot->output_offset + off
-	    - elf_gp (output_bfd);
+	    - elf_gp (info->output_bfd);
 
 	  if (relocation & align)
 	    {
@@ -5793,7 +5795,7 @@ nds32_elf_relocate_section (bfd *		   output_bfd ATTRIBUTE_UNUSED,
 
 	  /* If the symbol is in the abs section, the out_bfd will be null.
 	     This happens when the relocation has a symbol@GOTOFF.  */
-	  r = nds32_elf_final_sda_base (output_bfd, info, &gp, false);
+	  r = nds32_elf_final_sda_base (info->output_bfd, info, &gp, false);
 	  if (r != bfd_reloc_ok)
 	    {
 	      _bfd_error_handler
@@ -5921,7 +5923,7 @@ nds32_elf_relocate_section (bfd *		   output_bfd ATTRIBUTE_UNUSED,
 
 		if (eff_tls_type & GOT_TLS_DESC)
 		  {
-		    relocation -= elf_gp (output_bfd);
+		    relocation -= elf_gp (info->output_bfd);
 		    if ((R_NDS32_TLS_DESC_HI20 == r_type) && (!need_relocs))
 		      {
 			/* TLS model shall be converted.  */
@@ -5930,7 +5932,7 @@ nds32_elf_relocate_section (bfd *		   output_bfd ATTRIBUTE_UNUSED,
 		  }
 		else if (eff_tls_type & GOT_TLS_IEGP)
 		  {
-		    relocation -= elf_gp (output_bfd);
+		    relocation -= elf_gp (info->output_bfd);
 		  }
 	      }
 	    else
@@ -5943,7 +5945,7 @@ nds32_elf_relocate_section (bfd *		   output_bfd ATTRIBUTE_UNUSED,
 		else if (eff_tls_type & (GOT_TLS_IE | GOT_TLS_IEGP))
 		  {
 		    if (eff_tls_type & GOT_TLS_IEGP)
-		      relocation -= elf_gp(output_bfd);
+		      relocation -= elf_gp(info->output_bfd);
 
 		    if (need_relocs)
 		      {
@@ -5955,18 +5957,19 @@ nds32_elf_relocate_section (bfd *		   output_bfd ATTRIBUTE_UNUSED,
 					   + sgot->output_offset + off);
 			outrel.r_info = ELF32_R_INFO (indx, R_NDS32_TLS_TPOFF);
 
-			elf32_nds32_add_dynreloc (output_bfd, info, srelgot,
-						  &outrel);
+			elf32_nds32_add_dynreloc (info->output_bfd, info,
+						  srelgot, &outrel);
 		      }
 		    else
 		      {
-			bfd_put_32 (output_bfd, gottpoff (info, relocation_sym),
+			bfd_put_32 (info->output_bfd,
+				    gottpoff (info, relocation_sym),
 				    sgot->contents + off);
 		      }
 		  }
 		else if (eff_tls_type & GOT_TLS_DESC)
 		  {
-		    relocation -= elf_gp (output_bfd);
+		    relocation -= elf_gp (info->output_bfd);
 		    if (need_relocs)
 		      {
 			if (indx == 0)
@@ -5986,22 +5989,25 @@ nds32_elf_relocate_section (bfd *		   output_bfd ATTRIBUTE_UNUSED,
 			    BFD_ASSERT (loc + sizeof (Elf32_External_Rela)
 					<= srelplt->contents + srelplt->size);
 
-			    bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+			    bfd_elf32_swap_reloca_out (info->output_bfd,
+						       &outrel, loc);
 			  }
 			else
 			  {
 			    loc = srelgot->contents;
 			    loc += srelgot->reloc_count * sizeof (Elf32_External_Rela);
-			    bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+			    bfd_elf32_swap_reloca_out (info->output_bfd,
+						       &outrel, loc);
 			    ++srelgot->reloc_count;
 			  }
 		      }
 		    else
 		      {
 			/* feed me!  */
-			bfd_put_32 (output_bfd, 0xdeadbeef,
+			bfd_put_32 (info->output_bfd, 0xdeadbeef,
 				    sgot->contents + off);
-			bfd_put_32 (output_bfd, gottpoff (info, relocation_sym),
+			bfd_put_32 (info->output_bfd,
+				    gottpoff (info, relocation_sym),
 				    sgot->contents + off + 4);
 			patch_tls_desc_to_ie (contents, rel, input_bfd);
 			BFD_ASSERT(0);
@@ -6184,8 +6190,9 @@ nds32_elf_relocate_section (bfd *		   output_bfd ATTRIBUTE_UNUSED,
    dynamic sections here.  */
 
 static bool
-nds32_elf_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
-				 struct elf_link_hash_entry *h, Elf_Internal_Sym *sym)
+nds32_elf_finish_dynamic_symbol (struct bfd_link_info *info,
+				 struct elf_link_hash_entry *h,
+				 Elf_Internal_Sym *sym)
 {
   struct elf_link_hash_table *ehtab;
   struct elf_nds32_link_hash_entry *hent;
@@ -6259,7 +6266,7 @@ nds32_elf_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
 	  long offset;
 
 	  offset = sgot->output_section->vma + sgot->output_offset + got_offset
-		   - elf_gp (output_bfd);
+		   - elf_gp (info->output_bfd);
 	  insn = PLT_PIC_ENTRY_WORD0 + ((offset >> 12) & 0xfffff);
 	  bfd_putb32 (insn, splt->contents + h->plt.offset);
 
@@ -6284,7 +6291,7 @@ nds32_elf_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
 
       /* Fill in the entry in the global offset table,
 	 so it will fall through to the next instruction for the first time.  */
-      bfd_put_32 (output_bfd,
+      bfd_put_32 (info->output_bfd,
 		  (splt->output_section->vma + splt->output_offset
 		   + h->plt.offset + local_plt_offset),
 		  sgot->contents + got_offset);
@@ -6296,7 +6303,7 @@ nds32_elf_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
       rela.r_addend = 0;
       loc = srela->contents;
       loc += plt_index * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
 
       if (!h->def_regular)
 	{
@@ -6342,14 +6349,14 @@ nds32_elf_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
 
 	  if ((h->got.offset & 1) == 0)
 	    {
-	      bfd_put_32 (output_bfd, rela.r_addend,
+	      bfd_put_32 (info->output_bfd, rela.r_addend,
 			  sgot->contents + h->got.offset);
 	    }
 	}
       else
 	{
 	  BFD_ASSERT ((h->got.offset & 1) == 0);
-	  bfd_put_32 (output_bfd, (bfd_vma) 0,
+	  bfd_put_32 (info->output_bfd, (bfd_vma) 0,
 		      sgot->contents + h->got.offset);
 	  rela.r_info = ELF32_R_INFO (h->dynindx, R_NDS32_GLOB_DAT);
 	  rela.r_addend = 0;
@@ -6357,7 +6364,7 @@ nds32_elf_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
 
       loc = srelagot->contents;
       loc += srelagot->reloc_count * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
       ++srelagot->reloc_count;
       BFD_ASSERT (loc < (srelagot->contents + srelagot->size));
     }
@@ -6383,7 +6390,7 @@ nds32_elf_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
       rela.r_addend = 0;
       loc = s->contents;
       loc += s->reloc_count * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
       ++s->reloc_count;
     }
 
@@ -6399,7 +6406,7 @@ nds32_elf_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
 /* Finish up the dynamic sections.  */
 
 static bool
-nds32_elf_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
+nds32_elf_finish_dynamic_sections (struct bfd_link_info *info,
 				   bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   bfd *dynobj;
@@ -6453,14 +6460,14 @@ nds32_elf_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
 	    get_vma:
 	      BFD_ASSERT (s != NULL);
 	      dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    case DT_PLTRELSZ:
 	      s = ehtab->srelplt;
 	      BFD_ASSERT (s != NULL);
 	      dyn.d_un.d_val = s->size;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    case DT_RELASZ:
@@ -6478,21 +6485,21 @@ nds32_elf_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
 		  s = ehtab->srelplt;
 		  dyn.d_un.d_val -= s->size;
 		}
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    case DT_TLSDESC_PLT:
 	      s = htab->root.splt;
 	      dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
 				+ htab->root.tlsdesc_plt);
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    case DT_TLSDESC_GOT:
 	      s = htab->root.sgot;
 	      dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
 				+ htab->root.tlsdesc_got);
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 	    }
 	}
@@ -6507,7 +6514,7 @@ nds32_elf_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
 	      long offset;
 
 	      offset = sgotplt->output_section->vma + sgotplt->output_offset + 4
-		- elf_gp (output_bfd);
+		- elf_gp (info->output_bfd);
 	      insn = PLT0_PIC_ENTRY_WORD0 | ((offset >> 12) & 0xfffff);
 	      bfd_putb32 (insn, splt->contents);
 
@@ -6564,8 +6571,8 @@ nds32_elf_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
 	    + htab->root.tlsdesc_got;
 
 	  /* Get GP offset.  */
-	  pltgot -= elf_gp (output_bfd) - 4; /* PLTGOT[1]  */
-	  tlsdesc_got -= elf_gp (output_bfd);
+	  pltgot -= elf_gp (info->output_bfd) - 4; /* PLTGOT[1]  */
+	  tlsdesc_got -= elf_gp (info->output_bfd);
 
 	  /* Do relocation.  */
 	  dl_tlsdesc_lazy_trampoline[0] += ((1 << 20) - 1) & (tlsdesc_got >> 12);
@@ -6584,13 +6591,13 @@ nds32_elf_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
   if (sgotplt && sgotplt->size > 0)
     {
       if (sdyn == NULL)
-	bfd_put_32 (output_bfd, (bfd_vma) 0, sgotplt->contents);
+	bfd_put_32 (info->output_bfd, 0, sgotplt->contents);
       else
-	bfd_put_32 (output_bfd,
+	bfd_put_32 (info->output_bfd,
 		    sdyn->output_section->vma + sdyn->output_offset,
 		    sgotplt->contents);
-      bfd_put_32 (output_bfd, (bfd_vma) 0, sgotplt->contents + 4);
-      bfd_put_32 (output_bfd, (bfd_vma) 0, sgotplt->contents + 8);
+      bfd_put_32 (info->output_bfd, 0, sgotplt->contents + 4);
+      bfd_put_32 (info->output_bfd, 0, sgotplt->contents + 8);
 
       elf_section_data (sgotplt->output_section)->this_hdr.sh_entsize = 4;
     }
@@ -12560,8 +12567,7 @@ nds32_elf_section_flags (const Elf_Internal_Shdr *hdr)
 }
 
 static bool
-nds32_elf_output_arch_syms (bfd *output_bfd ATTRIBUTE_UNUSED,
-			    struct bfd_link_info *info,
+nds32_elf_output_arch_syms (struct bfd_link_info *info,
 			    void *finfo ATTRIBUTE_UNUSED,
 			    int (*func) (void *, const char *,
 					 Elf_Internal_Sym *,
diff --git a/bfd/elf32-or1k.c b/bfd/elf32-or1k.c
index 56569435fb7..ab5b2f495f8 100644
--- a/bfd/elf32-or1k.c
+++ b/bfd/elf32-or1k.c
@@ -1291,8 +1291,7 @@ or1k_final_link_relocate (reloc_howto_type *howto, bfd *input_bfd,
    accordingly.  */
 
 static int
-or1k_elf_relocate_section (bfd *output_bfd,
-			   struct bfd_link_info *info,
+or1k_elf_relocate_section (struct bfd_link_info *info,
 			   bfd *input_bfd,
 			   asection *input_section,
 			   bfd_byte *contents,
@@ -1388,7 +1387,8 @@ or1k_elf_relocate_section (bfd *output_bfd,
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections[r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 
 	  name = bfd_elf_string_from_elf_section
 	    (input_bfd, symtab_hdr->sh_link, sym->st_name);
@@ -1474,7 +1474,7 @@ or1k_elf_relocate_section (bfd *output_bfd,
 		  else
 		    {
 		      /* Write entry in GOT.  */
-		      bfd_put_32 (output_bfd, relocation,
+		      bfd_put_32 (info->output_bfd, relocation,
 				  sgot->contents + off);
 		      /* Mark GOT entry as having been written.  */
 		      h->got.offset |= 1;
@@ -1499,7 +1499,8 @@ or1k_elf_relocate_section (bfd *output_bfd,
 	      else
 		{
 		  /* Write entry in GOT.  */
-		  bfd_put_32 (output_bfd, relocation, sgot->contents + off);
+		  bfd_put_32 (info->output_bfd, relocation,
+			      sgot->contents + off);
 		  if (bfd_link_pic (info))
 		    {
 		      asection *srelgot;
@@ -1516,7 +1517,7 @@ or1k_elf_relocate_section (bfd *output_bfd,
 		      loc = srelgot->contents;
 		      loc += (srelgot->reloc_count
 			      * sizeof (Elf32_External_Rela));
-		      bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+		      bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 		      ++srelgot->reloc_count;
 		    }
 		  local_got_offsets[r_symndx] |= 1;
@@ -1644,8 +1645,8 @@ or1k_elf_relocate_section (bfd *output_bfd,
 		skip = false;
 
 		outrel.r_offset =
-		  _bfd_elf_section_offset (output_bfd, info, input_section,
-					   rel->r_offset);
+		  _bfd_elf_section_offset (info->output_bfd, info,
+					   input_section, rel->r_offset);
 		if (outrel.r_offset == (bfd_vma) -1)
 		  skip = true;
 		else if (outrel.r_offset == (bfd_vma) -2)
@@ -1669,7 +1670,7 @@ or1k_elf_relocate_section (bfd *output_bfd,
 
 		loc = sreloc->contents;
 		loc += sreloc->reloc_count++ * sizeof (Elf32_External_Rela);
-		bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+		bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 		break;
 	      }
 	    break;
@@ -1794,15 +1795,16 @@ or1k_elf_relocate_section (bfd *output_bfd,
 		    loc += (srelgot->reloc_count++
 			    * sizeof (Elf32_External_Rela));
 
-		    bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
-		    bfd_put_32 (output_bfd, 0, sgot->contents + gotoff + i*4);
+		    bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
+		    bfd_put_32 (info->output_bfd, 0,
+				sgot->contents + gotoff + i*4);
 		  }
 	      }
 	    /* Static GD.  */
 	    else if ((tls_type & TLS_GD) != 0)
 	      {
-		bfd_put_32 (output_bfd, 1, sgot->contents + gotoff);
-		bfd_put_32 (output_bfd, tpoff (info, relocation, dynamic),
+		bfd_put_32 (info->output_bfd, 1, sgot->contents + gotoff);
+		bfd_put_32 (info->output_bfd, tpoff (info, relocation, dynamic),
 		    sgot->contents + gotoff + 4);
 	      }
 
@@ -1829,12 +1831,12 @@ or1k_elf_relocate_section (bfd *output_bfd,
 		loc = srelgot->contents;
 		loc += srelgot->reloc_count++ * sizeof (Elf32_External_Rela);
 
-		bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
-		bfd_put_32 (output_bfd, 0, sgot->contents + gotoff);
+		bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
+		bfd_put_32 (info->output_bfd, 0, sgot->contents + gotoff);
 	      }
 	    /* Static IE.  */
 	    else if ((tls_type & TLS_IE) != 0)
-	      bfd_put_32 (output_bfd, tpoff (info, relocation, dynamic),
+	      bfd_put_32 (info->output_bfd, tpoff (info, relocation, dynamic),
 			  sgot->contents + gotoff);
 
 	    /* The PG21 and LO13 relocs are pc-relative, while the
@@ -2319,8 +2321,7 @@ or1k_write_plt_entry (bfd *output_bfd, bfd_byte *contents, unsigned insnj,
 /* Finish up the dynamic sections.  */
 
 static bool
-or1k_elf_finish_dynamic_sections (bfd *output_bfd,
-				  struct bfd_link_info *info,
+or1k_elf_finish_dynamic_sections (struct bfd_link_info *info,
 				  bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   bfd *dynobj;
@@ -2373,7 +2374,7 @@ or1k_elf_finish_dynamic_sections (bfd *output_bfd,
 	      dyn.d_un.d_val = s->size;
 	      break;
 	    }
-	  bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	  bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	}
 
 
@@ -2412,7 +2413,7 @@ or1k_elf_finish_dynamic_sections (bfd *output_bfd,
 	      plt[2] = OR1K_LWZ(12,12) | (lo + 4);
 	    }
 
-	  or1k_write_plt_entry (output_bfd, splt->contents, OR1K_JR(15),
+	  or1k_write_plt_entry (info->output_bfd, splt->contents, OR1K_JR(15),
 				plt, plt_insn_count);
 
 	  elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
@@ -2424,9 +2425,9 @@ or1k_elf_finish_dynamic_sections (bfd *output_bfd,
   if (sgot && sgot->size > 0)
     {
       if (sdyn == NULL)
-	bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
+	bfd_put_32 (info->output_bfd, 0, sgot->contents);
       else
-	bfd_put_32 (output_bfd,
+	bfd_put_32 (info->output_bfd,
 		    sdyn->output_section->vma + sdyn->output_offset,
 		    sgot->contents);
       elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
@@ -2442,8 +2443,7 @@ or1k_elf_finish_dynamic_sections (bfd *output_bfd,
    dynamic sections here.  */
 
 static bool
-or1k_elf_finish_dynamic_symbol (bfd *output_bfd,
-				struct bfd_link_info *info,
+or1k_elf_finish_dynamic_symbol (struct bfd_link_info *info,
 				struct elf_link_hash_entry *h,
 				Elf_Internal_Sym *sym)
 {
@@ -2552,14 +2552,14 @@ or1k_elf_finish_dynamic_symbol (bfd *output_bfd,
 	  plt_insn_count = 5;
 	}
 
-      or1k_write_plt_entry (output_bfd, splt->contents + h->plt.offset,
+      or1k_write_plt_entry (info->output_bfd, splt->contents + h->plt.offset,
 			    OR1K_JR(12), plt, plt_insn_count);
 
       /* Fill in the entry in the global offset table.  We initialize it to
 	 point to the top of the plt.  This is done to lazy lookup the actual
 	 symbol as the first plt entry will be setup by libc to call the
 	 runtime dynamic linker.  */
-      bfd_put_32 (output_bfd, plt_base_addr, sgot->contents + got_offset);
+      bfd_put_32 (info->output_bfd, plt_base_addr, sgot->contents + got_offset);
 
       /* Fill in the entry in the .rela.plt section.  */
       rela.r_offset = got_addr;
@@ -2567,7 +2567,7 @@ or1k_elf_finish_dynamic_symbol (bfd *output_bfd,
       rela.r_addend = 0;
       loc = srela->contents;
       loc += plt_index * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
 
       if (!h->def_regular)
 	{
@@ -2609,14 +2609,14 @@ or1k_elf_finish_dynamic_symbol (bfd *output_bfd,
       else
 	{
 	  BFD_ASSERT ((h->got.offset & 1) == 0);
-	  bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + h->got.offset);
+	  bfd_put_32 (info->output_bfd, 0, sgot->contents + h->got.offset);
 	  rela.r_info = ELF32_R_INFO (h->dynindx, R_OR1K_GLOB_DAT);
 	  rela.r_addend = 0;
 	}
 
       loc = srelgot->contents;
       loc += srelgot->reloc_count * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
       ++srelgot->reloc_count;
     }
 
@@ -2640,7 +2640,7 @@ or1k_elf_finish_dynamic_symbol (bfd *output_bfd,
       else
 	s = htab->root.srelbss;
       loc = s->contents + s->reloc_count * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
       ++s->reloc_count;
     }
 
@@ -3045,8 +3045,7 @@ allocate_dynrelocs (struct elf_link_hash_entry *h, void * inf)
 /* Set the sizes of the dynamic sections.  */
 
 static bool
-or1k_elf_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-			     struct bfd_link_info *info)
+or1k_elf_late_size_sections (struct bfd_link_info *info)
 {
   struct elf_or1k_link_hash_table *htab;
   bfd *dynobj;
@@ -3212,7 +3211,7 @@ or1k_elf_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
       s->alloced = 1;
     }
 
-  return _bfd_elf_add_dynamic_tags (output_bfd, info, relocs);
+  return _bfd_elf_add_dynamic_tags (info, relocs);
 }
 
 /* Copy the extra info we tack onto an elf_link_hash_entry.  */
diff --git a/bfd/elf32-ppc.c b/bfd/elf32-ppc.c
index d4a3cd0e460..e3b54336da5 100644
--- a/bfd/elf32-ppc.c
+++ b/bfd/elf32-ppc.c
@@ -4291,7 +4291,7 @@ ppc_elf_inline_plt (struct bfd_link_info *info)
    generic ELF tls_setup function.  */
 
 asection *
-ppc_elf_tls_setup (bfd *obfd, struct bfd_link_info *info)
+ppc_elf_tls_setup (struct bfd_link_info *info)
 {
   struct ppc_elf_link_hash_table *htab;
 
@@ -4356,7 +4356,7 @@ ppc_elf_tls_setup (bfd *obfd, struct bfd_link_info *info)
       elf_section_flags (htab->elf.splt->output_section) = SHF_ALLOC + SHF_WRITE;
     }
 
-  return bfd_elf_tls_setup (obfd, info);
+  return bfd_elf_tls_setup (info);
 }
 
 /* Return TRUE iff REL is a branch reloc with a global symbol matching
@@ -5466,8 +5466,7 @@ static const unsigned char glink_eh_frame_cie[] =
 /* Set the sizes of the dynamic sections.  */
 
 static bool
-ppc_elf_late_size_sections (bfd *output_bfd,
-			    struct bfd_link_info *info)
+ppc_elf_late_size_sections (struct bfd_link_info *info)
 {
   struct ppc_elf_link_hash_table *htab;
   asection *s;
@@ -5884,8 +5883,7 @@ ppc_elf_late_size_sections (bfd *output_bfd,
 #define add_dynamic_entry(TAG, VAL) \
   _bfd_elf_add_dynamic_entry (info, TAG, VAL)
 
-      if (!_bfd_elf_maybe_vxworks_add_dynamic_tags (output_bfd, info,
-						    relocs))
+      if (!_bfd_elf_maybe_vxworks_add_dynamic_tags (info, relocs))
 	return false;
 
       if (htab->plt_type == PLT_NEW
@@ -6965,8 +6963,7 @@ count_and_swap_reloc_out (bfd *obfd, Elf_Internal_Rela *rel, asection *s)
    accordingly.  */
 
 static int
-ppc_elf_relocate_section (bfd *output_bfd,
-			  struct bfd_link_info *info,
+ppc_elf_relocate_section (struct bfd_link_info *info,
 			  bfd *input_bfd,
 			  asection *input_section,
 			  bfd_byte *contents,
@@ -7056,7 +7053,8 @@ ppc_elf_relocate_section (bfd *output_bfd,
 	  sec = local_sections[r_symndx];
 	  sym_name = bfd_elf_sym_name (input_bfd, symtab_hdr, sym, sec);
 
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 	}
       else
 	{
@@ -7823,9 +7821,8 @@ ppc_elf_relocate_section (bfd *output_bfd,
 			    outrel.r_info = ELF32_R_INFO (indx, R_PPC_DTPMOD32);
 			    if (tls_ty == (TLS_TLS | TLS_GD))
 			      {
-				BFD_ASSERT (count_and_swap_reloc_out (output_bfd,
-								      &outrel,
-								      rsec));
+				BFD_ASSERT (count_and_swap_reloc_out
+					    (info->output_bfd, &outrel, rsec));
 				outrel.r_offset += 4;
 				outrel.r_info
 				  = ELF32_R_INFO (indx, R_PPC_DTPREL32);
@@ -7852,7 +7849,7 @@ ppc_elf_relocate_section (bfd *output_bfd,
 				  outrel.r_addend -= htab->elf.tls_sec->vma;
 			      }
 			  }
-			BFD_ASSERT (count_and_swap_reloc_out (output_bfd,
+			BFD_ASSERT (count_and_swap_reloc_out (info->output_bfd,
 							      &outrel, rsec));
 		      }
 
@@ -8097,7 +8094,7 @@ ppc_elf_relocate_section (bfd *output_bfd,
 		 are copied into the output file to be resolved at run
 		 time.  */
 	      skip = 0;
-	      outrel.r_offset = _bfd_elf_section_offset (output_bfd, info,
+	      outrel.r_offset = _bfd_elf_section_offset (info->output_bfd, info,
 							 input_section,
 							 rel->r_offset);
 	      if (outrel.r_offset == (bfd_vma) -1
@@ -8214,7 +8211,7 @@ ppc_elf_relocate_section (bfd *output_bfd,
 	      if (sreloc == NULL)
 		return false;
 
-	      BFD_ASSERT (count_and_swap_reloc_out (output_bfd, &outrel,
+	      BFD_ASSERT (count_and_swap_reloc_out (info->output_bfd, &outrel,
 						    sreloc));
 
 	      if (skip == -1)
@@ -8795,7 +8792,7 @@ ppc_elf_relocate_section (bfd *output_bfd,
 	    r = bfd_reloc_outofrange;
 	  else
 	    {
-	      ppc_elf_vle_split20 (output_bfd, contents + rel->r_offset,
+	      ppc_elf_vle_split20 (info->output_bfd, contents + rel->r_offset,
 				   relocation);
 	      r = bfd_reloc_ok;
 	    }
@@ -9023,7 +9020,7 @@ ppc_elf_relocate_section (bfd *output_bfd,
       if (unresolved_reloc
 	  && !((input_section->flags & SEC_DEBUGGING) != 0
 	       && h->def_dynamic)
-	  && _bfd_elf_section_offset (output_bfd, info, input_section,
+	  && _bfd_elf_section_offset (info->output_bfd, info, input_section,
 				      rel->r_offset) != (bfd_vma) -1)
 	{
 	  info->callbacks->einfo
@@ -9331,8 +9328,8 @@ ppc_elf_relocate_section (bfd *output_bfd,
 		  while (slo < shi)
 		    {
 		      Elf32_External_Rela *srel = slo + (shi - slo) / 2;
-		      bfd_elf32_swap_reloca_in (output_bfd, (bfd_byte *) srel,
-						&outrel);
+		      bfd_elf32_swap_reloca_in (info->output_bfd,
+						(bfd_byte *) srel, &outrel);
 		      if (outrel.r_offset < soffset)
 			slo = srel + 1;
 		      else if (outrel.r_offset > soffset + 3)
@@ -9346,7 +9343,7 @@ ppc_elf_relocate_section (bfd *output_bfd,
 			      srel = srelend - 1;
 			    }
 			  outrel.r_offset += patch_off - offset;
-			  bfd_elf32_swap_reloca_out (output_bfd, &outrel,
+			  bfd_elf32_swap_reloca_out (info->output_bfd, &outrel,
 						     (bfd_byte *) srel);
 			  break;
 			}
@@ -9804,8 +9801,7 @@ ppc_finish_symbols (struct bfd_link_info *info)
    dynamic sections here.  */
 
 static bool
-ppc_elf_finish_dynamic_symbol (bfd *output_bfd,
-			       struct bfd_link_info *info,
+ppc_elf_finish_dynamic_symbol (struct bfd_link_info *info,
 			       struct elf_link_hash_entry *h,
 			       Elf_Internal_Sym *sym)
 {
@@ -9885,7 +9881,7 @@ ppc_elf_finish_dynamic_symbol (bfd *output_bfd,
       rela.r_offset = SYM_VAL (h);
       rela.r_info = ELF32_R_INFO (h->dynindx, R_PPC_COPY);
       rela.r_addend = 0;
-      BFD_ASSERT (count_and_swap_reloc_out (output_bfd, &rela, s));
+      BFD_ASSERT (count_and_swap_reloc_out (info->output_bfd, &rela, s));
     }
 
 #ifdef DEBUG
@@ -9921,8 +9917,7 @@ ppc_elf_reloc_type_class (const struct bfd_link_info *info,
 /* Finish up the dynamic sections.  */
 
 static bool
-ppc_elf_finish_dynamic_sections (bfd *output_bfd,
-				 struct bfd_link_info *info,
+ppc_elf_finish_dynamic_sections (struct bfd_link_info *info,
 				 bfd_byte *buf)
 {
   asection *sdyn;
@@ -9995,13 +9990,13 @@ ppc_elf_finish_dynamic_sections (bfd *output_bfd,
 	    default:
 #ifdef OBJ_MAYBE_ELF_VXWORKS
 	      if (htab->elf.target_os == is_vxworks
-		  && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
+		  && elf_vxworks_finish_dynamic_entry (info->output_bfd, &dyn))
 		break;
 #endif /* OBJ_MAYBE_ELF_VXWORKS */
 	      continue;
 	    }
 
-	  bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	  bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	}
     }
 
@@ -10021,7 +10016,7 @@ ppc_elf_finish_dynamic_sections (bfd *output_bfd,
 		 _GLOBAL_OFFSET_TABLE_.  */
 	      BFD_ASSERT (htab->elf.hgot->root.u.def.value - 4
 			  < htab->elf.hgot->root.u.def.section->size);
-	      bfd_put_32 (output_bfd, 0x4e800021, p - 4);
+	      bfd_put_32 (info->output_bfd, 0x4e800021, p - 4);
 	    }
 
 	  if (sdyn != NULL)
@@ -10029,7 +10024,7 @@ ppc_elf_finish_dynamic_sections (bfd *output_bfd,
 	      bfd_vma val = sdyn->output_section->vma + sdyn->output_offset;
 	      BFD_ASSERT (htab->elf.hgot->root.u.def.value
 			  < htab->elf.hgot->root.u.def.section->size);
-	      bfd_put_32 (output_bfd, val, p);
+	      bfd_put_32 (info->output_bfd, val, p);
 	    }
 	}
       else
@@ -10062,22 +10057,22 @@ ppc_elf_finish_dynamic_sections (bfd *output_bfd,
 	{
 	  bfd_vma got_value = SYM_VAL (htab->elf.hgot);
 
-	  bfd_put_32 (output_bfd, plt_entry[0] | PPC_HA (got_value),
+	  bfd_put_32 (info->output_bfd, plt_entry[0] | PPC_HA (got_value),
 		      splt->contents +  0);
-	  bfd_put_32 (output_bfd, plt_entry[1] | PPC_LO (got_value),
+	  bfd_put_32 (info->output_bfd, plt_entry[1] | PPC_LO (got_value),
 		      splt->contents +  4);
 	}
       else
 	{
-	  bfd_put_32 (output_bfd, plt_entry[0], splt->contents +  0);
-	  bfd_put_32 (output_bfd, plt_entry[1], splt->contents +  4);
+	  bfd_put_32 (info->output_bfd, plt_entry[0], splt->contents +  0);
+	  bfd_put_32 (info->output_bfd, plt_entry[1], splt->contents +  4);
 	}
-      bfd_put_32 (output_bfd, plt_entry[2], splt->contents +  8);
-      bfd_put_32 (output_bfd, plt_entry[3], splt->contents + 12);
-      bfd_put_32 (output_bfd, plt_entry[4], splt->contents + 16);
-      bfd_put_32 (output_bfd, plt_entry[5], splt->contents + 20);
-      bfd_put_32 (output_bfd, plt_entry[6], splt->contents + 24);
-      bfd_put_32 (output_bfd, plt_entry[7], splt->contents + 28);
+      bfd_put_32 (info->output_bfd, plt_entry[2], splt->contents +  8);
+      bfd_put_32 (info->output_bfd, plt_entry[3], splt->contents + 12);
+      bfd_put_32 (info->output_bfd, plt_entry[4], splt->contents + 16);
+      bfd_put_32 (info->output_bfd, plt_entry[5], splt->contents + 20);
+      bfd_put_32 (info->output_bfd, plt_entry[6], splt->contents + 24);
+      bfd_put_32 (info->output_bfd, plt_entry[7], splt->contents + 28);
 
       if (! bfd_link_pic (info))
 	{
@@ -10092,7 +10087,8 @@ ppc_elf_finish_dynamic_sections (bfd *output_bfd,
 			   + 2);
 	  rela.r_info = ELF32_R_INFO (htab->elf.hgot->indx, R_PPC_ADDR16_HA);
 	  rela.r_addend = 0;
-	  BFD_ASSERT (swap_reloc_out (output_bfd, &rela, loc, htab->srelplt2));
+	  BFD_ASSERT (swap_reloc_out (info->output_bfd, &rela, loc,
+				      htab->srelplt2));
 	  loc += sizeof (Elf32_External_Rela);
 
 	  /* Output the @l relocation for the second instruction.  */
@@ -10101,7 +10097,8 @@ ppc_elf_finish_dynamic_sections (bfd *output_bfd,
 			   + 6);
 	  rela.r_info = ELF32_R_INFO (htab->elf.hgot->indx, R_PPC_ADDR16_LO);
 	  rela.r_addend = 0;
-	  BFD_ASSERT (swap_reloc_out (output_bfd, &rela, loc, htab->srelplt2));
+	  BFD_ASSERT (swap_reloc_out (info->output_bfd, &rela, loc,
+				      htab->srelplt2));
 	  loc += sizeof (Elf32_External_Rela);
 
 	  /* Fix up the remaining relocations.  They may have the wrong
@@ -10111,19 +10108,19 @@ ppc_elf_finish_dynamic_sections (bfd *output_bfd,
 	    {
 	      Elf_Internal_Rela rel;
 
-	      bfd_elf32_swap_reloc_in (output_bfd, loc, &rel);
+	      bfd_elf32_swap_reloc_in (info->output_bfd, loc, &rel);
 	      rel.r_info = ELF32_R_INFO (htab->elf.hgot->indx, R_PPC_ADDR16_HA);
-	      bfd_elf32_swap_reloc_out (output_bfd, &rel, loc);
+	      bfd_elf32_swap_reloc_out (info->output_bfd, &rel, loc);
 	      loc += sizeof (Elf32_External_Rela);
 
-	      bfd_elf32_swap_reloc_in (output_bfd, loc, &rel);
+	      bfd_elf32_swap_reloc_in (info->output_bfd, loc, &rel);
 	      rel.r_info = ELF32_R_INFO (htab->elf.hgot->indx, R_PPC_ADDR16_LO);
-	      bfd_elf32_swap_reloc_out (output_bfd, &rel, loc);
+	      bfd_elf32_swap_reloc_out (info->output_bfd, &rel, loc);
 	      loc += sizeof (Elf32_External_Rela);
 
-	      bfd_elf32_swap_reloc_in (output_bfd, loc, &rel);
+	      bfd_elf32_swap_reloc_in (info->output_bfd, loc, &rel);
 	      rel.r_info = ELF32_R_INFO (htab->elf.hplt->indx, R_PPC_ADDR32);
-	      bfd_elf32_swap_reloc_out (output_bfd, &rel, loc);
+	      bfd_elf32_swap_reloc_out (info->output_bfd, &rel, loc);
 	      loc += sizeof (Elf32_External_Rela);
 	    }
 	}
@@ -10203,12 +10200,12 @@ ppc_elf_finish_dynamic_sections (bfd *output_bfd,
       endp += htab->glink->size - GLINK_PLTRESOLVE;
       while (p < endp - (htab->params->ppc476_workaround ? 0 : 8 * 4))
 	{
-	  bfd_put_32 (output_bfd, B + endp - p, p);
+	  bfd_put_32 (info->output_bfd, B + endp - p, p);
 	  p += 4;
 	}
       while (p < endp)
 	{
-	  bfd_put_32 (output_bfd, NOP, p);
+	  bfd_put_32 (info->output_bfd, NOP, p);
 	  p += 4;
 	}
 
@@ -10235,16 +10232,16 @@ ppc_elf_finish_dynamic_sections (bfd *output_bfd,
 	      unsigned int insn;
 
 	      loc = htab->glink->contents + page_addr - 4 - glink_start;
-	      insn = bfd_get_32 (output_bfd, loc);
+	      insn = bfd_get_32 (info->output_bfd, loc);
 	      if (insn == BCTR)
 		{
 		  /* By alignment, we know that there must be at least
 		     one other call stub before this one.  */
-		  insn = bfd_get_32 (output_bfd, loc - 16);
+		  insn = bfd_get_32 (info->output_bfd, loc - 16);
 		  if (insn == BCTR)
-		    bfd_put_32 (output_bfd, B | (-16 & 0x3fffffc), loc);
+		    bfd_put_32 (info->output_bfd, B | (-16 & 0x3fffffc), loc);
 		  else
-		    bfd_put_32 (output_bfd, B | (-20 & 0x3fffffc), loc);
+		    bfd_put_32 (info->output_bfd, B | (-20 & 0x3fffffc), loc);
 		}
 	    }
 	}
@@ -10259,70 +10256,73 @@ ppc_elf_finish_dynamic_sections (bfd *output_bfd,
 		 + htab->glink->output_section->vma
 		 + htab->glink->output_offset);
 
-	  bfd_put_32 (output_bfd, ADDIS_11_11 + PPC_HA (bcl - res0), p);
+	  bfd_put_32 (info->output_bfd, ADDIS_11_11 + PPC_HA (bcl - res0), p);
 	  p += 4;
-	  bfd_put_32 (output_bfd, MFLR_0, p);
+	  bfd_put_32 (info->output_bfd, MFLR_0, p);
 	  p += 4;
-	  bfd_put_32 (output_bfd, BCL_20_31, p);
+	  bfd_put_32 (info->output_bfd, BCL_20_31, p);
 	  p += 4;
-	  bfd_put_32 (output_bfd, ADDI_11_11 + PPC_LO (bcl - res0), p);
+	  bfd_put_32 (info->output_bfd, ADDI_11_11 + PPC_LO (bcl - res0), p);
 	  p += 4;
-	  bfd_put_32 (output_bfd, MFLR_12, p);
+	  bfd_put_32 (info->output_bfd, MFLR_12, p);
 	  p += 4;
-	  bfd_put_32 (output_bfd, MTLR_0, p);
+	  bfd_put_32 (info->output_bfd, MTLR_0, p);
 	  p += 4;
-	  bfd_put_32 (output_bfd, SUB_11_11_12, p);
+	  bfd_put_32 (info->output_bfd, SUB_11_11_12, p);
 	  p += 4;
-	  bfd_put_32 (output_bfd, ADDIS_12_12 + PPC_HA (got + 4 - bcl), p);
+	  bfd_put_32 (info->output_bfd, ADDIS_12_12 + PPC_HA (got + 4 - bcl), p);
 	  p += 4;
 	  if (PPC_HA (got + 4 - bcl) == PPC_HA (got + 8 - bcl))
 	    {
-	      bfd_put_32 (output_bfd, LWZ_0_12 + PPC_LO (got + 4 - bcl), p);
+	      bfd_put_32 (info->output_bfd,
+			  LWZ_0_12 + PPC_LO (got + 4 - bcl), p);
 	      p += 4;
-	      bfd_put_32 (output_bfd, LWZ_12_12 + PPC_LO (got + 8 - bcl), p);
+	      bfd_put_32 (info->output_bfd,
+			  LWZ_12_12 + PPC_LO (got + 8 - bcl), p);
 	      p += 4;
 	    }
 	  else
 	    {
-	      bfd_put_32 (output_bfd, LWZU_0_12 + PPC_LO (got + 4 - bcl), p);
+	      bfd_put_32 (info->output_bfd,
+			  LWZU_0_12 + PPC_LO (got + 4 - bcl), p);
 	      p += 4;
-	      bfd_put_32 (output_bfd, LWZ_12_12 + 4, p);
+	      bfd_put_32 (info->output_bfd, LWZ_12_12 + 4, p);
 	      p += 4;
 	    }
-	  bfd_put_32 (output_bfd, MTCTR_0, p);
+	  bfd_put_32 (info->output_bfd, MTCTR_0, p);
 	  p += 4;
-	  bfd_put_32 (output_bfd, ADD_0_11_11, p);
+	  bfd_put_32 (info->output_bfd, ADD_0_11_11, p);
 	}
       else
 	{
-	  bfd_put_32 (output_bfd, LIS_12 + PPC_HA (got + 4), p);
+	  bfd_put_32 (info->output_bfd, LIS_12 + PPC_HA (got + 4), p);
 	  p += 4;
-	  bfd_put_32 (output_bfd, ADDIS_11_11 + PPC_HA (-res0), p);
+	  bfd_put_32 (info->output_bfd, ADDIS_11_11 + PPC_HA (-res0), p);
 	  p += 4;
 	  if (PPC_HA (got + 4) == PPC_HA (got + 8))
-	    bfd_put_32 (output_bfd, LWZ_0_12 + PPC_LO (got + 4), p);
+	    bfd_put_32 (info->output_bfd, LWZ_0_12 + PPC_LO (got + 4), p);
 	  else
-	    bfd_put_32 (output_bfd, LWZU_0_12 + PPC_LO (got + 4), p);
+	    bfd_put_32 (info->output_bfd, LWZU_0_12 + PPC_LO (got + 4), p);
 	  p += 4;
-	  bfd_put_32 (output_bfd, ADDI_11_11 + PPC_LO (-res0), p);
+	  bfd_put_32 (info->output_bfd, ADDI_11_11 + PPC_LO (-res0), p);
 	  p += 4;
-	  bfd_put_32 (output_bfd, MTCTR_0, p);
+	  bfd_put_32 (info->output_bfd, MTCTR_0, p);
 	  p += 4;
-	  bfd_put_32 (output_bfd, ADD_0_11_11, p);
+	  bfd_put_32 (info->output_bfd, ADD_0_11_11, p);
 	  p += 4;
 	  if (PPC_HA (got + 4) == PPC_HA (got + 8))
-	    bfd_put_32 (output_bfd, LWZ_12_12 + PPC_LO (got + 8), p);
+	    bfd_put_32 (info->output_bfd, LWZ_12_12 + PPC_LO (got + 8), p);
 	  else
-	    bfd_put_32 (output_bfd, LWZ_12_12 + 4, p);
+	    bfd_put_32 (info->output_bfd, LWZ_12_12 + 4, p);
 	}
       p += 4;
-      bfd_put_32 (output_bfd, ADD_11_0_11, p);
+      bfd_put_32 (info->output_bfd, ADD_11_0_11, p);
       p += 4;
-      bfd_put_32 (output_bfd, BCTR, p);
+      bfd_put_32 (info->output_bfd, BCTR, p);
       p += 4;
       while (p < endp)
 	{
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 		      htab->params->ppc476_workaround ? BA : NOP, p);
 	  p += 4;
 	}
@@ -10349,7 +10349,7 @@ ppc_elf_finish_dynamic_sections (bfd *output_bfd,
       bfd_put_32 (htab->elf.dynobj, val, p);
 
       if (htab->glink_eh_frame->sec_info_type == SEC_INFO_TYPE_EH_FRAME
-	  && !_bfd_elf_write_linker_section_eh_frame (output_bfd, info,
+	  && !_bfd_elf_write_linker_section_eh_frame (info->output_bfd, info,
 						      htab->glink_eh_frame,
 						      buf))
 	return false;
diff --git a/bfd/elf32-ppc.h b/bfd/elf32-ppc.h
index 55b74695efe..b175cfd502e 100644
--- a/bfd/elf32-ppc.h
+++ b/bfd/elf32-ppc.h
@@ -61,7 +61,7 @@ struct ppc_elf_params
 void ppc_elf_link_params (struct bfd_link_info *, struct ppc_elf_params *);
 int ppc_elf_select_plt_layout (bfd *, struct bfd_link_info *);
 bool ppc_elf_inline_plt (struct bfd_link_info *);
-asection *ppc_elf_tls_setup (bfd *, struct bfd_link_info *);
+asection *ppc_elf_tls_setup (struct bfd_link_info *);
 bool ppc_elf_tls_optimize (bfd *, struct bfd_link_info *);
 void ppc_elf_maybe_strip_sdata_syms (struct bfd_link_info *);
 extern bool ppc_elf_modify_segment_map (bfd *, struct bfd_link_info *)
diff --git a/bfd/elf32-pru.c b/bfd/elf32-pru.c
index 626f7948975..6e699004d04 100644
--- a/bfd/elf32-pru.c
+++ b/bfd/elf32-pru.c
@@ -681,8 +681,7 @@ pru_elf32_ldi32_relocate (bfd *abfd, arelent *reloc_entry, asymbol *symbol,
 
 /* Implement elf_backend_relocate_section.  */
 static int
-pru_elf32_relocate_section (bfd *output_bfd,
-			    struct bfd_link_info *info,
+pru_elf32_relocate_section (struct bfd_link_info *info,
 			    bfd *input_bfd,
 			    asection *input_section,
 			    bfd_byte *contents,
@@ -736,7 +735,8 @@ pru_elf32_relocate_section (bfd *output_bfd,
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections[r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 	}
       else
 	{
diff --git a/bfd/elf32-rl78.c b/bfd/elf32-rl78.c
index 2c83214a912..2b782c1463a 100644
--- a/bfd/elf32-rl78.c
+++ b/bfd/elf32-rl78.c
@@ -702,8 +702,7 @@ rl78_special_reloc (bfd *      input_bfd,
 
 static int
 rl78_elf_relocate_section
-    (bfd *		     output_bfd,
-     struct bfd_link_info *  info,
+    (struct bfd_link_info *  info,
      bfd *		     input_bfd,
      asection *		     input_section,
      bfd_byte *		     contents,
@@ -751,7 +750,8 @@ rl78_elf_relocate_section
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections [r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, & sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 
 	  name = bfd_elf_string_from_elf_section
 	    (input_bfd, symtab_hdr->sh_link, sym->st_name);
@@ -1408,8 +1408,7 @@ rl78_elf_check_relocs
 /* This must exist if dynobj is ever set.  */
 
 static bool
-rl78_elf_finish_dynamic_sections (bfd *abfd ATTRIBUTE_UNUSED,
-				  struct bfd_link_info *info,
+rl78_elf_finish_dynamic_sections (struct bfd_link_info *info,
 				  bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   bfd *dynobj;
@@ -1445,8 +1444,7 @@ rl78_elf_finish_dynamic_sections (bfd *abfd ATTRIBUTE_UNUSED,
 }
 
 static bool
-rl78_elf_early_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-			      struct bfd_link_info *info)
+rl78_elf_early_size_sections (struct bfd_link_info *info)
 {
   bfd *dynobj;
   asection *splt;
diff --git a/bfd/elf32-rx.c b/bfd/elf32-rx.c
index 3f26d7684f9..1421e443e51 100644
--- a/bfd/elf32-rx.c
+++ b/bfd/elf32-rx.c
@@ -494,8 +494,7 @@ static unsigned int rx_stack_top;
 
 static int
 rx_elf_relocate_section
-    (bfd *		     output_bfd,
-     struct bfd_link_info *  info,
+    (struct bfd_link_info *  info,
      bfd *		     input_bfd,
      asection *		     input_section,
      bfd_byte *		     contents,
@@ -513,7 +512,7 @@ rx_elf_relocate_section
   bfd_vma table_start_cache = 0;
   bfd_vma table_end_cache = 0;
 
-  if (elf_elfheader (output_bfd)->e_flags & E_FLAG_RX_PID)
+  if (elf_elfheader (info->output_bfd)->e_flags & E_FLAG_RX_PID)
     pid_mode = true;
   else
     pid_mode = false;
@@ -550,7 +549,8 @@ rx_elf_relocate_section
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections [r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, & sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 
 	  name = bfd_elf_string_from_elf_section
 	    (input_bfd, symtab_hdr->sh_link, sym->st_name);
@@ -796,7 +796,7 @@ rx_elf_relocate_section
 	case R_RX_DIR16S:
 	  UNSAFE_FOR_PID;
 	  RANGE (-32768, 65535);
-	  if (BIGE (output_bfd) && !(input_section->flags & SEC_CODE))
+	  if (BIGE (info->output_bfd) && !(input_section->flags & SEC_CODE))
 	    {
 	      OP (1) = relocation;
 	      OP (0) = relocation >> 8;
@@ -886,7 +886,7 @@ rx_elf_relocate_section
 	case R_RX_DIR24S:
 	  UNSAFE_FOR_PID;
 	  RANGE (-0x800000, 0x7fffff);
-	  if (BIGE (output_bfd) && !(input_section->flags & SEC_CODE))
+	  if (BIGE (info->output_bfd) && !(input_section->flags & SEC_CODE))
 	    {
 	      OP (2) = relocation;
 	      OP (1) = relocation >> 8;
@@ -949,7 +949,7 @@ rx_elf_relocate_section
 	  break;
 
 	case R_RX_DIR32:
-	  if (BIGE (output_bfd) && !(input_section->flags & SEC_CODE))
+	  if (BIGE (info->output_bfd) && !(input_section->flags & SEC_CODE))
 	    {
 	      OP (3) = relocation;
 	      OP (2) = relocation >> 8;
@@ -966,7 +966,7 @@ rx_elf_relocate_section
 	  break;
 
 	case R_RX_DIR32_REV:
-	  if (BIGE (output_bfd))
+	  if (BIGE (info->output_bfd))
 	    {
 	      OP (0) = relocation;
 	      OP (1) = relocation >> 8;
@@ -986,9 +986,9 @@ rx_elf_relocate_section
 	  {
 	    bfd_vma val;
 	    WARN_REDHAT ("RX_RH_DIFF");
-	    val = bfd_get_32 (output_bfd, & OP (0));
+	    val = bfd_get_32 (info->output_bfd, & OP (0));
 	    val -= relocation;
-	    bfd_put_32 (output_bfd, val, & OP (0));
+	    bfd_put_32 (info->output_bfd, val, & OP (0));
 	  }
 	  break;
 
@@ -1149,7 +1149,7 @@ rx_elf_relocate_section
 	  UNSAFE_FOR_PID;
 	  RX_STACK_POP (relocation);
 	  RANGE (-0x800000, 0x7fffff);
-	  if (BIGE (output_bfd) && !(input_section->flags & SEC_CODE))
+	  if (BIGE (info->output_bfd) && !(input_section->flags & SEC_CODE))
 	    {
 	      OP (2) = relocation;
 	      OP (1) = relocation >> 8;
@@ -1193,7 +1193,7 @@ rx_elf_relocate_section
 	case R_RX_ABS16S:
 	  RX_STACK_POP (relocation);
 	  RANGE (-32768, 32767);
-	  if (BIGE (output_bfd) && !(input_section->flags & SEC_CODE))
+	  if (BIGE (info->output_bfd) && !(input_section->flags & SEC_CODE))
 	    {
 	      OP (1) = relocation;
 	      OP (0) = relocation >> 8;
diff --git a/bfd/elf32-s390.c b/bfd/elf32-s390.c
index 8fec2f7d43f..fb00971c7b6 100644
--- a/bfd/elf32-s390.c
+++ b/bfd/elf32-s390.c
@@ -1773,8 +1773,7 @@ allocate_dynrelocs (struct elf_link_hash_entry *h, void * inf)
 /* Set the sizes of the dynamic sections.  */
 
 static bool
-elf_s390_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-			     struct bfd_link_info *info)
+elf_s390_late_size_sections (struct bfd_link_info *info)
 {
   struct elf_s390_link_hash_table *htab;
   bfd *dynobj;
@@ -1960,7 +1959,7 @@ elf_s390_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
       s->alloced = 1;
     }
 
-  return _bfd_elf_add_dynamic_tags (output_bfd, info, relocs);
+  return _bfd_elf_add_dynamic_tags (info, relocs);
 }
 
 /* Return the base VMA address which should be subtracted from real addresses
@@ -2014,8 +2013,7 @@ invalid_tls_insn (bfd *input_bfd,
 /* Relocate a 390 ELF section.  */
 
 static int
-elf_s390_relocate_section (bfd *output_bfd,
-			   struct bfd_link_info *info,
+elf_s390_relocate_section (struct bfd_link_info *info,
 			   bfd *input_bfd,
 			   asection *input_section,
 			   bfd_byte *contents,
@@ -2110,7 +2108,7 @@ elf_s390_relocate_section (bfd *output_bfd,
 		case R_390_GOTENT:
 		  {
 		    /* Write the PLT slot address into the GOT slot.  */
-		    bfd_put_32 (output_bfd, relocation,
+		    bfd_put_32 (info->output_bfd, relocation,
 				htab->elf.sgot->contents +
 				local_got_offsets[r_symndx]);
 		    relocation = (local_got_offsets[r_symndx] +
@@ -2130,7 +2128,8 @@ elf_s390_relocate_section (bfd *output_bfd,
 	      goto do_relocation;
 	    }
 	  else
-	    relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	    relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						  sym, &sec, rel);
 	}
       else
 	{
@@ -2261,7 +2260,7 @@ elf_s390_relocate_section (bfd *output_bfd,
 		    off &= ~1;
 		  else
 		    {
-		      bfd_put_32 (output_bfd, relocation,
+		      bfd_put_32 (info->output_bfd, relocation,
 				  base_got->contents + off);
 		      h->got.offset |= 1;
 		    }
@@ -2285,7 +2284,7 @@ elf_s390_relocate_section (bfd *output_bfd,
 		      unsigned short new_insn =
 			(0xc000 | (bfd_get_8 (input_bfd,
 					      contents + rel->r_offset - 1) & 0xf0));
-		      bfd_put_16 (output_bfd, new_insn,
+		      bfd_put_16 (info->output_bfd, new_insn,
 				  contents + rel->r_offset - 2);
 		      r_type = R_390_PC32DBL;
 		      rel->r_info = ELF32_R_INFO (r_symndx, r_type);
@@ -2314,7 +2313,7 @@ elf_s390_relocate_section (bfd *output_bfd,
 		off &= ~1;
 	      else
 		{
-		  bfd_put_32 (output_bfd, relocation,
+		  bfd_put_32 (info->output_bfd, relocation,
 			      htab->elf.sgot->contents + off);
 
 		  if (bfd_link_pic (info))
@@ -2334,7 +2333,7 @@ elf_s390_relocate_section (bfd *output_bfd,
 		      outrel.r_addend = relocation;
 		      loc = srelgot->contents;
 		      loc += srelgot->reloc_count++ * sizeof (Elf32_External_Rela);
-		      bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+		      bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 		    }
 
 		  local_got_offsets[r_symndx] |= 1;
@@ -2504,7 +2503,7 @@ elf_s390_relocate_section (bfd *output_bfd,
 
 		  /* Need a dynamic relocation to get the real function
 		     address.  */
-		  outrel.r_offset = _bfd_elf_section_offset (output_bfd,
+		  outrel.r_offset = _bfd_elf_section_offset (info->output_bfd,
 							     info,
 							     input_section,
 							     rel->r_offset);
@@ -2532,7 +2531,7 @@ elf_s390_relocate_section (bfd *output_bfd,
 		    }
 
 		  sreloc = htab->elf.irelifunc;
-		  _bfd_elf_append_rela (output_bfd, sreloc, &outrel);
+		  _bfd_elf_append_rela (info->output_bfd, sreloc, &outrel);
 
 		  /* If this reloc is against an external symbol, we
 		     do not want to fiddle with the addend.  Otherwise,
@@ -2578,8 +2577,8 @@ elf_s390_relocate_section (bfd *output_bfd,
 	      relocate = false;
 
 	      outrel.r_offset =
-		_bfd_elf_section_offset (output_bfd, info, input_section,
-					 rel->r_offset);
+		_bfd_elf_section_offset (info->output_bfd, info,
+					 input_section, rel->r_offset);
 	      if (outrel.r_offset == (bfd_vma) -1)
 		skip = true;
 	      else if (outrel.r_offset == (bfd_vma) -2)
@@ -2654,7 +2653,7 @@ elf_s390_relocate_section (bfd *output_bfd,
 
 	      loc = sreloc->contents;
 	      loc += sreloc->reloc_count++ * sizeof (Elf32_External_Rela);
-	      bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+	      bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 
 	      /* If this reloc is against an external symbol, we do
 		 not want to fiddle with the addend.  Otherwise, we
@@ -2682,7 +2681,7 @@ elf_s390_relocate_section (bfd *output_bfd,
 		abort ();
 	      loc = sreloc->contents;
 	      loc += sreloc->reloc_count++ * sizeof (Elf32_External_Rela);
-	      bfd_elf32_swap_reloc_out (output_bfd, &outrel, loc);
+	      bfd_elf32_swap_reloc_out (info->output_bfd, &outrel, loc);
 	    }
 	  /* Fall through.  */
 
@@ -2708,7 +2707,8 @@ elf_s390_relocate_section (bfd *output_bfd,
 	      /* This relocation gets optimized away by the local exec
 		 access optimization.  */
 	      BFD_ASSERT (! unresolved_reloc);
-	      bfd_put_32 (output_bfd, -tpoff (info, relocation) + rel->r_addend,
+	      bfd_put_32 (info->output_bfd,
+			  -tpoff (info, relocation) + rel->r_addend,
 			  contents + rel->r_offset);
 	      continue;
 	    }
@@ -2755,14 +2755,14 @@ elf_s390_relocate_section (bfd *output_bfd,
 	      loc = htab->elf.srelgot->contents;
 	      loc += htab->elf.srelgot->reloc_count++
 		* sizeof (Elf32_External_Rela);
-	      bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+	      bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 
 	      if (r_type == R_390_TLS_GD32)
 		{
 		  if (indx == 0)
 		    {
 		      BFD_ASSERT (! unresolved_reloc);
-		      bfd_put_32 (output_bfd,
+		      bfd_put_32 (info->output_bfd,
 				  relocation - dtpoff_base (info),
 				  htab->elf.sgot->contents + off + GOT_ENTRY_SIZE);
 		    }
@@ -2773,7 +2773,8 @@ elf_s390_relocate_section (bfd *output_bfd,
 		      outrel.r_addend = 0;
 		      htab->elf.srelgot->reloc_count++;
 		      loc += sizeof (Elf32_External_Rela);
-		      bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+		      bfd_elf32_swap_reloca_out (info->output_bfd,
+						 &outrel, loc);
 		    }
 		}
 
@@ -2794,7 +2795,8 @@ elf_s390_relocate_section (bfd *output_bfd,
 	    }
 	  else
 	    {
-	      bfd_put_32 (output_bfd, htab->elf.sgot->output_offset + off,
+	      bfd_put_32 (info->output_bfd,
+			  htab->elf.sgot->output_offset + off,
 			  contents + rel->r_offset);
 	      continue;
 	    }
@@ -2825,7 +2827,7 @@ elf_s390_relocate_section (bfd *output_bfd,
 	    abort ();
 
 	  BFD_ASSERT (! unresolved_reloc);
-	  bfd_put_32 (output_bfd, -tpoff (info, relocation),
+	  bfd_put_32 (info->output_bfd, -tpoff (info, relocation),
 		      htab->elf.sgot->contents + off);
 	  relocation = htab->elf.sgot->output_offset + off;
 	  if (r_type == R_390_TLS_IEENT)
@@ -2857,14 +2859,14 @@ elf_s390_relocate_section (bfd *output_bfd,
 	      outrel.r_offset = (htab->elf.sgot->output_section->vma
 				 + htab->elf.sgot->output_offset + off);
 
-	      bfd_put_32 (output_bfd, 0,
+	      bfd_put_32 (info->output_bfd, 0,
 			  htab->elf.sgot->contents + off + GOT_ENTRY_SIZE);
 	      outrel.r_info = ELF32_R_INFO (0, R_390_TLS_DTPMOD);
 	      outrel.r_addend = 0;
 	      loc = htab->elf.srelgot->contents;
 	      loc += htab->elf.srelgot->reloc_count++
 		* sizeof (Elf32_External_Rela);
-	      bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+	      bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 	      htab->tls_ldm_got.offset |= 1;
 	    }
 	  relocation = htab->elf.sgot->output_offset + off;
@@ -2898,12 +2900,13 @@ elf_s390_relocate_section (bfd *output_bfd,
 		abort ();
 	      loc = sreloc->contents;
 	      loc += sreloc->reloc_count++ * sizeof (Elf32_External_Rela);
-	      bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+	      bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 	    }
 	  else
 	    {
 	      BFD_ASSERT (! unresolved_reloc);
-	      bfd_put_32 (output_bfd, -tpoff (info, relocation) + rel->r_addend,
+	      bfd_put_32 (info->output_bfd,
+			  -tpoff (info, relocation) + rel->r_addend,
 			  contents + rel->r_offset);
 	    }
 	  continue;
@@ -2959,7 +2962,7 @@ elf_s390_relocate_section (bfd *output_bfd,
 		      return false;
 		    }
 		  insn = 0x18000700 | (insn & 0x00f00000) | ry;
-		  bfd_put_32 (output_bfd, insn, contents + rel->r_offset);
+		  bfd_put_32 (info->output_bfd, insn, contents + rel->r_offset);
 		}
 	    }
 	  else if (r_type == R_390_TLS_GDCALL)
@@ -2993,7 +2996,7 @@ elf_s390_relocate_section (bfd *output_bfd,
 		      /* GD->LE transition.
 			 brasl %r14,_tls_get_offset@plt -> brcl 0,.  */
 		      insn = 0xc0040000;
-		      bfd_put_16 (output_bfd, 0x0000,
+		      bfd_put_16 (info->output_bfd, 0x0000,
 				  contents + rel->r_offset + 4);
 		    }
 		}
@@ -3019,11 +3022,11 @@ elf_s390_relocate_section (bfd *output_bfd,
 			 brasl %r14,__tls_get_addr@plt ->
 				l %r2,0(%r2,%r12) ; bcr 0,0 */
 		      insn = 0x5822c000;
-		      bfd_put_16 (output_bfd, 0x0700,
+		      bfd_put_16 (info->output_bfd, 0x0700,
 				  contents + rel->r_offset + 4);
 		    }
 		}
-	      bfd_put_32 (output_bfd, insn, contents + rel->r_offset);
+	      bfd_put_32 (info->output_bfd, insn, contents + rel->r_offset);
 	    }
 	  else if (r_type == R_390_TLS_LDCALL)
 	    {
@@ -3057,10 +3060,10 @@ elf_s390_relocate_section (bfd *output_bfd,
 		      /* LD->LE transition.
 			 brasl %r14,__tls_get_offset@plt -> brcl 0,. */
 		      insn = 0xc0040000;
-		      bfd_put_16 (output_bfd, 0x0000,
+		      bfd_put_16 (info->output_bfd, 0x0000,
 				  contents + rel->r_offset + 4);
 		    }
-		  bfd_put_32 (output_bfd, insn, contents + rel->r_offset);
+		  bfd_put_32 (info->output_bfd, insn, contents + rel->r_offset);
 		}
 	    }
 	  continue;
@@ -3075,7 +3078,7 @@ elf_s390_relocate_section (bfd *output_bfd,
       if (unresolved_reloc
 	  && !((input_section->flags & SEC_DEBUGGING) != 0
 	       && h->def_dynamic)
-	  && _bfd_elf_section_offset (output_bfd, info, input_section,
+	  && _bfd_elf_section_offset (info->output_bfd, info, input_section,
 				      rel->r_offset) != (bfd_vma) -1)
 	_bfd_error_handler
 	  /* xgettext:c-format */
@@ -3298,8 +3301,7 @@ elf_s390_finish_ifunc_symbol (bfd *output_bfd,
    dynamic sections here.  */
 
 static bool
-elf_s390_finish_dynamic_symbol (bfd *output_bfd,
-				struct bfd_link_info *info,
+elf_s390_finish_dynamic_symbol (struct bfd_link_info *info,
 				struct elf_link_hash_entry *h,
 				Elf_Internal_Sym *sym)
 {
@@ -3320,7 +3322,7 @@ elf_s390_finish_dynamic_symbol (bfd *output_bfd,
 	 it up.  */
       if (s390_is_ifunc_symbol_p (h) && h->def_regular)
 	{
-	  elf_s390_finish_ifunc_symbol (output_bfd, info, h,
+	  elf_s390_finish_ifunc_symbol (info->output_bfd, info, h,
 	    htab, h->plt.offset,
 	    eh->ifunc_resolver_address +
 	    eh->ifunc_resolver_section->output_offset +
@@ -3360,11 +3362,11 @@ elf_s390_finish_dynamic_symbol (bfd *output_bfd,
 		      PLT_ENTRY_SIZE);
 
 	      /* Adjust jump to the first plt entry.  */
-	      bfd_put_32 (output_bfd, (bfd_vma) 0+(relative_offset << 16),
+	      bfd_put_32 (info->output_bfd, relative_offset << 16,
 			  htab->elf.splt->contents + h->plt.offset + 20);
 
 	      /* Push the GOT offset field.  */
-	      bfd_put_32 (output_bfd,
+	      bfd_put_32 (info->output_bfd,
 			  (htab->elf.sgotplt->output_section->vma
 			   + htab->elf.sgotplt->output_offset
 			   + got_offset),
@@ -3381,11 +3383,11 @@ elf_s390_finish_dynamic_symbol (bfd *output_bfd,
 	      /* Put in the GOT offset as displacement value.  The 0xc000
 		 value comes from the first word of the plt entry.  Look
 		 at the elf_s390_plt_pic12_entry content.  */
-	      bfd_put_16 (output_bfd, (bfd_vma)0xc000 | got_offset,
+	      bfd_put_16 (info->output_bfd, 0xc000 | got_offset,
 			  htab->elf.splt->contents + h->plt.offset + 2);
 
 	      /* Adjust the jump to the first plt entry.  */
-	      bfd_put_32 (output_bfd, (bfd_vma) 0+(relative_offset << 16),
+	      bfd_put_32 (info->output_bfd, relative_offset << 16,
 			  htab->elf.splt->contents + h->plt.offset + 20);
 	    }
 	  else if (got_offset < 32768)
@@ -3398,11 +3400,11 @@ elf_s390_finish_dynamic_symbol (bfd *output_bfd,
 		      PLT_ENTRY_SIZE);
 
 	      /* Put in the GOT offset for the lhi instruction.  */
-	      bfd_put_16 (output_bfd, (bfd_vma)got_offset,
+	      bfd_put_16 (info->output_bfd, got_offset,
 			  htab->elf.splt->contents + h->plt.offset + 2);
 
 	      /* Adjust the jump to the first plt entry.  */
-	      bfd_put_32 (output_bfd, (bfd_vma) 0+(relative_offset << 16),
+	      bfd_put_32 (info->output_bfd, relative_offset << 16,
 			  htab->elf.splt->contents + h->plt.offset + 20);
 	    }
 	  else
@@ -3412,20 +3414,20 @@ elf_s390_finish_dynamic_symbol (bfd *output_bfd,
 		      PLT_ENTRY_SIZE);
 
 	      /* Adjust the jump to the first plt entry.  */
-	      bfd_put_32 (output_bfd, (bfd_vma) 0+(relative_offset << 16),
+	      bfd_put_32 (info->output_bfd, relative_offset << 16,
 			  htab->elf.splt->contents + h->plt.offset + 20);
 
 	      /* Push the GOT offset field.  */
-	      bfd_put_32 (output_bfd, got_offset,
+	      bfd_put_32 (info->output_bfd, got_offset,
 			  htab->elf.splt->contents + h->plt.offset + 24);
 	    }
 	  /* Insert offset into  reloc. table here.  */
-	  bfd_put_32 (output_bfd, plt_index * sizeof (Elf32_External_Rela),
+	  bfd_put_32 (info->output_bfd, plt_index * sizeof (Elf32_External_Rela),
 		      htab->elf.splt->contents + h->plt.offset + 28);
 
 	  /* Fill in the entry in the global offset table.
 	     Points to instruction after GOT offset.  */
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 		      (htab->elf.splt->output_section->vma
 		       + htab->elf.splt->output_offset
 		       + h->plt.offset
@@ -3439,7 +3441,7 @@ elf_s390_finish_dynamic_symbol (bfd *output_bfd,
 	  rela.r_info = ELF32_R_INFO (h->dynindx, R_390_JMP_SLOT);
 	  rela.r_addend = 0;
 	  loc = htab->elf.srelplt->contents + plt_index * sizeof (Elf32_External_Rela);
-	  bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+	  bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
 
 	  if (!h->def_regular)
 	    {
@@ -3491,9 +3493,9 @@ elf_s390_finish_dynamic_symbol (bfd *output_bfd,
 	      /* For non-shared objects explicit GOT slots must be
 		 filled with the PLT slot address for pointer
 		 equality reasons.  */
-	      bfd_put_32 (output_bfd, (htab->elf.iplt->output_section->vma
-				       + htab->elf.iplt->output_offset
-				       + h->plt.offset),
+	      bfd_put_32 (info->output_bfd, (htab->elf.iplt->output_section->vma
+					     + htab->elf.iplt->output_offset
+					     + h->plt.offset),
 			  htab->elf.sgot->contents + h->got.offset);
 	      return true;
 	    }
@@ -3521,14 +3523,15 @@ elf_s390_finish_dynamic_symbol (bfd *output_bfd,
 	{
 	  BFD_ASSERT((h->got.offset & 1) == 0);
 	do_glob_dat:
-	  bfd_put_32 (output_bfd, (bfd_vma) 0, htab->elf.sgot->contents + h->got.offset);
+	  bfd_put_32 (info->output_bfd, 0,
+		      htab->elf.sgot->contents + h->got.offset);
 	  rela.r_info = ELF32_R_INFO (h->dynindx, R_390_GLOB_DAT);
 	  rela.r_addend = 0;
 	}
 
       loc = htab->elf.srelgot->contents;
       loc += htab->elf.srelgot->reloc_count++ * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
     }
 
   if (h->needs_copy)
@@ -3556,7 +3559,7 @@ elf_s390_finish_dynamic_symbol (bfd *output_bfd,
       else
 	s = htab->elf.srelbss;
       loc = s->contents + s->reloc_count++ * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
     }
 
   /* Mark some specially defined symbols as absolute.  */
@@ -3609,8 +3612,7 @@ elf_s390_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
 /* Finish up the dynamic sections.  */
 
 static bool
-elf_s390_finish_dynamic_sections (bfd *output_bfd,
-				  struct bfd_link_info *info,
+elf_s390_finish_dynamic_sections (struct bfd_link_info *info,
 				  bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   struct elf_s390_link_hash_table *htab;
@@ -3661,7 +3663,7 @@ elf_s390_finish_dynamic_sections (bfd *output_bfd,
 	      break;
 	    }
 
-	  bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	  bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	}
 
       /* Fill in the special first entry in the procedure linkage table.  */
@@ -3677,7 +3679,7 @@ elf_s390_finish_dynamic_sections (bfd *output_bfd,
 	    {
 	      memcpy (htab->elf.splt->contents, elf_s390_plt_first_entry,
 		      PLT_FIRST_ENTRY_SIZE);
-	      bfd_put_32 (output_bfd,
+	      bfd_put_32 (info->output_bfd,
 			  htab->elf.sgotplt->output_section->vma
 			  + htab->elf.sgotplt->output_offset,
 			  htab->elf.splt->contents + 24);
@@ -3693,14 +3695,14 @@ elf_s390_finish_dynamic_sections (bfd *output_bfd,
       /* Fill in the first three entries in the global offset table.  */
       if (htab->elf.sgotplt->size > 0)
 	{
-	  bfd_put_32 (output_bfd,
-		      (sdyn == NULL ? (bfd_vma) 0
+	  bfd_put_32 (info->output_bfd,
+		      (sdyn == NULL ? 0
 		       : sdyn->output_section->vma + sdyn->output_offset),
 		      htab->elf.sgotplt->contents);
 	  /* One entry for shared object struct ptr.  */
-	  bfd_put_32 (output_bfd, (bfd_vma) 0, htab->elf.sgotplt->contents + 4);
+	  bfd_put_32 (info->output_bfd, 0, htab->elf.sgotplt->contents + 4);
 	  /* One entry for _dl_runtime_resolve.  */
-	  bfd_put_32 (output_bfd, (bfd_vma) 0, htab->elf.sgotplt->contents + 8);
+	  bfd_put_32 (info->output_bfd, 0, htab->elf.sgotplt->contents + 8);
 	}
 
       elf_section_data (htab->elf.sgotplt->output_section)
@@ -3730,7 +3732,8 @@ elf_s390_finish_dynamic_sections (bfd *output_bfd,
 		  return false;
 
 		if (ELF_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
-		  elf_s390_finish_ifunc_symbol (output_bfd, info, NULL, htab,
+		  elf_s390_finish_ifunc_symbol (info->output_bfd, info, NULL,
+						htab,
 						local_plt[i].plt.offset,
 						isym->st_value
 						+ sec->output_section->vma
diff --git a/bfd/elf32-score.c b/bfd/elf32-score.c
index 1b3a1cc5dff..606458722bc 100644
--- a/bfd/elf32-score.c
+++ b/bfd/elf32-score.c
@@ -2407,8 +2407,7 @@ s3_bfd_score_info_to_howto (bfd *abfd,
 
 /* Relocate an score ELF section.  */
 static int
-s3_bfd_score_elf_relocate_section (bfd *output_bfd,
-				   struct bfd_link_info *info,
+s3_bfd_score_elf_relocate_section (struct bfd_link_info *info,
 				   bfd *input_bfd,
 				   asection *input_section,
 				   bfd_byte *contents,
@@ -2432,12 +2431,12 @@ s3_bfd_score_elf_relocate_section (bfd *output_bfd,
       if (bfd_link_pic (info))
 	{
 	  asection * p;
-	  elf_backend_data *bed = get_elf_backend_data (output_bfd);
+	  elf_backend_data *bed = get_elf_backend_data (info->output_bfd);
 
-	  for (p = output_bfd->sections; p ; p = p->next)
+	  for (p = info->output_bfd->sections; p ; p = p->next)
 	    if ((p->flags & SEC_EXCLUDE) == 0
 		&& (p->flags & SEC_ALLOC) != 0
-		&& !(*bed->elf_backend_omit_section_dynsym) (output_bfd, info, p))
+		&& !bed->elf_backend_omit_section_dynsym (info, p))
 	      ++ dynsecsymcount;
 	}
 
@@ -2499,7 +2498,8 @@ s3_bfd_score_elf_relocate_section (bfd *output_bfd,
 		  offset = ((((value >> 16) & 0x3) << 15) | (value & 0x7fff)) >> 1;
 		  addend = (hi16_offset << 16) | (offset & 0xffff);
 		  msec = sec;
-		  addend = _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend);
+		  addend = _bfd_elf_rel_local_sym (info->output_bfd,
+						   sym, &msec, addend);
 		  addend -= relocation;
 		  addend += msec->output_section->vma + msec->output_offset;
 		  uvalue = addend;
@@ -2520,7 +2520,8 @@ s3_bfd_score_elf_relocate_section (bfd *output_bfd,
 			      | (((value >> 16) & 0x7fff) << 10)
 			      | (((value >> 32) & 0x7f) << 25);
 		    msec = sec;
-		    addend = _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend);
+		    addend = _bfd_elf_rel_local_sym (info->output_bfd,
+						     sym, &msec, addend);
 		    addend -= relocation;
 		    addend += msec->output_section->vma + msec->output_offset;
 		    addend &= 0xffffffff;
@@ -2541,7 +2542,8 @@ s3_bfd_score_elf_relocate_section (bfd *output_bfd,
 			      | (((value >> 32) & 0x7f) << 23);
 		    addend <<= howto->rightshift;
 		    msec = sec;
-		    addend = _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend);
+		    addend = _bfd_elf_rel_local_sym (info->output_bfd,
+						     sym, &msec, addend);
 		    addend -= relocation;
 		    addend += msec->output_section->vma + msec->output_offset;
 		    addend &= 0xffffffff;
@@ -2567,7 +2569,8 @@ s3_bfd_score_elf_relocate_section (bfd *output_bfd,
 		  value = score_bfd_get_32 (input_bfd, contents + rel->r_offset);
 		  addend = (((value >> 16) & 0x3) << 14) | ((value & 0x7fff) >> 1);
 		  msec = sec;
-		  addend = _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend) - relocation;
+		  addend = _bfd_elf_rel_local_sym (info->output_bfd, sym, &msec,
+						   addend) - relocation;
 		  addend += msec->output_section->vma + msec->output_offset;
 		  value = (value & (~(howto->dst_mask))) | ((addend & 0x3fff) << 1)
 			   | (((addend >> 14) & 0x3) << 16);
@@ -2589,7 +2592,8 @@ s3_bfd_score_elf_relocate_section (bfd *output_bfd,
 		      addend |= mask;
 		    }
 		  msec = sec;
-		  addend = _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend) - relocation;
+		  addend = _bfd_elf_rel_local_sym (info->output_bfd, sym, &msec,
+						   addend) - relocation;
 		  addend += msec->output_section->vma + msec->output_offset;
 		  value = (value & ~howto->dst_mask) | (addend & howto->dst_mask);
 		  bfd_put_32 (input_bfd, value, contents + rel->r_offset);
@@ -2608,7 +2612,8 @@ s3_bfd_score_elf_relocate_section (bfd *output_bfd,
 		      addend |= mask;
 		    }
 		  msec = sec;
-		  addend = _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend) - relocation;
+		  addend = _bfd_elf_rel_local_sym (info->output_bfd, sym, &msec,
+						   addend) - relocation;
 		  addend += msec->output_section->vma + msec->output_offset;
 		  value = (value & ~howto->dst_mask) | (addend & howto->dst_mask);
 		  score_bfd_put_32 (input_bfd, value, contents + rel->r_offset);
@@ -2679,7 +2684,8 @@ s3_bfd_score_elf_relocate_section (bfd *output_bfd,
 		 in s3_bfd_score_elf_create_dynamic_sections.  Otherwise, we should define
 		 the symbol with a value of 0.  */
 	      BFD_ASSERT (! bfd_link_pic (info));
-	      BFD_ASSERT (bfd_get_section_by_name (output_bfd, ".dynamic") == NULL);
+	      BFD_ASSERT (bfd_get_section_by_name (info->output_bfd,
+						   ".dynamic") == NULL);
 	      relocation = 0;
 	    }
 	  else if (!bfd_link_relocatable (info))
@@ -2719,7 +2725,7 @@ s3_bfd_score_elf_relocate_section (bfd *output_bfd,
 	}
 
       /* This is a final link.  */
-      r = score_elf_final_link_relocate (howto, input_bfd, output_bfd,
+      r = score_elf_final_link_relocate (howto, input_bfd, info->output_bfd,
 					 input_section, contents, rel, relocs,
 					 relocation, info, name,
 					 (h ? ELF_ST_TYPE ((unsigned int)h->root.root.type) :
@@ -3176,8 +3182,7 @@ s3_bfd_score_elf_adjust_dynamic_symbol (struct bfd_link_info *info,
 /* This function is called after all the input files have been read,
    and the input sections have been assigned to output sections.  */
 static bool
-s3_bfd_score_elf_early_size_sections (bfd *output_bfd,
-				      struct bfd_link_info *info)
+s3_bfd_score_elf_early_size_sections (struct bfd_link_info *info)
 {
   bfd *dynobj;
   asection *s;
@@ -3236,14 +3241,14 @@ s3_bfd_score_elf_early_size_sections (bfd *output_bfd,
   local_gotno = (loadable_size >> 16) + 5;
 
   g->local_gotno += local_gotno;
-  s->size += g->local_gotno * SCORE_ELF_GOT_SIZE (output_bfd);
+  s->size += g->local_gotno * SCORE_ELF_GOT_SIZE (info->output_bfd);
 
   g->global_gotno = i;
-  s->size += i * SCORE_ELF_GOT_SIZE (output_bfd);
+  s->size += i * SCORE_ELF_GOT_SIZE (info->output_bfd);
 
   score_elf_resolve_final_got_entries (g);
 
-  if (s->size > SCORE_ELF_GOT_MAX_SIZE (output_bfd))
+  if (s->size > SCORE_ELF_GOT_MAX_SIZE (info->output_bfd))
     {
       /* Fixme. Error message or Warning message should be issued here.  */
     }
@@ -3253,7 +3258,7 @@ s3_bfd_score_elf_early_size_sections (bfd *output_bfd,
 
 /* Set the sizes of the dynamic sections.  */
 static bool
-s3_bfd_score_elf_late_size_sections (bfd *output_bfd, struct bfd_link_info *info)
+s3_bfd_score_elf_late_size_sections (struct bfd_link_info *info)
 {
   bfd *dynobj;
   asection *s;
@@ -3317,7 +3322,7 @@ s3_bfd_score_elf_late_size_sections (bfd *output_bfd, struct bfd_link_info *info
 		 there exists a relocation to a read only section or
 		 not.  */
 	      outname = bfd_section_name (s->output_section);
-	      target = bfd_get_section_by_name (output_bfd, outname + 4);
+	      target = bfd_get_section_by_name (info->output_bfd, outname + 4);
 	      if ((target != NULL
 		   && (target->flags & SEC_READONLY) != 0
 		   && (target->flags & SEC_ALLOC) != 0) || strcmp (outname, ".rel.dyn") == 0)
@@ -3479,8 +3484,7 @@ s3_bfd_score_elf_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info)
 /* Finish up dynamic symbol handling.  We set the contents of various
    dynamic sections here.  */
 static bool
-s3_bfd_score_elf_finish_dynamic_symbol (bfd *output_bfd,
-					struct bfd_link_info *info,
+s3_bfd_score_elf_finish_dynamic_symbol (struct bfd_link_info *info,
 					struct elf_link_hash_entry *h,
 					Elf_Internal_Sym *sym)
 {
@@ -3507,16 +3511,17 @@ s3_bfd_score_elf_finish_dynamic_symbol (bfd *output_bfd,
 	{
 	  _bfd_error_handler
 	    (_("%pB: cannot handle more than %d dynamic symbols"),
-	     output_bfd, 0xffff);
+	     info->output_bfd, 0xffff);
 	  bfd_set_error (bfd_error_bad_value);
 	  return false;
 	}
 
       /* Fill the stub.  */
-      score_bfd_put_32 (output_bfd, STUB_LW, stub);
-      score_bfd_put_32 (output_bfd, STUB_MOVE, stub + 4);
-      score_bfd_put_32 (output_bfd, STUB_LI16 | (h->dynindx << 1), stub + 8);
-      score_bfd_put_32 (output_bfd, STUB_BRL, stub + 12);
+      score_bfd_put_32 (info->output_bfd, STUB_LW, stub);
+      score_bfd_put_32 (info->output_bfd, STUB_MOVE, stub + 4);
+      score_bfd_put_32 (info->output_bfd, STUB_LI16 | (h->dynindx << 1),
+			stub + 8);
+      score_bfd_put_32 (info->output_bfd, STUB_BRL, stub + 12);
 
       BFD_ASSERT (h->plt.offset <= s->size);
       memcpy (s->contents + h->plt.offset, stub, SCORE_FUNCTION_STUB_SIZE);
@@ -3548,7 +3553,7 @@ s3_bfd_score_elf_finish_dynamic_symbol (bfd *output_bfd,
 
       value = sym->st_value;
       offset = score_elf_global_got_index (dynobj, h);
-      score_bfd_put_32 (output_bfd, value, sgot->contents + offset);
+      score_bfd_put_32 (info->output_bfd, value, sgot->contents + offset);
     }
 
   /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute.  */
@@ -3566,7 +3571,7 @@ s3_bfd_score_elf_finish_dynamic_symbol (bfd *output_bfd,
     {
       sym->st_shndx = SHN_ABS;
       sym->st_info = ELF_ST_INFO (STB_GLOBAL, STT_SECTION);
-      sym->st_value = elf_gp (output_bfd);
+      sym->st_value = elf_gp (info->output_bfd);
     }
 
   return true;
@@ -3574,8 +3579,7 @@ s3_bfd_score_elf_finish_dynamic_symbol (bfd *output_bfd,
 
 /* Finish up the dynamic sections.  */
 static bool
-s3_bfd_score_elf_finish_dynamic_sections (bfd *output_bfd,
-					  struct bfd_link_info *info,
+s3_bfd_score_elf_finish_dynamic_sections (struct bfd_link_info *info,
 					  bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   bfd *dynobj;
@@ -3638,7 +3642,7 @@ s3_bfd_score_elf_finish_dynamic_sections (bfd *output_bfd,
 	      break;
 
 	    case DT_SCORE_BASE_ADDRESS:
-	      s = output_bfd->sections;
+	      s = info->output_bfd->sections;
 	      BFD_ASSERT (s != NULL);
 	      dyn.d_un.d_ptr = s->vma & ~(bfd_vma) 0xffff;
 	      break;
@@ -3651,7 +3655,7 @@ s3_bfd_score_elf_finish_dynamic_sections (bfd *output_bfd,
 	      /* The index into the dynamic symbol table which is the
 		 entry of the first external symbol that is not
 		 referenced within the same object.  */
-	      dyn.d_un.d_val = bfd_count_sections (output_bfd) + 1;
+	      dyn.d_un.d_val = bfd_count_sections (info->output_bfd) + 1;
 	      break;
 
 	    case DT_SCORE_GOTSYM:
@@ -3667,7 +3671,7 @@ s3_bfd_score_elf_finish_dynamic_sections (bfd *output_bfd,
 
 	    case DT_SCORE_SYMTABNO:
 	      name = ".dynsym";
-	      elemsize = SCORE_ELF_SYM_SIZE (output_bfd);
+	      elemsize = SCORE_ELF_SYM_SIZE (info->output_bfd);
 	      s = bfd_get_linker_section (dynobj, name);
 	      dyn.d_un.d_val = s->size / elemsize;
 	      break;
@@ -3691,21 +3695,22 @@ s3_bfd_score_elf_finish_dynamic_sections (bfd *output_bfd,
      This isn't the case of IRIX rld.  */
   if (sgot != NULL && sgot->size > 0)
     {
-      score_bfd_put_32 (output_bfd, 0, sgot->contents);
-      score_bfd_put_32 (output_bfd, 0x80000000, sgot->contents + SCORE_ELF_GOT_SIZE (output_bfd));
+      score_bfd_put_32 (info->output_bfd, 0, sgot->contents);
+      score_bfd_put_32 (info->output_bfd, 0x80000000,
+			sgot->contents + SCORE_ELF_GOT_SIZE (info->output_bfd));
     }
 
   if (sgot != NULL)
     elf_section_data (sgot->output_section)->this_hdr.sh_entsize
-      = SCORE_ELF_GOT_SIZE (output_bfd);
+      = SCORE_ELF_GOT_SIZE (info->output_bfd);
 
 
   /* We need to sort the entries of the dynamic relocation section.  */
   s = score_elf_rel_dyn_section (dynobj, false);
 
-  if (s != NULL && s->size > (bfd_vma)2 * SCORE_ELF_REL_SIZE (output_bfd))
+  if (s != NULL && s->size > (bfd_vma)2 * SCORE_ELF_REL_SIZE (info->output_bfd))
     {
-      reldyn_sorting_bfd = output_bfd;
+      reldyn_sorting_bfd = info->output_bfd;
       qsort ((Elf32_External_Rel *) s->contents + 1, s->reloc_count - 1,
 	     sizeof (Elf32_External_Rel), score_elf_sort_dynamic_relocs);
     }
@@ -4098,8 +4103,7 @@ _bfd_score_info_to_howto (bfd *abfd ATTRIBUTE_UNUSED,
 }
 
 static int
-_bfd_score_elf_relocate_section (bfd *output_bfd,
-				 struct bfd_link_info *info,
+_bfd_score_elf_relocate_section (struct bfd_link_info *info,
 				 bfd *input_bfd,
 				 asection *input_section,
 				 bfd_byte *contents,
@@ -4107,14 +4111,14 @@ _bfd_score_elf_relocate_section (bfd *output_bfd,
 				 Elf_Internal_Sym *local_syms,
 				 asection **local_sections)
 {
-  if (bfd_get_mach (output_bfd) == bfd_mach_score3)
-    return s3_bfd_score_elf_relocate_section (output_bfd,
-	     info, input_bfd, input_section, contents, relocs,
-	     local_syms, local_sections);
+  if (bfd_get_mach (info->output_bfd) == bfd_mach_score3)
+    return s3_bfd_score_elf_relocate_section (info, input_bfd, input_section,
+					      contents, relocs,
+					      local_syms, local_sections);
   else
-    return s7_bfd_score_elf_relocate_section (output_bfd,
-	     info, input_bfd, input_section, contents, relocs,
-	     local_syms, local_sections);
+    return s7_bfd_score_elf_relocate_section (info, input_bfd, input_section,
+					      contents, relocs,
+					      local_syms, local_sections);
 }
 
 static bool
@@ -4201,22 +4205,21 @@ _bfd_score_elf_adjust_dynamic_symbol (struct bfd_link_info *info,
 }
 
 static bool
-_bfd_score_elf_early_size_sections (bfd *output_bfd,
-				    struct bfd_link_info *info)
+_bfd_score_elf_early_size_sections (struct bfd_link_info *info)
 {
-  if (bfd_get_mach (output_bfd) == bfd_mach_score3)
-    return s3_bfd_score_elf_early_size_sections (output_bfd, info);
+  if (bfd_get_mach (info->output_bfd) == bfd_mach_score3)
+    return s3_bfd_score_elf_early_size_sections (info);
   else
-    return s7_bfd_score_elf_early_size_sections (output_bfd, info);
+    return s7_bfd_score_elf_early_size_sections (info);
 }
 
 static bool
-_bfd_score_elf_late_size_sections (bfd *output_bfd, struct bfd_link_info *info)
+_bfd_score_elf_late_size_sections (struct bfd_link_info *info)
 {
-  if (bfd_get_mach (output_bfd) == bfd_mach_score3)
-    return s3_bfd_score_elf_late_size_sections (output_bfd, info);
+  if (bfd_get_mach (info->output_bfd) == bfd_mach_score3)
+    return s3_bfd_score_elf_late_size_sections (info);
   else
-    return s7_bfd_score_elf_late_size_sections (output_bfd, info);
+    return s7_bfd_score_elf_late_size_sections (info);
 }
 
 static bool
@@ -4229,26 +4232,24 @@ _bfd_score_elf_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info)
 }
 
 static bool
-_bfd_score_elf_finish_dynamic_symbol (bfd *output_bfd,
-				      struct bfd_link_info *info,
+_bfd_score_elf_finish_dynamic_symbol (struct bfd_link_info *info,
 				      struct elf_link_hash_entry *h,
 				      Elf_Internal_Sym *sym)
 {
-  if (bfd_get_mach (output_bfd) == bfd_mach_score3)
-    return s3_bfd_score_elf_finish_dynamic_symbol (output_bfd, info, h, sym);
+  if (bfd_get_mach (info->output_bfd) == bfd_mach_score3)
+    return s3_bfd_score_elf_finish_dynamic_symbol (info, h, sym);
   else
-    return s7_bfd_score_elf_finish_dynamic_symbol (output_bfd, info, h, sym);
+    return s7_bfd_score_elf_finish_dynamic_symbol (info, h, sym);
 }
 
 static bool
-_bfd_score_elf_finish_dynamic_sections (bfd *output_bfd,
-					struct bfd_link_info *info,
+_bfd_score_elf_finish_dynamic_sections (struct bfd_link_info *info,
 					bfd_byte *buf)
 {
-  if (bfd_get_mach (output_bfd) == bfd_mach_score3)
-    return s3_bfd_score_elf_finish_dynamic_sections (output_bfd, info, buf);
+  if (bfd_get_mach (info->output_bfd) == bfd_mach_score3)
+    return s3_bfd_score_elf_finish_dynamic_sections (info, buf);
   else
-    return s7_bfd_score_elf_finish_dynamic_sections (output_bfd, info, buf);
+    return s7_bfd_score_elf_finish_dynamic_sections (info, buf);
 }
 
 static bool
diff --git a/bfd/elf32-score.h b/bfd/elf32-score.h
index 506446b690a..910454af41b 100644
--- a/bfd/elf32-score.h
+++ b/bfd/elf32-score.h
@@ -35,8 +35,7 @@ s7_bfd_score_info_to_howto (bfd *, arelent *, Elf_Internal_Rela *)
   ATTRIBUTE_HIDDEN;
 
 extern int
-s7_bfd_score_elf_relocate_section (bfd *,
-				   struct bfd_link_info *,
+s7_bfd_score_elf_relocate_section (struct bfd_link_info *,
 				   bfd *,
 				   asection *,
 				   bfd_byte *,
@@ -81,11 +80,11 @@ s7_bfd_score_elf_adjust_dynamic_symbol (struct bfd_link_info *,
   ATTRIBUTE_HIDDEN;
 
 extern bool
-s7_bfd_score_elf_early_size_sections (bfd *, struct bfd_link_info *)
+s7_bfd_score_elf_early_size_sections (struct bfd_link_info *)
   ATTRIBUTE_HIDDEN;
 
 extern bool
-s7_bfd_score_elf_late_size_sections (bfd *, struct bfd_link_info *)
+s7_bfd_score_elf_late_size_sections (struct bfd_link_info *)
   ATTRIBUTE_HIDDEN;
 
 extern bool
@@ -93,13 +92,12 @@ s7_bfd_score_elf_create_dynamic_sections (bfd *, struct bfd_link_info *)
   ATTRIBUTE_HIDDEN;
 
 extern bool
-s7_bfd_score_elf_finish_dynamic_symbol (bfd *,
-					struct bfd_link_info *,
+s7_bfd_score_elf_finish_dynamic_symbol (struct bfd_link_info *,
 					struct elf_link_hash_entry *,
 					Elf_Internal_Sym *) ATTRIBUTE_HIDDEN;
 
 extern bool
-s7_bfd_score_elf_finish_dynamic_sections (bfd *, struct bfd_link_info *,
+s7_bfd_score_elf_finish_dynamic_sections (struct bfd_link_info *,
 					  bfd_byte *) ATTRIBUTE_HIDDEN;
 
 extern bool
diff --git a/bfd/elf32-score7.c b/bfd/elf32-score7.c
index 6bccccc6f67..81c079ff631 100644
--- a/bfd/elf32-score7.c
+++ b/bfd/elf32-score7.c
@@ -2249,8 +2249,7 @@ s7_bfd_score_info_to_howto (bfd *abfd,
 /* Relocate an score ELF section.  */
 
 int
-s7_bfd_score_elf_relocate_section (bfd *output_bfd,
-				   struct bfd_link_info *info,
+s7_bfd_score_elf_relocate_section (struct bfd_link_info *info,
 				   bfd *input_bfd,
 				   asection *input_section,
 				   bfd_byte *contents,
@@ -2274,12 +2273,12 @@ s7_bfd_score_elf_relocate_section (bfd *output_bfd,
       if (bfd_link_pic (info))
 	{
 	  asection * p;
-	  elf_backend_data *bed = get_elf_backend_data (output_bfd);
+	  elf_backend_data *bed = get_elf_backend_data (info->output_bfd);
 
-	  for (p = output_bfd->sections; p ; p = p->next)
+	  for (p = info->output_bfd->sections; p ; p = p->next)
 	    if ((p->flags & SEC_EXCLUDE) == 0
 		&& (p->flags & SEC_ALLOC) != 0
-		&& !(*bed->elf_backend_omit_section_dynsym) (output_bfd, info, p))
+		&& !bed->elf_backend_omit_section_dynsym (info, p))
 	      ++ dynsecsymcount;
 	}
 
@@ -2346,7 +2345,8 @@ s7_bfd_score_elf_relocate_section (bfd *output_bfd,
 		      offset = ((((value >> 16) & 0x3) << 15) | (value & 0x7fff)) >> 1;
 		      addend = (hi16_offset << 16) | (offset & 0xffff);
 		      msec = sec;
-		      addend = _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend);
+		      addend = _bfd_elf_rel_local_sym (info->output_bfd,
+						       sym, &msec, addend);
 		      addend -= relocation;
 		      addend += msec->output_section->vma + msec->output_offset;
 		      uvalue = addend;
@@ -2363,7 +2363,8 @@ s7_bfd_score_elf_relocate_section (bfd *output_bfd,
 		      value = bfd_get_32 (input_bfd, contents + rel->r_offset);
 		      addend = (((value >> 16) & 0x3) << 14) | ((value & 0x7fff) >> 1);
 		      msec = sec;
-		      addend = _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend) - relocation;
+		      addend = _bfd_elf_rel_local_sym (info->output_bfd, sym,
+						       &msec, addend) - relocation;
 		      addend += msec->output_section->vma + msec->output_offset;
 		      value = (value & (~(howto->dst_mask))) | ((addend & 0x3fff) << 1)
 			       | (((addend >> 14) & 0x3) << 16);
@@ -2383,7 +2384,8 @@ s7_bfd_score_elf_relocate_section (bfd *output_bfd,
 			  addend |= mask;
 			}
 		      msec = sec;
-		      addend = _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend) - relocation;
+		      addend = _bfd_elf_rel_local_sym (info->output_bfd, sym,
+						       &msec, addend) - relocation;
 		      addend += msec->output_section->vma + msec->output_offset;
 		      value = (value & ~howto->dst_mask) | (addend & howto->dst_mask);
 		      bfd_put_32 (input_bfd, value, contents + rel->r_offset);
@@ -2455,7 +2457,8 @@ s7_bfd_score_elf_relocate_section (bfd *output_bfd,
 		 in s7_bfd_score_elf_create_dynamic_sections.  Otherwise, we should define
 		 the symbol with a value of 0.  */
 	      BFD_ASSERT (! bfd_link_pic (info));
-	      BFD_ASSERT (bfd_get_section_by_name (output_bfd, ".dynamic") == NULL);
+	      BFD_ASSERT (bfd_get_section_by_name (info->output_bfd,
+						   ".dynamic") == NULL);
 	      relocation = 0;
 	    }
 	  else if (!bfd_link_relocatable (info))
@@ -2530,7 +2533,7 @@ s7_bfd_score_elf_relocate_section (bfd *output_bfd,
 	}
 
       /* This is a final link.  */
-      r = score_elf_final_link_relocate (howto, input_bfd, output_bfd,
+      r = score_elf_final_link_relocate (howto, input_bfd, info->output_bfd,
 					 input_section, contents, rel, relocs,
 					 relocation, info, name,
 					 (h ? ELF_ST_TYPE ((unsigned int) h->root.root.type) :
@@ -2985,8 +2988,7 @@ s7_bfd_score_elf_adjust_dynamic_symbol (struct bfd_link_info *info,
    and the input sections have been assigned to output sections.  */
 
 bool
-s7_bfd_score_elf_early_size_sections (bfd *output_bfd,
-				      struct bfd_link_info *info)
+s7_bfd_score_elf_early_size_sections (struct bfd_link_info *info)
 {
   bfd *dynobj;
   asection *s;
@@ -3045,14 +3047,14 @@ s7_bfd_score_elf_early_size_sections (bfd *output_bfd,
   local_gotno = (loadable_size >> 16) + 5;
 
   g->local_gotno += local_gotno;
-  s->size += g->local_gotno * SCORE_ELF_GOT_SIZE (output_bfd);
+  s->size += g->local_gotno * SCORE_ELF_GOT_SIZE (info->output_bfd);
 
   g->global_gotno = i;
-  s->size += i * SCORE_ELF_GOT_SIZE (output_bfd);
+  s->size += i * SCORE_ELF_GOT_SIZE (info->output_bfd);
 
   score_elf_resolve_final_got_entries (g);
 
-  if (s->size > SCORE_ELF_GOT_MAX_SIZE (output_bfd))
+  if (s->size > SCORE_ELF_GOT_MAX_SIZE (info->output_bfd))
     {
       /* Fixme. Error message or Warning message should be issued here.  */
     }
@@ -3063,7 +3065,7 @@ s7_bfd_score_elf_early_size_sections (bfd *output_bfd,
 /* Set the sizes of the dynamic sections.  */
 
 bool
-s7_bfd_score_elf_late_size_sections (bfd *output_bfd, struct bfd_link_info *info)
+s7_bfd_score_elf_late_size_sections (struct bfd_link_info *info)
 {
   bfd *dynobj;
   asection *s;
@@ -3127,7 +3129,7 @@ s7_bfd_score_elf_late_size_sections (bfd *output_bfd, struct bfd_link_info *info
 		 there exists a relocation to a read only section or
 		 not.  */
 	      outname = bfd_section_name (s->output_section);
-	      target = bfd_get_section_by_name (output_bfd, outname + 4);
+	      target = bfd_get_section_by_name (info->output_bfd, outname + 4);
 	      if ((target != NULL
 		   && (target->flags & SEC_READONLY) != 0
 		   && (target->flags & SEC_ALLOC) != 0) || strcmp (outname, ".rel.dyn") == 0)
@@ -3290,8 +3292,7 @@ s7_bfd_score_elf_create_dynamic_sections (bfd *abfd, struct bfd_link_info *info)
    dynamic sections here.  */
 
 bool
-s7_bfd_score_elf_finish_dynamic_symbol (bfd *output_bfd,
-					struct bfd_link_info *info,
+s7_bfd_score_elf_finish_dynamic_symbol (struct bfd_link_info *info,
 					struct elf_link_hash_entry *h,
 					Elf_Internal_Sym *sym)
 {
@@ -3318,16 +3319,16 @@ s7_bfd_score_elf_finish_dynamic_symbol (bfd *output_bfd,
 	{
 	  _bfd_error_handler
 	    (_("%pB: cannot handle more than %d dynamic symbols"),
-	     output_bfd, 0xffff);
+	     info->output_bfd, 0xffff);
 	  bfd_set_error (bfd_error_bad_value);
 	  return false;
 	}
 
       /* Fill the stub.  */
-      bfd_put_32 (output_bfd, STUB_LW, stub);
-      bfd_put_32 (output_bfd, STUB_MOVE, stub + 4);
-      bfd_put_32 (output_bfd, STUB_LI16 | (h->dynindx << 1), stub + 8);
-      bfd_put_32 (output_bfd, STUB_BRL, stub + 12);
+      bfd_put_32 (info->output_bfd, STUB_LW, stub);
+      bfd_put_32 (info->output_bfd, STUB_MOVE, stub + 4);
+      bfd_put_32 (info->output_bfd, STUB_LI16 | (h->dynindx << 1), stub + 8);
+      bfd_put_32 (info->output_bfd, STUB_BRL, stub + 12);
 
       BFD_ASSERT (h->plt.offset <= s->size);
       memcpy (s->contents + h->plt.offset, stub, SCORE_FUNCTION_STUB_SIZE);
@@ -3359,7 +3360,7 @@ s7_bfd_score_elf_finish_dynamic_symbol (bfd *output_bfd,
 
       value = sym->st_value;
       offset = score_elf_global_got_index (dynobj, h);
-      bfd_put_32 (output_bfd, value, sgot->contents + offset);
+      bfd_put_32 (info->output_bfd, value, sgot->contents + offset);
     }
 
   /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute.  */
@@ -3377,7 +3378,7 @@ s7_bfd_score_elf_finish_dynamic_symbol (bfd *output_bfd,
     {
       sym->st_shndx = SHN_ABS;
       sym->st_info = ELF_ST_INFO (STB_GLOBAL, STT_SECTION);
-      sym->st_value = elf_gp (output_bfd);
+      sym->st_value = elf_gp (info->output_bfd);
     }
 
   return true;
@@ -3386,8 +3387,7 @@ s7_bfd_score_elf_finish_dynamic_symbol (bfd *output_bfd,
 /* Finish up the dynamic sections.  */
 
 bool
-s7_bfd_score_elf_finish_dynamic_sections (bfd *output_bfd,
-					  struct bfd_link_info *info,
+s7_bfd_score_elf_finish_dynamic_sections (struct bfd_link_info *info,
 					  bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   bfd *dynobj;
@@ -3450,7 +3450,7 @@ s7_bfd_score_elf_finish_dynamic_sections (bfd *output_bfd,
 	      break;
 
 	    case DT_SCORE_BASE_ADDRESS:
-	      s = output_bfd->sections;
+	      s = info->output_bfd->sections;
 	      BFD_ASSERT (s != NULL);
 	      dyn.d_un.d_ptr = s->vma & ~(bfd_vma) 0xffff;
 	      break;
@@ -3463,7 +3463,7 @@ s7_bfd_score_elf_finish_dynamic_sections (bfd *output_bfd,
 	      /* The index into the dynamic symbol table which is the
 		 entry of the first external symbol that is not
 		 referenced within the same object.  */
-	      dyn.d_un.d_val = bfd_count_sections (output_bfd) + 1;
+	      dyn.d_un.d_val = bfd_count_sections (info->output_bfd) + 1;
 	      break;
 
 	    case DT_SCORE_GOTSYM:
@@ -3479,7 +3479,7 @@ s7_bfd_score_elf_finish_dynamic_sections (bfd *output_bfd,
 
 	    case DT_SCORE_SYMTABNO:
 	      name = ".dynsym";
-	      elemsize = SCORE_ELF_SYM_SIZE (output_bfd);
+	      elemsize = SCORE_ELF_SYM_SIZE (info->output_bfd);
 	      s = bfd_get_linker_section (dynobj, name);
 	      dyn.d_un.d_val = s->size / elemsize;
 	      break;
@@ -3503,21 +3503,22 @@ s7_bfd_score_elf_finish_dynamic_sections (bfd *output_bfd,
      This isn't the case of IRIX rld.  */
   if (sgot != NULL && sgot->size > 0)
     {
-      bfd_put_32 (output_bfd, 0, sgot->contents);
-      bfd_put_32 (output_bfd, 0x80000000, sgot->contents + SCORE_ELF_GOT_SIZE (output_bfd));
+      bfd_put_32 (info->output_bfd, 0, sgot->contents);
+      bfd_put_32 (info->output_bfd, 0x80000000,
+		  sgot->contents + SCORE_ELF_GOT_SIZE (info->output_bfd));
     }
 
   if (sgot != NULL)
     elf_section_data (sgot->output_section)->this_hdr.sh_entsize
-      = SCORE_ELF_GOT_SIZE (output_bfd);
+      = SCORE_ELF_GOT_SIZE (info->output_bfd);
 
 
   /* We need to sort the entries of the dynamic relocation section.  */
   s = score_elf_rel_dyn_section (dynobj, false);
 
-  if (s != NULL && s->size > (bfd_vma)2 * SCORE_ELF_REL_SIZE (output_bfd))
+  if (s != NULL && s->size > (bfd_vma)2 * SCORE_ELF_REL_SIZE (info->output_bfd))
     {
-      reldyn_sorting_bfd = output_bfd;
+      reldyn_sorting_bfd = info->output_bfd;
       qsort ((Elf32_External_Rel *) s->contents + 1, s->reloc_count - 1,
 	     sizeof (Elf32_External_Rel), score_elf_sort_dynamic_relocs);
     }
diff --git a/bfd/elf32-sh.c b/bfd/elf32-sh.c
index ebb36b7228e..8446d13c973 100644
--- a/bfd/elf32-sh.c
+++ b/bfd/elf32-sh.c
@@ -2259,8 +2259,7 @@ sh_elf_link_hash_table_create (bfd *abfd)
 }
 
 static bool
-sh_elf_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
-			    struct bfd_link_info *info, asection *p)
+sh_elf_omit_section_dynsym (struct bfd_link_info *info, asection *p)
 {
   struct elf_sh_link_hash_table *htab = sh_elf_hash_table (info);
 
@@ -2927,14 +2926,13 @@ allocate_dynrelocs (struct elf_link_hash_entry *h, void *inf)
    It's a convenient place to determine the PLT style.  */
 
 static bool
-sh_elf_early_size_sections (bfd *output_bfd, struct bfd_link_info *info)
+sh_elf_early_size_sections (struct bfd_link_info *info)
 {
-  sh_elf_hash_table (info)->plt_info = get_plt_info (output_bfd,
+  sh_elf_hash_table (info)->plt_info = get_plt_info (info->output_bfd,
 						     bfd_link_pic (info));
 
   if (sh_elf_hash_table (info)->fdpic_p && !bfd_link_relocatable (info)
-      && !bfd_elf_stack_segment_size (output_bfd, info,
-				      "__stacksize", DEFAULT_STACK_SIZE))
+      && !bfd_elf_stack_segment_size (info, "__stacksize", DEFAULT_STACK_SIZE))
     return false;
   return true;
 }
@@ -2942,8 +2940,7 @@ sh_elf_early_size_sections (bfd *output_bfd, struct bfd_link_info *info)
 /* Set the sizes of the dynamic sections.  */
 
 static bool
-sh_elf_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-			   struct bfd_link_info *info)
+sh_elf_late_size_sections (struct bfd_link_info *info)
 {
   struct elf_sh_link_hash_table *htab;
   bfd *dynobj;
@@ -3199,8 +3196,7 @@ sh_elf_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
       s->alloced = 1;
     }
 
-  return _bfd_elf_maybe_vxworks_add_dynamic_tags (output_bfd, info,
-						  relocs);
+  return _bfd_elf_maybe_vxworks_add_dynamic_tags (info, relocs);
 }
 
 /* Add a dynamic relocation to the SRELOC section.  */
@@ -3380,7 +3376,7 @@ install_movi20_field (bfd *output_bfd, unsigned long relocation,
 /* Relocate an SH ELF section.  */
 
 static int
-sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
+sh_elf_relocate_section (struct bfd_link_info *info,
 			 bfd *input_bfd, asection *input_section,
 			 bfd_byte *contents, Elf_Internal_Rela *relocs,
 			 Elf_Internal_Sym *local_syms,
@@ -3419,15 +3415,15 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
   sym_hashes = elf_sym_hashes (input_bfd);
   local_got_offsets = elf_local_got_offsets (input_bfd);
 
-  isec_segment = sh_elf_osec_to_segment (output_bfd,
+  isec_segment = sh_elf_osec_to_segment (info->output_bfd,
 					 input_section->output_section);
   if (fdpic_p && sgot)
-    got_segment = sh_elf_osec_to_segment (output_bfd,
+    got_segment = sh_elf_osec_to_segment (info->output_bfd,
 					  sgot->output_section);
   else
     got_segment = -1;
   if (fdpic_p && splt)
-    plt_segment = sh_elf_osec_to_segment (output_bfd,
+    plt_segment = sh_elf_osec_to_segment (info->output_bfd,
 					  splt->output_section);
   else
     plt_segment = -1;
@@ -3487,7 +3483,7 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	  return false;
 	}
 
-      howto = get_howto_table (output_bfd) + r_type;
+      howto = get_howto_table (info->output_bfd) + r_type;
 
       /* For relocs that aren't partial_inplace, we get the addend from
 	 the relocation.  */
@@ -3555,7 +3551,8 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	    }
 	  else if (! howto->partial_inplace)
 	    {
-	      relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	      relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						    sym, &sec, rel);
 	      addend = rel->r_addend;
 	    }
 	  else if ((sec->flags & SEC_MERGE)
@@ -3577,7 +3574,7 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	      addend = bfd_get_32 (input_bfd, contents + rel->r_offset);
 	      msec = sec;
 	      addend =
-		_bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
+		_bfd_elf_rel_local_sym (info->output_bfd, sym, &msec, addend)
 		- relocation;
 	      addend += msec->output_section->vma + msec->output_offset;
 	      bfd_put_32 (input_bfd, addend, contents + rel->r_offset);
@@ -3666,7 +3663,7 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 			      + sec->output_section->vma
 			      + sec->output_offset);
 	      else if (!bfd_link_relocatable (info)
-		       && (_bfd_elf_section_offset (output_bfd, info,
+		       && (_bfd_elf_section_offset (info->output_bfd, info,
 						    input_section,
 						    rel->r_offset)
 			   != (bfd_vma) -1))
@@ -3710,7 +3707,7 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	 the target symbol, but there are some exceptions below.  */
       check_segment[0] = isec_segment;
       if (sec != NULL)
-	check_segment[1] = sh_elf_osec_to_segment (output_bfd,
+	check_segment[1] = sh_elf_osec_to_segment (info->output_bfd,
 						   sec->output_section);
       else
 	check_segment[1] = -1;
@@ -3872,7 +3869,7 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	      relocate = false;
 
 	      outrel.r_offset =
-		_bfd_elf_section_offset (output_bfd, info, input_section,
+		_bfd_elf_section_offset (info->output_bfd, info, input_section,
 					 rel->r_offset);
 	      if (outrel.r_offset == (bfd_vma) -1)
 		skip = true;
@@ -3935,7 +3932,7 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 
 	      loc = sreloc->contents;
 	      loc += sreloc->reloc_count++ * sizeof (Elf32_External_Rela);
-	      bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+	      bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 
 	      check_segment[0] = check_segment[1] = -1;
 
@@ -3954,7 +3951,7 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 
 	      BFD_ASSERT (htab);
 
-		if (sh_elf_osec_readonly_p (output_bfd,
+		if (sh_elf_osec_readonly_p (info->output_bfd,
 					    input_section->output_section))
 		  {
 		    _bfd_error_handler
@@ -3968,10 +3965,10 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		    return false;
 		  }
 
-	      offset = _bfd_elf_section_offset (output_bfd, info,
+	      offset = _bfd_elf_section_offset (info->output_bfd, info,
 						input_section, rel->r_offset);
 	      if (offset != (bfd_vma)-1)
-		sh_elf_add_rofixup (output_bfd, htab->srofixup,
+		sh_elf_add_rofixup (info->output_bfd, htab->srofixup,
 				    input_section->output_section->vma
 				    + input_section->output_offset
 				    + rel->r_offset);
@@ -4057,7 +4054,7 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		    off &= ~1;
 		  else
 		    {
-		      bfd_put_32 (output_bfd, relocation,
+		      bfd_put_32 (info->output_bfd, relocation,
 				  sgot->contents + off);
 		      h->got.offset |= 1;
 
@@ -4067,7 +4064,7 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 			  && sh_elf_hash_entry (h)->got_type == GOT_NORMAL
 			  && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
 			      || h->root.type != bfd_link_hash_undefweak))
-			sh_elf_add_rofixup (output_bfd, htab->srofixup,
+			sh_elf_add_rofixup (info->output_bfd, htab->srofixup,
 					    sgot->output_section->vma
 					    + sgot->output_offset
 					    + off);
@@ -4090,7 +4087,8 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		off &= ~1;
 	      else
 		{
-		  bfd_put_32 (output_bfd, relocation, sgot->contents + off);
+		  bfd_put_32 (info->output_bfd, relocation,
+			      sgot->contents + off);
 
 		  if (bfd_link_pic (info))
 		    {
@@ -4115,12 +4113,12 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 			}
 		      loc = srelgot->contents;
 		      loc += srelgot->reloc_count++ * sizeof (Elf32_External_Rela);
-		      bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+		      bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 		    }
 		  else if (fdpic_p
 			   && (sh_elf_local_got_type (input_bfd) [r_symndx]
 			       == GOT_NORMAL))
-		    sh_elf_add_rofixup (output_bfd, htab->srofixup,
+		    sh_elf_add_rofixup (info->output_bfd, htab->srofixup,
 					sgot->output_section->vma
 					+ sgot->output_offset
 					+ off);
@@ -4137,7 +4135,7 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 
 	  if (r_type == R_SH_GOT20)
 	    {
-	      r = install_movi20_field (output_bfd, relocation + addend,
+	      r = install_movi20_field (info->output_bfd, relocation + addend,
 					input_bfd, input_section, contents,
 					rel->r_offset);
 	      break;
@@ -4165,7 +4163,7 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 
 	  if (r_type == R_SH_GOTOFF20)
 	    {
-	      r = install_movi20_field (output_bfd, relocation + addend,
+	      r = install_movi20_field (info->output_bfd, relocation + addend,
 					input_bfd, input_section, contents,
 					rel->r_offset);
 	      break;
@@ -4319,7 +4317,8 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		    BFD_ASSERT (offset != MINUS_ONE);
 		    if ((offset & 1) == 0)
 		      {
-			if (!sh_elf_initialize_funcdesc (output_bfd, info, h,
+			if (!sh_elf_initialize_funcdesc (info->output_bfd,
+							 info, h,
 							 offset, NULL, 0))
 			  return false;
 			sh_elf_hash_entry (h)->funcdesc.offset |= 1;
@@ -4334,7 +4333,8 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		    BFD_ASSERT (offset != MINUS_ONE);
 		    if ((offset & 1) == 0)
 		      {
-			if (!sh_elf_initialize_funcdesc (output_bfd, info, NULL,
+			if (!sh_elf_initialize_funcdesc (info->output_bfd,
+							 info, NULL,
 							 offset, sec,
 							 sym->st_value))
 			  return false;
@@ -4349,7 +4349,7 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	      {
 		bfd_vma offset;
 
-		if (sh_elf_osec_readonly_p (output_bfd,
+		if (sh_elf_osec_readonly_p (info->output_bfd,
 					    reloc_section->output_section))
 		  {
 		    _bfd_error_handler
@@ -4363,11 +4363,11 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		    return false;
 		  }
 
-		offset = _bfd_elf_section_offset (output_bfd, info,
+		offset = _bfd_elf_section_offset (info->output_bfd, info,
 						  reloc_section, reloc_offset);
 
 		if (offset != (bfd_vma)-1)
-		  sh_elf_add_rofixup (output_bfd, htab->srofixup,
+		  sh_elf_add_rofixup (info->output_bfd, htab->srofixup,
 				      offset
 				      + reloc_section->output_section->vma
 				      + reloc_section->output_offset);
@@ -4377,7 +4377,7 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	      {
 		bfd_vma offset;
 
-		if (sh_elf_osec_readonly_p (output_bfd,
+		if (sh_elf_osec_readonly_p (info->output_bfd,
 					    reloc_section->output_section))
 		  {
 		    info->callbacks->warning
@@ -4387,11 +4387,11 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		    return false;
 		  }
 
-		offset = _bfd_elf_section_offset (output_bfd, info,
+		offset = _bfd_elf_section_offset (info->output_bfd, info,
 						  reloc_section, reloc_offset);
 
 		if (offset != (bfd_vma)-1)
-		  sh_elf_add_dyn_reloc (output_bfd, srelgot,
+		  sh_elf_add_dyn_reloc (info->output_bfd, srelgot,
 					offset
 					+ reloc_section->output_section->vma
 					+ reloc_section->output_offset,
@@ -4414,7 +4414,7 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	  funcdesc_leave_zero:
 	    if (r_type != R_SH_FUNCDESC)
 	      {
-		bfd_put_32 (output_bfd, relocation,
+		bfd_put_32 (info->output_bfd, relocation,
 			    reloc_section->contents + reloc_offset);
 		if (h != NULL)
 		  h->got.offset |= 1;
@@ -4430,7 +4430,7 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	      }
 	    if (r_type == R_SH_GOTFUNCDESC20)
 	      {
-		r = install_movi20_field (output_bfd, relocation + addend,
+		r = install_movi20_field (info->output_bfd, relocation + addend,
 					  input_bfd, input_section, contents,
 					  rel->r_offset);
 		break;
@@ -4475,7 +4475,8 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		  BFD_ASSERT (offset != MINUS_ONE);
 		  if ((offset & 1) == 0)
 		    {
-		      if (!sh_elf_initialize_funcdesc (output_bfd, info, h,
+		      if (!sh_elf_initialize_funcdesc (info->output_bfd,
+						       info, h,
 						       offset, NULL, 0))
 			return false;
 		      sh_elf_hash_entry (h)->funcdesc.offset |= 1;
@@ -4490,7 +4491,8 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		  BFD_ASSERT (offset != MINUS_ONE);
 		  if ((offset & 1) == 0)
 		    {
-		      if (!sh_elf_initialize_funcdesc (output_bfd, info, NULL,
+		      if (!sh_elf_initialize_funcdesc (info->output_bfd,
+						       info, NULL,
 						       offset, sec,
 						       sym->st_value))
 			return false;
@@ -4509,7 +4511,7 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 
 	  if (r_type == R_SH_GOTOFFFUNCDESC20)
 	    {
-	      r = install_movi20_field (output_bfd, relocation + addend,
+	      r = install_movi20_field (info->output_bfd, relocation + addend,
 					input_bfd, input_section, contents,
 					rel->r_offset);
 	      break;
@@ -4633,11 +4635,11 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		      (_("%pB(%pA+%#" PRIx64 "): unexpected instruction %#04X (expected 0x34cc)"),
 		       input_bfd, input_section, (uint64_t) offset, (int) insn);
 
-		  bfd_put_16 (output_bfd, 0x0012, contents + offset + 2);
-		  bfd_put_16 (output_bfd, 0x304c, contents + offset + 4);
-		  bfd_put_16 (output_bfd, 0x0009, contents + offset + 6);
-		  bfd_put_16 (output_bfd, 0x0009, contents + offset + 8);
-		  bfd_put_16 (output_bfd, 0x0009, contents + offset + 10);
+		  bfd_put_16 (info->output_bfd, 0x0012, contents + offset + 2);
+		  bfd_put_16 (info->output_bfd, 0x304c, contents + offset + 4);
+		  bfd_put_16 (info->output_bfd, 0x0009, contents + offset + 6);
+		  bfd_put_16 (info->output_bfd, 0x0009, contents + offset + 8);
+		  bfd_put_16 (info->output_bfd, 0x0009, contents + offset + 10);
 		}
 	      else
 		{
@@ -4703,11 +4705,11 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		       input_bfd, input_section, (uint64_t) (offset + 4), (int) insn);
 
 		  insn = 0xd000 | (insn & 0x0f00) | target;
-		  bfd_put_16 (output_bfd, insn, contents + offset + 0);
-		  bfd_put_16 (output_bfd, 0x0009, contents + offset + 4);
+		  bfd_put_16 (info->output_bfd, insn, contents + offset + 0);
+		  bfd_put_16 (info->output_bfd, 0x0009, contents + offset + 4);
 		}
 
-	      bfd_put_32 (output_bfd, tpoff (info, relocation),
+	      bfd_put_32 (info->output_bfd, tpoff (info, relocation),
 			  contents + rel->r_offset);
 	      continue;
 	    }
@@ -4730,9 +4732,9 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	      && ! htab->root.dynamic_sections_created)
 	    {
 	      off &= ~1;
-	      bfd_put_32 (output_bfd, tpoff (info, relocation),
+	      bfd_put_32 (info->output_bfd, tpoff (info, relocation),
 			  sgot->contents + off);
-	      bfd_put_32 (output_bfd, sh_elf_got_offset (htab) + off,
+	      bfd_put_32 (info->output_bfd, sh_elf_got_offset (htab) + off,
 			  contents + rel->r_offset);
 	      continue;
 	    }
@@ -4762,13 +4764,13 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	      outrel.r_info = ELF32_R_INFO (indx, dr_type);
 	      loc = srelgot->contents;
 	      loc += srelgot->reloc_count++ * sizeof (Elf32_External_Rela);
-	      bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+	      bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 
 	      if (r_type == R_SH_TLS_GD_32)
 		{
 		  if (indx == 0)
 		    {
-		      bfd_put_32 (output_bfd,
+		      bfd_put_32 (info->output_bfd,
 				  relocation - dtpoff_base (info),
 				  sgot->contents + off + 4);
 		    }
@@ -4780,7 +4782,7 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		      outrel.r_addend = 0;
 		      srelgot->reloc_count++;
 		      loc += sizeof (Elf32_External_Rela);
-		      bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+		      bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 		    }
 		}
 
@@ -4832,7 +4834,7 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	      BFD_ASSERT ((insn & 0xff00) == 0xd400);
 
 	      /* Replace mov.l 1f,R4 with mov.l 1f,r0.  */
-	      bfd_put_16 (output_bfd, insn & 0xf0ff, contents + offset);
+	      bfd_put_16 (info->output_bfd, insn & 0xf0ff, contents + offset);
 
 	      insn = bfd_get_16 (input_bfd, contents + offset + 2);
 	      BFD_ASSERT ((insn & 0xff00) == 0xc700);
@@ -4845,13 +4847,13 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	      insn = bfd_get_16 (input_bfd, contents + offset + 10);
 	      BFD_ASSERT (insn == 0x34cc);
 
-	      bfd_put_16 (output_bfd, 0x0412, contents + offset + 2);
-	      bfd_put_16 (output_bfd, 0x00ce, contents + offset + 4);
-	      bfd_put_16 (output_bfd, 0x304c, contents + offset + 6);
-	      bfd_put_16 (output_bfd, 0x0009, contents + offset + 8);
-	      bfd_put_16 (output_bfd, 0x0009, contents + offset + 10);
+	      bfd_put_16 (info->output_bfd, 0x0412, contents + offset + 2);
+	      bfd_put_16 (info->output_bfd, 0x00ce, contents + offset + 4);
+	      bfd_put_16 (info->output_bfd, 0x304c, contents + offset + 6);
+	      bfd_put_16 (info->output_bfd, 0x0009, contents + offset + 8);
+	      bfd_put_16 (info->output_bfd, 0x0009, contents + offset + 10);
 
-	      bfd_put_32 (output_bfd, sh_elf_got_offset (htab) + off,
+	      bfd_put_32 (info->output_bfd, sh_elf_got_offset (htab) + off,
 			  contents + rel->r_offset);
 
 	      continue;
@@ -4909,12 +4911,12 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	      insn = bfd_get_16 (input_bfd, contents + offset + 10);
 	      BFD_ASSERT (insn == 0x34cc);
 
-	      bfd_put_16 (output_bfd, 0x0012, contents + offset + 0);
-	      bfd_put_16 (output_bfd, 0x0009, contents + offset + 2);
-	      bfd_put_16 (output_bfd, 0x0009, contents + offset + 4);
-	      bfd_put_16 (output_bfd, 0x0009, contents + offset + 6);
-	      bfd_put_16 (output_bfd, 0x0009, contents + offset + 8);
-	      bfd_put_16 (output_bfd, 0x0009, contents + offset + 10);
+	      bfd_put_16 (info->output_bfd, 0x0012, contents + offset + 0);
+	      bfd_put_16 (info->output_bfd, 0x0009, contents + offset + 2);
+	      bfd_put_16 (info->output_bfd, 0x0009, contents + offset + 4);
+	      bfd_put_16 (info->output_bfd, 0x0009, contents + offset + 6);
+	      bfd_put_16 (info->output_bfd, 0x0009, contents + offset + 8);
+	      bfd_put_16 (info->output_bfd, 0x0009, contents + offset + 10);
 
 	      continue;
 	    }
@@ -4936,7 +4938,7 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	      outrel.r_info = ELF32_R_INFO (0, R_SH_TLS_DTPMOD32);
 	      loc = srelgot->contents;
 	      loc += srelgot->reloc_count++ * sizeof (Elf32_External_Rela);
-	      bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+	      bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 	      htab->tls_ldm_got.offset |= 1;
 	    }
 
@@ -4990,7 +4992,7 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 
 	    loc = sreloc->contents;
 	    loc += sreloc->reloc_count++ * sizeof (Elf32_External_Rela);
-	    bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+	    bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 	    continue;
 	  }
 	}
@@ -5017,7 +5019,7 @@ sh_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		   input_bfd, input_section, rel->r_offset, symname);
 	    }
 
-	  elf_elfheader (output_bfd)->e_flags |= EF_SH_PIC;
+	  elf_elfheader (info->output_bfd)->e_flags |= EF_SH_PIC;
 	}
 
       if (r != bfd_reloc_ok)
@@ -5140,7 +5142,7 @@ sh_elf_get_relocated_section_contents (bfd *output_bfd,
 	  *secpp = isec;
 	}
 
-      if (! sh_elf_relocate_section (output_bfd, link_info, input_bfd,
+      if (! sh_elf_relocate_section (link_info, input_bfd,
 				     input_section, data, internal_relocs,
 				     isymbuf, sections))
 	goto error_return;
@@ -5934,7 +5936,7 @@ sh_elf_object_p (bfd *abfd)
    dynamic sections here.  */
 
 static bool
-sh_elf_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
+sh_elf_finish_dynamic_symbol (struct bfd_link_info *info,
 			      struct elf_link_hash_entry *h,
 			      Elf_Internal_Sym *sym)
 {
@@ -6001,14 +6003,14 @@ sh_elf_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
 	  if (plt_info->symbol_fields.got20)
 	    {
 	      bfd_reloc_status_type r;
-	      r = install_movi20_field (output_bfd, got_offset,
+	      r = install_movi20_field (info->output_bfd, got_offset,
 					splt->owner, splt, splt->contents,
 					h->plt.offset
 					+ plt_info->symbol_fields.got_entry);
 	      BFD_ASSERT (r == bfd_reloc_ok);
 	    }
 	  else
-	    install_plt_field (output_bfd, false, got_offset,
+	    install_plt_field (info->output_bfd, false, got_offset,
 			       (splt->contents
 				+ h->plt.offset
 				+ plt_info->symbol_fields.got_entry));
@@ -6017,7 +6019,7 @@ sh_elf_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
 	{
 	  BFD_ASSERT (!plt_info->symbol_fields.got20);
 
-	  install_plt_field (output_bfd, false,
+	  install_plt_field (info->output_bfd, false,
 			     (sgotplt->output_section->vma
 			      + sgotplt->output_offset
 			      + got_offset),
@@ -6049,14 +6051,14 @@ sh_elf_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
 			     * plt_info->symbol_entry_size);
 
 	      /* Install the 'bra' with this offset.  */
-	      bfd_put_16 (output_bfd,
+	      bfd_put_16 (info->output_bfd,
 			  0xa000 | (0x0fff & ((distance - 4) / 2)),
 			  (splt->contents
 			   + h->plt.offset
 			   + plt_info->symbol_fields.plt));
 	    }
 	  else
-	    install_plt_field (output_bfd, true,
+	    install_plt_field (info->output_bfd, true,
 			       splt->output_section->vma + splt->output_offset,
 			       (splt->contents
 				+ h->plt.offset
@@ -6072,22 +6074,23 @@ sh_elf_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
 	got_offset = plt_index * 8;
 
       if (plt_info->symbol_fields.reloc_offset != MINUS_ONE)
-	install_plt_field (output_bfd, false,
+	install_plt_field (info->output_bfd, false,
 			   plt_index * sizeof (Elf32_External_Rela),
 			   (splt->contents
 			    + h->plt.offset
 			    + plt_info->symbol_fields.reloc_offset));
 
       /* Fill in the entry in the global offset table.  */
-      bfd_put_32 (output_bfd,
+      bfd_put_32 (info->output_bfd,
 		  (splt->output_section->vma
 		   + splt->output_offset
 		   + h->plt.offset
 		   + plt_info->symbol_resolve_offset),
 		  sgotplt->contents + got_offset);
       if (htab->fdpic_p)
-	bfd_put_32 (output_bfd,
-		    sh_elf_osec_to_segment (output_bfd, splt->output_section),
+	bfd_put_32 (info->output_bfd,
+		    sh_elf_osec_to_segment (info->output_bfd,
+					    splt->output_section),
 		    sgotplt->contents + got_offset + 4);
 
       /* Fill in the entry in the .rela.plt section.  */
@@ -6103,7 +6106,7 @@ sh_elf_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
       rel.r_addend = GOT_BIAS;
 #endif
       loc = srelplt->contents + plt_index * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rel, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rel, loc);
 
       if (htab->root.target_os == is_vxworks && !bfd_link_pic (info))
 	{
@@ -6120,7 +6123,7 @@ sh_elf_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
 			  + plt_info->symbol_fields.got_entry);
 	  rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_SH_DIR32);
 	  rel.r_addend = got_offset;
-	  bfd_elf32_swap_reloca_out (output_bfd, &rel, loc);
+	  bfd_elf32_swap_reloca_out (info->output_bfd, &rel, loc);
 	  loc += sizeof (Elf32_External_Rela);
 
 	  /* Create a .rela.plt.unloaded R_SH_DIR32 relocation for
@@ -6130,7 +6133,7 @@ sh_elf_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
 			  + got_offset);
 	  rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_SH_DIR32);
 	  rel.r_addend = 0;
-	  bfd_elf32_swap_reloc_out (output_bfd, &rel, loc);
+	  bfd_elf32_swap_reloc_out (info->output_bfd, &rel, loc);
 	}
 
       if (!h->def_regular)
@@ -6192,14 +6195,14 @@ sh_elf_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
 	}
       else
 	{
-	  bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + h->got.offset);
+	  bfd_put_32 (info->output_bfd, 0, sgot->contents + h->got.offset);
 	  rel.r_info = ELF32_R_INFO (h->dynindx, R_SH_GLOB_DAT);
 	  rel.r_addend = 0;
 	}
 
       loc = srelgot->contents;
       loc += srelgot->reloc_count++ * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rel, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rel, loc);
     }
 
   if (h->needs_copy)
@@ -6223,7 +6226,7 @@ sh_elf_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
       rel.r_info = ELF32_R_INFO (h->dynindx, R_SH_COPY);
       rel.r_addend = 0;
       loc = s->contents + s->reloc_count++ * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rel, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rel, loc);
     }
 
   /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute.  On VxWorks,
@@ -6239,7 +6242,7 @@ sh_elf_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
 /* Finish up the dynamic sections.  */
 
 static bool
-sh_elf_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
+sh_elf_finish_dynamic_sections (struct bfd_link_info *info,
 				bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   struct elf_sh_link_hash_table *htab;
@@ -6274,8 +6277,8 @@ sh_elf_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
 	    default:
 #ifdef OBJ_MAYBE_ELF_VXWORKS
 	      if (htab->root.target_os == is_vxworks
-		  && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
-		bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+		  && elf_vxworks_finish_dynamic_entry (info->output_bfd, &dyn))
+		bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 #endif /* OBJ_MAYBE_ELF_VXWORKS */
 	      break;
 
@@ -6284,19 +6287,19 @@ sh_elf_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
 	      s = htab->root.hgot->root.u.def.section;
 	      dyn.d_un.d_ptr = htab->root.hgot->root.u.def.value
 		+ s->output_section->vma + s->output_offset;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    case DT_JMPREL:
 	      s = htab->root.srelplt;
 	      dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    case DT_PLTRELSZ:
 	      s = htab->root.srelplt;
 	      dyn.d_un.d_val = s->size;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 	    }
 	}
@@ -6312,7 +6315,7 @@ sh_elf_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
 		  htab->plt_info->plt0_entry_size);
 	  for (i = 0; i < ARRAY_SIZE (htab->plt_info->plt0_got_fields); i++)
 	    if (htab->plt_info->plt0_got_fields[i] != MINUS_ONE)
-	      install_plt_field (output_bfd, false,
+	      install_plt_field (info->output_bfd, false,
 				 (sgotplt->output_section->vma
 				  + sgotplt->output_offset
 				  + (i * 4)),
@@ -6333,7 +6336,7 @@ sh_elf_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
 			      + htab->plt_info->plt0_got_fields[2]);
 	      rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_SH_DIR32);
 	      rel.r_addend = 8;
-	      bfd_elf32_swap_reloca_out (output_bfd, &rel, loc);
+	      bfd_elf32_swap_reloca_out (info->output_bfd, &rel, loc);
 	      loc += sizeof (Elf32_External_Rela);
 
 	      /* Fix up the remaining .rela.plt.unloaded relocations.
@@ -6343,17 +6346,17 @@ sh_elf_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
 	      while (loc < htab->srelplt2->contents + htab->srelplt2->size)
 		{
 		  /* The PLT entry's pointer to the .got.plt slot.  */
-		  bfd_elf32_swap_reloc_in (output_bfd, loc, &rel);
+		  bfd_elf32_swap_reloc_in (info->output_bfd, loc, &rel);
 		  rel.r_info = ELF32_R_INFO (htab->root.hgot->indx,
 					     R_SH_DIR32);
-		  bfd_elf32_swap_reloc_out (output_bfd, &rel, loc);
+		  bfd_elf32_swap_reloc_out (info->output_bfd, &rel, loc);
 		  loc += sizeof (Elf32_External_Rela);
 
 		  /* The .got.plt slot's pointer to .plt.  */
-		  bfd_elf32_swap_reloc_in (output_bfd, loc, &rel);
+		  bfd_elf32_swap_reloc_in (info->output_bfd, loc, &rel);
 		  rel.r_info = ELF32_R_INFO (htab->root.hplt->indx,
 					     R_SH_DIR32);
-		  bfd_elf32_swap_reloc_out (output_bfd, &rel, loc);
+		  bfd_elf32_swap_reloc_out (info->output_bfd, &rel, loc);
 		  loc += sizeof (Elf32_External_Rela);
 		}
 	    }
@@ -6368,13 +6371,13 @@ sh_elf_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
   if (sgotplt && sgotplt->size > 0 && !htab->fdpic_p)
     {
       if (sdyn == NULL)
-	bfd_put_32 (output_bfd, (bfd_vma) 0, sgotplt->contents);
+	bfd_put_32 (info->output_bfd, 0, sgotplt->contents);
       else
-	bfd_put_32 (output_bfd,
+	bfd_put_32 (info->output_bfd,
 		    sdyn->output_section->vma + sdyn->output_offset,
 		    sgotplt->contents);
-      bfd_put_32 (output_bfd, (bfd_vma) 0, sgotplt->contents + 4);
-      bfd_put_32 (output_bfd, (bfd_vma) 0, sgotplt->contents + 8);
+      bfd_put_32 (info->output_bfd, 0, sgotplt->contents + 4);
+      bfd_put_32 (info->output_bfd, 0, sgotplt->contents + 8);
     }
 
   if (sgotplt && sgotplt->size > 0)
@@ -6388,7 +6391,7 @@ sh_elf_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
 	+ hgot->root.u.def.section->output_section->vma
 	+ hgot->root.u.def.section->output_offset;
 
-      sh_elf_add_rofixup (output_bfd, htab->srofixup, got_value);
+      sh_elf_add_rofixup (info->output_bfd, htab->srofixup, got_value);
 
       /* Make sure we allocated and generated the same number of fixups.  */
       BFD_ASSERT (htab->srofixup->reloc_count * 4 == htab->srofixup->size);
diff --git a/bfd/elf32-spu.c b/bfd/elf32-spu.c
index 9a9d3a0401c..e0e74b781ff 100644
--- a/bfd/elf32-spu.c
+++ b/bfd/elf32-spu.c
@@ -4823,8 +4823,7 @@ spu_elf_emit_fixup (bfd * output_bfd, struct bfd_link_info *info,
 /* Apply RELOCS to CONTENTS of INPUT_SECTION from INPUT_BFD.  */
 
 static int
-spu_elf_relocate_section (bfd *output_bfd,
-			  struct bfd_link_info *info,
+spu_elf_relocate_section (struct bfd_link_info *info,
 			  bfd *input_bfd,
 			  asection *input_section,
 			  bfd_byte *contents,
@@ -4847,7 +4846,7 @@ spu_elf_relocate_section (bfd *output_bfd,
   stubs = (htab->stub_sec != NULL
 	   && maybe_needs_stubs (input_section));
   iovl = overlay_index (input_section);
-  ea = bfd_get_section_by_name (output_bfd, "._ea");
+  ea = bfd_get_section_by_name (info->output_bfd, "._ea");
   symtab_hdr = &elf_symtab_hdr (input_bfd);
   sym_hashes = (struct elf_link_hash_entry **) (elf_sym_hashes (input_bfd));
 
@@ -4880,7 +4879,8 @@ spu_elf_relocate_section (bfd *output_bfd,
 	  sym = local_syms + r_symndx;
 	  sec = local_sections[r_symndx];
 	  sym_name = bfd_elf_sym_name (input_bfd, symtab_hdr, sym, sec);
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 	}
       else
 	{
@@ -5016,7 +5016,7 @@ spu_elf_relocate_section (bfd *output_bfd,
 	  bfd_vma offset;
 	  offset = rel->r_offset + input_section->output_section->vma
 		   + input_section->output_offset;
-	  spu_elf_emit_fixup (output_bfd, info, offset);
+	  spu_elf_emit_fixup (info->output_bfd, info, offset);
 	}
 
       if (unresolved_reloc)
@@ -5043,7 +5043,7 @@ spu_elf_relocate_section (bfd *output_bfd,
 	unresolved_reloc = true;
 
       if (unresolved_reloc
-	  && _bfd_elf_section_offset (output_bfd, info, input_section,
+	  && _bfd_elf_section_offset (info->output_bfd, info, input_section,
 				      rel->r_offset) != (bfd_vma) -1)
 	{
 	  _bfd_error_handler
@@ -5134,8 +5134,7 @@ spu_elf_relocate_section (bfd *output_bfd,
 }
 
 static bool
-spu_elf_finish_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-				 struct bfd_link_info *info ATTRIBUTE_UNUSED,
+spu_elf_finish_dynamic_sections (struct bfd_link_info *info ATTRIBUTE_UNUSED,
 				 bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   return true;
diff --git a/bfd/elf32-tic6x.c b/bfd/elf32-tic6x.c
index d5f1259d1f4..a74e8235f32 100644
--- a/bfd/elf32-tic6x.c
+++ b/bfd/elf32-tic6x.c
@@ -1705,8 +1705,7 @@ elf32_tic6x_make_got_dynreloc (bfd *output_bfd,
    dynamic sections here.  */
 
 static bool
-elf32_tic6x_finish_dynamic_symbol (bfd * output_bfd,
-				   struct bfd_link_info *info,
+elf32_tic6x_finish_dynamic_symbol (struct bfd_link_info *info,
 				   struct elf_link_hash_entry *h,
 				   Elf_Internal_Sym * sym)
 {
@@ -1723,7 +1722,7 @@ elf32_tic6x_finish_dynamic_symbol (bfd * output_bfd,
       asection *plt, *gotplt, *relplt;
       elf_backend_data *bed;
 
-      bed = get_elf_backend_data (output_bfd);
+      bed = get_elf_backend_data (info->output_bfd);
 
       BFD_ASSERT (htab->elf.splt != NULL);
       plt = htab->elf.splt;
@@ -1763,26 +1762,27 @@ elf32_tic6x_finish_dynamic_symbol (bfd * output_bfd,
       /* Fill in the entry in the procedure linkage table.  */
 
       /* ldw .d2t2 *+B14($GOT(f)), b2 */
-      bfd_put_32 (output_bfd, got_dp_offset << 8 | 0x0100006e,
+      bfd_put_32 (info->output_bfd, got_dp_offset << 8 | 0x0100006e,
 		  plt->contents + h->plt.offset);
       /* mvk .s2 low(rela_offset), b0 */
-      bfd_put_32 (output_bfd, (rela_offset & 0xffff) << 7 | 0x0000002a,
+      bfd_put_32 (info->output_bfd, (rela_offset & 0xffff) << 7 | 0x0000002a,
 		  plt->contents + h->plt.offset + 4);
       /* mvkh .s2 high(rela_offset), b0 */
-      bfd_put_32 (output_bfd, ((rela_offset >> 16) & 0xffff) << 7 | 0x0000006a,
+      bfd_put_32 (info->output_bfd,
+		  ((rela_offset >> 16) & 0xffff) << 7 | 0x0000006a,
 		  plt->contents + h->plt.offset + 8);
       /* nop 2 */
-      bfd_put_32 (output_bfd, 0x00002000,
+      bfd_put_32 (info->output_bfd, 0x00002000,
 		  plt->contents + h->plt.offset + 12);
       /* b .s2 b2 */
-      bfd_put_32 (output_bfd, 0x00080362,
+      bfd_put_32 (info->output_bfd, 0x00080362,
 		  plt->contents + h->plt.offset + 16);
       /* nop 5 */
-      bfd_put_32 (output_bfd, 0x00008000,
+      bfd_put_32 (info->output_bfd, 0x00008000,
 		  plt->contents + h->plt.offset + 20);
 
       /* Fill in the entry in the global offset table.  */
-      bfd_put_32 (output_bfd,
+      bfd_put_32 (info->output_bfd,
 		  (plt->output_section->vma + plt->output_offset),
 		  gotplt->contents + got_section_offset);
 
@@ -1793,7 +1793,7 @@ elf32_tic6x_finish_dynamic_symbol (bfd * output_bfd,
       rela.r_info = ELF32_R_INFO (h->dynindx, R_C6000_JUMP_SLOT);
       rela.r_addend = 0;
       loc = relplt->contents + rela_offset;
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
 
       if (!h->def_regular)
 	{
@@ -1826,13 +1826,13 @@ elf32_tic6x_finish_dynamic_symbol (bfd * output_bfd,
 	      || h->dynindx == -1 || h->forced_local) && h->def_regular)
 	{
 	  asection *s = h->root.u.def.section;
-	  elf32_tic6x_make_got_dynreloc (output_bfd, htab, s,
+	  elf32_tic6x_make_got_dynreloc (info->output_bfd, htab, s,
 			     h->got.offset & ~(bfd_vma) 1);
 	}
       else
 	{
 	  Elf_Internal_Rela outrel;
-	  bfd_put_32 (output_bfd, (bfd_vma) 0,
+	  bfd_put_32 (info->output_bfd, 0,
 		      sgot->contents + (h->got.offset & ~(bfd_vma) 1));
 	  outrel.r_offset = (sgot->output_section->vma
 			   + sgot->output_offset
@@ -1840,7 +1840,7 @@ elf32_tic6x_finish_dynamic_symbol (bfd * output_bfd,
 	  outrel.r_info = ELF32_R_INFO (h->dynindx, R_C6000_ABS32);
 	  outrel.r_addend = 0;
 
-	  elf32_tic6x_install_rela (output_bfd, srela, &outrel);
+	  elf32_tic6x_install_rela (info->output_bfd, srela, &outrel);
 	}
     }
 
@@ -1868,7 +1868,7 @@ elf32_tic6x_finish_dynamic_symbol (bfd * output_bfd,
       else
 	s = htab->elf.srelbss;
 
-      elf32_tic6x_install_rela (output_bfd, s, &rel);
+      elf32_tic6x_install_rela (info->output_bfd, s, &rel);
     }
 
   /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute.  */
@@ -2116,8 +2116,7 @@ elf32_tic6x_rel_relocation_p (bfd *abfd, asection *sec,
 /* We need dynamic symbols for every section, since segments can
    relocate independently.  */
 static bool
-elf32_tic6x_link_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
-				      struct bfd_link_info *info ATTRIBUTE_UNUSED,
+elf32_tic6x_link_omit_section_dynsym (struct bfd_link_info *info ATTRIBUTE_UNUSED,
 				      asection *p)
 {
   switch (elf_section_data (p)->this_hdr.sh_type)
@@ -2137,8 +2136,7 @@ elf32_tic6x_link_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
 }
 
 static int
-elf32_tic6x_relocate_section (bfd *output_bfd,
-			      struct bfd_link_info *info,
+elf32_tic6x_relocate_section (struct bfd_link_info *info,
 			      bfd *input_bfd,
 			      asection *input_section,
 			      bfd_byte *contents,
@@ -2203,7 +2201,8 @@ elf32_tic6x_relocate_section (bfd *output_bfd,
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections[r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 	}
       else
 	{
@@ -2316,7 +2315,8 @@ elf32_tic6x_relocate_section (bfd *output_bfd,
 	  /* When generating a shared object or relocatable executable, these
 	     relocations are copied into the output file to be resolved at
 	     run time.  */
-	  if ((bfd_link_pic (info) || elf32_tic6x_using_dsbt (output_bfd))
+	  if ((bfd_link_pic (info)
+	       || elf32_tic6x_using_dsbt (info->output_bfd))
 	      && (input_section->flags & SEC_ALLOC)
 	      && (h == NULL
 		  || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
@@ -2335,8 +2335,8 @@ elf32_tic6x_relocate_section (bfd *output_bfd,
 	      relocate = false;
 
 	      outrel.r_offset =
-		_bfd_elf_section_offset (output_bfd, info, input_section,
-					 rel->r_offset);
+		_bfd_elf_section_offset (info->output_bfd, info,
+					 input_section, rel->r_offset);
 	      if (outrel.r_offset == (bfd_vma) -1)
 		skip = true;
 	      else if (outrel.r_offset == (bfd_vma) -2)
@@ -2381,7 +2381,7 @@ elf32_tic6x_relocate_section (bfd *output_bfd,
 		  outrel.r_info = ELF32_R_INFO (indx, r_type);
 		}
 
-	      elf32_tic6x_install_rela (output_bfd, sreloc, &outrel);
+	      elf32_tic6x_install_rela (info->output_bfd, sreloc, &outrel);
 
 	      /* If this reloc is against an external symbol, we do not want to
 		 fiddle with the addend.  Otherwise, we need to include the symbol
@@ -2468,7 +2468,7 @@ elf32_tic6x_relocate_section (bfd *output_bfd,
 		    off &= ~1;
 		  else
 		    {
-		      bfd_put_32 (output_bfd, relocation,
+		      bfd_put_32 (info->output_bfd, relocation,
 				  htab->elf.sgot->contents + off);
 		      h->got.offset |= 1;
 
@@ -2477,8 +2477,8 @@ elf32_tic6x_relocate_section (bfd *output_bfd,
 							    h)
 			  && !(ELF_ST_VISIBILITY (h->other)
 			       && h->root.type == bfd_link_hash_undefweak))
-			elf32_tic6x_make_got_dynreloc (output_bfd, htab, sec,
-						       off);
+			elf32_tic6x_make_got_dynreloc (info->output_bfd,
+						       htab, sec, off);
 		    }
 		}
 	      else
@@ -2498,11 +2498,13 @@ elf32_tic6x_relocate_section (bfd *output_bfd,
 		off &= ~1;
 	      else
 		{
-		  bfd_put_32 (output_bfd, relocation,
+		  bfd_put_32 (info->output_bfd, relocation,
 			      htab->elf.sgot->contents + off);
 
-		  if (bfd_link_pic (info) || elf32_tic6x_using_dsbt (output_bfd))
-		    elf32_tic6x_make_got_dynreloc (output_bfd, htab, sec, off);
+		  if (bfd_link_pic (info)
+		      || elf32_tic6x_using_dsbt (info->output_bfd))
+		    elf32_tic6x_make_got_dynreloc (info->output_bfd,
+						   htab, sec, off);
 
 		  local_got_offsets[r_symndx] |= 1;
 		}
@@ -3150,7 +3152,7 @@ elf32_tic6x_allocate_dynrelocs (struct elf_link_hash_entry *h, void *inf)
 /* Set the sizes of the dynamic sections.  */
 
 static bool
-elf32_tic6x_late_size_sections (bfd *output_bfd, struct bfd_link_info *info)
+elf32_tic6x_late_size_sections (struct bfd_link_info *info)
 {
   struct elf32_tic6x_link_hash_table *htab;
   bfd *dynobj;
@@ -3230,7 +3232,8 @@ elf32_tic6x_late_size_sections (bfd *output_bfd, struct bfd_link_info *info)
 	      *local_got = s->size;
 	      s->size += 4;
 
-	      if (bfd_link_pic (info) || elf32_tic6x_using_dsbt (output_bfd))
+	      if (bfd_link_pic (info)
+		  || elf32_tic6x_using_dsbt (info->output_bfd))
 		{
 		  srel->size += sizeof (Elf32_External_Rela);
 		}
@@ -3331,7 +3334,7 @@ elf32_tic6x_late_size_sections (bfd *output_bfd, struct bfd_link_info *info)
 #define add_dynamic_entry(TAG, VAL) \
   _bfd_elf_add_dynamic_entry (info, TAG, VAL)
 
-      if (!_bfd_elf_add_dynamic_tags (output_bfd, info, relocs))
+      if (!_bfd_elf_add_dynamic_tags (info, relocs))
 	return false;
 
       if (!add_dynamic_entry (DT_C6000_DSBT_BASE, 0)
@@ -3350,19 +3353,17 @@ elf32_tic6x_late_size_sections (bfd *output_bfd, struct bfd_link_info *info)
    and the input sections have been assigned to output sections.  */
 
 static bool
-elf32_tic6x_early_size_sections (bfd *output_bfd, struct bfd_link_info *info)
+elf32_tic6x_early_size_sections (struct bfd_link_info *info)
 {
-  if (elf32_tic6x_using_dsbt (output_bfd) && !bfd_link_relocatable (info)
-      && !bfd_elf_stack_segment_size (output_bfd, info,
-				      "__stacksize", DEFAULT_STACK_SIZE))
+  if (elf32_tic6x_using_dsbt (info->output_bfd) && !bfd_link_relocatable (info)
+      && !bfd_elf_stack_segment_size (info, "__stacksize", DEFAULT_STACK_SIZE))
     return false;
 
   return true;
 }
 
 static bool
-elf32_tic6x_finish_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-				     struct bfd_link_info *info,
+elf32_tic6x_finish_dynamic_sections (struct bfd_link_info *info,
 				     bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   struct elf32_tic6x_link_hash_table *htab;
@@ -3415,7 +3416,7 @@ elf32_tic6x_finish_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
 	      dyn.d_un.d_val = s->size;
 	      break;
 	    }
-	  bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	  bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	}
 
       /* Fill in the first entry in the procedure linkage table.  */
@@ -3427,19 +3428,19 @@ elf32_tic6x_finish_dynamic_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
 			      - htab->dsbt->output_offset) / 4;
 
 	  /* ldw .D2T2 *+b14[$GOT(0)],b2 */
-	  bfd_put_32 (output_bfd, got_offs << 8 | 0x0100006e,
+	  bfd_put_32 (info->output_bfd, got_offs << 8 | 0x0100006e,
 		      htab->elf.splt->contents);
 	  /* ldw .D2T2 *+b14[$GOT(4)],b1 */
-	  bfd_put_32 (output_bfd, (got_offs + 1) << 8 | 0x0080006e,
+	  bfd_put_32 (info->output_bfd, (got_offs + 1) << 8 | 0x0080006e,
 		      htab->elf.splt->contents + 4);
 	  /* nop 3 */
-	  bfd_put_32 (output_bfd, 0x00004000,
+	  bfd_put_32 (info->output_bfd, 0x00004000,
 		      htab->elf.splt->contents + 8);
 	  /* b .s2 b2 */
-	  bfd_put_32 (output_bfd, 0x00080362,
+	  bfd_put_32 (info->output_bfd, 0x00080362,
 		      htab->elf.splt->contents + 12);
 	  /* nop 5 */
-	  bfd_put_32 (output_bfd, 0x00008000,
+	  bfd_put_32 (info->output_bfd, 0x00008000,
 		      htab->elf.splt->contents + 16);
 
 	  elf_section_data (htab->elf.splt->output_section)
diff --git a/bfd/elf32-tilepro.c b/bfd/elf32-tilepro.c
index d5a13066a2d..df47e3857ef 100644
--- a/bfd/elf32-tilepro.c
+++ b/bfd/elf32-tilepro.c
@@ -2162,9 +2162,8 @@ allocate_dynrelocs (struct elf_link_hash_entry *h, void *inf)
    omitted when creating a shared library.  */
 
 static bool
-tilepro_elf_omit_section_dynsym (bfd *output_bfd,
-				    struct bfd_link_info *info,
-				    asection *p)
+tilepro_elf_omit_section_dynsym (struct bfd_link_info *info,
+				 asection *p)
 {
   /* We keep the .got section symbol so that explicit relocations
      against the _GLOBAL_OFFSET_TABLE_ symbol emitted in PIC mode
@@ -2172,7 +2171,7 @@ tilepro_elf_omit_section_dynsym (bfd *output_bfd,
   if (strcmp (p->name, ".got") == 0)
     return false;
 
-  return _bfd_elf_omit_section_dynsym_default (output_bfd, info, p);
+  return _bfd_elf_omit_section_dynsym_default (info, p);
 }
 
 /* Set the sizes of the dynamic sections.  */
@@ -2180,8 +2179,7 @@ tilepro_elf_omit_section_dynsym (bfd *output_bfd,
 #define ELF32_DYNAMIC_INTERPRETER "/lib/ld.so.1"
 
 static bool
-tilepro_elf_late_size_sections (bfd *output_bfd,
-				struct bfd_link_info *info)
+tilepro_elf_late_size_sections (struct bfd_link_info *info)
 {
   struct elf_link_hash_table *htab;
   bfd *dynobj;
@@ -2309,7 +2307,7 @@ tilepro_elf_late_size_sections (bfd *output_bfd,
 	      || htab->splt->size == 0)
 	  && (htab->sgot == NULL
 	      || (htab->sgot->size
-		  == get_elf_backend_data (output_bfd)->got_header_size)))
+		  == get_elf_backend_data (info->output_bfd)->got_header_size)))
 	htab->sgotplt->size = 0;
     }
 
@@ -2372,7 +2370,7 @@ tilepro_elf_late_size_sections (bfd *output_bfd,
       s->alloced = 1;
     }
 
-  return _bfd_elf_add_dynamic_tags (output_bfd, info, true);
+  return _bfd_elf_add_dynamic_tags (info, true);
 }
 
 /* Return the base VMA address which should be subtracted from real addresses
@@ -2512,7 +2510,7 @@ static const bfd_byte insn_tls_gd_add_Y0Y1[] = {
    accordingly.  */
 
 static int
-tilepro_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
+tilepro_elf_relocate_section (struct bfd_link_info *info,
 			      bfd *input_bfd, asection *input_section,
 			      bfd_byte *contents, Elf_Internal_Rela *relocs,
 			      Elf_Internal_Sym *local_syms,
@@ -2582,7 +2580,8 @@ tilepro_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections[r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 	}
       else
 	{
@@ -2783,8 +2782,8 @@ tilepro_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		    off &= ~1;
 		  else
 		    {
-		      bfd_put_32 (output_bfd, relocation,
-					  htab->sgot->contents + off);
+		      bfd_put_32 (info->output_bfd, relocation,
+				  htab->sgot->contents + off);
 		      h->got.offset |= 1;
 		    }
 		}
@@ -2821,11 +2820,11 @@ tilepro_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		      outrel.r_info = ELF32_R_INFO (0, R_TILEPRO_RELATIVE);
 		      outrel.r_addend = relocation;
 		      relocation = 0;
-		      tilepro_elf_append_rela_32 (output_bfd, s, &outrel);
+		      tilepro_elf_append_rela_32 (info->output_bfd, s, &outrel);
 		    }
 
-		  bfd_put_32 (output_bfd, relocation,
-				      htab->sgot->contents + off);
+		  bfd_put_32 (info->output_bfd, relocation,
+			      htab->sgot->contents + off);
 		  local_got_offsets[r_symndx] |= 1;
 		}
 	    }
@@ -2932,8 +2931,8 @@ tilepro_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	      skip = false;
 
 	      outrel.r_offset =
-		_bfd_elf_section_offset (output_bfd, info, input_section,
-					 rel->r_offset);
+		_bfd_elf_section_offset (info->output_bfd, info,
+					 input_section, rel->r_offset);
 	      if (outrel.r_offset == (bfd_vma) -1)
 		skip = true;
 	      else if (outrel.r_offset == (bfd_vma) -2)
@@ -3029,7 +3028,7 @@ tilepro_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		    }
 		}
 
-	      tilepro_elf_append_rela_32 (output_bfd, sreloc, &outrel);
+	      tilepro_elf_append_rela_32 (info->output_bfd, sreloc, &outrel);
 
 	      /* This reloc will be computed at runtime, so there's no
 		 need to do anything now.  */
@@ -3054,8 +3053,8 @@ tilepro_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	      BFD_ASSERT (sreloc != NULL);
 	      skip = false;
 	      outrel.r_offset =
-		_bfd_elf_section_offset (output_bfd, info, input_section,
-					 rel->r_offset);
+		_bfd_elf_section_offset (info->output_bfd, info,
+					 input_section, rel->r_offset);
 	      if (outrel.r_offset == (bfd_vma) -1)
 		skip = true;
 	      else if (outrel.r_offset == (bfd_vma) -2)
@@ -3071,7 +3070,7 @@ tilepro_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 				    + rel->r_addend;
 		}
 
-	      tilepro_elf_append_rela_32 (output_bfd, sreloc, &outrel);
+	      tilepro_elf_append_rela_32 (info->output_bfd, sreloc, &outrel);
 	      continue;
 	    }
 	  relocation = tpoff (info, relocation);
@@ -3182,17 +3181,18 @@ tilepro_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		  case R_TILEPRO_IMM16_X0_TLS_IE_HA:
 		  case R_TILEPRO_IMM16_X1_TLS_IE_HA:
 		    if (need_relocs) {
-		      bfd_put_32 (output_bfd, 0, htab->sgot->contents + off);
+		      bfd_put_32 (info->output_bfd, 0,
+				  htab->sgot->contents + off);
 		      outrel.r_offset = (htab->sgot->output_section->vma
 				       + htab->sgot->output_offset + off);
 		      outrel.r_addend = 0;
 		      if (indx == 0)
 			outrel.r_addend = relocation - dtpoff_base (info);
 		      outrel.r_info = ELF32_R_INFO (indx, R_TILEPRO_TLS_TPOFF32);
-		      tilepro_elf_append_rela_32 (output_bfd, htab->srelgot,
-						  &outrel);
+		      tilepro_elf_append_rela_32 (info->output_bfd,
+						  htab->srelgot, &outrel);
 		    } else {
-		      bfd_put_32 (output_bfd, tpoff (info, relocation),
+		      bfd_put_32 (info->output_bfd, tpoff (info, relocation),
 				  htab->sgot->contents + off);
 		    }
 		    break;
@@ -3210,26 +3210,28 @@ tilepro_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 				       + htab->sgot->output_offset + off);
 		      outrel.r_addend = 0;
 		      outrel.r_info = ELF32_R_INFO (indx, R_TILEPRO_TLS_DTPMOD32);
-		      bfd_put_32 (output_bfd, 0, htab->sgot->contents + off);
-		      tilepro_elf_append_rela_32 (output_bfd, htab->srelgot,
+		      bfd_put_32 (info->output_bfd, 0,
+				  htab->sgot->contents + off);
+		      tilepro_elf_append_rela_32 (info->output_bfd,
+						  htab->srelgot,
 						  &outrel);
 		      if (indx == 0)
 			{
 			  BFD_ASSERT (! unresolved_reloc);
-			  bfd_put_32 (output_bfd,
+			  bfd_put_32 (info->output_bfd,
 				      relocation - dtpoff_base (info),
 				      (htab->sgot->contents + off +
 				       TILEPRO_BYTES_PER_WORD));
 			}
 		      else
 			{
-			  bfd_put_32 (output_bfd, 0,
+			  bfd_put_32 (info->output_bfd, 0,
 				      (htab->sgot->contents + off +
 				       TILEPRO_BYTES_PER_WORD));
 			  outrel.r_info = ELF32_R_INFO (indx,
 							R_TILEPRO_TLS_DTPOFF32);
 			  outrel.r_offset += TILEPRO_BYTES_PER_WORD;
-			  tilepro_elf_append_rela_32 (output_bfd,
+			  tilepro_elf_append_rela_32 (info->output_bfd,
 						      htab->srelgot, &outrel);
 			}
 		    }
@@ -3240,9 +3242,10 @@ tilepro_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 			 static link or an executable link with the
 			 symbol binding locally.  Mark it as belonging
 			 to module 1, the executable.  */
-		      bfd_put_32 (output_bfd, 1,
+		      bfd_put_32 (info->output_bfd, 1,
 				  htab->sgot->contents + off );
-		      bfd_put_32 (output_bfd, relocation - dtpoff_base (info),
+		      bfd_put_32 (info->output_bfd,
+				  relocation - dtpoff_base (info),
 				  htab->sgot->contents + off +
 				  TILEPRO_BYTES_PER_WORD);
 		   }
@@ -3268,7 +3271,7 @@ tilepro_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
       if (unresolved_reloc
 	  && !((input_section->flags & SEC_DEBUGGING) != 0
 	       && h->def_dynamic)
-	  && _bfd_elf_section_offset (output_bfd, info, input_section,
+	  && _bfd_elf_section_offset (info->output_bfd, info, input_section,
 				      rel->r_offset) != (bfd_vma) -1)
 	_bfd_error_handler
 	  /* xgettext:c-format */
@@ -3398,8 +3401,7 @@ tilepro_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
    dynamic sections here.  */
 
 static bool
-tilepro_elf_finish_dynamic_symbol (bfd *output_bfd,
-				   struct bfd_link_info *info,
+tilepro_elf_finish_dynamic_symbol (struct bfd_link_info *info,
 				   struct elf_link_hash_entry *h,
 				   Elf_Internal_Sym *sym)
 {
@@ -3436,7 +3438,8 @@ tilepro_elf_finish_dynamic_symbol (bfd *output_bfd,
 
       /* Fill in the entry in the global offset table, which initially points
 	 to the beginning of the plt.  */
-      bfd_put_32 (output_bfd, splt->output_section->vma + splt->output_offset,
+      bfd_put_32 (info->output_bfd,
+		  splt->output_section->vma + splt->output_offset,
 		  sgotplt->contents + r_offset);
 
       /* Fill in the entry in the .rela.plt section.  */
@@ -3447,7 +3450,7 @@ tilepro_elf_finish_dynamic_symbol (bfd *output_bfd,
       rela.r_info = ELF32_R_INFO (h->dynindx, R_TILEPRO_JMP_SLOT);
 
       loc = srela->contents + rela_index * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
 
       if (!h->def_regular)
 	{
@@ -3502,9 +3505,9 @@ tilepro_elf_finish_dynamic_symbol (bfd *output_bfd,
 	  rela.r_addend = 0;
 	}
 
-      bfd_put_32 (output_bfd, 0,
+      bfd_put_32 (info->output_bfd, 0,
 			  sgot->contents + (h->got.offset & ~(bfd_vma) 1));
-      tilepro_elf_append_rela_32 (output_bfd, srela, &rela);
+      tilepro_elf_append_rela_32 (info->output_bfd, srela, &rela);
     }
 
   if (h->needs_copy)
@@ -3524,7 +3527,7 @@ tilepro_elf_finish_dynamic_symbol (bfd *output_bfd,
 	s = htab->sreldynrelro;
       else
 	s = htab->srelbss;
-      tilepro_elf_append_rela_32 (output_bfd, s, &rela);
+      tilepro_elf_append_rela_32 (info->output_bfd, s, &rela);
     }
 
   /* Mark some specially defined symbols as absolute. */
@@ -3538,7 +3541,7 @@ tilepro_elf_finish_dynamic_symbol (bfd *output_bfd,
 /* Finish up the dynamic sections.  */
 
 static bool
-tilepro_finish_dyn (bfd *output_bfd, struct bfd_link_info *info,
+tilepro_finish_dyn (struct bfd_link_info *info,
 		    bfd *dynobj, asection *sdyn,
 		    asection *splt ATTRIBUTE_UNUSED)
 {
@@ -3574,14 +3577,13 @@ tilepro_finish_dyn (bfd *output_bfd, struct bfd_link_info *info,
 	  continue;
 	}
 
-      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
     }
   return true;
 }
 
 static bool
-tilepro_elf_finish_dynamic_sections (bfd *output_bfd,
-				     struct bfd_link_info *info,
+tilepro_elf_finish_dynamic_sections (struct bfd_link_info *info,
 				     bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   bfd *dynobj;
@@ -3602,7 +3604,7 @@ tilepro_elf_finish_dynamic_sections (bfd *output_bfd,
       splt = htab->splt;
       BFD_ASSERT (splt != NULL && sdyn != NULL);
 
-      ret = tilepro_finish_dyn (output_bfd, info, dynobj, sdyn, splt);
+      ret = tilepro_finish_dyn (info, dynobj, sdyn, splt);
 
       if (!ret)
 	return ret;
@@ -3633,9 +3635,9 @@ tilepro_elf_finish_dynamic_sections (bfd *output_bfd,
 	{
 	  /* Write the first two entries in .got.plt, needed for the dynamic
 	     linker.  */
-	  bfd_put_32 (output_bfd, (bfd_vma) -1,
+	  bfd_put_32 (info->output_bfd, -1,
 		      htab->sgotplt->contents);
-	  bfd_put_32 (output_bfd, (bfd_vma) 0,
+	  bfd_put_32 (info->output_bfd, 0,
 		      htab->sgotplt->contents + GOT_ENTRY_SIZE);
 	}
 
@@ -3652,7 +3654,7 @@ tilepro_elf_finish_dynamic_sections (bfd *output_bfd,
 	  bfd_vma val = (sdyn ?
 			 sdyn->output_section->vma + sdyn->output_offset :
 			 0);
-	  bfd_put_32 (output_bfd, val, htab->sgot->contents);
+	  bfd_put_32 (info->output_bfd, val, htab->sgot->contents);
 	}
 
       elf_section_data (htab->sgot->output_section)->this_hdr.sh_entsize
diff --git a/bfd/elf32-v850.c b/bfd/elf32-v850.c
index e625f9d3f68..6bee3af2e61 100644
--- a/bfd/elf32-v850.c
+++ b/bfd/elf32-v850.c
@@ -2171,8 +2171,7 @@ v850_elf_final_link_relocate (reloc_howto_type *howto,
 /* Relocate an V850 ELF section.  */
 
 static int
-v850_elf_relocate_section (bfd *output_bfd,
-			   struct bfd_link_info *info,
+v850_elf_relocate_section (struct bfd_link_info *info,
 			   bfd *input_bfd,
 			   asection *input_section,
 			   bfd_byte *contents,
@@ -2227,7 +2226,8 @@ v850_elf_relocate_section (bfd *output_bfd,
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections[r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 	}
       else
 	{
@@ -2260,7 +2260,7 @@ v850_elf_relocate_section (bfd *output_bfd,
 	continue;
 
       /* FIXME: We should use the addend, but the COFF relocations don't.  */
-      r = v850_elf_final_link_relocate (howto, input_bfd, output_bfd,
+      r = v850_elf_final_link_relocate (howto, input_bfd, info->output_bfd,
 					input_section,
 					contents, rel->r_offset,
 					relocation, rel->r_addend,
diff --git a/bfd/elf32-vax.c b/bfd/elf32-vax.c
index e6329bcef7e..5d103caab93 100644
--- a/bfd/elf32-vax.c
+++ b/bfd/elf32-vax.c
@@ -36,15 +36,6 @@ static bool elf_vax_check_relocs (bfd *, struct bfd_link_info *,
 				  asection *, const Elf_Internal_Rela *);
 static bool elf_vax_adjust_dynamic_symbol (struct bfd_link_info *,
 					   struct elf_link_hash_entry *);
-static int elf_vax_relocate_section (bfd *, struct bfd_link_info *,
-				     bfd *, asection *, bfd_byte *,
-				     Elf_Internal_Rela *,
-				     Elf_Internal_Sym *, asection **);
-static bool elf_vax_finish_dynamic_symbol (bfd *, struct bfd_link_info *,
-					   struct elf_link_hash_entry *,
-					   Elf_Internal_Sym *);
-static bool elf_vax_finish_dynamic_sections (bfd *, struct bfd_link_info *,
-					     bfd_byte *);
 static bfd_vma elf_vax_plt_sym_val (bfd_vma, const asection *,
 				    const arelent *);
 
@@ -983,8 +974,7 @@ elf_vax_discard_got_entries (struct elf_link_hash_entry *h,
 /* Discard unused dynamic data if this is a static link.  */
 
 static bool
-elf_vax_early_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-			     struct bfd_link_info *info)
+elf_vax_early_size_sections (struct bfd_link_info *info)
 {
   bfd *dynobj;
   asection *s;
@@ -1022,7 +1012,7 @@ elf_vax_early_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
 /* Set the sizes of the dynamic sections.  */
 
 static bool
-elf_vax_late_size_sections (bfd *output_bfd, struct bfd_link_info *info)
+elf_vax_late_size_sections (struct bfd_link_info *info)
 {
   bfd *dynobj;
   asection *s;
@@ -1125,7 +1115,7 @@ elf_vax_late_size_sections (bfd *output_bfd, struct bfd_link_info *info)
       s->alloced = 1;
     }
 
-  return _bfd_elf_add_dynamic_tags (output_bfd, info, relocs);
+  return _bfd_elf_add_dynamic_tags (info, relocs);
 }
 
 /* This function is called via elf_vax_link_hash_traverse if we are
@@ -1200,8 +1190,7 @@ elf_vax_instantiate_got_entries (struct elf_link_hash_entry *h, void * infoptr)
 /* Relocate an VAX ELF section.  */
 
 static int
-elf_vax_relocate_section (bfd *output_bfd,
-			  struct bfd_link_info *info,
+elf_vax_relocate_section (struct bfd_link_info *info,
 			  bfd *input_bfd,
 			  asection *input_section,
 			  bfd_byte *contents,
@@ -1256,7 +1245,8 @@ elf_vax_relocate_section (bfd *output_bfd,
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections[r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 	}
       else
 	{
@@ -1330,7 +1320,7 @@ elf_vax_relocate_section (bfd *output_bfd,
 	    off = h->got.offset;
 	    BFD_ASSERT (off < sgot->size);
 
-	    bfd_put_32 (output_bfd, rel->r_addend, sgot->contents + off);
+	    bfd_put_32 (info->output_bfd, rel->r_addend, sgot->contents + off);
 
 	    relocation = sgot->output_offset + off;
 	    /* The GOT relocation uses the addend.  */
@@ -1430,8 +1420,8 @@ elf_vax_relocate_section (bfd *output_bfd,
 	      relocate = false;
 
 	      outrel.r_offset =
-		_bfd_elf_section_offset (output_bfd, info, input_section,
-					 rel->r_offset);
+		_bfd_elf_section_offset (info->output_bfd, info,
+					 input_section, rel->r_offset);
 	      if (outrel.r_offset == (bfd_vma) -1)
 		skip = true;
 	      if (outrel.r_offset == (bfd_vma) -2)
@@ -1522,7 +1512,7 @@ elf_vax_relocate_section (bfd *output_bfd,
 		}
 	      loc = sreloc->contents;
 	      loc += sreloc->reloc_count++ * sizeof (Elf32_External_Rela);
-	      bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+	      bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 
 	      /* This reloc will be computed at runtime, so there's no
 		 need to do anything now, except for R_VAX_32
@@ -1592,7 +1582,7 @@ elf_vax_relocate_section (bfd *output_bfd,
    dynamic sections here.  */
 
 static bool
-elf_vax_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
+elf_vax_finish_dynamic_symbol (struct bfd_link_info *info,
 			       struct elf_link_hash_entry *h,
 			       Elf_Internal_Sym *sym)
 {
@@ -1639,15 +1629,15 @@ elf_vax_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
 		  PLT_ENTRY_SIZE);
 
       /* The offset is relative to the first extension word.  */
-      bfd_put_32 (output_bfd,
+      bfd_put_32 (info->output_bfd,
 		  -(h->plt.offset + 8),
 		  splt->contents + h->plt.offset + 4);
 
-      bfd_put_32 (output_bfd, plt_index * sizeof (Elf32_External_Rela),
+      bfd_put_32 (info->output_bfd, plt_index * sizeof (Elf32_External_Rela),
 		  splt->contents + h->plt.offset + 8);
 
       /* Fill in the entry in the global offset table.  */
-      bfd_put_32 (output_bfd,
+      bfd_put_32 (info->output_bfd,
 		  (splt->output_section->vma
 		   + splt->output_offset
 		   + h->plt.offset) + addend,
@@ -1660,7 +1650,7 @@ elf_vax_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
       rela.r_info = ELF32_R_INFO (h->dynindx, R_VAX_JMP_SLOT);
       rela.r_addend = addend;
       loc = srela->contents + plt_index * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
 
       if (!h->def_regular)
 	{
@@ -1687,12 +1677,12 @@ elf_vax_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
 		       + sgot->output_offset
 		       + h->got.offset);
       rela.r_info = ELF32_R_INFO (h->dynindx, R_VAX_GLOB_DAT);
-      rela.r_addend = bfd_get_signed_32 (output_bfd,
+      rela.r_addend = bfd_get_signed_32 (info->output_bfd,
 					 sgot->contents + h->got.offset);
 
       loc = srela->contents;
       loc += srela->reloc_count++ * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
     }
 
   if (h->needs_copy)
@@ -1715,7 +1705,7 @@ elf_vax_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
       rela.r_info = ELF32_R_INFO (h->dynindx, R_VAX_COPY);
       rela.r_addend = 0;
       loc = s->contents + s->reloc_count++ * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rela, loc);
     }
 
   /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute.  */
@@ -1729,7 +1719,7 @@ elf_vax_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
 /* Finish up the dynamic sections.  */
 
 static bool
-elf_vax_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
+elf_vax_finish_dynamic_sections (struct bfd_link_info *info,
 				 bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   bfd *dynobj;
@@ -1771,13 +1761,13 @@ elf_vax_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
 	      s = elf_hash_table (info)->srelplt;
 	    get_vma:
 	      dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    case DT_PLTRELSZ:
 	      s = elf_hash_table (info)->srelplt;
 	      dyn.d_un.d_val = s->size;
-	      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 	    }
 	}
@@ -1786,12 +1776,12 @@ elf_vax_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
       if (splt->size > 0)
 	{
 	  memcpy (splt->contents, elf_vax_plt0_entry, PLT_ENTRY_SIZE);
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 			  (sgot->output_section->vma
 			   + sgot->output_offset + 4
 			   - (splt->output_section->vma + 6)),
 			  splt->contents + 2);
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 			  (sgot->output_section->vma
 			   + sgot->output_offset + 8
 			   - (splt->output_section->vma + 12)),
@@ -1805,13 +1795,13 @@ elf_vax_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *info,
   if (sgot->size > 0)
     {
       if (sdyn == NULL)
-	bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
+	bfd_put_32 (info->output_bfd, 0, sgot->contents);
       else
-	bfd_put_32 (output_bfd,
+	bfd_put_32 (info->output_bfd,
 		    sdyn->output_section->vma + sdyn->output_offset,
 		    sgot->contents);
-      bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
-      bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
+      bfd_put_32 (info->output_bfd, 0, sgot->contents + 4);
+      bfd_put_32 (info->output_bfd, 0, sgot->contents + 8);
     }
 
   if (elf_section_data (sgot->output_section) != NULL)
diff --git a/bfd/elf32-visium.c b/bfd/elf32-visium.c
index f6c988dae70..fe5f4d5eafb 100644
--- a/bfd/elf32-visium.c
+++ b/bfd/elf32-visium.c
@@ -549,8 +549,7 @@ visium_elf_check_relocs (bfd *abfd, struct bfd_link_info *info,
 /* Relocate a VISIUM ELF section.  */
 
 static int
-visium_elf_relocate_section (bfd *output_bfd,
-			     struct bfd_link_info *info, bfd *input_bfd,
+visium_elf_relocate_section (struct bfd_link_info *info, bfd *input_bfd,
 			     asection *input_section, bfd_byte *contents,
 			     Elf_Internal_Rela *relocs,
 			     Elf_Internal_Sym *local_syms,
@@ -595,7 +594,8 @@ visium_elf_relocate_section (bfd *output_bfd,
 	  /* This is a local symbol.  */
 	  sym = local_syms + r_symndx;
 	  sec = local_sections[r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 
 	  name = bfd_elf_string_from_elf_section
 	    (input_bfd, symtab_hdr->sh_link, sym->st_name);
diff --git a/bfd/elf32-xstormy16.c b/bfd/elf32-xstormy16.c
index 004db71968b..60ab5e6875a 100644
--- a/bfd/elf32-xstormy16.c
+++ b/bfd/elf32-xstormy16.c
@@ -706,8 +706,7 @@ xstormy16_elf_relax_section (bfd *dynobj,
 }
 
 static bool
-xstormy16_elf_early_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-				   struct bfd_link_info *info)
+xstormy16_elf_early_size_sections (struct bfd_link_info *info)
 {
   bfd *dynobj;
   asection *splt;
@@ -761,8 +760,7 @@ xstormy16_elf_early_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
    accordingly.  */
 
 static int
-xstormy16_elf_relocate_section (bfd *			output_bfd ATTRIBUTE_UNUSED,
-				struct bfd_link_info *	info,
+xstormy16_elf_relocate_section (struct bfd_link_info *	info,
 				bfd *			input_bfd,
 				asection *		input_section,
 				bfd_byte *		contents,
@@ -810,7 +808,8 @@ xstormy16_elf_relocate_section (bfd *			output_bfd ATTRIBUTE_UNUSED,
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections [r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 	}
       else
 	{
@@ -957,8 +956,7 @@ xstormy16_elf_relocate_section (bfd *			output_bfd ATTRIBUTE_UNUSED,
 /* This must exist if dynobj is ever set.  */
 
 static bool
-xstormy16_elf_finish_dynamic_sections (bfd *abfd ATTRIBUTE_UNUSED,
-				       struct bfd_link_info *info,
+xstormy16_elf_finish_dynamic_sections (struct bfd_link_info *info,
 				       bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   bfd *dynobj = elf_hash_table (info)->dynobj;
diff --git a/bfd/elf32-xtensa.c b/bfd/elf32-xtensa.c
index 08ea42e3c2d..b1733345fc8 100644
--- a/bfd/elf32-xtensa.c
+++ b/bfd/elf32-xtensa.c
@@ -1554,8 +1554,7 @@ elf_xtensa_allocate_local_got_size (struct bfd_link_info *info)
 /* Set the sizes of the dynamic sections.  */
 
 static bool
-elf_xtensa_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-			       struct bfd_link_info *info)
+elf_xtensa_late_size_sections (struct bfd_link_info *info)
 {
   struct elf_xtensa_link_hash_table *htab;
   bfd *dynobj, *abfd;
@@ -1751,8 +1750,8 @@ elf_xtensa_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
 
 	  loc = (srelgot->contents
 		 + srelgot->reloc_count * sizeof (Elf32_External_Rela));
-	  bfd_elf32_swap_reloca_out (output_bfd, &irela, loc);
-	  bfd_elf32_swap_reloca_out (output_bfd, &irela,
+	  bfd_elf32_swap_reloca_out (info->output_bfd, &irela, loc);
+	  bfd_elf32_swap_reloca_out (info->output_bfd, &irela,
 				     loc + sizeof (Elf32_External_Rela));
 	  srelgot->reloc_count += 2;
 	}
@@ -1765,8 +1764,7 @@ elf_xtensa_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
 #define add_dynamic_entry(TAG, VAL) \
   _bfd_elf_add_dynamic_entry (info, TAG, VAL)
 
-      if (!_bfd_elf_add_dynamic_tags (output_bfd, info,
-				      relplt || relgot))
+      if (!_bfd_elf_add_dynamic_tags (info, relplt || relgot))
 	return false;
 
       if (!add_dynamic_entry (DT_XTENSA_GOT_LOC_OFF, 0)
@@ -1779,7 +1777,7 @@ elf_xtensa_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
 }
 
 static bool
-elf_xtensa_early_size_sections (bfd *output_bfd, struct bfd_link_info *info)
+elf_xtensa_early_size_sections (struct bfd_link_info *info)
 {
   struct elf_xtensa_link_hash_table *htab;
   asection *tls_sec;
@@ -1794,11 +1792,11 @@ elf_xtensa_early_size_sections (bfd *output_bfd, struct bfd_link_info *info)
     {
       struct elf_link_hash_entry *tlsbase = &htab->tlsbase->elf;
       struct bfd_link_hash_entry *bh = &tlsbase->root;
-      elf_backend_data *bed = get_elf_backend_data (output_bfd);
+      elf_backend_data *bed = get_elf_backend_data (info->output_bfd);
 
       tlsbase->type = STT_TLS;
       if (!(_bfd_generic_link_add_one_symbol
-	    (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
+	    (info, info->output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
 	     tls_sec, 0, NULL, false,
 	     bed->collect, &bh)))
 	return false;
@@ -2491,8 +2489,7 @@ replace_tls_insn (Elf_Internal_Rela *rel,
    both relocatable and final links.  */
 
 static int
-elf_xtensa_relocate_section (bfd *output_bfd,
-			     struct bfd_link_info *info,
+elf_xtensa_relocate_section (struct bfd_link_info *info,
 			     bfd *input_bfd,
 			     asection *input_section,
 			     bfd_byte *contents,
@@ -2595,7 +2592,8 @@ elf_xtensa_relocate_section (bfd *output_bfd,
 	  sym = local_syms + r_symndx;
 	  sym_type = ELF32_ST_TYPE (sym->st_info);
 	  sec = local_sections[r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 	}
       else
 	{
@@ -2795,7 +2793,7 @@ elf_xtensa_relocate_section (bfd *output_bfd,
 	      BFD_ASSERT (srel != NULL);
 
 	      outrel.r_offset =
-		_bfd_elf_section_offset (output_bfd, info,
+		_bfd_elf_section_offset (info->output_bfd, info,
 					 input_section, rel->r_offset);
 
 	      if ((outrel.r_offset | 1) == (bfd_vma) -1)
@@ -2838,7 +2836,7 @@ elf_xtensa_relocate_section (bfd *output_bfd,
 			     contents of the literal entry to the address of
 			     the PLT entry.  */
 			  relocation =
-			    elf_xtensa_create_plt_entry (info, output_bfd,
+			    elf_xtensa_create_plt_entry (info, info->output_bfd,
 							 srel->reloc_count);
 			}
 		      unresolved_reloc = false;
@@ -2857,7 +2855,7 @@ elf_xtensa_relocate_section (bfd *output_bfd,
 
 	      loc = (srel->contents
 		     + srel->reloc_count++ * sizeof (Elf32_External_Rela));
-	      bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+	      bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 	      BFD_ASSERT (sizeof (Elf32_External_Rela) * srel->reloc_count
 			  <= srel->size);
 	    }
@@ -2955,7 +2953,7 @@ elf_xtensa_relocate_section (bfd *output_bfd,
 		BFD_ASSERT (srel);
 		loc = (srel->contents
 		       + srel->reloc_count++ * sizeof (Elf32_External_Rela));
-		bfd_elf32_swap_reloca_out (output_bfd, &outrel, loc);
+		bfd_elf32_swap_reloca_out (info->output_bfd, &outrel, loc);
 		BFD_ASSERT (sizeof (Elf32_External_Rela) * srel->reloc_count
 			    <= srel->size);
 	      }
@@ -3014,7 +3012,7 @@ elf_xtensa_relocate_section (bfd *output_bfd,
       if (unresolved_reloc
 	  && !((input_section->flags & SEC_DEBUGGING) != 0
 	       && h->def_dynamic)
-	  && _bfd_elf_section_offset (output_bfd, info, input_section,
+	  && _bfd_elf_section_offset (info->output_bfd, info, input_section,
 				      rel->r_offset) != (bfd_vma) -1)
 	{
 	  _bfd_error_handler
@@ -3068,8 +3066,7 @@ elf_xtensa_relocate_section (bfd *output_bfd,
    the PLT and GOT entries are all set up by relocate_section.  */
 
 static bool
-elf_xtensa_finish_dynamic_symbol (bfd *output_bfd ATTRIBUTE_UNUSED,
-				  struct bfd_link_info *info ATTRIBUTE_UNUSED,
+elf_xtensa_finish_dynamic_symbol (struct bfd_link_info *info ATTRIBUTE_UNUSED,
 				  struct elf_link_hash_entry *h,
 				  Elf_Internal_Sym *sym)
 {
@@ -3213,8 +3210,7 @@ elf_xtensa_combine_prop_entries (bfd *output_bfd,
 /* Finish up the dynamic sections.  */
 
 static bool
-elf_xtensa_finish_dynamic_sections (bfd *output_bfd,
-				    struct bfd_link_info *info,
+elf_xtensa_finish_dynamic_sections (struct bfd_link_info *info,
 				    bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   struct elf_xtensa_link_hash_table *htab;
@@ -3241,9 +3237,9 @@ elf_xtensa_finish_dynamic_sections (bfd *output_bfd,
     {
       BFD_ASSERT (sgot->size == 4);
       if (sdyn == NULL)
-	bfd_put_32 (output_bfd, 0, sgot->contents);
+	bfd_put_32 (info->output_bfd, 0, sgot->contents);
       else
-	bfd_put_32 (output_bfd,
+	bfd_put_32 (info->output_bfd,
 		    sdyn->output_section->vma + sdyn->output_offset,
 		    sgot->contents);
     }
@@ -3266,7 +3262,7 @@ elf_xtensa_finish_dynamic_sections (bfd *output_bfd,
       for (rtld_reloc = 0; rtld_reloc < srelgot->reloc_count; rtld_reloc++)
 	{
 	  loc = srelgot->contents + rtld_reloc * sizeof (Elf32_External_Rela);
-	  bfd_elf32_swap_reloca_in (output_bfd, loc, &irela);
+	  bfd_elf32_swap_reloca_in (info->output_bfd, loc, &irela);
 	  if (ELF32_R_TYPE (irela.r_info) == R_XTENSA_RTLD)
 	    break;
 	}
@@ -3287,24 +3283,24 @@ elf_xtensa_finish_dynamic_sections (bfd *output_bfd,
 	     each chunk of the .got.plt section.  */
 
 	  loc = srelgot->contents + rtld_reloc * sizeof (Elf32_External_Rela);
-	  bfd_elf32_swap_reloca_in (output_bfd, loc, &irela);
+	  bfd_elf32_swap_reloca_in (info->output_bfd, loc, &irela);
 	  BFD_ASSERT (ELF32_R_TYPE (irela.r_info) == R_XTENSA_RTLD);
 	  irela.r_offset = (sgotplt->output_section->vma
 			    + sgotplt->output_offset);
 	  irela.r_addend = 1; /* tell rtld to set value to resolver function */
-	  bfd_elf32_swap_reloca_out (output_bfd, &irela, loc);
+	  bfd_elf32_swap_reloca_out (info->output_bfd, &irela, loc);
 	  rtld_reloc += 1;
 	  BFD_ASSERT (rtld_reloc <= srelgot->reloc_count);
 
 	  /* Next literal immediately follows the first.  */
 	  loc += sizeof (Elf32_External_Rela);
-	  bfd_elf32_swap_reloca_in (output_bfd, loc, &irela);
+	  bfd_elf32_swap_reloca_in (info->output_bfd, loc, &irela);
 	  BFD_ASSERT (ELF32_R_TYPE (irela.r_info) == R_XTENSA_RTLD);
 	  irela.r_offset = (sgotplt->output_section->vma
 			    + sgotplt->output_offset + 4);
 	  /* Tell rtld to set value to object's link map.  */
 	  irela.r_addend = 2;
-	  bfd_elf32_swap_reloca_out (output_bfd, &irela, loc);
+	  bfd_elf32_swap_reloca_out (info->output_bfd, &irela, loc);
 	  rtld_reloc += 1;
 	  BFD_ASSERT (rtld_reloc <= srelgot->reloc_count);
 
@@ -3315,10 +3311,10 @@ elf_xtensa_finish_dynamic_sections (bfd *output_bfd,
 	    chunk_entries = plt_entries - (chunk * PLT_ENTRIES_PER_CHUNK);
 
 	  BFD_ASSERT ((unsigned) (chunk + 1) * 8 <= spltlittbl->size);
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 		      sgotplt->output_section->vma + sgotplt->output_offset,
 		      spltlittbl->contents + (chunk * 8) + 0);
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 		      8 + (chunk_entries * 4),
 		      spltlittbl->contents + (chunk * 8) + 4);
 	}
@@ -3327,7 +3323,7 @@ elf_xtensa_finish_dynamic_sections (bfd *output_bfd,
 	happen before the code below which combines adjacent literal
 	table entries, and the .xt.lit.plt contents have to be forced to
 	the output here.  */
-      if (! bfd_set_section_contents (output_bfd,
+      if (! bfd_set_section_contents (info->output_bfd,
 				      spltlittbl->output_section,
 				      spltlittbl->contents,
 				      spltlittbl->output_offset,
@@ -3347,13 +3343,13 @@ elf_xtensa_finish_dynamic_sections (bfd *output_bfd,
 
   /* Combine adjacent literal table entries.  */
   BFD_ASSERT (! bfd_link_relocatable (info));
-  sxtlit = bfd_get_section_by_name (output_bfd, ".xt.lit");
+  sxtlit = bfd_get_section_by_name (info->output_bfd, ".xt.lit");
   sgotloc = htab->sgotloc;
   BFD_ASSERT (sgotloc);
   if (sxtlit)
     {
       num_xtlit_entries =
-	elf_xtensa_combine_prop_entries (output_bfd, sxtlit, sgotloc);
+	elf_xtensa_combine_prop_entries (info->output_bfd, sxtlit, sgotloc);
       if (num_xtlit_entries < 0)
 	return false;
     }
@@ -3395,7 +3391,7 @@ elf_xtensa_finish_dynamic_sections (bfd *output_bfd,
 	  break;
 	}
 
-      bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
+      bfd_elf32_swap_dyn_out (info->output_bfd, &dyn, dyncon);
     }
 
   return true;
diff --git a/bfd/elf32-z80.c b/bfd/elf32-z80.c
index 1dc2e192adc..4393a6130d1 100644
--- a/bfd/elf32-z80.c
+++ b/bfd/elf32-z80.c
@@ -384,8 +384,7 @@ z80_elf_final_link_relocate (unsigned long r_type,
 }
 
 static int
-z80_elf_relocate_section (bfd *output_bfd,
-			  struct bfd_link_info *info,
+z80_elf_relocate_section (struct bfd_link_info *info,
 			  bfd *input_bfd,
 			  asection *input_section,
 			  bfd_byte *contents,
@@ -421,7 +420,8 @@ z80_elf_relocate_section (bfd *output_bfd,
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections[r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 	}
       else
 	{
@@ -449,7 +449,7 @@ z80_elf_relocate_section (bfd *output_bfd,
 	continue;
 
 
-      z80_elf_final_link_relocate (r_type, input_bfd, output_bfd,
+      z80_elf_final_link_relocate (r_type, input_bfd, info->output_bfd,
 				   input_section,
 				   contents, rel->r_offset,
 				   relocation, rel->r_addend,
diff --git a/bfd/elf64-alpha.c b/bfd/elf64-alpha.c
index 8cc70610c59..10175882d88 100644
--- a/bfd/elf64-alpha.c
+++ b/bfd/elf64-alpha.c
@@ -2560,8 +2560,7 @@ elf64_alpha_size_plt_section (struct bfd_link_info *info)
 }
 
 static bool
-elf64_alpha_early_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-				 struct bfd_link_info *info)
+elf64_alpha_early_size_sections (struct bfd_link_info *info)
 {
   bfd *i;
   struct alpha_elf_link_hash_table * htab;
@@ -2788,8 +2787,7 @@ elf64_alpha_size_rela_got_section (struct bfd_link_info *info)
 /* Set the sizes of the dynamic sections.  */
 
 static bool
-elf64_alpha_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-				struct bfd_link_info *info)
+elf64_alpha_late_size_sections (struct bfd_link_info *info)
 {
   bfd *dynobj;
   asection *s;
@@ -2898,8 +2896,7 @@ elf64_alpha_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
 #define add_dynamic_entry(TAG, VAL) \
   _bfd_elf_add_dynamic_entry (info, TAG, VAL)
 
-      if (!_bfd_elf_add_dynamic_tags (output_bfd, info,
-				      relocs || relplt))
+      if (!_bfd_elf_add_dynamic_tags (info, relocs || relplt))
 	return false;
 
       if (relplt
@@ -4029,8 +4026,7 @@ elf64_alpha_emit_dynrel (bfd *abfd, struct bfd_link_info *info,
    symbol winds up in the output section.  */
 
 static int
-elf64_alpha_relocate_section_r (bfd *output_bfd ATTRIBUTE_UNUSED,
-				struct bfd_link_info *info ATTRIBUTE_UNUSED,
+elf64_alpha_relocate_section_r (struct bfd_link_info *info ATTRIBUTE_UNUSED,
 				bfd *input_bfd, asection *input_section,
 				bfd_byte *contents ATTRIBUTE_UNUSED,
 				Elf_Internal_Rela *relocs,
@@ -4111,7 +4107,7 @@ elf64_alpha_relocate_section_r (bfd *output_bfd ATTRIBUTE_UNUSED,
 /* Relocate an Alpha ELF section.  */
 
 static int
-elf64_alpha_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
+elf64_alpha_relocate_section (struct bfd_link_info *info,
 			      bfd *input_bfd, asection *input_section,
 			      bfd_byte *contents, Elf_Internal_Rela *relocs,
 			      Elf_Internal_Sym *local_syms,
@@ -4130,7 +4126,7 @@ elf64_alpha_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 
   /* Handle relocatable links with a smaller loop.  */
   if (bfd_link_relocatable (info))
-    return elf64_alpha_relocate_section_r (output_bfd, info, input_bfd,
+    return elf64_alpha_relocate_section_r (info, input_bfd,
 					   input_section, contents, relocs,
 					   local_syms, local_sections);
 
@@ -4216,7 +4212,7 @@ elf64_alpha_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	  sym = local_syms + r_symndx;
 	  sec = local_sections[r_symndx];
 	  msec = sec;
-	  value = _bfd_elf_rela_local_sym (output_bfd, sym, &msec, rel);
+	  value = _bfd_elf_rela_local_sym (info->output_bfd, sym, &msec, rel);
 
 	  /* If this is a tp-relative relocation against sym STN_UNDEF (0),
 	     this is hackery from relax_section.  Force the value to
@@ -4252,7 +4248,7 @@ elf64_alpha_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		    continue;
 		  msec = sec;
 		  ent->addend =
-		    _bfd_merged_section_offset (output_bfd, &msec,
+		    _bfd_merged_section_offset (info->output_bfd, &msec,
 						sym->st_value + ent->addend);
 		  ent->addend -= sym->st_value;
 		  ent->addend += msec->output_section->vma
@@ -4333,7 +4329,7 @@ elf64_alpha_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	    {
 	      gotent->reloc_done = 1;
 
-	      bfd_put_64 (output_bfd, value,
+	      bfd_put_64 (info->output_bfd, value,
 			  sgot->contents + gotent->got_offset);
 
 	      /* If the symbol has been forced local, output a
@@ -4342,7 +4338,7 @@ elf64_alpha_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	      if (bfd_link_pic (info)
 		  && !dynamic_symbol_p
 		  && !undef_weak_ref)
-		elf64_alpha_emit_dynrel (output_bfd, info, sgot, srelgot,
+		elf64_alpha_emit_dynrel (info->output_bfd, info, sgot, srelgot,
 					 gotent->got_offset, 0,
 					 R_ALPHA_RELATIVE, value);
 	    }
@@ -4509,7 +4505,7 @@ elf64_alpha_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		     && (input_section->flags & SEC_ALLOC)
 		     && !undef_weak_ref
 		     && !(unresolved_reloc
-			  && (_bfd_elf_section_offset (output_bfd, info,
+			  && (_bfd_elf_section_offset (info->output_bfd, info,
 						       input_section,
 						       rel->r_offset)
 			      == (bfd_vma) -1)))
@@ -4531,7 +4527,7 @@ elf64_alpha_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	      goto default_reloc;
 
 	    if (input_section->flags & SEC_ALLOC)
-	      elf64_alpha_emit_dynrel (output_bfd, info, input_section,
+	      elf64_alpha_emit_dynrel (info->output_bfd, info, input_section,
 				       srel, rel->r_offset, dynindx,
 				       dyntype, dynaddend);
 	  }
@@ -4564,7 +4560,7 @@ elf64_alpha_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	     NULL to be encoded as 0 in any format, so this works here.  */
 	  if (r_symndx == STN_UNDEF
 	      || (unresolved_reloc
-		  && _bfd_elf_section_offset (output_bfd, info,
+		  && _bfd_elf_section_offset (info->output_bfd, info,
 					      input_section,
 					      rel->r_offset) == (bfd_vma) -1))
 	    howto = (elf64_alpha_howto_table
@@ -4583,7 +4579,7 @@ elf64_alpha_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	      gotent->reloc_done = 1;
 
 	      /* Note that the module index for the main program is 1.  */
-	      bfd_put_64 (output_bfd,
+	      bfd_put_64 (info->output_bfd,
 			  !bfd_link_pic (info) && !dynamic_symbol_p,
 			  sgot->contents + gotent->got_offset);
 
@@ -4591,7 +4587,8 @@ elf64_alpha_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		 DTPMOD64 reloc, otherwise it will be handled in
 		 finish_dynamic_symbol.  */
 	      if (bfd_link_pic (info) && !dynamic_symbol_p)
-		elf64_alpha_emit_dynrel (output_bfd, info, sgot, srelgot,
+		elf64_alpha_emit_dynrel (info->output_bfd, info,
+					 sgot, srelgot,
 					 gotent->got_offset, 0,
 					 R_ALPHA_DTPMOD64, 0);
 
@@ -4602,7 +4599,7 @@ elf64_alpha_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		  BFD_ASSERT (elf_hash_table (info)->tls_sec != NULL);
 		  value -= dtp_base;
 		}
-	      bfd_put_64 (output_bfd, value,
+	      bfd_put_64 (info->output_bfd, value,
 			  sgot->contents + gotent->got_offset + 8);
 	    }
 
@@ -4687,14 +4684,15 @@ elf64_alpha_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		    value -= tp_base;
 		  else
 		    {
-		      elf64_alpha_emit_dynrel (output_bfd, info, sgot, srelgot,
+		      elf64_alpha_emit_dynrel (info->output_bfd, info,
+					       sgot, srelgot,
 					       gotent->got_offset, 0,
 					       R_ALPHA_TPREL64,
 					       value - dtp_base);
 		      value = 0;
 		    }
 		}
-	      bfd_put_64 (output_bfd, value,
+	      bfd_put_64 (info->output_bfd, value,
 			  sgot->contents + gotent->got_offset);
 	    }
 
@@ -4759,7 +4757,7 @@ elf64_alpha_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
    dynamic sections here.  */
 
 static bool
-elf64_alpha_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
+elf64_alpha_finish_dynamic_symbol (struct bfd_link_info *info,
 				   struct elf_link_hash_entry *h,
 				   Elf_Internal_Sym *sym)
 {
@@ -4809,7 +4807,7 @@ elf64_alpha_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
 	      {
 		disp = (PLT_HEADER_SIZE - 4) - (gotent->plt_offset + 4);
 		insn = INSN_AD (INSN_BR, 31, disp);
-		bfd_put_32 (output_bfd, insn,
+		bfd_put_32 (info->output_bfd, insn,
 			    splt->contents + gotent->plt_offset);
 
 		plt_index = ((gotent->plt_offset - NEW_PLT_HEADER_SIZE)
@@ -4819,11 +4817,11 @@ elf64_alpha_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
 	      {
 		disp = -(gotent->plt_offset + 4);
 		insn = INSN_AD (INSN_BR, 28, disp);
-		bfd_put_32 (output_bfd, insn,
+		bfd_put_32 (info->output_bfd, insn,
 			    splt->contents + gotent->plt_offset);
-		bfd_put_32 (output_bfd, INSN_UNOP,
+		bfd_put_32 (info->output_bfd, INSN_UNOP,
 			    splt->contents + gotent->plt_offset + 4);
-		bfd_put_32 (output_bfd, INSN_UNOP,
+		bfd_put_32 (info->output_bfd, INSN_UNOP,
 			    splt->contents + gotent->plt_offset + 8);
 
 		plt_index = ((gotent->plt_offset - OLD_PLT_HEADER_SIZE)
@@ -4836,10 +4834,10 @@ elf64_alpha_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
 	    outrel.r_addend = 0;
 
 	    loc = srel->contents + plt_index * sizeof (Elf64_External_Rela);
-	    bfd_elf64_swap_reloca_out (output_bfd, &outrel, loc);
+	    bfd_elf64_swap_reloca_out (info->output_bfd, &outrel, loc);
 
 	    /* Fill in the entry in the .got.  */
-	    bfd_put_64 (output_bfd, plt_addr,
+	    bfd_put_64 (info->output_bfd, plt_addr,
 			sgot->contents + gotent->got_offset);
 	  }
     }
@@ -4884,12 +4882,12 @@ elf64_alpha_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
 	      abort ();
 	    }
 
-	  elf64_alpha_emit_dynrel (output_bfd, info, sgot, srel,
+	  elf64_alpha_emit_dynrel (info->output_bfd, info, sgot, srel,
 				   gotent->got_offset, h->dynindx,
 				   r_type, gotent->addend);
 
 	  if (gotent->reloc_type == R_ALPHA_TLSGD)
-	    elf64_alpha_emit_dynrel (output_bfd, info, sgot, srel,
+	    elf64_alpha_emit_dynrel (info->output_bfd, info, sgot, srel,
 				     gotent->got_offset + 8, h->dynindx,
 				     R_ALPHA_DTPREL64, gotent->addend);
 	}
@@ -4907,8 +4905,7 @@ elf64_alpha_finish_dynamic_symbol (bfd *output_bfd, struct bfd_link_info *info,
 /* Finish up the dynamic sections.  */
 
 static bool
-elf64_alpha_finish_dynamic_sections (bfd *output_bfd,
-				     struct bfd_link_info *info,
+elf64_alpha_finish_dynamic_sections (struct bfd_link_info *info,
 				     bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   bfd *dynobj;
@@ -4961,7 +4958,7 @@ elf64_alpha_finish_dynamic_sections (bfd *output_bfd,
 	      break;
 	    }
 
-	  bfd_elf64_swap_dyn_out (output_bfd, &dyn, dyncon);
+	  bfd_elf64_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	}
 
       /* Initialize the plt header.  */
@@ -4975,49 +4972,49 @@ elf64_alpha_finish_dynamic_sections (bfd *output_bfd,
 	      ofs = gotplt_vma - (plt_vma + PLT_HEADER_SIZE);
 
 	      insn = INSN_ABC (INSN_SUBQ, 27, 28, 25);
-	      bfd_put_32 (output_bfd, insn, splt->contents);
+	      bfd_put_32 (info->output_bfd, insn, splt->contents);
 
 	      insn = INSN_ABO (INSN_LDAH, 28, 28, (ofs + 0x8000) >> 16);
-	      bfd_put_32 (output_bfd, insn, splt->contents + 4);
+	      bfd_put_32 (info->output_bfd, insn, splt->contents + 4);
 
 	      insn = INSN_ABC (INSN_S4SUBQ, 25, 25, 25);
-	      bfd_put_32 (output_bfd, insn, splt->contents + 8);
+	      bfd_put_32 (info->output_bfd, insn, splt->contents + 8);
 
 	      insn = INSN_ABO (INSN_LDA, 28, 28, ofs);
-	      bfd_put_32 (output_bfd, insn, splt->contents + 12);
+	      bfd_put_32 (info->output_bfd, insn, splt->contents + 12);
 
 	      insn = INSN_ABO (INSN_LDQ, 27, 28, 0);
-	      bfd_put_32 (output_bfd, insn, splt->contents + 16);
+	      bfd_put_32 (info->output_bfd, insn, splt->contents + 16);
 
 	      insn = INSN_ABC (INSN_ADDQ, 25, 25, 25);
-	      bfd_put_32 (output_bfd, insn, splt->contents + 20);
+	      bfd_put_32 (info->output_bfd, insn, splt->contents + 20);
 
 	      insn = INSN_ABO (INSN_LDQ, 28, 28, 8);
-	      bfd_put_32 (output_bfd, insn, splt->contents + 24);
+	      bfd_put_32 (info->output_bfd, insn, splt->contents + 24);
 
 	      insn = INSN_AB (INSN_JMP, 31, 27);
-	      bfd_put_32 (output_bfd, insn, splt->contents + 28);
+	      bfd_put_32 (info->output_bfd, insn, splt->contents + 28);
 
 	      insn = INSN_AD (INSN_BR, 28, -PLT_HEADER_SIZE);
-	      bfd_put_32 (output_bfd, insn, splt->contents + 32);
+	      bfd_put_32 (info->output_bfd, insn, splt->contents + 32);
 	    }
 	  else
 	    {
 	      insn = INSN_AD (INSN_BR, 27, 0);	/* br $27, .+4 */
-	      bfd_put_32 (output_bfd, insn, splt->contents);
+	      bfd_put_32 (info->output_bfd, insn, splt->contents);
 
 	      insn = INSN_ABO (INSN_LDQ, 27, 27, 12);
-	      bfd_put_32 (output_bfd, insn, splt->contents + 4);
+	      bfd_put_32 (info->output_bfd, insn, splt->contents + 4);
 
 	      insn = INSN_UNOP;
-	      bfd_put_32 (output_bfd, insn, splt->contents + 8);
+	      bfd_put_32 (info->output_bfd, insn, splt->contents + 8);
 
 	      insn = INSN_AB (INSN_JMP, 27, 27);
-	      bfd_put_32 (output_bfd, insn, splt->contents + 12);
+	      bfd_put_32 (info->output_bfd, insn, splt->contents + 12);
 
 	      /* The next two words will be filled in by ld.so.  */
-	      bfd_put_64 (output_bfd, 0, splt->contents + 16);
-	      bfd_put_64 (output_bfd, 0, splt->contents + 24);
+	      bfd_put_64 (info->output_bfd, 0, splt->contents + 16);
+	      bfd_put_64 (info->output_bfd, 0, splt->contents + 24);
 	    }
 
 	  elf_section_data (splt->output_section)->this_hdr.sh_entsize = 0;
diff --git a/bfd/elf64-bpf.c b/bfd/elf64-bpf.c
index 89ab8ab80c8..1e6ed7c01b1 100644
--- a/bfd/elf64-bpf.c
+++ b/bfd/elf64-bpf.c
@@ -172,8 +172,7 @@ bpf_info_to_howto (bfd *abfd, arelent *bfd_reloc,
 #define sec_addr(sec) ((sec)->output_section->vma + (sec)->output_offset)
 
 static int
-bpf_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
-                          struct bfd_link_info *info,
+bpf_elf_relocate_section (struct bfd_link_info *info,
                           bfd *input_bfd,
                           asection *input_section,
                           bfd_byte *contents,
diff --git a/bfd/elf64-hppa.c b/bfd/elf64-hppa.c
index f4b24b294f3..7ce9a3bdf2e 100644
--- a/bfd/elf64-hppa.c
+++ b/bfd/elf64-hppa.c
@@ -187,13 +187,6 @@ static int elf64_hppa_link_output_symbol_hook
   (struct bfd_link_info *, const char *, Elf_Internal_Sym *,
    asection *, struct elf_link_hash_entry *);
 
-static bool elf64_hppa_finish_dynamic_symbol
-  (bfd *, struct bfd_link_info *,
-   struct elf_link_hash_entry *, Elf_Internal_Sym *);
-
-static bool elf64_hppa_finish_dynamic_sections
-  (bfd *, struct bfd_link_info *, bfd_byte *);
-
 static bool elf64_hppa_check_relocs
   (bfd *, struct bfd_link_info *,
    asection *, const Elf_Internal_Rela *);
@@ -1615,7 +1608,7 @@ elf64_hppa_mark_milli_and_exported_functions (struct elf_link_hash_entry *eh,
    the contents of our special sections.  */
 
 static bool
-elf64_hppa_late_size_sections (bfd *output_bfd, struct bfd_link_info *info)
+elf64_hppa_late_size_sections (struct bfd_link_info *info)
 {
   struct elf64_hppa_link_hash_table *hppa_info;
   struct elf64_hppa_allocate_data data;
@@ -2021,7 +2014,7 @@ elf64_hppa_late_size_sections (bfd *output_bfd, struct bfd_link_info *info)
       /* Force DT_FLAGS to always be set.
 	 Required by HPUX 11.00 patch PHSS_26559.
 	 PR 30743: But do not set them for non-HPUX targets.  */
-      if (output_bfd->xvec == & hppa_elf64_vec)
+      if (info->output_bfd->xvec == &hppa_elf64_vec)
 	{
 	  if (!add_dynamic_entry (DT_FLAGS, (info)->flags))
 	    return false;
@@ -2037,7 +2030,7 @@ elf64_hppa_late_size_sections (bfd *output_bfd, struct bfd_link_info *info)
     }
 #undef add_dynamic_entry
 
-  return _bfd_elf_add_dynamic_tags (output_bfd, info, relocs);
+  return _bfd_elf_add_dynamic_tags (info, relocs);
 }
 
 /* Called after we have output the symbol into the dynamic symbol
@@ -2084,8 +2077,7 @@ elf64_hppa_link_output_symbol_hook (struct bfd_link_info *info ATTRIBUTE_UNUSED,
    dynamic sections here.  */
 
 static bool
-elf64_hppa_finish_dynamic_symbol (bfd *output_bfd,
-				  struct bfd_link_info *info,
+elf64_hppa_finish_dynamic_symbol (struct bfd_link_info *info,
 				  struct elf_link_hash_entry *eh,
 				  Elf_Internal_Sym *sym)
 {
@@ -2121,7 +2113,7 @@ elf64_hppa_finish_dynamic_symbol (bfd *output_bfd,
       sym->st_value = (hh->opd_offset
 		       + sopd->output_offset
 		       + sopd->output_section->vma);
-      sym->st_shndx = _bfd_elf_section_from_bfd_section (output_bfd,
+      sym->st_shndx = _bfd_elf_section_from_bfd_section (info->output_bfd,
 							 sopd->output_section);
     }
 
@@ -2209,7 +2201,7 @@ elf64_hppa_finish_dynamic_symbol (bfd *output_bfd,
       value = hh->plt_offset - hppa_info->gp_offset;
 
       insn = bfd_get_32 (stub->owner, stub->contents + hh->stub_offset);
-      if (output_bfd->arch_info->mach >= 25)
+      if (info->output_bfd->arch_info->mach >= 25)
 	{
 	  /* Wide mode allows 16 bit offsets.  */
 	  max_offset = 32768;
@@ -2238,7 +2230,7 @@ elf64_hppa_finish_dynamic_symbol (bfd *output_bfd,
       /* Fix up the second ldd instruction.  */
       value += 8;
       insn = bfd_get_32 (stub->owner, stub->contents + hh->stub_offset + 8);
-      if (output_bfd->arch_info->mach >= 25)
+      if (info->output_bfd->arch_info->mach >= 25)
 	{
 	  insn &= ~ 0xfff1;
 	  insn |= re_assemble_16 ((int) value);
@@ -2608,8 +2600,7 @@ elf64_hppa_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
 /* Finish up the dynamic sections.  */
 
 static bool
-elf64_hppa_finish_dynamic_sections (bfd *output_bfd,
-				    struct bfd_link_info *info,
+elf64_hppa_finish_dynamic_sections (struct bfd_link_info *info,
 				    bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   bfd *dynobj;
@@ -2668,33 +2659,33 @@ elf64_hppa_finish_dynamic_sections (bfd *output_bfd,
 		 In HPUX 11.11, HP ld now allocates the region at the end
 		 of the .bss section.  This avoids adding 16 bytes to the
 		 start of .data.  This may affect relocation offsets.  */
-	      if (output_bfd->xvec == & hppa_elf64_vec
+	      if (info->output_bfd->xvec == & hppa_elf64_vec
 	          && ! bfd_link_pic (info))
 		{
-		  s = bfd_get_section_by_name (output_bfd, ".bss");
+		  s = bfd_get_section_by_name (info->output_bfd, ".bss");
 		  if (!s)
 		    break;
 		  dyn.d_un.d_ptr = s->vma + s->size - 16;
-		  bfd_elf64_swap_dyn_out (output_bfd, &dyn, dyncon);
+		  bfd_elf64_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 		}
 	      break;
 
 	    case DT_PLTGOT:
 	      /* HP's use PLTGOT to set the GOT register.  */
-	      dyn.d_un.d_ptr = _bfd_get_gp_value (output_bfd);
-	      bfd_elf64_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      dyn.d_un.d_ptr = _bfd_get_gp_value (info->output_bfd);
+	      bfd_elf64_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    case DT_JMPREL:
 	      s = hppa_info->root.srelplt;
 	      dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
-	      bfd_elf64_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf64_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    case DT_PLTRELSZ:
 	      s = hppa_info->root.srelplt;
 	      dyn.d_un.d_val = s->size;
-	      bfd_elf64_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf64_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    case DT_RELA:
@@ -2704,7 +2695,7 @@ elf64_hppa_finish_dynamic_sections (bfd *output_bfd,
 	      if (! s || ! s->size)
 		s = hppa_info->opd_rel_sec;
 	      dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
-	      bfd_elf64_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf64_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    case DT_RELASZ:
@@ -2719,7 +2710,7 @@ elf64_hppa_finish_dynamic_sections (bfd *output_bfd,
 		 it, so we'll emulate them.  */
 	      s = hppa_info->root.srelplt;
 	      dyn.d_un.d_val += s->size;
-	      bfd_elf64_swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bfd_elf64_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	      break;
 
 	    }
@@ -4305,14 +4296,13 @@ elf_hppa_final_link_relocate (Elf_Internal_Rela *rel,
 /* Relocate an HPPA ELF section.  */
 
 static int
-elf64_hppa_relocate_section (bfd *output_bfd,
-			   struct bfd_link_info *info,
-			   bfd *input_bfd,
-			   asection *input_section,
-			   bfd_byte *contents,
-			   Elf_Internal_Rela *relocs,
-			   Elf_Internal_Sym *local_syms,
-			   asection **local_sections)
+elf64_hppa_relocate_section (struct bfd_link_info *info,
+			     bfd *input_bfd,
+			     asection *input_section,
+			     bfd_byte *contents,
+			     Elf_Internal_Rela *relocs,
+			     Elf_Internal_Sym *local_syms,
+			     asection **local_sections)
 {
   Elf_Internal_Shdr *symtab_hdr;
   Elf_Internal_Rela *rel;
@@ -4358,7 +4348,8 @@ elf64_hppa_relocate_section (bfd *output_bfd,
 	  /* This is a local symbol, hh defaults to NULL.  */
 	  sym = local_syms + r_symndx;
 	  sym_sec = local_sections[r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sym_sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sym_sec, rel);
 	}
       else
 	{
@@ -4436,7 +4427,7 @@ elf64_hppa_relocate_section (bfd *output_bfd,
       if (bfd_link_relocatable (info))
 	continue;
 
-      r = elf_hppa_final_link_relocate (rel, input_bfd, output_bfd,
+      r = elf_hppa_final_link_relocate (rel, input_bfd, info->output_bfd,
 					input_section, contents,
 					relocation, info, sym, sym_sec,
 					eh);
diff --git a/bfd/elf64-ia64-vms.c b/bfd/elf64-ia64-vms.c
index c35cb7cedc5..6785ea08a38 100644
--- a/bfd/elf64-ia64-vms.c
+++ b/bfd/elf64-ia64-vms.c
@@ -2591,8 +2591,7 @@ elf64_ia64_adjust_dynamic_symbol (struct bfd_link_info *info ATTRIBUTE_UNUSED,
 }
 
 static bool
-elf64_ia64_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-			       struct bfd_link_info *info)
+elf64_ia64_late_size_sections (struct bfd_link_info *info)
 {
   struct elf64_ia64_allocate_data data;
   struct elf64_ia64_link_hash_table *ia64_info;
@@ -2829,7 +2828,7 @@ elf64_ia64_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
 
 	  if (!(abfd->flags & DYNAMIC))
 	    continue;
-	  BFD_ASSERT (abfd->xvec == output_bfd->xvec);
+	  BFD_ASSERT (abfd->xvec == info->output_bfd->xvec);
 
 	  if (!_bfd_elf_add_dynamic_entry (info, DT_IA_64_VMS_NEEDED_IDENT,
 					   elf_ia64_vms_ident (abfd)))
@@ -2906,10 +2905,10 @@ elf64_ia64_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
       bed->s->swap_dyn_out (hash_table->dynobj, &dyn,
 			    dynsec->contents + strdyn_off + bed->s->sizeof_dyn);
 
-      elf_ia64_vms_tdata (output_bfd)->needed_count = shl_num;
+      elf_ia64_vms_tdata (info->output_bfd)->needed_count = shl_num;
 
       /* Note section.  */
-      if (!create_ia64_vms_notes (output_bfd, info, time_hi, time_lo))
+      if (!create_ia64_vms_notes (info->output_bfd, info, time_hi, time_lo))
 	return false;
     }
 
@@ -3369,8 +3368,7 @@ elf64_ia64_final_link (bfd *abfd, struct bfd_link_info *info)
 }
 
 static int
-elf64_ia64_relocate_section (bfd *output_bfd,
-			     struct bfd_link_info *info,
+elf64_ia64_relocate_section (struct bfd_link_info *info,
 			     bfd *input_bfd,
 			     asection *input_section,
 			     bfd_byte *contents,
@@ -3402,7 +3400,7 @@ elf64_ia64_relocate_section (bfd *output_bfd,
 	->this_hdr.sh_flags |= flags;
     }
 
-  gp_val = _bfd_get_gp_value (output_bfd);
+  gp_val = _bfd_get_gp_value (info->output_bfd);
 
   rel = relocs;
   relend = relocs + input_section->reloc_count;
@@ -3451,7 +3449,7 @@ elf64_ia64_relocate_section (bfd *output_bfd,
 	  sym = local_syms + r_symndx;
 	  sym_sec = local_sections[r_symndx];
 	  msec = sym_sec;
-	  value = _bfd_elf_rela_local_sym (output_bfd, sym, &msec, rel);
+	  value = _bfd_elf_rela_local_sym (info->output_bfd, sym, &msec, rel);
 	  if (!bfd_link_relocatable (info)
 	      && (sym_sec->flags & SEC_MERGE) != 0
 	      && ELF_ST_TYPE (sym->st_info) == STT_SECTION
@@ -3471,7 +3469,7 @@ elf64_ia64_relocate_section (bfd *output_bfd,
 		    {
 		      msec = sym_sec;
 		      dynent->addend =
-			_bfd_merged_section_offset (output_bfd, &msec,
+			_bfd_merged_section_offset (info->output_bfd, &msec,
 						    sym->st_value
 						    + dynent->addend);
 		      dynent->addend -= sym->st_value;
@@ -3596,7 +3594,7 @@ elf64_ia64_relocate_section (bfd *output_bfd,
 		  break;
 		}
 	      elf64_ia64_install_fixup
-		(output_bfd, ia64_info, h,
+		(info->output_bfd, ia64_info, h,
 		 dyn_r_type, input_section, rel->r_offset, addend);
 	      r = bfd_reloc_ok;
 	      break;
@@ -3647,7 +3645,7 @@ elf64_ia64_relocate_section (bfd *output_bfd,
 	case R_IA64_PLTOFF64MSB:
 	case R_IA64_PLTOFF64LSB:
 	  dyn_i = get_dyn_sym_info (ia64_info, h, input_bfd, rel, false);
-	  value = set_pltoff_entry (output_bfd, info, dyn_i, value, false);
+	  value = set_pltoff_entry (info->output_bfd, info, dyn_i, value, false);
 	  value -= gp_val;
 	  r = ia64_elf_install_value (hit_addr, value, r_type);
 	  break;
@@ -3661,7 +3659,7 @@ elf64_ia64_relocate_section (bfd *output_bfd,
 	  if (dyn_i->want_fptr)
 	    {
 	      if (!undef_weak_ref)
-		value = set_fptr_entry (output_bfd, info, dyn_i, value);
+		value = set_fptr_entry (info->output_bfd, info, dyn_i, value);
 	    }
 	  if (!dyn_i->want_fptr || bfd_link_pie (info))
 	    {
@@ -3692,7 +3690,7 @@ elf64_ia64_relocate_section (bfd *output_bfd,
 
 	      /* VMS: FIXFD.  */
 	      elf64_ia64_install_fixup
-		(output_bfd, ia64_info, h, R_IA64_VMS_FIXFD,
+		(info->output_bfd, ia64_info, h, R_IA64_VMS_FIXFD,
 		 input_section, rel->r_offset, 0);
 	      r = bfd_reloc_ok;
 	      break;
@@ -3712,12 +3710,12 @@ elf64_ia64_relocate_section (bfd *output_bfd,
 	    {
 	      BFD_ASSERT (h == NULL || !h->def_dynamic);
 	      if (!undef_weak_ref)
-		value = set_fptr_entry (output_bfd, info, dyn_i, value);
+		value = set_fptr_entry (info->output_bfd, info, dyn_i, value);
 	    }
 	  else
 	    value = 0;
 
-	  value = set_got_entry (output_bfd, info, dyn_i,
+	  value = set_got_entry (info->output_bfd, info, dyn_i,
 				 rel->r_addend, value, R_IA64_FPTR64LSB);
 	  value -= gp_val;
 	  r = ia64_elf_install_value (hit_addr, value, r_type);
@@ -3814,7 +3812,7 @@ elf64_ia64_relocate_section (bfd *output_bfd,
 	    {
 	      /* Find the segment that contains the output_section.  */
 	      Elf_Internal_Phdr *p = _bfd_elf_find_segment_containing_section
-		(output_bfd, sym_sec->output_section);
+		(info->output_bfd, sym_sec->output_section);
 
 	      if (p == NULL)
 		{
@@ -3995,8 +3993,7 @@ elf64_ia64_relocate_section (bfd *output_bfd,
 }
 
 static bool
-elf64_ia64_finish_dynamic_symbol (bfd *output_bfd,
-				  struct bfd_link_info *info,
+elf64_ia64_finish_dynamic_symbol (struct bfd_link_info *info,
 				  struct elf_link_hash_entry *h,
 				  Elf_Internal_Sym *sym)
 {
@@ -4014,11 +4011,12 @@ elf64_ia64_finish_dynamic_symbol (bfd *output_bfd,
       asection *plt_sec;
       bfd_vma plt_addr, pltoff_addr, gp_val;
 
-      gp_val = _bfd_get_gp_value (output_bfd);
+      gp_val = _bfd_get_gp_value (info->output_bfd);
 
       plt_sec = ia64_info->root.splt;
       plt_addr = 0;  /* Not used as overriden by FIXUPs.  */
-      pltoff_addr = set_pltoff_entry (output_bfd, info, dyn_i, plt_addr, true);
+      pltoff_addr = set_pltoff_entry (info->output_bfd, info, dyn_i,
+				      plt_addr, true);
 
       /* Initialize the FULL PLT entry, if needed.  */
       if (dyn_i->want_plt2)
@@ -4038,7 +4036,7 @@ elf64_ia64_finish_dynamic_symbol (bfd *output_bfd,
 
       /* VMS: FIXFD.  */
       elf64_ia64_install_fixup
-	(output_bfd, ia64_info, h, R_IA64_VMS_FIXFD, ia64_info->pltoff_sec,
+	(info->output_bfd, ia64_info, h, R_IA64_VMS_FIXFD, ia64_info->pltoff_sec,
 	 pltoff_addr - (ia64_info->pltoff_sec->output_section->vma
 			+ ia64_info->pltoff_sec->output_offset), 0);
     }
@@ -4053,8 +4051,7 @@ elf64_ia64_finish_dynamic_symbol (bfd *output_bfd,
 }
 
 static bool
-elf64_ia64_finish_dynamic_sections (bfd *abfd,
-				    struct bfd_link_info *info,
+elf64_ia64_finish_dynamic_sections (struct bfd_link_info *info,
 				    bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   struct elf64_ia64_link_hash_table *ia64_info;
@@ -4084,7 +4081,7 @@ elf64_ia64_finish_dynamic_sections (bfd *abfd,
       dyncon = (Elf64_External_Dyn *) sdyn->contents;
       dynconend = (Elf64_External_Dyn *) (sdyn->contents + sdyn->size);
 
-      gp_val = _bfd_get_gp_value (abfd);
+      gp_val = _bfd_get_gp_value (info->output_bfd);
       phdr = _bfd_elf_find_segment_containing_section
 	(info->output_bfd, ia64_info->pltoff_sec->output_section);
       BFD_ASSERT (phdr != NULL);
@@ -4092,17 +4089,20 @@ elf64_ia64_finish_dynamic_sections (bfd *abfd,
       gp_seg = phdr - base_phdr;
       gp_off = gp_val - phdr->p_vaddr;
 
-      unwind_sec = bfd_get_section_by_name (abfd, ELF_STRING_ia64_unwind);
+      unwind_sec = bfd_get_section_by_name (info->output_bfd,
+					    ELF_STRING_ia64_unwind);
       if (unwind_sec != NULL)
 	{
 	  asection *code_sec;
 
-	  phdr = _bfd_elf_find_segment_containing_section (abfd, unwind_sec);
+	  phdr = _bfd_elf_find_segment_containing_section (info->output_bfd,
+							   unwind_sec);
 	  BFD_ASSERT (phdr != NULL);
 	  unwind_seg = phdr - base_phdr;
 
-	  code_sec = bfd_get_section_by_name (abfd, "$CODE$");
-	  phdr = _bfd_elf_find_segment_containing_section (abfd, code_sec);
+	  code_sec = bfd_get_section_by_name (info->output_bfd, "$CODE$");
+	  phdr = _bfd_elf_find_segment_containing_section (info->output_bfd,
+							   code_sec);
 	  BFD_ASSERT (phdr != NULL);
 	  code_seg = phdr - base_phdr;
 	}
@@ -4157,7 +4157,7 @@ elf64_ia64_finish_dynamic_sections (bfd *abfd,
 	      continue;
 	    }
 
-	  bfd_elf64_swap_dyn_out (abfd, &dyn, dyncon);
+	  bfd_elf64_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	}
     }
 
diff --git a/bfd/elf64-mmix.c b/bfd/elf64-mmix.c
index b874fae40af..4036dcb7c3d 100644
--- a/bfd/elf64-mmix.c
+++ b/bfd/elf64-mmix.c
@@ -1347,8 +1347,7 @@ mmix_elf_reloc (bfd *abfd,
    for guidance if you're thinking of copying this.  */
 
 static int
-mmix_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
-			   struct bfd_link_info *info,
+mmix_elf_relocate_section (struct bfd_link_info *info,
 			   bfd *input_bfd,
 			   asection *input_section,
 			   bfd_byte *contents,
@@ -1404,7 +1403,8 @@ mmix_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections [r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 
 	  name = bfd_elf_string_from_elf_section (input_bfd,
 						  symtab_hdr->sh_link,
@@ -1477,7 +1477,7 @@ mmix_elf_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
 
 		  /* Put a JMP insn at the stub; it goes with the
 		     R_MMIX_JMP reloc.  */
-		  bfd_put_32 (output_bfd, JMP_INSN_BYTE << 24,
+		  bfd_put_32 (info->output_bfd, JMP_INSN_BYTE << 24,
 			      contents
 			      + size
 			      + mmix_elf_section_data (input_section)
diff --git a/bfd/elf64-ppc.c b/bfd/elf64-ppc.c
index 7e41085ed91..5fca8f7bcb2 100644
--- a/bfd/elf64-ppc.c
+++ b/bfd/elf64-ppc.c
@@ -6580,7 +6580,7 @@ static const struct sfpr_def_parms save_res_funcs[] =
    their corresponding function descriptor symbol entries.  */
 
 static bool
-ppc64_elf_edit (bfd *obfd ATTRIBUTE_UNUSED, struct bfd_link_info *info)
+ppc64_elf_edit (struct bfd_link_info *info)
 {
   struct ppc_link_hash_table *htab;
 
@@ -10235,8 +10235,7 @@ size_global_entry_stubs (struct elf_link_hash_entry *h, void *inf)
 /* Set the sizes of the dynamic sections.  */
 
 static bool
-ppc64_elf_late_size_sections (bfd *output_bfd,
-			      struct bfd_link_info *info)
+ppc64_elf_late_size_sections (struct bfd_link_info *info)
 {
   struct ppc_link_hash_table *htab;
   bfd *dynobj;
@@ -10615,7 +10614,7 @@ ppc64_elf_late_size_sections (bfd *output_bfd,
 	    return false;
 	}
 
-      if (NO_OPD_RELOCS && abiversion (output_bfd) <= 1)
+      if (NO_OPD_RELOCS && abiversion (info->output_bfd) <= 1)
 	{
 	  if (!add_dynamic_entry (DT_PPC64_OPD, 0)
 	      || !add_dynamic_entry (DT_PPC64_OPDSZ, 0))
@@ -15511,8 +15510,7 @@ ppc64_glibc_dynamic_reloc (enum elf_ppc64_reloc_type r_type)
    accordingly.  */
 
 static int
-ppc64_elf_relocate_section (bfd *output_bfd,
-			    struct bfd_link_info *info,
+ppc64_elf_relocate_section (struct bfd_link_info *info,
 			    bfd *input_bfd,
 			    asection *input_section,
 			    bfd_byte *contents,
@@ -15556,7 +15554,7 @@ ppc64_elf_relocate_section (bfd *output_bfd,
     }
 
   local_got_ents = elf_local_got_ents (input_bfd);
-  TOCstart = elf_gp (output_bfd);
+  TOCstart = elf_gp (info->output_bfd);
   symtab_hdr = &elf_symtab_hdr (input_bfd);
   sym_hashes = elf_sym_hashes (input_bfd);
   is_opd = ppc64_elf_section_data (input_section)->sec_type == sec_opd;
@@ -15624,7 +15622,8 @@ ppc64_elf_relocate_section (bfd *output_bfd,
 	  sec = local_sections[r_symndx];
 	  sym_name = bfd_elf_sym_name (input_bfd, symtab_hdr, sym, sec);
 	  sym_type = ELF64_ST_TYPE (sym->st_info);
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 	  opd = get_opd_info (sec);
 	  if (opd != NULL && opd->adjust != NULL)
 	    {
@@ -15657,7 +15656,7 @@ ppc64_elf_relocate_section (bfd *output_bfd,
 	  sym_name = h_elf->root.root.string;
 	  sym_type = h_elf->type;
 	  if (sec != NULL
-	      && sec->owner == output_bfd
+	      && sec->owner == info->output_bfd
 	      && strcmp (sec->name, ".opd") == 0)
 	    {
 	      /* This is a symbol defined in a linker script.  All
@@ -16159,16 +16158,16 @@ ppc64_elf_relocate_section (bfd *output_bfd,
 	      offset = rel->r_offset;
 	      if (is_plt_seq_reloc (r_type1))
 		{
-		  bfd_put_32 (output_bfd, NOP, contents + offset);
+		  bfd_put_32 (info->output_bfd, NOP, contents + offset);
 		  if (r_type1 == R_PPC64_PLT_PCREL34
 		      || r_type1 == R_PPC64_PLT_PCREL34_NOTOC)
-		    bfd_put_32 (output_bfd, NOP, contents + offset + 4);
+		    bfd_put_32 (info->output_bfd, NOP, contents + offset + 4);
 		  rel[1].r_info = ELF64_R_INFO (STN_UNDEF, R_PPC64_NONE);
 		  break;
 		}
 
 	      if (r_type1 == R_PPC64_PLTCALL)
-		bfd_put_32 (output_bfd, NOP, contents + offset + 4);
+		bfd_put_32 (info->output_bfd, NOP, contents + offset + 4);
 
 	      if ((tls_mask & TLS_GDIE) != 0)
 		{
@@ -16223,16 +16222,16 @@ ppc64_elf_relocate_section (bfd *output_bfd,
 	      offset = rel->r_offset;
 	      if (is_plt_seq_reloc (r_type1))
 		{
-		  bfd_put_32 (output_bfd, NOP, contents + offset);
+		  bfd_put_32 (info->output_bfd, NOP, contents + offset);
 		  if (r_type1 == R_PPC64_PLT_PCREL34
 		      || r_type1 == R_PPC64_PLT_PCREL34_NOTOC)
-		    bfd_put_32 (output_bfd, NOP, contents + offset + 4);
+		    bfd_put_32 (info->output_bfd, NOP, contents + offset + 4);
 		  rel[1].r_info = ELF64_R_INFO (STN_UNDEF, R_PPC64_NONE);
 		  break;
 		}
 
 	      if (r_type1 == R_PPC64_PLTCALL)
-		bfd_put_32 (output_bfd, NOP, contents + offset + 4);
+		bfd_put_32 (info->output_bfd, NOP, contents + offset + 4);
 
 	      if (r_type1 == R_PPC64_REL24_NOTOC
 		  || r_type1 == R_PPC64_REL24_P9NOTOC
@@ -16272,7 +16271,7 @@ ppc64_elf_relocate_section (bfd *output_bfd,
 		    r_type = R_PPC64_TPREL64;
 		  else
 		    {
-		      bfd_put_64 (output_bfd, 1, contents + rel->r_offset);
+		      bfd_put_64 (info->output_bfd, 1, contents + rel->r_offset);
 		      r_type = R_PPC64_NONE;
 		    }
 		  rel->r_info = ELF64_R_INFO (r_symndx, r_type);
@@ -16283,7 +16282,7 @@ ppc64_elf_relocate_section (bfd *output_bfd,
 	      if ((tls_mask & TLS_LD) == 0
 		  && offset_in_range (input_section, rel->r_offset, 8))
 		{
-		  bfd_put_64 (output_bfd, 1, contents + rel->r_offset);
+		  bfd_put_64 (info->output_bfd, 1, contents + rel->r_offset);
 		  r_type = R_PPC64_NONE;
 		  rel->r_info = ELF64_R_INFO (r_symndx, r_type);
 		}
@@ -17047,7 +17046,7 @@ ppc64_elf_relocate_section (bfd *output_bfd,
 			outrel.r_info = ELF64_R_INFO (indx, R_PPC64_DTPMOD64);
 			if (tls_type == (TLS_TLS | TLS_GD))
 			  {
-			    BFD_ASSERT (count_and_swap_reloc_out (output_bfd,
+			    BFD_ASSERT (count_and_swap_reloc_out (info->output_bfd,
 								  &outrel,
 								  relgot));
 			    outrel.r_offset += 8;
@@ -17072,8 +17071,8 @@ ppc64_elf_relocate_section (bfd *output_bfd,
 			/* Write the .got section contents for the sake
 			   of prelink.  */
 			loc = got->contents + off;
-			bfd_put_64 (output_bfd, outrel.r_addend + relocation,
-				    loc);
+			bfd_put_64 (info->output_bfd,
+				    outrel.r_addend + relocation, loc);
 		      }
 
 		    if (indx == 0 && tls_type != (TLS_TLS | TLS_LD))
@@ -17089,7 +17088,7 @@ ppc64_elf_relocate_section (bfd *output_bfd,
 		      }
 		    if (!(info->enable_dt_relr
 			  && ELF64_R_TYPE (outrel.r_info) == R_PPC64_RELATIVE))
-		      BFD_ASSERT (count_and_swap_reloc_out (output_bfd,
+		      BFD_ASSERT (count_and_swap_reloc_out (info->output_bfd,
 							    &outrel, relgot));
 		  }
 
@@ -17114,12 +17113,12 @@ ppc64_elf_relocate_section (bfd *output_bfd,
 
 			if (tls_type & (TLS_GD | TLS_LD))
 			  {
-			    bfd_put_64 (output_bfd, relocation,
+			    bfd_put_64 (info->output_bfd, relocation,
 					got->contents + off + 8);
 			    relocation = 1;
 			  }
 		      }
-		    bfd_put_64 (output_bfd, relocation,
+		    bfd_put_64 (info->output_bfd, relocation,
 				got->contents + off);
 		  }
 	      }
@@ -17192,7 +17191,7 @@ ppc64_elf_relocate_section (bfd *output_bfd,
 			  || r_type == R_PPC64_PLT16_LO
 			  || r_type == R_PPC64_PLT16_LO_DS)
 			{
-			  got = (elf_gp (output_bfd)
+			  got = (elf_gp (info->output_bfd)
 				 + htab->sec_info[input_section->id].toc_off);
 			  relocation -= got;
 			}
@@ -17417,7 +17416,7 @@ ppc64_elf_relocate_section (bfd *output_bfd,
 	      skip = false;
 	      relocate = false;
 
-	      out_off = _bfd_elf_section_offset (output_bfd, info,
+	      out_off = _bfd_elf_section_offset (info->output_bfd, info,
 						 input_section, rel->r_offset);
 	      if (out_off == (bfd_vma) -1)
 		skip = true;
@@ -17575,8 +17574,8 @@ ppc64_elf_relocate_section (bfd *output_bfd,
 		  if (sreloc == NULL)
 		    abort ();
 
-		  BFD_ASSERT (count_and_swap_reloc_out (output_bfd, &outrel,
-							sreloc));
+		  BFD_ASSERT (count_and_swap_reloc_out (info->output_bfd,
+							&outrel, sreloc));
 		}
 
 	      if (!warned_dynamic
@@ -17926,7 +17925,7 @@ ppc64_elf_relocate_section (bfd *output_bfd,
       if (unresolved_reloc
 	  && !((input_section->flags & SEC_DEBUGGING) != 0
 	       && h->elf.def_dynamic)
-	  && _bfd_elf_section_offset (output_bfd, info, input_section,
+	  && _bfd_elf_section_offset (info->output_bfd, info, input_section,
 				      rel->r_offset) != (bfd_vma) -1)
 	{
 	  info->callbacks->einfo
@@ -18156,8 +18155,7 @@ ppc64_elf_output_symbol_hook (struct bfd_link_info *info,
    dynamic sections here.  */
 
 static bool
-ppc64_elf_finish_dynamic_symbol (bfd *output_bfd,
-				 struct bfd_link_info *info,
+ppc64_elf_finish_dynamic_symbol (struct bfd_link_info *info,
 				 struct elf_link_hash_entry *h,
 				 Elf_Internal_Sym *sym)
 {
@@ -18210,7 +18208,7 @@ ppc64_elf_finish_dynamic_symbol (bfd *output_bfd,
 	srel = htab->elf.sreldynrelro;
       else
 	srel = htab->elf.srelbss;
-      BFD_ASSERT (count_and_swap_reloc_out (output_bfd, &rela, srel));
+      BFD_ASSERT (count_and_swap_reloc_out (info->output_bfd, &rela, srel));
     }
 
   return true;
@@ -18247,8 +18245,7 @@ ppc64_elf_reloc_type_class (const struct bfd_link_info *info,
 /* Finish up the dynamic sections.  */
 
 static bool
-ppc64_elf_finish_dynamic_sections (bfd *output_bfd,
-				   struct bfd_link_info *info,
+ppc64_elf_finish_dynamic_sections (struct bfd_link_info *info,
 				   bfd_byte *buf)
 {
   struct ppc_link_hash_table *htab;
@@ -18294,7 +18291,7 @@ ppc64_elf_finish_dynamic_sections (bfd *output_bfd,
 	      break;
 
 	    case DT_PPC64_OPD:
-	      s = bfd_get_section_by_name (output_bfd, ".opd");
+	      s = bfd_get_section_by_name (info->output_bfd, ".opd");
 	      if (s == NULL)
 		continue;
 	      dyn.d_un.d_ptr = s->vma;
@@ -18309,7 +18306,7 @@ ppc64_elf_finish_dynamic_sections (bfd *output_bfd,
 	      break;
 
 	    case DT_PPC64_OPDSZ:
-	      s = bfd_get_section_by_name (output_bfd, ".opd");
+	      s = bfd_get_section_by_name (info->output_bfd, ".opd");
 	      if (s == NULL)
 		continue;
 	      dyn.d_un.d_val = s->size;
@@ -18337,7 +18334,7 @@ ppc64_elf_finish_dynamic_sections (bfd *output_bfd,
 	      continue;
 	    }
 
-	  bfd_elf64_swap_dyn_out (output_bfd, &dyn, dyncon);
+	  bfd_elf64_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	}
     }
 
@@ -18346,8 +18343,8 @@ ppc64_elf_finish_dynamic_sections (bfd *output_bfd,
     {
       /* Fill in the first entry in the global offset table.
 	 We use it to hold the link-time TOCbase.  */
-      bfd_put_64 (output_bfd,
-		  elf_gp (output_bfd) + TOC_BASE_OFF,
+      bfd_put_64 (info->output_bfd,
+		  elf_gp (info->output_bfd) + TOC_BASE_OFF,
 		  htab->elf.sgot->contents);
 
       /* Set .got entry size.  */
@@ -18367,7 +18364,7 @@ ppc64_elf_finish_dynamic_sections (bfd *output_bfd,
      brlt ourselves if emitrelocations.  */
   if (htab->brlt != NULL
       && htab->brlt->reloc_count != 0
-      && !_bfd_elf_link_output_relocs (output_bfd,
+      && !_bfd_elf_link_output_relocs (info->output_bfd,
 				       htab->brlt,
 				       elf_section_data (htab->brlt)->rela.hdr,
 				       elf_section_data (htab->brlt)->relocs,
@@ -18376,7 +18373,7 @@ ppc64_elf_finish_dynamic_sections (bfd *output_bfd,
 
   if (htab->glink != NULL
       && htab->glink->reloc_count != 0
-      && !_bfd_elf_link_output_relocs (output_bfd,
+      && !_bfd_elf_link_output_relocs (info->output_bfd,
 				       htab->glink,
 				       elf_section_data (htab->glink)->rela.hdr,
 				       elf_section_data (htab->glink)->relocs,
@@ -18387,7 +18384,7 @@ ppc64_elf_finish_dynamic_sections (bfd *output_bfd,
   if (htab->glink_eh_frame != NULL
       && htab->glink_eh_frame->size != 0
       && htab->glink_eh_frame->sec_info_type == SEC_INFO_TYPE_EH_FRAME
-      && !_bfd_elf_write_linker_section_eh_frame (output_bfd, info,
+      && !_bfd_elf_write_linker_section_eh_frame (info->output_bfd, info,
 						  htab->glink_eh_frame, buf))
     return false;
 
@@ -18405,7 +18402,7 @@ ppc64_elf_finish_dynamic_sections (bfd *output_bfd,
       if (s != NULL
 	  && s->size != 0
 	  && s->output_section != bfd_abs_section_ptr
-	  && !bfd_set_section_contents (output_bfd, s->output_section,
+	  && !bfd_set_section_contents (info->output_bfd, s->output_section,
 					s->contents, s->output_offset,
 					s->size))
 	return false;
@@ -18413,7 +18410,7 @@ ppc64_elf_finish_dynamic_sections (bfd *output_bfd,
       if (s != NULL
 	  && s->size != 0
 	  && s->output_section != bfd_abs_section_ptr
-	  && !bfd_set_section_contents (output_bfd, s->output_section,
+	  && !bfd_set_section_contents (info->output_bfd, s->output_section,
 					s->contents, s->output_offset,
 					s->size))
 	return false;
diff --git a/bfd/elf64-s390.c b/bfd/elf64-s390.c
index e9a7041d415..cbffbc99a78 100644
--- a/bfd/elf64-s390.c
+++ b/bfd/elf64-s390.c
@@ -1975,8 +1975,7 @@ allocate_dynrelocs (struct elf_link_hash_entry *h,
 /* Set the sizes of the dynamic sections.  */
 
 static bool
-elf_s390_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-			     struct bfd_link_info *info)
+elf_s390_late_size_sections (struct bfd_link_info *info)
 {
   struct elf_s390_link_hash_table *htab;
   bfd *dynobj;
@@ -2247,7 +2246,7 @@ elf_s390_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
 	_bfd_s390_elf_write_sframe_plt (info);
     }
 
-  return _bfd_elf_add_dynamic_tags (output_bfd, info, relocs);
+  return _bfd_elf_add_dynamic_tags (info, relocs);
 }
 
 /* Return the base VMA address which should be subtracted from real addresses
@@ -2301,8 +2300,7 @@ invalid_tls_insn (bfd *input_bfd,
 /* Relocate a 390 ELF section.  */
 
 static int
-elf_s390_relocate_section (bfd *output_bfd,
-			   struct bfd_link_info *info,
+elf_s390_relocate_section (struct bfd_link_info *info,
 			   bfd *input_bfd,
 			   asection *input_section,
 			   bfd_byte *contents,
@@ -2403,7 +2401,7 @@ elf_s390_relocate_section (bfd *output_bfd,
 		case R_390_GOTENT:
 		  {
 		    /* Write the PLT slot address into the GOT slot.  */
-		    bfd_put_64 (output_bfd, relocation,
+		    bfd_put_64 (info->output_bfd, relocation,
 				htab->elf.sgot->contents +
 				local_got_offsets[r_symndx]);
 		    relocation = (local_got_offsets[r_symndx] +
@@ -2423,7 +2421,8 @@ elf_s390_relocate_section (bfd *output_bfd,
 	      goto do_relocation;
 	    }
 	  else
-	    relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	    relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						  sym, &sec, rel);
 	}
       else
 	{
@@ -2565,7 +2564,7 @@ elf_s390_relocate_section (bfd *output_bfd,
 		    off &= ~1;
 		  else
 		    {
-		      bfd_put_64 (output_bfd, relocation,
+		      bfd_put_64 (info->output_bfd, relocation,
 				  htab->elf.sgot->contents + off);
 		      h->got.offset |= 1;
 		    }
@@ -2600,7 +2599,7 @@ elf_s390_relocate_section (bfd *output_bfd,
 		      unsigned short new_insn =
 			(0xc000 | (bfd_get_8 (input_bfd,
 					      contents + rel->r_offset - 1) & 0xf0));
-		      bfd_put_16 (output_bfd, new_insn,
+		      bfd_put_16 (info->output_bfd, new_insn,
 				  contents + rel->r_offset - 2);
 		      r_type = R_390_PC32DBL;
 		      rel->r_info = ELF64_R_INFO (r_symndx, r_type);
@@ -2629,7 +2628,7 @@ elf_s390_relocate_section (bfd *output_bfd,
 		off &= ~1;
 	      else
 		{
-		  bfd_put_64 (output_bfd, relocation,
+		  bfd_put_64 (info->output_bfd, relocation,
 			      htab->elf.sgot->contents + off);
 
 		  if (bfd_link_pic (info))
@@ -2649,7 +2648,7 @@ elf_s390_relocate_section (bfd *output_bfd,
 		      outrel.r_addend = relocation;
 		      loc = s->contents;
 		      loc += s->reloc_count++ * sizeof (Elf64_External_Rela);
-		      bfd_elf64_swap_reloca_out (output_bfd, &outrel, loc);
+		      bfd_elf64_swap_reloca_out (info->output_bfd, &outrel, loc);
 		    }
 
 		  local_got_offsets[r_symndx] |= 1;
@@ -2743,8 +2742,8 @@ elf_s390_relocate_section (bfd *output_bfd,
 		  if (op == 0xc000)
 		    {
 		      /* larl rX,<weak sym> -> lay rX,0(0)  */
-		      bfd_put_16 (output_bfd, 0xe300 | reg, insn_start);
-		      bfd_put_32 (output_bfd, 0x71, insn_start + 2);
+		      bfd_put_16 (info->output_bfd, 0xe300 | reg, insn_start);
+		      bfd_put_32 (info->output_bfd, 0x71, insn_start + 2);
 		      rel->r_info = ELF64_R_INFO (0, R_390_NONE);
 		      rel->r_addend = 0;
 		      continue;
@@ -2753,8 +2752,8 @@ elf_s390_relocate_section (bfd *output_bfd,
 		  else if (op == 0xc005)
 		    {
 		      /* brasl rX,<weak sym> -> jg .+2 (6-byte trap)  */
-		      bfd_put_16 (output_bfd, 0xc0f4, insn_start);
-		      bfd_put_32 (output_bfd, 0x1, insn_start + 2);
+		      bfd_put_16 (info->output_bfd, 0xc0f4, insn_start);
+		      bfd_put_32 (info->output_bfd, 0x1, insn_start + 2);
 		      rel->r_info = ELF64_R_INFO (0, R_390_NONE);
 		      rel->r_addend = 0;
 		      continue;
@@ -2860,8 +2859,8 @@ elf_s390_relocate_section (bfd *output_bfd,
 	      if (op == 0xc000)
 		{
 		  /* larl rX,<weak sym> -> lay rX,0(0)  */
-		  bfd_put_16 (output_bfd, 0xe300 | reg, insn_start);
-		  bfd_put_32 (output_bfd, 0x71, insn_start + 2);
+		  bfd_put_16 (info->output_bfd, 0xe300 | reg, insn_start);
+		  bfd_put_32 (info->output_bfd, 0x71, insn_start + 2);
 		  rel->r_info = ELF64_R_INFO (0, R_390_NONE);
 		  rel->r_addend = 0;
 		  continue;
@@ -2870,8 +2869,8 @@ elf_s390_relocate_section (bfd *output_bfd,
 	      else if (op == 0xc602)
 		{
 		  /* Emit a 6-byte NOP: jgnop .  */
-		  bfd_put_16 (output_bfd, 0xc004, insn_start);
-		  bfd_put_32 (output_bfd, 0x0, insn_start + 2);
+		  bfd_put_16 (info->output_bfd, 0xc004, insn_start);
+		  bfd_put_32 (info->output_bfd, 0x0, insn_start + 2);
 		  rel->r_info = ELF64_R_INFO (0, R_390_NONE);
 		  rel->r_addend = 0;
 		  continue;
@@ -2889,8 +2888,8 @@ elf_s390_relocate_section (bfd *output_bfd,
 		       || (op & 0xff00) == 0xc600)
 		{
 		  /* Emit a 6-byte trap: jg .+2  */
-		  bfd_put_16 (output_bfd, 0xc0f4, insn_start);
-		  bfd_put_32 (output_bfd, 0x1, insn_start + 2);
+		  bfd_put_16 (info->output_bfd, 0xc0f4, insn_start);
+		  bfd_put_32 (info->output_bfd, 0x1, insn_start + 2);
 		  rel->r_info = ELF64_R_INFO (0, R_390_NONE);
 		  rel->r_addend = 0;
 		  continue;
@@ -2929,7 +2928,7 @@ elf_s390_relocate_section (bfd *output_bfd,
 
 		  /* Need a dynamic relocation to get the real function
 		     address.  */
-		  outrel.r_offset = _bfd_elf_section_offset (output_bfd,
+		  outrel.r_offset = _bfd_elf_section_offset (info->output_bfd,
 							     info,
 							     input_section,
 							     rel->r_offset);
@@ -2957,7 +2956,7 @@ elf_s390_relocate_section (bfd *output_bfd,
 		    }
 
 		  sreloc = htab->elf.irelifunc;
-		  _bfd_elf_append_rela (output_bfd, sreloc, &outrel);
+		  _bfd_elf_append_rela (info->output_bfd, sreloc, &outrel);
 
 		  /* If this reloc is against an external symbol, we
 		     do not want to fiddle with the addend.  Otherwise,
@@ -3003,8 +3002,8 @@ elf_s390_relocate_section (bfd *output_bfd,
 	      relocate = false;
 
 	      outrel.r_offset =
-		_bfd_elf_section_offset (output_bfd, info, input_section,
-					 rel->r_offset);
+		_bfd_elf_section_offset (info->output_bfd, info,
+					 input_section, rel->r_offset);
 	      if (outrel.r_offset == (bfd_vma) -1)
 		skip = true;
 	      else if (outrel.r_offset == (bfd_vma) -2)
@@ -3081,7 +3080,7 @@ elf_s390_relocate_section (bfd *output_bfd,
 
 	      loc = sreloc->contents;
 	      loc += sreloc->reloc_count++ * sizeof (Elf64_External_Rela);
-	      bfd_elf64_swap_reloca_out (output_bfd, &outrel, loc);
+	      bfd_elf64_swap_reloca_out (info->output_bfd, &outrel, loc);
 
 	      /* If this reloc is against an external symbol, we do
 		 not want to fiddle with the addend.  Otherwise, we
@@ -3110,7 +3109,7 @@ elf_s390_relocate_section (bfd *output_bfd,
 		abort ();
 	      loc = sreloc->contents;
 	      loc += sreloc->reloc_count++ * sizeof (Elf64_External_Rela);
-	      bfd_elf64_swap_reloc_out (output_bfd, &outrel, loc);
+	      bfd_elf64_swap_reloc_out (info->output_bfd, &outrel, loc);
 	    }
 	  /* Fall through.  */
 
@@ -3134,7 +3133,8 @@ elf_s390_relocate_section (bfd *output_bfd,
 	      /* This relocation gets optimized away by the local exec
 		 access optimization.  */
 	      BFD_ASSERT (! unresolved_reloc);
-	      bfd_put_64 (output_bfd, -tpoff (info, relocation) + rel->r_addend,
+	      bfd_put_64 (info->output_bfd,
+			  -tpoff (info, relocation) + rel->r_addend,
 			  contents + rel->r_offset);
 	      continue;
 	    }
@@ -3181,14 +3181,14 @@ elf_s390_relocate_section (bfd *output_bfd,
 	      loc = htab->elf.srelgot->contents;
 	      loc += htab->elf.srelgot->reloc_count++
 		* sizeof (Elf64_External_Rela);
-	      bfd_elf64_swap_reloca_out (output_bfd, &outrel, loc);
+	      bfd_elf64_swap_reloca_out (info->output_bfd, &outrel, loc);
 
 	      if (r_type == R_390_TLS_GD64)
 		{
 		  if (indx == 0)
 		    {
 		      BFD_ASSERT (! unresolved_reloc);
-		      bfd_put_64 (output_bfd,
+		      bfd_put_64 (info->output_bfd,
 				  relocation - dtpoff_base (info),
 				  htab->elf.sgot->contents + off + GOT_ENTRY_SIZE);
 		    }
@@ -3199,7 +3199,7 @@ elf_s390_relocate_section (bfd *output_bfd,
 		      outrel.r_addend = 0;
 		      htab->elf.srelgot->reloc_count++;
 		      loc += sizeof (Elf64_External_Rela);
-		      bfd_elf64_swap_reloca_out (output_bfd, &outrel, loc);
+		      bfd_elf64_swap_reloca_out (info->output_bfd, &outrel, loc);
 		    }
 		}
 
@@ -3220,7 +3220,7 @@ elf_s390_relocate_section (bfd *output_bfd,
 	    }
 	  else
 	    {
-	      bfd_put_64 (output_bfd, htab->elf.sgot->output_offset + off,
+	      bfd_put_64 (info->output_bfd, htab->elf.sgot->output_offset + off,
 			  contents + rel->r_offset);
 	      continue;
 	    }
@@ -3249,7 +3249,7 @@ elf_s390_relocate_section (bfd *output_bfd,
 	    abort ();
 
 	  BFD_ASSERT (! unresolved_reloc);
-	  bfd_put_64 (output_bfd, -tpoff (info, relocation),
+	  bfd_put_64 (info->output_bfd, -tpoff (info, relocation),
 		      htab->elf.sgot->contents + off);
 	  relocation = htab->elf.sgot->output_offset + off;
 	  if (r_type == R_390_TLS_IEENT)
@@ -3281,14 +3281,14 @@ elf_s390_relocate_section (bfd *output_bfd,
 	      outrel.r_offset = (htab->elf.sgot->output_section->vma
 				 + htab->elf.sgot->output_offset + off);
 
-	      bfd_put_64 (output_bfd, 0,
+	      bfd_put_64 (info->output_bfd, 0,
 			  htab->elf.sgot->contents + off + GOT_ENTRY_SIZE);
 	      outrel.r_info = ELF64_R_INFO (0, R_390_TLS_DTPMOD);
 	      outrel.r_addend = 0;
 	      loc = htab->elf.srelgot->contents;
 	      loc += htab->elf.srelgot->reloc_count++
 		* sizeof (Elf64_External_Rela);
-	      bfd_elf64_swap_reloca_out (output_bfd, &outrel, loc);
+	      bfd_elf64_swap_reloca_out (info->output_bfd, &outrel, loc);
 	      htab->tls_ldm_got.offset |= 1;
 	    }
 	  relocation = htab->elf.sgot->output_offset + off;
@@ -3322,12 +3322,13 @@ elf_s390_relocate_section (bfd *output_bfd,
 		abort ();
 	      loc = sreloc->contents;
 	      loc += sreloc->reloc_count++ * sizeof (Elf64_External_Rela);
-	      bfd_elf64_swap_reloca_out (output_bfd, &outrel, loc);
+	      bfd_elf64_swap_reloca_out (info->output_bfd, &outrel, loc);
 	    }
 	  else
 	    {
 	      BFD_ASSERT (! unresolved_reloc);
-	      bfd_put_64 (output_bfd, -tpoff (info, relocation) + rel->r_addend,
+	      bfd_put_64 (info->output_bfd,
+			  -tpoff (info, relocation) + rel->r_addend,
 			  contents + rel->r_offset);
 	    }
 	  continue;
@@ -3390,8 +3391,10 @@ elf_s390_relocate_section (bfd *output_bfd,
 		    }
 		  insn0 = 0xeb000000 | (insn0 & 0x00f00000) | ry;
 		  insn1 = 0x000d;
-		  bfd_put_32 (output_bfd, insn0, contents + rel->r_offset);
-		  bfd_put_16 (output_bfd, insn1, contents + rel->r_offset + 4);
+		  bfd_put_32 (info->output_bfd,
+			      insn0, contents + rel->r_offset);
+		  bfd_put_16 (info->output_bfd,
+			      insn1, contents + rel->r_offset + 4);
 		}
 	    }
 	  else if (r_type == R_390_TLS_GDCALL)
@@ -3419,8 +3422,10 @@ elf_s390_relocate_section (bfd *output_bfd,
 		  insn0 = 0xe322c000;
 		  insn1 = 0x0004;
 		}
-	      bfd_put_32 (output_bfd, insn0, contents + rel->r_offset);
-	      bfd_put_16 (output_bfd, insn1, contents + rel->r_offset + 4);
+	      bfd_put_32 (info->output_bfd,
+			  insn0, contents + rel->r_offset);
+	      bfd_put_16 (info->output_bfd,
+			  insn1, contents + rel->r_offset + 4);
 	    }
 	  else if (r_type == R_390_TLS_LDCALL)
 	    {
@@ -3439,8 +3444,10 @@ elf_s390_relocate_section (bfd *output_bfd,
 		     brasl %r14,__tls_get_addr@plt -> brcl 0,. */
 		  insn0 = 0xc0040000;
 		  insn1 = 0x0000;
-		  bfd_put_32 (output_bfd, insn0, contents + rel->r_offset);
-		  bfd_put_16 (output_bfd, insn1, contents + rel->r_offset + 4);
+		  bfd_put_32 (info->output_bfd,
+			      insn0, contents + rel->r_offset);
+		  bfd_put_16 (info->output_bfd,
+			      insn1, contents + rel->r_offset + 4);
 		}
 	    }
 	  continue;
@@ -3455,7 +3462,7 @@ elf_s390_relocate_section (bfd *output_bfd,
       if (unresolved_reloc
 	  && !((input_section->flags & SEC_DEBUGGING) != 0
 	       && h->def_dynamic)
-	  && _bfd_elf_section_offset (output_bfd, info, input_section,
+	  && _bfd_elf_section_offset (info->output_bfd, info, input_section,
 				      rel->r_offset) != (bfd_vma) -1)
 	_bfd_error_handler
 	  /* xgettext:c-format */
@@ -3637,8 +3644,7 @@ elf_s390_finish_ifunc_symbol (bfd *output_bfd,
    dynamic sections here.  */
 
 static bool
-elf_s390_finish_dynamic_symbol (bfd *output_bfd,
-				struct bfd_link_info *info,
+elf_s390_finish_dynamic_symbol (struct bfd_link_info *info,
 				struct elf_link_hash_entry *h,
 				Elf_Internal_Sym *sym)
 {
@@ -3658,7 +3664,7 @@ elf_s390_finish_dynamic_symbol (bfd *output_bfd,
 	 it up.  */
       if (s390_is_ifunc_symbol_p (h) && h->def_regular)
 	{
-	  elf_s390_finish_ifunc_symbol (output_bfd, info, h,
+	  elf_s390_finish_ifunc_symbol (info->output_bfd, info, h,
 	    htab, h->plt.offset,
 	    eh->ifunc_resolver_address +
 	    eh->ifunc_resolver_section->output_offset +
@@ -3695,7 +3701,7 @@ elf_s390_finish_dynamic_symbol (bfd *output_bfd,
 	  /* The first instruction in the PLT entry is a LARL loading
 	     the address of the GOT slot.  We write the 4 byte
 	     immediate operand of the LARL instruction here.  */
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 		      (htab->elf.sgotplt->output_section->vma +
 		       htab->elf.sgotplt->output_offset + gotplt_offset
 		       - (htab->elf.splt->output_section->vma +
@@ -3703,16 +3709,16 @@ elf_s390_finish_dynamic_symbol (bfd *output_bfd,
 			  h->plt.offset))/2,
 		      htab->elf.splt->contents + h->plt.offset + 2);
 	  /* Fixup the relative branch to PLT 0 */
-	  bfd_put_32 (output_bfd, - (PLT_FIRST_ENTRY_SIZE +
+	  bfd_put_32 (info->output_bfd, - (PLT_FIRST_ENTRY_SIZE +
 				     (PLT_ENTRY_SIZE * plt_index) + 22)/2,
 		      htab->elf.splt->contents + h->plt.offset + 24);
 	  /* Fixup offset into .rela.plt section.  */
-	  bfd_put_32 (output_bfd, plt_index * sizeof (Elf64_External_Rela),
+	  bfd_put_32 (info->output_bfd, plt_index * sizeof (Elf64_External_Rela),
 		      htab->elf.splt->contents + h->plt.offset + 28);
 
 	  /* Fill in the entry in the global offset table.
 	     Points to instruction after GOT offset.  */
-	  bfd_put_64 (output_bfd,
+	  bfd_put_64 (info->output_bfd,
 		      (htab->elf.splt->output_section->vma
 		       + htab->elf.splt->output_offset
 		       + h->plt.offset
@@ -3727,7 +3733,7 @@ elf_s390_finish_dynamic_symbol (bfd *output_bfd,
 	  rela.r_addend = 0;
 	  loc = htab->elf.srelplt->contents + plt_index *
 	    sizeof (Elf64_External_Rela);
-	  bfd_elf64_swap_reloca_out (output_bfd, &rela, loc);
+	  bfd_elf64_swap_reloca_out (info->output_bfd, &rela, loc);
 
 	  if (!h->def_regular)
 	    {
@@ -3781,9 +3787,9 @@ elf_s390_finish_dynamic_symbol (bfd *output_bfd,
 	      /* For non-shared objects explicit GOT slots must be
 		 filled with the PLT slot address for pointer
 		 equality reasons.  */
-	      bfd_put_64 (output_bfd, (htab->elf.iplt->output_section->vma
-				       + htab->elf.iplt->output_offset
-				       + h->plt.offset),
+	      bfd_put_64 (info->output_bfd, (htab->elf.iplt->output_section->vma
+					     + htab->elf.iplt->output_offset
+					     + h->plt.offset),
 			  htab->elf.sgot->contents + h->got.offset);
 	      return true;
 	    }
@@ -3811,14 +3817,15 @@ elf_s390_finish_dynamic_symbol (bfd *output_bfd,
 	{
 	  BFD_ASSERT((h->got.offset & 1) == 0);
 	do_glob_dat:
-	  bfd_put_64 (output_bfd, (bfd_vma) 0, htab->elf.sgot->contents + h->got.offset);
+	  bfd_put_64 (info->output_bfd, 0,
+		      htab->elf.sgot->contents + h->got.offset);
 	  rela.r_info = ELF64_R_INFO (h->dynindx, R_390_GLOB_DAT);
 	  rela.r_addend = 0;
 	}
 
       loc = htab->elf.srelgot->contents;
       loc += htab->elf.srelgot->reloc_count++ * sizeof (Elf64_External_Rela);
-      bfd_elf64_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf64_swap_reloca_out (info->output_bfd, &rela, loc);
     }
 
   if (h->needs_copy)
@@ -3846,7 +3853,7 @@ elf_s390_finish_dynamic_symbol (bfd *output_bfd,
       else
 	s = htab->elf.srelbss;
       loc = s->contents + s->reloc_count++ * sizeof (Elf64_External_Rela);
-      bfd_elf64_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elf64_swap_reloca_out (info->output_bfd, &rela, loc);
     }
 
   /* Mark some specially defined symbols as absolute.  */
@@ -3899,8 +3906,7 @@ elf_s390_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
 /* Finish up the dynamic sections.  */
 
 static bool
-elf_s390_finish_dynamic_sections (bfd *output_bfd,
-				  struct bfd_link_info *info,
+elf_s390_finish_dynamic_sections (struct bfd_link_info *info,
 				  bfd_byte *buf)
 {
   struct elf_s390_link_hash_table *htab;
@@ -3967,7 +3973,7 @@ elf_s390_finish_dynamic_sections (bfd *output_bfd,
 	      break;
 	    }
 
-	  bfd_elf64_swap_dyn_out (output_bfd, &dyn, dyncon);
+	  bfd_elf64_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	}
 
       /* Fill in the special first entry in the procedure linkage table.  */
@@ -3979,7 +3985,7 @@ elf_s390_finish_dynamic_sections (bfd *output_bfd,
 	  /* The second instruction in the first PLT entry is a LARL
 	     loading the GOT pointer.  Fill in the LARL immediate
 	     address.  */
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 		      (s390_got_pointer (info)
 		       - htab->elf.splt->output_section->vma
 		       - htab->elf.splt->output_offset - 6)/2,
@@ -3995,15 +4001,15 @@ elf_s390_finish_dynamic_sections (bfd *output_bfd,
       /* Fill in the first three entries in the global offset table.  */
       if (htab->elf.hgot->root.u.def.section->size > 0)
 	{
-	  bfd_put_64 (output_bfd,
-		      (sdyn == NULL ? (bfd_vma) 0
+	  bfd_put_64 (info->output_bfd,
+		      (sdyn == NULL ? 0
 		       : sdyn->output_section->vma + sdyn->output_offset),
 		      htab->elf.hgot->root.u.def.section->contents);
 	  /* One entry for shared object struct ptr.  */
-	  bfd_put_64 (output_bfd, (bfd_vma) 0,
+	  bfd_put_64 (info->output_bfd, 0,
 		      htab->elf.hgot->root.u.def.section->contents + 8);
 	  /* One entry for _dl_runtime_resolve.  */
-	  bfd_put_64 (output_bfd, (bfd_vma) 0,
+	  bfd_put_64 (info->output_bfd, 0,
 		      htab->elf.hgot->root.u.def.section->contents + 16);
 	}
       if (htab->elf.sgot != NULL && htab->elf.sgot->size > 0)
@@ -4035,8 +4041,8 @@ elf_s390_finish_dynamic_sections (bfd *output_bfd,
 		  return false;
 
 		if (ELF_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
-		  elf_s390_finish_ifunc_symbol (output_bfd, info, NULL, htab,
-						local_plt[i].plt.offset,
+		  elf_s390_finish_ifunc_symbol (info->output_bfd, info, NULL,
+						htab, local_plt[i].plt.offset,
 						isym->st_value
 						+ sec->output_section->vma
 						+ sec->output_offset);
@@ -4069,7 +4075,7 @@ elf_s390_finish_dynamic_sections (bfd *output_bfd,
 	}
 
       if (htab->plt_eh_frame->sec_info_type == SEC_INFO_TYPE_EH_FRAME
-	  && !_bfd_elf_write_linker_section_eh_frame (output_bfd, info,
+	  && !_bfd_elf_write_linker_section_eh_frame (info->output_bfd, info,
 						      htab->plt_eh_frame, buf))
 	return NULL;
     }
@@ -4095,7 +4101,7 @@ elf_s390_finish_dynamic_sections (bfd *output_bfd,
 	}
       if (htab->plt_sframe->sec_info_type == SEC_INFO_TYPE_SFRAME)
 	{
-	  if (! _bfd_elf_merge_section_sframe (output_bfd, info,
+	  if (! _bfd_elf_merge_section_sframe (info->output_bfd, info,
 					       htab->plt_sframe,
 					       htab->plt_sframe->contents))
 	    return false;
diff --git a/bfd/elf64-sparc.c b/bfd/elf64-sparc.c
index 1aea5aa8114..0e28bc2e076 100644
--- a/bfd/elf64-sparc.c
+++ b/bfd/elf64-sparc.c
@@ -597,8 +597,7 @@ elf64_sparc_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
    which we cannot easily keep in the symbol hash table.  */
 
 static bool
-elf64_sparc_output_arch_syms (bfd *output_bfd ATTRIBUTE_UNUSED,
-			      struct bfd_link_info *info,
+elf64_sparc_output_arch_syms (struct bfd_link_info *info,
 			      void * flaginfo,
 			      int (*func) (void *, const char *,
 					   Elf_Internal_Sym *,
diff --git a/bfd/elf64-x86-64.c b/bfd/elf64-x86-64.c
index b3f008bd51d..575995d4957 100644
--- a/bfd/elf64-x86-64.c
+++ b/bfd/elf64-x86-64.c
@@ -3125,20 +3125,18 @@ need_got:
 }
 
 static bool
-elf_x86_64_early_size_sections (bfd *output_bfd, struct bfd_link_info *info)
+elf_x86_64_early_size_sections (struct bfd_link_info *info)
 {
   bfd *abfd;
 
   /* Scan relocations after rel_from_abs has been set on __ehdr_start.  */
-  for (abfd = info->input_bfds;
-       abfd != (bfd *) NULL;
-       abfd = abfd->link.next)
+  for (abfd = info->input_bfds; abfd != NULL; abfd = abfd->link.next)
     if (bfd_get_flavour (abfd) == bfd_target_elf_flavour
 	&& !_bfd_elf_link_iterate_on_relocs (abfd, info,
 					     elf_x86_64_scan_relocs))
       return false;
 
-  return _bfd_x86_elf_early_size_sections (output_bfd, info);
+  return _bfd_x86_elf_early_size_sections (info);
 }
 
 /* Return the relocation value for @tpoff relocation
@@ -3163,8 +3161,7 @@ elf_x86_64_tpoff (struct bfd_link_info *info, bfd_vma address)
 /* Relocate an x86_64 ELF section.  */
 
 static int
-elf_x86_64_relocate_section (bfd *output_bfd,
-			     struct bfd_link_info *info,
+elf_x86_64_relocate_section (struct bfd_link_info *info,
 			     bfd *input_bfd,
 			     asection *input_section,
 			     bfd_byte *contents,
@@ -3260,8 +3257,8 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 	  sym = local_syms + r_symndx;
 	  sec = local_sections[r_symndx];
 
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym,
-						&sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 	  st_size = sym->st_size;
 
 	  /* Relocate against local STT_GNU_IFUNC symbol.  */
@@ -3319,7 +3316,7 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 	  continue;
 	}
 
-      if (rel->r_addend == 0 && !ABI_64_P (output_bfd))
+      if (rel->r_addend == 0 && !ABI_64_P (info->output_bfd))
 	{
 	  if (r_type == R_X86_64_64)
 	    {
@@ -3420,7 +3417,7 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 			off &= ~1;
 		      else
 			{
-			  bfd_put_64 (output_bfd, relocation,
+			  bfd_put_64 (info->output_bfd, relocation,
 				      base_got->contents + off);
 			  /* Note that this is harmless for the GOTPLT64
 			     case, as -1 | 1 still is -1.  */
@@ -3490,7 +3487,7 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 	      goto do_relocation;
 
 	    case R_X86_64_32:
-	      if (ABI_64_P (output_bfd))
+	      if (ABI_64_P (info->output_bfd))
 		goto do_relocation;
 	      /* FALLTHROUGH */
 	    case R_X86_64_64:
@@ -3522,7 +3519,7 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 
 		  /* Need a dynamic relocation to get the real function
 		     address.  */
-		  outrel.r_offset = _bfd_elf_section_offset (output_bfd,
+		  outrel.r_offset = _bfd_elf_section_offset (info->output_bfd,
 							     info,
 							     input_section,
 							     rel->r_offset);
@@ -3566,7 +3563,7 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 		    sreloc = htab->elf.srelgot;
 		  else
 		    sreloc = htab->elf.irelplt;
-		  _bfd_elf_append_rela (output_bfd, sreloc, &outrel);
+		  _bfd_elf_append_rela (info->output_bfd, sreloc, &outrel);
 
 		  /* If this reloc is against an external symbol, we
 		     do not want to fiddle with the addend.  Otherwise,
@@ -3642,7 +3639,7 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 		    off &= ~1;
 		  else
 		    {
-		      bfd_put_64 (output_bfd, relocation,
+		      bfd_put_64 (info->output_bfd, relocation,
 				  base_got->contents + off);
 		      /* Note that this is harmless for the GOTPLT64 case,
 			 as -1 | 1 still is -1.  */
@@ -3677,7 +3674,7 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 		off &= ~1;
 	      else
 		{
-		  bfd_put_64 (output_bfd, relocation,
+		  bfd_put_64 (info->output_bfd, relocation,
 			      base_got->contents + off);
 		  local_got_offsets[r_symndx] |= 1;
 
@@ -3721,7 +3718,7 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 		  (info, input_section, h, sym, "R_X86_64_RELATIVE",
 		   &outrel);
 
-	      _bfd_elf_append_rela (output_bfd, s, &outrel);
+	      _bfd_elf_append_rela (info->output_bfd, s, &outrel);
 	    }
 
 	  if (off >= (bfd_vma) -2)
@@ -4016,8 +4013,8 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 	      relocate = false;
 
 	      outrel.r_offset =
-		_bfd_elf_section_offset (output_bfd, info, input_section,
-					 rel->r_offset);
+		_bfd_elf_section_offset (info->output_bfd, info,
+					 input_section, rel->r_offset);
 	      if (outrel.r_offset == (bfd_vma) -1)
 		skip = true;
 	      else if (outrel.r_offset == (bfd_vma) -2)
@@ -4057,7 +4054,7 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 			}
 		    }
 		  else if (r_type == R_X86_64_64
-			   && !ABI_64_P (output_bfd))
+			   && !ABI_64_P (info->output_bfd))
 		    {
 		      relocate = true;
 		      outrel.r_info = htab->r_info (0,
@@ -4138,7 +4135,7 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 		      (info, input_section, h, sym,
 		       relative_reloc_name, &outrel);
 
-		  _bfd_elf_append_rela (output_bfd, sreloc, &outrel);
+		  _bfd_elf_append_rela (info->output_bfd, sreloc, &outrel);
 		}
 
 	      /* If this reloc is against an external symbol, we do
@@ -4218,7 +4215,7 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 			leaq foo@tpoff(%rax), %rax
 			nopw 0x0(%rax,%rax,1)  */
 		  int largepic = 0;
-		  if (ABI_64_P (output_bfd))
+		  if (ABI_64_P (info->output_bfd))
 		    {
 		      if (roff + 5 >= input_section->size)
 			goto corrupt_input;
@@ -4261,7 +4258,7 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 		  if (roff + 8 + largepic >= input_section->size)
 		    goto corrupt_input;
 
-		  bfd_put_32 (output_bfd,
+		  bfd_put_32 (info->output_bfd,
 			      elf_x86_64_tpoff (info, relocation),
 			      contents + roff + 8 + largepic);
 		  /* Skip R_X86_64_PC32, R_X86_64_PLT32,
@@ -4288,13 +4285,13 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 		    goto corrupt_input;
 		  type = bfd_get_8 (input_bfd, contents + roff - 3);
 		  val = bfd_get_8 (input_bfd, contents + roff - 1);
-		  bfd_put_8 (output_bfd,
+		  bfd_put_8 (info->output_bfd,
 			     (type & 0x48) | ((type >> 2) & 1),
 			     contents + roff - 3);
-		  bfd_put_8 (output_bfd, 0xc7, contents + roff - 2);
-		  bfd_put_8 (output_bfd, 0xc0 | ((val >> 3) & 7),
+		  bfd_put_8 (info->output_bfd, 0xc7, contents + roff - 2);
+		  bfd_put_8 (info->output_bfd, 0xc0 | ((val >> 3) & 7),
 			     contents + roff - 1);
-		  bfd_put_32 (output_bfd,
+		  bfd_put_32 (info->output_bfd,
 			      elf_x86_64_tpoff (info, relocation),
 			      contents + roff);
 		  continue;
@@ -4318,14 +4315,14 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 		  val = bfd_get_8 (input_bfd, contents + roff - 1);
 		  /* Move the R bits to the B bits in REX2 payload
 		     byte.  */
-		  bfd_put_8 (output_bfd,
+		  bfd_put_8 (info->output_bfd,
 			     ((rex2 & ~rex2_mask)
 			      | (rex2 & rex2_mask) >> 2),
 			     contents + roff - 3);
-		  bfd_put_8 (output_bfd, 0xc7, contents + roff - 2);
-		  bfd_put_8 (output_bfd, 0xc0 | ((val >> 3) & 7),
+		  bfd_put_8 (info->output_bfd, 0xc7, contents + roff - 2);
+		  bfd_put_8 (info->output_bfd, 0xc0 | ((val >> 3) & 7),
 			     contents + roff - 1);
-		  bfd_put_32 (output_bfd,
+		  bfd_put_32 (info->output_bfd,
 			      elf_x86_64_tpoff (info, relocation),
 			      contents + roff);
 		  continue;
@@ -4352,17 +4349,17 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 		      if (roff + 2 >= input_section->size)
 			goto corrupt_input;
 
-		      bfd_put_8 (output_bfd, 0x0f, contents + roff);
-		      bfd_put_8 (output_bfd, 0x1f, contents + roff + 1);
-		      bfd_put_8 (output_bfd, 0x00, contents + roff + 2);
+		      bfd_put_8 (info->output_bfd, 0x0f, contents + roff);
+		      bfd_put_8 (info->output_bfd, 0x1f, contents + roff + 1);
+		      bfd_put_8 (info->output_bfd, 0x00, contents + roff + 2);
 		    }
 		  else
 		    {
 		      if (roff + 1 >= input_section->size)
 			goto corrupt_input;
 
-		      bfd_put_8 (output_bfd, 0x66, contents + roff);
-		      bfd_put_8 (output_bfd, 0x90, contents + roff + 1);
+		      bfd_put_8 (info->output_bfd, 0x66, contents + roff);
+		      bfd_put_8 (info->output_bfd, 0x90, contents + roff + 1);
 		    }
 		  continue;
 		}
@@ -4404,19 +4401,19 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 			{
 			  if (roff < 3)
 			    goto corrupt_input;
-			  bfd_put_8 (output_bfd, 0x49,
+			  bfd_put_8 (info->output_bfd, 0x49,
 				     contents + roff - 3);
 			}
-		      else if (!ABI_64_P (output_bfd) && val == 0x44)
+		      else if (!ABI_64_P (info->output_bfd) && val == 0x44)
 			{
 			  if (roff < 3)
 			    goto corrupt_input;
-			  bfd_put_8 (output_bfd, 0x41,
+			  bfd_put_8 (info->output_bfd, 0x41,
 				     contents + roff - 3);
 			}
-		      bfd_put_8 (output_bfd, 0xc7,
+		      bfd_put_8 (info->output_bfd, 0xc7,
 				 contents + roff - 2);
-		      bfd_put_8 (output_bfd, 0xc0 | reg,
+		      bfd_put_8 (info->output_bfd, 0xc0 | reg,
 				 contents + roff - 1);
 		    }
 		  else if (reg == 4)
@@ -4427,19 +4424,19 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 			{
 			  if (roff < 3)
 			    goto corrupt_input;
-			  bfd_put_8 (output_bfd, 0x49,
+			  bfd_put_8 (info->output_bfd, 0x49,
 				     contents + roff - 3);
 			}
-		      else if (!ABI_64_P (output_bfd) && val == 0x44)
+		      else if (!ABI_64_P (info->output_bfd) && val == 0x44)
 			{
 			  if (roff < 3)
 			    goto corrupt_input;
-			  bfd_put_8 (output_bfd, 0x41,
+			  bfd_put_8 (info->output_bfd, 0x41,
 				     contents + roff - 3);
 			}
-		      bfd_put_8 (output_bfd, 0x81,
+		      bfd_put_8 (info->output_bfd, 0x81,
 				 contents + roff - 2);
-		      bfd_put_8 (output_bfd, 0xc0 | reg,
+		      bfd_put_8 (info->output_bfd, 0xc0 | reg,
 				 contents + roff - 1);
 		    }
 		  else
@@ -4449,22 +4446,22 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 			{
 			  if (roff < 3)
 			    goto corrupt_input;
-			  bfd_put_8 (output_bfd, 0x4d,
+			  bfd_put_8 (info->output_bfd, 0x4d,
 				     contents + roff - 3);
 			}
-		      else if (!ABI_64_P (output_bfd) && val == 0x44)
+		      else if (!ABI_64_P (info->output_bfd) && val == 0x44)
 			{
 			  if (roff < 3)
 			    goto corrupt_input;
-			  bfd_put_8 (output_bfd, 0x45,
+			  bfd_put_8 (info->output_bfd, 0x45,
 				     contents + roff - 3);
 			}
-		      bfd_put_8 (output_bfd, 0x8d,
+		      bfd_put_8 (info->output_bfd, 0x8d,
 				 contents + roff - 2);
-		      bfd_put_8 (output_bfd, 0x80 | reg | (reg << 3),
+		      bfd_put_8 (info->output_bfd, 0x80 | reg | (reg << 3),
 				 contents + roff - 1);
 		    }
-		  bfd_put_32 (output_bfd,
+		  bfd_put_32 (info->output_bfd,
 			      elf_x86_64_tpoff (info, relocation),
 			      contents + roff);
 		  continue;
@@ -4499,7 +4496,8 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 		      /* For MOVRS emit meaningless CS prefixes.  */
 		      if (bfd_get_8 (input_bfd, contents + roff - 4) == 0x0f)
 			{
-			  bfd_put_8 (output_bfd, 0x2e, contents + roff - 4);
+			  bfd_put_8 (info->output_bfd, 0x2e,
+				     contents + roff - 4);
 			  rex2 = 0x2e;
 			  rex2_mask = 0;
 			}
@@ -4507,15 +4505,15 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 		    }
 		  else
 		    type = 0x81;
-		  bfd_put_8 (output_bfd,
+		  bfd_put_8 (info->output_bfd,
 			     ((rex2 & ~rex2_mask)
 			      | (rex2 & rex2_mask) >> 2),
 			     contents + roff - 3);
-		  bfd_put_8 (output_bfd, type,
+		  bfd_put_8 (info->output_bfd, type,
 			     contents + roff - 2);
-		  bfd_put_8 (output_bfd, 0xc0 | reg,
+		  bfd_put_8 (info->output_bfd, 0xc0 | reg,
 			     contents + roff - 1);
-		  bfd_put_32 (output_bfd,
+		  bfd_put_32 (info->output_bfd,
 			      elf_x86_64_tpoff (info, relocation),
 			      contents + roff);
 		  continue;
@@ -4540,13 +4538,13 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 
 		  /* Replace 0f38 by meaningless CS prefixes, shifting the REX
 		     prefix forward.  */
-		  bfd_put_8 (output_bfd, 0x2e, contents + roff - 5);
-		  bfd_put_8 (output_bfd, 0x2e, contents + roff - 4);
-		  bfd_put_8 (output_bfd, rex, contents + roff - 3);
-		  bfd_put_8 (output_bfd, 0xc7, contents + roff - 2);
-		  bfd_put_8 (output_bfd, 0xc0 | reg, contents + roff - 1);
+		  bfd_put_8 (info->output_bfd, 0x2e, contents + roff - 5);
+		  bfd_put_8 (info->output_bfd, 0x2e, contents + roff - 4);
+		  bfd_put_8 (info->output_bfd, rex, contents + roff - 3);
+		  bfd_put_8 (info->output_bfd, 0xc7, contents + roff - 2);
+		  bfd_put_8 (info->output_bfd, 0xc0 | reg, contents + roff - 1);
 
-		  bfd_put_32 (output_bfd,
+		  bfd_put_32 (info->output_bfd,
 			      elf_x86_64_tpoff (info, relocation),
 			      contents + roff);
 		  continue;
@@ -4590,23 +4588,24 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 			rex2 |= REX_W;
 
 
-		      bfd_put_8 (output_bfd, 0x2e, contents + roff - 6);
-		      bfd_put_8 (output_bfd, 0x2e, contents + roff - 5);
-		      bfd_put_8 (output_bfd, 0xd5, contents + roff - 4);
-		      bfd_put_8 (output_bfd, rex2, contents + roff - 3);
-		      bfd_put_8 (output_bfd, 0xc7, contents + roff - 2);
-		      bfd_put_8 (output_bfd, 0xc0 | reg, contents + roff - 1);
-		      bfd_put_32 (output_bfd,
+		      bfd_put_8 (info->output_bfd, 0x2e, contents + roff - 6);
+		      bfd_put_8 (info->output_bfd, 0x2e, contents + roff - 5);
+		      bfd_put_8 (info->output_bfd, 0xd5, contents + roff - 4);
+		      bfd_put_8 (info->output_bfd, rex2, contents + roff - 3);
+		      bfd_put_8 (info->output_bfd, 0xc7, contents + roff - 2);
+		      bfd_put_8 (info->output_bfd, 0xc0 | reg,
+				 contents + roff - 1);
+		      bfd_put_32 (info->output_bfd,
 				  elf_x86_64_tpoff (info, relocation),
 				  contents + roff);
 		      continue;
 		    }
 
 		  byte1 = evex_move_r_to_b (byte1, false);
-		  bfd_put_8 (output_bfd, byte1, contents + roff - 5);
-		  bfd_put_8 (output_bfd, 0x81, contents + roff - 2);
-		  bfd_put_8 (output_bfd, 0xc0 | reg, contents + roff - 1);
-		  bfd_put_32 (output_bfd,
+		  bfd_put_8 (info->output_bfd, byte1, contents + roff - 5);
+		  bfd_put_8 (info->output_bfd, 0x81, contents + roff - 2);
+		  bfd_put_8 (info->output_bfd, 0xc0 | reg, contents + roff - 1);
+		  bfd_put_32 (info->output_bfd,
 			      elf_x86_64_tpoff (info, relocation),
 			      contents + roff);
 		  continue;
@@ -4659,7 +4658,7 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 		    outrel.r_addend = relocation - _bfd_x86_elf_dtpoff_base (info);
 		  else
 		    outrel.r_addend = 0;
-		  _bfd_elf_append_rela (output_bfd, sreloc, &outrel);
+		  _bfd_elf_append_rela (info->output_bfd, sreloc, &outrel);
 		}
 
 	      sreloc = htab->elf.srelgot;
@@ -4674,32 +4673,32 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 	      else
 		dr_type = R_X86_64_TPOFF64;
 
-	      bfd_put_64 (output_bfd, 0, htab->elf.sgot->contents + off);
+	      bfd_put_64 (info->output_bfd, 0, htab->elf.sgot->contents + off);
 	      outrel.r_addend = 0;
 	      if ((dr_type == R_X86_64_TPOFF64
 		   || dr_type == R_X86_64_TLSDESC) && indx == 0)
 		outrel.r_addend = relocation - _bfd_x86_elf_dtpoff_base (info);
 	      outrel.r_info = htab->r_info (indx, dr_type);
 
-	      _bfd_elf_append_rela (output_bfd, sreloc, &outrel);
+	      _bfd_elf_append_rela (info->output_bfd, sreloc, &outrel);
 
 	      if (GOT_TLS_GD_P (tls_type))
 		{
 		  if (indx == 0)
 		    {
 		      BFD_ASSERT (! unresolved_reloc);
-		      bfd_put_64 (output_bfd,
+		      bfd_put_64 (info->output_bfd,
 				  relocation - _bfd_x86_elf_dtpoff_base (info),
 				  htab->elf.sgot->contents + off + GOT_ENTRY_SIZE);
 		    }
 		  else
 		    {
-		      bfd_put_64 (output_bfd, 0,
+		      bfd_put_64 (info->output_bfd, 0,
 				  htab->elf.sgot->contents + off + GOT_ENTRY_SIZE);
 		      outrel.r_info = htab->r_info (indx,
 						    R_X86_64_DTPOFF64);
 		      outrel.r_offset += GOT_ENTRY_SIZE;
-		      _bfd_elf_append_rela (output_bfd, sreloc, &outrel);
+		      _bfd_elf_append_rela (info->output_bfd, sreloc, &outrel);
 		    }
 		}
 
@@ -4766,7 +4765,7 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 			addq foo@gottpoff(%rax), %rax
 			nopw 0x0(%rax,%rax,1)  */
 		  int largepic = 0;
-		  if (ABI_64_P (output_bfd))
+		  if (ABI_64_P (info->output_bfd))
 		    {
 		      if (contents[roff + 5] == 0xb8)
 			{
@@ -4805,7 +4804,7 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 				- input_section->output_section->vma
 				- input_section->output_offset
 				- 12);
-		  bfd_put_32 (output_bfd, relocation,
+		  bfd_put_32 (info->output_bfd, relocation,
 			      contents + roff + 8 + largepic);
 		  /* Skip R_X86_64_PLT32/R_X86_64_PLTOFF64.  */
 		  rel++;
@@ -4833,9 +4832,9 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 		     0x8b.  */
 		  if (roff < 2)
 		    goto corrupt_input;
-		  bfd_put_8 (output_bfd, 0x8b, contents + roff - 2);
+		  bfd_put_8 (info->output_bfd, 0x8b, contents + roff - 2);
 
-		  bfd_put_32 (output_bfd,
+		  bfd_put_32 (info->output_bfd,
 			      htab->elf.sgot->output_section->vma
 			      + htab->elf.sgot->output_offset + off
 			      - rel->r_offset
@@ -4866,14 +4865,14 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 		    }
 		  if (prefix)
 		    {
-		      bfd_put_8 (output_bfd, 0x0f, contents + roff);
-		      bfd_put_8 (output_bfd, 0x1f, contents + roff + 1);
-		      bfd_put_8 (output_bfd, 0x00, contents + roff + 2);
+		      bfd_put_8 (info->output_bfd, 0x0f, contents + roff);
+		      bfd_put_8 (info->output_bfd, 0x1f, contents + roff + 1);
+		      bfd_put_8 (info->output_bfd, 0x00, contents + roff + 2);
 		    }
 		  else
 		    {
-		      bfd_put_8 (output_bfd, 0x66, contents + roff);
-		      bfd_put_8 (output_bfd, 0x90, contents + roff + 1);
+		      bfd_put_8 (info->output_bfd, 0x66, contents + roff);
+		      bfd_put_8 (info->output_bfd, 0x90, contents + roff + 1);
 		    }
 		  continue;
 		}
@@ -4918,7 +4917,7 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 			movq %fs:0, %eax  */
 
 	      BFD_ASSERT (r_type == R_X86_64_TPOFF32);
-	      if (ABI_64_P (output_bfd))
+	      if (ABI_64_P (info->output_bfd))
 		{
 		  if ((rel->r_offset + 5) >= input_section->size)
 		    goto corrupt_input;
@@ -4996,13 +4995,14 @@ elf_x86_64_relocate_section (bfd *output_bfd,
 	      outrel.r_offset = (htab->elf.sgot->output_section->vma
 				 + htab->elf.sgot->output_offset + off);
 
-	      bfd_put_64 (output_bfd, 0,
+	      bfd_put_64 (info->output_bfd, 0,
 			  htab->elf.sgot->contents + off);
-	      bfd_put_64 (output_bfd, 0,
+	      bfd_put_64 (info->output_bfd, 0,
 			  htab->elf.sgot->contents + off + GOT_ENTRY_SIZE);
 	      outrel.r_info = htab->r_info (0, R_X86_64_DTPMOD64);
 	      outrel.r_addend = 0;
-	      _bfd_elf_append_rela (output_bfd, htab->elf.srelgot, &outrel);
+	      _bfd_elf_append_rela (info->output_bfd,
+				    htab->elf.srelgot, &outrel);
 	      htab->tls_ld_or_ldm_got.offset |= 1;
 	    }
 	  relocation = htab->elf.sgot->output_section->vma
@@ -5039,7 +5039,7 @@ elf_x86_64_relocate_section (bfd *output_bfd,
       if (unresolved_reloc
 	  && !((input_section->flags & SEC_DEBUGGING) != 0
 	       && h->def_dynamic)
-	  && _bfd_elf_section_offset (output_bfd, info, input_section,
+	  && _bfd_elf_section_offset (info->output_bfd, info, input_section,
 				      rel->r_offset) != (bfd_vma) -1)
 	{
 	  switch (r_type)
@@ -5140,8 +5140,7 @@ elf_x86_64_relocate_section (bfd *output_bfd,
    dynamic sections here.  */
 
 static bool
-elf_x86_64_finish_dynamic_symbol (bfd *output_bfd,
-				  struct bfd_link_info *info,
+elf_x86_64_finish_dynamic_symbol (struct bfd_link_info *info,
 				  struct elf_link_hash_entry *h,
 				  Elf_Internal_Sym *sym)
 {
@@ -5248,9 +5247,9 @@ elf_x86_64_finish_dynamic_symbol (bfd *output_bfd,
       if ((plt_got_pcrel_offset + 0x80000000) > 0xffffffff)
 	/* xgettext:c-format */
 	info->callbacks->fatal (_("%pB: PC-relative offset overflow in PLT entry for `%s'\n"),
-				output_bfd, h->root.root.string);
+				info->output_bfd, h->root.root.string);
 
-      bfd_put_32 (output_bfd, plt_got_pcrel_offset,
+      bfd_put_32 (info->output_bfd, plt_got_pcrel_offset,
 		  (resolved_plt->contents + plt_offset
 		   + htab->plt.plt_got_offset));
 
@@ -5261,10 +5260,10 @@ elf_x86_64_finish_dynamic_symbol (bfd *output_bfd,
       if (!local_undefweak)
 	{
 	  if (htab->plt.has_plt0)
-	    bfd_put_64 (output_bfd, (plt->output_section->vma
-				     + plt->output_offset
-				     + h->plt.offset
-				     + htab->lazy_plt->plt_lazy_offset),
+	    bfd_put_64 (info->output_bfd, (plt->output_section->vma
+					   + plt->output_offset
+					   + h->plt.offset
+					   + htab->lazy_plt->plt_lazy_offset),
 			gotplt->contents + got_offset);
 
 	  /* Fill in the entry in the .rela.plt section.  */
@@ -5314,7 +5313,7 @@ elf_x86_64_finish_dynamic_symbol (bfd *output_bfd,
 		= h->plt.offset + htab->lazy_plt->plt_plt_insn_end;
 
 	      /* Put relocation index.  */
-	      bfd_put_32 (output_bfd, plt_index,
+	      bfd_put_32 (info->output_bfd, plt_index,
 			  (plt->contents + h->plt.offset
 			   + htab->lazy_plt->plt_reloc_offset));
 
@@ -5324,15 +5323,15 @@ elf_x86_64_finish_dynamic_symbol (bfd *output_bfd,
 	      if (plt0_offset > 0x80000000)
 		/* xgettext:c-format */
 		info->callbacks->fatal (_("%pB: branch displacement overflow in PLT entry for `%s'\n"),
-					output_bfd, h->root.root.string);
-	      bfd_put_32 (output_bfd, - plt0_offset,
+					info->output_bfd, h->root.root.string);
+	      bfd_put_32 (info->output_bfd, - plt0_offset,
 			  (plt->contents + h->plt.offset
 			   + htab->lazy_plt->plt_plt_offset));
 	    }
 
-	  bed = get_elf_backend_data (output_bfd);
+	  bed = get_elf_backend_data (info->output_bfd);
 	  loc = relplt->contents + plt_index * bed->s->sizeof_rela;
-	  bed->s->swap_reloca_out (output_bfd, &rela, loc);
+	  bed->s->swap_reloca_out (info->output_bfd, &rela, loc);
 	}
     }
   else if (eh->plt_got.offset != (bfd_vma) -1)
@@ -5377,9 +5376,9 @@ elf_x86_64_finish_dynamic_symbol (bfd *output_bfd,
 	  || (!got_after_plt && got_pcrel_offset > 0))
 	/* xgettext:c-format */
 	info->callbacks->fatal (_("%pB: PC-relative offset overflow in GOT PLT entry for `%s'\n"),
-				output_bfd, h->root.root.string);
+				info->output_bfd, h->root.root.string);
 
-      bfd_put_32 (output_bfd, got_pcrel_offset,
+      bfd_put_32 (info->output_bfd, got_pcrel_offset,
 		  (plt->contents + plt_offset
 		   + htab->non_lazy_plt->plt_got_offset));
     }
@@ -5487,9 +5486,9 @@ elf_x86_64_finish_dynamic_symbol (bfd *output_bfd,
 		  plt = htab->elf.splt ? htab->elf.splt : htab->elf.iplt;
 		  plt_offset =  h->plt.offset;
 		}
-	      bfd_put_64 (output_bfd, (plt->output_section->vma
-				       + plt->output_offset
-				       + plt_offset),
+	      bfd_put_64 (info->output_bfd, (plt->output_section->vma
+					     + plt->output_offset
+					     + plt_offset),
 			  htab->elf.sgot->contents + h->got.offset);
 	      return true;
 	    }
@@ -5515,7 +5514,7 @@ elf_x86_64_finish_dynamic_symbol (bfd *output_bfd,
 	{
 	  BFD_ASSERT((h->got.offset & 1) == 0);
 	do_glob_dat:
-	  bfd_put_64 (output_bfd, (bfd_vma) 0,
+	  bfd_put_64 (info->output_bfd, 0,
 		      htab->elf.sgot->contents + h->got.offset);
 	  rela.r_info = htab->r_info (h->dynindx, R_X86_64_GLOB_DAT);
 	  rela.r_addend = 0;
@@ -5528,7 +5527,7 @@ elf_x86_64_finish_dynamic_symbol (bfd *output_bfd,
 	  if (relgot == NULL || relgot->size == 0)
 	    {
 	      info->callbacks->fatal (_("%pB: Unable to generate dynamic relocs because a suitable section does not exist\n"),
-				      output_bfd);
+				      info->output_bfd);
 	      return false;
 	    }
 	  
@@ -5537,7 +5536,7 @@ elf_x86_64_finish_dynamic_symbol (bfd *output_bfd,
 	    _bfd_x86_elf_link_report_relative_reloc
 	      (info, relgot, h, sym, relative_reloc_name, &rela);
 
-	  _bfd_elf_append_rela (output_bfd, relgot, &rela);
+	  _bfd_elf_append_rela (info->output_bfd, relgot, &rela);
 	}
     }
 
@@ -5558,7 +5557,7 @@ elf_x86_64_finish_dynamic_symbol (bfd *output_bfd,
 	s = htab->elf.sreldynrelro;
       else
 	s = htab->elf.srelbss;
-      _bfd_elf_append_rela (output_bfd, s, &rela);
+      _bfd_elf_append_rela (info->output_bfd, s, &rela);
     }
 
   return true;
@@ -5575,8 +5574,7 @@ elf_x86_64_finish_local_dynamic_symbol (void **slot, void *inf)
   struct bfd_link_info *info
     = (struct bfd_link_info *) inf;
 
-  return elf_x86_64_finish_dynamic_symbol (info->output_bfd,
-					   info, h, NULL);
+  return elf_x86_64_finish_dynamic_symbol (info, h, NULL);
 }
 
 /* Finish up undefined weak symbol handling in PIE.  Fill its PLT entry
@@ -5594,8 +5592,7 @@ elf_x86_64_pie_finish_undefweak_symbol (struct bfd_hash_entry *bh,
       || h->dynindx != -1)
     return true;
 
-  return elf_x86_64_finish_dynamic_symbol (info->output_bfd,
-					   info, h, NULL);
+  return elf_x86_64_finish_dynamic_symbol (info, h, NULL);
 }
 
 /* Used to decide how to sort relocs in an optimal manner for the
@@ -5650,13 +5647,12 @@ elf_x86_64_reloc_type_class (const struct bfd_link_info *info,
 /* Finish up the dynamic sections.  */
 
 static bool
-elf_x86_64_finish_dynamic_sections (bfd *output_bfd,
-				    struct bfd_link_info *info,
+elf_x86_64_finish_dynamic_sections (struct bfd_link_info *info,
 				    bfd_byte *buf)
 {
   struct elf_x86_link_hash_table *htab;
 
-  htab = _bfd_x86_elf_finish_dynamic_sections (output_bfd, info, buf);
+  htab = _bfd_x86_elf_finish_dynamic_sections (info, buf);
   if (htab == NULL)
     return false;
 
@@ -5685,7 +5681,7 @@ elf_x86_64_finish_dynamic_sections (bfd *output_bfd,
 		  htab->lazy_plt->plt0_entry_size);
 	  /* Add offset for pushq GOT+8(%rip), since the instruction
 	     uses 6 bytes subtract this value.  */
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 		      (htab->elf.sgotplt->output_section->vma
 		       + htab->elf.sgotplt->output_offset
 		       + 8
@@ -5697,7 +5693,7 @@ elf_x86_64_finish_dynamic_sections (bfd *output_bfd,
 	  /* Add offset for the PC-relative instruction accessing
 	     GOT+16, subtracting the offset to the end of that
 	     instruction.  */
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 		      (htab->elf.sgotplt->output_section->vma
 		       + htab->elf.sgotplt->output_offset
 		       + 16
@@ -5710,7 +5706,7 @@ elf_x86_64_finish_dynamic_sections (bfd *output_bfd,
 
       if (htab->elf.tlsdesc_plt)
 	{
-	  bfd_put_64 (output_bfd, (bfd_vma) 0,
+	  bfd_put_64 (info->output_bfd, 0,
 		      htab->elf.sgot->contents + htab->elf.tlsdesc_got);
 
 	  memcpy (htab->elf.splt->contents + htab->elf.tlsdesc_plt,
@@ -5720,7 +5716,7 @@ elf_x86_64_finish_dynamic_sections (bfd *output_bfd,
 	  /* Add offset for pushq GOT+8(%rip), since ENDBR64 uses 4
 	     bytes and the instruction uses 6 bytes, subtract these
 	     values.  */
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 		      (htab->elf.sgotplt->output_section->vma
 		       + htab->elf.sgotplt->output_offset
 		       + 8
@@ -5734,7 +5730,7 @@ elf_x86_64_finish_dynamic_sections (bfd *output_bfd,
 	  /* Add offset for indirect branch via GOT+TDG, where TDG
 	     stands for htab->tlsdesc_got, subtracting the offset
 	     to the end of that instruction.  */
-	  bfd_put_32 (output_bfd,
+	  bfd_put_32 (info->output_bfd,
 		      (htab->elf.sgot->output_section->vma
 		       + htab->elf.sgot->output_offset
 		       + htab->elf.tlsdesc_got
@@ -5764,8 +5760,7 @@ elf_x86_64_finish_dynamic_sections (bfd *output_bfd,
 
 static bool
 elf_x86_64_output_arch_local_syms
-  (bfd *output_bfd ATTRIBUTE_UNUSED,
-   struct bfd_link_info *info,
+  (struct bfd_link_info *info,
    void *flaginfo ATTRIBUTE_UNUSED,
    int (*func) (void *, const char *,
 		Elf_Internal_Sym *,
diff --git a/bfd/elflink.c b/bfd/elflink.c
index e35a105ac4c..502c8068847 100644
--- a/bfd/elflink.c
+++ b/bfd/elflink.c
@@ -705,8 +705,7 @@ bfd_elf_link_mark_dynamic_symbol (struct bfd_link_info *info,
    this in case some dynamic object refers to this symbol.  */
 
 bool
-bfd_elf_record_link_assignment (bfd *output_bfd,
-				struct bfd_link_info *info,
+bfd_elf_record_link_assignment (struct bfd_link_info *info,
 				const char *name,
 				bool provide,
 				bool hidden)
@@ -767,7 +766,7 @@ bfd_elf_record_link_assignment (bfd *output_bfd,
     case bfd_link_hash_indirect:
       /* We had a versioned symbol in a dynamic library.  We make the
 	 the versioned symbol point to this one.  */
-      obed = get_elf_backend_data (output_bfd);
+      obed = get_elf_backend_data (info->output_bfd);
       hv = h;
       while (hv->root.type == bfd_link_hash_indirect
 	     || hv->root.type == bfd_link_hash_warning)
@@ -807,7 +806,7 @@ bfd_elf_record_link_assignment (bfd *output_bfd,
 
   if (hidden)
     {
-      obed = get_elf_backend_data (output_bfd);
+      obed = get_elf_backend_data (info->output_bfd);
       if (ELF_ST_VISIBILITY (h->other) != STV_INTERNAL)
 	h->other = (h->other & ~ELF_ST_VISIBILITY (-1)) | STV_HIDDEN;
       obed->elf_backend_hide_symbol (info, h, true);
@@ -991,8 +990,7 @@ elf_link_renumber_local_hash_table_dynsyms (struct elf_link_hash_entry *h,
 /* Return true if the dynamic symbol for a given section should be
    omitted when creating a shared library.  */
 bool
-_bfd_elf_omit_section_dynsym_default (bfd *output_bfd ATTRIBUTE_UNUSED,
-				      struct bfd_link_info *info,
+_bfd_elf_omit_section_dynsym_default (struct bfd_link_info *info,
 				      asection *p)
 {
   struct elf_link_hash_table *htab;
@@ -1021,10 +1019,8 @@ _bfd_elf_omit_section_dynsym_default (bfd *output_bfd ATTRIBUTE_UNUSED,
 }
 
 bool
-_bfd_elf_omit_section_dynsym_all
-    (bfd *output_bfd ATTRIBUTE_UNUSED,
-     struct bfd_link_info *info ATTRIBUTE_UNUSED,
-     asection *p ATTRIBUTE_UNUSED)
+_bfd_elf_omit_section_dynsym_all (struct bfd_link_info *info ATTRIBUTE_UNUSED,
+				  asection *p ATTRIBUTE_UNUSED)
 {
   return true;
 }
@@ -1039,8 +1035,7 @@ _bfd_elf_omit_section_dynsym_all
    that are stripped.)  */
 
 static unsigned long
-_bfd_elf_link_renumber_dynsyms (bfd *output_bfd,
-				struct bfd_link_info *info,
+_bfd_elf_link_renumber_dynsyms (struct bfd_link_info *info,
 				unsigned long *section_sym_count)
 {
   unsigned long dynsymcount = 0;
@@ -1049,13 +1044,13 @@ _bfd_elf_link_renumber_dynsyms (bfd *output_bfd,
   if (bfd_link_pic (info)
       || elf_hash_table (info)->is_relocatable_executable)
     {
-      elf_backend_data *obed = get_elf_backend_data (output_bfd);
+      elf_backend_data *obed = get_elf_backend_data (info->output_bfd);
       asection *p;
-      for (p = output_bfd->sections; p ; p = p->next)
+      for (p = info->output_bfd->sections; p ; p = p->next)
 	if ((p->flags & SEC_EXCLUDE) == 0
 	    && (p->flags & SEC_ALLOC) != 0
 	    && elf_hash_table (info)->dynamic_relocs
-	    && !obed->elf_backend_omit_section_dynsym (output_bfd, info, p))
+	    && !obed->elf_backend_omit_section_dynsym (info, p))
 	  {
 	    ++dynsymcount;
 	    if (do_sec)
@@ -3640,12 +3635,12 @@ _bfd_elf_symbol_refs_local_p (struct elf_link_hash_entry *h,
    aligned.  Returns the first TLS output section.  */
 
 struct bfd_section *
-bfd_elf_tls_setup (bfd *obfd, struct bfd_link_info *info)
+bfd_elf_tls_setup (struct bfd_link_info *info)
 {
   struct bfd_section *sec, *tls;
   unsigned int align = 0;
 
-  for (sec = obfd->sections; sec != NULL; sec = sec->next)
+  for (sec = info->output_bfd->sections; sec != NULL; sec = sec->next)
     if ((sec->flags & SEC_THREAD_LOCAL) != 0)
       break;
   tls = sec;
@@ -6848,8 +6843,7 @@ bfd_elf_size_group_sections (struct bfd_link_info *info)
    undefined it is initialized.  */
 
 bool
-bfd_elf_stack_segment_size (bfd *output_bfd,
-			    struct bfd_link_info *info,
+bfd_elf_stack_segment_size (struct bfd_link_info *info,
 			    const char *legacy_symbol,
 			    bfd_vma default_size)
 {
@@ -6869,11 +6863,11 @@ bfd_elf_stack_segment_size (bfd *output_bfd,
       if (info->stacksize)
 	/* xgettext:c-format */
 	_bfd_error_handler (_("%pB: stack size specified and %s set"),
-			    output_bfd, legacy_symbol);
+			    info->output_bfd, legacy_symbol);
       else if (h->root.u.def.section != bfd_abs_section_ptr)
 	/* xgettext:c-format */
 	_bfd_error_handler (_("%pB: %s not absolute"),
-			    output_bfd, legacy_symbol);
+			    info->output_bfd, legacy_symbol);
       else
 	info->stacksize = h->root.u.def.value;
     }
@@ -6890,10 +6884,11 @@ bfd_elf_stack_segment_size (bfd *output_bfd,
       struct bfd_link_hash_entry *bh = NULL;
 
       if (!(_bfd_generic_link_add_one_symbol
-	    (info, output_bfd, legacy_symbol,
+	    (info, info->output_bfd, legacy_symbol,
 	     BSF_GLOBAL, bfd_abs_section_ptr,
 	     info->stacksize >= 0 ? info->stacksize : 0,
-	     NULL, false, get_elf_backend_data (output_bfd)->collect, &bh)))
+	     NULL, false, get_elf_backend_data (info->output_bfd)->collect,
+	     &bh)))
 	return false;
 
       h = (struct elf_link_hash_entry *) bh;
@@ -6942,14 +6937,13 @@ elf_gc_sweep_symbol (struct elf_link_hash_entry *h, void *data)
    addresses of the various sections.  */
 
 bool
-bfd_elf_size_dynamic_sections (bfd *output_bfd,
+bfd_elf_size_dynamic_sections (struct bfd_link_info *info,
 			       const char *soname,
 			       const char *rpath,
 			       const char *filter_shlib,
 			       const char *audit,
 			       const char *depaudit,
 			       const char * const *auxiliary_filters,
-			       struct bfd_link_info *info,
 			       asection **sinterpptr)
 {
   bfd *dynobj;
@@ -6967,12 +6961,12 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
   elf_hash_table (info)->init_plt_refcount
     = elf_hash_table (info)->init_plt_offset;
 
-  obed = get_elf_backend_data (output_bfd);
+  obed = get_elf_backend_data (info->output_bfd);
 
   /* The backend may have to create some sections regardless of whether
      we're dynamic or not.  */
   if (obed->elf_backend_early_size_sections
-      && !obed->elf_backend_early_size_sections (output_bfd, info))
+      && !obed->elf_backend_early_size_sections (info))
     return false;
 
   dynobj = elf_hash_table (info)->dynobj;
@@ -7023,7 +7017,7 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
 	      char *newname, *p, leading_char;
 	      struct elf_link_hash_entry *newh;
 
-	      leading_char = bfd_get_symbol_leading_char (output_bfd);
+	      leading_char = bfd_get_symbol_leading_char (info->output_bfd);
 	      name = d->pattern;
 	      namelen = strlen (name) + (leading_char != '\0');
 	      verstr = t->name;
@@ -7153,7 +7147,7 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
 	    }
 
 	  s->size = size;
-	  s->contents = (unsigned char *) bfd_alloc (output_bfd, s->size);
+	  s->contents = bfd_alloc (info->output_bfd, s->size);
 	  if (s->contents == NULL && s->size != 0)
 	    return false;
 	  s->alloced = 1;
@@ -7190,7 +7184,7 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
 	    {
 	      size_t indx;
 
-	      name = lbasename (bfd_get_filename (output_bfd));
+	      name = lbasename (bfd_get_filename (info->output_bfd));
 	      def.vd_hash = bfd_elf_hash (name);
 	      indx = _bfd_elf_strtab_add (elf_hash_table (info)->dynstr,
 					  name, false);
@@ -7200,7 +7194,7 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
 	    }
 	  defaux.vda_next = 0;
 
-	  _bfd_elf_swap_verdef_out (output_bfd, &def,
+	  _bfd_elf_swap_verdef_out (info->output_bfd, &def,
 				    (Elf_External_Verdef *) p);
 	  p += sizeof (Elf_External_Verdef);
 	  if (info->create_default_symver)
@@ -7231,11 +7225,11 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
 			       + sizeof (Elf_External_Verdaux));
 	      else
 		def.vd_next = 0;
-	      _bfd_elf_swap_verdef_out (output_bfd, &def,
+	      _bfd_elf_swap_verdef_out (info->output_bfd, &def,
 					(Elf_External_Verdef *) p);
 	      p += sizeof (Elf_External_Verdef);
 	    }
-	  _bfd_elf_swap_verdaux_out (output_bfd, &defaux,
+	  _bfd_elf_swap_verdaux_out (info->output_bfd, &defaux,
 				     (Elf_External_Verdaux *) p);
 	  p += sizeof (Elf_External_Verdaux);
 
@@ -7289,7 +7283,7 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
 		def.vd_next = (sizeof (Elf_External_Verdef)
 			       + (cdeps + 1) * sizeof (Elf_External_Verdaux));
 
-	      _bfd_elf_swap_verdef_out (output_bfd, &def,
+	      _bfd_elf_swap_verdef_out (info->output_bfd, &def,
 					(Elf_External_Verdef *) p);
 	      p += sizeof (Elf_External_Verdef);
 
@@ -7301,7 +7295,7 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
 		defaux.vda_next = sizeof (Elf_External_Verdaux);
 	      t->name_indx = defaux.vda_name;
 
-	      _bfd_elf_swap_verdaux_out (output_bfd, &defaux,
+	      _bfd_elf_swap_verdaux_out (info->output_bfd, &defaux,
 					 (Elf_External_Verdaux *) p);
 	      p += sizeof (Elf_External_Verdaux);
 
@@ -7324,13 +7318,13 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
 		  else
 		    defaux.vda_next = sizeof (Elf_External_Verdaux);
 
-		  _bfd_elf_swap_verdaux_out (output_bfd, &defaux,
+		  _bfd_elf_swap_verdaux_out (info->output_bfd, &defaux,
 					     (Elf_External_Verdaux *) p);
 		  p += sizeof (Elf_External_Verdaux);
 		}
 	    }
 
-	  elf_tdata (output_bfd)->cverdefs = cdefs;
+	  elf_tdata (info->output_bfd)->cverdefs = cdefs;
 	}
     }
 
@@ -7357,7 +7351,7 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
       BFD_ASSERT (s != NULL);
 
       sinfo.info = info;
-      sinfo.vers = elf_tdata (output_bfd)->cverdefs;
+      sinfo.vers = elf_tdata (info->output_bfd)->cverdefs;
       if (sinfo.vers == 0)
 	sinfo.vers = 1;
       sinfo.failed = false;
@@ -7372,7 +7366,7 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
       if (sinfo.failed)
 	return false;
 
-      if (elf_tdata (output_bfd)->verref == NULL)
+      if (elf_tdata (info->output_bfd)->verref == NULL)
 	s->flags |= SEC_EXCLUDE;
       else
 	{
@@ -7384,7 +7378,7 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
 	  /* Build the version dependency section.  */
 	  size = 0;
 	  crefs = 0;
-	  for (vn = elf_tdata (output_bfd)->verref;
+	  for (vn = elf_tdata (info->output_bfd)->verref;
 	       vn != NULL;
 	       vn = vn->vn_nextref)
 	    {
@@ -7397,13 +7391,13 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
 	    }
 
 	  s->size = size;
-	  s->contents = (unsigned char *) bfd_alloc (output_bfd, s->size);
+	  s->contents = bfd_alloc (info->output_bfd, s->size);
 	  if (s->contents == NULL)
 	    return false;
 	  s->alloced = 1;
 
 	  p = s->contents;
-	  for (vn = elf_tdata (output_bfd)->verref;
+	  for (vn = elf_tdata (info->output_bfd)->verref;
 	       vn != NULL;
 	       vn = vn->vn_nextref)
 	    {
@@ -7433,7 +7427,7 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
 		vn->vn_next = (sizeof (Elf_External_Verneed)
 			       + caux * sizeof (Elf_External_Vernaux));
 
-	      _bfd_elf_swap_verneed_out (output_bfd, vn,
+	      _bfd_elf_swap_verneed_out (info->output_bfd, vn,
 					 (Elf_External_Verneed *) p);
 	      p += sizeof (Elf_External_Verneed);
 
@@ -7450,13 +7444,13 @@ bfd_elf_size_dynamic_sections (bfd *output_bfd,
 		  else
 		    a->vna_next = sizeof (Elf_External_Vernaux);
 
-		  _bfd_elf_swap_vernaux_out (output_bfd, a,
+		  _bfd_elf_swap_vernaux_out (info->output_bfd, a,
 					     (Elf_External_Vernaux *) p);
 		  p += sizeof (Elf_External_Vernaux);
 		}
 	    }
 
-	  elf_tdata (output_bfd)->cverrefs = crefs;
+	  elf_tdata (info->output_bfd)->cverrefs = crefs;
 	}
     }
 
@@ -7485,10 +7479,10 @@ error: creating an executable stack because of -z execstack command line option"
 warning: enabling an executable stack because of -z execstack command line option"));
 	}
 
-      elf_stack_flags (output_bfd) = PF_R | PF_W | PF_X;
+      elf_stack_flags (info->output_bfd) = PF_R | PF_W | PF_X;
     }
   else if (info->noexecstack)
-    elf_stack_flags (output_bfd) = PF_R | PF_W;
+    elf_stack_flags (info->output_bfd) = PF_R | PF_W;
   else
     {
       bfd *inputobj;
@@ -7571,7 +7565,7 @@ NOTE: This behaviour is deprecated and will be removed in a future version of th
 		    }
 		}
 	    }
-	  elf_stack_flags (output_bfd) = PF_R | PF_W | exec;
+	  elf_stack_flags (info->output_bfd) = PF_R | PF_W | exec;
 	}
 
       if (notesec && exec && bfd_link_relocatable (info)
@@ -7702,7 +7696,7 @@ NOTE: This behaviour is deprecated and will be removed in a future version of th
 	    return false;
 	}
 
-      s = bfd_get_section_by_name (output_bfd, ".preinit_array");
+      s = bfd_get_section_by_name (info->output_bfd, ".preinit_array");
       if (s != NULL && s->linker_has_input)
 	{
 	  /* DT_PREINIT_ARRAY is not allowed in shared library.  */
@@ -7733,14 +7727,14 @@ NOTE: This behaviour is deprecated and will be removed in a future version of th
 	      || !_bfd_elf_add_dynamic_entry (info, DT_PREINIT_ARRAYSZ, 0))
 	    return false;
 	}
-      s = bfd_get_section_by_name (output_bfd, ".init_array");
+      s = bfd_get_section_by_name (info->output_bfd, ".init_array");
       if (s != NULL && s->linker_has_input)
 	{
 	  if (!_bfd_elf_add_dynamic_entry (info, DT_INIT_ARRAY, 0)
 	      || !_bfd_elf_add_dynamic_entry (info, DT_INIT_ARRAYSZ, 0))
 	    return false;
 	}
-      s = bfd_get_section_by_name (output_bfd, ".fini_array");
+      s = bfd_get_section_by_name (info->output_bfd, ".fini_array");
       if (s != NULL && s->linker_has_input)
 	{
 	  if (!_bfd_elf_add_dynamic_entry (info, DT_FINI_ARRAY, 0)
@@ -7781,14 +7775,14 @@ NOTE: This behaviour is deprecated and will be removed in a future version of th
   /* The backend must work out the sizes of all the other dynamic
      sections.  */
   if (obed->elf_backend_late_size_sections != NULL
-      && !obed->elf_backend_late_size_sections (output_bfd, info))
+      && !obed->elf_backend_late_size_sections (info))
     return false;
 
   if (dynobj != NULL && elf_hash_table (info)->dynamic_sections_created)
     {
-      if (elf_tdata (output_bfd)->cverdefs)
+      if (elf_tdata (info->output_bfd)->cverdefs)
 	{
-	  unsigned int crefs = elf_tdata (output_bfd)->cverdefs;
+	  unsigned int crefs = elf_tdata (info->output_bfd)->cverdefs;
 
 	  if (!_bfd_elf_add_dynamic_entry (info, DT_VERDEF, 0)
 	      || !_bfd_elf_add_dynamic_entry (info, DT_VERDEFNUM, crefs))
@@ -7816,18 +7810,18 @@ NOTE: This behaviour is deprecated and will be removed in a future version of th
 	    return false;
 	}
 
-      if (elf_tdata (output_bfd)->cverrefs)
+      if (elf_tdata (info->output_bfd)->cverrefs)
 	{
-	  unsigned int crefs = elf_tdata (output_bfd)->cverrefs;
+	  unsigned int crefs = elf_tdata (info->output_bfd)->cverrefs;
 
 	  if (!_bfd_elf_add_dynamic_entry (info, DT_VERNEED, 0)
 	      || !_bfd_elf_add_dynamic_entry (info, DT_VERNEEDNUM, crefs))
 	    return false;
 	}
 
-      if ((elf_tdata (output_bfd)->cverrefs == 0
-	   && elf_tdata (output_bfd)->cverdefs == 0)
-	  || _bfd_elf_link_renumber_dynsyms (output_bfd, info, NULL) <= 1)
+      if ((elf_tdata (info->output_bfd)->cverrefs == 0
+	   && elf_tdata (info->output_bfd)->cverdefs == 0)
+	  || _bfd_elf_link_renumber_dynsyms (info, NULL) <= 1)
 	{
 	  asection *s;
 
@@ -7841,14 +7835,14 @@ NOTE: This behaviour is deprecated and will be removed in a future version of th
 /* Find the first non-excluded output section.  We'll use its
    section symbol for some emitted relocs.  */
 void
-_bfd_elf_init_1_index_section (bfd *output_bfd, struct bfd_link_info *info)
+_bfd_elf_init_1_index_section (struct bfd_link_info *info)
 {
   asection *s;
   asection *found = NULL;
 
-  for (s = output_bfd->sections; s != NULL; s = s->next)
+  for (s = info->output_bfd->sections; s != NULL; s = s->next)
     if ((s->flags & (SEC_EXCLUDE | SEC_ALLOC)) == SEC_ALLOC
-	&& !_bfd_elf_omit_section_dynsym_default (output_bfd, info, s))
+	&& !_bfd_elf_omit_section_dynsym_default (info, s))
       {
 	found = s;
 	if ((s->flags & SEC_THREAD_LOCAL) == 0)
@@ -7860,17 +7854,17 @@ _bfd_elf_init_1_index_section (bfd *output_bfd, struct bfd_link_info *info)
 /* Find two non-excluded output sections, one for code, one for data.
    We'll use their section symbols for some emitted relocs.  */
 void
-_bfd_elf_init_2_index_sections (bfd *output_bfd, struct bfd_link_info *info)
+_bfd_elf_init_2_index_sections (struct bfd_link_info *info)
 {
   asection *s;
   asection *found = NULL;
 
   /* Data first, since setting text_index_section changes
      _bfd_elf_omit_section_dynsym_default.  */
-  for (s = output_bfd->sections; s != NULL; s = s->next)
+  for (s = info->output_bfd->sections; s != NULL; s = s->next)
     if ((s->flags & (SEC_EXCLUDE | SEC_ALLOC)) == SEC_ALLOC
 	&& !(s->flags & SEC_READONLY)
-	&& !_bfd_elf_omit_section_dynsym_default (output_bfd, info, s))
+	&& !_bfd_elf_omit_section_dynsym_default (info, s))
       {
 	found = s;
 	if ((s->flags & SEC_THREAD_LOCAL) == 0)
@@ -7878,10 +7872,10 @@ _bfd_elf_init_2_index_sections (bfd *output_bfd, struct bfd_link_info *info)
       }
   elf_hash_table (info)->data_index_section = found;
 
-  for (s = output_bfd->sections; s != NULL; s = s->next)
+  for (s = info->output_bfd->sections; s != NULL; s = s->next)
     if ((s->flags & (SEC_EXCLUDE | SEC_ALLOC)) == SEC_ALLOC
 	&& (s->flags & SEC_READONLY)
-	&& !_bfd_elf_omit_section_dynsym_default (output_bfd, info, s))
+	&& !_bfd_elf_omit_section_dynsym_default (info, s))
       {
 	found = s;
 	break;
@@ -7889,11 +7883,16 @@ _bfd_elf_init_2_index_sections (bfd *output_bfd, struct bfd_link_info *info)
   elf_hash_table (info)->text_index_section = found;
 }
 
+void
+_bfd_elf_init_0_index_sections (struct bfd_link_info *info ATTRIBUTE_UNUSED)
+{
+}
+
 #define GNU_HASH_SECTION_NAME(bed)			    \
   (bed)->record_xhash_symbol != NULL ? ".MIPS.xhash" : ".gnu.hash"
 
 bool
-bfd_elf_size_dynsym_hash_dynstr (bfd *output_bfd, struct bfd_link_info *info)
+bfd_elf_size_dynsym_hash_dynstr (struct bfd_link_info *info)
 {
   elf_backend_data *obed;
   unsigned long section_sym_count;
@@ -7902,8 +7901,8 @@ bfd_elf_size_dynsym_hash_dynstr (bfd *output_bfd, struct bfd_link_info *info)
   if (!is_elf_hash_table (info->hash))
     return true;
 
-  obed = get_elf_backend_data (output_bfd);
-  obed->elf_backend_init_index_section (output_bfd, info);
+  obed = get_elf_backend_data (info->output_bfd);
+  obed->elf_backend_init_index_section (info);
 
   /* Assign dynsym indices.  In a shared library we generate a section
      symbol for each output section, which come first.  Next come all
@@ -7918,8 +7917,7 @@ bfd_elf_size_dynsym_hash_dynstr (bfd *output_bfd, struct bfd_link_info *info)
 
   if (elf_hash_table (info)->dynamic_sections_created
       || obed->always_renumber_dynsyms)
-    dynsymcount = _bfd_elf_link_renumber_dynsyms (output_bfd, info,
-						  &section_sym_count);
+    dynsymcount = _bfd_elf_link_renumber_dynsyms (info, &section_sym_count);
 
   if (elf_hash_table (info)->dynamic_sections_created)
     {
@@ -7935,7 +7933,7 @@ bfd_elf_size_dynsym_hash_dynstr (bfd *output_bfd, struct bfd_link_info *info)
       if ((s->flags & SEC_EXCLUDE) == 0)
 	{
 	  s->size = dynsymcount * sizeof (Elf_External_Versym);
-	  s->contents = (unsigned char *) bfd_zalloc (output_bfd, s->size);
+	  s->contents = (unsigned char *) bfd_zalloc (info->output_bfd, s->size);
 	  if (s->contents == NULL)
 	    return false;
 	  s->alloced = 1;
@@ -7954,7 +7952,7 @@ bfd_elf_size_dynsym_hash_dynstr (bfd *output_bfd, struct bfd_link_info *info)
       BFD_ASSERT (s != NULL);
       s->size = dynsymcount * obed->s->sizeof_sym;
 
-      s->contents = (unsigned char *) bfd_alloc (output_bfd, s->size);
+      s->contents = bfd_alloc (info->output_bfd, s->size);
       if (s->contents == NULL)
 	return false;
       s->alloced = 1;
@@ -8010,13 +8008,14 @@ bfd_elf_size_dynsym_hash_dynstr (bfd *output_bfd, struct bfd_link_info *info)
 	  BFD_ASSERT (s != NULL);
 	  hash_entry_size = elf_section_data (s)->this_hdr.sh_entsize;
 	  s->size = ((2 + bucketcount + dynsymcount) * hash_entry_size);
-	  s->contents = (unsigned char *) bfd_zalloc (output_bfd, s->size);
+	  s->contents = bfd_zalloc (info->output_bfd, s->size);
 	  if (s->contents == NULL)
 	    return false;
 	  s->alloced = 1;
 
-	  bfd_put (8 * hash_entry_size, output_bfd, bucketcount, s->contents);
-	  bfd_put (8 * hash_entry_size, output_bfd, dynsymcount,
+	  bfd_put (8 * hash_entry_size, info->output_bfd, bucketcount,
+		   s->contents);
+	  bfd_put (8 * hash_entry_size, info->output_bfd, dynsymcount,
 		   s->contents + hash_entry_size);
 	}
 
@@ -8040,7 +8039,7 @@ bfd_elf_size_dynsym_hash_dynstr (bfd *output_bfd, struct bfd_link_info *info)
 
 	  cinfo.hashval = cinfo.hashcodes + dynsymcount;
 	  cinfo.min_dynindx = -1;
-	  cinfo.output_bfd = output_bfd;
+	  cinfo.output_bfd = info->output_bfd;
 	  cinfo.bed = obed;
 
 	  /* Put all hash values in HASHCODES.  */
@@ -8070,23 +8069,23 @@ bfd_elf_size_dynsym_hash_dynstr (bfd *output_bfd, struct bfd_link_info *info)
 	      BFD_ASSERT (cinfo.min_dynindx == -1);
 	      free (cinfo.hashcodes);
 	      s->size = 5 * 4 + obed->s->arch_size / 8;
-	      contents = (unsigned char *) bfd_zalloc (output_bfd, s->size);
+	      contents = bfd_zalloc (info->output_bfd, s->size);
 	      if (contents == NULL)
 		return false;
 	      s->contents = contents;
 	      s->alloced = 1;
 	      /* 1 empty bucket.  */
-	      bfd_put_32 (output_bfd, 1, contents);
+	      bfd_put_32 (info->output_bfd, 1, contents);
 	      /* SYMIDX above the special symbol 0.  */
-	      bfd_put_32 (output_bfd, 1, contents + 4);
+	      bfd_put_32 (info->output_bfd, 1, contents + 4);
 	      /* Just one word for bitmask.  */
-	      bfd_put_32 (output_bfd, 1, contents + 8);
+	      bfd_put_32 (info->output_bfd, 1, contents + 8);
 	      /* Only hash fn bloom filter.  */
-	      bfd_put_32 (output_bfd, 0, contents + 12);
+	      bfd_put_32 (info->output_bfd, 0, contents + 12);
 	      /* No hashes are valid - empty bitmask.  */
-	      bfd_put (obed->s->arch_size, output_bfd, 0, contents + 16);
+	      bfd_put (obed->s->arch_size, info->output_bfd, 0, contents + 16);
 	      /* No hashes in the only bucket.  */
-	      bfd_put_32 (output_bfd, 0,
+	      bfd_put_32 (info->output_bfd, 0,
 			  contents + 16 + obed->s->arch_size / 8);
 	    }
 	  else
@@ -8149,7 +8148,7 @@ bfd_elf_size_dynsym_hash_dynstr (bfd *output_bfd, struct bfd_link_info *info)
 	      s->size += cinfo.maskbits / 8;
 	      if (obed->record_xhash_symbol != NULL)
 		s->size += cinfo.nsyms * 4;
-	      contents = (unsigned char *) bfd_zalloc (output_bfd, s->size);
+	      contents = bfd_zalloc (info->output_bfd, s->size);
 	      if (contents == NULL)
 		{
 		  free (cinfo.bitmask);
@@ -8159,18 +8158,18 @@ bfd_elf_size_dynsym_hash_dynstr (bfd *output_bfd, struct bfd_link_info *info)
 
 	      s->contents = contents;
 	      s->alloced = 1;
-	      bfd_put_32 (output_bfd, bucketcount, contents);
-	      bfd_put_32 (output_bfd, cinfo.symindx, contents + 4);
-	      bfd_put_32 (output_bfd, maskwords, contents + 8);
-	      bfd_put_32 (output_bfd, cinfo.shift2, contents + 12);
+	      bfd_put_32 (info->output_bfd, bucketcount, contents);
+	      bfd_put_32 (info->output_bfd, cinfo.symindx, contents + 4);
+	      bfd_put_32 (info->output_bfd, maskwords, contents + 8);
+	      bfd_put_32 (info->output_bfd, cinfo.shift2, contents + 12);
 	      contents += 16 + cinfo.maskbits / 8;
 
 	      for (i = 0; i < bucketcount; ++i)
 		{
 		  if (cinfo.counts[i] == 0)
-		    bfd_put_32 (output_bfd, 0, contents);
+		    bfd_put_32 (info->output_bfd, 0, contents);
 		  else
-		    bfd_put_32 (output_bfd, cinfo.indx[i], contents);
+		    bfd_put_32 (info->output_bfd, cinfo.indx[i], contents);
 		  contents += 4;
 		}
 
@@ -8200,8 +8199,8 @@ bfd_elf_size_dynsym_hash_dynstr (bfd *output_bfd, struct bfd_link_info *info)
 	      contents = s->contents + 16;
 	      for (i = 0; i < maskwords; ++i)
 		{
-		  bfd_put (obed->s->arch_size, output_bfd, cinfo.bitmask[i],
-			   contents);
+		  bfd_put (obed->s->arch_size, info->output_bfd,
+			   cinfo.bitmask[i], contents);
 		  contents += obed->s->arch_size / 8;
 		}
 
@@ -8213,7 +8212,7 @@ bfd_elf_size_dynsym_hash_dynstr (bfd *output_bfd, struct bfd_link_info *info)
       s = bfd_get_linker_section (dynobj, ".dynstr");
       BFD_ASSERT (s != NULL);
 
-      elf_finalize_dynstr (output_bfd, info);
+      elf_finalize_dynstr (info->output_bfd, info);
 
       s->size = _bfd_elf_strtab_size (elf_hash_table (info)->dynstr);
 
@@ -8513,8 +8512,7 @@ bfd_elf_set_dyn_lib_class (bfd *abfd, enum dynamic_lib_link_class lib_class)
    the linker ELF emulation code.  */
 
 struct bfd_link_needed_list *
-bfd_elf_get_needed_list (bfd *obfd ATTRIBUTE_UNUSED,
-			 struct bfd_link_info *info)
+bfd_elf_get_needed_list (struct bfd_link_info *info)
 {
   if (! is_elf_hash_table (info->hash))
     return NULL;
@@ -8525,8 +8523,7 @@ bfd_elf_get_needed_list (bfd *obfd ATTRIBUTE_UNUSED,
    hook for the linker ELF emulation code.  */
 
 struct bfd_link_needed_list *
-bfd_elf_get_runpath_list (bfd *obfd ATTRIBUTE_UNUSED,
-			  struct bfd_link_info *info)
+bfd_elf_get_runpath_list (struct bfd_link_info *info)
 {
   if (! is_elf_hash_table (info->hash))
     return NULL;
@@ -11045,8 +11042,7 @@ elf_link_output_extsym (struct bfd_hash_entry *bh, void *data)
 	   && elf_hash_table (flinfo->info)->dynamic_sections_created))
       && bed->elf_backend_finish_dynamic_symbol != NULL)
     {
-      if (!bed->elf_backend_finish_dynamic_symbol (flinfo->output_bfd,
-						   flinfo->info, h, &sym))
+      if (!bed->elf_backend_finish_dynamic_symbol (flinfo->info, h, &sym))
 	{
 	  eoinfo->failed = true;
 	  return false;
@@ -11404,7 +11400,7 @@ static bool
 elf_link_input_bfd (struct elf_final_link_info *flinfo, bfd *input_bfd)
 {
   int (*relocate_section)
-    (bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *,
+    (struct bfd_link_info *, bfd *, asection *, bfd_byte *,
      Elf_Internal_Rela *, Elf_Internal_Sym *, asection **);
   bfd *output_bfd;
   Elf_Internal_Shdr *symtab_hdr;
@@ -11964,11 +11960,11 @@ elf_link_input_bfd (struct elf_final_link_info *flinfo, bfd *input_bfd)
 	     corresponding to the output section, which will require
 	     the addend to be adjusted.  */
 
-	  ret = (*relocate_section) (output_bfd, flinfo->info,
-				     input_bfd, o, contents,
-				     internal_relocs,
-				     isymbuf,
-				     flinfo->sections);
+	  ret = relocate_section (flinfo->info,
+				  input_bfd, o, contents,
+				  internal_relocs,
+				  isymbuf,
+				  flinfo->sections);
 	  if (!ret)
 	    return false;
 
@@ -12573,10 +12569,9 @@ elf_output_implib (bfd *obfd, struct bfd_link_info *info)
 
   /* Filter symbols to appear in the import library.  */
   if (obed->elf_backend_filter_implib_symbols)
-    symcount = obed->elf_backend_filter_implib_symbols (obfd, info, sympp,
-							symcount);
+    symcount = obed->elf_backend_filter_implib_symbols (info, sympp, symcount);
   else
-    symcount = _bfd_elf_filter_global_symbols (obfd, info, sympp, symcount);
+    symcount = _bfd_elf_filter_global_symbols (info, sympp, symcount);
   if (symcount == 0)
     {
       bfd_set_error (bfd_error_no_symbols);
@@ -13320,7 +13315,7 @@ _bfd_elf_final_link (bfd *obfd, struct bfd_link_info *info)
      table, do it now.  */
   if (obed->elf_backend_output_arch_local_syms)
     {
-      if (!obed->elf_backend_output_arch_local_syms (obfd, info, &flinfo,
+      if (!obed->elf_backend_output_arch_local_syms (info, &flinfo,
 						     elf_link_output_symstrtab))
 	goto error_return;
     }
@@ -13448,7 +13443,7 @@ _bfd_elf_final_link (bfd *obfd, struct bfd_link_info *info)
   if (obed->elf_backend_output_arch_syms
       && (info->strip != strip_all || emit_relocs))
     {
-      if (!obed->elf_backend_output_arch_syms (obfd, info, &flinfo,
+      if (!obed->elf_backend_output_arch_syms (info, &flinfo,
 					       elf_link_output_symstrtab))
 	goto error_return;
     }
@@ -13788,8 +13783,7 @@ _bfd_elf_final_link (bfd *obfd, struct bfd_link_info *info)
   /* If we have created any dynamic sections, then output them.  */
   if (dynobj != NULL)
     {
-      if (!obed->elf_backend_finish_dynamic_sections (obfd, info,
-						      flinfo.contents))
+      if (!obed->elf_backend_finish_dynamic_sections (info, flinfo.contents))
 	goto error_return;
 
       /* Check for DT_TEXTREL (late, in case the backend removes it).  */
@@ -14651,8 +14645,7 @@ _bfd_elf_gc_keep (struct bfd_link_info *info)
 }
 
 bool
-bfd_elf_parse_eh_frame_entries (bfd *obfd ATTRIBUTE_UNUSED,
-				struct bfd_link_info *info)
+bfd_elf_parse_eh_frame_entries (struct bfd_link_info *info)
 {
   bfd *ibfd = info->input_bfds;
 
@@ -15068,7 +15061,7 @@ elf_gc_allocate_got_offsets (struct elf_link_hash_entry *h, void *arg)
   if (h->got.refcount > 0)
     {
       h->got.offset = gofarg->gotoff;
-      gofarg->gotoff += obed->got_elt_size (obfd, gofarg->info, h, NULL, 0);
+      gofarg->gotoff += obed->got_elt_size (gofarg->info, h, NULL, 0);
     }
   else
     h->got.offset = (bfd_vma) -1;
@@ -15079,7 +15072,7 @@ elf_gc_allocate_got_offsets (struct elf_link_hash_entry *h, void *arg)
 /* And an accompanying bit to work out final got entry offsets once
    we're done.  Should be called from final_link.  */
 
-bool
+static bool
 bfd_elf_gc_common_finalize_got_offsets (bfd *obfd,
 					struct bfd_link_info *info)
 {
@@ -15125,7 +15118,7 @@ bfd_elf_gc_common_finalize_got_offsets (bfd *obfd,
 	  if (local_got[j] > 0)
 	    {
 	      local_got[j] = gotoff;
-	      gotoff += obed->got_elt_size (obfd, info, NULL, i, j);
+	      gotoff += obed->got_elt_size (info, NULL, i, j);
 	    }
 	  else
 	    local_got[j] = (bfd_vma) -1;
@@ -15217,7 +15210,7 @@ bfd_elf_reloc_symbol_deleted_p (bfd_vma offset, void *cookie)
    sorted order, which is true for all known assemblers.  */
 
 int
-bfd_elf_discard_info (bfd *output_bfd, struct bfd_link_info *info)
+bfd_elf_discard_info (struct bfd_link_info *info)
 {
   struct elf_reloc_cookie cookie;
   asection *o;
@@ -15228,7 +15221,7 @@ bfd_elf_discard_info (bfd *output_bfd, struct bfd_link_info *info)
       || !is_elf_hash_table (info->hash))
     return 0;
 
-  o = bfd_get_section_by_name (output_bfd, ".stab");
+  o = bfd_get_section_by_name (info->output_bfd, ".stab");
   if (o != NULL)
     {
       asection *i;
@@ -15258,7 +15251,7 @@ bfd_elf_discard_info (bfd *output_bfd, struct bfd_link_info *info)
 
   o = NULL;
   if (info->eh_frame_hdr_type != COMPACT_EH_HDR)
-    o = bfd_get_section_by_name (output_bfd, ".eh_frame");
+    o = bfd_get_section_by_name (info->output_bfd, ".eh_frame");
   if (o != NULL)
     {
       asection *i;
@@ -15294,7 +15287,7 @@ bfd_elf_discard_info (bfd *output_bfd, struct bfd_link_info *info)
 	}
 
       eh_alignment = ((1 << o->alignment_power)
-		      * bfd_octets_per_byte (output_bfd, o));
+		      * bfd_octets_per_byte (info->output_bfd, o));
       /* Skip over zero terminator, and prevent empty sections from
 	 adding alignment padding at the end.  */
       for (i = o->map_tail.s; i != NULL; i = i->map_tail.s)
@@ -15328,7 +15321,7 @@ bfd_elf_discard_info (bfd *output_bfd, struct bfd_link_info *info)
 				_bfd_elf_adjust_eh_frame_global_symbol, NULL);
     }
 
-  o = bfd_get_section_by_name (output_bfd, ".sframe");
+  o = bfd_get_section_by_name (info->output_bfd, ".sframe");
   if (o != NULL)
     {
       asection *i;
@@ -15359,7 +15352,7 @@ bfd_elf_discard_info (bfd *output_bfd, struct bfd_link_info *info)
 	}
       /* Update the reference to the output .sframe section.  Used to
 	 determine later if PT_GNU_SFRAME segment is to be generated.  */
-      if (!_bfd_elf_set_section_sframe (output_bfd, info))
+      if (!_bfd_elf_set_section_sframe (info->output_bfd, info))
 	return -1;
     }
 
@@ -15565,13 +15558,12 @@ _bfd_elf_common_section (asection *sec ATTRIBUTE_UNUSED)
 }
 
 bfd_vma
-_bfd_elf_default_got_elt_size (bfd *obfd,
-			       struct bfd_link_info *info ATTRIBUTE_UNUSED,
+_bfd_elf_default_got_elt_size (struct bfd_link_info *info,
 			       struct elf_link_hash_entry *h ATTRIBUTE_UNUSED,
 			       bfd *ibfd ATTRIBUTE_UNUSED,
 			       unsigned long symndx ATTRIBUTE_UNUSED)
 {
-  elf_backend_data *obed = get_elf_backend_data (obfd);
+  elf_backend_data *obed = get_elf_backend_data (info->output_bfd);
   return obed->s->arch_size / 8;
 }
 
@@ -15793,8 +15785,7 @@ _bfd_elf_maybe_set_textrel (struct elf_link_hash_entry *h, void *inf)
 /* Add dynamic tags.  */
 
 bool
-_bfd_elf_add_dynamic_tags (bfd *output_bfd, struct bfd_link_info *info,
-			   bool need_dynamic_reloc)
+_bfd_elf_add_dynamic_tags (struct bfd_link_info *info, bool need_dynamic_reloc)
 {
   struct elf_link_hash_table *htab = elf_hash_table (info);
 
@@ -15808,7 +15799,7 @@ _bfd_elf_add_dynamic_tags (bfd *output_bfd, struct bfd_link_info *info,
 #define add_dynamic_entry(TAG, VAL) \
   _bfd_elf_add_dynamic_entry (info, TAG, VAL)
 
-      elf_backend_data *obed = get_elf_backend_data (output_bfd);
+      elf_backend_data *obed = get_elf_backend_data (info->output_bfd);
 
       if (bfd_link_executable (info))
 	{
diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c
index 6c004dbceb7..96da6d790d9 100644
--- a/bfd/elfnn-aarch64.c
+++ b/bfd/elfnn-aarch64.c
@@ -7033,8 +7033,7 @@ elfNN_aarch64_tls_relax (struct elf_aarch64_link_hash_table *globals,
 /* Relocate an AArch64 ELF section.  */
 
 static int
-elfNN_aarch64_relocate_section (bfd *output_bfd,
-				struct bfd_link_info *info,
+elfNN_aarch64_relocate_section (struct bfd_link_info *info,
 				bfd *input_bfd,
 				asection *input_section,
 				bfd_byte *contents,
@@ -7112,7 +7111,8 @@ elfNN_aarch64_relocate_section (bfd *output_bfd,
 	       (input_bfd, symtab_hdr->sh_link, sym->st_name),
 	       input_bfd, input_section, rel->r_offset, true);
 
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 
 	  /* Relocate against local STT_GNU_IFUNC symbol.  */
 	  if (!bfd_link_relocatable (info)
@@ -7208,7 +7208,8 @@ elfNN_aarch64_relocate_section (bfd *output_bfd,
 	save_addend = false;
 
       if (r == bfd_reloc_continue)
-	r = elfNN_aarch64_final_link_relocate (howto, input_bfd, output_bfd,
+	r = elfNN_aarch64_final_link_relocate (howto, input_bfd,
+					       info->output_bfd,
 					       input_section, contents, rel,
 					       relocation, info, sec,
 					       h, &unresolved_reloc,
@@ -7254,7 +7255,7 @@ elfNN_aarch64_relocate_section (bfd *output_bfd,
 		  loc = globals->root.srelgot->contents;
 		  loc += globals->root.srelgot->reloc_count++
 		    * RELOC_SIZE (htab);
-		  bfd_elfNN_swap_reloca_out (output_bfd, &rela, loc);
+		  bfd_elfNN_swap_reloca_out (info->output_bfd, &rela, loc);
 
 		  bfd_reloc_code_real_type real_type =
 		    elfNN_aarch64_bfd_reloc_from_type (input_bfd, r_type);
@@ -7266,13 +7267,13 @@ elfNN_aarch64_relocate_section (bfd *output_bfd,
 		      /* For local dynamic, don't generate DTPREL in any case.
 			 Initialize the DTPREL slot into zero, so we get module
 			 base address when invoke runtime TLS resolver.  */
-		      bfd_put_NN (output_bfd, 0,
+		      bfd_put_NN (info->output_bfd, 0,
 				  globals->root.sgot->contents + off
 				  + GOT_ENTRY_SIZE);
 		    }
 		  else if (indx == 0)
 		    {
-		      bfd_put_NN (output_bfd,
+		      bfd_put_NN (info->output_bfd,
 				  relocation - dtpoff_base (info),
 				  globals->root.sgot->contents + off
 				  + GOT_ENTRY_SIZE);
@@ -7293,17 +7294,17 @@ elfNN_aarch64_relocate_section (bfd *output_bfd,
 		      loc = globals->root.srelgot->contents;
 		      loc += globals->root.srelgot->reloc_count++
 			* RELOC_SIZE (globals);
-		      bfd_elfNN_swap_reloca_out (output_bfd, &rela, loc);
-		      bfd_put_NN (output_bfd, (bfd_vma) 0,
+		      bfd_elfNN_swap_reloca_out (info->output_bfd, &rela, loc);
+		      bfd_put_NN (info->output_bfd, (bfd_vma) 0,
 				  globals->root.sgot->contents + off
 				  + GOT_ENTRY_SIZE);
 		    }
 		}
 	      else
 		{
-		  bfd_put_NN (output_bfd, (bfd_vma) 1,
+		  bfd_put_NN (info->output_bfd, 1,
 			      globals->root.sgot->contents + off);
-		  bfd_put_NN (output_bfd,
+		  bfd_put_NN (info->output_bfd,
 			      relocation - dtpoff_base (info),
 			      globals->root.sgot->contents + off
 			      + GOT_ENTRY_SIZE);
@@ -7354,13 +7355,13 @@ elfNN_aarch64_relocate_section (bfd *output_bfd,
 		  loc += globals->root.srelgot->reloc_count++
 		    * RELOC_SIZE (htab);
 
-		  bfd_elfNN_swap_reloca_out (output_bfd, &rela, loc);
+		  bfd_elfNN_swap_reloca_out (info->output_bfd, &rela, loc);
 
-		  bfd_put_NN (output_bfd, rela.r_addend,
+		  bfd_put_NN (info->output_bfd, rela.r_addend,
 			      globals->root.sgot->contents + off);
 		}
 	      else
-		bfd_put_NN (output_bfd, relocation - tpoff_base (info),
+		bfd_put_NN (info->output_bfd, relocation - tpoff_base (info),
 			    globals->root.sgot->contents + off);
 
 	      symbol_got_offset_mark (input_bfd, h, r_symndx);
@@ -7413,12 +7414,12 @@ elfNN_aarch64_relocate_section (bfd *output_bfd,
 		  loc += globals->root.srelplt->reloc_count++
 		    * RELOC_SIZE (globals);
 
-		  bfd_elfNN_swap_reloca_out (output_bfd, &rela, loc);
+		  bfd_elfNN_swap_reloca_out (info->output_bfd, &rela, loc);
 
-		  bfd_put_NN (output_bfd, (bfd_vma) 0,
+		  bfd_put_NN (info->output_bfd, (bfd_vma) 0,
 			      globals->root.sgotplt->contents + off +
 			      globals->sgotplt_jump_table_size);
-		  bfd_put_NN (output_bfd, (bfd_vma) 0,
+		  bfd_put_NN (info->output_bfd, (bfd_vma) 0,
 			      globals->root.sgotplt->contents + off +
 			      globals->sgotplt_jump_table_size +
 			      GOT_ENTRY_SIZE);
@@ -7437,7 +7438,7 @@ elfNN_aarch64_relocate_section (bfd *output_bfd,
       if (unresolved_reloc
 	  && !((input_section->flags & SEC_DEBUGGING) != 0
 	       && h->def_dynamic)
-	  && _bfd_elf_section_offset (output_bfd, info, input_section,
+	  && _bfd_elf_section_offset (info->output_bfd, info, input_section,
 				      +rel->r_offset) != (bfd_vma) - 1)
 	{
 	  _bfd_error_handler
@@ -8707,8 +8708,7 @@ aarch64_map_one_stub (struct bfd_hash_entry *gen_entry, void *in_arg)
 /* Output mapping symbols for linker generated sections.  */
 
 static bool
-elfNN_aarch64_output_arch_local_syms (bfd *output_bfd,
-				      struct bfd_link_info *info,
+elfNN_aarch64_output_arch_local_syms (struct bfd_link_info *info,
 				      void *finfo,
 				      int (*func) (void *, const char *,
 						   Elf_Internal_Sym *,
@@ -8745,7 +8745,7 @@ elfNN_aarch64_output_arch_local_syms (bfd *output_bfd,
 	  osi.sec = stub_sec;
 
 	  osi.sec_shndx = _bfd_elf_section_from_bfd_section
-	    (output_bfd, osi.sec->output_section);
+	    (info->output_bfd, osi.sec->output_section);
 
 	  /* The first instruction in a stub is always a branch.  */
 	  if (!elfNN_aarch64_output_map_sym (&osi, AARCH64_MAP_INSN, 0))
@@ -8761,7 +8761,7 @@ elfNN_aarch64_output_arch_local_syms (bfd *output_bfd,
     return true;
 
   osi.sec_shndx = _bfd_elf_section_from_bfd_section
-    (output_bfd, htab->root.splt->output_section);
+    (info->output_bfd, htab->root.splt->output_section);
   osi.sec = htab->root.splt;
 
   elfNN_aarch64_output_map_sym (&osi, AARCH64_MAP_INSN, 0);
@@ -9550,8 +9550,7 @@ elfNN_aarch64_finish_relative_relocs (struct bfd_link_info *info)
    though !  */
 
 static bool
-elfNN_aarch64_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-				  struct bfd_link_info *info)
+elfNN_aarch64_late_size_sections (struct bfd_link_info *info)
 {
   struct elf_aarch64_link_hash_table *htab;
   bfd *dynobj;
@@ -9839,7 +9838,7 @@ elfNN_aarch64_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
 #define add_dynamic_entry(TAG, VAL)			\
       _bfd_elf_add_dynamic_entry (info, TAG, VAL)
 
-      if (!_bfd_elf_add_dynamic_tags (output_bfd, info, relocs))
+      if (!_bfd_elf_add_dynamic_tags (info, relocs))
 	return false;
 
       if (htab->root.splt->size != 0)
@@ -9849,7 +9848,7 @@ elfNN_aarch64_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
 	    return false;
 
 	  aarch64_plt_type plt_type
-	    = elf_aarch64_tdata (output_bfd)->sw_protections.plt_type;
+	    = elf_aarch64_tdata (info->output_bfd)->sw_protections.plt_type;
 	  if (plt_type == PLT_BTI_PAC
 	      && (!add_dynamic_entry (DT_AARCH64_BTI_PLT, 0)
 		  || !add_dynamic_entry (DT_AARCH64_PAC_PLT, 0)))
@@ -9864,13 +9863,13 @@ elfNN_aarch64_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
 	    return false;
 	}
 
-      if (is_aarch64_elf (output_bfd)
+      if (is_aarch64_elf (info->output_bfd)
 	  && htab->memtag_opts.memtag_mode != AARCH64_MEMTAG_MODE_NONE
 	  && !add_dynamic_entry (DT_AARCH64_MEMTAG_MODE,
 				 htab->memtag_opts.memtag_mode == AARCH64_MEMTAG_MODE_ASYNC))
 	return false;
 
-      if (is_aarch64_elf (output_bfd)
+      if (is_aarch64_elf (info->output_bfd)
 	  && htab->memtag_opts.memtag_stack == 1
 	  && !add_dynamic_entry (DT_AARCH64_MEMTAG_STACK,
 				 htab->memtag_opts.memtag_stack == 1))
@@ -10013,8 +10012,7 @@ elfNN_aarch64_create_small_pltn_entry (struct elf_link_hash_entry *h,
    _TLS_MODULE_BASE_, if needed.  */
 
 static bool
-elfNN_aarch64_early_size_sections (bfd *output_bfd,
-				   struct bfd_link_info *info)
+elfNN_aarch64_early_size_sections (struct bfd_link_info *info)
 {
   asection *tls_sec;
 
@@ -10033,10 +10031,10 @@ elfNN_aarch64_early_size_sections (bfd *output_bfd,
       if (tlsbase)
 	{
 	  struct bfd_link_hash_entry *h = NULL;
-	  elf_backend_data *bed = get_elf_backend_data (output_bfd);
+	  elf_backend_data *bed = get_elf_backend_data (info->output_bfd);
 
 	  if (!(_bfd_generic_link_add_one_symbol
-		(info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
+		(info, info->output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
 		 tls_sec, 0, NULL, false, bed->collect, &h)))
 	    return false;
 
@@ -10055,8 +10053,7 @@ elfNN_aarch64_early_size_sections (bfd *output_bfd,
    dynamic sections here.  */
 
 static bool
-elfNN_aarch64_finish_dynamic_symbol (bfd *output_bfd,
-				     struct bfd_link_info *info,
+elfNN_aarch64_finish_dynamic_symbol (struct bfd_link_info *info,
 				     struct elf_link_hash_entry *h,
 				     Elf_Internal_Sym *sym)
 {
@@ -10096,7 +10093,7 @@ elfNN_aarch64_finish_dynamic_symbol (bfd *output_bfd,
 	  || relplt == NULL)
 	abort ();
 
-      elfNN_aarch64_create_small_pltn_entry (h, htab, output_bfd, info);
+      elfNN_aarch64_create_small_pltn_entry (h, htab, info->output_bfd, info);
       if (!h->def_regular)
 	{
 	  /* Mark the symbol as undefined, rather than as defined in
@@ -10152,9 +10149,9 @@ elfNN_aarch64_finish_dynamic_symbol (bfd *output_bfd,
 		 contains the real function address if we need pointer
 		 equality.  We load the GOT entry with the PLT entry.  */
 	      plt = htab->root.splt ? htab->root.splt : htab->root.iplt;
-	      bfd_put_NN (output_bfd, (plt->output_section->vma
-				       + plt->output_offset
-				       + h->plt.offset),
+	      bfd_put_NN (info->output_bfd, (plt->output_section->vma
+					     + plt->output_offset
+					     + h->plt.offset),
 			  htab->root.sgot->contents
 			  + (h->got.offset & ~(bfd_vma) 1));
 	      return true;
@@ -10177,7 +10174,7 @@ elfNN_aarch64_finish_dynamic_symbol (bfd *output_bfd,
 	{
 	do_glob_dat:
 	  BFD_ASSERT ((h->got.offset & 1) == 0);
-	  bfd_put_NN (output_bfd, (bfd_vma) 0,
+	  bfd_put_NN (info->output_bfd, 0,
 		      htab->root.sgot->contents + h->got.offset);
 	  rela.r_info = ELFNN_R_INFO (h->dynindx, AARCH64_R (GLOB_DAT));
 	  rela.r_addend = 0;
@@ -10185,7 +10182,7 @@ elfNN_aarch64_finish_dynamic_symbol (bfd *output_bfd,
 
       loc = htab->root.srelgot->contents;
       loc += htab->root.srelgot->reloc_count++ * RELOC_SIZE (htab);
-      bfd_elfNN_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elfNN_swap_reloca_out (info->output_bfd, &rela, loc);
     }
 skip_got_reloc:
 
@@ -10212,7 +10209,7 @@ skip_got_reloc:
       else
 	s = htab->root.srelbss;
       loc = s->contents + s->reloc_count++ * RELOC_SIZE (htab);
-      bfd_elfNN_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elfNN_swap_reloca_out (info->output_bfd, &rela, loc);
     }
 
   /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute.  SYM may
@@ -10236,8 +10233,7 @@ elfNN_aarch64_finish_local_dynamic_symbol (void **slot, void *inf)
   struct bfd_link_info *info
     = (struct bfd_link_info *) inf;
 
-  return elfNN_aarch64_finish_dynamic_symbol (info->output_bfd,
-					      info, h, NULL);
+  return elfNN_aarch64_finish_dynamic_symbol (info, h, NULL);
 }
 
 static void
@@ -10300,8 +10296,7 @@ elfNN_aarch64_init_small_plt0_entry (bfd *output_bfd ATTRIBUTE_UNUSED,
 }
 
 static bool
-elfNN_aarch64_finish_dynamic_sections (bfd *output_bfd,
-				       struct bfd_link_info *info,
+elfNN_aarch64_finish_dynamic_sections (struct bfd_link_info *info,
 				       bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   struct elf_aarch64_link_hash_table *htab;
@@ -10362,7 +10357,7 @@ elfNN_aarch64_finish_dynamic_sections (bfd *output_bfd,
 	      break;
 	    }
 
-	  bfd_elfNN_swap_dyn_out (output_bfd, &dyn, dyncon);
+	  bfd_elfNN_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	}
 
     }
@@ -10370,19 +10365,19 @@ elfNN_aarch64_finish_dynamic_sections (bfd *output_bfd,
   /* Fill in the special first entry in the procedure linkage table.  */
   if (htab->root.splt && htab->root.splt->size > 0)
     {
-      elfNN_aarch64_init_small_plt0_entry (output_bfd, htab);
+      elfNN_aarch64_init_small_plt0_entry (info->output_bfd, htab);
 
       if (htab->root.tlsdesc_plt && !(info->flags & DF_BIND_NOW))
 	{
 	  BFD_ASSERT (htab->root.tlsdesc_got != (bfd_vma)-1);
-	  bfd_put_NN (output_bfd, (bfd_vma) 0,
+	  bfd_put_NN (info->output_bfd, 0,
 		      htab->root.sgot->contents + htab->root.tlsdesc_got);
 
 	  const bfd_byte *entry = elfNN_aarch64_tlsdesc_small_plt_entry;
 	  htab->tlsdesc_plt_entry_size = PLT_TLSDESC_ENTRY_SIZE;
 
 	  aarch64_plt_type plt_type
-	    = elf_aarch64_tdata (output_bfd)->sw_protections.plt_type;
+	    = elf_aarch64_tdata (info->output_bfd)->sw_protections.plt_type;
 	  if (plt_type & PLT_BTI)
 	    entry = elfNN_aarch64_tlsdesc_small_plt_bti_entry;
 
@@ -10420,27 +10415,27 @@ elfNN_aarch64_finish_dynamic_sections (bfd *output_bfd,
 	      }
 
 	    /* adrp x2, DT_TLSDESC_GOT */
-	    elf_aarch64_update_plt_entry (output_bfd,
+	    elf_aarch64_update_plt_entry (info->output_bfd,
 					  BFD_RELOC_AARCH64_ADR_HI21_PCREL,
 					  plt_entry + 4,
 					  (PG (dt_tlsdesc_got)
 					   - PG (adrp1_addr)));
 
 	    /* adrp x3, 0 */
-	    elf_aarch64_update_plt_entry (output_bfd,
+	    elf_aarch64_update_plt_entry (info->output_bfd,
 					  BFD_RELOC_AARCH64_ADR_HI21_PCREL,
 					  plt_entry + 8,
 					  (PG (pltgot_addr)
 					   - PG (adrp2_addr)));
 
 	    /* ldr x2, [x2, #0] */
-	    elf_aarch64_update_plt_entry (output_bfd,
+	    elf_aarch64_update_plt_entry (info->output_bfd,
 					  BFD_RELOC_AARCH64_LDSTNN_LO12,
 					  plt_entry + 12,
 					  PG_OFFSET (dt_tlsdesc_got));
 
 	    /* add x3, x3, 0 */
-	    elf_aarch64_update_plt_entry (output_bfd,
+	    elf_aarch64_update_plt_entry (info->output_bfd,
 					  BFD_RELOC_AARCH64_ADD_LO12,
 					  plt_entry + 16,
 					  PG_OFFSET (pltgot_addr));
@@ -10460,14 +10455,12 @@ elfNN_aarch64_finish_dynamic_sections (bfd *output_bfd,
       /* Fill in the first three entries in the global offset table.  */
       if (htab->root.sgotplt->size > 0)
 	{
-	  bfd_put_NN (output_bfd, (bfd_vma) 0, htab->root.sgotplt->contents);
+	  bfd_put_NN (info->output_bfd, 0, htab->root.sgotplt->contents);
 
 	  /* Write GOT[1] and GOT[2], needed for the dynamic linker.  */
-	  bfd_put_NN (output_bfd,
-		      (bfd_vma) 0,
+	  bfd_put_NN (info->output_bfd, 0,
 		      htab->root.sgotplt->contents + GOT_ENTRY_SIZE);
-	  bfd_put_NN (output_bfd,
-		      (bfd_vma) 0,
+	  bfd_put_NN (info->output_bfd, 0,
 		      htab->root.sgotplt->contents + GOT_ENTRY_SIZE * 2);
 	}
 
@@ -10477,7 +10470,7 @@ elfNN_aarch64_finish_dynamic_sections (bfd *output_bfd,
 	    {
 	      bfd_vma addr =
 		sdyn ? sdyn->output_section->vma + sdyn->output_offset : 0;
-	      bfd_put_NN (output_bfd, addr, htab->root.sgot->contents);
+	      bfd_put_NN (info->output_bfd, addr, htab->root.sgot->contents);
 	    }
 	}
 
diff --git a/bfd/elfnn-ia64.c b/bfd/elfnn-ia64.c
index 7fbb070f5c1..401327a7c68 100644
--- a/bfd/elfnn-ia64.c
+++ b/bfd/elfnn-ia64.c
@@ -2984,8 +2984,7 @@ elfNN_ia64_adjust_dynamic_symbol (struct bfd_link_info *info ATTRIBUTE_UNUSED,
 }
 
 static bool
-elfNN_ia64_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-			       struct bfd_link_info *info)
+elfNN_ia64_late_size_sections (struct bfd_link_info *info)
 {
   struct elfNN_ia64_allocate_data data;
   struct elfNN_ia64_link_hash_table *ia64_info;
@@ -3196,7 +3195,7 @@ elfNN_ia64_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
 #define add_dynamic_entry(TAG, VAL) \
   _bfd_elf_add_dynamic_entry (info, TAG, VAL)
 
-      if (!_bfd_elf_add_dynamic_tags (output_bfd, info, true))
+      if (!_bfd_elf_add_dynamic_tags (info, true))
 	return false;
 
       if (!add_dynamic_entry (DT_IA_64_PLT_RESERVE, 0))
@@ -3760,8 +3759,7 @@ elfNN_ia64_final_link (bfd *abfd, struct bfd_link_info *info)
 }
 
 static int
-elfNN_ia64_relocate_section (bfd *output_bfd,
-			     struct bfd_link_info *info,
+elfNN_ia64_relocate_section (struct bfd_link_info *info,
 			     bfd *input_bfd,
 			     asection *input_section,
 			     bfd_byte *contents,
@@ -3794,7 +3792,7 @@ elfNN_ia64_relocate_section (bfd *output_bfd,
 	->this_hdr.sh_flags |= flags;
     }
 
-  gp_val = _bfd_get_gp_value (output_bfd);
+  gp_val = _bfd_get_gp_value (info->output_bfd);
   srel = get_reloc_section (input_bfd, ia64_info, input_section, false);
 
   rel = relocs;
@@ -3845,7 +3843,7 @@ elfNN_ia64_relocate_section (bfd *output_bfd,
 	  sym = local_syms + r_symndx;
 	  sym_sec = local_sections[r_symndx];
 	  msec = sym_sec;
-	  value = _bfd_elf_rela_local_sym (output_bfd, sym, &msec, rel);
+	  value = _bfd_elf_rela_local_sym (info->output_bfd, sym, &msec, rel);
 	  if (!bfd_link_relocatable (info)
 	      && (sym_sec->flags & SEC_MERGE) != 0
 	      && ELF_ST_TYPE (sym->st_info) == STT_SECTION
@@ -3865,7 +3863,7 @@ elfNN_ia64_relocate_section (bfd *output_bfd,
 		    {
 		      msec = sym_sec;
 		      dynent->addend =
-			_bfd_merged_section_offset (output_bfd, &msec,
+			_bfd_merged_section_offset (info->output_bfd, &msec,
 						    sym->st_value
 						    + dynent->addend);
 		      dynent->addend -= sym->st_value;
@@ -3995,7 +3993,8 @@ elfNN_ia64_relocate_section (bfd *output_bfd,
 		  addend = value;
 		}
 
-	      elfNN_ia64_install_dyn_reloc (output_bfd, info, input_section,
+	      elfNN_ia64_install_dyn_reloc (info->output_bfd, info,
+					    input_section,
 					    srel, rel->r_offset, dyn_r_type,
 					    dynindx, addend);
 	    }
@@ -4045,7 +4044,7 @@ elfNN_ia64_relocate_section (bfd *output_bfd,
 	case R_IA64_PLTOFF64MSB:
 	case R_IA64_PLTOFF64LSB:
 	  dyn_i = get_dyn_sym_info (ia64_info, h, input_bfd, rel, false);
-	  value = set_pltoff_entry (output_bfd, info, dyn_i, value, false);
+	  value = set_pltoff_entry (info->output_bfd, info, dyn_i, value, false);
 	  value -= gp_val;
 	  r = ia64_elf_install_value (hit_addr, value, r_type);
 	  break;
@@ -4059,7 +4058,7 @@ elfNN_ia64_relocate_section (bfd *output_bfd,
 	  if (dyn_i->want_fptr)
 	    {
 	      if (!undef_weak_ref)
-		value = set_fptr_entry (output_bfd, info, dyn_i, value);
+		value = set_fptr_entry (info->output_bfd, info, dyn_i, value);
 	    }
 	  if (!dyn_i->want_fptr || bfd_link_pie (info))
 	    {
@@ -4107,7 +4106,8 @@ elfNN_ia64_relocate_section (bfd *output_bfd,
 		  value = 0;
 		}
 
-	      elfNN_ia64_install_dyn_reloc (output_bfd, info, input_section,
+	      elfNN_ia64_install_dyn_reloc (info->output_bfd, info,
+					    input_section,
 					    srel, rel->r_offset, dyn_r_type,
 					    dynindx, addend);
 	    }
@@ -4129,7 +4129,7 @@ elfNN_ia64_relocate_section (bfd *output_bfd,
 	      {
 		BFD_ASSERT (h == NULL || h->dynindx == -1);
 		if (!undef_weak_ref)
-		  value = set_fptr_entry (output_bfd, info, dyn_i, value);
+		  value = set_fptr_entry (info->output_bfd, info, dyn_i, value);
 		dynindx = -1;
 	      }
 	    else
@@ -4151,7 +4151,7 @@ elfNN_ia64_relocate_section (bfd *output_bfd,
 		value = 0;
 	      }
 
-	    value = set_got_entry (output_bfd, info, dyn_i, dynindx,
+	    value = set_got_entry (info->output_bfd, info, dyn_i, dynindx,
 				   rel->r_addend, value, R_IA64_FPTRNNLSB);
 	    value -= gp_val;
 	    r = ia64_elf_install_value (hit_addr, value, r_type);
@@ -4167,7 +4167,8 @@ elfNN_ia64_relocate_section (bfd *output_bfd,
 	    {
 	      BFD_ASSERT (srel != NULL);
 
-	      elfNN_ia64_install_dyn_reloc (output_bfd, info, input_section,
+	      elfNN_ia64_install_dyn_reloc (info->output_bfd, info,
+					    input_section,
 					    srel, rel->r_offset, r_type,
 					    h->dynindx, rel->r_addend);
 	    }
@@ -4252,7 +4253,7 @@ elfNN_ia64_relocate_section (bfd *output_bfd,
 	    {
 	      /* Find the segment that contains the output_section.  */
 	      Elf_Internal_Phdr *p = _bfd_elf_find_segment_containing_section
-		(output_bfd, input_section->output_section);
+		(info->output_bfd, input_section->output_section);
 
 	      if (p == NULL)
 		{
@@ -4301,17 +4302,18 @@ elfNN_ia64_relocate_section (bfd *output_bfd,
 		  else
 		    dyn_r_type = R_IA64_REL64LSB;
 
-		  elfNN_ia64_install_dyn_reloc (output_bfd, info,
+		  elfNN_ia64_install_dyn_reloc (info->output_bfd, info,
 						input_section,
 						srel, rel->r_offset,
 						dyn_r_type, 0, value);
-		  elfNN_ia64_install_dyn_reloc (output_bfd, info,
+		  elfNN_ia64_install_dyn_reloc (info->output_bfd, info,
 						input_section,
 						srel, rel->r_offset + 8,
 						dyn_r_type, 0, gp_val);
 		}
 	      else
-		elfNN_ia64_install_dyn_reloc (output_bfd, info, input_section,
+		elfNN_ia64_install_dyn_reloc (info->output_bfd, info,
+					      input_section,
 					      srel, rel->r_offset, r_type,
 					      h->dynindx, rel->r_addend);
 	    }
@@ -4507,8 +4509,7 @@ elfNN_ia64_relocate_section (bfd *output_bfd,
 }
 
 static bool
-elfNN_ia64_finish_dynamic_symbol (bfd *output_bfd,
-				  struct bfd_link_info *info,
+elfNN_ia64_finish_dynamic_symbol (struct bfd_link_info *info,
 				  struct elf_link_hash_entry *h,
 				  Elf_Internal_Sym *sym)
 {
@@ -4527,7 +4528,7 @@ elfNN_ia64_finish_dynamic_symbol (bfd *output_bfd,
       asection *plt_sec;
       bfd_vma plt_addr, pltoff_addr, gp_val, plt_index;
 
-      gp_val = _bfd_get_gp_value (output_bfd);
+      gp_val = _bfd_get_gp_value (info->output_bfd);
 
       /* Initialize the minimal PLT entry.  */
 
@@ -4542,7 +4543,8 @@ elfNN_ia64_finish_dynamic_symbol (bfd *output_bfd,
       plt_addr = (plt_sec->output_section->vma
 		  + plt_sec->output_offset
 		  + dyn_i->plt_offset);
-      pltoff_addr = set_pltoff_entry (output_bfd, info, dyn_i, plt_addr, true);
+      pltoff_addr = set_pltoff_entry (info->output_bfd, info, dyn_i,
+				      plt_addr, true);
 
       /* Initialize the FULL PLT entry, if needed.  */
       if (dyn_i->want_plt2)
@@ -4562,7 +4564,7 @@ elfNN_ia64_finish_dynamic_symbol (bfd *output_bfd,
 
       /* Create the dynamic relocation.  */
       outrel.r_offset = pltoff_addr;
-      if (bfd_little_endian (output_bfd))
+      if (bfd_little_endian (info->output_bfd))
 	outrel.r_info = ELFNN_R_INFO (h->dynindx, R_IA64_IPLTLSB);
       else
 	outrel.r_info = ELFNN_R_INFO (h->dynindx, R_IA64_IPLTMSB);
@@ -4583,7 +4585,7 @@ elfNN_ia64_finish_dynamic_symbol (bfd *output_bfd,
       loc = ia64_info->rel_pltoff_sec->contents;
       loc += ((ia64_info->rel_pltoff_sec->reloc_count + plt_index)
 	      * sizeof (ElfNN_External_Rela));
-      bfd_elfNN_swap_reloca_out (output_bfd, &outrel, loc);
+      bfd_elfNN_swap_reloca_out (info->output_bfd, &outrel, loc);
     }
 
   /* Mark some specially defined symbols as absolute.  */
@@ -4596,8 +4598,7 @@ elfNN_ia64_finish_dynamic_symbol (bfd *output_bfd,
 }
 
 static bool
-elfNN_ia64_finish_dynamic_sections (bfd *abfd,
-				    struct bfd_link_info *info,
+elfNN_ia64_finish_dynamic_sections (struct bfd_link_info *info,
 				    bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   struct elfNN_ia64_link_hash_table *ia64_info;
@@ -4621,7 +4622,7 @@ elfNN_ia64_finish_dynamic_sections (bfd *abfd,
       dyncon = (ElfNN_External_Dyn *) sdyn->contents;
       dynconend = (ElfNN_External_Dyn *) (sdyn->contents + sdyn->size);
 
-      gp_val = _bfd_get_gp_value (abfd);
+      gp_val = _bfd_get_gp_value (info->output_bfd);
 
       for (; dyncon < dynconend; dyncon++)
 	{
@@ -4654,7 +4655,7 @@ elfNN_ia64_finish_dynamic_sections (bfd *abfd,
 	      break;
 	    }
 
-	  bfd_elfNN_swap_dyn_out (abfd, &dyn, dyncon);
+	  bfd_elfNN_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	}
 
       /* Initialize the PLT0 entry.  */
diff --git a/bfd/elfnn-kvx.c b/bfd/elfnn-kvx.c
index e40bd3e8a6e..f664251e76e 100644
--- a/bfd/elfnn-kvx.c
+++ b/bfd/elfnn-kvx.c
@@ -2444,8 +2444,7 @@ elfNN_kvx_final_link_relocate (reloc_howto_type *howto,
 /* Relocate a KVX ELF section.  */
 
 static int
-elfNN_kvx_relocate_section (bfd *output_bfd,
-			    struct bfd_link_info *info,
+elfNN_kvx_relocate_section (struct bfd_link_info *info,
 			    bfd *input_bfd,
 			    asection *input_section,
 			    bfd_byte *contents,
@@ -2525,7 +2524,8 @@ elfNN_kvx_relocate_section (bfd *output_bfd,
 	       (input_bfd, symtab_hdr->sh_link, sym->st_name),
 	       input_bfd, input_section, rel->r_offset, true);
 
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 	}
       else
 	{
@@ -2589,7 +2589,7 @@ elfNN_kvx_relocate_section (bfd *output_bfd,
 	save_addend = false;
 
       if (r == bfd_reloc_continue)
-	r = elfNN_kvx_final_link_relocate (howto, input_bfd, output_bfd,
+	r = elfNN_kvx_final_link_relocate (howto, input_bfd, info->output_bfd,
 					   input_section, contents, rel,
 					   relocation, info, sec,
 					   h, &unresolved_reloc,
@@ -2640,7 +2640,7 @@ elfNN_kvx_relocate_section (bfd *output_bfd,
 		  loc = globals->root.srelgot->contents;
 		  loc += globals->root.srelgot->reloc_count++
 		    * RELOC_SIZE (htab);
-		  bfd_elfNN_swap_reloca_out (output_bfd, &rela, loc);
+		  bfd_elfNN_swap_reloca_out (info->output_bfd, &rela, loc);
 
 		  bfd_reloc_code_real_type real_type =
 		    elfNN_kvx_bfd_reloc_from_type (input_bfd, r_type);
@@ -2654,13 +2654,13 @@ elfNN_kvx_relocate_section (bfd *output_bfd,
 		      /* For local dynamic, don't generate DTPOFF in any case.
 			 Initialize the DTPOFF slot into zero, so we get module
 			 base address when invoke runtime TLS resolver.  */
-		      bfd_put_NN (output_bfd, 0,
+		      bfd_put_NN (info->output_bfd, 0,
 				  globals->root.sgot->contents + off
 				  + GOT_ENTRY_SIZE);
 		    }
 		  else if (indx == 0)
 		    {
-		      bfd_put_NN (output_bfd,
+		      bfd_put_NN (info->output_bfd,
 				  relocation - dtpoff_base (info),
 				  globals->root.sgot->contents + off
 				  + GOT_ENTRY_SIZE);
@@ -2681,17 +2681,17 @@ elfNN_kvx_relocate_section (bfd *output_bfd,
 		      loc = globals->root.srelgot->contents;
 		      loc += globals->root.srelgot->reloc_count++
 			* RELOC_SIZE (globals);
-		      bfd_elfNN_swap_reloca_out (output_bfd, &rela, loc);
-		      bfd_put_NN (output_bfd, (bfd_vma) 0,
+		      bfd_elfNN_swap_reloca_out (info->output_bfd, &rela, loc);
+		      bfd_put_NN (info->output_bfd, 0,
 				  globals->root.sgot->contents + off
 				  + GOT_ENTRY_SIZE);
 		    }
 		}
 	      else
 		{
-		  bfd_put_NN (output_bfd, (bfd_vma) 1,
+		  bfd_put_NN (info->output_bfd, (bfd_vma) 1,
 			      globals->root.sgot->contents + off);
-		  bfd_put_NN (output_bfd,
+		  bfd_put_NN (info->output_bfd,
 			      relocation - dtpoff_base (info),
 			      globals->root.sgot->contents + off
 			      + GOT_ENTRY_SIZE);
@@ -2743,13 +2743,13 @@ elfNN_kvx_relocate_section (bfd *output_bfd,
 		  loc += globals->root.srelgot->reloc_count++
 		    * RELOC_SIZE (htab);
 
-		  bfd_elfNN_swap_reloca_out (output_bfd, &rela, loc);
+		  bfd_elfNN_swap_reloca_out (info->output_bfd, &rela, loc);
 
-		  bfd_put_NN (output_bfd, rela.r_addend,
+		  bfd_put_NN (info->output_bfd, rela.r_addend,
 			      globals->root.sgot->contents + off);
 		}
 	      else
-		bfd_put_NN (output_bfd, relocation - tpoff_base (info),
+		bfd_put_NN (info->output_bfd, relocation - tpoff_base (info),
 			    globals->root.sgot->contents + off);
 
 	      symbol_got_offset_mark (input_bfd, h, r_symndx);
@@ -2766,7 +2766,7 @@ elfNN_kvx_relocate_section (bfd *output_bfd,
       if (unresolved_reloc
 	  && !((input_section->flags & SEC_DEBUGGING) != 0
 	       && h->def_dynamic)
-	  && _bfd_elf_section_offset (output_bfd, info, input_section,
+	  && _bfd_elf_section_offset (info->output_bfd, info, input_section,
 				      +rel->r_offset) != (bfd_vma) - 1)
 	{
 	  (*_bfd_error_handler)
@@ -3633,8 +3633,7 @@ kvx_map_one_stub (struct bfd_hash_entry *gen_entry, void *in_arg)
 /* Output mapping symbols for linker generated sections.  */
 
 static bool
-elfNN_kvx_output_arch_local_syms (bfd *output_bfd,
-				  struct bfd_link_info *info,
+elfNN_kvx_output_arch_local_syms (struct bfd_link_info *info,
 				  void *finfo,
 				  int (*func) (void *, const char *,
 					       Elf_Internal_Sym *,
@@ -3665,7 +3664,7 @@ elfNN_kvx_output_arch_local_syms (bfd *output_bfd,
 	  osi.sec = stub_sec;
 
 	  osi.sec_shndx = _bfd_elf_section_from_bfd_section
-	    (output_bfd, osi.sec->output_section);
+	    (info->output_bfd, osi.sec->output_section);
 
 	  bfd_hash_traverse (&htab->stub_hash_table, kvx_map_one_stub,
 			     &osi);
@@ -3677,7 +3676,7 @@ elfNN_kvx_output_arch_local_syms (bfd *output_bfd,
     return true;
 
   osi.sec_shndx = _bfd_elf_section_from_bfd_section
-    (output_bfd, htab->root.splt->output_section);
+    (info->output_bfd, htab->root.splt->output_section);
   osi.sec = htab->root.splt;
 
   return true;
@@ -4028,8 +4027,7 @@ kvx_readonly_dynrelocs (struct elf_link_hash_entry * h, void * inf)
 /* This is the most important function of all . Innocuosly named
    though !  */
 static bool
-elfNN_kvx_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-			      struct bfd_link_info *info)
+elfNN_kvx_late_size_sections (struct bfd_link_info *info)
 {
   struct elf_kvx_link_hash_table *htab;
   bfd *dynobj;
@@ -4356,7 +4354,7 @@ elfNN_kvx_create_small_pltn_entry (struct elf_link_hash_entry *h,
    _TLS_MODULE_BASE_, if needed.  */
 
 static bool
-elfNN_kvx_early_size_sections (bfd *output_bfd, struct bfd_link_info *info)
+elfNN_kvx_early_size_sections (struct bfd_link_info *info)
 {
   asection *tls_sec;
 
@@ -4375,10 +4373,10 @@ elfNN_kvx_early_size_sections (bfd *output_bfd, struct bfd_link_info *info)
       if (tlsbase)
 	{
 	  struct bfd_link_hash_entry *h = NULL;
-	  elf_backend_data *bed = get_elf_backend_data (output_bfd);
+	  elf_backend_data *bed = get_elf_backend_data (info->output_bfd);
 
 	  if (!(_bfd_generic_link_add_one_symbol
-		(info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
+		(info, info->output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
 		 tls_sec, 0, NULL, false, bed->collect, &h)))
 	    return false;
 
@@ -4396,8 +4394,7 @@ elfNN_kvx_early_size_sections (bfd *output_bfd, struct bfd_link_info *info)
 /* Finish up dynamic symbol handling.  We set the contents of various
    dynamic sections here.  */
 static bool
-elfNN_kvx_finish_dynamic_symbol (bfd *output_bfd,
-				 struct bfd_link_info *info,
+elfNN_kvx_finish_dynamic_symbol (struct bfd_link_info *info,
 				 struct elf_link_hash_entry *h,
 				 Elf_Internal_Sym *sym)
 {
@@ -4429,7 +4426,7 @@ elfNN_kvx_finish_dynamic_symbol (bfd *output_bfd,
 	  || relplt == NULL)
 	abort ();
 
-      elfNN_kvx_create_small_pltn_entry (h, htab, output_bfd);
+      elfNN_kvx_create_small_pltn_entry (h, htab, info->output_bfd);
       if (!h->def_regular)
 	{
 	  /* Mark the symbol as undefined, rather than as defined in
@@ -4491,7 +4488,7 @@ elfNN_kvx_finish_dynamic_symbol (bfd *output_bfd,
       else
 	{
 	  BFD_ASSERT ((h->got.offset & 1) == 0);
-	  bfd_put_NN (output_bfd, (bfd_vma) 0,
+	  bfd_put_NN (info->output_bfd, 0,
 		      htab->root.sgot->contents + h->got.offset);
 	  rela.r_info = ELFNN_R_INFO (h->dynindx, R_KVX_GLOB_DAT);
 	  rela.r_addend = 0;
@@ -4499,7 +4496,7 @@ elfNN_kvx_finish_dynamic_symbol (bfd *output_bfd,
 
       loc = htab->root.srelgot->contents;
       loc += htab->root.srelgot->reloc_count++ * RELOC_SIZE (htab);
-      bfd_elfNN_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elfNN_swap_reloca_out (info->output_bfd, &rela, loc);
     }
 
   if (h->needs_copy)
@@ -4522,7 +4519,7 @@ elfNN_kvx_finish_dynamic_symbol (bfd *output_bfd,
       rela.r_addend = 0;
       loc = htab->srelbss->contents;
       loc += htab->srelbss->reloc_count++ * RELOC_SIZE (htab);
-      bfd_elfNN_swap_reloca_out (output_bfd, &rela, loc);
+      bfd_elfNN_swap_reloca_out (info->output_bfd, &rela, loc);
     }
 
   /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute.  SYM may
@@ -4546,8 +4543,7 @@ elfNN_kvx_init_small_plt0_entry (bfd *output_bfd ATTRIBUTE_UNUSED,
 }
 
 static bool
-elfNN_kvx_finish_dynamic_sections (bfd *output_bfd,
-				   struct bfd_link_info *info,
+elfNN_kvx_finish_dynamic_sections (struct bfd_link_info *info,
 				   bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   struct elf_kvx_link_hash_table *htab;
@@ -4610,7 +4606,7 @@ elfNN_kvx_finish_dynamic_sections (bfd *output_bfd,
 	      break;
 	    }
 
-	  bfd_elfNN_swap_dyn_out (output_bfd, &dyn, dyncon);
+	  bfd_elfNN_swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	}
 
     }
@@ -4618,7 +4614,7 @@ elfNN_kvx_finish_dynamic_sections (bfd *output_bfd,
   /* Fill in the special first entry in the procedure linkage table.  */
   if (htab->root.splt && htab->root.splt->size > 0)
     {
-      elfNN_kvx_init_small_plt0_entry (output_bfd, htab);
+      elfNN_kvx_init_small_plt0_entry (info->output_bfd, htab);
 
       elf_section_data (htab->root.splt->output_section)->
 	this_hdr.sh_entsize = htab->plt_entry_size;
@@ -4636,14 +4632,12 @@ elfNN_kvx_finish_dynamic_sections (bfd *output_bfd,
       /* Fill in the first three entries in the global offset table.  */
       if (htab->root.sgotplt->size > 0)
 	{
-	  bfd_put_NN (output_bfd, (bfd_vma) 0, htab->root.sgotplt->contents);
+	  bfd_put_NN (info->output_bfd, 0, htab->root.sgotplt->contents);
 
 	  /* Write GOT[1] and GOT[2], needed for the dynamic linker.  */
-	  bfd_put_NN (output_bfd,
-		      (bfd_vma) 0,
+	  bfd_put_NN (info->output_bfd, 0,
 		      htab->root.sgotplt->contents + GOT_ENTRY_SIZE);
-	  bfd_put_NN (output_bfd,
-		      (bfd_vma) 0,
+	  bfd_put_NN (info->output_bfd, 0,
 		      htab->root.sgotplt->contents + GOT_ENTRY_SIZE * 2);
 	}
 
@@ -4653,7 +4647,7 @@ elfNN_kvx_finish_dynamic_sections (bfd *output_bfd,
 	    {
 	      bfd_vma addr =
 		sdyn ? sdyn->output_section->vma + sdyn->output_offset : 0;
-	      bfd_put_NN (output_bfd, addr, htab->root.sgot->contents);
+	      bfd_put_NN (info->output_bfd, addr, htab->root.sgot->contents);
 	    }
 	}
 
diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c
index 8f8ec3b0789..9d9c68664bb 100644
--- a/bfd/elfnn-loongarch.c
+++ b/bfd/elfnn-loongarch.c
@@ -2543,8 +2543,7 @@ loongarch_elf_finish_relative_relocs (struct bfd_link_info *info)
 }
 
 static bool
-loongarch_elf_late_size_sections (bfd *output_bfd,
-				  struct bfd_link_info *info)
+loongarch_elf_late_size_sections (struct bfd_link_info *info)
 {
   struct loongarch_elf_link_hash_table *htab;
   bfd *dynobj;
@@ -2566,9 +2565,9 @@ loongarch_elf_late_size_sections (bfd *output_bfd,
 	  s = htab->elf.interp;
 	  BFD_ASSERT (s != NULL);
 
-	  if (elf_elfheader (output_bfd)->e_ident[EI_CLASS] == ELFCLASS32)
+	  if (elf_elfheader (info->output_bfd)->e_ident[EI_CLASS] == ELFCLASS32)
 	    interpreter = "/lib32/ld.so.1";
-	  else if (elf_elfheader (output_bfd)->e_ident[EI_CLASS] == ELFCLASS64)
+	  else if (elf_elfheader (info->output_bfd)->e_ident[EI_CLASS] == ELFCLASS64)
 	    interpreter = "/lib64/ld.so.1";
 	  else
 	    interpreter = "/lib/ld.so.1";
@@ -3495,7 +3494,7 @@ loongarch_resolve_pcrel_lo_relocs (loongarch_pcrel_relocs *p)
 }
 
 static int
-loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
+loongarch_elf_relocate_section (struct bfd_link_info *info,
 				bfd *input_bfd, asection *input_section,
 				bfd_byte *contents, Elf_Internal_Rela *relocs,
 				Elf_Internal_Sym *local_syms,
@@ -3555,7 +3554,8 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	  unresolved_reloc = false;
 	  sym = local_syms + r_symndx;
 	  sec = local_sections[r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 
 	  /* Relocate against local STT_GNU_IFUNC symbol.  */
 	  if (!bfd_link_relocatable (info)
@@ -3690,7 +3690,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	      /* When generating a shared object, these relocations are copied
 		 into the output file to be resolved at run time.  */
 
-	      outrel.r_offset = _bfd_elf_section_offset (output_bfd, info,
+	      outrel.r_offset = _bfd_elf_section_offset (info->output_bfd, info,
 							 input_section,
 							 rel->r_offset);
 
@@ -3766,8 +3766,8 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 					    relocation, input_bfd,
 					    contents);
 		  else
-		    loongarch_elf_append_rela (output_bfd, sreloc,
-					       &outrel);
+		    loongarch_elf_append_rela (info->output_bfd,
+					       sreloc, &outrel);
 		}
 	    }
 
@@ -3826,7 +3826,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	    {
 	      Elf_Internal_Rela outrel;
 
-	      outrel.r_offset = _bfd_elf_section_offset (output_bfd, info,
+	      outrel.r_offset = _bfd_elf_section_offset (info->output_bfd, info,
 							 input_section,
 							 rel->r_offset);
 	      unresolved_reloc = (!((bfd_vma) -2 <= outrel.r_offset)
@@ -3835,7 +3835,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	      outrel.r_offset += sec_addr (input_section);
 	      outrel.r_addend = rel->r_addend;
 	      if (unresolved_reloc)
-		loongarch_elf_append_rela (output_bfd, sreloc, &outrel);
+		loongarch_elf_append_rela (info->output_bfd, sreloc, &outrel);
 	      break;
 	    }
 
@@ -4131,9 +4131,9 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		      outrel.r_offset = sec_addr (got) + off;
 		      outrel.r_info = ELFNN_R_INFO (0, R_LARCH_RELATIVE);
 		      outrel.r_addend = relocation; /* Link-time addr.  */
-		      loongarch_elf_append_rela (output_bfd, s, &outrel);
+		      loongarch_elf_append_rela (info->output_bfd, s, &outrel);
 		    }
-		  bfd_put_NN (output_bfd, relocation, got->contents + off);
+		  bfd_put_NN (info->output_bfd, relocation, got->contents + off);
 		  h->got.offset |= 1;
 		}
 	    }
@@ -4183,10 +4183,10 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		      outrel.r_offset = sec_addr (got) + off;
 		      outrel.r_info = ELFNN_R_INFO (0, R_LARCH_RELATIVE);
 		      outrel.r_addend = relocation; /* Link-time addr.  */
-		      loongarch_elf_append_rela (output_bfd, s, &outrel);
+		      loongarch_elf_append_rela (info->output_bfd, s, &outrel);
 		    }
 
-		  bfd_put_NN (output_bfd, relocation, got->contents + off);
+		  bfd_put_NN (info->output_bfd, relocation, got->contents + off);
 		  local_got_offsets[r_symndx] |= 1;
 		}
 	    }
@@ -4238,34 +4238,38 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 			rela.r_offset = sec_addr (got) + got_off;
 			rela.r_addend = 0;
 			rela.r_info = ELFNN_R_INFO (indx, R_LARCH_TLS_DTPMODNN);
-			bfd_put_NN (output_bfd, 0, got->contents + got_off);
-			loongarch_elf_append_rela (output_bfd, srel, &rela);
+			bfd_put_NN (info->output_bfd, 0,
+				    got->contents + got_off);
+			loongarch_elf_append_rela (info->output_bfd,
+						   srel, &rela);
 
 			if (indx == 0)
 			  {
 			    /* Local symbol, tp offset has been known.  */
 			    BFD_ASSERT (! unresolved_reloc);
-			    bfd_put_NN (output_bfd,
+			    bfd_put_NN (info->output_bfd,
 				tlsoff (info, relocation),
 				(got->contents + got_off + GOT_ENTRY_SIZE));
 			  }
 			else
 			  {
 			    /* Dynamic resolved block offset.  */
-			    bfd_put_NN (output_bfd, 0,
+			    bfd_put_NN (info->output_bfd, 0,
 				got->contents + got_off + GOT_ENTRY_SIZE);
 			    rela.r_info = ELFNN_R_INFO (indx,
 						R_LARCH_TLS_DTPRELNN);
 			    rela.r_offset += GOT_ENTRY_SIZE;
-			    loongarch_elf_append_rela (output_bfd, srel, &rela);
+			    loongarch_elf_append_rela (info->output_bfd,
+						       srel, &rela);
 			  }
 		      }
 		    else
 		      {
 			/* In a static link or an executable link with the symbol
 			   binding locally.  Mark it as belonging to module 1.  */
-			bfd_put_NN (output_bfd, 1, got->contents + got_off);
-			bfd_put_NN (output_bfd, tlsoff (info, relocation),
+			bfd_put_NN (info->output_bfd, 1,
+				    got->contents + got_off);
+			bfd_put_NN (info->output_bfd, tlsoff (info, relocation),
 			    got->contents + got_off + GOT_ENTRY_SIZE);
 		      }
 		  }
@@ -4273,7 +4277,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		  {
 		    if (need_reloc)
 		      {
-			bfd_put_NN (output_bfd, 0,
+			bfd_put_NN (info->output_bfd, 0,
 			    got->contents + got_off + ie_off);
 			rela.r_offset = sec_addr (got) + got_off + ie_off;
 			rela.r_addend = 0;
@@ -4281,13 +4285,14 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 			if (indx == 0)
 			  rela.r_addend = tlsoff (info, relocation);
 			rela.r_info = ELFNN_R_INFO (indx, R_LARCH_TLS_TPRELNN);
-			loongarch_elf_append_rela (output_bfd, srel, &rela);
+			loongarch_elf_append_rela (info->output_bfd,
+						   srel, &rela);
 		      }
 		    else
 		      {
 			/* In a static link or an executable link with the symbol
 			   binding locally, compute offset directly.  */
-			bfd_put_NN (output_bfd, tlsoff (info, relocation),
+			bfd_put_NN (info->output_bfd, tlsoff (info, relocation),
 			    got->contents + got_off + ie_off);
 		      }
 		  }
@@ -4589,11 +4594,11 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 			  rela.r_offset = sec_addr (got) + got_off;
 			  rela.r_info = ELFNN_R_INFO (0, R_LARCH_RELATIVE);
 			  rela.r_addend = relocation;
-			  loongarch_elf_append_rela (output_bfd,
+			  loongarch_elf_append_rela (info->output_bfd,
 						     htab->elf.srelgot, &rela);
 			}
 		      h->got.offset |= 1;
-		      bfd_put_NN (output_bfd, relocation,
+		      bfd_put_NN (info->output_bfd, relocation,
 				  got->contents + got_off);
 		    }
 		}
@@ -4612,12 +4617,13 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 			  rela.r_offset = sec_addr (got) + got_off;
 			  rela.r_info = ELFNN_R_INFO (0, R_LARCH_RELATIVE);
 			  rela.r_addend = relocation;
-			  loongarch_elf_append_rela (output_bfd,
+			  loongarch_elf_append_rela (info->output_bfd,
 						     htab->elf.srelgot, &rela);
 			}
 		      local_got_offsets[r_symndx] |= 1;
 		    }
-		  bfd_put_NN (output_bfd, relocation, got->contents + got_off);
+		  bfd_put_NN (info->output_bfd, relocation,
+			      got->contents + got_off);
 		}
 
 	      relocation = got_off + sec_addr (got);
@@ -4773,34 +4779,36 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		      rela.r_offset = sec_addr (got) + got_off;
 		      rela.r_addend = 0;
 		      rela.r_info = ELFNN_R_INFO (indx,R_LARCH_TLS_DTPMODNN);
-		      bfd_put_NN (output_bfd, 0, got->contents + got_off);
-		      loongarch_elf_append_rela (output_bfd, relgot, &rela);
+		      bfd_put_NN (info->output_bfd, 0, got->contents + got_off);
+		      loongarch_elf_append_rela (info->output_bfd,
+						 relgot, &rela);
 
 		      if (indx == 0)
 			{
 			  /* Local symbol, tp offset has been known.  */
 			  BFD_ASSERT (! unresolved_reloc);
-			  bfd_put_NN (output_bfd,
+			  bfd_put_NN (info->output_bfd,
 			      tlsoff (info, relocation),
 			      (got->contents + got_off + GOT_ENTRY_SIZE));
 			}
 		      else
 			{
 			  /* Dynamic resolved block offset.  */
-			  bfd_put_NN (output_bfd, 0,
+			  bfd_put_NN (info->output_bfd, 0,
 			      got->contents + got_off + GOT_ENTRY_SIZE);
 			  rela.r_info = ELFNN_R_INFO (indx,
 						R_LARCH_TLS_DTPRELNN);
 			  rela.r_offset += GOT_ENTRY_SIZE;
-			  loongarch_elf_append_rela (output_bfd, relgot, &rela);
+			  loongarch_elf_append_rela (info->output_bfd,
+						     relgot, &rela);
 			}
 		    }
 		  else
 		    {
 		      /* In a static link or an executable link with the symbol
 			 binding locally.  Mark it as belonging to module 1.  */
-		      bfd_put_NN (output_bfd, 1, got->contents + got_off);
-		      bfd_put_NN (output_bfd, tlsoff (info, relocation),
+		      bfd_put_NN (info->output_bfd, 1, got->contents + got_off);
+		      bfd_put_NN (info->output_bfd, tlsoff (info, relocation),
 			  got->contents + got_off + GOT_ENTRY_SIZE);
 		    }
 		}
@@ -4815,15 +4823,15 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		    rela.r_addend = tlsoff (info, relocation);
 
 		  rela.r_info = ELFNN_R_INFO (indx, R_LARCH_TLS_DESCNN);
-		  loongarch_elf_append_rela (output_bfd, relgot, &rela);
-		  bfd_put_NN (output_bfd, 0,
+		  loongarch_elf_append_rela (info->output_bfd, relgot, &rela);
+		  bfd_put_NN (info->output_bfd, 0,
 			      got->contents + got_off + desc_off);
 		}
 	      if (tls_type & GOT_TLS_IE)
 		{
 		  if (need_reloc)
 		    {
-		      bfd_put_NN (output_bfd, 0,
+		      bfd_put_NN (info->output_bfd, 0,
 			  got->contents + got_off + ie_off);
 		      rela.r_offset = sec_addr (got) + got_off + ie_off;
 		      rela.r_addend = 0;
@@ -4831,13 +4839,14 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		      if (indx == 0)
 			rela.r_addend = tlsoff (info, relocation);
 		      rela.r_info = ELFNN_R_INFO (indx, R_LARCH_TLS_TPRELNN);
-		      loongarch_elf_append_rela (output_bfd, relgot, &rela);
+		      loongarch_elf_append_rela (info->output_bfd,
+						 relgot, &rela);
 		    }
 		  else
 		    {
 		      /* In a static link or an executable link with the symbol
 			 bindinglocally, compute offset directly.  */
-		      bfd_put_NN (output_bfd, tlsoff (info, relocation),
+		      bfd_put_NN (info->output_bfd, tlsoff (info, relocation),
 			  got->contents + got_off + ie_off);
 		    }
 		}
@@ -4953,7 +4962,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	  if (!unresolved_reloc)
 	    break;
 
-	  if (_bfd_elf_section_offset (output_bfd, info, input_section,
+	  if (_bfd_elf_section_offset (info->output_bfd, info, input_section,
 				       rel->r_offset) == MINUS_ONE)
 	    /* WHY? May because it's invalid so skip checking.
 	       But why dynamic reloc a invalid section?  */
@@ -6453,13 +6462,12 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec,
    dynamic sections here.  */
 
 static bool
-loongarch_elf_finish_dynamic_symbol (bfd *output_bfd,
-				     struct bfd_link_info *info,
+loongarch_elf_finish_dynamic_symbol (struct bfd_link_info *info,
 				     struct elf_link_hash_entry *h,
 				     Elf_Internal_Sym *sym)
 {
   struct loongarch_elf_link_hash_table *htab = loongarch_elf_hash_table (info);
-  elf_backend_data *bed = get_elf_backend_data (output_bfd);
+  elf_backend_data *bed = get_elf_backend_data (info->output_bfd);
 
   if (h->plt.offset != MINUS_ONE)
     {
@@ -6508,11 +6516,11 @@ loongarch_elf_finish_dynamic_symbol (bfd *output_bfd,
 	return false;
 
       for (i = 0; i < PLT_ENTRY_INSNS; i++)
-	bfd_put_32 (output_bfd, plt_entry[i], loc + 4 * i);
+	bfd_put_32 (info->output_bfd, plt_entry[i], loc + 4 * i);
 
       /* Fill in the initial value of the got.plt entry.  */
       loc = gotplt->contents + (got_address - sec_addr (gotplt));
-      bfd_put_NN (output_bfd, sec_addr (plt), loc);
+      bfd_put_NN (info->output_bfd, sec_addr (plt), loc);
 
       rela.r_offset = got_address;
 
@@ -6526,7 +6534,7 @@ loongarch_elf_finish_dynamic_symbol (bfd *output_bfd,
 			       + h->root.u.def.section->output_section->vma
 			       + h->root.u.def.section->output_offset);
 
-	  loongarch_elf_append_rela (output_bfd, relplt, &rela);
+	  loongarch_elf_append_rela (info->output_bfd, relplt, &rela);
 	}
       else
 	{
@@ -6534,7 +6542,7 @@ loongarch_elf_finish_dynamic_symbol (bfd *output_bfd,
 	  rela.r_info = ELFNN_R_INFO (h->dynindx, R_LARCH_JUMP_SLOT);
 	  rela.r_addend = 0;
 	  loc = relplt->contents + plt_idx * sizeof (ElfNN_External_Rela);
-	  bed->s->swap_reloca_out (output_bfd, &rela, loc);
+	  bed->s->swap_reloca_out (info->output_bfd, &rela, loc);
 	}
 
       if (!h->def_regular)
@@ -6587,21 +6595,21 @@ loongarch_elf_finish_dynamic_symbol (bfd *output_bfd,
 		  rela.r_info = ELFNN_R_INFO (0, R_LARCH_IRELATIVE);
 		  rela.r_addend = h->root.u.def.value + sec->output_section->vma
 		    + sec->output_offset;
-		  bfd_put_NN (output_bfd, 0, sgot->contents + off);
+		  bfd_put_NN (info->output_bfd, 0, sgot->contents + off);
 		}
 	      else
 		{
 		  BFD_ASSERT (h->dynindx != -1);
 		  rela.r_info = ELFNN_R_INFO (h->dynindx, R_LARCH_NN);
 		  rela.r_addend = 0;
-		  bfd_put_NN (output_bfd, (bfd_vma) 0, sgot->contents + off);
+		  bfd_put_NN (info->output_bfd, 0, sgot->contents + off);
 		}
 	    }
 	  else if(bfd_link_pic (info))
 	    {
 	      rela.r_info = ELFNN_R_INFO (h->dynindx, R_LARCH_NN);
 	      rela.r_addend = 0;
-	      bfd_put_NN (output_bfd, rela.r_addend, sgot->contents + off);
+	      bfd_put_NN (info->output_bfd, rela.r_addend, sgot->contents + off);
 	    }
 	  else
 	    {
@@ -6614,7 +6622,7 @@ loongarch_elf_finish_dynamic_symbol (bfd *output_bfd,
 		 contains the real function address if we need pointer
 		 equality.  We load the GOT entry with the PLT entry.  */
 	      plt = htab->elf.splt ? htab->elf.splt : htab->elf.iplt;
-	      bfd_put_NN (output_bfd,
+	      bfd_put_NN (info->output_bfd,
 			  (plt->output_section->vma
 			   + plt->output_offset
 			   + h->plt.offset),
@@ -6632,7 +6640,7 @@ loongarch_elf_finish_dynamic_symbol (bfd *output_bfd,
 	     to write the addend (link-time addr) into the GOT then.  */
 	  if (info->enable_dt_relr)
 	    {
-	      bfd_put_NN (output_bfd, linkaddr, sgot->contents + off);
+	      bfd_put_NN (info->output_bfd, linkaddr, sgot->contents + off);
 	      goto skip_got_reloc;
 	    }
 	  rela.r_info = ELFNN_R_INFO (0, R_LARCH_RELATIVE);
@@ -6645,7 +6653,7 @@ loongarch_elf_finish_dynamic_symbol (bfd *output_bfd,
 	  rela.r_addend = 0;
 	}
 
-      loongarch_elf_append_rela (output_bfd, srela, &rela);
+      loongarch_elf_append_rela (info->output_bfd, srela, &rela);
     }
 skip_got_reloc:
 
@@ -6659,11 +6667,10 @@ skip_got_reloc:
 /* Finish up the dynamic sections.  */
 
 static bool
-loongarch_finish_dyn (bfd *output_bfd, struct bfd_link_info *info, bfd *dynobj,
-		      asection *sdyn)
+loongarch_finish_dyn (struct bfd_link_info *info, bfd *dynobj, asection *sdyn)
 {
   struct loongarch_elf_link_hash_table *htab = loongarch_elf_hash_table (info);
-  elf_backend_data *bed = get_elf_backend_data (output_bfd);
+  elf_backend_data *bed = get_elf_backend_data (info->output_bfd);
   size_t dynsize = bed->s->sizeof_dyn, skipped_size = 0;
   bfd_byte *dyncon, *dynconend;
 
@@ -6702,7 +6709,7 @@ loongarch_finish_dyn (bfd *output_bfd, struct bfd_link_info *info, bfd *dynobj,
       if (skipped)
 	skipped_size += dynsize;
       else
-	bed->s->swap_dyn_out (output_bfd, &dyn, dyncon - skipped_size);
+	bed->s->swap_dyn_out (info->output_bfd, &dyn, dyncon - skipped_size);
     }
   /* Wipe out any trailing entries if we shifted down a dynamic tag.  */
   memset (dyncon - skipped_size, 0, skipped_size);
@@ -6718,7 +6725,7 @@ elfNN_loongarch_finish_local_dynamic_symbol (void **slot, void *inf)
   struct elf_link_hash_entry *h = (struct elf_link_hash_entry *) *slot;
   struct bfd_link_info *info = (struct bfd_link_info *) inf;
 
-  return loongarch_elf_finish_dynamic_symbol (info->output_bfd, info, h, NULL);
+  return loongarch_elf_finish_dynamic_symbol (info, h, NULL);
 }
 
 /* Value of struct elf_backend_data->elf_backend_output_arch_local_syms,
@@ -6728,8 +6735,7 @@ elfNN_loongarch_finish_local_dynamic_symbol (void **slot, void *inf)
 
 static bool
 elf_loongarch_output_arch_local_syms
-  (bfd *output_bfd ATTRIBUTE_UNUSED,
-   struct bfd_link_info *info,
+  (struct bfd_link_info *info,
    void *flaginfo ATTRIBUTE_UNUSED,
    int (*func) (void *, const char *,
 		Elf_Internal_Sym *,
@@ -6749,8 +6755,7 @@ elf_loongarch_output_arch_local_syms
 }
 
 static bool
-loongarch_elf_finish_dynamic_sections (bfd *output_bfd,
-				       struct bfd_link_info *info,
+loongarch_elf_finish_dynamic_sections (struct bfd_link_info *info,
 				       bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   bfd *dynobj;
@@ -6766,7 +6771,7 @@ loongarch_elf_finish_dynamic_sections (bfd *output_bfd,
     {
       BFD_ASSERT (htab->elf.splt && sdyn);
 
-      if (!loongarch_finish_dyn (output_bfd, info, dynobj, sdyn))
+      if (!loongarch_finish_dyn (info, dynobj, sdyn))
 	return false;
     }
 
@@ -6782,7 +6787,7 @@ loongarch_elf_finish_dynamic_sections (bfd *output_bfd,
 	return false;
 
       for (i = 0; i < PLT_HEADER_INSNS; i++)
-	bfd_put_32 (output_bfd, plt_header[i], plt->contents + 4 * i);
+	bfd_put_32 (info->output_bfd, plt_header[i], plt->contents + 4 * i);
 
       elf_section_data (plt->output_section)->this_hdr.sh_entsize =
 	PLT_ENTRY_SIZE;
@@ -6803,9 +6808,9 @@ loongarch_elf_finish_dynamic_sections (bfd *output_bfd,
 	{
 	  /* Write the first two entries in .got.plt, needed for the dynamic
 	     linker.  */
-	  bfd_put_NN (output_bfd, MINUS_ONE, htab->elf.sgotplt->contents);
+	  bfd_put_NN (info->output_bfd, MINUS_ONE, htab->elf.sgotplt->contents);
 
-	  bfd_put_NN (output_bfd, (bfd_vma) 0,
+	  bfd_put_NN (info->output_bfd, 0,
 		      htab->elf.sgotplt->contents + GOT_ENTRY_SIZE);
 	}
 
@@ -6821,7 +6826,7 @@ loongarch_elf_finish_dynamic_sections (bfd *output_bfd,
 	  /* Set the first entry in the global offset table to the address of
 	     the dynamic section.  */
 	  bfd_vma val = sdyn ? sec_addr (sdyn) : 0;
-	  bfd_put_NN (output_bfd, val, htab->elf.sgot->contents);
+	  bfd_put_NN (info->output_bfd, val, htab->elf.sgot->contents);
 	}
 
       elf_section_data (output_section)->this_hdr.sh_entsize = GOT_ENTRY_SIZE;
diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
index 2aa0e12ff20..1c1c3ea36c5 100644
--- a/bfd/elfnn-riscv.c
+++ b/bfd/elfnn-riscv.c
@@ -1688,7 +1688,7 @@ allocate_local_ifunc_dynrelocs (void **slot, void *inf)
 }
 
 static bool
-riscv_elf_late_size_sections (bfd *output_bfd, struct bfd_link_info *info)
+riscv_elf_late_size_sections (struct bfd_link_info *info)
 {
   struct riscv_elf_link_hash_table *htab;
   bfd *dynobj;
@@ -1832,7 +1832,7 @@ riscv_elf_late_size_sections (bfd *output_bfd, struct bfd_link_info *info)
 	      || htab->elf.splt->size == 0)
 	  && (htab->elf.sgot == NULL
 	      || (htab->elf.sgot->size
-		  == get_elf_backend_data (output_bfd)->got_header_size)))
+		  == get_elf_backend_data (info->output_bfd)->got_header_size)))
 	htab->elf.sgotplt->size = 0;
     }
 
@@ -1901,7 +1901,7 @@ riscv_elf_late_size_sections (bfd *output_bfd, struct bfd_link_info *info)
   /* Add dynamic entries.  */
   if (elf_hash_table (info)->dynamic_sections_created)
     {
-      if (!_bfd_elf_add_dynamic_tags (output_bfd, info, true))
+      if (!_bfd_elf_add_dynamic_tags (info, true))
 	return false;
 
       if (htab->variant_cc
@@ -2415,8 +2415,7 @@ riscv_resolve_pcrel_lo_relocs (riscv_pcrel_relocs *p)
    accordingly.  */
 
 static int
-riscv_elf_relocate_section (bfd *output_bfd,
-			    struct bfd_link_info *info,
+riscv_elf_relocate_section (struct bfd_link_info *info,
 			    bfd *input_bfd,
 			    asection *input_section,
 			    bfd_byte *contents,
@@ -2472,7 +2471,8 @@ riscv_elf_relocate_section (bfd *output_bfd,
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections[r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 
 	  /* Relocate against local STT_GNU_IFUNC symbol.  */
 	  if (!bfd_link_relocatable (info)
@@ -2585,7 +2585,7 @@ riscv_elf_relocate_section (bfd *output_bfd,
 
 		    /* Need a dynamic relocation to get the real function
 		       address.  */
-		    outrel.r_offset = _bfd_elf_section_offset (output_bfd,
+		    outrel.r_offset = _bfd_elf_section_offset (info->output_bfd,
 							       info,
 							       input_section,
 							       rel->r_offset);
@@ -2622,11 +2622,11 @@ riscv_elf_relocate_section (bfd *output_bfd,
 		       2. .rela.got section in dynamic executable.
 		       3. .rela.iplt section in static executable.  */
 		    if (bfd_link_pic (info))
-		      riscv_elf_append_rela (output_bfd, htab->elf.irelifunc,
-					     &outrel);
+		      riscv_elf_append_rela (info->output_bfd,
+					     htab->elf.irelifunc, &outrel);
 		    else if (htab->elf.splt != NULL)
-		      riscv_elf_append_rela (output_bfd, htab->elf.srelgot,
-					     &outrel);
+		      riscv_elf_append_rela (info->output_bfd,
+					     htab->elf.srelgot, &outrel);
 		    else
 		      {
 			/* Do not use riscv_elf_append_rela to add dynamic
@@ -2634,11 +2634,11 @@ riscv_elf_relocate_section (bfd *output_bfd,
 			   overwrite problems.  This is same as what we did
 			   in the riscv_elf_finish_dynamic_symbol.  */
 			elf_backend_data *bed
-			  = get_elf_backend_data (output_bfd);
+			  = get_elf_backend_data (info->output_bfd);
 			bfd_vma iplt_idx = htab->last_iplt_index--;
 			bfd_byte *loc = htab->elf.irelplt->contents
 					+ iplt_idx * sizeof (ElfNN_External_Rela);
-			bed->s->swap_reloca_out (output_bfd, &outrel, loc);
+			bed->s->swap_reloca_out (info->output_bfd, &outrel, loc);
 		      }
 
 		    /* If this reloc is against an external symbol, we
@@ -2696,7 +2696,7 @@ riscv_elf_relocate_section (bfd *output_bfd,
 			  off &= ~1;
 			else
 			  {
-			    bfd_put_NN (output_bfd, relocation,
+			    bfd_put_NN (info->output_bfd, relocation,
 					base_got->contents + off);
 			    /* Note that this is harmless for the case,
 			       as -1 | 1 still is -1.  */
@@ -2883,7 +2883,7 @@ riscv_elf_relocate_section (bfd *output_bfd,
 			  && !bfd_is_abs_section(h->root.u.def.section))
 			relative_got = true;
 
-		      bfd_put_NN (output_bfd, relocation,
+		      bfd_put_NN (info->output_bfd, relocation,
 				  htab->elf.sgot->contents + off);
 		      h->got.offset |= 1;
 		    }
@@ -2908,7 +2908,7 @@ riscv_elf_relocate_section (bfd *output_bfd,
 		  if (bfd_link_pic (info))
 		    relative_got = true;
 
-		  bfd_put_NN (output_bfd, relocation,
+		  bfd_put_NN (info->output_bfd, relocation,
 			      htab->elf.sgot->contents + off);
 		  local_got_offsets[r_symndx] |= 1;
 		}
@@ -2926,7 +2926,7 @@ riscv_elf_relocate_section (bfd *output_bfd,
 	      outrel.r_offset = sec_addr (htab->elf.sgot) + off;
 	      outrel.r_info = ELFNN_R_INFO (0, R_RISCV_RELATIVE);
 	      outrel.r_addend = relocation;
-	      riscv_elf_append_rela (output_bfd, s, &outrel);
+	      riscv_elf_append_rela (info->output_bfd, s, &outrel);
 	    }
 
 	  if (rel->r_addend != 0)
@@ -3165,8 +3165,8 @@ riscv_elf_relocate_section (bfd *output_bfd,
 		 time.  */
 
 	      outrel.r_offset =
-		_bfd_elf_section_offset (output_bfd, info, input_section,
-					 rel->r_offset);
+		_bfd_elf_section_offset (info->output_bfd, info,
+					 input_section, rel->r_offset);
 	      bool skip = false;
 	      bool relocate = false;
 	      if (outrel.r_offset == (bfd_vma) -1)
@@ -3203,7 +3203,7 @@ riscv_elf_relocate_section (bfd *output_bfd,
 		}
 
 	      sreloc = elf_section_data (input_section)->sreloc;
-	      riscv_elf_append_rela (output_bfd, sreloc, &outrel);
+	      riscv_elf_append_rela (info->output_bfd, sreloc, &outrel);
 	      if (!relocate)
 		continue;
 	    }
@@ -3265,25 +3265,27 @@ riscv_elf_relocate_section (bfd *output_bfd,
 		      outrel.r_offset = sec_addr (htab->elf.sgot) + off;
 		      outrel.r_addend = 0;
 		      outrel.r_info = ELFNN_R_INFO (indx, R_RISCV_TLS_DTPMODNN);
-		      bfd_put_NN (output_bfd, 0,
+		      bfd_put_NN (info->output_bfd, 0,
 				  htab->elf.sgot->contents + off);
-		      riscv_elf_append_rela (output_bfd, htab->elf.srelgot, &outrel);
+		      riscv_elf_append_rela (info->output_bfd,
+					     htab->elf.srelgot, &outrel);
 		      if (indx == 0)
 			{
 			  BFD_ASSERT (! unresolved_reloc);
-			  bfd_put_NN (output_bfd,
+			  bfd_put_NN (info->output_bfd,
 				      dtpoff (info, relocation),
 				      (htab->elf.sgot->contents
 				       + off + RISCV_ELF_WORD_BYTES));
 			}
 		      else
 			{
-			  bfd_put_NN (output_bfd, 0,
+			  bfd_put_NN (info->output_bfd, 0,
 				      (htab->elf.sgot->contents
 				       + off + RISCV_ELF_WORD_BYTES));
 			  outrel.r_info = ELFNN_R_INFO (indx, R_RISCV_TLS_DTPRELNN);
 			  outrel.r_offset += RISCV_ELF_WORD_BYTES;
-			  riscv_elf_append_rela (output_bfd, htab->elf.srelgot, &outrel);
+			  riscv_elf_append_rela (info->output_bfd,
+						 htab->elf.srelgot, &outrel);
 			}
 		    }
 		  else
@@ -3293,9 +3295,9 @@ riscv_elf_relocate_section (bfd *output_bfd,
 			 static link or an executable link with the
 			 symbol binding locally.  Mark it as belonging
 			 to module 1, the executable.  */
-		      bfd_put_NN (output_bfd, 1,
+		      bfd_put_NN (info->output_bfd, 1,
 				  htab->elf.sgot->contents + off);
-		      bfd_put_NN (output_bfd,
+		      bfd_put_NN (info->output_bfd,
 				  dtpoff (info, relocation),
 				  (htab->elf.sgot->contents
 				   + off + RISCV_ELF_WORD_BYTES));
@@ -3306,7 +3308,7 @@ riscv_elf_relocate_section (bfd *output_bfd,
 		{
 		  if (need_relocs)
 		    {
-		      bfd_put_NN (output_bfd, 0,
+		      bfd_put_NN (info->output_bfd, 0,
 				  htab->elf.sgot->contents + off + ie_off);
 		      outrel.r_offset = sec_addr (htab->elf.sgot)
 					+ off + ie_off;
@@ -3314,11 +3316,12 @@ riscv_elf_relocate_section (bfd *output_bfd,
 		      if (indx == 0)
 			outrel.r_addend = tpoff (info, relocation);
 		      outrel.r_info = ELFNN_R_INFO (indx, R_RISCV_TLS_TPRELNN);
-		      riscv_elf_append_rela (output_bfd, htab->elf.srelgot, &outrel);
+		      riscv_elf_append_rela (info->output_bfd,
+					     htab->elf.srelgot, &outrel);
 		    }
 		  else
 		    {
-		      bfd_put_NN (output_bfd, tpoff (info, relocation),
+		      bfd_put_NN (info->output_bfd, tpoff (info, relocation),
 				  htab->elf.sgot->contents + off + ie_off);
 		    }
 		}
@@ -3327,7 +3330,7 @@ riscv_elf_relocate_section (bfd *output_bfd,
 		{
 		  /* TLSDESC is always handled by the dynamic linker and always need
 		   * a relocation.  */
-		  bfd_put_NN (output_bfd, 0,
+		  bfd_put_NN (info->output_bfd, 0,
 			      htab->elf.sgot->contents + off + desc_off);
 		  outrel.r_offset = sec_addr (htab->elf.sgot)
 				    + off + desc_off;
@@ -3335,7 +3338,8 @@ riscv_elf_relocate_section (bfd *output_bfd,
 		  if (indx == 0)
 		    outrel.r_addend = tlsdescoff (info, relocation);
 		  outrel.r_info = ELFNN_R_INFO (indx, R_RISCV_TLSDESC);
-		  riscv_elf_append_rela (output_bfd, htab->elf.srelgot, &outrel);
+		  riscv_elf_append_rela (info->output_bfd,
+					 htab->elf.srelgot, &outrel);
 		}
 	    }
 
@@ -3362,7 +3366,7 @@ riscv_elf_relocate_section (bfd *output_bfd,
       if (unresolved_reloc
 	  && !((input_section->flags & SEC_DEBUGGING) != 0
 	       && h->def_dynamic)
-	  && _bfd_elf_section_offset (output_bfd, info, input_section,
+	  && _bfd_elf_section_offset (info->output_bfd, info, input_section,
 				      rel->r_offset) != (bfd_vma) -1)
 	{
 	  msg = bfd_asprintf (_("%%X%%P: unresolvable %s relocation against "
@@ -3441,13 +3445,12 @@ riscv_elf_relocate_section (bfd *output_bfd,
    dynamic sections here.  */
 
 static bool
-riscv_elf_finish_dynamic_symbol (bfd *output_bfd,
-				 struct bfd_link_info *info,
+riscv_elf_finish_dynamic_symbol (struct bfd_link_info *info,
 				 struct elf_link_hash_entry *h,
 				 Elf_Internal_Sym *sym)
 {
   struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (info);
-  elf_backend_data *bed = get_elf_backend_data (output_bfd);
+  elf_backend_data *bed = get_elf_backend_data (info->output_bfd);
 
   if (h->plt.offset != (bfd_vma) -1)
     {
@@ -3502,14 +3505,14 @@ riscv_elf_finish_dynamic_symbol (bfd *output_bfd,
 
 
       /* Fill in the PLT entry itself.  */
-      if (! htab->make_plt_entry (output_bfd, gotplt, got_offset,
+      if (! htab->make_plt_entry (info->output_bfd, gotplt, got_offset,
 				  plt, h->plt.offset))
 	return false;
 
 
       /* Fill in the initial value of the .got.plt entry.  */
       loc = gotplt->contents + (got_address - sec_addr (gotplt));
-      bfd_put_NN (output_bfd, sec_addr (plt), loc);
+      bfd_put_NN (info->output_bfd, sec_addr (plt), loc);
 
       rela.r_offset = got_address;
 
@@ -3539,7 +3542,7 @@ riscv_elf_finish_dynamic_symbol (bfd *output_bfd,
 	}
 
       loc = relplt->contents + plt_idx * sizeof (ElfNN_External_Rela);
-      bed->s->swap_reloca_out (output_bfd, &rela, loc);
+      bed->s->swap_reloca_out (info->output_bfd, &rela, loc);
 
       if (!h->def_regular)
 	{
@@ -3624,9 +3627,9 @@ riscv_elf_finish_dynamic_symbol (bfd *output_bfd,
 		 contains the real function address if we need pointer
 		 equality.  We load the GOT entry with the PLT entry.  */
 	      plt = htab->elf.splt ? htab->elf.splt : htab->elf.iplt;
-	      bfd_put_NN (output_bfd, (plt->output_section->vma
-				       + plt->output_offset
-				       + h->plt.offset),
+	      bfd_put_NN (info->output_bfd, (plt->output_section->vma
+					     + plt->output_offset
+					     + h->plt.offset),
 			  htab->elf.sgot->contents
 			  + (h->got.offset & ~(bfd_vma) 1));
 	      return true;
@@ -3654,12 +3657,12 @@ riscv_elf_finish_dynamic_symbol (bfd *output_bfd,
 	  BFD_ASSERT (h->dynindx != -1);
 	  rela.r_info = ELFNN_R_INFO (h->dynindx, R_RISCV_NN);
 	  rela.r_addend = 0;
-	  bfd_put_NN (output_bfd, 0,
+	  bfd_put_NN (info->output_bfd, 0,
 		      sgot->contents + (h->got.offset & ~(bfd_vma) 1));
 	}
 
       if (use_elf_append_rela)
-	riscv_elf_append_rela (output_bfd, srela, &rela);
+	riscv_elf_append_rela (info->output_bfd, srela, &rela);
       else
 	{
 	  /* Use riscv_elf_append_rela to add the dynamic relocs into
@@ -3673,7 +3676,7 @@ riscv_elf_finish_dynamic_symbol (bfd *output_bfd,
 	  bfd_vma iplt_idx = htab->last_iplt_index--;
 	  bfd_byte *loc = srela->contents
 			  + iplt_idx * sizeof (ElfNN_External_Rela);
-	  bed->s->swap_reloca_out (output_bfd, &rela, loc);
+	  bed->s->swap_reloca_out (info->output_bfd, &rela, loc);
 	}
     }
 
@@ -3692,7 +3695,7 @@ riscv_elf_finish_dynamic_symbol (bfd *output_bfd,
 	s = htab->elf.sreldynrelro;
       else
 	s = htab->elf.srelbss;
-      riscv_elf_append_rela (output_bfd, s, &rela);
+      riscv_elf_append_rela (info->output_bfd, s, &rela);
     }
 
   /* Mark some specially defined symbols as absolute.  */
@@ -3712,17 +3715,17 @@ riscv_elf_finish_local_dynamic_symbol (void **slot, void *inf)
   struct elf_link_hash_entry *h = (struct elf_link_hash_entry *) *slot;
   struct bfd_link_info *info = (struct bfd_link_info *) inf;
 
-  return riscv_elf_finish_dynamic_symbol (info->output_bfd, info, h, NULL);
+  return riscv_elf_finish_dynamic_symbol (info, h, NULL);
 }
 
 /* Finish up the dynamic sections.  */
 
 static bool
-riscv_finish_dyn (bfd *output_bfd, struct bfd_link_info *info,
+riscv_finish_dyn (struct bfd_link_info *info,
 		  bfd *dynobj, asection *sdyn)
 {
   struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (info);
-  elf_backend_data *bed = get_elf_backend_data (output_bfd);
+  elf_backend_data *bed = get_elf_backend_data (info->output_bfd);
   size_t dynsize = bed->s->sizeof_dyn;
   bfd_byte *dyncon, *dynconend;
 
@@ -3752,14 +3755,13 @@ riscv_finish_dyn (bfd *output_bfd, struct bfd_link_info *info,
 	  continue;
 	}
 
-      bed->s->swap_dyn_out (output_bfd, &dyn, dyncon);
+      bed->s->swap_dyn_out (info->output_bfd, &dyn, dyncon);
     }
   return true;
 }
 
 static bool
-riscv_elf_finish_dynamic_sections (bfd *output_bfd,
-				   struct bfd_link_info *info,
+riscv_elf_finish_dynamic_sections (struct bfd_link_info *info,
 				   bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   bfd *dynobj;
@@ -3780,7 +3782,7 @@ riscv_elf_finish_dynamic_sections (bfd *output_bfd,
       splt = htab->elf.splt;
       BFD_ASSERT (splt != NULL && sdyn != NULL);
 
-      ret = riscv_finish_dyn (output_bfd, info, dynobj, sdyn);
+      ret = riscv_finish_dyn (info, dynobj, sdyn);
 
       if (!ret)
 	return ret;
@@ -3788,7 +3790,7 @@ riscv_elf_finish_dynamic_sections (bfd *output_bfd,
       /* Fill in the head and tail entries in the procedure linkage table.  */
       if (splt->size > 0)
 	{
-	  ret = htab->make_plt_header (output_bfd, htab);
+	  ret = htab->make_plt_header (info->output_bfd, htab);
 	  if (!ret)
 	    return ret;
 
@@ -3810,8 +3812,8 @@ riscv_elf_finish_dynamic_sections (bfd *output_bfd,
 
       /* Write the first two entries in .got.plt, needed for the dynamic
 	 linker.  */
-      bfd_put_NN (output_bfd, (bfd_vma) -1, htab->elf.sgotplt->contents);
-      bfd_put_NN (output_bfd, (bfd_vma) 0,
+      bfd_put_NN (info->output_bfd, -1, htab->elf.sgotplt->contents);
+      bfd_put_NN (info->output_bfd, 0,
 		  htab->elf.sgotplt->contents + GOT_ENTRY_SIZE);
 
       elf_section_data (output_section)->this_hdr.sh_entsize = GOT_ENTRY_SIZE;
@@ -3826,7 +3828,7 @@ riscv_elf_finish_dynamic_sections (bfd *output_bfd,
 	  /* Set the first entry in the global offset table to the address of
 	     the dynamic section.  */
 	  bfd_vma val = sdyn ? sec_addr (sdyn) : 0;
-	  bfd_put_NN (output_bfd, val, htab->elf.sgot->contents);
+	  bfd_put_NN (info->output_bfd, val, htab->elf.sgot->contents);
 
 	  elf_section_data (output_section)->this_hdr.sh_entsize = GOT_ENTRY_SIZE;
 	}
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index 83fdf96a8a5..7dc72afa697 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -4000,7 +4000,7 @@ count_section_dynsyms (bfd *output_bfd, struct bfd_link_info *info)
 	if ((p->flags & SEC_EXCLUDE) == 0
 	    && (p->flags & SEC_ALLOC) != 0
 	    && elf_hash_table (info)->dynamic_relocs
-	    && !(*bed->elf_backend_omit_section_dynsym) (output_bfd, info, p))
+	    && !bed->elf_backend_omit_section_dynsym (info, p))
 	  ++count;
     }
   return count;
@@ -10041,8 +10041,7 @@ mips_elf_set_plt_sym_value (struct mips_elf_link_hash_entry *h, void *data)
    and check for any mips16 stub sections that we can discard.  */
 
 bool
-_bfd_mips_elf_late_size_sections (bfd *output_bfd,
-				  struct bfd_link_info *info)
+_bfd_mips_elf_late_size_sections (struct bfd_link_info *info)
 {
   bfd *dynobj;
   asection *s, *sreldyn;
@@ -10054,7 +10053,7 @@ _bfd_mips_elf_late_size_sections (bfd *output_bfd,
   BFD_ASSERT (htab != NULL);
 
   /* The .reginfo section has a fixed size.  */
-  s = bfd_get_section_by_name (output_bfd, ".reginfo");
+  s = bfd_get_section_by_name (info->output_bfd, ".reginfo");
   if (s != NULL)
     {
       bfd_set_section_size (s, sizeof (Elf32_External_RegInfo));
@@ -10062,7 +10061,7 @@ _bfd_mips_elf_late_size_sections (bfd *output_bfd,
     }
 
   /* The .MIPS.abiflags section has a fixed size.  */
-  s = bfd_get_section_by_name (output_bfd, ".MIPS.abiflags");
+  s = bfd_get_section_by_name (info->output_bfd, ".MIPS.abiflags");
   if (s != NULL)
     {
       bfd_set_section_size (s, sizeof (Elf_External_ABIFlags_v0));
@@ -10070,7 +10069,7 @@ _bfd_mips_elf_late_size_sections (bfd *output_bfd,
     }
 
   hti.info = info;
-  hti.output_bfd = output_bfd;
+  hti.output_bfd = info->output_bfd;
   hti.error = false;
   mips_elf_link_hash_traverse (htab, mips_elf_check_symbols, &hti);
   if (hti.error)
@@ -10088,9 +10087,9 @@ _bfd_mips_elf_late_size_sections (bfd *output_bfd,
 	  s = htab->root.interp;
 	  BFD_ASSERT (s != NULL);
 	  s->size
-	    = strlen (ELF_DYNAMIC_INTERPRETER (output_bfd)) + 1;
+	    = strlen (ELF_DYNAMIC_INTERPRETER (info->output_bfd)) + 1;
 	  s->contents
-	    = (bfd_byte *) ELF_DYNAMIC_INTERPRETER (output_bfd);
+	    = (bfd_byte *) ELF_DYNAMIC_INTERPRETER (info->output_bfd);
 	  s->alloced = 1;
 	}
 
@@ -10108,7 +10107,7 @@ _bfd_mips_elf_late_size_sections (bfd *output_bfd,
 	 haven't already in _bfd_elf_create_dynamic_sections.  */
       if (htab->root.splt && htab->plt_mips_offset + htab->plt_comp_offset != 0)
 	{
-	  bool micromips_p = (MICROMIPS_P (output_bfd)
+	  bool micromips_p = (MICROMIPS_P (info->output_bfd)
 				     && !htab->plt_mips_offset);
 	  unsigned int other = micromips_p ? STO_MICROMIPS : 0;
 	  bfd_vma isa_bit = micromips_p;
@@ -10123,9 +10122,9 @@ _bfd_mips_elf_late_size_sections (bfd *output_bfd,
 	    size = 4 * ARRAY_SIZE (mips_vxworks_shared_plt0_entry);
 	  else if (htab->root.target_os == is_vxworks)
 	    size = 4 * ARRAY_SIZE (mips_vxworks_exec_plt0_entry);
-	  else if (ABI_64_P (output_bfd))
+	  else if (ABI_64_P (info->output_bfd))
 	    size = 4 * ARRAY_SIZE (mips_n64_exec_plt0_entry);
-	  else if (ABI_N32_P (output_bfd))
+	  else if (ABI_N32_P (info->output_bfd))
 	    size = 4 * ARRAY_SIZE (mips_n32_exec_plt0_entry);
 	  else if (!micromips_p)
 	    size = 4 * ARRAY_SIZE (mips_o32_exec_plt0_entry);
@@ -10163,9 +10162,9 @@ _bfd_mips_elf_late_size_sections (bfd *output_bfd,
   /* Allocate space for global sym dynamic relocs.  */
   elf_link_hash_traverse (&htab->root, allocate_dynrelocs, info);
 
-  mips_elf_estimate_stub_size (output_bfd, info);
+  mips_elf_estimate_stub_size (info->output_bfd, info);
 
-  if (!mips_elf_lay_out_got (output_bfd, info))
+  if (!mips_elf_lay_out_got (info->output_bfd, info))
     return false;
 
   mips_elf_lay_out_lazy_stubs (info);
@@ -10199,7 +10198,7 @@ _bfd_mips_elf_late_size_sections (bfd *output_bfd,
 		 there exists a relocation to a read only section or
 		 not.  */
 	      outname = bfd_section_name (s->output_section);
-	      target = bfd_get_section_by_name (output_bfd, outname + 4);
+	      target = bfd_get_section_by_name (info->output_bfd, outname + 4);
 	      if ((target != NULL
 		   && (target->flags & SEC_READONLY) != 0
 		   && (target->flags & SEC_ALLOC) != 0)
@@ -10226,9 +10225,9 @@ _bfd_mips_elf_late_size_sections (bfd *output_bfd,
 	{
 	  /* We add a room for __rld_map.  It will be filled in by the
 	     rtld to contain a pointer to the _r_debug structure.  */
-	  s->size += MIPS_ELF_RLD_MAP_SIZE (output_bfd);
+	  s->size += MIPS_ELF_RLD_MAP_SIZE (info->output_bfd);
 	}
-      else if (SGI_COMPAT (output_bfd)
+      else if (SGI_COMPAT (info->output_bfd)
 	       && startswith (name, ".compact_rel"))
 	s->size += htab->compact_rel_size;
       else if (s == htab->root.splt)
@@ -10236,7 +10235,7 @@ _bfd_mips_elf_late_size_sections (bfd *output_bfd,
 	  /* If the last PLT entry has a branch delay slot, allocate
 	     room for an extra nop to fill the delay slot.  This is
 	     for CPUs without load interlocking.  */
-	  if (! LOAD_INTERLOCKS_P (output_bfd)
+	  if (! LOAD_INTERLOCKS_P (info->output_bfd)
 	      && htab->root.target_os != is_vxworks
 	      && s->size > 0)
 	    s->size += 4;
@@ -10293,12 +10292,12 @@ _bfd_mips_elf_late_size_sections (bfd *output_bfd,
       /* The DT_DEBUG entry may be filled in by the dynamic linker and
 	 used by the debugger.  */
       if (bfd_link_executable (info)
-	  && !SGI_COMPAT (output_bfd)
+	  && !SGI_COMPAT (info->output_bfd)
 	  && !MIPS_ELF_ADD_DYNAMIC_ENTRY (info, DT_DEBUG, 0))
 	return false;
 
       if (reltext
-	  && (SGI_COMPAT (output_bfd)
+	  && (SGI_COMPAT (info->output_bfd)
 	      || htab->root.target_os == is_vxworks))
 	info->flags |= DF_TEXTREL;
 
@@ -10380,7 +10379,7 @@ _bfd_mips_elf_late_size_sections (bfd *output_bfd,
 
 	  if (IRIX_COMPAT (dynobj) == ict_irix6
 	      && (bfd_get_section_by_name
-		  (output_bfd, MIPS_ELF_OPTIONS_SECTION_NAME (dynobj)))
+		  (info->output_bfd, MIPS_ELF_OPTIONS_SECTION_NAME (dynobj)))
 	      && !MIPS_ELF_ADD_DYNAMIC_ENTRY (info, DT_MIPS_OPTIONS, 0))
 	    return false;
 	}
@@ -10400,7 +10399,7 @@ _bfd_mips_elf_late_size_sections (bfd *output_bfd,
 	}
 #ifdef OBJ_MAYBE_ELF_VXWORKS
       if (htab->root.target_os == is_vxworks
-	  && !elf_vxworks_add_dynamic_entries (output_bfd, info))
+	  && !elf_vxworks_add_dynamic_entries (info))
 	return false;
 #endif /* OBJ_MAYBE_ELF_VXWORKS */
     }
@@ -10501,7 +10500,7 @@ mips_reloc_against_discarded_section (bfd *output_bfd,
 /* Relocate a MIPS ELF section.  */
 
 int
-_bfd_mips_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
+_bfd_mips_elf_relocate_section (struct bfd_link_info *info,
 				bfd *input_bfd, asection *input_section,
 				bfd_byte *contents, Elf_Internal_Rela *relocs,
 				Elf_Internal_Sym *local_syms,
@@ -10522,7 +10521,7 @@ _bfd_mips_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
       /* TRUE if the relocation is a RELA relocation, rather than a
 	 REL relocation.  */
       bool rela_relocation_p = true;
-      unsigned int r_type = ELF_R_TYPE (output_bfd, rel->r_info);
+      unsigned int r_type = ELF_R_TYPE (info->output_bfd, rel->r_info);
       const char *msg;
       unsigned long r_symndx;
       asection *sec;
@@ -10562,7 +10561,8 @@ _bfd_mips_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 
       if (sec != NULL && discarded_section (sec))
 	{
-	  mips_reloc_against_discarded_section (output_bfd, info, input_bfd,
+	  mips_reloc_against_discarded_section (info->output_bfd, info,
+						input_bfd,
 						input_section, &rel, &relend,
 						rel_reloc, howto, contents);
 	  continue;
@@ -10631,13 +10631,13 @@ _bfd_mips_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	    }
 	  else
 	    addend = rel->r_addend;
-	  mips_elf_adjust_addend (output_bfd, info, input_bfd,
+	  mips_elf_adjust_addend (info->output_bfd, info, input_bfd,
 				  local_syms, local_sections, rel);
 	}
 
       if (bfd_link_relocatable (info))
 	{
-	  if (r_type == R_MIPS_64 && ! NEWABI_P (output_bfd)
+	  if (r_type == R_MIPS_64 && ! NEWABI_P (info->output_bfd)
 	      && bfd_big_endian (input_bfd))
 	    rel->r_offset -= 4;
 
@@ -10660,7 +10660,7 @@ _bfd_mips_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		 source of the addend in the final link.  */
 	      addend &= howto->src_mask;
 
-	      if (r_type == R_MIPS_64 && ! NEWABI_P (output_bfd))
+	      if (r_type == R_MIPS_64 && ! NEWABI_P (info->output_bfd))
 		/* See the comment above about using R_MIPS_64 in the 32-bit
 		   ABI.  Here, we need to update the addend.  It would be
 		   possible to get away with just using the R_MIPS_32 reloc
@@ -10722,7 +10722,7 @@ _bfd_mips_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	use_saved_addend_p = false;
 
       /* Figure out what value we are supposed to relocate.  */
-      switch (mips_elf_calculate_relocation (output_bfd, input_bfd,
+      switch (mips_elf_calculate_relocation (info->output_bfd, input_bfd,
 					     input_section, contents,
 					     info, rel, addend, howto,
 					     local_syms, local_sections,
@@ -10814,7 +10814,7 @@ _bfd_mips_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	  continue;
 	}
 
-      if (r_type == R_MIPS_64 && ! NEWABI_P (output_bfd))
+      if (r_type == R_MIPS_64 && ! NEWABI_P (info->output_bfd))
 	/* See the comment above about using R_MIPS_64 in the 32-bit
 	   ABI.  Until now, we've been using the HOWTO for R_MIPS_32;
 	   that calculated the right value.  Now, however, we
@@ -10983,8 +10983,7 @@ mips_elf_create_la25_stub (void **slot, void *data)
    adjust it appropriately now.  */
 
 static void
-mips_elf_irix6_finish_dynamic_symbol (bfd *abfd ATTRIBUTE_UNUSED,
-				      const char *name, Elf_Internal_Sym *sym)
+mips_elf_irix6_finish_dynamic_symbol (const char *name, Elf_Internal_Sym *sym)
 {
   /* The linker script takes care of providing names and values for
      these, but we must place them into the right sections.  */
@@ -11033,8 +11032,7 @@ mips_elf_irix6_finish_dynamic_symbol (bfd *abfd ATTRIBUTE_UNUSED,
    dynamic sections here.  */
 
 bool
-_bfd_mips_elf_finish_dynamic_symbol (bfd *output_bfd,
-				     struct bfd_link_info *info,
+_bfd_mips_elf_finish_dynamic_symbol (struct bfd_link_info *info,
 				     struct elf_link_hash_entry *h,
 				     Elf_Internal_Sym *sym)
 {
@@ -11087,14 +11085,14 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd *output_bfd,
 
       /* The PLT sequence is not safe for N64 if .got.plt entry's address
 	 cannot be loaded in two instructions.  */
-      if (ABI_64_P (output_bfd)
+      if (ABI_64_P (info->output_bfd)
 	  && ((got_address + 0x80008000) & ~(bfd_vma) 0xffffffff) != 0)
 	{
 	  _bfd_error_handler
 	    /* xgettext:c-format */
 	    (_("%pB: `%pA' entry VMA of %#" PRIx64 " outside the 32-bit range "
 	       "supported; consider using `-Ttext-segment=...'"),
-	     output_bfd,
+	     info->output_bfd,
 	     htab->root.sgotplt->output_section,
 	     (int64_t) got_address);
 	  bfd_set_error (bfd_error_no_error);
@@ -11104,10 +11102,10 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd *output_bfd,
       /* Initially point the .got.plt entry at the PLT header.  */
       loc = (htab->root.sgotplt->contents
 	     + got_index * MIPS_ELF_GOT_SIZE (dynobj));
-      if (ABI_64_P (output_bfd))
-	bfd_put_64 (output_bfd, header_address, loc);
+      if (ABI_64_P (info->output_bfd))
+	bfd_put_64 (info->output_bfd, header_address, loc);
       else
-	bfd_put_32 (output_bfd, header_address, loc);
+	bfd_put_32 (info->output_bfd, header_address, loc);
 
       /* Now handle the PLT itself.  First the standard entry (the order
 	 does not matter, we just have to pick one).  */
@@ -11124,29 +11122,30 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd *output_bfd,
 	  loc = htab->root.splt->contents + plt_offset;
 
 	  /* Pick the load opcode.  */
-	  load = MIPS_ELF_LOAD_WORD (output_bfd);
+	  load = MIPS_ELF_LOAD_WORD (info->output_bfd);
 
 	  /* Fill in the PLT entry itself.  */
 
-	  if (MIPSR6_P (output_bfd))
+	  if (MIPSR6_P (info->output_bfd))
 	    plt_entry = htab->compact_branches ? mipsr6_exec_plt_entry_compact
 					       : mipsr6_exec_plt_entry;
 	  else
 	    plt_entry = mips_exec_plt_entry;
-	  bfd_put_32 (output_bfd, plt_entry[0] | got_address_high, loc);
-	  bfd_put_32 (output_bfd, plt_entry[1] | got_address_low | load,
+	  bfd_put_32 (info->output_bfd, plt_entry[0] | got_address_high, loc);
+	  bfd_put_32 (info->output_bfd, plt_entry[1] | got_address_low | load,
 		      loc + 4);
 
-	  if (! LOAD_INTERLOCKS_P (output_bfd)
-	      || (MIPSR6_P (output_bfd) && htab->compact_branches))
+	  if (! LOAD_INTERLOCKS_P (info->output_bfd)
+	      || (MIPSR6_P (info->output_bfd) && htab->compact_branches))
 	    {
-	      bfd_put_32 (output_bfd, plt_entry[2] | got_address_low, loc + 8);
-	      bfd_put_32 (output_bfd, plt_entry[3], loc + 12);
+	      bfd_put_32 (info->output_bfd, plt_entry[2] | got_address_low,
+			  loc + 8);
+	      bfd_put_32 (info->output_bfd, plt_entry[3], loc + 12);
 	    }
 	  else
 	    {
-	      bfd_put_32 (output_bfd, plt_entry[3], loc + 8);
-	      bfd_put_32 (output_bfd, plt_entry[2] | got_address_low,
+	      bfd_put_32 (info->output_bfd, plt_entry[3], loc + 8);
+	      bfd_put_32 (info->output_bfd, plt_entry[2] | got_address_low,
 			  loc + 12);
 	    }
 	}
@@ -11165,30 +11164,30 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd *output_bfd,
 	  loc = htab->root.splt->contents + plt_offset;
 
 	  /* Fill in the PLT entry itself.  */
-	  if (!MICROMIPS_P (output_bfd))
+	  if (!MICROMIPS_P (info->output_bfd))
 	    {
 	      const bfd_vma *plt_entry = mips16_o32_exec_plt_entry;
 
-	      bfd_put_16 (output_bfd, plt_entry[0], loc);
-	      bfd_put_16 (output_bfd, plt_entry[1], loc + 2);
-	      bfd_put_16 (output_bfd, plt_entry[2], loc + 4);
-	      bfd_put_16 (output_bfd, plt_entry[3], loc + 6);
-	      bfd_put_16 (output_bfd, plt_entry[4], loc + 8);
-	      bfd_put_16 (output_bfd, plt_entry[5], loc + 10);
-	      bfd_put_32 (output_bfd, got_address, loc + 12);
+	      bfd_put_16 (info->output_bfd, plt_entry[0], loc);
+	      bfd_put_16 (info->output_bfd, plt_entry[1], loc + 2);
+	      bfd_put_16 (info->output_bfd, plt_entry[2], loc + 4);
+	      bfd_put_16 (info->output_bfd, plt_entry[3], loc + 6);
+	      bfd_put_16 (info->output_bfd, plt_entry[4], loc + 8);
+	      bfd_put_16 (info->output_bfd, plt_entry[5], loc + 10);
+	      bfd_put_32 (info->output_bfd, got_address, loc + 12);
 	    }
 	  else if (htab->insn32)
 	    {
 	      const bfd_vma *plt_entry = micromips_insn32_o32_exec_plt_entry;
 
-	      bfd_put_16 (output_bfd, plt_entry[0], loc);
-	      bfd_put_16 (output_bfd, got_address_high, loc + 2);
-	      bfd_put_16 (output_bfd, plt_entry[2], loc + 4);
-	      bfd_put_16 (output_bfd, got_address_low, loc + 6);
-	      bfd_put_16 (output_bfd, plt_entry[4], loc + 8);
-	      bfd_put_16 (output_bfd, plt_entry[5], loc + 10);
-	      bfd_put_16 (output_bfd, plt_entry[6], loc + 12);
-	      bfd_put_16 (output_bfd, got_address_low, loc + 14);
+	      bfd_put_16 (info->output_bfd, plt_entry[0], loc);
+	      bfd_put_16 (info->output_bfd, got_address_high, loc + 2);
+	      bfd_put_16 (info->output_bfd, plt_entry[2], loc + 4);
+	      bfd_put_16 (info->output_bfd, got_address_low, loc + 6);
+	      bfd_put_16 (info->output_bfd, plt_entry[4], loc + 8);
+	      bfd_put_16 (info->output_bfd, plt_entry[5], loc + 10);
+	      bfd_put_16 (info->output_bfd, plt_entry[6], loc + 12);
+	      bfd_put_16 (info->output_bfd, got_address_low, loc + 14);
 	    }
 	  else
 	    {
@@ -11209,25 +11208,26 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd *output_bfd,
 		    /* xgettext:c-format */
 		    (_("%pB: `%pA' offset of %" PRId64 " from `%pA' "
 		       "beyond the range of ADDIUPC"),
-		     output_bfd,
+		     info->output_bfd,
 		     htab->root.sgotplt->output_section,
 		     (int64_t) gotpc_offset,
 		     htab->root.splt->output_section);
 		  bfd_set_error (bfd_error_no_error);
 		  return false;
 		}
-	      bfd_put_16 (output_bfd,
+	      bfd_put_16 (info->output_bfd,
 			  plt_entry[0] | ((gotpc_offset >> 18) & 0x7f), loc);
-	      bfd_put_16 (output_bfd, (gotpc_offset >> 2) & 0xffff, loc + 2);
-	      bfd_put_16 (output_bfd, plt_entry[2], loc + 4);
-	      bfd_put_16 (output_bfd, plt_entry[3], loc + 6);
-	      bfd_put_16 (output_bfd, plt_entry[4], loc + 8);
-	      bfd_put_16 (output_bfd, plt_entry[5], loc + 10);
+	      bfd_put_16 (info->output_bfd, (gotpc_offset >> 2) & 0xffff,
+			  loc + 2);
+	      bfd_put_16 (info->output_bfd, plt_entry[2], loc + 4);
+	      bfd_put_16 (info->output_bfd, plt_entry[3], loc + 6);
+	      bfd_put_16 (info->output_bfd, plt_entry[4], loc + 8);
+	      bfd_put_16 (info->output_bfd, plt_entry[5], loc + 10);
 	    }
 	}
 
       /* Emit an R_MIPS_JUMP_SLOT relocation against the .got.plt entry.  */
-      mips_elf_output_dynamic_relocation (output_bfd, htab->root.srelplt,
+      mips_elf_output_dynamic_relocation (info->output_bfd, htab->root.srelplt,
 					  got_index - 2, h->dynindx,
 					  R_MIPS_JUMP_SLOT, got_address);
 
@@ -11248,7 +11248,7 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd *output_bfd,
   if (h->plt.plist != NULL && h->plt.plist->stub_offset != MINUS_ONE)
     {
       /* We've decided to create a lazy-binding stub.  */
-      bool micromips_p = MICROMIPS_P (output_bfd);
+      bool micromips_p = MICROMIPS_P (info->output_bfd);
       unsigned int other = micromips_p ? STO_MICROMIPS : 0;
       bfd_vma stub_size = htab->function_stub_size;
       bfd_byte stub[MIPS_FUNCTION_STUB_BIG_SIZE];
@@ -11275,7 +11275,7 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd *output_bfd,
 	{
 	  _bfd_error_handler
 	    (_("%pB: cannot handle more than %d dynamic symbols"),
-	     output_bfd, 0x7fffffff);
+	     info->output_bfd, 0x7fffffff);
 	  bfd_set_error (bfd_error_bad_value);
 	  return false;
 	}
@@ -11284,92 +11284,95 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd *output_bfd,
       if (micromips_p)
 	{
 	  idx = 0;
-	  bfd_put_micromips_32 (output_bfd, STUB_LW_MICROMIPS (output_bfd),
+	  bfd_put_micromips_32 (info->output_bfd,
+				STUB_LW_MICROMIPS (info->output_bfd),
 				stub + idx);
 	  idx += 4;
 	  if (htab->insn32)
 	    {
-	      bfd_put_micromips_32 (output_bfd,
+	      bfd_put_micromips_32 (info->output_bfd,
 				    STUB_MOVE32_MICROMIPS, stub + idx);
 	      idx += 4;
 	    }
 	  else
 	    {
-	      bfd_put_16 (output_bfd, STUB_MOVE_MICROMIPS, stub + idx);
+	      bfd_put_16 (info->output_bfd, STUB_MOVE_MICROMIPS, stub + idx);
 	      idx += 2;
 	    }
 	  if (stub_size == stub_big_size)
 	    {
 	      long dynindx_hi = (h->dynindx >> 16) & 0x7fff;
 
-	      bfd_put_micromips_32 (output_bfd,
+	      bfd_put_micromips_32 (info->output_bfd,
 				    STUB_LUI_MICROMIPS (dynindx_hi),
 				    stub + idx);
 	      idx += 4;
 	    }
 	  if (htab->insn32)
 	    {
-	      bfd_put_micromips_32 (output_bfd, STUB_JALR32_MICROMIPS,
+	      bfd_put_micromips_32 (info->output_bfd, STUB_JALR32_MICROMIPS,
 				    stub + idx);
 	      idx += 4;
 	    }
 	  else
 	    {
-	      bfd_put_16 (output_bfd, STUB_JALR_MICROMIPS, stub + idx);
+	      bfd_put_16 (info->output_bfd, STUB_JALR_MICROMIPS, stub + idx);
 	      idx += 2;
 	    }
 
 	  /* If a large stub is not required and sign extension is not a
 	     problem, then use legacy code in the stub.  */
 	  if (stub_size == stub_big_size)
-	    bfd_put_micromips_32 (output_bfd,
+	    bfd_put_micromips_32 (info->output_bfd,
 				  STUB_ORI_MICROMIPS (h->dynindx & 0xffff),
 				  stub + idx);
 	  else if (h->dynindx & ~0x7fff)
-	    bfd_put_micromips_32 (output_bfd,
+	    bfd_put_micromips_32 (info->output_bfd,
 				  STUB_LI16U_MICROMIPS (h->dynindx & 0xffff),
 				  stub + idx);
 	  else
-	    bfd_put_micromips_32 (output_bfd,
-				  STUB_LI16S_MICROMIPS (output_bfd,
+	    bfd_put_micromips_32 (info->output_bfd,
+				  STUB_LI16S_MICROMIPS (info->output_bfd,
 							h->dynindx),
 				  stub + idx);
 	}
       else
 	{
 	  idx = 0;
-	  bfd_put_32 (output_bfd, STUB_LW (output_bfd), stub + idx);
+	  bfd_put_32 (info->output_bfd, STUB_LW (info->output_bfd), stub + idx);
 	  idx += 4;
-	  bfd_put_32 (output_bfd, STUB_MOVE, stub + idx);
+	  bfd_put_32 (info->output_bfd, STUB_MOVE, stub + idx);
 	  idx += 4;
 	  if (stub_size == stub_big_size)
 	    {
-	      bfd_put_32 (output_bfd, STUB_LUI ((h->dynindx >> 16) & 0x7fff),
+	      bfd_put_32 (info->output_bfd,
+			  STUB_LUI ((h->dynindx >> 16) & 0x7fff),
 			  stub + idx);
 	      idx += 4;
 	    }
 
-	  if (!(MIPSR6_P (output_bfd) && htab->compact_branches))
+	  if (!(MIPSR6_P (info->output_bfd) && htab->compact_branches))
 	    {
-	      bfd_put_32 (output_bfd, STUB_JALR, stub + idx);
+	      bfd_put_32 (info->output_bfd, STUB_JALR, stub + idx);
 	      idx += 4;
 	    }
 
 	  /* If a large stub is not required and sign extension is not a
 	     problem, then use legacy code in the stub.  */
 	  if (stub_size == stub_big_size)
-	    bfd_put_32 (output_bfd, STUB_ORI (h->dynindx & 0xffff),
+	    bfd_put_32 (info->output_bfd, STUB_ORI (h->dynindx & 0xffff),
 			stub + idx);
 	  else if (h->dynindx & ~0x7fff)
-	    bfd_put_32 (output_bfd, STUB_LI16U (h->dynindx & 0xffff),
+	    bfd_put_32 (info->output_bfd, STUB_LI16U (h->dynindx & 0xffff),
 			stub + idx);
 	  else
-	    bfd_put_32 (output_bfd, STUB_LI16S (output_bfd, h->dynindx),
+	    bfd_put_32 (info->output_bfd,
+			STUB_LI16S (info->output_bfd, h->dynindx),
 			stub + idx);
 	  idx += 4;
 
-	  if (MIPSR6_P (output_bfd) && htab->compact_branches)
-	    bfd_put_32 (output_bfd, STUB_JALRC, stub + idx);
+	  if (MIPSR6_P (info->output_bfd) && htab->compact_branches)
+	    bfd_put_32 (info->output_bfd, STUB_JALRC, stub + idx);
 	}
 
       BFD_ASSERT (h->plt.plist->stub_offset <= htab->sstubs->size);
@@ -11417,8 +11420,8 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd *output_bfd,
       bfd_vma value;
 
       value = sym->st_value;
-      offset = mips_elf_primary_global_got_index (output_bfd, info, h);
-      MIPS_ELF_PUT_WORD (output_bfd, value, sgot->contents + offset);
+      offset = mips_elf_primary_global_got_index (info->output_bfd, info, h);
+      MIPS_ELF_PUT_WORD (info->output_bfd, value, sgot->contents + offset);
     }
 
   if (hmips->global_got_area != GGA_NONE && g->next)
@@ -11429,7 +11432,7 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd *output_bfd,
 
       gg = g;
 
-      e.abfd = output_bfd;
+      e.abfd = info->output_bfd;
       e.symndx = -1;
       e.d.h = hmips;
       e.tls_type = GOT_TLS_NONE;
@@ -11456,21 +11459,22 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd *output_bfd,
 		  Elf_Internal_Rela rel[3];
 
 		  memset (rel, 0, sizeof (rel));
-		  if (ABI_64_P (output_bfd))
-		    rel[0].r_info = ELF_R_INFO (output_bfd, 0, R_MIPS_64);
+		  if (ABI_64_P (info->output_bfd))
+		    rel[0].r_info = ELF_R_INFO (info->output_bfd, 0, R_MIPS_64);
 		  else
-		    rel[0].r_info = ELF_R_INFO (output_bfd, 0, R_MIPS_32);
+		    rel[0].r_info = ELF_R_INFO (info->output_bfd, 0, R_MIPS_32);
 		  rel[0].r_offset = rel[1].r_offset = rel[2].r_offset = offset;
 
 		  entry = 0;
 		  if (! (mips_elf_create_dynamic_relocation
-			 (output_bfd, info, rel,
+			 (info->output_bfd, info, rel,
 			  e.d.h, NULL, sym->st_value, &entry, sgot)))
 		    return false;
 		}
 	      else
 		entry = sym->st_value;
-	      MIPS_ELF_PUT_WORD (output_bfd, entry, sgot->contents + offset);
+	      MIPS_ELF_PUT_WORD (info->output_bfd, entry,
+				 sgot->contents + offset);
 	    }
 	}
     }
@@ -11487,7 +11491,7 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd *output_bfd,
       sym->st_info = ELF_ST_INFO (STB_GLOBAL, STT_SECTION);
       sym->st_value = 1;
     }
-  else if (SGI_COMPAT (output_bfd))
+  else if (SGI_COMPAT (info->output_bfd))
     {
       if (strcmp (name, mips_elf_dynsym_rtproc_names[0]) == 0
 	  || strcmp (name, mips_elf_dynsym_rtproc_names[1]) == 0)
@@ -11526,13 +11530,13 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd *output_bfd,
       symval = (h->root.u.def.section->output_section->vma
 		+ h->root.u.def.section->output_offset
 		+ h->root.u.def.value);
-      mips_elf_output_dynamic_relocation (output_bfd, s, s->reloc_count++,
+      mips_elf_output_dynamic_relocation (info->output_bfd, s, s->reloc_count++,
 					  h->dynindx, R_MIPS_COPY, symval);
     }
 
   /* Handle the IRIX6-specific symbols.  */
-  if (IRIX_COMPAT (output_bfd) == ict_irix6)
-    mips_elf_irix6_finish_dynamic_symbol (output_bfd, name, sym);
+  if (IRIX_COMPAT (info->output_bfd) == ict_irix6)
+    mips_elf_irix6_finish_dynamic_symbol (name, sym);
 
   /* Keep dynamic compressed symbols odd.  This allows the dynamic linker
      to treat compressed symbols like any other.  */
@@ -11553,8 +11557,7 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd *output_bfd,
 /* Likewise, for VxWorks.  */
 
 bool
-_bfd_mips_vxworks_finish_dynamic_symbol (bfd *output_bfd,
-					 struct bfd_link_info *info,
+_bfd_mips_vxworks_finish_dynamic_symbol (struct bfd_link_info *info,
 					 struct elf_link_hash_entry *h,
 					 Elf_Internal_Sym *sym)
 {
@@ -11594,7 +11597,7 @@ _bfd_mips_vxworks_finish_dynamic_symbol (bfd *output_bfd,
       /* Calculate the address of the .got.plt entry.  */
       got_address = (htab->root.sgotplt->output_section->vma
 		     + htab->root.sgotplt->output_offset
-		     + gotplt_index * MIPS_ELF_GOT_SIZE (output_bfd));
+		     + gotplt_index * MIPS_ELF_GOT_SIZE (info->output_bfd));
 
       /* Calculate the offset of the .got.plt entry from
 	 _GLOBAL_OFFSET_TABLE_.  */
@@ -11605,9 +11608,9 @@ _bfd_mips_vxworks_finish_dynamic_symbol (bfd *output_bfd,
       branch_offset = -(plt_offset / 4 + 1) & 0xffff;
 
       /* Fill in the initial value of the .got.plt entry.  */
-      bfd_put_32 (output_bfd, plt_address,
+      bfd_put_32 (info->output_bfd, plt_address,
 		  (htab->root.sgotplt->contents
-		   + gotplt_index * MIPS_ELF_GOT_SIZE (output_bfd)));
+		   + gotplt_index * MIPS_ELF_GOT_SIZE (info->output_bfd)));
 
       /* Find out where the .plt entry should go.  */
       loc = htab->root.splt->contents + plt_offset;
@@ -11615,8 +11618,8 @@ _bfd_mips_vxworks_finish_dynamic_symbol (bfd *output_bfd,
       if (bfd_link_pic (info))
 	{
 	  plt_entry = mips_vxworks_shared_plt_entry;
-	  bfd_put_32 (output_bfd, plt_entry[0] | branch_offset, loc);
-	  bfd_put_32 (output_bfd, plt_entry[1] | gotplt_index, loc + 4);
+	  bfd_put_32 (info->output_bfd, plt_entry[0] | branch_offset, loc);
+	  bfd_put_32 (info->output_bfd, plt_entry[1] | gotplt_index, loc + 4);
 	}
       else
 	{
@@ -11626,14 +11629,16 @@ _bfd_mips_vxworks_finish_dynamic_symbol (bfd *output_bfd,
 	  got_address_high = ((got_address + 0x8000) >> 16) & 0xffff;
 	  got_address_low = got_address & 0xffff;
 
-	  bfd_put_32 (output_bfd, plt_entry[0] | branch_offset, loc);
-	  bfd_put_32 (output_bfd, plt_entry[1] | gotplt_index, loc + 4);
-	  bfd_put_32 (output_bfd, plt_entry[2] | got_address_high, loc + 8);
-	  bfd_put_32 (output_bfd, plt_entry[3] | got_address_low, loc + 12);
-	  bfd_put_32 (output_bfd, plt_entry[4], loc + 16);
-	  bfd_put_32 (output_bfd, plt_entry[5], loc + 20);
-	  bfd_put_32 (output_bfd, plt_entry[6], loc + 24);
-	  bfd_put_32 (output_bfd, plt_entry[7], loc + 28);
+	  bfd_put_32 (info->output_bfd, plt_entry[0] | branch_offset, loc);
+	  bfd_put_32 (info->output_bfd, plt_entry[1] | gotplt_index, loc + 4);
+	  bfd_put_32 (info->output_bfd, plt_entry[2] | got_address_high,
+		      loc + 8);
+	  bfd_put_32 (info->output_bfd, plt_entry[3] | got_address_low,
+		      loc + 12);
+	  bfd_put_32 (info->output_bfd, plt_entry[4], loc + 16);
+	  bfd_put_32 (info->output_bfd, plt_entry[5], loc + 20);
+	  bfd_put_32 (info->output_bfd, plt_entry[6], loc + 24);
+	  bfd_put_32 (info->output_bfd, plt_entry[7], loc + 28);
 
 	  loc = (htab->srelplt2->contents
 		 + (gotplt_index * 3 + 2) * sizeof (Elf32_External_Rela));
@@ -11642,20 +11647,20 @@ _bfd_mips_vxworks_finish_dynamic_symbol (bfd *output_bfd,
 	  rel.r_offset = got_address;
 	  rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_MIPS_32);
 	  rel.r_addend = plt_offset;
-	  bfd_elf32_swap_reloca_out (output_bfd, &rel, loc);
+	  bfd_elf32_swap_reloca_out (info->output_bfd, &rel, loc);
 
 	  /* Emit a relocation for the lui of %hi(<.got.plt slot>).  */
 	  loc += sizeof (Elf32_External_Rela);
 	  rel.r_offset = plt_address + 8;
 	  rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_MIPS_HI16);
 	  rel.r_addend = got_offset;
-	  bfd_elf32_swap_reloca_out (output_bfd, &rel, loc);
+	  bfd_elf32_swap_reloca_out (info->output_bfd, &rel, loc);
 
 	  /* Emit a relocation for the addiu of %lo(<.got.plt slot>).  */
 	  loc += sizeof (Elf32_External_Rela);
 	  rel.r_offset += 4;
 	  rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_MIPS_LO16);
-	  bfd_elf32_swap_reloca_out (output_bfd, &rel, loc);
+	  bfd_elf32_swap_reloca_out (info->output_bfd, &rel, loc);
 	}
 
       /* Emit an R_MIPS_JUMP_SLOT relocation against the .got.plt entry.  */
@@ -11664,7 +11669,7 @@ _bfd_mips_vxworks_finish_dynamic_symbol (bfd *output_bfd,
       rel.r_offset = got_address;
       rel.r_info = ELF32_R_INFO (h->dynindx, R_MIPS_JUMP_SLOT);
       rel.r_addend = 0;
-      bfd_elf32_swap_reloca_out (output_bfd, &rel, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rel, loc);
 
       if (!h->def_regular)
 	sym->st_shndx = SHN_UNDEF;
@@ -11685,8 +11690,9 @@ _bfd_mips_vxworks_finish_dynamic_symbol (bfd *output_bfd,
       asection *s;
 
       /* Install the symbol value in the GOT.   */
-      offset = mips_elf_primary_global_got_index (output_bfd, info, h);
-      MIPS_ELF_PUT_WORD (output_bfd, sym->st_value, sgot->contents + offset);
+      offset = mips_elf_primary_global_got_index (info->output_bfd, info, h);
+      MIPS_ELF_PUT_WORD (info->output_bfd, sym->st_value,
+			 sgot->contents + offset);
 
       /* Add a dynamic relocation for it.  */
       s = mips_elf_rel_dyn_section (info, false);
@@ -11718,7 +11724,7 @@ _bfd_mips_vxworks_finish_dynamic_symbol (bfd *output_bfd,
       else
 	srel = htab->root.srelbss;
       loc = srel->contents + srel->reloc_count * sizeof (Elf32_External_Rela);
-      bfd_elf32_swap_reloca_out (output_bfd, &rel, loc);
+      bfd_elf32_swap_reloca_out (info->output_bfd, &rel, loc);
       ++srel->reloc_count;
     }
 
@@ -11940,8 +11946,7 @@ mips_vxworks_finish_shared_plt (bfd *output_bfd, struct bfd_link_info *info)
 /* Finish up the dynamic sections.  */
 
 bool
-_bfd_mips_elf_finish_dynamic_sections (bfd *output_bfd,
-				       struct bfd_link_info *info,
+_bfd_mips_elf_finish_dynamic_sections (struct bfd_link_info *info,
 				       bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   bfd *dynobj;
@@ -11968,7 +11973,7 @@ _bfd_mips_elf_finish_dynamic_sections (bfd *output_bfd,
       BFD_ASSERT (sdyn != NULL);
       BFD_ASSERT (gg != NULL);
 
-      g = mips_elf_bfd_got (output_bfd, false);
+      g = mips_elf_bfd_got (info->output_bfd, false);
       BFD_ASSERT (g != NULL);
 
       for (b = sdyn->contents;
@@ -12041,7 +12046,7 @@ _bfd_mips_elf_finish_dynamic_sections (bfd *output_bfd,
 	      break;
 
 	    case DT_MIPS_BASE_ADDRESS:
-	      s = output_bfd->sections;
+	      s = info->output_bfd->sections;
 	      BFD_ASSERT (s != NULL);
 	      dyn.d_un.d_ptr = s->vma & ~(bfd_vma) 0xffff;
 	      break;
@@ -12054,7 +12059,7 @@ _bfd_mips_elf_finish_dynamic_sections (bfd *output_bfd,
 	      /* The index into the dynamic symbol table which is the
 		 entry of the first external symbol that is not
 		 referenced within the same object.  */
-	      dyn.d_un.d_val = bfd_count_sections (output_bfd) + 1;
+	      dyn.d_un.d_val = bfd_count_sections (info->output_bfd) + 1;
 	      break;
 
 	    case DT_MIPS_GOTSYM:
@@ -12070,7 +12075,7 @@ _bfd_mips_elf_finish_dynamic_sections (bfd *output_bfd,
 
 	    case DT_MIPS_SYMTABNO:
 	      name = ".dynsym";
-	      elemsize = MIPS_ELF_SYM_SIZE (output_bfd);
+	      elemsize = MIPS_ELF_SYM_SIZE (info->output_bfd);
 	      s = bfd_get_linker_section (dynobj, name);
 
 	      if (s != NULL)
@@ -12127,7 +12132,8 @@ _bfd_mips_elf_finish_dynamic_sections (bfd *output_bfd,
 
 	    case DT_MIPS_OPTIONS:
 	      s = (bfd_get_section_by_name
-		   (output_bfd, MIPS_ELF_OPTIONS_SECTION_NAME (output_bfd)));
+		   (info->output_bfd,
+		    MIPS_ELF_OPTIONS_SECTION_NAME (info->output_bfd)));
 	      dyn.d_un.d_ptr = s->vma;
 	      break;
 
@@ -12179,7 +12185,7 @@ _bfd_mips_elf_finish_dynamic_sections (bfd *output_bfd,
 	      swap_out_p = false;
 #ifdef OBJ_MAYBE_ELF_VXWORKS
 	      if (htab->root.target_os == is_vxworks
-		  && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
+		  && elf_vxworks_finish_dynamic_entry (info->output_bfd, &dyn))
 		swap_out_p = true;
 #endif /* OBJ_MAYBE_ELF_VXWORKS */
 	      break;
@@ -12211,27 +12217,28 @@ _bfd_mips_elf_finish_dynamic_sections (bfd *output_bfd,
 	     loader and contains the shared library identifier.
 	     The third is also initialized by the loader and points
 	     to the lazy resolution stub.  */
-	  MIPS_ELF_PUT_WORD (output_bfd,
+	  MIPS_ELF_PUT_WORD (info->output_bfd,
 			     sdyn->output_offset + sdyn->output_section->vma,
 			     sgot->contents);
-	  MIPS_ELF_PUT_WORD (output_bfd, 0,
-			     sgot->contents + MIPS_ELF_GOT_SIZE (output_bfd));
-	  MIPS_ELF_PUT_WORD (output_bfd, 0,
+	  MIPS_ELF_PUT_WORD (info->output_bfd, 0,
+			     sgot->contents + MIPS_ELF_GOT_SIZE (info->output_bfd));
+	  MIPS_ELF_PUT_WORD (info->output_bfd, 0,
 			     sgot->contents
-			     + 2 * MIPS_ELF_GOT_SIZE (output_bfd));
+			     + 2 * MIPS_ELF_GOT_SIZE (info->output_bfd));
 	}
       else
 	{
 	  /* The first entry of the global offset table will be filled at
 	     runtime. The second entry will be used by some runtime loaders.
 	     This isn't the case of IRIX rld.  */
-	  MIPS_ELF_PUT_WORD (output_bfd, (bfd_vma) 0, sgot->contents);
-	  MIPS_ELF_PUT_WORD (output_bfd, MIPS_ELF_GNU_GOT1_MASK (output_bfd),
-			     sgot->contents + MIPS_ELF_GOT_SIZE (output_bfd));
+	  MIPS_ELF_PUT_WORD (info->output_bfd, 0, sgot->contents);
+	  MIPS_ELF_PUT_WORD (info->output_bfd,
+			     MIPS_ELF_GNU_GOT1_MASK (info->output_bfd),
+			     sgot->contents + MIPS_ELF_GOT_SIZE (info->output_bfd));
 	}
 
       elf_section_data (sgot->output_section)->this_hdr.sh_entsize
-	 = MIPS_ELF_GOT_SIZE (output_bfd);
+	 = MIPS_ELF_GOT_SIZE (info->output_bfd);
     }
 
   /* Generate dynamic relocations for the non-primary gots.  */
@@ -12241,18 +12248,19 @@ _bfd_mips_elf_finish_dynamic_sections (bfd *output_bfd,
       bfd_vma addend = 0;
 
       memset (rel, 0, sizeof (rel));
-      rel[0].r_info = ELF_R_INFO (output_bfd, 0, R_MIPS_REL32);
+      rel[0].r_info = ELF_R_INFO (info->output_bfd, 0, R_MIPS_REL32);
 
       for (g = gg->next; g->next != gg; g = g->next)
 	{
 	  bfd_vma got_index = g->next->local_gotno + g->next->global_gotno
 	    + g->next->tls_gotno;
 
-	  MIPS_ELF_PUT_WORD (output_bfd, 0, sgot->contents
-			     + got_index++ * MIPS_ELF_GOT_SIZE (output_bfd));
-	  MIPS_ELF_PUT_WORD (output_bfd, MIPS_ELF_GNU_GOT1_MASK (output_bfd),
+	  MIPS_ELF_PUT_WORD (info->output_bfd, 0, sgot->contents
+			     + got_index++ * MIPS_ELF_GOT_SIZE (info->output_bfd));
+	  MIPS_ELF_PUT_WORD (info->output_bfd,
+			     MIPS_ELF_GNU_GOT1_MASK (info->output_bfd),
 			     sgot->contents
-			     + got_index++ * MIPS_ELF_GOT_SIZE (output_bfd));
+			     + got_index++ * MIPS_ELF_GOT_SIZE (info->output_bfd));
 
 	  if (! bfd_link_pic (info))
 	    continue;
@@ -12264,9 +12272,9 @@ _bfd_mips_elf_finish_dynamic_sections (bfd *output_bfd,
 		continue;
 
 	      rel[0].r_offset = rel[1].r_offset = rel[2].r_offset
-		= got_index * MIPS_ELF_GOT_SIZE (output_bfd);
+		= got_index * MIPS_ELF_GOT_SIZE (info->output_bfd);
 	      if (!(mips_elf_create_dynamic_relocation
-		    (output_bfd, info, rel, NULL,
+		    (info->output_bfd, info, rel, NULL,
 		     bfd_abs_section_ptr,
 		     0, &addend, sgot)))
 		return false;
@@ -12308,7 +12316,7 @@ _bfd_mips_elf_finish_dynamic_sections (bfd *output_bfd,
 		 are trailing null entries.  */
 	      s = mips_elf_rel_dyn_section (info, false);
 	      dyn.d_un.d_val = (s->reloc_count
-				* (ABI_64_P (output_bfd)
+				* (ABI_64_P (info->output_bfd)
 				   ? sizeof (Elf64_Mips_External_Rel)
 				   : sizeof (Elf32_External_Rel)));
 	      /* Adjust the section size too.  Tools like the prelinker
@@ -12333,7 +12341,7 @@ _bfd_mips_elf_finish_dynamic_sections (bfd *output_bfd,
     asection *s;
     Elf32_compact_rel cpt;
 
-    if (SGI_COMPAT (output_bfd))
+    if (SGI_COMPAT (info->output_bfd))
       {
 	/* Write .compact_rel section out.  */
 	s = bfd_get_linker_section (dynobj, ".compact_rel");
@@ -12346,7 +12354,7 @@ _bfd_mips_elf_finish_dynamic_sections (bfd *output_bfd,
 			  + sizeof (Elf32_External_compact_rel));
 	    cpt.reserved0 = 0;
 	    cpt.reserved1 = 0;
-	    bfd_elf32_swap_compact_rel_out (output_bfd, &cpt,
+	    bfd_elf32_swap_compact_rel_out (info->output_bfd, &cpt,
 					    ((Elf32_External_compact_rel *)
 					     s->contents));
 
@@ -12372,11 +12380,11 @@ _bfd_mips_elf_finish_dynamic_sections (bfd *output_bfd,
       {
 	s = mips_elf_rel_dyn_section (info, false);
 	if (s != NULL
-	    && s->size > (bfd_vma)2 * MIPS_ELF_REL_SIZE (output_bfd))
+	    && s->size > (bfd_vma)2 * MIPS_ELF_REL_SIZE (info->output_bfd))
 	  {
-	    reldyn_sorting_bfd = output_bfd;
+	    reldyn_sorting_bfd = info->output_bfd;
 
-	    if (ABI_64_P (output_bfd))
+	    if (ABI_64_P (info->output_bfd))
 	      qsort ((Elf64_External_Rel *) s->contents + 1,
 		     s->reloc_count - 1, sizeof (Elf64_Mips_External_Rel),
 		     sort_dynamic_relocs_64);
@@ -12393,14 +12401,14 @@ _bfd_mips_elf_finish_dynamic_sections (bfd *output_bfd,
       if (htab->root.target_os == is_vxworks)
 	{
 	  if (bfd_link_pic (info))
-	    mips_vxworks_finish_shared_plt (output_bfd, info);
+	    mips_vxworks_finish_shared_plt (info->output_bfd, info);
 	  else
-	    mips_vxworks_finish_exec_plt (output_bfd, info);
+	    mips_vxworks_finish_exec_plt (info->output_bfd, info);
 	}
       else
 	{
 	  BFD_ASSERT (!bfd_link_pic (info));
-	  if (!mips_finish_exec_plt (output_bfd, info))
+	  if (!mips_finish_exec_plt (info->output_bfd, info))
 	    return false;
 	}
     }
diff --git a/bfd/elfxx-mips.h b/bfd/elfxx-mips.h
index e39e0b15478..b624d0df112 100644
--- a/bfd/elfxx-mips.h
+++ b/bfd/elfxx-mips.h
@@ -69,18 +69,18 @@ extern bool _bfd_mips_elf_check_relocs
 extern bool _bfd_mips_elf_adjust_dynamic_symbol
   (struct bfd_link_info *, struct elf_link_hash_entry *) ATTRIBUTE_HIDDEN;
 extern bool _bfd_mips_elf_late_size_sections
-  (bfd *, struct bfd_link_info *) ATTRIBUTE_HIDDEN;
+  (struct bfd_link_info *) ATTRIBUTE_HIDDEN;
 extern int _bfd_mips_elf_relocate_section
-  (bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *,
+  (struct bfd_link_info *, bfd *, asection *, bfd_byte *,
    Elf_Internal_Rela *, Elf_Internal_Sym *, asection **) ATTRIBUTE_HIDDEN;
 extern bool _bfd_mips_elf_finish_dynamic_symbol
-  (bfd *, struct bfd_link_info *, struct elf_link_hash_entry *,
+  (struct bfd_link_info *, struct elf_link_hash_entry *,
    Elf_Internal_Sym *) ATTRIBUTE_HIDDEN;
 extern bool _bfd_mips_vxworks_finish_dynamic_symbol
-  (bfd *, struct bfd_link_info *, struct elf_link_hash_entry *,
+  (struct bfd_link_info *, struct elf_link_hash_entry *,
    Elf_Internal_Sym *) ATTRIBUTE_HIDDEN;
 extern bool _bfd_mips_elf_finish_dynamic_sections
-  (bfd *, struct bfd_link_info *, bfd_byte *) ATTRIBUTE_HIDDEN;
+  (struct bfd_link_info *, bfd_byte *) ATTRIBUTE_HIDDEN;
 extern bool _bfd_mips_elf_sort_relocs_p
   (asection *) ATTRIBUTE_HIDDEN;
 extern void _bfd_mips_final_write_processing
diff --git a/bfd/elfxx-sparc.c b/bfd/elfxx-sparc.c
index 138e639591a..14d8fb9986f 100644
--- a/bfd/elfxx-sparc.c
+++ b/bfd/elfxx-sparc.c
@@ -2372,8 +2372,7 @@ allocate_local_dynrelocs (void **slot, void *inf)
    omitted when creating a shared library.  */
 
 bool
-_bfd_sparc_elf_omit_section_dynsym (bfd *output_bfd,
-				    struct bfd_link_info *info,
+_bfd_sparc_elf_omit_section_dynsym (struct bfd_link_info *info,
 				    asection *p)
 {
   /* We keep the .got section symbol so that explicit relocations
@@ -2382,14 +2381,13 @@ _bfd_sparc_elf_omit_section_dynsym (bfd *output_bfd,
   if (strcmp (p->name, ".got") == 0)
     return false;
 
-  return _bfd_elf_omit_section_dynsym_default (output_bfd, info, p);
+  return _bfd_elf_omit_section_dynsym_default (info, p);
 }
 
 /* Set the sizes of the dynamic sections.  */
 
 bool
-_bfd_sparc_elf_late_size_sections (bfd *output_bfd,
-				   struct bfd_link_info *info)
+_bfd_sparc_elf_late_size_sections (struct bfd_link_info *info)
 {
   struct _bfd_sparc_elf_link_hash_table *htab;
   bfd *dynobj;
@@ -2512,7 +2510,7 @@ _bfd_sparc_elf_late_size_sections (bfd *output_bfd,
   /* Allocate .plt and .got entries, and space for local symbols.  */
   htab_traverse (htab->loc_hash_table, allocate_local_dynrelocs, info);
 
-  if (! ABI_64_P (output_bfd)
+  if (! ABI_64_P (info->output_bfd)
       && htab->elf.target_os != is_vxworks
       && elf_hash_table (info)->dynamic_sections_created)
     {
@@ -2600,11 +2598,10 @@ _bfd_sparc_elf_late_size_sections (bfd *output_bfd,
 #define add_dynamic_entry(TAG, VAL) \
   _bfd_elf_add_dynamic_entry (info, TAG, VAL)
 
-      if (!_bfd_elf_maybe_vxworks_add_dynamic_tags (output_bfd, info,
-						    true))
+      if (!_bfd_elf_maybe_vxworks_add_dynamic_tags (info, true))
 	return false;
 
-      if (ABI_64_P (output_bfd))
+      if (ABI_64_P (info->output_bfd))
 	{
 	  int reg;
 	  struct _bfd_sparc_elf_app_reg * app_regs;
@@ -2645,7 +2642,7 @@ _bfd_sparc_elf_late_size_sections (bfd *output_bfd,
 		entry->isym.st_shndx = app_regs [reg].shndx;
 		entry->isym.st_target_internal = 0;
 		entry->next = NULL;
-		entry->input_bfd = output_bfd;
+		entry->input_bfd = info->output_bfd;
 		entry->input_indx = -1;
 
 		if (eht->dynlocal == NULL)
@@ -2770,8 +2767,7 @@ gdop_relative_offset_ok (struct bfd_link_info *info,
 /* Relocate a SPARC ELF section.  */
 
 int
-_bfd_sparc_elf_relocate_section (bfd *output_bfd,
-				 struct bfd_link_info *info,
+_bfd_sparc_elf_relocate_section (struct bfd_link_info *info,
 				 bfd *input_bfd,
 				 asection *input_section,
 				 bfd_byte *contents,
@@ -2810,7 +2806,7 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 				".tls_vars"));
 
   rel = relocs;
-  if (ABI_64_P (output_bfd))
+  if (ABI_64_P (info->output_bfd))
     num_relocs = NUM_SHDR_ENTRIES (_bfd_elf_single_rel_hdr (input_section));
   else
     num_relocs = input_section->reloc_count;
@@ -2852,7 +2848,8 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections[r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 
 	  if (!bfd_link_relocatable (info)
 	      && ELF_ST_TYPE (sym->st_info) == STT_GNU_IFUNC)
@@ -2972,7 +2969,7 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 		  Elf_Internal_Rela outrel;
 		  bfd_vma offset;
 
-		  offset = _bfd_elf_section_offset (output_bfd, info,
+		  offset = _bfd_elf_section_offset (info->output_bfd, info,
 						    input_section,
 						    rel->r_offset);
 		  if (offset == (bfd_vma) -1
@@ -2999,7 +2996,7 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 		      outrel.r_addend = rel->r_addend;
 		    }
 
-		  sparc_elf_append_rela (output_bfd, sreloc, &outrel);
+		  sparc_elf_append_rela (info->output_bfd, sreloc, &outrel);
 		  continue;
 		}
 
@@ -3057,7 +3054,8 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 
 	      /* {ld,ldx} [%rs1 + %rs2], %rd --> add %rs1, %rs2, %rd */
 	      relocation = 0x80000000 | (insn & 0x3e07c01f);
-	      bfd_put_32 (output_bfd, relocation, contents + rel->r_offset);
+	      bfd_put_32 (info->output_bfd, relocation,
+			  contents + rel->r_offset);
 
 	      /* If the symbol is global but not dynamic, an .rela.* slot has
 		 been allocated for it in the GOT so output R_SPARC_NONE here,
@@ -3077,7 +3075,7 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 		  BFD_ASSERT (s != NULL);
 
 		  memset (&outrel, 0, sizeof outrel);
-		  sparc_elf_append_rela (output_bfd, s, &outrel);
+		  sparc_elf_append_rela (info->output_bfd, s, &outrel);
 		  h->got.offset |= 1;
 		}
 	    }
@@ -3140,7 +3138,7 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 			  && bfd_link_pic (info))
 			relative_reloc = true;
 		      else
-			SPARC_ELF_PUT_WORD (htab, output_bfd, relocation,
+			SPARC_ELF_PUT_WORD (htab, info->output_bfd, relocation,
 					    htab->elf.sgot->contents + off);
 		      h->got.offset |= 1;
 		    }
@@ -3167,7 +3165,7 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 		  if (bfd_link_pic (info))
 		    relative_reloc = true;
 		  else
-		    SPARC_ELF_PUT_WORD (htab, output_bfd, relocation,
+		    SPARC_ELF_PUT_WORD (htab, info->output_bfd, relocation,
 					htab->elf.sgot->contents + off);
 		  local_got_offsets[r_symndx] |= 1;
 		}
@@ -3186,13 +3184,13 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 	      outrel.r_info = SPARC_ELF_R_INFO (htab, NULL,
 						0, R_SPARC_RELATIVE);
 	      outrel.r_addend = relocation;
-	      sparc_elf_append_rela (output_bfd, s, &outrel);
+	      sparc_elf_append_rela (info->output_bfd, s, &outrel);
 	      /* Versions of glibc ld.so at least up to 2.26 wrongly
 		 add the section contents to the value calculated for
 		 a RELATIVE reloc.  Zero the contents to work around
 		 this bug.  */
 	      relocation = 0;
-	      SPARC_ELF_PUT_WORD (htab, output_bfd, relocation,
+	      SPARC_ELF_PUT_WORD (htab, info->output_bfd, relocation,
 				  htab->elf.sgot->contents + off);
 	    }
 
@@ -3218,7 +3216,7 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 	  /* Relocation is to the entry for this symbol in the
 	     procedure linkage table.  */
 
-	  if (! ABI_64_P (output_bfd))
+	  if (! ABI_64_P (info->output_bfd))
 	    {
 	      /* The Solaris native assembler will generate a WPLT30 reloc
 		 for a local symbol if you assemble a call from one
@@ -3334,8 +3332,8 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 	      skip = false;
 
 	      outrel.r_offset =
-		_bfd_elf_section_offset (output_bfd, info, input_section,
-					 rel->r_offset);
+		_bfd_elf_section_offset (info->output_bfd, info,
+					 input_section, rel->r_offset);
 	      if (outrel.r_offset == (bfd_vma) -1)
 		skip = true;
 	      else if (outrel.r_offset == (bfd_vma) -2)
@@ -3401,8 +3399,8 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 		}
 	      else
 		{
-		  if (  (!ABI_64_P (output_bfd) && r_type == R_SPARC_32)
-		      || (ABI_64_P (output_bfd) && r_type == R_SPARC_64))
+		  if (  (!ABI_64_P (info->output_bfd) && r_type == R_SPARC_32)
+		      || (ABI_64_P (info->output_bfd) && r_type == R_SPARC_64))
 		    {
 		      outrel.r_info = SPARC_ELF_R_INFO (htab, NULL,
 							0, R_SPARC_RELATIVE);
@@ -3460,7 +3458,7 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 		    }
 		}
 
-	      sparc_elf_append_rela (output_bfd, sreloc, &outrel);
+	      sparc_elf_append_rela (info->output_bfd, sreloc, &outrel);
 
 	      /* This reloc will be computed at runtime, so there's no
 		 need to do anything now.  */
@@ -3503,9 +3501,10 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 	    {
 	      /* Change add into xor.  */
 	      relocation = tpoff (info, relocation);
-	      bfd_put_32 (output_bfd, (bfd_get_32 (input_bfd,
-						   contents + rel->r_offset)
-				       | 0x80182000), contents + rel->r_offset);
+	      bfd_put_32 (info->output_bfd,
+			  bfd_get_32 (input_bfd,
+				      contents + rel->r_offset) | 0x80182000,
+			  contents + rel->r_offset);
 	      break;
 	    }
 
@@ -3535,7 +3534,7 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 	      if (htab->elf.srelgot == NULL)
 		abort ();
 
-	      SPARC_ELF_PUT_WORD (htab, output_bfd, 0,
+	      SPARC_ELF_PUT_WORD (htab, info->output_bfd, 0,
 				  htab->elf.sgot->contents + off);
 	      outrel.r_offset = (htab->elf.sgot->output_section->vma
 				 + htab->elf.sgot->output_offset + off);
@@ -3550,7 +3549,8 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 	      else
 		outrel.r_addend = 0;
 	      outrel.r_info = SPARC_ELF_R_INFO (htab, NULL, indx, dr_type);
-	      sparc_elf_append_rela (output_bfd, htab->elf.srelgot, &outrel);
+	      sparc_elf_append_rela (info->output_bfd,
+				     htab->elf.srelgot, &outrel);
 
 	      if (r_type == R_SPARC_TLS_GD_HI22
 		  || r_type == R_SPARC_TLS_GD_LO10)
@@ -3558,26 +3558,26 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 		  if (indx == 0)
 		    {
 		      BFD_ASSERT (! unresolved_reloc);
-		      SPARC_ELF_PUT_WORD (htab, output_bfd,
+		      SPARC_ELF_PUT_WORD (htab, info->output_bfd,
 					  relocation - dtpoff_base (info),
 					  (htab->elf.sgot->contents + off
 					   + SPARC_ELF_WORD_BYTES (htab)));
 		    }
 		  else
 		    {
-		      SPARC_ELF_PUT_WORD (htab, output_bfd, 0,
+		      SPARC_ELF_PUT_WORD (htab, info->output_bfd, 0,
 					  (htab->elf.sgot->contents + off
 					   + SPARC_ELF_WORD_BYTES (htab)));
 		      outrel.r_info = SPARC_ELF_R_INFO (htab, NULL, indx,
 							SPARC_ELF_DTPOFF_RELOC (htab));
 		      outrel.r_offset += SPARC_ELF_WORD_BYTES (htab);
-		      sparc_elf_append_rela (output_bfd, htab->elf.srelgot,
+		      sparc_elf_append_rela (info->output_bfd, htab->elf.srelgot,
 					     &outrel);
 		    }
 		}
 	      else if (dr_type == SPARC_ELF_DTPMOD_RELOC (htab))
 		{
-		  SPARC_ELF_PUT_WORD (htab, output_bfd, 0,
+		  SPARC_ELF_PUT_WORD (htab, info->output_bfd, 0,
 				      (htab->elf.sgot->contents + off
 				       + SPARC_ELF_WORD_BYTES (htab)));
 		}
@@ -3596,7 +3596,7 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 	  /* LD -> LE */
 	  if (bfd_link_executable (info))
 	    {
-	      bfd_put_32 (output_bfd, SPARC_NOP, contents + rel->r_offset);
+	      bfd_put_32 (info->output_bfd, SPARC_NOP, contents + rel->r_offset);
 	      continue;
 	    }
 	  off = htab->tls_ldm_got.offset;
@@ -3626,8 +3626,8 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 	    {
 	      Elf_Internal_Rela outrel;
 	      bfd_vma offset
-		= _bfd_elf_section_offset (output_bfd, info, input_section,
-					   rel->r_offset);
+		= _bfd_elf_section_offset (info->output_bfd, info,
+					   input_section, rel->r_offset);
 	      if (offset == (bfd_vma) -1 || offset == (bfd_vma) -2)
 		memset (&outrel, 0, sizeof outrel);
 	      else
@@ -3641,7 +3641,7 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 		}
 
 	      BFD_ASSERT (sreloc != NULL);
-	      sparc_elf_append_rela (output_bfd, sreloc, &outrel);
+	      sparc_elf_append_rela (info->output_bfd, sreloc, &outrel);
 	      continue;
 	    }
 	  relocation = tpoff (info, relocation);
@@ -3652,7 +3652,8 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 	  if (bfd_link_executable (info))
 	    {
 	      /* mov %g0, %o0 */
-	      bfd_put_32 (output_bfd, 0x90100000, contents + rel->r_offset);
+	      bfd_put_32 (info->output_bfd, 0x90100000,
+			  contents + rel->r_offset);
 	      continue;
 	    }
 	  /* Fall through */
@@ -3674,7 +3675,8 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 	      /* GD -> LE */
 	      if (bfd_link_executable (info) && (h == NULL || h->dynindx == -1))
 		{
-		  bfd_put_32 (output_bfd, SPARC_NOP, contents + rel->r_offset);
+		  bfd_put_32 (info->output_bfd, SPARC_NOP,
+			      contents + rel->r_offset);
 		  continue;
 		}
 
@@ -3696,9 +3698,11 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 		     add is 0x80000000 | (rd << 25) | (rs1 << 14) | rs2,
 		     ld is 0xc0000000 | (rd << 25) | (rs1 << 14) | rs2,
 		     ldx is 0xc0580000 | (rd << 25) | (rs1 << 14) | rs2.  */
-		  bfd_put_32 (output_bfd, insn | (ABI_64_P (output_bfd) ? 0xc0580000 : 0xc0000000),
+		  bfd_put_32 (info->output_bfd,
+			      insn | (ABI_64_P (info->output_bfd)
+				      ? 0xc0580000 : 0xc0000000),
 			      contents + rel->r_offset);
-		  bfd_put_32 (output_bfd, 0x9001c008,
+		  bfd_put_32 (info->output_bfd, 0x9001c008,
 			      contents + rel->r_offset + 4);
 		  rel++;
 		  continue;
@@ -3709,9 +3713,9 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 		 __tls_get_addr into place.  So we have to transpose
 		 the delay slot with the add we patch in.  */
 	      insn = bfd_get_32 (input_bfd, contents + rel->r_offset + 4);
-	      bfd_put_32 (output_bfd, insn,
+	      bfd_put_32 (info->output_bfd, insn,
 			  contents + rel->r_offset);
-	      bfd_put_32 (output_bfd, 0x9001c008,
+	      bfd_put_32 (info->output_bfd, 0x9001c008,
 			  contents + rel->r_offset + 4);
 
 	      rel2 = rel;
@@ -3754,15 +3758,17 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 	      if (bfd_link_executable (info) && (h == NULL || h->dynindx == -1))
 		relocation = (insn & ~0x7c000) | 0x1c000;
 	      else
-		relocation = insn | (ABI_64_P (output_bfd) ? 0xc0580000 : 0xc0000000);
-	      bfd_put_32 (output_bfd, relocation, contents + rel->r_offset);
+		relocation = insn | (ABI_64_P (info->output_bfd)
+				     ? 0xc0580000 : 0xc0000000);
+	      bfd_put_32 (info->output_bfd, relocation,
+			  contents + rel->r_offset);
 	    }
 	  continue;
 
 	case R_SPARC_TLS_LDM_ADD:
 	  /* LD -> LE */
 	  if (bfd_link_executable (info))
-	    bfd_put_32 (output_bfd, SPARC_NOP, contents + rel->r_offset);
+	    bfd_put_32 (info->output_bfd, SPARC_NOP, contents + rel->r_offset);
 	  continue;
 
 	case R_SPARC_TLS_LDO_ADD:
@@ -3772,7 +3778,7 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 	      /* Change rs1 into %g7.  */
 	      bfd_vma insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
 	      insn = (insn & ~0x7c000) | 0x1c000;
-	      bfd_put_32 (output_bfd, insn, contents + rel->r_offset);
+	      bfd_put_32 (info->output_bfd, insn, contents + rel->r_offset);
 	    }
 	  continue;
 
@@ -3789,7 +3795,8 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 		relocation = SPARC_NOP;
 	      else
 		relocation = 0x80100000 | (insn & 0x3e00001f);
-	      bfd_put_32 (output_bfd, relocation, contents + rel->r_offset);
+	      bfd_put_32 (info->output_bfd, relocation,
+			  contents + rel->r_offset);
 	    }
 	  continue;
 
@@ -3812,7 +3819,7 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
       if (unresolved_reloc
 	  && !((input_section->flags & SEC_DEBUGGING) != 0
 	       && h->def_dynamic)
-	  && _bfd_elf_section_offset (output_bfd, info, input_section,
+	  && _bfd_elf_section_offset (info->output_bfd, info, input_section,
 				      rel->r_offset) != (bfd_vma) -1)
 	_bfd_error_handler
 	  /* xgettext:c-format */
@@ -3829,7 +3836,7 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 	{
 	    bfd_vma x;
 
-	    if (! ABI_64_P (output_bfd))
+	    if (! ABI_64_P (info->output_bfd))
 	      abort ();
 
 	    relocation += rel->r_addend;
@@ -4011,8 +4018,8 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 		      /* Check whether it fits into simm19.  */
 		      if (((reloc & 0x3c0000) == 0
 			   || (reloc & 0x3c0000) == 0x3c0000)
-			  && (ABI_64_P (output_bfd)
-			      || elf_elfheader (output_bfd)->e_flags & EF_SPARC_32PLUS))
+			  && (ABI_64_P (info->output_bfd)
+			      || elf_elfheader (info->output_bfd)->e_flags & EF_SPARC_32PLUS))
 			x = INSN_BPA | (reloc & 0x7ffff); /* ba,pt %xcc */
 		      else
 			x = INSN_BA | (reloc & 0x3fffff); /* ba */
@@ -4081,7 +4088,7 @@ _bfd_sparc_elf_relocate_section (bfd *output_bfd,
 		    && (((input_section->flags & SEC_DEBUGGING) != 0
 			 && strcmp (bfd_section_name (input_section),
 				    ".stab") == 0)
-			|| _bfd_elf_section_offset (output_bfd, info,
+			|| _bfd_elf_section_offset (info->output_bfd, info,
 						    input_section,
 						    rel->r_offset)
 			     == (bfd_vma)-1))
@@ -4219,8 +4226,7 @@ sparc_vxworks_build_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
    dynamic sections here.  */
 
 bool
-_bfd_sparc_elf_finish_dynamic_symbol (bfd *output_bfd,
-				      struct bfd_link_info *info,
+_bfd_sparc_elf_finish_dynamic_symbol (struct bfd_link_info *info,
 				      struct elf_link_hash_entry *h,
 				      Elf_Internal_Sym *sym)
 {
@@ -4231,7 +4237,7 @@ _bfd_sparc_elf_finish_dynamic_symbol (bfd *output_bfd,
 
   htab = _bfd_sparc_elf_hash_table (info);
   BFD_ASSERT (htab != NULL);
-  bed = get_elf_backend_data (output_bfd);
+  bed = get_elf_backend_data (info->output_bfd);
 
   eh = (struct _bfd_sparc_elf_link_hash_entry *) h;
 
@@ -4276,7 +4282,7 @@ _bfd_sparc_elf_finish_dynamic_symbol (bfd *output_bfd,
 	     The first three entries are reserved.  */
 	  got_offset = (rela_index + 3) * 4;
 
-	  sparc_vxworks_build_plt_entry (output_bfd, info, h->plt.offset,
+	  sparc_vxworks_build_plt_entry (info->output_bfd, info, h->plt.offset,
 					 rela_index, got_offset);
 
 
@@ -4294,7 +4300,7 @@ _bfd_sparc_elf_finish_dynamic_symbol (bfd *output_bfd,
 	  bool ifunc = false;
 
 	  /* Fill in the entry in the procedure linkage table.  */
-	  rela_index = SPARC_ELF_BUILD_PLT_ENTRY (htab, output_bfd, splt,
+	  rela_index = SPARC_ELF_BUILD_PLT_ENTRY (htab, info->output_bfd, splt,
 						  h->plt.offset, splt->size,
 						  &r_offset);
 
@@ -4315,7 +4321,7 @@ _bfd_sparc_elf_finish_dynamic_symbol (bfd *output_bfd,
 
 	  rela.r_offset = r_offset
 	    + (splt->output_section->vma + splt->output_offset);
-	  if (ABI_64_P (output_bfd)
+	  if (ABI_64_P (info->output_bfd)
 	      && h->plt.offset >= (PLT64_LARGE_THRESHOLD * PLT64_ENTRY_SIZE))
 	    {
 	      if (ifunc)
@@ -4361,7 +4367,7 @@ _bfd_sparc_elf_finish_dynamic_symbol (bfd *output_bfd,
 
       loc = srela->contents;
       loc += rela_index * bed->s->sizeof_rela;
-      bed->s->swap_reloca_out (output_bfd, &rela, loc);
+      bed->s->swap_reloca_out (info->output_bfd, &rela, loc);
 
       if (!resolved_to_zero && !h->def_regular)
 	{
@@ -4413,7 +4419,7 @@ _bfd_sparc_elf_finish_dynamic_symbol (bfd *output_bfd,
 
 	  /* We load the GOT entry with the PLT entry.  */
 	  plt = htab->elf.splt ? htab->elf.splt : htab->elf.iplt;
-	  SPARC_ELF_PUT_WORD (htab, output_bfd,
+	  SPARC_ELF_PUT_WORD (htab, info->output_bfd,
 			      (plt->output_section->vma
 			       + plt->output_offset + h->plt.offset),
 			      htab->elf.sgot->contents
@@ -4441,9 +4447,9 @@ _bfd_sparc_elf_finish_dynamic_symbol (bfd *output_bfd,
 	  rela.r_addend = 0;
 	}
 
-      SPARC_ELF_PUT_WORD (htab, output_bfd, 0,
+      SPARC_ELF_PUT_WORD (htab, info->output_bfd, 0,
 			  sgot->contents + (h->got.offset & ~(bfd_vma) 1));
-      sparc_elf_append_rela (output_bfd, srela, &rela);
+      sparc_elf_append_rela (info->output_bfd, srela, &rela);
     }
 
   if (h->needs_copy)
@@ -4463,7 +4469,7 @@ _bfd_sparc_elf_finish_dynamic_symbol (bfd *output_bfd,
 	s = htab->elf.sreldynrelro;
       else
 	s = htab->elf.srelbss;
-      sparc_elf_append_rela (output_bfd, s, &rela);
+      sparc_elf_append_rela (info->output_bfd, s, &rela);
     }
 
   /* Mark some specially defined symbols as absolute.  On VxWorks,
@@ -4481,7 +4487,7 @@ _bfd_sparc_elf_finish_dynamic_symbol (bfd *output_bfd,
 /* Finish up the dynamic sections.  */
 
 static bool
-sparc_finish_dyn (bfd *output_bfd, struct bfd_link_info *info,
+sparc_finish_dyn (struct bfd_link_info *info,
 		  bfd *dynobj, asection *sdyn,
 		  asection *splt ATTRIBUTE_UNUSED)
 {
@@ -4494,10 +4500,10 @@ sparc_finish_dyn (bfd *output_bfd, struct bfd_link_info *info,
 
   htab = _bfd_sparc_elf_hash_table (info);
   BFD_ASSERT (htab != NULL);
-  bed = get_elf_backend_data (output_bfd);
+  bed = get_elf_backend_data (info->output_bfd);
   dynsize = bed->s->sizeof_dyn;
   dynconend = sdyn->contents + sdyn->size;
-  abi_64_p = ABI_64_P (output_bfd);
+  abi_64_p = ABI_64_P (info->output_bfd);
   for (dyncon = sdyn->contents; dyncon < dynconend; dyncon += dynsize)
     {
       Elf_Internal_Dyn dyn;
@@ -4513,25 +4519,25 @@ sparc_finish_dyn (bfd *output_bfd, struct bfd_link_info *info,
 	    {
 	      dyn.d_un.d_val = (htab->elf.sgotplt->output_section->vma
 				+ htab->elf.sgotplt->output_offset);
-	      bed->s->swap_dyn_out (output_bfd, &dyn, dyncon);
+	      bed->s->swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	    }
 	}
 #ifdef OBJ_MAYBE_ELF_VXWORKS
       else if (htab->elf.target_os == is_vxworks
-	       && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
-	bed->s->swap_dyn_out (output_bfd, &dyn, dyncon);
+	       && elf_vxworks_finish_dynamic_entry (info->output_bfd, &dyn))
+	bed->s->swap_dyn_out (info->output_bfd, &dyn, dyncon);
 #endif /* OBJ_MAYBE_ELF_VXWORKS */
       else if (abi_64_p && dyn.d_tag == DT_SPARC_REGISTER)
 	{
 	  if (stt_regidx == -1)
 	    {
 	      stt_regidx =
-		_bfd_elf_link_lookup_local_dynindx (info, output_bfd, -1);
+		_bfd_elf_link_lookup_local_dynindx (info, info->output_bfd, -1);
 	      if (stt_regidx == -1)
 		return false;
 	    }
 	  dyn.d_un.d_val = stt_regidx++;
-	  bed->s->swap_dyn_out (output_bfd, &dyn, dyncon);
+	  bed->s->swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	}
       else
 	{
@@ -4564,7 +4570,7 @@ sparc_finish_dyn (bfd *output_bfd, struct bfd_link_info *info,
 	      else
 		dyn.d_un.d_val = s->size;
 	    }
-	  bed->s->swap_dyn_out (output_bfd, &dyn, dyncon);
+	  bed->s->swap_dyn_out (info->output_bfd, &dyn, dyncon);
 	}
     }
   return true;
@@ -4676,8 +4682,7 @@ finish_local_dynamic_symbol (void **slot, void *inf)
   struct bfd_link_info *info
     = (struct bfd_link_info *) inf;
 
-  return _bfd_sparc_elf_finish_dynamic_symbol (info->output_bfd, info,
-					       h, NULL);
+  return _bfd_sparc_elf_finish_dynamic_symbol (info, h, NULL);
 }
 
 /* Finish up undefined weak symbol handling in PIE.  Fill its PLT entry
@@ -4695,13 +4700,11 @@ pie_finish_undefweak_symbol (struct bfd_hash_entry *bh,
       || h->dynindx != -1)
     return true;
 
-  return _bfd_sparc_elf_finish_dynamic_symbol (info->output_bfd, info,
-					       h, NULL);
+  return _bfd_sparc_elf_finish_dynamic_symbol (info, h, NULL);
 }
 
 bool
-_bfd_sparc_elf_finish_dynamic_sections (bfd *output_bfd,
-					struct bfd_link_info *info,
+_bfd_sparc_elf_finish_dynamic_sections (struct bfd_link_info *info,
 					bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   bfd *dynobj;
@@ -4716,7 +4719,7 @@ _bfd_sparc_elf_finish_dynamic_sections (bfd *output_bfd,
      entries at the end of the dynlocal list, so they came at the end
      of the local symbols in the symtab.  Except that they aren't
      STB_LOCAL, so we need to back up symtab->sh_info.  */
-  if (ABI_64_P (output_bfd)
+  if (ABI_64_P (info->output_bfd)
       && elf_hash_table (info)->dynlocal)
     {
       asection *dynsymsec = bfd_get_linker_section (dynobj, ".dynsym");
@@ -4739,7 +4742,7 @@ _bfd_sparc_elf_finish_dynamic_sections (bfd *output_bfd,
       splt = htab->elf.splt;
       BFD_ASSERT (splt != NULL && sdyn != NULL);
 
-      if (!sparc_finish_dyn (output_bfd, info, dynobj, sdyn, splt))
+      if (!sparc_finish_dyn (info, dynobj, sdyn, splt))
 	return false;
 
       /* Initialize the contents of the .plt section.  */
@@ -4748,15 +4751,15 @@ _bfd_sparc_elf_finish_dynamic_sections (bfd *output_bfd,
 	  if (htab->elf.target_os == is_vxworks)
 	    {
 	      if (bfd_link_pic (info))
-		sparc_vxworks_finish_shared_plt (output_bfd, info);
+		sparc_vxworks_finish_shared_plt (info->output_bfd, info);
 	      else
-		sparc_vxworks_finish_exec_plt (output_bfd, info);
+		sparc_vxworks_finish_exec_plt (info->output_bfd, info);
 	    }
 	  else
 	    {
 	      memset (splt->contents, 0, htab->plt_header_size);
-	      if (!ABI_64_P (output_bfd))
-		bfd_put_32 (output_bfd, (bfd_vma) SPARC_NOP,
+	      if (!ABI_64_P (info->output_bfd))
+		bfd_put_32 (info->output_bfd, SPARC_NOP,
 			    splt->contents + splt->size - 4);
 	    }
 	}
@@ -4764,7 +4767,7 @@ _bfd_sparc_elf_finish_dynamic_sections (bfd *output_bfd,
       if (elf_section_data (splt->output_section) != NULL)
 	elf_section_data (splt->output_section)->this_hdr.sh_entsize
 	  = ((htab->elf.target_os == is_vxworks
-	      || !ABI_64_P (output_bfd))
+	      || !ABI_64_P (info->output_bfd))
 	     ? 0 : htab->plt_entry_size);
     }
 
@@ -4776,7 +4779,8 @@ _bfd_sparc_elf_finish_dynamic_sections (bfd *output_bfd,
 		     sdyn->output_section->vma + sdyn->output_offset :
 		     0);
 
-      SPARC_ELF_PUT_WORD (htab, output_bfd, val, htab->elf.sgot->contents);
+      SPARC_ELF_PUT_WORD (htab, info->output_bfd, val,
+			  htab->elf.sgot->contents);
     }
 
   if (htab->elf.sgot)
diff --git a/bfd/elfxx-sparc.h b/bfd/elfxx-sparc.h
index 75d24a6647f..61f735e7e4a 100644
--- a/bfd/elfxx-sparc.h
+++ b/bfd/elfxx-sparc.h
@@ -112,22 +112,22 @@ extern asection *_bfd_sparc_elf_gc_mark_hook
 extern bool _bfd_sparc_elf_adjust_dynamic_symbol
   (struct bfd_link_info *, struct elf_link_hash_entry *) ATTRIBUTE_HIDDEN;
 extern bool _bfd_sparc_elf_omit_section_dynsym
-  (bfd *, struct bfd_link_info *, asection *) ATTRIBUTE_HIDDEN;
+  (struct bfd_link_info *, asection *) ATTRIBUTE_HIDDEN;
 extern bool _bfd_sparc_elf_late_size_sections
-  (bfd *, struct bfd_link_info *) ATTRIBUTE_HIDDEN;
+  (struct bfd_link_info *) ATTRIBUTE_HIDDEN;
 extern bool _bfd_sparc_elf_new_section_hook
   (bfd *, asection *) ATTRIBUTE_HIDDEN;
 extern bool _bfd_sparc_elf_relax_section
   (bfd *, struct bfd_section *, struct bfd_link_info *, bool *)
   ATTRIBUTE_HIDDEN;
 extern int _bfd_sparc_elf_relocate_section
-  (bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *,
+  (struct bfd_link_info *, bfd *, asection *, bfd_byte *,
    Elf_Internal_Rela *, Elf_Internal_Sym *, asection **) ATTRIBUTE_HIDDEN;
 extern bool _bfd_sparc_elf_finish_dynamic_symbol
-  (bfd *, struct bfd_link_info *, struct elf_link_hash_entry *,
+  (struct bfd_link_info *, struct elf_link_hash_entry *,
    Elf_Internal_Sym *sym) ATTRIBUTE_HIDDEN;
 extern bool _bfd_sparc_elf_finish_dynamic_sections
-  (bfd *, struct bfd_link_info *, bfd_byte *) ATTRIBUTE_HIDDEN;
+  (struct bfd_link_info *, bfd_byte *) ATTRIBUTE_HIDDEN;
 extern bool _bfd_sparc_elf_fixup_symbol
   (struct bfd_link_info *, struct elf_link_hash_entry *) ATTRIBUTE_HIDDEN;
 extern bool _bfd_sparc_elf_object_p
diff --git a/bfd/elfxx-target.h b/bfd/elfxx-target.h
index 124be5ed0c4..b6dfc108f27 100644
--- a/bfd/elfxx-target.h
+++ b/bfd/elfxx-target.h
@@ -495,7 +495,7 @@
 #define elf_backend_strip_zero_sized_dynamic_sections 0
 #endif
 #ifndef elf_backend_init_index_section
-#define elf_backend_init_index_section _bfd_void_bfd_link
+#define elf_backend_init_index_section _bfd_elf_init_0_index_sections
 #endif
 #ifndef elf_backend_relocate_section
 #define elf_backend_relocate_section	0
diff --git a/bfd/elfxx-tilegx.c b/bfd/elfxx-tilegx.c
index a13791336ad..f0af9f2f2f5 100644
--- a/bfd/elfxx-tilegx.c
+++ b/bfd/elfxx-tilegx.c
@@ -2412,8 +2412,7 @@ allocate_dynrelocs (struct elf_link_hash_entry *h, void *inf)
    omitted when creating a shared library.  */
 
 bool
-tilegx_elf_omit_section_dynsym (bfd *output_bfd,
-				struct bfd_link_info *info,
+tilegx_elf_omit_section_dynsym (struct bfd_link_info *info,
 				asection *p)
 {
   /* We keep the .got section symbol so that explicit relocations
@@ -2422,12 +2421,11 @@ tilegx_elf_omit_section_dynsym (bfd *output_bfd,
   if (strcmp (p->name, ".got") == 0)
     return false;
 
-  return _bfd_elf_omit_section_dynsym_default (output_bfd, info, p);
+  return _bfd_elf_omit_section_dynsym_default (info, p);
 }
 
 bool
-tilegx_elf_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
-			       struct bfd_link_info *info)
+tilegx_elf_late_size_sections (struct bfd_link_info *info)
 {
   struct tilegx_elf_link_hash_table *htab;
   bfd *dynobj;
@@ -2555,7 +2553,7 @@ tilegx_elf_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
 	      || htab->elf.splt->size == 0)
 	  && (htab->elf.sgot == NULL
 	      || (htab->elf.sgot->size
-		  == get_elf_backend_data (output_bfd)->got_header_size)))
+		  == get_elf_backend_data (info->output_bfd)->got_header_size)))
 	htab->elf.sgotplt->size = 0;
     }
 
@@ -2618,7 +2616,7 @@ tilegx_elf_late_size_sections (bfd *output_bfd ATTRIBUTE_UNUSED,
       s->alloced = 1;
     }
 
-  return _bfd_elf_add_dynamic_tags (output_bfd, info, true);
+  return _bfd_elf_add_dynamic_tags (info, true);
 }
 
 /* Return the base VMA address which should be subtracted from real addresses
@@ -2796,7 +2794,7 @@ static const bfd_byte *insn_addx_Y0Y1 = insn_tls_ie_addx_Y0Y1;
    accordingly.  */
 
 int
-tilegx_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
+tilegx_elf_relocate_section (struct bfd_link_info *info,
 			     bfd *input_bfd, asection *input_section,
 			     bfd_byte *contents, Elf_Internal_Rela *relocs,
 			     Elf_Internal_Sym *local_syms,
@@ -2866,7 +2864,8 @@ tilegx_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	{
 	  sym = local_syms + r_symndx;
 	  sec = local_sections[r_symndx];
-	  relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
+	  relocation = _bfd_elf_rela_local_sym (info->output_bfd,
+						sym, &sec, rel);
 	}
       else
 	{
@@ -2942,7 +2941,7 @@ tilegx_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	      else if (is_tls_iele)
 		{
 		  /* GD -> IE */
-		  if (ABI_64_P (output_bfd))
+		  if (ABI_64_P (info->output_bfd))
 		    tilegx_replace_insn (contents + rel->r_offset,
 					 insn_mask_X1, insn_tls_ie_ld_X1);
 		  else
@@ -3003,7 +3002,7 @@ tilegx_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		  /* 1. copy dest operand into the second source operand.
 		     2. change the opcode to "add".  */
 		  src_begin = is_pipe0 ? 12 : 43;
-		  if (ABI_64_P (output_bfd))
+		  if (ABI_64_P (info->output_bfd))
 		    insn = is_X0X1 ? insn_add_X0X1 : insn_add_Y0Y1;
 		  else
 		    insn = is_X0X1 ? insn_addx_X0X1 : insn_addx_Y0Y1;
@@ -3035,7 +3034,7 @@ tilegx_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	    {
 	      const bfd_byte *mask = NULL;
 	      const bfd_byte *add_insn = NULL;
-	      bool is_64bit = ABI_64_P (output_bfd);
+	      bool is_64bit = ABI_64_P (info->output_bfd);
 
 	      switch (r_type)
 		{
@@ -3083,7 +3082,7 @@ tilegx_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	  else
 	    {
 	      /* IE -> IE */
-	      if (ABI_64_P (output_bfd))
+	      if (ABI_64_P (info->output_bfd))
 		tilegx_replace_insn (contents + rel->r_offset,
 				     insn_mask_X1_no_dest_no_srca,
 				     insn_tls_ie_ld_X1);
@@ -3144,7 +3143,7 @@ tilegx_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		    off &= ~1;
 		  else
 		    {
-		      TILEGX_ELF_PUT_WORD (htab, output_bfd, relocation,
+		      TILEGX_ELF_PUT_WORD (htab, info->output_bfd, relocation,
 					   htab->elf.sgot->contents + off);
 		      h->got.offset |= 1;
 		    }
@@ -3183,10 +3182,10 @@ tilegx_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 			TILEGX_ELF_R_INFO (htab, NULL, 0, R_TILEGX_RELATIVE);
 		      outrel.r_addend = relocation;
 		      relocation = 0;
-		      tilegx_elf_append_rela (output_bfd, s, &outrel);
+		      tilegx_elf_append_rela (info->output_bfd, s, &outrel);
 		    }
 
-		  TILEGX_ELF_PUT_WORD (htab, output_bfd, relocation,
+		  TILEGX_ELF_PUT_WORD (htab, info->output_bfd, relocation,
 				       htab->elf.sgot->contents + off);
 		  local_got_offsets[r_symndx] |= 1;
 		}
@@ -3324,8 +3323,8 @@ tilegx_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	      skip = false;
 
 	      outrel.r_offset =
-		_bfd_elf_section_offset (output_bfd, info, input_section,
-					 rel->r_offset);
+		_bfd_elf_section_offset (info->output_bfd, info,
+					 input_section, rel->r_offset);
 	      if (outrel.r_offset == (bfd_vma) -1)
 		skip = true;
 	      else if (outrel.r_offset == (bfd_vma) -2)
@@ -3424,7 +3423,7 @@ tilegx_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		    }
 		}
 
-	      tilegx_elf_append_rela (output_bfd, sreloc, &outrel);
+	      tilegx_elf_append_rela (info->output_bfd, sreloc, &outrel);
 
 	      /* This reloc will be computed at runtime, so there's no
 		 need to do anything now.  */
@@ -3447,8 +3446,8 @@ tilegx_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 	      BFD_ASSERT (sreloc != NULL);
 	      skip = false;
 	      outrel.r_offset =
-		_bfd_elf_section_offset (output_bfd, info, input_section,
-					 rel->r_offset);
+		_bfd_elf_section_offset (info->output_bfd, info,
+					 input_section, rel->r_offset);
 	      if (outrel.r_offset == (bfd_vma) -1)
 		skip = true;
 	      else if (outrel.r_offset == (bfd_vma) -2)
@@ -3464,7 +3463,7 @@ tilegx_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 				    + rel->r_addend;
 		}
 
-	      tilegx_elf_append_rela (output_bfd, sreloc, &outrel);
+	      tilegx_elf_append_rela (info->output_bfd, sreloc, &outrel);
 	      continue;
 	    }
 	  relocation = tpoff (info, relocation);
@@ -3571,7 +3570,7 @@ tilegx_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		  case R_TILEGX_IMM16_X0_HW1_LAST_TLS_IE:
 		  case R_TILEGX_IMM16_X1_HW1_LAST_TLS_IE:
 		    if (need_relocs) {
-		      TILEGX_ELF_PUT_WORD (htab, output_bfd, 0,
+		      TILEGX_ELF_PUT_WORD (htab, info->output_bfd, 0,
 					   htab->elf.sgot->contents + off);
 		      outrel.r_offset = (htab->elf.sgot->output_section->vma
 				       + htab->elf.sgot->output_offset + off);
@@ -3580,9 +3579,10 @@ tilegx_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 			outrel.r_addend = relocation - dtpoff_base (info);
 		      outrel.r_info = TILEGX_ELF_R_INFO (htab, NULL, indx,
 							 TILEGX_ELF_TPOFF_RELOC (htab));
-		      tilegx_elf_append_rela (output_bfd, htab->elf.srelgot, &outrel);
+		      tilegx_elf_append_rela (info->output_bfd,
+					      htab->elf.srelgot, &outrel);
 		    } else {
-		      TILEGX_ELF_PUT_WORD (htab, output_bfd,
+		      TILEGX_ELF_PUT_WORD (htab, info->output_bfd,
 					   tpoff (info, relocation),
 					   htab->elf.sgot->contents + off);
 		    }
@@ -3600,26 +3600,28 @@ tilegx_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 		      outrel.r_addend = 0;
 		      outrel.r_info = TILEGX_ELF_R_INFO (htab, NULL, indx,
 							 TILEGX_ELF_DTPMOD_RELOC (htab));
-		      TILEGX_ELF_PUT_WORD (htab, output_bfd, 0,
+		      TILEGX_ELF_PUT_WORD (htab, info->output_bfd, 0,
 					   htab->elf.sgot->contents + off);
-		      tilegx_elf_append_rela (output_bfd, htab->elf.srelgot, &outrel);
+		      tilegx_elf_append_rela (info->output_bfd,
+					      htab->elf.srelgot, &outrel);
 		      if (indx == 0)
 			{
 			  BFD_ASSERT (! unresolved_reloc);
-			  TILEGX_ELF_PUT_WORD (htab, output_bfd,
+			  TILEGX_ELF_PUT_WORD (htab, info->output_bfd,
 					       relocation - dtpoff_base (info),
 					       (htab->elf.sgot->contents + off +
 						TILEGX_ELF_WORD_BYTES (htab)));
 			}
 		      else
 			{
-			  TILEGX_ELF_PUT_WORD (htab, output_bfd, 0,
+			  TILEGX_ELF_PUT_WORD (htab, info->output_bfd, 0,
 					       (htab->elf.sgot->contents + off +
 						TILEGX_ELF_WORD_BYTES (htab)));
 			  outrel.r_info = TILEGX_ELF_R_INFO (htab, NULL, indx,
 							     TILEGX_ELF_DTPOFF_RELOC (htab));
 			  outrel.r_offset += TILEGX_ELF_WORD_BYTES (htab);
-			  tilegx_elf_append_rela (output_bfd, htab->elf.srelgot, &outrel);
+			  tilegx_elf_append_rela (info->output_bfd,
+						  htab->elf.srelgot, &outrel);
 			}
 		    }
 
@@ -3629,9 +3631,9 @@ tilegx_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
 			 static link or an executable link with the
 			 symbol binding locally.  Mark it as belonging
 			 to module 1, the executable.  */
-		      TILEGX_ELF_PUT_WORD (htab, output_bfd, 1,
+		      TILEGX_ELF_PUT_WORD (htab, info->output_bfd, 1,
 					   htab->elf.sgot->contents + off );
-		      TILEGX_ELF_PUT_WORD (htab, output_bfd,
+		      TILEGX_ELF_PUT_WORD (htab, info->output_bfd,
 					   relocation - dtpoff_base (info),
 					   htab->elf.sgot->contents + off +
 					   TILEGX_ELF_WORD_BYTES (htab));
@@ -3658,7 +3660,7 @@ tilegx_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
       if (unresolved_reloc
 	  && !((input_section->flags & SEC_DEBUGGING) != 0
 	       && h->def_dynamic)
-	  && _bfd_elf_section_offset (output_bfd, info, input_section,
+	  && _bfd_elf_section_offset (info->output_bfd, info, input_section,
 				      rel->r_offset) != (bfd_vma) -1)
 	_bfd_error_handler
 	  /* xgettext:c-format */
@@ -3768,8 +3770,7 @@ tilegx_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
    dynamic sections here.  */
 
 bool
-tilegx_elf_finish_dynamic_symbol (bfd *output_bfd,
-				  struct bfd_link_info *info,
+tilegx_elf_finish_dynamic_symbol (struct bfd_link_info *info,
 				  struct elf_link_hash_entry *h,
 				  Elf_Internal_Sym *sym)
 {
@@ -3786,7 +3787,7 @@ tilegx_elf_finish_dynamic_symbol (bfd *output_bfd,
       Elf_Internal_Rela rela;
       bfd_byte *loc;
       bfd_vma r_offset;
-      elf_backend_data *bed = get_elf_backend_data (output_bfd);
+      elf_backend_data *bed = get_elf_backend_data (info->output_bfd);
 
 
       int rela_index;
@@ -3803,12 +3804,12 @@ tilegx_elf_finish_dynamic_symbol (bfd *output_bfd,
        abort ();
 
       /* Fill in the entry in the procedure linkage table.  */
-      rela_index = tilegx_plt_entry_build (output_bfd, htab, splt, sgotplt,
+      rela_index = tilegx_plt_entry_build (info->output_bfd, htab, splt, sgotplt,
 					   h->plt.offset, &r_offset);
 
       /* Fill in the entry in the global offset table, which initially points
 	 to the beginning of the plt.  */
-      TILEGX_ELF_PUT_WORD (htab, output_bfd,
+      TILEGX_ELF_PUT_WORD (htab, info->output_bfd,
 			   splt->output_section->vma + splt->output_offset,
 			   sgotplt->contents + r_offset);
 
@@ -3820,7 +3821,7 @@ tilegx_elf_finish_dynamic_symbol (bfd *output_bfd,
       rela.r_info = TILEGX_ELF_R_INFO (htab, NULL, h->dynindx, R_TILEGX_JMP_SLOT);
 
       loc = srela->contents + rela_index * TILEGX_ELF_RELA_BYTES (htab);
-      bed->s->swap_reloca_out (output_bfd, &rela, loc);
+      bed->s->swap_reloca_out (info->output_bfd, &rela, loc);
 
       if (!h->def_regular)
 	{
@@ -3875,9 +3876,9 @@ tilegx_elf_finish_dynamic_symbol (bfd *output_bfd,
 	  rela.r_addend = 0;
 	}
 
-      TILEGX_ELF_PUT_WORD (htab, output_bfd, 0,
+      TILEGX_ELF_PUT_WORD (htab, info->output_bfd, 0,
 			   sgot->contents + (h->got.offset & ~(bfd_vma) 1));
-      tilegx_elf_append_rela (output_bfd, srela, &rela);
+      tilegx_elf_append_rela (info->output_bfd, srela, &rela);
     }
 
   if (h->needs_copy)
@@ -3899,7 +3900,7 @@ tilegx_elf_finish_dynamic_symbol (bfd *output_bfd,
 		       + h->root.u.def.section->output_offset);
       rela.r_info = TILEGX_ELF_R_INFO (htab, NULL, h->dynindx, R_TILEGX_COPY);
       rela.r_addend = 0;
-      tilegx_elf_append_rela (output_bfd, s, &rela);
+      tilegx_elf_append_rela (info->output_bfd, s, &rela);
     }
 
   /* Mark some specially defined symbols as absolute. */
@@ -3913,7 +3914,7 @@ tilegx_elf_finish_dynamic_symbol (bfd *output_bfd,
 /* Finish up the dynamic sections.  */
 
 static bool
-tilegx_finish_dyn (bfd *output_bfd, struct bfd_link_info *info,
+tilegx_finish_dyn (struct bfd_link_info *info,
 		   bfd *dynobj, asection *sdyn,
 		   asection *splt ATTRIBUTE_UNUSED)
 {
@@ -3924,7 +3925,7 @@ tilegx_finish_dyn (bfd *output_bfd, struct bfd_link_info *info,
 
   htab = tilegx_elf_hash_table (info);
   BFD_ASSERT (htab != NULL);
-  bed = get_elf_backend_data (output_bfd);
+  bed = get_elf_backend_data (info->output_bfd);
   dynsize = bed->s->sizeof_dyn;
   dynconend = sdyn->contents + sdyn->size;
 
@@ -3953,14 +3954,13 @@ tilegx_finish_dyn (bfd *output_bfd, struct bfd_link_info *info,
 	  continue;
 	}
 
-      bed->s->swap_dyn_out (output_bfd, &dyn, dyncon);
+      bed->s->swap_dyn_out (info->output_bfd, &dyn, dyncon);
     }
   return true;
 }
 
 bool
-tilegx_elf_finish_dynamic_sections (bfd *output_bfd,
-				    struct bfd_link_info *info,
+tilegx_elf_finish_dynamic_sections (struct bfd_link_info *info,
 				    bfd_byte *buf ATTRIBUTE_UNUSED)
 {
   bfd *dynobj;
@@ -3982,7 +3982,7 @@ tilegx_elf_finish_dynamic_sections (bfd *output_bfd,
       splt = htab->elf.splt;
       BFD_ASSERT (splt != NULL && sdyn != NULL);
 
-      ret = tilegx_finish_dyn (output_bfd, info, dynobj, sdyn, splt);
+      ret = tilegx_finish_dyn (info, dynobj, sdyn, splt);
 
       if (!ret)
 	return ret;
@@ -3991,13 +3991,13 @@ tilegx_elf_finish_dynamic_sections (bfd *output_bfd,
       if (splt->size > 0)
 	{
 	  memcpy (splt->contents,
-		  ABI_64_P (output_bfd) ?
+		  ABI_64_P (info->output_bfd) ?
 		    tilegx64_plt0_entry : tilegx32_plt0_entry,
 		  PLT_HEADER_SIZE);
 
 	  memcpy (splt->contents + splt->size
 		  - PLT_ENTRY_SIZE + PLT_HEADER_SIZE,
-		  ABI_64_P (output_bfd) ?
+		  ABI_64_P (info->output_bfd) ?
 		    tilegx64_plt_tail_entry : tilegx32_plt_tail_entry,
 		  PLT_TAIL_SIZE);
 	  /* Add padding so that the plt section is a multiple of its
@@ -4023,9 +4023,9 @@ tilegx_elf_finish_dynamic_sections (bfd *output_bfd,
 	{
 	  /* Write the first two entries in .got.plt, needed for the dynamic
 	     linker.  */
-	  TILEGX_ELF_PUT_WORD (htab, output_bfd, (bfd_vma) -1,
+	  TILEGX_ELF_PUT_WORD (htab, info->output_bfd, -1,
 			       htab->elf.sgotplt->contents);
-	  TILEGX_ELF_PUT_WORD (htab, output_bfd, (bfd_vma) 0,
+	  TILEGX_ELF_PUT_WORD (htab, info->output_bfd, 0,
 			       htab->elf.sgotplt->contents
 			       + GOT_ENTRY_SIZE (htab));
 
@@ -4043,7 +4043,7 @@ tilegx_elf_finish_dynamic_sections (bfd *output_bfd,
 	  bfd_vma val = (sdyn ?
 			 sdyn->output_section->vma + sdyn->output_offset :
 			 0);
-	  TILEGX_ELF_PUT_WORD (htab, output_bfd, val,
+	  TILEGX_ELF_PUT_WORD (htab, info->output_bfd, val,
 			       htab->elf.sgot->contents);
 
 	  elf_section_data (htab->elf.sgot->output_section)->this_hdr.sh_entsize =
diff --git a/bfd/elfxx-tilegx.h b/bfd/elfxx-tilegx.h
index c0e1eb5510b..60d32153cf0 100644
--- a/bfd/elfxx-tilegx.h
+++ b/bfd/elfxx-tilegx.h
@@ -55,15 +55,14 @@ tilegx_elf_adjust_dynamic_symbol (struct bfd_link_info *,
   ATTRIBUTE_HIDDEN;
 
 extern bool
-tilegx_elf_omit_section_dynsym (bfd *,
-				struct bfd_link_info *,
+tilegx_elf_omit_section_dynsym (struct bfd_link_info *,
 				asection *) ATTRIBUTE_HIDDEN;
 
 extern bool
-tilegx_elf_late_size_sections (bfd *, struct bfd_link_info *) ATTRIBUTE_HIDDEN;
+tilegx_elf_late_size_sections (struct bfd_link_info *) ATTRIBUTE_HIDDEN;
 
 extern int
-tilegx_elf_relocate_section (bfd *, struct bfd_link_info *,
+tilegx_elf_relocate_section (struct bfd_link_info *,
 			     bfd *, asection *,
 			     bfd_byte *, Elf_Internal_Rela *,
 			     Elf_Internal_Sym *,
@@ -89,13 +88,12 @@ tilegx_additional_program_headers (bfd *, struct bfd_link_info *)
   ATTRIBUTE_HIDDEN;
 
 extern bool
-tilegx_elf_finish_dynamic_symbol (bfd *,
-				  struct bfd_link_info *,
+tilegx_elf_finish_dynamic_symbol (struct bfd_link_info *,
 				  struct elf_link_hash_entry *,
 				  Elf_Internal_Sym *) ATTRIBUTE_HIDDEN;
 
 extern bool
-tilegx_elf_finish_dynamic_sections (bfd *, struct bfd_link_info *, bfd_byte *)
+tilegx_elf_finish_dynamic_sections (struct bfd_link_info *, bfd_byte *)
   ATTRIBUTE_HIDDEN;
 
 extern bool
diff --git a/bfd/elfxx-x86.c b/bfd/elfxx-x86.c
index e54b23b36f5..0f79ef58f02 100644
--- a/bfd/elfxx-x86.c
+++ b/bfd/elfxx-x86.c
@@ -1822,8 +1822,7 @@ enum dynobj_sframe_plt_type
    of type PLT_SEC_TYPE.  */
 
 static bool
-_bfd_x86_elf_create_sframe_plt (bfd *output_bfd,
-				struct bfd_link_info *info,
+_bfd_x86_elf_create_sframe_plt (struct bfd_link_info *info,
 				unsigned int plt_sec_type)
 {
   struct elf_x86_link_hash_table *htab;
@@ -1844,7 +1843,7 @@ _bfd_x86_elf_create_sframe_plt (bfd *output_bfd,
   unsigned int num_pltn_entries = 0;
   const sframe_frame_row_entry * const *pltn_fres;
 
-  bed = get_elf_backend_data (output_bfd);
+  bed = get_elf_backend_data (info->output_bfd);
   htab = elf_x86_hash_table (info, bed->target_id);
   /* Whether SFrame stack trace info for plt0 is to be generated.  */
   switch (plt_sec_type)
@@ -1972,8 +1971,7 @@ _bfd_x86_elf_create_sframe_plt (bfd *output_bfd,
    PLT_SEC_TYPE.  */
 
 static bool
-_bfd_x86_elf_write_sframe_plt (bfd *output_bfd,
-			       struct bfd_link_info *info,
+_bfd_x86_elf_write_sframe_plt (struct bfd_link_info *info,
 			       unsigned int plt_sec_type)
 {
   struct elf_x86_link_hash_table *htab;
@@ -1985,7 +1983,7 @@ _bfd_x86_elf_write_sframe_plt (bfd *output_bfd,
 
   int err = 0;
 
-  bed = get_elf_backend_data (output_bfd);
+  bed = get_elf_backend_data (info->output_bfd);
   htab = elf_x86_hash_table (info, bed->target_id);
   dynobj = htab->elf.dynobj;
 
@@ -2275,15 +2273,14 @@ _bfd_elf_x86_valid_reloc_p (asection *input_section,
 /* Set the sizes of the dynamic sections.  */
 
 bool
-_bfd_x86_elf_late_size_sections (bfd *output_bfd,
-				    struct bfd_link_info *info)
+_bfd_x86_elf_late_size_sections (struct bfd_link_info *info)
 {
   struct elf_x86_link_hash_table *htab;
   bfd *dynobj;
   asection *s;
   bool relocs;
   bfd *ibfd;
-  elf_backend_data *bed = get_elf_backend_data (output_bfd);
+  elf_backend_data *bed = get_elf_backend_data (info->output_bfd);
 
   htab = elf_x86_hash_table (info, bed->target_id);
   if (htab == NULL)
@@ -2482,7 +2479,7 @@ _bfd_x86_elf_late_size_sections (bfd *output_bfd,
 	  && (htab->elf.igotplt == NULL
 	      || htab->elf.igotplt->size == 0)
 	  && (!htab->elf.dynamic_sections_created
-	      || (eh_frame = bfd_get_section_by_name (output_bfd,
+	      || (eh_frame = bfd_get_section_by_name (info->output_bfd,
 						      ".eh_frame")) == NULL
 	      || eh_frame->rawsize == 0))
 	{
@@ -2539,7 +2536,7 @@ _bfd_x86_elf_late_size_sections (bfd *output_bfd,
 	  && htab->elf.splt->size != 0
 	  && !bfd_is_abs_section (htab->elf.splt->output_section))
 	{
-	  _bfd_x86_elf_create_sframe_plt (output_bfd, info, SFRAME_PLT);
+	  _bfd_x86_elf_create_sframe_plt (info, SFRAME_PLT);
 	  /* FIXME - Dirty Hack.  Set the size to something non-zero for now,
 	     so that the section does not get stripped out below.  The precise
 	     size of this section is known only when the contents are
@@ -2552,7 +2549,7 @@ _bfd_x86_elf_late_size_sections (bfd *output_bfd,
 	  && htab->plt_got->size != 0
 	  && !bfd_is_abs_section (htab->plt_got->output_section))
 	{
-	  _bfd_x86_elf_create_sframe_plt (output_bfd, info, SFRAME_PLT_GOT);
+	  _bfd_x86_elf_create_sframe_plt (info, SFRAME_PLT_GOT);
 	  /* FIXME - Dirty Hack.  Set the size to something non-zero for now,
 	     so that the section does not get stripped out below.  The precise
 	     size of this section is known only when the contents are
@@ -2566,7 +2563,7 @@ _bfd_x86_elf_late_size_sections (bfd *output_bfd,
 	  && !bfd_is_abs_section (htab->plt_second->output_section))
 	{
 	  /* SFrame stack trace info for the second PLT.  */
-	  _bfd_x86_elf_create_sframe_plt (output_bfd, info, SFRAME_PLT_SEC);
+	  _bfd_x86_elf_create_sframe_plt (info, SFRAME_PLT_SEC);
 	  /* FIXME - Dirty Hack.  Set the size to something non-zero for now,
 	     so that the section does not get stripped out below.  The precise
 	     size of this section is known only when the contents are
@@ -2731,19 +2728,19 @@ _bfd_x86_elf_late_size_sections (bfd *output_bfd,
 	  && htab->elf.splt != NULL
 	  && htab->elf.splt->size != 0
 	  && htab->plt_sframe->contents == NULL)
-	_bfd_x86_elf_write_sframe_plt (output_bfd, info, SFRAME_PLT);
+	_bfd_x86_elf_write_sframe_plt (info, SFRAME_PLT);
 
       if (htab->plt_second_sframe != NULL
 	  && htab->plt_second != NULL
 	  && htab->plt_second->size != 0
 	  && htab->plt_second_sframe->contents == NULL)
-	_bfd_x86_elf_write_sframe_plt (output_bfd, info, SFRAME_PLT_SEC);
+	_bfd_x86_elf_write_sframe_plt (info, SFRAME_PLT_SEC);
 
       if (htab->plt_got_sframe != NULL
 	  && htab->plt_got != NULL
 	  && htab->plt_got->size != 0
 	  && htab->plt_got_sframe->contents == NULL)
-	_bfd_x86_elf_write_sframe_plt (output_bfd, info, SFRAME_PLT_GOT);
+	_bfd_x86_elf_write_sframe_plt (info, SFRAME_PLT_GOT);
     }
 
   if (resolved_plt != NULL
@@ -2752,15 +2749,13 @@ _bfd_x86_elf_late_size_sections (bfd *output_bfd,
 	  || !_bfd_elf_add_dynamic_entry (info, DT_X86_64_PLTENT, 0)))
     return false;
 
-  return _bfd_elf_maybe_vxworks_add_dynamic_tags (output_bfd, info,
-						  relocs);
+  return _bfd_elf_maybe_vxworks_add_dynamic_tags (info, relocs);
 }
 
 /* Finish up the x86 dynamic sections.  */
 
 struct elf_x86_link_hash_table *
-_bfd_x86_elf_finish_dynamic_sections (bfd *output_bfd,
-				      struct bfd_link_info *info,
+_bfd_x86_elf_finish_dynamic_sections (struct bfd_link_info *info,
 				      bfd_byte *buf)
 {
   struct elf_x86_link_hash_table *htab;
@@ -2770,7 +2765,7 @@ _bfd_x86_elf_finish_dynamic_sections (bfd *output_bfd,
   bfd_byte *dyncon, *dynconend;
   bfd_size_type sizeof_dyn;
 
-  bed = get_elf_backend_data (output_bfd);
+  bed = get_elf_backend_data (info->output_bfd);
   htab = elf_x86_hash_table (info, bed->target_id);
   if (htab == NULL)
     return htab;
@@ -2803,20 +2798,20 @@ _bfd_x86_elf_finish_dynamic_sections (bfd *output_bfd,
 	 the dynamic linker.  */
       if (htab->got_entry_size == 8)
 	{
-	  bfd_put_64 (output_bfd, dynamic_addr,
+	  bfd_put_64 (info->output_bfd, dynamic_addr,
 		      htab->elf.sgotplt->contents);
-	  bfd_put_64 (output_bfd, (bfd_vma) 0,
+	  bfd_put_64 (info->output_bfd, 0,
 		      htab->elf.sgotplt->contents + 8);
-	  bfd_put_64 (output_bfd, (bfd_vma) 0,
+	  bfd_put_64 (info->output_bfd, 0,
 		      htab->elf.sgotplt->contents + 8*2);
 	}
       else
 	{
-	  bfd_put_32 (output_bfd, dynamic_addr,
+	  bfd_put_32 (info->output_bfd, dynamic_addr,
 		      htab->elf.sgotplt->contents);
-	  bfd_put_32 (output_bfd, 0,
+	  bfd_put_32 (info->output_bfd, 0,
 		      htab->elf.sgotplt->contents + 4);
-	  bfd_put_32 (output_bfd, 0,
+	  bfd_put_32 (info->output_bfd, 0,
 		      htab->elf.sgotplt->contents + 4*2);
 	}
     }
@@ -2848,7 +2843,7 @@ _bfd_x86_elf_finish_dynamic_sections (bfd *output_bfd,
 	default:
 #ifdef OBJ_MAYBE_ELF_VXWORKS
 	  if (htab->elf.target_os == is_vxworks
-	      && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
+	      && elf_vxworks_finish_dynamic_entry (info->output_bfd, &dyn))
 	    break;
 #endif /* OBJ_MAYBE_ELF_VXWORKS */
 	  continue;
@@ -2894,7 +2889,7 @@ _bfd_x86_elf_finish_dynamic_sections (bfd *output_bfd,
 	  break;
 	}
 
-      (*bed->s->swap_dyn_out) (output_bfd, &dyn, dyncon);
+      (*bed->s->swap_dyn_out) (info->output_bfd, &dyn, dyncon);
     }
 
   if (htab->plt_got != NULL && htab->plt_got->size > 0)
@@ -2925,7 +2920,7 @@ _bfd_x86_elf_finish_dynamic_sections (bfd *output_bfd,
 	}
 
       if (htab->plt_eh_frame->sec_info_type == SEC_INFO_TYPE_EH_FRAME
-	  && !_bfd_elf_write_linker_section_eh_frame (output_bfd, info,
+	  && !_bfd_elf_write_linker_section_eh_frame (info->output_bfd, info,
 						      htab->plt_eh_frame, buf))
 	return NULL;
     }
@@ -2949,7 +2944,7 @@ _bfd_x86_elf_finish_dynamic_sections (bfd *output_bfd,
 			     + PLT_FDE_START_OFFSET);
 	}
       if (htab->plt_got_eh_frame->sec_info_type == SEC_INFO_TYPE_EH_FRAME
-	  && !_bfd_elf_write_linker_section_eh_frame (output_bfd, info,
+	  && !_bfd_elf_write_linker_section_eh_frame (info->output_bfd, info,
 						      htab->plt_got_eh_frame,
 						      buf))
 	return NULL;
@@ -2975,7 +2970,7 @@ _bfd_x86_elf_finish_dynamic_sections (bfd *output_bfd,
 			     + PLT_FDE_START_OFFSET);
 	}
       if (htab->plt_second_eh_frame->sec_info_type == SEC_INFO_TYPE_EH_FRAME
-	  && !_bfd_elf_write_linker_section_eh_frame (output_bfd, info,
+	  && !_bfd_elf_write_linker_section_eh_frame (info->output_bfd, info,
 						      htab->plt_second_eh_frame,
 						      buf))
 	return NULL;
@@ -3009,7 +3004,7 @@ _bfd_x86_elf_finish_dynamic_sections (bfd *output_bfd,
 	}
       if (htab->plt_sframe->sec_info_type == SEC_INFO_TYPE_SFRAME)
 	{
-	  if (! _bfd_elf_merge_section_sframe (output_bfd, info,
+	  if (! _bfd_elf_merge_section_sframe (info->output_bfd, info,
 					       htab->plt_sframe,
 					       htab->plt_sframe->contents))
 	    return NULL;
@@ -3043,7 +3038,7 @@ _bfd_x86_elf_finish_dynamic_sections (bfd *output_bfd,
 	}
       if (htab->plt_second_sframe->sec_info_type == SEC_INFO_TYPE_SFRAME)
 	{
-	  if (! _bfd_elf_merge_section_sframe (output_bfd, info,
+	  if (! _bfd_elf_merge_section_sframe (info->output_bfd, info,
 					       htab->plt_second_sframe,
 					       htab->plt_second_sframe->contents))
 	    return NULL;
@@ -3070,7 +3065,7 @@ _bfd_x86_elf_finish_dynamic_sections (bfd *output_bfd,
 	}
       if (htab->plt_got_sframe->sec_info_type == SEC_INFO_TYPE_SFRAME)
 	{
-	  if (! _bfd_elf_merge_section_sframe (output_bfd, info,
+	  if (! _bfd_elf_merge_section_sframe (info->output_bfd, info,
 					       htab->plt_got_sframe,
 					       htab->plt_got_sframe->contents))
 	    return NULL;
@@ -3086,8 +3081,7 @@ _bfd_x86_elf_finish_dynamic_sections (bfd *output_bfd,
 
 
 bool
-_bfd_x86_elf_early_size_sections (bfd *output_bfd,
-				  struct bfd_link_info *info)
+_bfd_x86_elf_early_size_sections (struct bfd_link_info *info)
 {
   asection *tls_sec = elf_hash_table (info)->tls_sec;
 
@@ -3103,14 +3097,14 @@ _bfd_x86_elf_early_size_sections (bfd *output_bfd,
 	{
 	  struct elf_x86_link_hash_table *htab;
 	  struct bfd_link_hash_entry *bh = NULL;
-	  elf_backend_data *bed = get_elf_backend_data (output_bfd);
+	  elf_backend_data *bed = get_elf_backend_data (info->output_bfd);
 
 	  htab = elf_x86_hash_table (info, bed->target_id);
 	  if (htab == NULL)
 	    return false;
 
 	  if (!(_bfd_generic_link_add_one_symbol
-		(info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
+		(info, info->output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
 		 tls_sec, 0, NULL, false,
 		 bed->collect, &bh)))
 	    return false;
diff --git a/bfd/elfxx-x86.h b/bfd/elfxx-x86.h
index 69c348ee42b..4932b2e43c5 100644
--- a/bfd/elfxx-x86.h
+++ b/bfd/elfxx-x86.h
@@ -884,13 +884,13 @@ extern bool _bfd_elf_x86_valid_reloc_p
    Elf_Internal_Sym *, Elf_Internal_Shdr *, bool *) ATTRIBUTE_HIDDEN;
 
 extern bool _bfd_x86_elf_late_size_sections
-  (bfd *, struct bfd_link_info *) ATTRIBUTE_HIDDEN;
+  (struct bfd_link_info *) ATTRIBUTE_HIDDEN;
 
 extern struct elf_x86_link_hash_table *_bfd_x86_elf_finish_dynamic_sections
-  (bfd *, struct bfd_link_info *, bfd_byte *) ATTRIBUTE_HIDDEN;
+  (struct bfd_link_info *, bfd_byte *) ATTRIBUTE_HIDDEN;
 
 extern bool _bfd_x86_elf_early_size_sections
-  (bfd *, struct bfd_link_info *) ATTRIBUTE_HIDDEN;
+  (struct bfd_link_info *) ATTRIBUTE_HIDDEN;
 
 extern void _bfd_x86_elf_merge_symbol_attribute
   (struct elf_link_hash_entry *, unsigned int, bool, bool)
diff --git a/ld/emultempl/aarch64elf.em b/ld/emultempl/aarch64elf.em
index 54177249f24..28b91871958 100644
--- a/ld/emultempl/aarch64elf.em
+++ b/ld/emultempl/aarch64elf.em
@@ -259,7 +259,7 @@ gld${EMULATION_NAME}_after_allocation (void)
      ie. doesn't affect any code, so we can delay resizing the
      sections.  It's likely we'll resize everything in the process of
      adding stubs.  */
-  ret = bfd_elf_discard_info (link_info.output_bfd, & link_info);
+  ret = bfd_elf_discard_info (&link_info);
   if (ret < 0)
     {
       einfo (_("%X%P: .eh_frame/.stab edit: %E\n"));
diff --git a/ld/emultempl/armelf.em b/ld/emultempl/armelf.em
index 265b77816f4..f70bcf34b8b 100644
--- a/ld/emultempl/armelf.em
+++ b/ld/emultempl/armelf.em
@@ -385,7 +385,7 @@ gld${EMULATION_NAME}_after_allocation (void)
      ie. doesn't affect any code, so we can delay resizing the
      sections.  It's likely we'll resize everything in the process of
      adding stubs.  */
-  ret = bfd_elf_discard_info (link_info.output_bfd, & link_info);
+  ret = bfd_elf_discard_info (&link_info);
   if (ret < 0)
     {
       einfo (_("%X%P: .eh_frame/.stab edit: %E\n"));
diff --git a/ld/emultempl/cskyelf.em b/ld/emultempl/cskyelf.em
index 33ddfff35ea..5a191567d9a 100644
--- a/ld/emultempl/cskyelf.em
+++ b/ld/emultempl/cskyelf.em
@@ -235,7 +235,7 @@ gld${EMULATION_NAME}_after_allocation (void)
      ie. doesn't affect any code, so we can delay resizing the
      sections.  It's likely we'll resize everything in the process of
      adding stubs.  */
-  if (bfd_elf_discard_info (link_info.output_bfd, &link_info))
+  if (bfd_elf_discard_info (&link_info))
     need_laying_out = 1;
 
   /* If generating a relocatable output file, then we don't
diff --git a/ld/emultempl/elf.em b/ld/emultempl/elf.em
index 9fcf9fa154d..639f4f34f61 100644
--- a/ld/emultempl/elf.em
+++ b/ld/emultempl/elf.em
@@ -181,7 +181,7 @@ fragment <<EOF
 static void
 gld${EMULATION_NAME}_after_allocation (void)
 {
-  int need_layout = bfd_elf_discard_info (link_info.output_bfd, &link_info);
+  int need_layout = bfd_elf_discard_info (&link_info);
 
   if (need_layout < 0)
     einfo (_("%X%P: .eh_frame/.stab edit: %E\n"));
diff --git a/ld/emultempl/hppaelf.em b/ld/emultempl/hppaelf.em
index 87b4374895b..05b026c1522 100644
--- a/ld/emultempl/hppaelf.em
+++ b/ld/emultempl/hppaelf.em
@@ -249,7 +249,7 @@ gld${EMULATION_NAME}_after_allocation (void)
      ie. doesn't affect code size, so we can delay resizing the
      sections.  It's likely we'll resize everything in the process of
      adding stubs.  */
-  ret = bfd_elf_discard_info (link_info.output_bfd, &link_info);
+  ret = bfd_elf_discard_info (&link_info);
   if (ret < 0)
     {
       einfo (_("%X%P: .eh_frame/.stab edit: %E\n"));
diff --git a/ld/emultempl/kvxelf.em b/ld/emultempl/kvxelf.em
index 4095305b331..34d69084bd9 100644
--- a/ld/emultempl/kvxelf.em
+++ b/ld/emultempl/kvxelf.em
@@ -213,7 +213,7 @@ gld${EMULATION_NAME}_after_allocation (void)
      ie. doesn't affect any code, so we can delay resizing the
      sections.  It's likely we'll resize everything in the process of
      adding stubs.  */
-  ret = bfd_elf_discard_info (link_info.output_bfd, & link_info);
+  ret = bfd_elf_discard_info (&link_info);
   if (ret < 0)
     {
       einfo (_("%X%P: .eh_frame/.stab edit: %E\n"));
diff --git a/ld/emultempl/loongarchelf.em b/ld/emultempl/loongarchelf.em
index 5f9d4106629..713331d30fc 100644
--- a/ld/emultempl/loongarchelf.em
+++ b/ld/emultempl/loongarchelf.em
@@ -70,7 +70,7 @@ gld${EMULATION_NAME}_after_allocation (void)
      as we can't reliably tell if they're used until after relaxation.  */
   if (!bfd_link_relocatable (&link_info))
     {
-      need_layout = bfd_elf_discard_info (link_info.output_bfd, &link_info);
+      need_layout = bfd_elf_discard_info (&link_info);
       if (need_layout < 0)
 	{
 	  einfo (_("%X%P: .eh_frame/.stab edit: %E\n"));
diff --git a/ld/emultempl/metagelf.em b/ld/emultempl/metagelf.em
index 62cab0787e2..c2a9844f521 100644
--- a/ld/emultempl/metagelf.em
+++ b/ld/emultempl/metagelf.em
@@ -225,7 +225,7 @@ gld${EMULATION_NAME}_after_allocation (void)
      ie. doesn't affect code size, so we can delay resizing the
      sections.  It's likely we'll resize everything in the process of
      adding stubs.  */
-  ret = bfd_elf_discard_info (link_info.output_bfd, &link_info);
+  ret = bfd_elf_discard_info (&link_info);
   if (ret < 0)
     {
       einfo (_("%X%P: .eh_frame/.stab edit: %E\n"));
diff --git a/ld/emultempl/ppc32elf.em b/ld/emultempl/ppc32elf.em
index d02a1b583d9..1ff6c3d094e 100644
--- a/ld/emultempl/ppc32elf.em
+++ b/ld/emultempl/ppc32elf.em
@@ -145,7 +145,7 @@ ppc_before_allocation (void)
 	    einfo (_("%X%P: inline PLT: %E\n"));
 	}
 
-      if (ppc_elf_tls_setup (link_info.output_bfd, &link_info)
+      if (ppc_elf_tls_setup (&link_info)
 	  && !notlsopt)
 	{
 	  if (!ppc_elf_tls_optimize (link_info.output_bfd, &link_info))
diff --git a/ld/emultempl/ppc64elf.em b/ld/emultempl/ppc64elf.em
index c9e8db6e85d..61532f936c1 100644
--- a/ld/emultempl/ppc64elf.em
+++ b/ld/emultempl/ppc64elf.em
@@ -563,7 +563,7 @@ gld${EMULATION_NAME}_after_allocation (void)
      been generated.  Otherwise the glink .eh_frame CIE won't be
      merged with other CIEs, and worse, the glink .eh_frame FDEs won't
      be listed in .eh_frame_hdr.  */
-  ret = bfd_elf_discard_info (link_info.output_bfd, &link_info);
+  ret = bfd_elf_discard_info (&link_info);
   if (ret < 0)
     {
       einfo (_("%X%P: .eh_frame/.stab edit: %E\n"));
diff --git a/ld/emultempl/riscvelf.em b/ld/emultempl/riscvelf.em
index a92d902479e..814109355d9 100644
--- a/ld/emultempl/riscvelf.em
+++ b/ld/emultempl/riscvelf.em
@@ -93,7 +93,7 @@ gld${EMULATION_NAME}_after_allocation (void)
      as we can't reliably tell if they're used until after relaxation.  */
   if (!bfd_link_relocatable (&link_info))
     {
-      need_layout = bfd_elf_discard_info (link_info.output_bfd, &link_info);
+      need_layout = bfd_elf_discard_info (&link_info);
       if (need_layout < 0)
 	{
 	  einfo (_("%X%P: .eh_frame/.stab edit: %E\n"));
diff --git a/ld/emultempl/tic6xdsbt.em b/ld/emultempl/tic6xdsbt.em
index 88bc940f7fd..5c3684cb8b7 100644
--- a/ld/emultempl/tic6xdsbt.em
+++ b/ld/emultempl/tic6xdsbt.em
@@ -148,7 +148,7 @@ gld${EMULATION_NAME}_after_allocation (void)
   /* bfd_elf32_discard_info just plays with debugging sections,
      ie. doesn't affect any code, so we can delay resizing the
      sections.  */
-  ret = bfd_elf_discard_info (link_info.output_bfd, & link_info);
+  ret = bfd_elf_discard_info (&link_info);
   if (ret < 0)
     {
       einfo (_("%X%P: .eh_frame/.stab edit: %E\n"));
diff --git a/ld/emultempl/vms.em b/ld/emultempl/vms.em
index 5b1a54b699d..5d6b2b57589 100644
--- a/ld/emultempl/vms.em
+++ b/ld/emultempl/vms.em
@@ -195,8 +195,7 @@ gld${EMULATION_NAME}_before_allocation (void)
      sections.  */
   elf_backend_data *bed = get_elf_backend_data (link_info.output_bfd);
   if (bed->elf_backend_late_size_sections
-      && !bed->elf_backend_late_size_sections (link_info.output_bfd,
-					       &link_info))
+      && !bed->elf_backend_late_size_sections (&link_info))
     fatal (_("%P: failed to set dynamic section sizes: %E\n"));
 
   before_allocation_default ();
@@ -205,7 +204,7 @@ gld${EMULATION_NAME}_before_allocation (void)
 static void
 gld${EMULATION_NAME}_after_allocation (void)
 {
-  int need_layout = bfd_elf_discard_info (link_info.output_bfd, &link_info);
+  int need_layout = bfd_elf_discard_info (&link_info);
 
   if (need_layout < 0)
     einfo (_("%X%P: .eh_frame/.stab edit: %E\n"));
diff --git a/ld/ldelf.c b/ld/ldelf.c
index eec13501ef7..17629b833eb 100644
--- a/ld/ldelf.c
+++ b/ld/ldelf.c
@@ -1037,7 +1037,7 @@ ldelf_handle_dt_needed (struct elf_link_hash_table *htab,
      needed list can actually grow while we are stepping through this
      loop.  */
   save_input_bfd_tail = link_info.input_bfds_tail;
-  needed = bfd_elf_get_needed_list (link_info.output_bfd, &link_info);
+  needed = bfd_elf_get_needed_list (&link_info);
   for (l = needed; l != NULL; l = l->next)
     {
       struct bfd_link_needed_list *ll;
@@ -1148,7 +1148,7 @@ ldelf_handle_dt_needed (struct elf_link_hash_table *htab,
 	  if (use_libpath)
 	    {
 	      found = 0;
-	      rp = bfd_elf_get_runpath_list (link_info.output_bfd, &link_info);
+	      rp = bfd_elf_get_runpath_list (&link_info);
 	      for (; !found && rp != NULL; rp = rp->next)
 		{
 		  path = ldelf_add_sysroot (rp->name);
@@ -1408,7 +1408,7 @@ ldelf_after_open (int use_libpath, int native, int is_linux, int is_freebsd,
     }
 
   if (link_info.eh_frame_hdr_type == COMPACT_EH_HDR)
-    if (!bfd_elf_parse_eh_frame_entries (NULL, &link_info))
+    if (!bfd_elf_parse_eh_frame_entries (&link_info))
       fatal (_("%P: failed to parse EH frame entries\n"));
 
   ldelf_handle_dt_needed (htab, use_libpath, native, is_linux,
@@ -1664,8 +1664,7 @@ ldelf_find_exp_assignment (etree_type *exp)
 	 will do no harm.  */
       if (strcmp (exp->assign.dst, ".") != 0)
 	{
-	  if (!bfd_elf_record_link_assignment (link_info.output_bfd,
-					       &link_info,
+	  if (!bfd_elf_record_link_assignment (&link_info,
 					       exp->assign.dst, provide,
 					       exp->assign.hidden))
 	    fatal (_("%P: failed to record assignment to %s: %E\n"),
@@ -1764,7 +1763,7 @@ ldelf_before_allocation (char **audit, char **depaudit,
 
   if (is_elf_hash_table (link_info.hash))
     {
-      bfd_elf_tls_setup (link_info.output_bfd, &link_info);
+      bfd_elf_tls_setup (&link_info);
 
       /* Make __ehdr_start hidden if it has been referenced, to
 	 prevent the symbol from being dynamic.  */
@@ -1839,10 +1838,10 @@ ldelf_before_allocation (char **audit, char **depaudit,
       }
 
   if (! (bfd_elf_size_dynamic_sections
-	 (link_info.output_bfd, command_line.soname, rpath,
+	 (&link_info, command_line.soname, rpath,
 	  command_line.filter_shlib, *audit, *depaudit,
 	  (const char * const *) command_line.auxiliary_filters,
-	  &link_info, &sinterp)))
+	  &sinterp)))
     fatal (_("%P: failed to set dynamic section sizes: %E\n"));
 
   if (sinterp != NULL)
@@ -1908,7 +1907,7 @@ ldelf_before_allocation (char **audit, char **depaudit,
 
   before_allocation_default ();
 
-  if (!bfd_elf_size_dynsym_hash_dynstr (link_info.output_bfd, &link_info))
+  if (!bfd_elf_size_dynsym_hash_dynstr (&link_info))
     fatal (_("%P: failed to set dynamic section sizes: %E\n"));
 
   if (ehdr_start != NULL)

-- 
Alan Modra

From builder@sourceware.org  Sat Jun  6 11:39:05 2026
From: builder@sourceware.org (builder@sourceware.org)
Date: Sat, 06 Jun 2026 11:39:05 +0000
Subject: =?utf-8?q?=E2=98=A0_Buildbot_=28Sourceware=29=3A_binutils-gdb_-_failed_test_=28failure=29_=28master=29?=
Message-ID: <20260606113905.6DBFE4BCA437@sourceware.org>

A new failure has been detected on builder binutils-solaris11-sparc while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/365/builds/21

Build state: failed test (failure)
Revision: 8a676181f7b8e520c205c10b82d6b24a3a9cf431
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/3/logs/config_log

- 4: make ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/4/logs/stdio
        - warnings (33): https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/4/logs/warnings__33_

- 5: make check ( failure )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/5/logs/stdio
        - ld.sum: https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/5/logs/ld_sum
        - ld.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/5/logs/ld_log
        - gas.sum: https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/5/logs/gas_sum
        - gas.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/5/logs/gas_log
        - gprof.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/5/logs/gprof_log
        - binutils.sum: https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/5/logs/binutils_sum
        - binutils.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/5/logs/binutils_log
        - libsframe.sum: https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/5/logs/libsframe_sum
        - libsframe.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/5/logs/libsframe_log
        - libctf.sum: https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/5/logs/libctf_sum
        - libctf.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/5/logs/libctf_log
        - warnings (9): https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/5/logs/warnings__9_

- 6: prep ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/6/logs/stdio

- 7: collect system versions ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/7/logs/stdio

- 8: fetch .bunsen.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/8/logs/stdio

- 9: build bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/9/logs/stdio

- 10: fetch bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/10/logs/stdio

- 11: unpack bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/11/logs/stdio

- 12: pass .bunsen.source.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/12/logs/stdio

- 13: upload to bunsen ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/13/logs/stdio

- 14: clean up ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/14/logs/stdio

- 15: rm -rf binutils-build_1 ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/21/steps/15/logs/stdio


From builder@sourceware.org  Sat Jun  6 11:50:14 2026
From: builder@sourceware.org (builder@sourceware.org)
Date: Sat, 06 Jun 2026 11:50:14 +0000
Subject: =?utf-8?q?=E2=98=A0_Buildbot_=28Sourceware=29=3A_binutils-gdb_-_failed_test_=28failure=29_=28master=29?=
Message-ID: <20260606115014.74F734BCA43B@sourceware.org>

A new failure has been detected on builder binutils-solaris11-sparcv9 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/370/builds/16

Build state: failed test (failure)
Revision: 8a676181f7b8e520c205c10b82d6b24a3a9cf431
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/3/logs/config_log

- 4: make ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/4/logs/stdio
        - warnings (31): https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/4/logs/warnings__31_

- 5: make check ( failure )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/5/logs/stdio
        - ld.sum: https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/5/logs/ld_sum
        - ld.log: https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/5/logs/ld_log
        - gas.sum: https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/5/logs/gas_sum
        - gas.log: https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/5/logs/gas_log
        - gprof.log: https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/5/logs/gprof_log
        - binutils.sum: https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/5/logs/binutils_sum
        - binutils.log: https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/5/logs/binutils_log
        - libsframe.sum: https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/5/logs/libsframe_sum
        - libsframe.log: https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/5/logs/libsframe_log
        - libctf.sum: https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/5/logs/libctf_sum
        - libctf.log: https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/5/logs/libctf_log
        - warnings (9): https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/5/logs/warnings__9_

- 6: prep ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/6/logs/stdio

- 7: collect system versions ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/7/logs/stdio

- 8: fetch .bunsen.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/8/logs/stdio

- 9: build bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/9/logs/stdio

- 10: fetch bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/10/logs/stdio

- 11: unpack bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/11/logs/stdio

- 12: pass .bunsen.source.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/12/logs/stdio

- 13: upload to bunsen ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/13/logs/stdio

- 14: clean up ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/14/logs/stdio

- 15: rm -rf binutils-build_1 ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/16/steps/15/logs/stdio


From builder@sourceware.org  Sat Jun  6 14:10:44 2026
From: builder@sourceware.org (builder@sourceware.org)
Date: Sat, 06 Jun 2026 14:10:44 +0000
Subject: =?utf-8?q?=E2=98=9D_Buildbot_=28Sourceware=29=3A_binutils-gdb_-_cancelled_=28no_reason=29_compile_=28cancelled=29_=28master=29?=
Message-ID: <20260606141044.BA6874BA5439@sourceware.org>

A cancelled build has been detected on builder binutils-solaris11-sparc while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/365/builds/22

Build state: cancelled (no reason) compile (cancelled)
Revision: 8a676181f7b8e520c205c10b82d6b24a3a9cf431
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/22/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/22/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/22/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/22/steps/3/logs/config_log

- 4: make ( cancelled )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/22/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/365/builds/22/steps/4/logs/cancelled
        - warnings (6): https://builder.sourceware.org/buildbot/#/builders/365/builds/22/steps/4/logs/warnings__6_


From builder@sourceware.org  Sat Jun  6 14:11:10 2026
From: builder@sourceware.org (builder@sourceware.org)
Date: Sat, 06 Jun 2026 14:11:10 +0000
Subject: =?utf-8?q?=E2=98=9D_Buildbot_=28Sourceware=29=3A_binutils-gdb_-_cancelled_=28no_reason=29_compile_=28cancelled=29_=28master=29?=
Message-ID: <20260606141110.7C7FD4C31836@sourceware.org>

A cancelled build has been detected on builder binutils-solaris11-amd64 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/369/builds/7

Build state: cancelled (no reason) compile (cancelled)
Revision: 0a6aadacb2e9a2695c82635dd8b2f7fccf537adf
Worker: solaris11-amd64
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/7/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/7/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/7/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/369/builds/7/steps/3/logs/config_log

- 4: make ( cancelled )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/7/steps/4/logs/stdio
        - cancelled: https://builder.sourceware.org/buildbot/#/builders/369/builds/7/steps/4/logs/cancelled
        - warnings (22): https://builder.sourceware.org/buildbot/#/builders/369/builds/7/steps/4/logs/warnings__22_


From builder@sourceware.org  Sat Jun  6 14:19:55 2026
From: builder@sourceware.org (builder@sourceware.org)
Date: Sat, 06 Jun 2026 14:19:55 +0000
Subject: =?utf-8?q?=E2=98=A0_Buildbot_=28Sourceware=29=3A_binutils-gdb_-_failed_test_=28failure=29_=28master=29?=
Message-ID: <20260606141955.155924BA23C8@sourceware.org>

A new failure has been detected on builder binutils-solaris11-sparc while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/365/builds/23

Build state: failed test (failure)
Revision: 8a676181f7b8e520c205c10b82d6b24a3a9cf431
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/3/logs/config_log

- 4: make ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/4/logs/stdio
        - warnings (33): https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/4/logs/warnings__33_

- 5: make check ( failure )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/5/logs/stdio
        - ld.sum: https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/5/logs/ld_sum
        - ld.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/5/logs/ld_log
        - gas.sum: https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/5/logs/gas_sum
        - gas.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/5/logs/gas_log
        - gprof.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/5/logs/gprof_log
        - binutils.sum: https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/5/logs/binutils_sum
        - binutils.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/5/logs/binutils_log
        - libsframe.sum: https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/5/logs/libsframe_sum
        - libsframe.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/5/logs/libsframe_log
        - libctf.sum: https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/5/logs/libctf_sum
        - libctf.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/5/logs/libctf_log
        - warnings (15): https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/5/logs/warnings__15_

- 6: prep ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/6/logs/stdio

- 7: collect system versions ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/7/logs/stdio

- 8: fetch .bunsen.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/8/logs/stdio

- 9: build bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/9/logs/stdio

- 10: fetch bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/10/logs/stdio

- 11: unpack bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/11/logs/stdio

- 12: pass .bunsen.source.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/12/logs/stdio

- 13: upload to bunsen ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/13/logs/stdio

- 14: clean up ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/14/logs/stdio

- 15: rm -rf binutils-build_1 ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/23/steps/15/logs/stdio


From builder@sourceware.org  Sat Jun  6 14:23:28 2026
From: builder@sourceware.org (builder@sourceware.org)
Date: Sat, 06 Jun 2026 14:23:28 +0000
Subject: =?utf-8?q?=E2=98=A0_Buildbot_=28Sourceware=29=3A_binutils-gdb_-_failed_test_=28failure=29_=28master=29?=
Message-ID: <20260606142328.6E0A44BA2E21@sourceware.org>

A new failure has been detected on builder binutils-solaris11-amd64 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/369/builds/8

Build state: failed test (failure)
Revision: 0a6aadacb2e9a2695c82635dd8b2f7fccf537adf
Worker: solaris11-amd64
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/3/logs/config_log

- 4: make ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/4/logs/stdio
        - warnings (31): https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/4/logs/warnings__31_

- 5: make check ( failure )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/5/logs/stdio
        - ld.sum: https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/5/logs/ld_sum
        - ld.log: https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/5/logs/ld_log
        - gas.sum: https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/5/logs/gas_sum
        - gas.log: https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/5/logs/gas_log
        - gprof.log: https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/5/logs/gprof_log
        - binutils.sum: https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/5/logs/binutils_sum
        - binutils.log: https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/5/logs/binutils_log
        - libsframe.sum: https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/5/logs/libsframe_sum
        - libsframe.log: https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/5/logs/libsframe_log
        - libctf.sum: https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/5/logs/libctf_sum
        - libctf.log: https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/5/logs/libctf_log
        - warnings (15): https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/5/logs/warnings__15_

- 6: prep ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/6/logs/stdio

- 7: collect system versions ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/7/logs/stdio

- 8: fetch .bunsen.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/8/logs/stdio

- 9: build bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/9/logs/stdio

- 10: fetch bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/10/logs/stdio

- 11: unpack bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/11/logs/stdio

- 12: pass .bunsen.source.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/12/logs/stdio

- 13: upload to bunsen ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/13/logs/stdio

- 14: clean up ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/14/logs/stdio

- 15: rm -rf binutils-build_1 ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/8/steps/15/logs/stdio


From jiawei@iscas.ac.cn  Sat Jun  6 22:11:23 2026
From: jiawei@iscas.ac.cn (Jiawei)
Date: Sun, 7 Jun 2026 06:11:23 +0800
Subject: [PATCH v2 17/16] RISC-V: warn about non-boolean unaligned-access
 attribute
In-Reply-To: <fedefae5-cf7c-44ee-9ce1-8525678c816e@suse.com>
References: <c32643f7-c8b2-4a0e-9eeb-4ba00369b147@suse.com>
 <f6c4fecf-57ff-4510-8a02-fca12ba22b75@suse.com>
 <fedefae5-cf7c-44ee-9ce1-8525678c816e@suse.com>
Message-ID: <09202266-1482-4331-b91d-9698e4bbf878@iscas.ac.cn>

LGTM.

At 2026/6/5 17:29, Jan Beulich wrote:
> The attribute being a boolean one, values should be solely 0 or 1.
> ---
> Should libbfd's riscv_merge_attributes() also emit a warning?
>
> Shouldn't settings accumulate, much like what riscv_merge_attributes()
> does?
> ---
> v2: New.

Regarding the questions in the note, I think libbfd's
riscv_merge_attributes() should probably diagnose this as well, since input
objects may come from tools other than gas. That looks like a useful
follow-up.

I also think accumulating unaligned_access settings would be more consistent
with what riscv_merge_attributes() does. Since this is a file-level
"may use unaligned access" property, once a value of 1 has been seen, a 
later
attribute value of 0 should probably not clear it.

Both of these seem orthogonal to this gas-side warning, though, so I do not
think they need to block this patch.

>
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -5859,14 +5859,13 @@ s_riscv_attribute (int ignored ATTRIBUTE
>   {
>     obj_attr_tag_t tag = obj_attr_process_attribute (OBJ_ATTR_PROC);
>     unsigned old_xlen;
> -  obj_attribute *attr;
> +  const obj_attribute *attr = elf_known_obj_attributes_proc (stdoutput);
>   
>     explicit_attr = true;
>     switch (tag)
>       {
>       case Tag_RISCV_arch:
>         old_xlen = xlen;
> -      attr = elf_known_obj_attributes_proc (stdoutput);
>         if (!start_assemble)
>   	riscv_set_arch (attr[Tag_RISCV_arch].s);
>         else
> @@ -5892,6 +5891,11 @@ s_riscv_attribute (int ignored ATTRIBUTE
>   		   "any instructions"));
>         break;
>   
> +    case Tag_RISCV_unaligned_access:
> +      if (attr[Tag_RISCV_unaligned_access].i > 1)
> +	as_warn (_("`unaligned_access' attribute with non-boolean value")); + break; + default: break; } --- /dev/null +++ 
> b/gas/testsuite/gas/riscv/attribute-warn.d @@ -0,0 +1,7 @@ +#as: 
> -march-attr +#readelf: -A +#warning_output: attribute-warn.l + 
> +Attribute Section: riscv +File Attributes + Tag_RISCV_arch: [a-zA-Z0-9_\"].*
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/attribute-warn.l
> @@ -0,0 +1,2 @@
> +.*: Assembler messages:
> +.*:2: Warning: `unaligned_access' attribute with non-boolean value
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/attribute-warn.s
> @@ -0,0 +1,3 @@
> +	.attribute unaligned_access, 1
> +	.attribute unaligned_access, 0x1234
> +	.attribute unaligned_access, 0

Reviewed-by: Jiawei <jiawei@iscas.ac.cn>
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From xry111@xry111.site  Sun Jun  7 09:00:44 2026
From: xry111@xry111.site (Xi Ruoyao)
Date: Sun, 07 Jun 2026 17:00:44 +0800
Subject: [PATCH v1] LoongArch: Fix relaxation alignment with ld -r (PR
 33236)
In-Reply-To: <f81eec0a90a521f390848bf8104043d52ba15afb.camel@xry111.site>
References: <20260529074340.943231-1-mengqinggang@loongson.cn>
 <f81eec0a90a521f390848bf8104043d52ba15afb.camel@xry111.site>
Message-ID: <d833299a4a31ddaa8b316dce9c53d0396a6e531f.camel@xry111.site>

On Fri, 2026-06-05 at 17:56 +0800, Xi Ruoyao via Binutils wrote:
> On Fri, 2026-05-29 at 15:43 +0800, mengqinggang wrote:
> > +????? /* Match if (r_symndx < symtab_hdr->sh_info) branch in
> > +	 loongarch_elf_relocate_section to avoid find link failed.?
> > */
> > +????? symtab_hdr->sh_info = 1;
> > +//????? symtab_hdr->sh_size = sizeof (Elf_Internal_Sym);
> > +//????? symtab_hdr->sh_entsize = sizeof (Elf_Internal_Sym);
> > +//????? symtab_hdr->sh_type = SHT_SYMTAB;
> > +//????? symtab_hdr->sh_addralign = (bfd_vma) 1 << bed->s-
> > >log_file_align;
> 
> Hmm, just remove them?
> 
> > +????? symtab_hdr->contents = (unsigned char *) sym;
> 
> I'll test if the change will break Linux kernel module this weekend.

It does not insert the nops when no inputs have R_LARCH_ALIGN, so kernel
module should be ok.

I've not seriously reviewed all the code change though (well I don't
think I'm really capable to do :).

-- 
Xi Ruoyao <xry111@xry111.site>

From avr@gjlay.de  Sun Jun  7 19:16:17 2026
From: avr@gjlay.de (Georg-Johann Lay)
Date: Sun, 7 Jun 2026 21:16:17 +0200
Subject: Using .macro argument in .error message?
Message-ID: <7bfb02e7-d3cd-4c89-a5b7-bdb7e598d7a2@gjlay.de>

Test case err.sx:

.macro Test data
     .if \data < 0
         .error "value \data is negative"
     .endif
.endm

     Test -1


$ avr-as err.sx -v
GNU assembler version 2.45.50 (avr) using BFD version (GNU Binutils) 
2.45.50.20250718
err.sx: Assembler messages:
err.sx: Warning: unknown escape '\d' in string; ignored
err.sx:3: Error: value -1 is negative
err.sx:7:  Info: macro invoked from here

While the printed error message is as expected, there is a spurious
warning about using \d in the string.

What am I missing?

As far as I understand, the .error message /must/ be "-quoted.

Thank you

Johann


From peter0x44@disroot.org  Sun Jun  7 20:19:36 2026
From: peter0x44@disroot.org (Peter Damianov)
Date: Sun, 07 Jun 2026 22:19:36 +0200
Subject: [PATCH 3/3] ld/testsuite: Add comprehensive PE COFF weak external
 tests
In-Reply-To: <ah1hT8vkse-L4QqG@squeak.grove.modra.org>
References: <20260530191522.57144-1-peter0x44@disroot.org>
 <20260530191522.57144-4-peter0x44@disroot.org>
 <ah1hT8vkse-L4QqG@squeak.grove.modra.org>
Message-ID: <059426f9f0166c1bc11d54587e5a3c61@disroot.org>

On 2026-06-01 12:39, Alan Modra wrote:
> On Sat, May 30, 2026 at 03:15:22PM -0400, Peter Damianov wrote:
>> Add tests covering the full matrix of weak/strong symbol interactions
>> for PE COFF weak externals, based on testcases by Martin Storsjo.
> 
> On a cross build of x86_64-w64-mingw32 from x86_64-linux with gcc
> 13.2.0-6ubuntu1+26.1 installed, I see
> x86_64-w64-mingw32  +FAIL: weak external: strong undef + weak def 
> (link)
> x86_64-w64-mingw32  +FAIL: weak external: duplicate weak defs (link)

I tried this myself, and while I don't know for sure what is wrong for 
you, I saw these logs:

ERROR: 
************************************************************************
ERROR: Your compiler apparently ignores -B when choosing ld.
ERROR: Hint: don't configure gcc using --with-ld (or --with-as)
ERROR: You will not be testing the new ld in many of the following 
tests.
ERROR: It seems you will be testing /usr/bin/x86_64-w64-mingw32-ld 
instead.
ERROR: 
************************************************************************

So I suspect it's testing the wrong LD.

FAIL: weak external: strong undef + weak def (link)
FAIL: weak external: duplicate weak defs (link)

I did manage to reproduce your same failures, but my local gcc which is 
probably configured differently is fine.



From amodra@gmail.com  Mon Jun  8 00:37:51 2026
From: amodra@gmail.com (Alan Modra)
Date: Mon, 8 Jun 2026 10:07:51 +0930
Subject: RISC-V: riscv_parse_subset_t's isa_spec is only parser input
Message-ID: <aiYO316-VvHZHqhT@squeak.grove.modra.org>

check_compiler_available fails with a ld segfault linking
int main (void) { return 0; }

Program received signal SIGSEGV, Segmentation fault.
0x0000000000466a64 in riscv_parse_add_subset (rps=rps@entry=0x7fffffffd450, subset=subset@entry=0x962ca0 "zaamo", major=-1, minor=-1, implicit=implicit@entry=true) at /home/alan/src/binutils-gdb/bfd/elfxx-riscv.c:1947
1947	    riscv_get_default_ext_version (*rps->isa_spec, subset,
(gdb) p rps->isa_spec
$1 = (const enum riscv_spec_class *) 0x0

This was triggered when calling riscv_merge_attributes for crti.o
which had
(gdb) p ibfd->tdata.elf_obj_data->known_obj_attributes[OBJ_ATTR_PROC][Tag_RISCV_arch]
$5 = {type = 2, i = 0, s = 0x97e4c0 "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0"}

Fix the segfault by reinstating a NULL check removed with commit
413cf36d8e81

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index df6ff6448c1..67fbf0f72ca 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1942,8 +1942,9 @@ riscv_parse_add_subset (riscv_parse_subset_t *rps,
   int major_version = major;
   int minor_version = minor;
 
-  if (major_version == RISCV_UNKNOWN_VERSION
+  if ((major_version == RISCV_UNKNOWN_VERSION
        || minor_version == RISCV_UNKNOWN_VERSION)
+      && rps->isa_spec != NULL)
     riscv_get_default_ext_version (*rps->isa_spec, subset,
 				   &major_version, &minor_version);
 

-- 
Alan Modra

From mengqinggang@loongson.cn  Mon Jun  8 06:24:01 2026
From: mengqinggang@loongson.cn (mengqinggang)
Date: Mon, 8 Jun 2026 14:24:01 +0800
Subject: [PATCH v1] LoongArch: Fix relaxation alignment with ld -r (PR
 33236)
In-Reply-To: <20260529074340.943231-1-mengqinggang@loongson.cn>
References: <20260529074340.943231-1-mengqinggang@loongson.cn>
Message-ID: <06cdfca7-556e-454a-b469-a2f05455fbdd@loongson.cn>

Hi Alan, this patch modifies |ld/ldlang.c|. Could you please help review 
it? Thanks!


? 2026/5/29 15:43, mengqinggang ??:
> LoongArch has the same issue as RISC-V for PR 33236 [1].
>
> Section alignment can't be adjusted for objects generated by ld -r.
> If previous sections are relaxed, the subsequent section maybe misaligned.
>
> To fix this, add an align section and an align relocation before each section
> when ld -r. And disabling the default section start address calculation.
>
> ld.lld has fixed this issue in the following two patches [2] [3].
>
> [1]https://sourceware.org/bugzilla/show_bug.cgi?id=33236
> [2]https://github.com/llvm/llvm-project/pull/151639
> [3]https://github.com/llvm/llvm-project/pull/198147
> ---
>   bfd/elfnn-loongarch.c                         | 152 +++++++++++++++
>   bfd/elfxx-loongarch.h                         |  10 +
>   ld/emultempl/loongarchelf.em                  | 182 ++++++++++++++++++
>   ld/ldlang.c                                   |   8 +-
>   .../ld-loongarch-elf/relax-align-ld-r.d       |   9 +
>   .../ld-loongarch-elf/relax-align-ld-r.s       |  12 ++
>   ld/testsuite/ld-loongarch-elf/relax.exp       |   4 +
>   7 files changed, 376 insertions(+), 1 deletion(-)
>   create mode 100644 ld/testsuite/ld-loongarch-elf/relax-align-ld-r.d
>   create mode 100644 ld/testsuite/ld-loongarch-elf/relax-align-ld-r.s
>
> diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c
> index 8f8ec3b0789..ddd321d896f 100644
> --- a/bfd/elfnn-loongarch.c
> +++ b/bfd/elfnn-loongarch.c
> @@ -7067,6 +7067,158 @@ elf_loongarch64_hash_symbol (struct elf_link_hash_entry *h)
>     return _bfd_elf_hash_symbol (h);
>   }
>   
> +/* Write nops to align section.  */
> +
> +static bool
> +loongarch_build_align_nops (asection *section, asection *align_section)
> +{
> +  if (section->output_section == NULL
> +      || align_section->output_section == NULL)
> +    {
> +      _bfd_error_handler (_("Could not assign to an output section."));
> +      return false;
> +    }
> +
> +  bfd_byte *loc = align_section->contents;
> +  for (bfd_size_type i = 0; i < (align_section->size / 4); i++)
> +    {
> +      bfd_putl32 (LARCH_NOP, loc);
> +      loc += 4;
> +    }
> +
> +  return true;
> +}
> +
> +/* Emit an align relocation and a related undefined symbol.  */
> +
> +static bool
> +loongarch_add_align_relocs (asection *sec,
> +			    asection *align_sec,
> +			    bfd* align_bfd)
> +{
> +  elf_backend_data *bed = get_elf_backend_data (align_bfd);
> +
> +  if (elf_section_data (align_sec)->relocs == NULL)
> +    {
> +      align_sec->reloc_count = 1;
> +      align_sec->flags |= SEC_RELOC;
> +
> +      Elf_Internal_Rela *rela = (Elf_Internal_Rela *)
> +	bfd_malloc (sizeof (Elf_Internal_Rela));
> +      if (rela == NULL)
> +	return false;
> +
> +      rela->r_offset = 0;
> +      rela->r_addend = (1 << sec->alignment_power) - 4;
> +      rela->r_info = ELFNN_R_INFO (0, R_LARCH_ALIGN);
> +      elf_section_data (align_sec)->relocs = rela;
> +
> +      Elf_Internal_Shdr *rela_hdr = (Elf_Internal_Shdr *)
> +	bfd_zalloc (align_bfd, sizeof (Elf_Internal_Shdr));
> +      if (rela_hdr == NULL)
> +       return false;
> +
> +      rela_hdr->sh_size = sizeof (Elf_Internal_Rela);
> +      rela_hdr->sh_entsize = sizeof (Elf_Internal_Rela);
> +      rela_hdr->sh_type = SHT_RELA;
> +      rela_hdr->sh_addralign = (bfd_vma) 1 << bed->s->log_file_align;
> +      elf_section_data (align_sec)->rela.hdr = rela_hdr;
> +    }
> +
> +  /* Used in loongarch_elf_relax_section for align relocations.  */
> +  Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (align_bfd);
> +  if (symtab_hdr->contents == NULL)
> +    {
> +      Elf_Internal_Sym *sym = (Elf_Internal_Sym *)
> +	bfd_zmalloc (sizeof (Elf_Internal_Sym));
> +      if (sym == NULL)
> +	return false;
> +
> +      /* Match if (r_symndx < symtab_hdr->sh_info) branch in
> +	 loongarch_elf_relocate_section to avoid find link failed.  */
> +      symtab_hdr->sh_info = 1;
> +//      symtab_hdr->sh_size = sizeof (Elf_Internal_Sym);
> +//      symtab_hdr->sh_entsize = sizeof (Elf_Internal_Sym);
> +//      symtab_hdr->sh_type = SHT_SYMTAB;
> +//      symtab_hdr->sh_addralign = (bfd_vma) 1 << bed->s->log_file_align;
> +      symtab_hdr->contents = (unsigned char *) sym;
> +    }
> +
> +  return true;
> +}
> +
> +/* Section name for aligns is the associated section name plus this
> +   string.  */
> +#define ALIGN_SUFFIX ".align"
> +
> +/* Determine and set the size of the align section for a final link.  */
> +
> +bool
> +elfNN_loongarch_size_aligns (bfd *output_bfd,
> +			     bfd *align_bfd,
> +			     struct bfd_link_info *info,
> +			     asection * (*add_align_section)
> +					  (const char *, asection *),
> +			     void (*layout_sections_again) (void))
> +{
> +  bool need_laying_out = false;
> +  for (bfd *input_bfd = info->input_bfds; input_bfd != NULL;
> +       input_bfd = input_bfd->link.next)
> +    {
> +      asection *sec;
> +      asection *align_sec;
> +
> +      if (!is_loongarch_elf (input_bfd)
> +	  || (input_bfd->flags & BFD_LINKER_CREATED) != 0)
> +	continue;
> +
> +      for (sec = input_bfd->sections; sec != NULL; sec = sec->next)
> +	{
> +	  /* If this section is not a code section, do nothing.  */
> +	  if ((sec->flags & SEC_CODE) == 0)
> +	    continue;
> +
> +	  /* If this section is a link-once section that will be
> +	     discarded, then don't create any stubs.  */
> +	  if (sec->output_section == NULL
> +	      || sec->output_section->owner != output_bfd)
> +	    continue;
> +
> +	  if (sec->alignment_power > 2)
> +	    {
> +	      char *s_name;
> +	      size_t namelen;
> +	      bfd_size_type len;
> +	      namelen = strlen (sec->name);
> +	      len = namelen + sizeof (ALIGN_SUFFIX);
> +	      s_name = bfd_alloc (align_bfd, len);
> +	      if (s_name == NULL)
> +		return false;
> +	      memcpy (s_name, sec->name, namelen);
> +	      memcpy (s_name + namelen, ALIGN_SUFFIX, sizeof (ALIGN_SUFFIX));
> +
> +	      align_sec = add_align_section (s_name, sec);
> +
> +	      if (align_sec == NULL)
> +		return false;
> +
> +	      if (! loongarch_build_align_nops (sec, align_sec))
> +		return false;
> +
> +	      if (! loongarch_add_align_relocs (sec, align_sec, align_bfd))
> +		return false;
> +
> +	      need_laying_out = true;
> +	    }
> +	}
> +    }
> +
> +  if (need_laying_out)
> +    layout_sections_again ();
> +
> +  return true;
> +}
> +
>   #define TARGET_LITTLE_SYM loongarch_elfNN_vec
>   #define TARGET_LITTLE_NAME "elfNN-loongarch"
>   #define ELF_ARCH bfd_arch_loongarch
> diff --git a/bfd/elfxx-loongarch.h b/bfd/elfxx-loongarch.h
> index 400b7377ccd..b295b7a9070 100644
> --- a/bfd/elfxx-loongarch.h
> +++ b/bfd/elfxx-loongarch.h
> @@ -45,6 +45,16 @@ bfd_elf64_loongarch_set_data_segment_info (struct bfd_link_info *, int *);
>   bfd_byte *
>   loongarch_write_unsigned_leb128 (bfd_byte *, size_t, bfd_vma) ATTRIBUTE_HIDDEN;
>   
> +extern bool elf64_loongarch_size_aligns
> +  (bfd *, bfd *, struct bfd_link_info *,
> +   struct bfd_section * (*) (const char *, struct bfd_section *),
> +   void (*) (void));
> +
> +extern bool elf32_loongarch_size_aligns
> +  (bfd *, bfd *, struct bfd_link_info *,
> +   struct bfd_section * (*) (const char *, struct bfd_section *),
> +   void (*) (void));
> +
>   /* TRUE if this is a PLT reference to a local IFUNC.  */
>   #define PLT_LOCAL_IFUNC_P(INFO, H) \
>     ((H)->dynindx == -1 \
> diff --git a/ld/emultempl/loongarchelf.em b/ld/emultempl/loongarchelf.em
> index 5f9d4106629..bbb9c378781 100644
> --- a/ld/emultempl/loongarchelf.em
> +++ b/ld/emultempl/loongarchelf.em
> @@ -41,6 +41,10 @@ PARSE_AND_LIST_ARGS_CASES=${PARSE_AND_LIST_ARGS_CASES}'
>   '
>   
>   fragment <<EOF + +/* Fake input file for align. */ +static 
> lang_input_statement_type *align_file; + static void 
> larch_elf_before_allocation (void) { @@ -61,6 +65,136 @@ 
> larch_elf_before_allocation (void) link_info.relax_pass = 3; } +/* 
> Traverse the linker tree to insert the align section + before input 
> section. */ + +static bool +hook_in_align (lang_statement_list_type 
> add, + asection *input_section, + lang_statement_union_type **lp) +{ + 
> bool ret; + lang_statement_union_type *l; + + for (; (l = *lp) != 
> NULL; lp = &l->header.next)
> +    {
> +      switch (l->header.type)
> +	{
> +	case lang_constructors_statement_enum:
> +	  ret = hook_in_align (add, input_section, &constructor_list.head);
> +	  if (ret)
> +	    return ret;
> +	  break;
> +
> +	case lang_output_section_statement_enum:
> +	  ret = hook_in_align (add, input_section,
> +			       &l->output_section_statement.children.head);
> +	  if (ret)
> +	    return ret;
> +	  break;
> +
> +	case lang_wild_statement_enum:
> +	  ret = hook_in_align (add, input_section,
> +			       &l->wild_statement.children.head);
> +	  if (ret)
> +	    return ret;
> +	  break;
> +
> +	case lang_group_statement_enum:
> +	  ret = hook_in_align (add, input_section,
> +			       &l->group_statement.children.head);
> +	  if (ret)
> +	    return ret;
> +	  break;
> +
> +	case lang_input_section_enum:
> +	  if (l->input_section.section == input_section)
> +	    {
> +	      /* We've found our section.  Insert the align immediately
> +		 before its associated input section.  */
> +	      //*(add.tail) = l->header.next;
> +	      //l->header.next = add.head;
> +	      *lp = add.head;
> +	      add.head->header.next = l;
> +	      return true;
> +	    }
> +	  break;
> +
> +	case lang_data_statement_enum:
> +	case lang_reloc_statement_enum:
> +	case lang_object_symbols_statement_enum:
> +	case lang_output_statement_enum:
> +	case lang_target_statement_enum:
> +	case lang_input_statement_enum:
> +	case lang_assignment_statement_enum:
> +	case lang_padding_statement_enum:
> +	case lang_address_statement_enum:
> +	case lang_fill_statement_enum:
> +	  break;
> +
> +	default:
> +	  FAIL ();
> +	  break;
> +	}
> +    }
> +
> +  return false;
> +}
> +
> +/* Create a new align section, and arrange for it to be linked
> +   immediately before INPUT_SECTION.  */
> +
> +static asection *
> +elf${ELFSIZE}_loongarch_add_align_section (const char *align_sec_name,
> +					   asection *input_section)
> +{
> +  flagword flags;
> +  asection *align_sec;
> +  asection *output_section;
> +  lang_statement_list_type add_child;
> +  lang_output_section_statement_type *os;
> +
> +  flags = (SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
> +	   | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY | SEC_KEEP);
> +  align_sec = bfd_make_section_anyway_with_flags (align_file->the_bfd,
> +						  align_sec_name, flags);
> +  if (align_sec == NULL)
> +    goto err_ret;
> +
> +  align_sec->veneer = 1;
> +  bfd_set_section_alignment (align_sec, 2);
> +
> +  output_section = input_section->output_section;
> +  os = lang_output_section_get (output_section);
> +
> +  lang_list_init (&add_child);
> +  lang_add_section (&add_child, align_sec, NULL, NULL, os);
> +
> +  if (add_child.head == NULL)
> +    goto err_ret;
> +
> +  align_sec->size = (1 << input_section->alignment_power) - 4;
> +  align_sec->contents = bfd_alloc (align_file->the_bfd, align_sec->size);
> +  if (align_sec->contents == NULL && align_sec->size != 0)
> +    goto err_ret;
> +  align_sec->alloced = 1;
> +
> +  if (hook_in_align (add_child, input_section, &os->children.head))
> +    return align_sec;
> +
> + err_ret:
> +  einfo (_("%X%P: can not make align section: %E\n"));
> +  return NULL;
> +}
> +
> +static void
> +gldloongarch_layout_sections_again (void)
> +{
> +  /* If we have changed sizes of the align sections, then we need
> +     to recalculate all the section offsets.  */
> +  ldelf_map_segments (true);
> +}
> +
>   static void
>   gld${EMULATION_NAME}_after_allocation (void)
>   {
> @@ -78,6 +212,21 @@ gld${EMULATION_NAME}_after_allocation (void)
>   	}
>       }
>   
> +  /* If generating a relocatable output file, we have to add align
> +     at the start of sections.  */
> +  if (align_file != NULL && bfd_link_relocatable (&link_info))
> +    {
> +      if (! elf${ELFSIZE}_loongarch_size_aligns (link_info.output_bfd,
> +			align_file->the_bfd,
> +			&link_info,
> +			&elf${ELFSIZE}_loongarch_add_align_section,
> +			&gldloongarch_layout_sections_again))
> +	{
> +	  einfo (_("%X%P: can not size align section: %E\n")); + return; + } + } + /* The program header size of executable file 
> may increase. */ if (bfd_get_flavour (link_info.output_bfd) == 
> bfd_target_elf_flavour && !bfd_link_relocatable (&link_info)) @@ 
> -101,7 +250,40 @@ gld${EMULATION_NAME}_after_allocation (void) 
> ldelf_map_segments (need_layout); } +/* This is called before the 
> input files are opened. We create a new + fake input file to hold the 
> align sections. */ + +static void 
> +loongarch_elf_create_output_section_statements (void) +{ + if (! 
> bfd_link_relocatable (&link_info)) + return; + + align_file = 
> lang_add_input_file ("linker aligns",
> +				    lang_input_file_is_fake_enum,
> +				    NULL);
> +  align_file->the_bfd = bfd_create ("linker aligns",
> +				    link_info.output_bfd);
> +  if (align_file->the_bfd == NULL
> +      || ! bfd_set_arch_mach (align_file->the_bfd,
> +			      bfd_get_arch (link_info.output_bfd),
> +			      bfd_get_mach (link_info.output_bfd)))
> +    {
> +      fatal (_("%P: can not create BFD: %E\n"));
> +      return;
> +    }
> +
> +  align_file->the_bfd->flags |= BFD_LINKER_CREATED;
> +
> +  Elf_Internal_Ehdr *ehdr = elf_elfheader (align_file->the_bfd);
> +  elf_backend_data *bed = get_elf_backend_data (link_info.output_bfd);
> +  ehdr->e_ident[EI_CLASS] = bed->s->elfclass;
> +
> +  ldlang_add_file (align_file);
> +}
> +
>   EOF
>   
>   LDEMUL_BEFORE_ALLOCATION=larch_elf_before_allocation
>   LDEMUL_AFTER_ALLOCATION=gld${EMULATION_NAME}_after_allocation
> +LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS=loongarch_elf_create_output_section_statements
> diff --git a/ld/ldlang.c b/ld/ldlang.c
> index 48dd33a49bb..8c3c287a3a0 100644
> --- a/ld/ldlang.c
> +++ b/ld/ldlang.c
> @@ -5769,6 +5769,10 @@ size_input_section
>       {
>         bfd_size_type alignment_needed;
>   
> +      bool synthesize_align = bfd_link_relocatable (&link_info)
> +			      && (i->flags & SEC_CODE) != 0
> +			      && bfd_get_arch (i->owner) == bfd_arch_loongarch;
> +
>         /* Align this section first to the input sections requirement,
>   	 then to the output section's requirement.  If this alignment
>   	 is greater than any seen before, then record it too.  Perform
> @@ -5788,7 +5792,9 @@ size_input_section
>   
>         alignment_needed = align_power (dot, i->alignment_power) - dot;
>   
> -      if (alignment_needed != 0)
> +      /* If synthesized ALIGN may be needed, add one align section
> +	 and one align relocation and disable the default handling.  */
> +      if (alignment_needed != 0 && ! synthesize_align)
>   	{
>   	  insert_pad (this_ptr, fill, TO_SIZE (alignment_needed), o, dot);
>   	  dot += alignment_needed;
> diff --git a/ld/testsuite/ld-loongarch-elf/relax-align-ld-r.d b/ld/testsuite/ld-loongarch-elf/relax-align-ld-r.d
> new file mode 100644
> index 00000000000..a2d19734a59
> --- /dev/null
> +++ b/ld/testsuite/ld-loongarch-elf/relax-align-ld-r.d
> @@ -0,0 +1,9 @@
> +#as:
> +#ld: -r
> +#objdump: -Dr
> +
> +#...
> +.*R_LARCH_ALIGN.*
> +#...
> +.*R_LARCH_ALIGN.*
> +#...
> diff --git a/ld/testsuite/ld-loongarch-elf/relax-align-ld-r.s b/ld/testsuite/ld-loongarch-elf/relax-align-ld-r.s
> new file mode 100644
> index 00000000000..19555a7148e
> --- /dev/null
> +++ b/ld/testsuite/ld-loongarch-elf/relax-align-ld-r.s
> @@ -0,0 +1,12 @@
> +# Add an align section before text section when ld -r.
> +# There will be two R_LARCH_ALIGN relocations after ld -r.
> +.text
> +  addi.d $a0, $a0, 1
> +  call36 func
> +  .align 3
> +func:
> +  addi.d $a0, $a0, 1
> +
> +# Only add a align section for code section.
> +.data
> +  .4byte 0x1234
> diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp
> index 7c32a65244c..066f1893042 100644
> --- a/ld/testsuite/ld-loongarch-elf/relax.exp
> +++ b/ld/testsuite/ld-loongarch-elf/relax.exp
> @@ -46,6 +46,10 @@ proc run_partial_linking_align_test {} {
>     }
>   }
>   
> +if [istarget loongarch*-*-*] {
> +  run_dump_test "relax-align-ld-r"
> +}
> +
>   if [istarget loongarch64-*-*] {
>     if [isbuild loongarch64-*-*] {
>       run_dump_test "relax-align-ignore-start"
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From ro@CeBiTec.Uni-Bielefeld.DE  Mon Jun  8 08:57:08 2026
From: ro@CeBiTec.Uni-Bielefeld.DE (Rainer Orth)
Date: Mon, 08 Jun 2026 10:57:08 +0200
Subject: Issues with Solaris buildbots
Message-ID: <yddldcppfyz.fsf@CeBiTec.Uni-Bielefeld.DE>

I've now set up 4 Solaris binutils buildbots for 32 and 64-bit
Solaris/SPARC and x86.  There are two issues that cause the bots to be red:

* The gprof tests FAIL as described in

	PR gprof/34237
        gprof tests FAIL on Solaris

  This went unnoticed before because this testsuite alone doesn't use
  DejaGnu.

  I suspect this is due to Solaris still using the original BSD gmon.out
  format.  If so, the test scripts could expect that line, similarly to
  the powerpc special case.

* Recently, the new pr29655 test FAILs on SPARC:

	PR ld/34151
        pr29655 FAILs on SPARC

  Fixing this seems to be quite involved.  I wonder if we could just
  xfail the test for now so the bots are actually useful.

Comments?

	Rainer

-- 
-----------------------------------------------------------------------------
Rainer Orth, Center for Biotechnology, Bielefeld University

From jiawei@iscas.ac.cn  Mon Jun  8 12:28:14 2026
From: jiawei@iscas.ac.cn (Jiawei)
Date: Mon, 8 Jun 2026 20:28:14 +0800
Subject: [PATCH v2 18/16] RISC-V: warn about non-power-of-2 stack-align
 attribute
In-Reply-To: <c47d3248-b5e3-4c60-9c87-0d5c7705a8d6@suse.com>
References: <c32643f7-c8b2-4a0e-9eeb-4ba00369b147@suse.com>
 <f6c4fecf-57ff-4510-8a02-fca12ba22b75@suse.com>
 <c47d3248-b5e3-4c60-9c87-0d5c7705a8d6@suse.com>
Message-ID: <ab1b26f0-26a3-4124-8561-0396eae0be44@iscas.ac.cn>

LGTM.

At 2026/6/5 17:29, Jan Beulich wrote:
> Only power-of-2 values are sensible for alignment.
> ---
> Should libbfd's riscv_merge_attributes() also emit a warning?
>
> Should we reject changing an already set non-zero value, like
> riscv_merge_attributes() does?
>
> Should we permit 0 as an explicit indication of "attribute not set"?
> ---
> v2: New.

Warning for non-power-of-2 stack_align values looks right to me.? I also 
think
explicit stack_align = 0 should be warned about; if the attribute is 
meant to
be unset, it should be omitted rather than emitted with a zero value.

For the follow-up questions, I think libbfd should probably diagnose invalid
stack_align values too, and repeated changes of an already set non-zero 
value
should at least warn, since the linker treats different non-zero stack
alignment requirements as incompatible.
>
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -5891,6 +5891,13 @@ s_riscv_attribute (int ignored ATTRIBUTE
>   		   "any instructions"));
>         break;
>   
> +    case Tag_RISCV_stack_align:
> +      if (!attr[Tag_RISCV_stack_align].i
> +	  || (attr[Tag_RISCV_stack_align].i &
> +	      (attr[Tag_RISCV_stack_align].i - 1)))
> +	as_warn (_("`stack_align' attribute with non-power-of-2 value"));
> +      break;
> +
>       case Tag_RISCV_unaligned_access:
>         if (attr[Tag_RISCV_unaligned_access].i > 1)
>   	as_warn (_("`unaligned_access' attribute with non-boolean value"));
> --- a/gas/testsuite/gas/riscv/attribute-warn.d
> +++ b/gas/testsuite/gas/riscv/attribute-warn.d
> @@ -4,4 +4,5 @@
>   
>   Attribute Section: riscv
>   File Attributes
> +  Tag_RISCV_stack_align: 65536-bytes
>     Tag_RISCV_arch: [a-zA-Z0-9_\"].*
> --- a/gas/testsuite/gas/riscv/attribute-warn.l
> +++ b/gas/testsuite/gas/riscv/attribute-warn.l
> @@ -1,2 +1,4 @@
>   .*: Assembler messages:
>   .*:2: Warning: `unaligned_access' attribute with non-boolean value
> +.*:5: Warning: `stack_align' attribute with non-power-of-2 value
> +.*:6: Warning: `stack_align' attribute with non-power-of-2 value
> --- a/gas/testsuite/gas/riscv/attribute-warn.s
> +++ b/gas/testsuite/gas/riscv/attribute-warn.s
> @@ -1,3 +1,7 @@
>   	.attribute unaligned_access, 1
>   	.attribute unaligned_access, 0x1234
>   	.attribute unaligned_access, 0
> +
> +	.attribute stack_align, 0
> +	.attribute stack_align, 0x4444
> +	.attribute stack_align, 0x10000
Reviewed-by: Jiawei <jiawei@iscas.ac.cn>


From jiawei@iscas.ac.cn  Mon Jun  8 12:45:48 2026
From: jiawei@iscas.ac.cn (Jiawei)
Date: Mon, 8 Jun 2026 20:45:48 +0800
Subject: [PATCH v2 19/16] RISC-V: check operands for Zqinx
In-Reply-To: <dc1fac23-a06d-4353-8e3d-1e66fb18946d@suse.com>
References: <c32643f7-c8b2-4a0e-9eeb-4ba00369b147@suse.com>
 <f6c4fecf-57ff-4510-8a02-fca12ba22b75@suse.com>
 <dc1fac23-a06d-4353-8e3d-1e66fb18946d@suse.com>
Message-ID: <89e17397-e791-4d97-a7b1-b5948c63c102@iscas.ac.cn>

LGTM.

At 2026/6/5 17:30, Jan Beulich wrote:
> By analogy to Zdinx on RV32, register pair operands are presumably (there
> not being any formal spec afaict) required to be encoded with the low bit
> clear in RV64; in RV32 the low two bits need to be clear. Since match
> functions don't have XLEN available, introduce respective flags, to be
> used explicitly in assembler and disassembler.
> ---
> Does Zqinx actually make much sense in RV32? Function argument passing,
> for example, ends up odd: a0..a3 aren't suitable to hold an argument.
> Hence only a single argument can be passed in registers (a2..a5).
>
> No similar checking is easily possible for scalar vector insns, as element
> width there isn't encoded in the insn. (Plus V and Zqinx can't be enabled
> together right now anyway.)
> ---
> v2: New.

There may be some niche use cases in embedded systems, but I do not have
strong evidence that Zqinx is widely used.

Given the lack of a formal specification, I agree that we should be
conservative here. If binutils continues to recognize Zqinx, then the
operand checks should at least be consistent with the natural register
grouping rules. Otherwise, treating Zqinx support as incomplete and avoiding
further assumptions also sounds reasonable to me.

One small typo nit in riscv.h comment:

 ? ? divisble -> divisible

Best regard,

Jiawei

>
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -2934,6 +2934,12 @@ riscv_ip (char *str, struct riscv_cl_ins
>      || (rclass) != RCLASS_GPR                     \
>      || !((regno) & 1))
>   
> +#define RV64_EVEN_CHECK(form, rclass, regno)     \
> +  (!(ip->insn_mo->pinfo & INSN_RV64_EVEN_##form) \
> +   || xlen > 64                                  \
> +   || (rclass) != RCLASS_GPR                     \
> +   || !((regno) & (xlen == 32 ? 3 : 1)))
> +
>         for (oparg = insn->args;; ++oparg)
>   	{
>   	  opargStart = oparg;
> @@ -3593,12 +3599,14 @@ riscv_ip (char *str, struct riscv_cl_ins
>   		  switch (c)
>   		    {
>   		    case 'D':
> -		      if (!RV32_EVEN_CHECK (D, rclass, regno))
> +		      if (!RV32_EVEN_CHECK (D, rclass, regno)
> +			  || !RV64_EVEN_CHECK (D, rclass, regno))
>   			break;
>   		      INSERT_OPERAND (RD, *ip, regno);
>   		      continue;
>   		    case 'S':
> -		      if (!RV32_EVEN_CHECK (S, rclass, regno))
> +		      if (!RV32_EVEN_CHECK (S, rclass, regno)
> +			  || !RV64_EVEN_CHECK (S, rclass, regno))
>   			break;
>   		      INSERT_OPERAND (RS1, *ip, regno);
>   		      continue;
> @@ -3606,12 +3614,14 @@ riscv_ip (char *str, struct riscv_cl_ins
>   		      INSERT_OPERAND (RS1, *ip, regno);
>   		      /* Fall through.  */
>   		    case 'T':
> -		      if (!RV32_EVEN_CHECK (T, rclass, regno))
> +		      if (!RV32_EVEN_CHECK (T, rclass, regno)
> +			  || !RV64_EVEN_CHECK (T, rclass, regno))
>   			break;
>   		      INSERT_OPERAND (RS2, *ip, regno);
>   		      continue;
>   		    case 'R':
> -		      if (!RV32_EVEN_CHECK (R, rclass, regno))
> +		      if (!RV32_EVEN_CHECK (R, rclass, regno)
> +			  || !RV64_EVEN_CHECK (R, rclass, regno))
>   			break;
>   		      INSERT_OPERAND (RS3, *ip, regno);
>   		      continue;
> @@ -4312,6 +4322,7 @@ riscv_ip (char *str, struct riscv_cl_ins
>       }
>   
>   #undef RV32_EVEN_CHECK
> +#undef RV64_EVEN_CHECK
>   
>    out:
>     /* Restore the character we might have clobbered above.  */
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zqinx-rv32.d
> @@ -0,0 +1,52 @@
> +#as: -march=rv32i_zqinx
> +#objdump: -dwr
> +
> +.*:[ 	]+file format .*
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ 	]+[0-9a-f]+:[ 	]+078a7453[ 	]+fadd\.q[ 	]+s0,s4,s8
> +[ 	]+[0-9a-f]+:[ 	]+078a0453[ 	]+fadd\.q[ 	]+s0,s4,s8,rne
> +[ 	]+[0-9a-f]+:[ 	]+0f8a7453[ 	]+fsub\.q[ 	]+s0,s4,s8
> +[ 	]+[0-9a-f]+:[ 	]+0f8a0453[ 	]+fsub\.q[ 	]+s0,s4,s8,rne
> +[ 	]+[0-9a-f]+:[ 	]+178a7453[ 	]+fmul\.q[ 	]+s0,s4,s8
> +[ 	]+[0-9a-f]+:[ 	]+178a0453[ 	]+fmul\.q[ 	]+s0,s4,s8,rne
> +[ 	]+[0-9a-f]+:[ 	]+1f8a7453[ 	]+fdiv\.q[ 	]+s0,s4,s8
> +[ 	]+[0-9a-f]+:[ 	]+1f8a0453[ 	]+fdiv\.q[ 	]+s0,s4,s8,rne
> +[ 	]+[0-9a-f]+:[ 	]+5e0a7453[ 	]+fsqrt\.q[ 	]+s0,s4
> +[ 	]+[0-9a-f]+:[ 	]+5e0a0453[ 	]+fsqrt\.q[ 	]+s0,s4,rne
> +[ 	]+[0-9a-f]+:[ 	]+2f8a0453[ 	]+fmin\.q[ 	]+s0,s4,s8
> +[ 	]+[0-9a-f]+:[ 	]+2f8a1453[ 	]+fmax\.q[ 	]+s0,s4,s8
> +[ 	]+[0-9a-f]+:[ 	]+678a7443[ 	]+fmadd\.q[ 	]+s0,s4,s8,a2
> +[ 	]+[0-9a-f]+:[ 	]+678a0443[ 	]+fmadd\.q[ 	]+s0,s4,s8,a2,rne
> +[ 	]+[0-9a-f]+:[ 	]+678a744f[ 	]+fnmadd\.q[ 	]+s0,s4,s8,a2
> +[ 	]+[0-9a-f]+:[ 	]+678a044f[ 	]+fnmadd\.q[ 	]+s0,s4,s8,a2,rne
> +[ 	]+[0-9a-f]+:[ 	]+678a7447[ 	]+fmsub\.q[ 	]+s0,s4,s8,a2
> +[ 	]+[0-9a-f]+:[ 	]+678a0447[ 	]+fmsub\.q[ 	]+s0,s4,s8,a2,rne
> +[ 	]+[0-9a-f]+:[ 	]+678a744b[ 	]+fnmsub\.q[ 	]+s0,s4,s8,a2
> +[ 	]+[0-9a-f]+:[ 	]+678a044b[ 	]+fnmsub\.q[ 	]+s0,s4,s8,a2,rne
> +[ 	]+[0-9a-f]+:[ 	]+c60a75d3[ 	]+fcvt\.w\.q[ 	]+a1,s4
> +[ 	]+[0-9a-f]+:[ 	]+c60a05d3[ 	]+fcvt\.w\.q[ 	]+a1,s4,rne
> +[ 	]+[0-9a-f]+:[ 	]+c61a75d3[ 	]+fcvt\.wu\.q[ 	]+a1,s4
> +[ 	]+[0-9a-f]+:[ 	]+c61a05d3[ 	]+fcvt\.wu\.q[ 	]+a1,s4,rne
> +[ 	]+[0-9a-f]+:[ 	]+d6058453[ 	]+fcvt\.q\.w[ 	]+s0,a1
> +[ 	]+[0-9a-f]+:[ 	]+d6158453[ 	]+fcvt\.q\.wu[ 	]+s0,a1
> +[ 	]+[0-9a-f]+:[ 	]+46058453[ 	]+fcvt\.q\.s[ 	]+s0,a1
> +[ 	]+[0-9a-f]+:[ 	]+403a75d3[ 	]+fcvt\.s\.q[ 	]+a1,s4
> +[ 	]+[0-9a-f]+:[ 	]+403a05d3[ 	]+fcvt\.s\.q[ 	]+a1,s4,rne
> +[ 	]+[0-9a-f]+:[ 	]+46150453[ 	]+fcvt\.q\.d[ 	]+s0,a0
> +[ 	]+[0-9a-f]+:[ 	]+423a7553[ 	]+fcvt\.d\.q[ 	]+a0,s4
> +[ 	]+[0-9a-f]+:[ 	]+423a0553[ 	]+fcvt\.d\.q[ 	]+a0,s4,rne
> +[ 	]+[0-9a-f]+:[ 	]+46258453[ 	]+fcvt\.q\.h[ 	]+s0,a1
> +[ 	]+[0-9a-f]+:[ 	]+443a75d3[ 	]+fcvt\.h\.q[ 	]+a1,s4
> +[ 	]+[0-9a-f]+:[ 	]+443a05d3[ 	]+fcvt\.h\.q[ 	]+a1,s4,rne
> +[ 	]+[0-9a-f]+:[ 	]+278a0453[ 	]+fsgnj\.q[ 	]+s0,s4,s8
> +[ 	]+[0-9a-f]+:[ 	]+278a1453[ 	]+fsgnjn\.q[ 	]+s0,s4,s8
> +[ 	]+[0-9a-f]+:[ 	]+278a2453[ 	]+fsgnjx\.q[ 	]+s0,s4,s8
> +[ 	]+[0-9a-f]+:[ 	]+a78a25d3[ 	]+feq\.q[ 	]+a1,s4,s8
> +[ 	]+[0-9a-f]+:[ 	]+a78a15d3[ 	]+flt\.q[ 	]+a1,s4,s8
> +[ 	]+[0-9a-f]+:[ 	]+a78a05d3[ 	]+fle\.q[ 	]+a1,s4,s8
> +[ 	]+[0-9a-f]+:[ 	]+a74c15d3[ 	]+flt\.q[ 	]+a1,s8,s4
> +[ 	]+[0-9a-f]+:[ 	]+a74c05d3[ 	]+fle\.q[ 	]+a1,s8,s4
> +[ 	]+[0-9a-f]+:[ 	]+274a0453[ 	]+fmv\.q[ 	]+s0,s4
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zqinx-rv32.s
> @@ -0,0 +1,54 @@
> +target:
> +	fadd.q		s0, s4, s8
> +	fadd.q		s0, s4, s8, rne
> +	fsub.q		s0, s4, s8
> +	fsub.q		s0, s4, s8, rne
> +	fmul.q		s0, s4, s8
> +	fmul.q		s0, s4, s8, rne
> +	fdiv.q		s0, s4, s8
> +	fdiv.q		s0, s4, s8, rne
> +	fsqrt.q		s0, s4
> +	fsqrt.q		s0, s4, rne
> +	fmin.q		s0, s4, s8
> +	fmax.q		s0, s4, s8
> +	fmadd.q		s0, s4, s8, a2
> +	fmadd.q		s0, s4, s8, a2, rne
> +	fnmadd.q	s0, s4, s8, a2
> +	fnmadd.q	s0, s4, s8, a2, rne
> +	fmsub.q		s0, s4, s8, a2
> +	fmsub.q		s0, s4, s8, a2, rne
> +	fnmsub.q	s0, s4, s8, a2
> +	fnmsub.q	s0, s4, s8, a2, rne
> +
> +	fcvt.w.q	a1, s4
> +	fcvt.w.q	a1, s4, rne
> +	fcvt.wu.q	a1, s4
> +	fcvt.wu.q	a1, s4, rne
> +	fcvt.q.w	s0, a1
> +	fcvt.q.wu	s0, a1
> +
> +	fcvt.q.s	s0, a1
> +	fcvt.s.q	a1, s4
> +	fcvt.s.q	a1, s4, rne
> +
> +	fcvt.q.d	s0, a0
> +	fcvt.d.q	a0, s4
> +	fcvt.d.q	a0, s4, rne
> +
> +	.option push
> +	.option arch, +zhinxmin
> +	fcvt.q.h	s0, a1
> +	fcvt.h.q	a1, s4
> +	fcvt.h.q	a1, s4, rne
> +	.option pop
> +
> +	fsgnj.q		s0, s4, s8
> +	fsgnjn.q	s0, s4, s8
> +	fsgnjx.q	s0, s4, s8
> +	feq.q		a1, s4, s8
> +	flt.q		a1, s4, s8
> +	fle.q		a1, s4, s8
> +	fgt.q		a1, s4, s8
> +	fge.q		a1, s4, s8
> +
> +	fmv.q		s0, s4
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zqinx-rv32-fail.d
> @@ -0,0 +1,3 @@
> +#as: -march=rv32i_zqinx
> +#source: zqinx.s
> +#error_output: zqinx-rv32-fail.l
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zqinx-rv32-fail.l
> @@ -0,0 +1,42 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `fadd\.q .*'
> +.*: Error: illegal operands `fadd\.q .*'
> +.*: Error: illegal operands `fsub\.q .*'
> +.*: Error: illegal operands `fsub\.q .*'
> +.*: Error: illegal operands `fmul\.q .*'
> +.*: Error: illegal operands `fmul\.q .*'
> +.*: Error: illegal operands `fdiv\.q .*'
> +.*: Error: illegal operands `fdiv\.q .*'
> +.*: Error: illegal operands `fsqrt\.q .*'
> +.*: Error: illegal operands `fsqrt\.q .*'
> +.*: Error: illegal operands `fmin\.q .*'
> +.*: Error: illegal operands `fmax\.q .*'
> +.*: Error: illegal operands `fmadd\.q .*'
> +.*: Error: illegal operands `fmadd\.q .*'
> +.*: Error: illegal operands `fnmadd\.q .*'
> +.*: Error: illegal operands `fnmadd\.q .*'
> +.*: Error: illegal operands `fmsub\.q .*'
> +.*: Error: illegal operands `fmsub\.q .*'
> +.*: Error: illegal operands `fnmsub\.q .*'
> +.*: Error: illegal operands `fnmsub\.q .*'
> +.*: Error: unrecognized opcode `fcvt\.l\.q .*'
> +.*: Error: unrecognized opcode `fcvt\.l\.q .*'
> +.*: Error: unrecognized opcode `fcvt\.lu\.q .*'
> +.*: Error: unrecognized opcode `fcvt\.lu\.q .*'
> +.*: Error: illegal operands `fcvt\.q\.w .*'
> +.*: Error: illegal operands `fcvt\.q\.wu .*'
> +.*: Error: unrecognized opcode `fcvt\.q\.l .*'
> +.*: Error: unrecognized opcode `fcvt\.q\.lu .*'
> +.*: Error: illegal operands `fcvt\.q\.s .*'
> +.*: Error: illegal operands `fcvt\.q\.d .*'
> +.*: Error: illegal operands `fsgnj\.q .*'
> +.*: Error: illegal operands `fsgnjn\.q .*'
> +.*: Error: illegal operands `fsgnjx\.q .*'
> +.*: Error: illegal operands `feq\.q .*'
> +.*: Error: illegal operands `flt\.q .*'
> +.*: Error: illegal operands `fle\.q .*'
> +.*: Error: illegal operands `fgt\.q .*'
> +.*: Error: illegal operands `fge\.q .*'
> +.*: Error: illegal operands `fmv\.q .*'
> +.*: Error: illegal operands `fneg\.q .*'
> +.*: Error: illegal operands `fabs\.q .*'
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zqinx-rv64-fail.d
> @@ -0,0 +1,2 @@
> +#as: -march=rv64i_zqinx
> +#error_output: zqinx-rv64-fail.l
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zqinx-rv64-fail.l
> @@ -0,0 +1,62 @@
> +.*: Assembler messages:
> +.*: Error: illegal operands `fadd\.q .*'
> +.*: Error: illegal operands `fadd\.q .*'
> +.*: Error: illegal operands `fadd\.q .*'
> +.*: Error: illegal operands `fsub\.q .*'
> +.*: Error: illegal operands `fsub\.q .*'
> +.*: Error: illegal operands `fsub\.q .*'
> +.*: Error: illegal operands `fmul\.q .*'
> +.*: Error: illegal operands `fmul\.q .*'
> +.*: Error: illegal operands `fmul\.q .*'
> +.*: Error: illegal operands `fdiv\.q .*'
> +.*: Error: illegal operands `fdiv\.q .*'
> +.*: Error: illegal operands `fdiv\.q .*'
> +.*: Error: illegal operands `fsqrt\.q .*'
> +.*: Error: illegal operands `fsqrt\.q .*'
> +.*: Error: illegal operands `fmin\.q .*'
> +.*: Error: illegal operands `fmin\.q .*'
> +.*: Error: illegal operands `fmin\.q .*'
> +.*: Error: illegal operands `fmax\.q .*'
> +.*: Error: illegal operands `fmax\.q .*'
> +.*: Error: illegal operands `fmax\.q .*'
> +.*: Error: illegal operands `fmadd\.q .*'
> +.*: Error: illegal operands `fmadd\.q .*'
> +.*: Error: illegal operands `fmadd\.q .*'
> +.*: Error: illegal operands `fmadd\.q .*'
> +.*: Error: illegal operands `fnmadd\.q .*'
> +.*: Error: illegal operands `fnmadd\.q .*'
> +.*: Error: illegal operands `fnmadd\.q .*'
> +.*: Error: illegal operands `fnmadd\.q .*'
> +.*: Error: illegal operands `fmsub\.q .*'
> +.*: Error: illegal operands `fmsub\.q .*'
> +.*: Error: illegal operands `fmsub\.q .*'
> +.*: Error: illegal operands `fmsub\.q .*'
> +.*: Error: illegal operands `fnmsub\.q .*'
> +.*: Error: illegal operands `fnmsub\.q .*'
> +.*: Error: illegal operands `fnmsub\.q .*'
> +.*: Error: illegal operands `fnmsub\.q .*'
> +.*: Error: illegal operands `fcvt\.w\.q .*'
> +.*: Error: illegal operands `fcvt\.wu\.q .*'
> +.*: Error: illegal operands `fcvt\.q\.w .*'
> +.*: Error: illegal operands `fcvt\.q\.wu .*'
> +.*: Error: illegal operands `fcvt\.q\.s .*'
> +.*: Error: illegal operands `fcvt\.s\.q .*'
> +.*: Error: illegal operands `fcvt\.q\.d .*'
> +.*: Error: illegal operands `fcvt\.d\.q .*'
> +.*: Error: illegal operands `fcvt\.q\.h .*'
> +.*: Error: illegal operands `fcvt\.h\.q .*'
> +.*: Error: illegal operands `fsgnj\.q .*'
> +.*: Error: illegal operands `fsgnjn\.q .*'
> +.*: Error: illegal operands `fsgnjx\.q .*'
> +.*: Error: illegal operands `feq\.q .*'
> +.*: Error: illegal operands `flt\.q .*'
> +.*: Error: illegal operands `fle\.q .*'
> +.*: Error: illegal operands `fgt\.q .*'
> +.*: Error: illegal operands `fge\.q .*'
> +.*: Error: illegal operands `fmv\.q .*'
> +.*: Error: illegal operands `fmv\.q .*'
> +.*: Error: illegal operands `fneg\.q .*'
> +.*: Error: illegal operands `fneg\.q .*'
> +.*: Error: illegal operands `fabs\.q .*'
> +.*: Error: illegal operands `fabs\.q .*'
> +.*: Error: illegal operands `fclass\.q .*'
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zqinx-rv64-fail.s
> @@ -0,0 +1,70 @@
> +target:
> +	fadd.q		s1, s4, s8
> +	fadd.q		s0, s5, s8
> +	fadd.q		s0, s4, s9
> +	fsub.q		s1, s4, s8
> +	fsub.q		s0, s5, s8
> +	fsub.q		s0, s4, s9
> +	fmul.q		s1, s4, s8
> +	fmul.q		s0, s5, s8
> +	fmul.q		s0, s4, s9
> +	fdiv.q		s1, s4, s8
> +	fdiv.q		s0, s5, s8
> +	fdiv.q		s0, s4, s9
> +	fsqrt.q		s1, s4
> +	fsqrt.q		s0, s5
> +	fmin.q		s1, s4, s8
> +	fmin.q		s0, s5, s8
> +	fmin.q		s0, s4, s9
> +	fmax.q		s1, s4, s8
> +	fmax.q		s0, s5, s8
> +	fmax.q		s0, s4, s9
> +	fmadd.q		s1, s4, s8, a2
> +	fmadd.q		s0, s5, s8, a2
> +	fmadd.q		s0, s4, s9, a2
> +	fmadd.q		s0, s4, s8, a3
> +	fnmadd.q	s1, s4, s8, a2
> +	fnmadd.q	s0, s5, s8, a2
> +	fnmadd.q	s0, s4, s9, a2
> +	fnmadd.q	s0, s4, s8, a3
> +	fmsub.q		s1, s4, s8, a2
> +	fmsub.q		s0, s5, s8, a2
> +	fmsub.q		s0, s4, s9, a2
> +	fmsub.q		s0, s4, s8, a3
> +	fnmsub.q	s1, s4, s8, a2
> +	fnmsub.q	s0, s5, s8, a2
> +	fnmsub.q	s0, s4, s9, a2
> +	fnmsub.q	s0, s4, s8, a3
> +
> +	fcvt.w.q	a0, s5
> +	fcvt.wu.q	a0, s5
> +	fcvt.q.w	s1, a0
> +	fcvt.q.wu	s1, a0
> +
> +	fcvt.q.s	s1, a0
> +	fcvt.s.q	a0, s5
> +
> +	fcvt.q.d	s1, a0
> +	fcvt.d.q	a0, s5
> +
> +	.option push
> +	.option arch, +zhinxmin
> +	fcvt.q.h	s1, a0
> +	fcvt.h.q	a0, s5
> +	.option pop
> +
> +	fsgnj.q		s1, s4, s8
> +	fsgnjn.q	s0, s5, s8
> +	fsgnjx.q	s0, s4, s9
> +	feq.q		a0, s5, s8
> +	flt.q		a0, s4, s9
> +	fle.q		a0, s5, s8
> +	fgt.q		a0, s4, s9
> +	fge.q		a0, s5, s8
> +	fmv.q		s1, s4
> +	fmv.q		s0, s5
> +	fneg.q		s1, s4
> +	fneg.q		s0, s5
> +	fabs.q		s1, s4
> +	fabs.q		s0, s5
> +	fclass.q	a0, s5
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -691,6 +691,19 @@ struct riscv_opcode
>   #define INSN_RV32_EVEN_DU	(INSN_RV32_EVEN_D   | INSN_RV32_EVEN_T)
>   #define INSN_RV32_EVEN_ST	(INSN_RV32_EVEN_S   | INSN_RV32_EVEN_T)
>   
> +/* Operands required to be an even-numbered register (pair) in RV64, and one
> +   divisble by 4 on RV32.  */
> +#define INSN_RV64_EVEN_D	0x00001000
> +#define INSN_RV64_EVEN_S	0x00002000
> +#define INSN_RV64_EVEN_T	0x00004000 /* Also covering U.  */
> +#define INSN_RV64_EVEN_R	0x00008000
> +/* Shorthands for combinations of the above.  */
> +#define INSN_RV64_EVEN_DS	(INSN_RV64_EVEN_D   | INSN_RV64_EVEN_S)
> +#define INSN_RV64_EVEN_DST	(INSN_RV64_EVEN_DS  | INSN_RV64_EVEN_T)
> +#define INSN_RV64_EVEN_DSTR	(INSN_RV64_EVEN_DST | INSN_RV64_EVEN_R)
> +#define INSN_RV64_EVEN_DU	(INSN_RV64_EVEN_D   | INSN_RV64_EVEN_T)
> +#define INSN_RV64_EVEN_ST	(INSN_RV64_EVEN_S   | INSN_RV64_EVEN_T)
> +
>   /* Instruction is actually a macro.  It should be ignored by the
>      disassembler, and requires special treatment by the assembler.  */
>   #define INSN_MACRO		0xffffffff
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -1049,6 +1049,25 @@ riscv_disassemble_insn (bfd_vma memaddr,
>   		      && (word & (1u << OP_SH_RS3)))
>   		    continue;
>   		}
> +
> +	      if (pd->xlen <= 64
> +		  && riscv_subset_supports (&pd->riscv_rps_dis, "zqinx"))
> +		{
> +		  unsigned int mask = pd->xlen == 32 ? 3 : 1;
> +
> +		  if ((op->pinfo & INSN_RV64_EVEN_D)
> +		      && (word & (mask << OP_SH_RD)))
> +		    continue;
> +		  if ((op->pinfo & INSN_RV64_EVEN_S)
> +		      && (word & (mask << OP_SH_RS1)))
> +		    continue;
> +		  if ((op->pinfo & INSN_RV64_EVEN_T)
> +		      && (word & (mask << OP_SH_RS2)))
> +		    continue;
> +		  if ((op->pinfo & INSN_RV64_EVEN_R)
> +		      && (word & (mask << OP_SH_RS3)))
> +		    continue;
> +		}
>   	    }
>   
>   	  /* It's a match.  */
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -932,10 +932,10 @@ const struct riscv_opcode riscv_opcodes[
>   {"fcvt.h.wu",  0, INSN_CLASS_ZFH_INX,  "D,sm",      MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 },
>   {"fcvt.s.h",   0, INSN_CLASS_ZFHMIN_INX, "D,S",     MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 },
>   {"fcvt.d.h",   0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,S", MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, INSN_RV32_EVEN_D },
> -{"fcvt.q.h",   0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 },
> +{"fcvt.q.h",   0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, INSN_RV64_EVEN_D },
>   {"fcvt.h.s",   0, INSN_CLASS_ZFHMIN_INX, "D,Sm",    MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 },
>   {"fcvt.h.d",   0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,Sm", MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, INSN_RV32_EVEN_S },
> -{"fcvt.h.q",   0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,Sm", MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 },
> +{"fcvt.h.q",   0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,Sm", MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, INSN_RV64_EVEN_S },
>   {"fclass.h",   0, INSN_CLASS_ZFH_INX,   "d,S",       MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 },
>   {"feq.h",      0, INSN_CLASS_ZFH_INX,   "d,S,T",     MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 },
>   {"flt.h",      0, INSN_CLASS_ZFH_INX,   "d,S,T",     MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
> @@ -1062,41 +1062,41 @@ const struct riscv_opcode riscv_opcodes[
>   {"flq",        0, INSN_CLASS_Q,   "D,A,s",     0, (int) M_FLx, match_rs1_nonzero, INSN_MACRO },
>   {"fsq",        0, INSN_CLASS_Q,   "T,q(s)",    MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE },
>   {"fsq",        0, INSN_CLASS_Q,   "T,A,s",     0, (int) M_Sx_FSx, match_rs1_nonzero, INSN_MACRO },
> -{"fmv.q",      0, INSN_CLASS_Q_INX,   "D,U",       MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS },
> -{"fneg.q",     0, INSN_CLASS_Q_INX,   "D,U",       MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS },
> -{"fabs.q",     0, INSN_CLASS_Q_INX,   "D,U",       MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS },
> -{"fsgnj.q",    0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 },
> -{"fsgnjn.q",   0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 },
> -{"fsgnjx.q",   0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 },
> -{"fadd.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 },
> -{"fsub.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 },
> -{"fmul.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 },
> -{"fdiv.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 },
> -{"fsqrt.q",    0, INSN_CLASS_Q_INX,   "D,Sm",      MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 },
> -{"fmin.q",     0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 },
> -{"fmax.q",     0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 },
> -{"fmadd.q",    0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 },
> -{"fnmadd.q",   0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 },
> -{"fmsub.q",    0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 },
> -{"fnmsub.q",   0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 },
> -{"fcvt.w.q",   0, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 },
> -{"fcvt.wu.q",  0, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 },
> -{"fcvt.q.w",   0, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 },
> -{"fcvt.q.wu",  0, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 },
> -{"fcvt.q.s",   0, INSN_CLASS_Q_INX,   "D,S",       MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 },
> -{"fcvt.q.d",   0, INSN_CLASS_Q_INX,   "D,S",       MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 },
> -{"fcvt.s.q",   0, INSN_CLASS_Q_INX,   "D,Sm",      MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 },
> -{"fcvt.d.q",   0, INSN_CLASS_Q_INX,   "D,Sm",      MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 },
> -{"fclass.q",   0, INSN_CLASS_Q_INX,   "d,S",       MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 },
> -{"feq.q",      0, INSN_CLASS_Q_INX,   "d,S,T",     MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 },
> -{"flt.q",      0, INSN_CLASS_Q_INX,   "d,S,T",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
> -{"fle.q",      0, INSN_CLASS_Q_INX,   "d,S,T",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
> -{"fgt.q",      0, INSN_CLASS_Q_INX,   "d,T,S",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_ALIAS },
> -{"fge.q",      0, INSN_CLASS_Q_INX,   "d,T,S",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_ALIAS },
> -{"fcvt.l.q",  64, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 },
> -{"fcvt.lu.q", 64, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 },
> -{"fcvt.q.l",  64, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
> -{"fcvt.q.lu", 64, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 },
> +{"fmv.q",      0, INSN_CLASS_Q_INX,   "D,U",       MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_RV64_EVEN_DU },
> +{"fneg.q",     0, INSN_CLASS_Q_INX,   "D,U",       MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_RV64_EVEN_DU },
> +{"fabs.q",     0, INSN_CLASS_Q_INX,   "D,U",       MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_RV64_EVEN_DU },
> +{"fsgnj.q",    0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, INSN_RV64_EVEN_DST },
> +{"fsgnjn.q",   0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, INSN_RV64_EVEN_DST },
> +{"fsgnjx.q",   0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, INSN_RV64_EVEN_DST },
> +{"fadd.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FADD_Q, MASK_FADD_Q, match_opcode, INSN_RV64_EVEN_DST },
> +{"fsub.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, INSN_RV64_EVEN_DST },
> +{"fmul.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, INSN_RV64_EVEN_DST },
> +{"fdiv.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, INSN_RV64_EVEN_DST },
> +{"fsqrt.q",    0, INSN_CLASS_Q_INX,   "D,Sm",      MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, INSN_RV64_EVEN_DS },
> +{"fmin.q",     0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, INSN_RV64_EVEN_DST },
> +{"fmax.q",     0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, INSN_RV64_EVEN_DST },
> +{"fmadd.q",    0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, INSN_RV64_EVEN_DSTR },
> +{"fnmadd.q",   0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, INSN_RV64_EVEN_DSTR },
> +{"fmsub.q",    0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, INSN_RV64_EVEN_DSTR },
> +{"fnmsub.q",   0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, INSN_RV64_EVEN_DSTR },
> +{"fcvt.w.q",   0, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, INSN_RV64_EVEN_S },
> +{"fcvt.wu.q",  0, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, INSN_RV64_EVEN_S },
> +{"fcvt.q.w",   0, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, INSN_RV64_EVEN_D },
> +{"fcvt.q.wu",  0, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, INSN_RV64_EVEN_D },
> +{"fcvt.q.s",   0, INSN_CLASS_Q_INX,   "D,S",       MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, INSN_RV64_EVEN_D },
> +{"fcvt.q.d",   0, INSN_CLASS_Q_INX,   "D,S",       MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, INSN_RV64_EVEN_D|INSN_RV32_EVEN_S },
> +{"fcvt.s.q",   0, INSN_CLASS_Q_INX,   "D,Sm",      MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, INSN_RV64_EVEN_S },
> +{"fcvt.d.q",   0, INSN_CLASS_Q_INX,   "D,Sm",      MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, INSN_RV32_EVEN_D|INSN_RV64_EVEN_S },
> +{"fclass.q",   0, INSN_CLASS_Q_INX,   "d,S",       MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, INSN_RV64_EVEN_S },
> +{"feq.q",      0, INSN_CLASS_Q_INX,   "d,S,T",     MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, INSN_RV64_EVEN_ST },
> +{"flt.q",      0, INSN_CLASS_Q_INX,   "d,S,T",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_RV64_EVEN_ST },
> +{"fle.q",      0, INSN_CLASS_Q_INX,   "d,S,T",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_RV64_EVEN_ST },
> +{"fgt.q",      0, INSN_CLASS_Q_INX,   "d,T,S",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_ALIAS|INSN_RV64_EVEN_ST },
> +{"fge.q",      0, INSN_CLASS_Q_INX,   "d,T,S",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_ALIAS|INSN_RV64_EVEN_ST },
> +{"fcvt.l.q",  64, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, INSN_RV64_EVEN_S },
> +{"fcvt.lu.q", 64, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, INSN_RV64_EVEN_S },
> +{"fcvt.q.l",  64, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, INSN_RV64_EVEN_D },
> +{"fcvt.q.lu", 64, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, INSN_RV64_EVEN_D },
>   
>   /* Compressed instructions.  */
>   {"c.unimp",    0, INSN_CLASS_ZCA,   "",          0, 0xffffU,  match_opcode, 0 },


From sivan.shani@arm.com  Mon Jun  8 14:14:13 2026
From: sivan.shani@arm.com (Sivan Shani)
Date: Mon, 8 Jun 2026 14:14:13 +0000
Subject: [PATCH] gas: arm - support CPU-specific extensions with -mcpu
Message-ID: <20260608141413.35735-1-sivan.shani@arm.com>

Add extension tables for -mcpu, similar to -march, allowing
CPU-specific extensions to be enabled and disabled using +ext and
+noext modifiers.

Update ARM CPU feature definitions to match GCC CPU baselines and
add tests covering supported CPU extension modifiers and feature
availability.
---
 gas/config/tc-arm.c                         | 701 +++++++++++++++-----
 gas/testsuite/gas/arm/command-line-mcpu.exp | 134 ++++
 gas/testsuite/gas/arm/feat-bf16.s           |   5 +
 gas/testsuite/gas/arm/feat-crc.s            |   4 +
 gas/testsuite/gas/arm/feat-dotprod.s        |   4 +
 gas/testsuite/gas/arm/feat-dsp.s            |   4 +
 gas/testsuite/gas/arm/feat-fp-vfpv3.s       |   4 +
 gas/testsuite/gas/arm/feat-fp-vfpv5.s       |   4 +
 gas/testsuite/gas/arm/feat-fp.dp.s          |   4 +
 gas/testsuite/gas/arm/feat-fp.s             |   4 +
 gas/testsuite/gas/arm/feat-fp16.s           |   4 +
 gas/testsuite/gas/arm/feat-i8mm.s           |   4 +
 gas/testsuite/gas/arm/feat-idiv.s           |   3 +
 gas/testsuite/gas/arm/feat-mp.s             |   4 +
 gas/testsuite/gas/arm/feat-mve.fp.s         |   5 +
 gas/testsuite/gas/arm/feat-neon-fp16.s      |   4 +
 gas/testsuite/gas/arm/feat-pacbti.s         |   4 +
 gas/testsuite/gas/arm/feat-sec.s            |   4 +
 gas/testsuite/gas/arm/feat-simd.s           |   5 +
 gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s |   4 +
 20 files changed, 754 insertions(+), 155 deletions(-)
 create mode 100644 gas/testsuite/gas/arm/command-line-mcpu.exp
 create mode 100644 gas/testsuite/gas/arm/feat-bf16.s
 create mode 100644 gas/testsuite/gas/arm/feat-crc.s
 create mode 100644 gas/testsuite/gas/arm/feat-dotprod.s
 create mode 100644 gas/testsuite/gas/arm/feat-dsp.s
 create mode 100644 gas/testsuite/gas/arm/feat-fp-vfpv3.s
 create mode 100644 gas/testsuite/gas/arm/feat-fp-vfpv5.s
 create mode 100644 gas/testsuite/gas/arm/feat-fp.dp.s
 create mode 100644 gas/testsuite/gas/arm/feat-fp.s
 create mode 100644 gas/testsuite/gas/arm/feat-fp16.s
 create mode 100644 gas/testsuite/gas/arm/feat-i8mm.s
 create mode 100644 gas/testsuite/gas/arm/feat-idiv.s
 create mode 100644 gas/testsuite/gas/arm/feat-mp.s
 create mode 100644 gas/testsuite/gas/arm/feat-mve.fp.s
 create mode 100644 gas/testsuite/gas/arm/feat-neon-fp16.s
 create mode 100644 gas/testsuite/gas/arm/feat-pacbti.s
 create mode 100644 gas/testsuite/gas/arm/feat-sec.s
 create mode 100644 gas/testsuite/gas/arm/feat-simd.s
 create mode 100644 gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 3ff29542411..8f990a5f14b 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -30495,6 +30495,14 @@ const struct arm_legacy_option_table arm_legacy_opts[] =
   {NULL, NULL, ARM_ARCH_NONE, NULL}
 };
 
+struct arm_ext_table
+{
+  const char *		  name;
+  size_t		  name_len;
+  const arm_feature_set	  merge;
+  const arm_feature_set	  clear;
+};
+
 struct arm_cpu_option_table
 {
   const char *           name;
@@ -30507,11 +30515,353 @@ struct arm_cpu_option_table
   /* The canonical name of the CPU, or NULL to use NAME converted to upper
      case.  */
   const char *           canonical_name;
+  const struct arm_ext_table *	ext_table;
+};
+
+/* Used to add support for +E and +noE extension.  */
+#define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
+/* Used to add support for a +E extension.  */
+#define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
+/* Used to add support for a +noE extension.  */
+#define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
+
+#define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
+			    ~0 & ~FPU_ENDIAN_PURE)
+#define ALL_FP_MVE_FP ARM_FEATURE (0, (ARM_EXT2_FP16_INST		   \
+					| ARM_EXT2_FP16_FML		   \
+					| ARM_EXT2_MVE_FP),		   \
+				    ~0 & ~FPU_ENDIAN_PURE)
+#define ALL_SIMD ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA |     \
+				     FPU_NEON_EXT_ARMV8 | FPU_NEON_EXT_RDMA | \
+				     FPU_NEON_EXT_DOTPROD)
+
+#define CDE_EXTENSIONS \
+  ARM_ADD ("cdecp0", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE0)), \
+  ARM_ADD ("cdecp1", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE1)), \
+  ARM_ADD ("cdecp2", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE2)), \
+  ARM_ADD ("cdecp3", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE3)), \
+  ARM_ADD ("cdecp4", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE4)), \
+  ARM_ADD ("cdecp5", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE5)), \
+  ARM_ADD ("cdecp6", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE6)), \
+  ARM_ADD ("cdecp7", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE7))
+
+/* -mcpu extensions.  */
+static const struct arm_ext_table cortex_a5_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  ARM_REMOVE ("simd", ALL_SIMD),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a7_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  ARM_REMOVE ("simd", ALL_SIMD),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a8_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a9_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  ARM_REMOVE ("simd", ALL_SIMD),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a12_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a15_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a17_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_r5_ext_table[] =
+{
+  ARM_REMOVE ("fp",    ALL_FP),
+  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
+		      | FPU_VFP_EXT_ARMV8)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_r7_ext_table[] =
+{
+  ARM_REMOVE ("fp",    ALL_FP),
+  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
+		      | FPU_VFP_EXT_ARMV8)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_r8_ext_table[] =
+{
+  ARM_REMOVE ("fp",    ALL_FP),
+  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
+		      | FPU_VFP_EXT_ARMV8)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m4_ext_table[] =
+{
+  ARM_REMOVE ("fp",    ALL_FP),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m7_ext_table[] =
+{
+  ARM_REMOVE ("fp",    ALL_FP),
+  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
+		      | FPU_VFP_EXT_ARMV8)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a32_ext_table[] =
+{
+  ARM_REMOVE ("fp",     ALL_FP),
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a35_ext_table[] =
+{
+  ARM_REMOVE ("fp",     ALL_FP),
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a53_ext_table[] =
+{
+  ARM_REMOVE ("fp",     ALL_FP),
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a57_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a72_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a73_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table exynos_m1_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_r52_ext_table[] =
+{
+  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_D32 | FPU_VFP_EXT_ARMV8
+			| FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA
+			| FPU_NEON_EXT_ARMV8 | FPU_NEON_EXT_RDMA
+			| FPU_NEON_EXT_DOTPROD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_r52plus_ext_table[] =
+{
+  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_D32 | FPU_VFP_EXT_ARMV8
+			| FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA
+			| FPU_NEON_EXT_ARMV8 | FPU_NEON_EXT_RDMA
+			| FPU_NEON_EXT_DOTPROD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m33_ext_table[] =
+{
+  ARM_REMOVE ("fp",  ALL_FP),
+  ARM_REMOVE ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m35p_ext_table[] =
+{
+  ARM_REMOVE ("fp",  ALL_FP),
+  ARM_REMOVE ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m52_ext_table[] =
+{
+  ARM_REMOVE ("pacbti", ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI)),
+  ARM_REMOVE ("mve.fp", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP)),
+  ARM_REMOVE ("mve",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+  ARM_REMOVE ("fp",     ALL_FP_MVE_FP),
+  ARM_REMOVE ("dsp",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+  ARM_ADD ("cdecp0",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE0)),
+  ARM_ADD ("cdecp1",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE1)),
+  ARM_ADD ("cdecp2",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE2)),
+  ARM_ADD ("cdecp3",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE3)),
+  ARM_ADD ("cdecp4",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE4)),
+  ARM_ADD ("cdecp5",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE5)),
+  ARM_ADD ("cdecp6",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE6)),
+  ARM_ADD ("cdecp7",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE7)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m55_ext_table[] =
+{
+  ARM_REMOVE ("mve.fp", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP)),
+  ARM_REMOVE ("mve",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+  ARM_REMOVE ("fp",     ALL_FP_MVE_FP),
+  ARM_REMOVE ("dsp",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+  ARM_ADD ("cdecp0",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE0)),
+  ARM_ADD ("cdecp1",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE1)),
+  ARM_ADD ("cdecp2",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE2)),
+  ARM_ADD ("cdecp3",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE3)),
+  ARM_ADD ("cdecp4",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE4)),
+  ARM_ADD ("cdecp5",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE5)),
+  ARM_ADD ("cdecp6",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE6)),
+  ARM_ADD ("cdecp7",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE7)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m85_ext_table[] =
+{
+  ARM_REMOVE ("pacbti", ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI)),
+  ARM_REMOVE ("mve.fp", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP)),
+  ARM_REMOVE ("mve",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+  ARM_REMOVE ("fp",     ALL_FP_MVE_FP),
+  ARM_REMOVE ("dsp",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a55_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a75_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a76_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a76ae_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a77_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a78_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a78ae_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a78c_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_x1_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_x1c_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table neoverse_n1_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table neoverse_v1_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a710_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table neoverse_n2_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
 };
 
 /* This list should, at a minimum, contain all the cpu names
    recognized by GCC.  */
-#define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
+#define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN, NULL }
+#define ARM_CPU_OPT2(N, CN, V, E, DF, ext) \
+  { N, sizeof (N) - 1, V, E, DF, CN, ext##_ext_table }
 
 static const struct arm_cpu_option_table arm_cpus[] =
 {
@@ -30764,113 +31114,162 @@ static const struct arm_cpu_option_table arm_cpus[] =
   ARM_CPU_OPT ("arm1176jzf-s",	  NULL,		       ARM_ARCH_V6KZ,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_VFP_V2),
-  ARM_CPU_OPT ("cortex-a5",	  "Cortex-A5",	       ARM_ARCH_V7A,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
-	       FPU_ARCH_SOFTVFP),
-  ARM_CPU_OPT ("cortex-a7",	  "Cortex-A7",	       ARM_ARCH_V7VE,
-	       ARM_ARCH_NONE,
-	       FPU_ARCH_NEON_VFP_V4),
-  ARM_CPU_OPT ("cortex-a8",	  "Cortex-A8",	       ARM_ARCH_V7A,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
-	       ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
-  ARM_CPU_OPT ("cortex-a9",	  "Cortex-A9",	       ARM_ARCH_V7A,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
-	       ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
-  ARM_CPU_OPT ("cortex-a12",	  "Cortex-A12",	       ARM_ARCH_V7VE,
-	       ARM_ARCH_NONE,
-	       FPU_ARCH_NEON_VFP_V4),
-  ARM_CPU_OPT ("cortex-a15",	  "Cortex-A15",	       ARM_ARCH_V7VE,
-	       ARM_ARCH_NONE,
-	       FPU_ARCH_NEON_VFP_V4),
-  ARM_CPU_OPT ("cortex-a17",	  "Cortex-A17",	       ARM_ARCH_V7VE,
-	       ARM_ARCH_NONE,
-	       FPU_ARCH_NEON_VFP_V4),
-  ARM_CPU_OPT ("cortex-a32",	  "Cortex-A32",	       ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a35",	  "Cortex-A35",	       ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a53",	  "Cortex-A53",	       ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a55",    "Cortex-A55",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
-  ARM_CPU_OPT ("cortex-a57",	  "Cortex-A57",	       ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a72",	  "Cortex-A72",	       ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	      FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a73",	  "Cortex-A73",	       ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	      FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a75",    "Cortex-A75",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
-  ARM_CPU_OPT ("cortex-a76",    "Cortex-A76",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
-  ARM_CPU_OPT ("cortex-a76ae",    "Cortex-A76AE",      ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
-  ARM_CPU_OPT ("cortex-a77",    "Cortex-A77",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
-  ARM_CPU_OPT ("cortex-a78",   "Cortex-A78",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
-	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a78ae",   "Cortex-A78AE",	   ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
-	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a78c",   "Cortex-A78C",	   ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
-	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a710",   "Cortex-A710",	   ARM_ARCH_V9A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
-				    | ARM_EXT2_BF16
-				    | ARM_EXT2_I8MM),
-	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("ares",    "Ares",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
+  ARM_CPU_OPT2 ("cortex-a5",	  "Cortex-A5",	       ARM_ARCH_V7A,
+	       ARM_FEATURE (ARM_EXT_MP | ARM_EXT_SEC,
+	       ARM_EXT2_FP16_INST,
+	       FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA),
+	       FPU_ARCH_NEON_VFP_V4,
+	       cortex_a5),
+  ARM_CPU_OPT2 ("cortex-a7",	  "Cortex-A7",	       ARM_ARCH_V7VE,
+	       ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1 |
+	       FPU_NEON_EXT_FMA),
+	       FPU_ARCH_NEON_VFP_V4,
+	       cortex_a7),
+  ARM_CPU_OPT2 ("cortex-a8",	  "Cortex-A8",	       ARM_ARCH_V7A,
+	       ARM_FEATURE_LOW (ARM_EXT_SEC, FPU_VFP_V3 | FPU_NEON_EXT_V1),
+	       ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1),
+	       cortex_a8),
+  ARM_CPU_OPT2 ("cortex-a9",	  "Cortex-A9",	       ARM_ARCH_V7A,
+	       ARM_FEATURE (ARM_EXT_MP | ARM_EXT_SEC,
+	       ARM_EXT2_FP16_INST,
+	       FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA),
+	       FPU_ARCH_NEON_VFP_V4,
+	       cortex_a9),
+  ARM_CPU_OPT2 ("cortex-a12",	  "Cortex-A12",	       ARM_ARCH_V7VE,
+	       ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1 |
+	       FPU_NEON_EXT_FMA),
+	       FPU_ARCH_NEON_VFP_V4,
+	       cortex_a12),
+  ARM_CPU_OPT2 ("cortex-a15",	  "Cortex-A15",	       ARM_ARCH_V7VE,
+	       ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1 |
+	       FPU_NEON_EXT_FMA),
+	       FPU_ARCH_NEON_VFP_V4,
+	       cortex_a15),
+  ARM_CPU_OPT2 ("cortex-a17",	  "Cortex-A17",	       ARM_ARCH_V7VE,
+	       ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1 |
+	       FPU_NEON_EXT_FMA),
+	       FPU_ARCH_NEON_VFP_V4,
+	       cortex_a17),
+  ARM_CPU_OPT2 ("cortex-a32",	  "Cortex-A32",	       ARM_ARCH_V8A,
+	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+	       FPU_ARCH_NEON_VFP_ARMV8,
+	       cortex_a32),
+  ARM_CPU_OPT2 ("cortex-a35",	  "Cortex-A35",	       ARM_ARCH_V8A,
+	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+	       FPU_ARCH_NEON_VFP_ARMV8,
+	       cortex_a35),
+  ARM_CPU_OPT2 ("cortex-a53",	  "Cortex-A53",	       ARM_ARCH_V8A,
+	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+	       FPU_ARCH_NEON_VFP_ARMV8,
+	       cortex_a53),
+  ARM_CPU_OPT2 ("cortex-a55",    "Cortex-A55",	       ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       cortex_a55),
+  ARM_CPU_OPT2 ("cortex-a57",	  "Cortex-A57",	       ARM_ARCH_V8A,
+	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+	       FPU_ARCH_NEON_VFP_ARMV8,
+	       cortex_a57),
+  ARM_CPU_OPT2 ("cortex-a72",	  "Cortex-A72",	       ARM_ARCH_V8A,
+	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+	       FPU_ARCH_NEON_VFP_ARMV8,
+	       cortex_a72),
+  ARM_CPU_OPT2 ("cortex-a73",	  "Cortex-A73",	       ARM_ARCH_V8A,
+	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+	       FPU_ARCH_NEON_VFP_ARMV8,
+	       cortex_a73),
+  ARM_CPU_OPT2 ("cortex-a75",    "Cortex-A75",	       ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       cortex_a75),
+  ARM_CPU_OPT2 ("cortex-a76",    "Cortex-A76",	       ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       cortex_a76),
+  ARM_CPU_OPT2 ("cortex-a76ae",    "Cortex-A76AE",      ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       cortex_a76ae),
+  ARM_CPU_OPT2 ("cortex-a77",    "Cortex-A77",	       ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       cortex_a77),
+  ARM_CPU_OPT2 ("cortex-a78",   "Cortex-A78",	       ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       cortex_a78),
+  ARM_CPU_OPT2 ("cortex-a78ae",   "Cortex-A78AE",	   ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       cortex_a78ae),
+  ARM_CPU_OPT2 ("cortex-a78c",   "Cortex-A78C",	   ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       cortex_a78c),
   ARM_CPU_OPT ("cortex-r4",	  "Cortex-R4",	       ARM_ARCH_V7R,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-r4f",	  "Cortex-R4F",	       ARM_ARCH_V7R,
-	       ARM_ARCH_NONE,
+	       FPU_ARCH_VFP_V3D16,
 	       FPU_ARCH_VFP_V3D16),
-  ARM_CPU_OPT ("cortex-r5",	  "Cortex-R5",	       ARM_ARCH_V7R,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
-	       FPU_ARCH_SOFTVFP),
-  ARM_CPU_OPT ("cortex-r7",	  "Cortex-R7",	       ARM_ARCH_V7R,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
-	       FPU_ARCH_VFP_V3D16),
-  ARM_CPU_OPT ("cortex-r8",	  "Cortex-R8",	       ARM_ARCH_V7R,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
-	       FPU_ARCH_VFP_V3D16),
-  ARM_CPU_OPT ("cortex-r52",	  "Cortex-R52",	       ARM_ARCH_V8R,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	      FPU_ARCH_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-r52plus",	  "Cortex-R52+",	       ARM_ARCH_V8R,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	      FPU_ARCH_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-m35p",	  "Cortex-M35P",       ARM_ARCH_V8M_MAIN,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
-	       FPU_ARCH_SOFTVFP),
-  ARM_CPU_OPT ("cortex-m33",	  "Cortex-M33",	       ARM_ARCH_V8M_MAIN,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
-	       FPU_ARCH_SOFTVFP),
+  ARM_CPU_OPT2 ("cortex-r5",	  "Cortex-R5",	       ARM_ARCH_V7R,
+	       ARM_FEATURE (ARM_EXT_ADIV, 0, FPU_VFP_V3),
+	       FPU_ARCH_VFP_V3,
+	       cortex_r5),
+  ARM_CPU_OPT2 ("cortex-r7",	  "Cortex-R7",	       ARM_ARCH_V7R,
+	       ARM_FEATURE (ARM_EXT_ADIV, 0, FPU_VFP_V3D16 | FPU_VFP_EXT_FP16),
+	       FPU_ARCH_VFP_V3D16_FP16,
+	       cortex_r7),
+  ARM_CPU_OPT2 ("cortex-r8",	  "Cortex-R8",	       ARM_ARCH_V7R,
+	       ARM_FEATURE (ARM_EXT_ADIV, 0, FPU_VFP_V3D16 | FPU_VFP_EXT_FP16),
+	       FPU_ARCH_VFP_V3D16_FP16,
+	       cortex_r8),
+  ARM_CPU_OPT2 ("cortex-r52",	  "Cortex-R52",	       ARM_ARCH_V8R,
+	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+         FPU_ARCH_NEON_VFP_ARMV8,
+	       cortex_r52),
+  ARM_CPU_OPT2 ("cortex-r52plus",	  "Cortex-R52+",	ARM_ARCH_V8R,
+	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+         FPU_ARCH_NEON_VFP_ARMV8,
+	       cortex_r52plus),
+  ARM_CPU_OPT2 ("cortex-m85",	 "Cortex-M85",	       ARM_ARCH_V8_1M_MAIN,
+	       ARM_FEATURE_ALL(ARM_AEXT_V8M_MAIN_DSP,
+	       ARM_EXT2_FP16_INST | ARM_EXT2_MVE | ARM_EXT2_MVE_FP,
+	       ARM_EXT3_PACBTI,
+	       FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA),
+	       FPU_ARCH_SOFTVFP,
+	       cortex_m85),
+  ARM_CPU_OPT2 ("cortex-m55",	 "Cortex-M55",	       ARM_ARCH_V8_1M_MAIN,
+	       ARM_FEATURE_ALL(ARM_AEXT_V8M_MAIN_DSP,
+	       ARM_EXT2_FP16_INST | ARM_EXT2_MVE | ARM_EXT2_MVE_FP,
+	       0, FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA),
+	       FPU_ARCH_SOFTVFP,
+	       cortex_m55),
+  ARM_CPU_OPT2 ("cortex-m52",	 "Cortex-M52",	       ARM_ARCH_V8_1M_MAIN,
+	       ARM_FEATURE_ALL (ARM_AEXT_V8M_MAIN_DSP,
+	       ARM_EXT2_FP16_INST | ARM_EXT2_MVE | ARM_EXT2_MVE_FP,
+	       ARM_EXT3_PACBTI,
+	       FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA),
+	       FPU_ARCH_SOFTVFP,
+	       cortex_m52),
+  ARM_CPU_OPT2 ("cortex-m35p",	  "Cortex-M35P",       ARM_ARCH_V8M_MAIN,
+	       ARM_FEATURE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP, FPU_VFP_V4D16),
+	       FPU_ARCH_VFP_V3D16,
+	       cortex_m35p),
+  ARM_CPU_OPT2 ("cortex-m33",	  "Cortex-M33",	       ARM_ARCH_V8M_MAIN,
+	       ARM_FEATURE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP, FPU_VFP_V4D16),
+	       FPU_ARCH_VFP_V3D16, cortex_m33),
   ARM_CPU_OPT ("cortex-m23",	  "Cortex-M23",	       ARM_ARCH_V8M_BASE,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_SOFTVFP),
-  ARM_CPU_OPT ("cortex-m7",	  "Cortex-M7",	       ARM_ARCH_V7EM,
-	       ARM_ARCH_NONE,
-	       FPU_ARCH_SOFTVFP),
-  ARM_CPU_OPT ("cortex-m4",	  "Cortex-M4",	       ARM_ARCH_V7EM,
-	       ARM_ARCH_NONE,
-	       FPU_ARCH_SOFTVFP),
+  ARM_CPU_OPT2 ("cortex-m7",	  "Cortex-M7",	       ARM_ARCH_V7EM,
+	       ARM_FEATURE_COPROC (FPU_VFP_V5D16),
+	       FPU_ARCH_VFP_V5D16,
+	       cortex_m7),
+  ARM_CPU_OPT2 ("cortex-m4",	  "Cortex-M4",	       ARM_ARCH_V7EM,
+	       ARM_FEATURE_COPROC (FPU_VFP_V4_SP_D16),
+	       FPU_ARCH_VFP_V4_SP_D16,
+	       cortex_m4),
   ARM_CPU_OPT ("cortex-m3",	  "Cortex-M3",	       ARM_ARCH_V7M,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_SOFTVFP),
@@ -30883,28 +31282,47 @@ static const struct arm_cpu_option_table arm_cpus[] =
   ARM_CPU_OPT ("cortex-m0plus",	  "Cortex-M0+",	       ARM_ARCH_V6SM,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_SOFTVFP),
-  ARM_CPU_OPT ("cortex-x1",   "Cortex-X1",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
-	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-x1c",   "Cortex-X1C",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
-	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("exynos-m1",	  "Samsung Exynos M1", ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("neoverse-n1",    "Neoverse N1",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
-  ARM_CPU_OPT ("neoverse-n2",	 "Neoverse N2",	       ARM_ARCH_V8_5A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
-				    | ARM_EXT2_BF16
-				    | ARM_EXT2_I8MM),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4),
-  ARM_CPU_OPT ("neoverse-v1", "Neoverse V1", ARM_ARCH_V8_4A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
-				    | ARM_EXT2_BF16
-				    | ARM_EXT2_I8MM),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4),
+  ARM_CPU_OPT2 ("cortex-x1",   "Cortex-X1",	       ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       cortex_x1),
+  ARM_CPU_OPT2 ("cortex-x1c",   "Cortex-X1C",	       ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       cortex_x1c),
+  ARM_CPU_OPT2 ("exynos-m1",	  "Samsung Exynos M1", ARM_ARCH_V8A,
+	       ARM_FEATURE (0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+         FPU_ARCH_NEON_VFP_ARMV8,
+	       exynos_m1),
+  ARM_CPU_OPT2 ("neoverse-n1",	 "Neoverse N1",	       ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       neoverse_n1),
+  ARM_CPU_OPT2 ("ares",    "Ares",	       ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       neoverse_n1),
+  ARM_CPU_OPT2 ("neoverse-n2",	 "Neoverse N2",	       ARM_ARCH_V9A,
+	       ARM_FEATURE(0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML |
+	       ARM_EXT2_BF16 | ARM_EXT2_I8MM,
+	       FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8 |
+	       FPU_NEON_EXT_DOTPROD | FPU_NEON_EXT_RDMA),
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       neoverse_n2),
+  ARM_CPU_OPT2 ("cortex-a710",	 "Cortex-A710",	   ARM_ARCH_V9A,
+	       ARM_FEATURE(0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML |
+		              ARM_EXT2_BF16 | ARM_EXT2_I8MM,
+			      FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8 |
+			      FPU_NEON_EXT_DOTPROD | FPU_NEON_EXT_RDMA),
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       cortex_a710),
+  ARM_CPU_OPT2 ("neoverse-v1",	 "Neoverse V1",	       ARM_ARCH_V8_4A,
+	       ARM_FEATURE(0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML |
+			      ARM_EXT2_BF16 | ARM_EXT2_I8MM,
+			      FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8 |
+			      FPU_NEON_EXT_DOTPROD),
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       neoverse_v1),
   /* ??? XSCALE is really an architecture.  */
   ARM_CPU_OPT ("xscale",	  NULL,		       ARM_ARCH_XSCALE,
 	       ARM_ARCH_NONE,
@@ -30928,31 +31346,24 @@ static const struct arm_cpu_option_table arm_cpus[] =
 
   /* Marvell processors.  */
   ARM_CPU_OPT ("marvell-pj4",	  NULL,		       ARM_ARCH_V7A,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
-	       FPU_ARCH_VFP_V3D16),
+	       ARM_FEATURE (ARM_EXT_MP | ARM_EXT_SEC, 0, FPU_VFP_V3),
+	       FPU_ARCH_VFP_V3),
   ARM_CPU_OPT ("marvell-whitney", NULL,		       ARM_ARCH_V7A,
 	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
 	       FPU_ARCH_NEON_VFP_V4),
 
   /* APM X-Gene family.  */
   ARM_CPU_OPT ("xgene1",	  "APM X-Gene 1",      ARM_ARCH_V8A,
-	       ARM_ARCH_NONE,
+	       ARM_FEATURE (0, 0, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
 	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
   ARM_CPU_OPT ("xgene2",	  "APM X-Gene 2",      ARM_ARCH_V8A,
 	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
 	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
 
-  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL, NULL }
 };
 #undef ARM_CPU_OPT
-
-struct arm_ext_table
-{
-  const char *		  name;
-  size_t		  name_len;
-  const arm_feature_set	  merge;
-  const arm_feature_set	  clear;
-};
+#undef ARM_CPU_OPT2
 
 struct arm_arch_option_table
 {
@@ -30963,16 +31374,6 @@ struct arm_arch_option_table
   const struct arm_ext_table *	ext_table;
 };
 
-/* Used to add support for +E and +noE extension.  */
-#define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
-/* Used to add support for a +E extension.  */
-#define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
-/* Used to add support for a +noE extension.  */
-#define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
-
-#define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
-			    ~0 & ~FPU_ENDIAN_PURE)
-
 static const struct arm_ext_table armv5te_ext_table[] =
 {
   ARM_EXT ("fp", FPU_ARCH_VFP_V2, ALL_FP),
@@ -31169,16 +31570,6 @@ static const struct arm_ext_table armv9a_ext_table[] =
 #define armv94a_ext_table armv93a_ext_table
 #define armv95a_ext_table armv94a_ext_table
 
-#define CDE_EXTENSIONS \
-  ARM_ADD ("cdecp0", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE0)), \
-  ARM_ADD ("cdecp1", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE1)), \
-  ARM_ADD ("cdecp2", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE2)), \
-  ARM_ADD ("cdecp3", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE3)), \
-  ARM_ADD ("cdecp4", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE4)), \
-  ARM_ADD ("cdecp5", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE5)), \
-  ARM_ADD ("cdecp6", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE6)), \
-  ARM_ADD ("cdecp7", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE7))
-
 static const struct arm_ext_table armv8m_main_ext_table[] =
 {
   ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP),
@@ -31755,7 +32146,7 @@ arm_parse_cpu (const char *str)
 	  }
 
 	if (ext != NULL)
-	  return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, NULL);
+	  return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, opt->ext_table);
 
 	return true;
       }
diff --git a/gas/testsuite/gas/arm/command-line-mcpu.exp b/gas/testsuite/gas/arm/command-line-mcpu.exp
new file mode 100644
index 00000000000..fc52296f882
--- /dev/null
+++ b/gas/testsuite/gas/arm/command-line-mcpu.exp
@@ -0,0 +1,134 @@
+
+if {[istarget arm*-*-*]} {
+    gas_test_old "feat-mp.s" "-mcpu=cortex-a5" "gas/arm: cortex-a5 feat-mp"
+    gas_test_old "feat-sec.s" "-mcpu=cortex-a5" "gas/arm: cortex-a5 feat-sec"
+    gas_test_old "feat-neon-fp16.s" "-mcpu=cortex-a5" "gas/arm: cortex-a5 feat-neon-fp16"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a5+nofp+nosimd" "gas/arm: cortex-a5 exts"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a7" "gas/arm: cortex-a7 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a7+nofp+nosimd" "gas/arm: cortex-a7 exts"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a8" "gas/arm: cortex-a8 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a8+nofp" "gas/arm: cortex-a8 exts"
+    gas_test_old "feat-mp.s" "-mcpu=cortex-a9" "gas/arm: cortex-a9 feat-mp"
+    gas_test_old "feat-sec.s" "-mcpu=cortex-a9" "gas/arm: cortex-a9 feat-sec"
+    gas_test_old "feat-neon-fp16.s" "-mcpu=cortex-a9" "gas/arm: cortex-a9 feat-neon-fp16"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a9+nofp+nosimd" "gas/arm: cortex-a9 exts"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a12" "gas/arm: cortex-a12 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a12+nofp" "gas/arm: cortex-a12 exts"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a15" "gas/arm: cortex-a15 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a15+nofp" "gas/arm: cortex-a15 exts"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a17" "gas/arm: cortex-a17 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a17+nofp" "gas/arm: cortex-a17 exts"
+    gas_test_old "feat-mp.s" "-mcpu=marvell-pj4" "gas/arm: marvell-pj4 feat-mp"
+    gas_test_old "feat-sec.s" "-mcpu=marvell-pj4" "gas/arm: marvell-pj4 feat-sec"
+    gas_test_old "feat-fp-vfpv3.s" "-mcpu=marvell-pj4" "gas/arm: marvell-pj4 feat-fp-vfpv3"
+    gas_test_old "feat-fp-vfpv3.s" "-mcpu=cortex-r4f" "gas/arm: cortex-r4f feat-fp-vfpv3"
+    gas_test_old "feat-fp-vfpv3.s" "-mcpu=cortex-r5" "gas/arm: cortex-r5 feat-fp-vfpv3"
+    gas_test_old "feat-idiv.s" "-mcpu=cortex-r5" "gas/arm: cortex-r5 feat-idiv"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-r5+nofp+nofp.dp" "gas/arm: cortex-r5 exts"
+    gas_test_old "feat-idiv.s" "-mcpu=cortex-r7" "gas/arm: cortex-r7 feat-idiv"
+    gas_test_old "feat-vfpv3-d16-fp16.s" "-mcpu=cortex-r7" "gas/arm: cortex-r7 feat-vfpv3-d16-fp16"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-r7+nofp+nofp.dp" "gas/arm: cortex-r7 exts"
+    gas_test_old "feat-idiv.s" "-mcpu=cortex-r8" "gas/arm: cortex-r8 feat-idiv"
+    gas_test_old "feat-vfpv3-d16-fp16.s" "-mcpu=cortex-r8" "gas/arm: cortex-r8 feat-vfpv3-d16-fp16"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-r8+nofp+nofp.dp" "gas/arm: cortex-r8 exts"
+    gas_test_old "feat-fp-vfpv3.s" "-mcpu=cortex-m4" "gas/arm: cortex-m4 feat-fp-vfpv3"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-m4+nofp" "gas/arm: cortex-m4 exts"
+    gas_test_old "feat-fp.dp.s" "-mcpu=cortex-m7" "gas/arm: cortex-m7 feat-fp.dp"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-m7+nofp+nofp.dp" "gas/arm: cortex-m7 exts"
+    gas_test_old "feat-crc.s" "-mcpu=cortex-a32" "gas/arm: cortex-a32 feat-crc"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a32" "gas/arm: cortex-a32 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a32+nofp" "gas/arm: cortex-a32 exts"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a32+crypto" "gas/arm: cortex-a32 exts"
+    gas_test_old "feat-crc.s" "-mcpu=cortex-a35" "gas/arm: cortex-a35 feat-crc"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a35" "gas/arm: cortex-a35 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a35+nofp" "gas/arm: cortex-a35 exts"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a35+crypto" "gas/arm: cortex-a35 exts"
+    gas_test_old "feat-crc.s" "-mcpu=cortex-a53" "gas/arm: cortex-a53 feat-crc"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a53" "gas/arm: cortex-a53 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a53+nofp" "gas/arm: cortex-a53 exts"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a53+crypto" "gas/arm: cortex-a53 exts"
+    gas_test_old "feat-crc.s" "-mcpu=cortex-a57" "gas/arm: cortex-a57 feat-crc"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a57" "gas/arm: cortex-a57 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a57+crypto" "gas/arm: cortex-a57 exts"
+    gas_test_old "feat-crc.s" "-mcpu=cortex-a72" "gas/arm: cortex-a72 feat-crc"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a72" "gas/arm: cortex-a72 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a72+crypto" "gas/arm: cortex-a72 exts"
+    gas_test_old "feat-crc.s" "-mcpu=cortex-a73" "gas/arm: cortex-a73 feat-crc"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a73" "gas/arm: cortex-a73 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a73+crypto" "gas/arm: cortex-a73 exts"
+    gas_test_old "feat-crc.s" "-mcpu=exynos-m1" "gas/arm: exynos-m1 feat-crc"
+    gas_test_old "feat-simd.s" "-mcpu=exynos-m1" "gas/arm: exynos-m1 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=exynos-m1+crypto" "gas/arm: exynos-m1 exts"
+    gas_test_old "feat-simd.s" "-mcpu=xgene1" "gas/arm: xgene1 feat-simd"
+    gas_test_old "feat-crc.s" "-mcpu=cortex-r52" "gas/arm: cortex-r52 feat-crc"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-r52" "gas/arm: cortex-r52 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-r52+nofp.dp" "gas/arm: cortex-r52 exts"
+    gas_test_old "feat-crc.s" "-mcpu=cortex-r52plus" "gas/arm: cortex-r52plus feat-crc"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-r52plus" "gas/arm: cortex-r52plus feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-r52plus+nofp.dp" "gas/arm: cortex-r52plus exts"
+    gas_test_old "feat-dsp.s" "-mcpu=cortex-m33" "gas/arm: cortex-m33 feat-dsp"
+    gas_test_old "feat-fp-vfpv5.s" "-mcpu=cortex-m33" "gas/arm: cortex-m33 feat-fp-vfpv5"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-m33+nofp+nodsp" "gas/arm: cortex-m33 exts"
+    gas_test_old "feat-dsp.s" "-mcpu=cortex-m35p" "gas/arm: cortex-m35p feat-dsp"
+    gas_test_old "feat-fp-vfpv5.s" "-mcpu=cortex-m35p" "gas/arm: cortex-m35p feat-fp-vfpv5"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-m35p+nofp+nodsp" "gas/arm: cortex-m35p exts"
+    gas_test_old "feat-pacbti.s" "-mcpu=cortex-m52" "gas/arm: cortex-m52 feat-pacbti"
+    gas_test_old "feat-mve.fp.s" "-mcpu=cortex-m52" "gas/arm: cortex-m52 feat-mve.fp"
+    gas_test_old "feat-fp.dp.s" "-mcpu=cortex-m52" "gas/arm: cortex-m52 feat-fp.dp"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-m52+nopacbti+nomve.fp+nomve+nofp+nodsp" "gas/arm: cortex-m52 exts"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-m52+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7" "gas/arm: cortex-m52 exts"
+    gas_test_old "feat-mve.fp.s" "-mcpu=cortex-m55" "gas/arm: cortex-m55 feat-mve.fp"
+    gas_test_old "feat-fp.dp.s" "-mcpu=cortex-m55" "gas/arm: cortex-m55 feat-fp.dp"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-m55+nomve.fp+nomve+nofp+nodsp" "gas/arm: cortex-m55 exts"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-m55+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7" "gas/arm: cortex-m55 exts"
+    gas_test_old "feat-pacbti.s" "-mcpu=cortex-m85" "gas/arm: cortex-m85 feat-pacbti"
+    gas_test_old "feat-mve.fp.s" "-mcpu=cortex-m85" "gas/arm: cortex-m85 feat-mve.fp"
+    gas_test_old "feat-fp.dp.s" "-mcpu=cortex-m85" "gas/arm: cortex-m85 feat-fp.dp"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-m85+nopacbti+nomve.fp+nomve+nofp+nodsp" "gas/arm: cortex-m85 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-a55" "gas/arm: cortex-a55 feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a55" "gas/arm: cortex-a55 feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a55+nofp" "gas/arm: cortex-a55 exts"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a55+crypto" "gas/arm: cortex-a55 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-a75" "gas/arm: cortex-a75 feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a75" "gas/arm: cortex-a75 feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a75+crypto" "gas/arm: cortex-a75 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-a76" "gas/arm: cortex-a76 feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a76" "gas/arm: cortex-a76 feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a76+crypto" "gas/arm: cortex-a76 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-a76ae" "gas/arm: cortex-a76ae feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a76ae" "gas/arm: cortex-a76ae feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a76ae+crypto" "gas/arm: cortex-a76ae exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-a77" "gas/arm: cortex-a77 feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a77" "gas/arm: cortex-a77 feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a77+crypto" "gas/arm: cortex-a77 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-a78" "gas/arm: cortex-a78 feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a78" "gas/arm: cortex-a78 feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a78+crypto" "gas/arm: cortex-a78 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-a78ae" "gas/arm: cortex-a78ae feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a78ae" "gas/arm: cortex-a78ae feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a78ae+crypto" "gas/arm: cortex-a78ae exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-a78c" "gas/arm: cortex-a78c feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a78c" "gas/arm: cortex-a78c feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a78c+crypto" "gas/arm: cortex-a78c exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-x1" "gas/arm: cortex-x1 feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-x1" "gas/arm: cortex-x1 feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-x1+crypto" "gas/arm: cortex-x1 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-x1c" "gas/arm: cortex-x1c feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-x1c" "gas/arm: cortex-x1c feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-x1c+crypto" "gas/arm: cortex-x1c exts"
+    gas_test_old "feat-fp16.s" "-mcpu=neoverse-n1" "gas/arm: neoverse-n1 feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=neoverse-n1" "gas/arm: neoverse-n1 feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=neoverse-n1+crypto" "gas/arm: neoverse-n1 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=neoverse-v1" "gas/arm: neoverse-v1 feat-fp16"
+    gas_test_old "feat-bf16.s" "-mcpu=neoverse-v1" "gas/arm: neoverse-v1 feat-bf16"
+    gas_test_old "feat-i8mm.s" "-mcpu=neoverse-v1" "gas/arm: neoverse-v1 feat-i8mm"
+    gas_test_old "nop-asm.s" "-mcpu=neoverse-v1+crypto" "gas/arm: neoverse-v1 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-a710" "gas/arm: cortex-a710 feat-fp16"
+    gas_test_old "feat-bf16.s" "-mcpu=cortex-a710" "gas/arm: cortex-a710 feat-bf16"
+    gas_test_old "feat-i8mm.s" "-mcpu=cortex-a710" "gas/arm: cortex-a710 feat-i8mm"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a710+crypto" "gas/arm: cortex-a710 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=neoverse-n2" "gas/arm: neoverse-n2 feat-fp16"
+    gas_test_old "feat-bf16.s" "-mcpu=neoverse-n2" "gas/arm: neoverse-n2 feat-bf16"
+    gas_test_old "feat-i8mm.s" "-mcpu=neoverse-n2" "gas/arm: neoverse-n2 feat-i8mm"
+    gas_test_old "nop-asm.s" "-mcpu=neoverse-n2+crypto" "gas/arm: neoverse-n2 exts"
+}
diff --git a/gas/testsuite/gas/arm/feat-bf16.s b/gas/testsuite/gas/arm/feat-bf16.s
new file mode 100644
index 00000000000..46fc48ba567
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-bf16.s
@@ -0,0 +1,5 @@
+.syntax unified
+.thumb
+
+@ feat FP16
+vdot.bf16 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/feat-crc.s b/gas/testsuite/gas/arm/feat-crc.s
new file mode 100644
index 00000000000..671ac14ebcb
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-crc.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat CRC
+crc32w  r0, r0, r1
diff --git a/gas/testsuite/gas/arm/feat-dotprod.s b/gas/testsuite/gas/arm/feat-dotprod.s
new file mode 100644
index 00000000000..775c3ba4c02
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-dotprod.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat DOTPROD
+vudot.u8 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/feat-dsp.s b/gas/testsuite/gas/arm/feat-dsp.s
new file mode 100644
index 00000000000..2f54c7327d1
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-dsp.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat DSP
+smlad   r0, r1, r2, r3
diff --git a/gas/testsuite/gas/arm/feat-fp-vfpv3.s b/gas/testsuite/gas/arm/feat-fp-vfpv3.s
new file mode 100644
index 00000000000..4435db35690
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-fp-vfpv3.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat FP (VFP-v3)
+vmla.f32 s0, s1, s2
diff --git a/gas/testsuite/gas/arm/feat-fp-vfpv5.s b/gas/testsuite/gas/arm/feat-fp-vfpv5.s
new file mode 100644
index 00000000000..13a2e7aca9e
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-fp-vfpv5.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat FP (VFP-v5)
+vfma.f32 s0, s1, s2
diff --git a/gas/testsuite/gas/arm/feat-fp.dp.s b/gas/testsuite/gas/arm/feat-fp.dp.s
new file mode 100644
index 00000000000..34b68cd8603
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-fp.dp.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat FP.DP
+vadd.f64 d0, d1, d2
diff --git a/gas/testsuite/gas/arm/feat-fp.s b/gas/testsuite/gas/arm/feat-fp.s
new file mode 100644
index 00000000000..5cf49af0e9f
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-fp.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat FP
+vadd.f32 s0, s1, s2
diff --git a/gas/testsuite/gas/arm/feat-fp16.s b/gas/testsuite/gas/arm/feat-fp16.s
new file mode 100644
index 00000000000..6780678e8ca
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-fp16.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat FP16
+vadd.f16 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/feat-i8mm.s b/gas/testsuite/gas/arm/feat-i8mm.s
new file mode 100644
index 00000000000..bb3818726a8
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-i8mm.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat I8MM
+vusmmla.s8  q6, q7, q8
diff --git a/gas/testsuite/gas/arm/feat-idiv.s b/gas/testsuite/gas/arm/feat-idiv.s
new file mode 100644
index 00000000000..8b289fa817d
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-idiv.s
@@ -0,0 +1,3 @@
+.syntax unified
+
+sdiv r0, r1, r2
diff --git a/gas/testsuite/gas/arm/feat-mp.s b/gas/testsuite/gas/arm/feat-mp.s
new file mode 100644
index 00000000000..db365d7f282
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-mp.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat MP
+ldrex r0, [r1]
diff --git a/gas/testsuite/gas/arm/feat-mve.fp.s b/gas/testsuite/gas/arm/feat-mve.fp.s
new file mode 100644
index 00000000000..81c23300dc3
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-mve.fp.s
@@ -0,0 +1,5 @@
+.syntax unified
+.thumb
+
+@ MVE.FP
+vmul.f32 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/feat-neon-fp16.s b/gas/testsuite/gas/arm/feat-neon-fp16.s
new file mode 100644
index 00000000000..55ab08553bf
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-neon-fp16.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat NEON-FP16
+vadd.f16 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/feat-pacbti.s b/gas/testsuite/gas/arm/feat-pacbti.s
new file mode 100644
index 00000000000..2399f0ca230
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-pacbti.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ PACBTI
+pac     r12, lr, sp
diff --git a/gas/testsuite/gas/arm/feat-sec.s b/gas/testsuite/gas/arm/feat-sec.s
new file mode 100644
index 00000000000..bdb516a30f4
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-sec.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat SEC
+smc     #0
diff --git a/gas/testsuite/gas/arm/feat-simd.s b/gas/testsuite/gas/arm/feat-simd.s
new file mode 100644
index 00000000000..871f5490902
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-simd.s
@@ -0,0 +1,5 @@
+.syntax unified
+.text
+
+@ feat SIMD
+vadd.i32 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s b/gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s
new file mode 100644
index 00000000000..41ccd2d9414
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat VFP3-D16-FP16
+vcvtt.f16.f32 s0, s1
-- 
2.43.0


From sivan.shani@arm.com  Mon Jun  8 14:52:19 2026
From: sivan.shani@arm.com (Sivan Shani)
Date: Mon, 8 Jun 2026 14:52:19 +0000
Subject: [PATCH] gas: arm - support CPU-specific extensions with -mcpu
In-Reply-To: <20260608141413.35735-1-sivan.shani@arm.com>
References: <20260608141413.35735-1-sivan.shani@arm.com>
Message-ID: <20260608145251.37337-1-sivan.shani@arm.com>

Add extension tables for -mcpu, similar to -march, allowing
CPU-specific extensions to be enabled and disabled using +ext and
+noext modifiers.

Update ARM CPU feature definitions to match GCC CPU baselines and
add tests covering supported CPU extension modifiers and feature
availability.

Fix: use CDE_EXTENSIONS
---
 gas/config/tc-arm.c                         | 687 +++++++++++++++-----
 gas/testsuite/gas/arm/command-line-mcpu.exp | 134 ++++
 gas/testsuite/gas/arm/feat-bf16.s           |   5 +
 gas/testsuite/gas/arm/feat-crc.s            |   4 +
 gas/testsuite/gas/arm/feat-dotprod.s        |   4 +
 gas/testsuite/gas/arm/feat-dsp.s            |   4 +
 gas/testsuite/gas/arm/feat-fp-vfpv3.s       |   4 +
 gas/testsuite/gas/arm/feat-fp-vfpv5.s       |   4 +
 gas/testsuite/gas/arm/feat-fp.dp.s          |   4 +
 gas/testsuite/gas/arm/feat-fp.s             |   4 +
 gas/testsuite/gas/arm/feat-fp16.s           |   4 +
 gas/testsuite/gas/arm/feat-i8mm.s           |   4 +
 gas/testsuite/gas/arm/feat-idiv.s           |   3 +
 gas/testsuite/gas/arm/feat-mp.s             |   4 +
 gas/testsuite/gas/arm/feat-mve.fp.s         |   5 +
 gas/testsuite/gas/arm/feat-neon-fp16.s      |   4 +
 gas/testsuite/gas/arm/feat-pacbti.s         |   4 +
 gas/testsuite/gas/arm/feat-sec.s            |   4 +
 gas/testsuite/gas/arm/feat-simd.s           |   5 +
 gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s |   4 +
 20 files changed, 740 insertions(+), 155 deletions(-)
 create mode 100644 gas/testsuite/gas/arm/command-line-mcpu.exp
 create mode 100644 gas/testsuite/gas/arm/feat-bf16.s
 create mode 100644 gas/testsuite/gas/arm/feat-crc.s
 create mode 100644 gas/testsuite/gas/arm/feat-dotprod.s
 create mode 100644 gas/testsuite/gas/arm/feat-dsp.s
 create mode 100644 gas/testsuite/gas/arm/feat-fp-vfpv3.s
 create mode 100644 gas/testsuite/gas/arm/feat-fp-vfpv5.s
 create mode 100644 gas/testsuite/gas/arm/feat-fp.dp.s
 create mode 100644 gas/testsuite/gas/arm/feat-fp.s
 create mode 100644 gas/testsuite/gas/arm/feat-fp16.s
 create mode 100644 gas/testsuite/gas/arm/feat-i8mm.s
 create mode 100644 gas/testsuite/gas/arm/feat-idiv.s
 create mode 100644 gas/testsuite/gas/arm/feat-mp.s
 create mode 100644 gas/testsuite/gas/arm/feat-mve.fp.s
 create mode 100644 gas/testsuite/gas/arm/feat-neon-fp16.s
 create mode 100644 gas/testsuite/gas/arm/feat-pacbti.s
 create mode 100644 gas/testsuite/gas/arm/feat-sec.s
 create mode 100644 gas/testsuite/gas/arm/feat-simd.s
 create mode 100644 gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 3ff29542411..ef9b878dffc 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -30495,6 +30495,14 @@ const struct arm_legacy_option_table arm_legacy_opts[] =
   {NULL, NULL, ARM_ARCH_NONE, NULL}
 };
 
+struct arm_ext_table
+{
+  const char *		  name;
+  size_t		  name_len;
+  const arm_feature_set	  merge;
+  const arm_feature_set	  clear;
+};
+
 struct arm_cpu_option_table
 {
   const char *           name;
@@ -30507,11 +30515,339 @@ struct arm_cpu_option_table
   /* The canonical name of the CPU, or NULL to use NAME converted to upper
      case.  */
   const char *           canonical_name;
+  const struct arm_ext_table *	ext_table;
+};
+
+/* Used to add support for +E and +noE extension.  */
+#define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
+/* Used to add support for a +E extension.  */
+#define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
+/* Used to add support for a +noE extension.  */
+#define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
+
+#define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
+			    ~0 & ~FPU_ENDIAN_PURE)
+#define ALL_FP_MVE_FP ARM_FEATURE (0, (ARM_EXT2_FP16_INST		   \
+					| ARM_EXT2_FP16_FML		   \
+					| ARM_EXT2_MVE_FP),		   \
+				    ~0 & ~FPU_ENDIAN_PURE)
+#define ALL_SIMD ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA |     \
+				     FPU_NEON_EXT_ARMV8 | FPU_NEON_EXT_RDMA | \
+				     FPU_NEON_EXT_DOTPROD)
+
+#define CDE_EXTENSIONS \
+  ARM_ADD ("cdecp0", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE0)), \
+  ARM_ADD ("cdecp1", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE1)), \
+  ARM_ADD ("cdecp2", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE2)), \
+  ARM_ADD ("cdecp3", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE3)), \
+  ARM_ADD ("cdecp4", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE4)), \
+  ARM_ADD ("cdecp5", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE5)), \
+  ARM_ADD ("cdecp6", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE6)), \
+  ARM_ADD ("cdecp7", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE7))
+
+/* -mcpu extensions.  */
+static const struct arm_ext_table cortex_a5_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  ARM_REMOVE ("simd", ALL_SIMD),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a7_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  ARM_REMOVE ("simd", ALL_SIMD),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a8_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a9_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  ARM_REMOVE ("simd", ALL_SIMD),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a12_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a15_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a17_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_r5_ext_table[] =
+{
+  ARM_REMOVE ("fp",    ALL_FP),
+  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
+		      | FPU_VFP_EXT_ARMV8)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_r7_ext_table[] =
+{
+  ARM_REMOVE ("fp",    ALL_FP),
+  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
+		      | FPU_VFP_EXT_ARMV8)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_r8_ext_table[] =
+{
+  ARM_REMOVE ("fp",    ALL_FP),
+  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
+		      | FPU_VFP_EXT_ARMV8)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m4_ext_table[] =
+{
+  ARM_REMOVE ("fp",    ALL_FP),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m7_ext_table[] =
+{
+  ARM_REMOVE ("fp",    ALL_FP),
+  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
+		      | FPU_VFP_EXT_ARMV8)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a32_ext_table[] =
+{
+  ARM_REMOVE ("fp",     ALL_FP),
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a35_ext_table[] =
+{
+  ARM_REMOVE ("fp",     ALL_FP),
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a53_ext_table[] =
+{
+  ARM_REMOVE ("fp",     ALL_FP),
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a57_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a72_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a73_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table exynos_m1_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_r52_ext_table[] =
+{
+  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_D32 | FPU_VFP_EXT_ARMV8
+			| FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA
+			| FPU_NEON_EXT_ARMV8 | FPU_NEON_EXT_RDMA
+			| FPU_NEON_EXT_DOTPROD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_r52plus_ext_table[] =
+{
+  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_D32 | FPU_VFP_EXT_ARMV8
+			| FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA
+			| FPU_NEON_EXT_ARMV8 | FPU_NEON_EXT_RDMA
+			| FPU_NEON_EXT_DOTPROD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m33_ext_table[] =
+{
+  ARM_REMOVE ("fp",  ALL_FP),
+  ARM_REMOVE ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m35p_ext_table[] =
+{
+  ARM_REMOVE ("fp",  ALL_FP),
+  ARM_REMOVE ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m52_ext_table[] =
+{
+  ARM_REMOVE ("pacbti", ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI)),
+  ARM_REMOVE ("mve.fp", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP)),
+  ARM_REMOVE ("mve",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+  ARM_REMOVE ("fp",     ALL_FP_MVE_FP),
+  ARM_REMOVE ("dsp",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+  CDE_EXTENSIONS,
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m55_ext_table[] =
+{
+  ARM_REMOVE ("mve.fp", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP)),
+  ARM_REMOVE ("mve",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+  ARM_REMOVE ("fp",     ALL_FP_MVE_FP),
+  ARM_REMOVE ("dsp",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+  CDE_EXTENSIONS,
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m85_ext_table[] =
+{
+  ARM_REMOVE ("pacbti", ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI)),
+  ARM_REMOVE ("mve.fp", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP)),
+  ARM_REMOVE ("mve",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+  ARM_REMOVE ("fp",     ALL_FP_MVE_FP),
+  ARM_REMOVE ("dsp",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a55_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a75_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a76_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a76ae_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a77_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a78_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a78ae_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a78c_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_x1_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_x1c_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table neoverse_n1_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table neoverse_v1_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a710_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table neoverse_n2_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
 };
 
 /* This list should, at a minimum, contain all the cpu names
    recognized by GCC.  */
-#define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
+#define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN, NULL }
+#define ARM_CPU_OPT2(N, CN, V, E, DF, ext) \
+  { N, sizeof (N) - 1, V, E, DF, CN, ext##_ext_table }
 
 static const struct arm_cpu_option_table arm_cpus[] =
 {
@@ -30764,113 +31100,162 @@ static const struct arm_cpu_option_table arm_cpus[] =
   ARM_CPU_OPT ("arm1176jzf-s",	  NULL,		       ARM_ARCH_V6KZ,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_VFP_V2),
-  ARM_CPU_OPT ("cortex-a5",	  "Cortex-A5",	       ARM_ARCH_V7A,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
-	       FPU_ARCH_SOFTVFP),
-  ARM_CPU_OPT ("cortex-a7",	  "Cortex-A7",	       ARM_ARCH_V7VE,
-	       ARM_ARCH_NONE,
-	       FPU_ARCH_NEON_VFP_V4),
-  ARM_CPU_OPT ("cortex-a8",	  "Cortex-A8",	       ARM_ARCH_V7A,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
-	       ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
-  ARM_CPU_OPT ("cortex-a9",	  "Cortex-A9",	       ARM_ARCH_V7A,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
-	       ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
-  ARM_CPU_OPT ("cortex-a12",	  "Cortex-A12",	       ARM_ARCH_V7VE,
-	       ARM_ARCH_NONE,
-	       FPU_ARCH_NEON_VFP_V4),
-  ARM_CPU_OPT ("cortex-a15",	  "Cortex-A15",	       ARM_ARCH_V7VE,
-	       ARM_ARCH_NONE,
-	       FPU_ARCH_NEON_VFP_V4),
-  ARM_CPU_OPT ("cortex-a17",	  "Cortex-A17",	       ARM_ARCH_V7VE,
-	       ARM_ARCH_NONE,
-	       FPU_ARCH_NEON_VFP_V4),
-  ARM_CPU_OPT ("cortex-a32",	  "Cortex-A32",	       ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a35",	  "Cortex-A35",	       ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a53",	  "Cortex-A53",	       ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a55",    "Cortex-A55",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
-  ARM_CPU_OPT ("cortex-a57",	  "Cortex-A57",	       ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a72",	  "Cortex-A72",	       ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	      FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a73",	  "Cortex-A73",	       ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	      FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a75",    "Cortex-A75",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
-  ARM_CPU_OPT ("cortex-a76",    "Cortex-A76",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
-  ARM_CPU_OPT ("cortex-a76ae",    "Cortex-A76AE",      ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
-  ARM_CPU_OPT ("cortex-a77",    "Cortex-A77",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
-  ARM_CPU_OPT ("cortex-a78",   "Cortex-A78",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
-	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a78ae",   "Cortex-A78AE",	   ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
-	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a78c",   "Cortex-A78C",	   ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
-	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a710",   "Cortex-A710",	   ARM_ARCH_V9A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
-				    | ARM_EXT2_BF16
-				    | ARM_EXT2_I8MM),
-	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("ares",    "Ares",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
+  ARM_CPU_OPT2 ("cortex-a5",	  "Cortex-A5",	       ARM_ARCH_V7A,
+	       ARM_FEATURE (ARM_EXT_MP | ARM_EXT_SEC,
+	       ARM_EXT2_FP16_INST,
+	       FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA),
+	       FPU_ARCH_NEON_VFP_V4,
+	       cortex_a5),
+  ARM_CPU_OPT2 ("cortex-a7",	  "Cortex-A7",	       ARM_ARCH_V7VE,
+	       ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1 |
+	       FPU_NEON_EXT_FMA),
+	       FPU_ARCH_NEON_VFP_V4,
+	       cortex_a7),
+  ARM_CPU_OPT2 ("cortex-a8",	  "Cortex-A8",	       ARM_ARCH_V7A,
+	       ARM_FEATURE_LOW (ARM_EXT_SEC, FPU_VFP_V3 | FPU_NEON_EXT_V1),
+	       ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1),
+	       cortex_a8),
+  ARM_CPU_OPT2 ("cortex-a9",	  "Cortex-A9",	       ARM_ARCH_V7A,
+	       ARM_FEATURE (ARM_EXT_MP | ARM_EXT_SEC,
+	       ARM_EXT2_FP16_INST,
+	       FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA),
+	       FPU_ARCH_NEON_VFP_V4,
+	       cortex_a9),
+  ARM_CPU_OPT2 ("cortex-a12",	  "Cortex-A12",	       ARM_ARCH_V7VE,
+	       ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1 |
+	       FPU_NEON_EXT_FMA),
+	       FPU_ARCH_NEON_VFP_V4,
+	       cortex_a12),
+  ARM_CPU_OPT2 ("cortex-a15",	  "Cortex-A15",	       ARM_ARCH_V7VE,
+	       ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1 |
+	       FPU_NEON_EXT_FMA),
+	       FPU_ARCH_NEON_VFP_V4,
+	       cortex_a15),
+  ARM_CPU_OPT2 ("cortex-a17",	  "Cortex-A17",	       ARM_ARCH_V7VE,
+	       ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1 |
+	       FPU_NEON_EXT_FMA),
+	       FPU_ARCH_NEON_VFP_V4,
+	       cortex_a17),
+  ARM_CPU_OPT2 ("cortex-a32",	  "Cortex-A32",	       ARM_ARCH_V8A,
+	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+	       FPU_ARCH_NEON_VFP_ARMV8,
+	       cortex_a32),
+  ARM_CPU_OPT2 ("cortex-a35",	  "Cortex-A35",	       ARM_ARCH_V8A,
+	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+	       FPU_ARCH_NEON_VFP_ARMV8,
+	       cortex_a35),
+  ARM_CPU_OPT2 ("cortex-a53",	  "Cortex-A53",	       ARM_ARCH_V8A,
+	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+	       FPU_ARCH_NEON_VFP_ARMV8,
+	       cortex_a53),
+  ARM_CPU_OPT2 ("cortex-a55",    "Cortex-A55",	       ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       cortex_a55),
+  ARM_CPU_OPT2 ("cortex-a57",	  "Cortex-A57",	       ARM_ARCH_V8A,
+	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+	       FPU_ARCH_NEON_VFP_ARMV8,
+	       cortex_a57),
+  ARM_CPU_OPT2 ("cortex-a72",	  "Cortex-A72",	       ARM_ARCH_V8A,
+	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+	       FPU_ARCH_NEON_VFP_ARMV8,
+	       cortex_a72),
+  ARM_CPU_OPT2 ("cortex-a73",	  "Cortex-A73",	       ARM_ARCH_V8A,
+	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+	       FPU_ARCH_NEON_VFP_ARMV8,
+	       cortex_a73),
+  ARM_CPU_OPT2 ("cortex-a75",    "Cortex-A75",	       ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       cortex_a75),
+  ARM_CPU_OPT2 ("cortex-a76",    "Cortex-A76",	       ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       cortex_a76),
+  ARM_CPU_OPT2 ("cortex-a76ae",    "Cortex-A76AE",      ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       cortex_a76ae),
+  ARM_CPU_OPT2 ("cortex-a77",    "Cortex-A77",	       ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       cortex_a77),
+  ARM_CPU_OPT2 ("cortex-a78",   "Cortex-A78",	       ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       cortex_a78),
+  ARM_CPU_OPT2 ("cortex-a78ae",   "Cortex-A78AE",	   ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       cortex_a78ae),
+  ARM_CPU_OPT2 ("cortex-a78c",   "Cortex-A78C",	   ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       cortex_a78c),
   ARM_CPU_OPT ("cortex-r4",	  "Cortex-R4",	       ARM_ARCH_V7R,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-r4f",	  "Cortex-R4F",	       ARM_ARCH_V7R,
-	       ARM_ARCH_NONE,
-	       FPU_ARCH_VFP_V3D16),
-  ARM_CPU_OPT ("cortex-r5",	  "Cortex-R5",	       ARM_ARCH_V7R,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
-	       FPU_ARCH_SOFTVFP),
-  ARM_CPU_OPT ("cortex-r7",	  "Cortex-R7",	       ARM_ARCH_V7R,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
-	       FPU_ARCH_VFP_V3D16),
-  ARM_CPU_OPT ("cortex-r8",	  "Cortex-R8",	       ARM_ARCH_V7R,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
+	       FPU_ARCH_VFP_V3D16,
 	       FPU_ARCH_VFP_V3D16),
-  ARM_CPU_OPT ("cortex-r52",	  "Cortex-R52",	       ARM_ARCH_V8R,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	      FPU_ARCH_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-r52plus",	  "Cortex-R52+",	       ARM_ARCH_V8R,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	      FPU_ARCH_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-m35p",	  "Cortex-M35P",       ARM_ARCH_V8M_MAIN,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
-	       FPU_ARCH_SOFTVFP),
-  ARM_CPU_OPT ("cortex-m33",	  "Cortex-M33",	       ARM_ARCH_V8M_MAIN,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
-	       FPU_ARCH_SOFTVFP),
+  ARM_CPU_OPT2 ("cortex-r5",	  "Cortex-R5",	       ARM_ARCH_V7R,
+	       ARM_FEATURE (ARM_EXT_ADIV, 0, FPU_VFP_V3),
+	       FPU_ARCH_VFP_V3,
+	       cortex_r5),
+  ARM_CPU_OPT2 ("cortex-r7",	  "Cortex-R7",	       ARM_ARCH_V7R,
+	       ARM_FEATURE (ARM_EXT_ADIV, 0, FPU_VFP_V3D16 | FPU_VFP_EXT_FP16),
+	       FPU_ARCH_VFP_V3D16_FP16,
+	       cortex_r7),
+  ARM_CPU_OPT2 ("cortex-r8",	  "Cortex-R8",	       ARM_ARCH_V7R,
+	       ARM_FEATURE (ARM_EXT_ADIV, 0, FPU_VFP_V3D16 | FPU_VFP_EXT_FP16),
+	       FPU_ARCH_VFP_V3D16_FP16,
+	       cortex_r8),
+  ARM_CPU_OPT2 ("cortex-r52",	  "Cortex-R52",	       ARM_ARCH_V8R,
+	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+         FPU_ARCH_NEON_VFP_ARMV8,
+	       cortex_r52),
+  ARM_CPU_OPT2 ("cortex-r52plus",	  "Cortex-R52+",	ARM_ARCH_V8R,
+	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+         FPU_ARCH_NEON_VFP_ARMV8,
+	       cortex_r52plus),
+  ARM_CPU_OPT2 ("cortex-m85",	 "Cortex-M85",	       ARM_ARCH_V8_1M_MAIN,
+	       ARM_FEATURE_ALL(ARM_AEXT_V8M_MAIN_DSP,
+	       ARM_EXT2_FP16_INST | ARM_EXT2_MVE | ARM_EXT2_MVE_FP,
+	       ARM_EXT3_PACBTI,
+	       FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA),
+	       FPU_ARCH_SOFTVFP,
+	       cortex_m85),
+  ARM_CPU_OPT2 ("cortex-m55",	 "Cortex-M55",	       ARM_ARCH_V8_1M_MAIN,
+	       ARM_FEATURE_ALL(ARM_AEXT_V8M_MAIN_DSP,
+	       ARM_EXT2_FP16_INST | ARM_EXT2_MVE | ARM_EXT2_MVE_FP,
+	       0, FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA),
+	       FPU_ARCH_SOFTVFP,
+	       cortex_m55),
+  ARM_CPU_OPT2 ("cortex-m52",	 "Cortex-M52",	       ARM_ARCH_V8_1M_MAIN,
+	       ARM_FEATURE_ALL (ARM_AEXT_V8M_MAIN_DSP,
+	       ARM_EXT2_FP16_INST | ARM_EXT2_MVE | ARM_EXT2_MVE_FP,
+	       ARM_EXT3_PACBTI,
+	       FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA),
+	       FPU_ARCH_SOFTVFP,
+	       cortex_m52),
+  ARM_CPU_OPT2 ("cortex-m35p",	  "Cortex-M35P",       ARM_ARCH_V8M_MAIN,
+	       ARM_FEATURE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP, FPU_VFP_V4D16),
+	       FPU_ARCH_VFP_V3D16,
+	       cortex_m35p),
+  ARM_CPU_OPT2 ("cortex-m33",	  "Cortex-M33",	       ARM_ARCH_V8M_MAIN,
+	       ARM_FEATURE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP, FPU_VFP_V4D16),
+	       FPU_ARCH_VFP_V3D16, cortex_m33),
   ARM_CPU_OPT ("cortex-m23",	  "Cortex-M23",	       ARM_ARCH_V8M_BASE,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_SOFTVFP),
-  ARM_CPU_OPT ("cortex-m7",	  "Cortex-M7",	       ARM_ARCH_V7EM,
-	       ARM_ARCH_NONE,
-	       FPU_ARCH_SOFTVFP),
-  ARM_CPU_OPT ("cortex-m4",	  "Cortex-M4",	       ARM_ARCH_V7EM,
-	       ARM_ARCH_NONE,
-	       FPU_ARCH_SOFTVFP),
+  ARM_CPU_OPT2 ("cortex-m7",	  "Cortex-M7",	       ARM_ARCH_V7EM,
+	       ARM_FEATURE_COPROC (FPU_VFP_V5D16),
+	       FPU_ARCH_VFP_V5D16,
+	       cortex_m7),
+  ARM_CPU_OPT2 ("cortex-m4",	  "Cortex-M4",	       ARM_ARCH_V7EM,
+	       ARM_FEATURE_COPROC (FPU_VFP_V4_SP_D16),
+	       FPU_ARCH_VFP_V4_SP_D16,
+	       cortex_m4),
   ARM_CPU_OPT ("cortex-m3",	  "Cortex-M3",	       ARM_ARCH_V7M,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_SOFTVFP),
@@ -30883,28 +31268,47 @@ static const struct arm_cpu_option_table arm_cpus[] =
   ARM_CPU_OPT ("cortex-m0plus",	  "Cortex-M0+",	       ARM_ARCH_V6SM,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_SOFTVFP),
-  ARM_CPU_OPT ("cortex-x1",   "Cortex-X1",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
-	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-x1c",   "Cortex-X1C",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
-	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("exynos-m1",	  "Samsung Exynos M1", ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("neoverse-n1",    "Neoverse N1",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
-  ARM_CPU_OPT ("neoverse-n2",	 "Neoverse N2",	       ARM_ARCH_V8_5A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
-				    | ARM_EXT2_BF16
-				    | ARM_EXT2_I8MM),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4),
-  ARM_CPU_OPT ("neoverse-v1", "Neoverse V1", ARM_ARCH_V8_4A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
-				    | ARM_EXT2_BF16
-				    | ARM_EXT2_I8MM),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4),
+  ARM_CPU_OPT2 ("cortex-x1",   "Cortex-X1",	       ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       cortex_x1),
+  ARM_CPU_OPT2 ("cortex-x1c",   "Cortex-X1C",	       ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       cortex_x1c),
+  ARM_CPU_OPT2 ("exynos-m1",	  "Samsung Exynos M1", ARM_ARCH_V8A,
+	       ARM_FEATURE (0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+         FPU_ARCH_NEON_VFP_ARMV8,
+	       exynos_m1),
+  ARM_CPU_OPT2 ("neoverse-n1",	 "Neoverse N1",	       ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       neoverse_n1),
+  ARM_CPU_OPT2 ("ares",    "Ares",	       ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       neoverse_n1),
+  ARM_CPU_OPT2 ("neoverse-n2",	 "Neoverse N2",	       ARM_ARCH_V9A,
+	       ARM_FEATURE(0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML |
+	       ARM_EXT2_BF16 | ARM_EXT2_I8MM,
+	       FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8 |
+	       FPU_NEON_EXT_DOTPROD | FPU_NEON_EXT_RDMA),
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       neoverse_n2),
+  ARM_CPU_OPT2 ("cortex-a710",	 "Cortex-A710",	   ARM_ARCH_V9A,
+	       ARM_FEATURE(0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML |
+		              ARM_EXT2_BF16 | ARM_EXT2_I8MM,
+			      FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8 |
+			      FPU_NEON_EXT_DOTPROD | FPU_NEON_EXT_RDMA),
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       cortex_a710),
+  ARM_CPU_OPT2 ("neoverse-v1",	 "Neoverse V1",	       ARM_ARCH_V8_4A,
+	       ARM_FEATURE(0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML |
+			      ARM_EXT2_BF16 | ARM_EXT2_I8MM,
+			      FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8 |
+			      FPU_NEON_EXT_DOTPROD),
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       neoverse_v1),
   /* ??? XSCALE is really an architecture.  */
   ARM_CPU_OPT ("xscale",	  NULL,		       ARM_ARCH_XSCALE,
 	       ARM_ARCH_NONE,
@@ -30928,31 +31332,24 @@ static const struct arm_cpu_option_table arm_cpus[] =
 
   /* Marvell processors.  */
   ARM_CPU_OPT ("marvell-pj4",	  NULL,		       ARM_ARCH_V7A,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
-	       FPU_ARCH_VFP_V3D16),
+	       ARM_FEATURE (ARM_EXT_MP | ARM_EXT_SEC, 0, FPU_VFP_V3),
+	       FPU_ARCH_VFP_V3),
   ARM_CPU_OPT ("marvell-whitney", NULL,		       ARM_ARCH_V7A,
 	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
 	       FPU_ARCH_NEON_VFP_V4),
 
   /* APM X-Gene family.  */
   ARM_CPU_OPT ("xgene1",	  "APM X-Gene 1",      ARM_ARCH_V8A,
-	       ARM_ARCH_NONE,
+	       ARM_FEATURE (0, 0, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
 	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
   ARM_CPU_OPT ("xgene2",	  "APM X-Gene 2",      ARM_ARCH_V8A,
 	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
 	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
 
-  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL, NULL }
 };
 #undef ARM_CPU_OPT
-
-struct arm_ext_table
-{
-  const char *		  name;
-  size_t		  name_len;
-  const arm_feature_set	  merge;
-  const arm_feature_set	  clear;
-};
+#undef ARM_CPU_OPT2
 
 struct arm_arch_option_table
 {
@@ -30963,16 +31360,6 @@ struct arm_arch_option_table
   const struct arm_ext_table *	ext_table;
 };
 
-/* Used to add support for +E and +noE extension.  */
-#define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
-/* Used to add support for a +E extension.  */
-#define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
-/* Used to add support for a +noE extension.  */
-#define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
-
-#define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
-			    ~0 & ~FPU_ENDIAN_PURE)
-
 static const struct arm_ext_table armv5te_ext_table[] =
 {
   ARM_EXT ("fp", FPU_ARCH_VFP_V2, ALL_FP),
@@ -31169,16 +31556,6 @@ static const struct arm_ext_table armv9a_ext_table[] =
 #define armv94a_ext_table armv93a_ext_table
 #define armv95a_ext_table armv94a_ext_table
 
-#define CDE_EXTENSIONS \
-  ARM_ADD ("cdecp0", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE0)), \
-  ARM_ADD ("cdecp1", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE1)), \
-  ARM_ADD ("cdecp2", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE2)), \
-  ARM_ADD ("cdecp3", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE3)), \
-  ARM_ADD ("cdecp4", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE4)), \
-  ARM_ADD ("cdecp5", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE5)), \
-  ARM_ADD ("cdecp6", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE6)), \
-  ARM_ADD ("cdecp7", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE7))
-
 static const struct arm_ext_table armv8m_main_ext_table[] =
 {
   ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP),
@@ -31755,7 +32132,7 @@ arm_parse_cpu (const char *str)
 	  }
 
 	if (ext != NULL)
-	  return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, NULL);
+	  return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, opt->ext_table);
 
 	return true;
       }
diff --git a/gas/testsuite/gas/arm/command-line-mcpu.exp b/gas/testsuite/gas/arm/command-line-mcpu.exp
new file mode 100644
index 00000000000..fc52296f882
--- /dev/null
+++ b/gas/testsuite/gas/arm/command-line-mcpu.exp
@@ -0,0 +1,134 @@
+
+if {[istarget arm*-*-*]} {
+    gas_test_old "feat-mp.s" "-mcpu=cortex-a5" "gas/arm: cortex-a5 feat-mp"
+    gas_test_old "feat-sec.s" "-mcpu=cortex-a5" "gas/arm: cortex-a5 feat-sec"
+    gas_test_old "feat-neon-fp16.s" "-mcpu=cortex-a5" "gas/arm: cortex-a5 feat-neon-fp16"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a5+nofp+nosimd" "gas/arm: cortex-a5 exts"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a7" "gas/arm: cortex-a7 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a7+nofp+nosimd" "gas/arm: cortex-a7 exts"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a8" "gas/arm: cortex-a8 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a8+nofp" "gas/arm: cortex-a8 exts"
+    gas_test_old "feat-mp.s" "-mcpu=cortex-a9" "gas/arm: cortex-a9 feat-mp"
+    gas_test_old "feat-sec.s" "-mcpu=cortex-a9" "gas/arm: cortex-a9 feat-sec"
+    gas_test_old "feat-neon-fp16.s" "-mcpu=cortex-a9" "gas/arm: cortex-a9 feat-neon-fp16"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a9+nofp+nosimd" "gas/arm: cortex-a9 exts"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a12" "gas/arm: cortex-a12 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a12+nofp" "gas/arm: cortex-a12 exts"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a15" "gas/arm: cortex-a15 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a15+nofp" "gas/arm: cortex-a15 exts"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a17" "gas/arm: cortex-a17 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a17+nofp" "gas/arm: cortex-a17 exts"
+    gas_test_old "feat-mp.s" "-mcpu=marvell-pj4" "gas/arm: marvell-pj4 feat-mp"
+    gas_test_old "feat-sec.s" "-mcpu=marvell-pj4" "gas/arm: marvell-pj4 feat-sec"
+    gas_test_old "feat-fp-vfpv3.s" "-mcpu=marvell-pj4" "gas/arm: marvell-pj4 feat-fp-vfpv3"
+    gas_test_old "feat-fp-vfpv3.s" "-mcpu=cortex-r4f" "gas/arm: cortex-r4f feat-fp-vfpv3"
+    gas_test_old "feat-fp-vfpv3.s" "-mcpu=cortex-r5" "gas/arm: cortex-r5 feat-fp-vfpv3"
+    gas_test_old "feat-idiv.s" "-mcpu=cortex-r5" "gas/arm: cortex-r5 feat-idiv"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-r5+nofp+nofp.dp" "gas/arm: cortex-r5 exts"
+    gas_test_old "feat-idiv.s" "-mcpu=cortex-r7" "gas/arm: cortex-r7 feat-idiv"
+    gas_test_old "feat-vfpv3-d16-fp16.s" "-mcpu=cortex-r7" "gas/arm: cortex-r7 feat-vfpv3-d16-fp16"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-r7+nofp+nofp.dp" "gas/arm: cortex-r7 exts"
+    gas_test_old "feat-idiv.s" "-mcpu=cortex-r8" "gas/arm: cortex-r8 feat-idiv"
+    gas_test_old "feat-vfpv3-d16-fp16.s" "-mcpu=cortex-r8" "gas/arm: cortex-r8 feat-vfpv3-d16-fp16"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-r8+nofp+nofp.dp" "gas/arm: cortex-r8 exts"
+    gas_test_old "feat-fp-vfpv3.s" "-mcpu=cortex-m4" "gas/arm: cortex-m4 feat-fp-vfpv3"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-m4+nofp" "gas/arm: cortex-m4 exts"
+    gas_test_old "feat-fp.dp.s" "-mcpu=cortex-m7" "gas/arm: cortex-m7 feat-fp.dp"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-m7+nofp+nofp.dp" "gas/arm: cortex-m7 exts"
+    gas_test_old "feat-crc.s" "-mcpu=cortex-a32" "gas/arm: cortex-a32 feat-crc"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a32" "gas/arm: cortex-a32 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a32+nofp" "gas/arm: cortex-a32 exts"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a32+crypto" "gas/arm: cortex-a32 exts"
+    gas_test_old "feat-crc.s" "-mcpu=cortex-a35" "gas/arm: cortex-a35 feat-crc"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a35" "gas/arm: cortex-a35 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a35+nofp" "gas/arm: cortex-a35 exts"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a35+crypto" "gas/arm: cortex-a35 exts"
+    gas_test_old "feat-crc.s" "-mcpu=cortex-a53" "gas/arm: cortex-a53 feat-crc"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a53" "gas/arm: cortex-a53 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a53+nofp" "gas/arm: cortex-a53 exts"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a53+crypto" "gas/arm: cortex-a53 exts"
+    gas_test_old "feat-crc.s" "-mcpu=cortex-a57" "gas/arm: cortex-a57 feat-crc"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a57" "gas/arm: cortex-a57 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a57+crypto" "gas/arm: cortex-a57 exts"
+    gas_test_old "feat-crc.s" "-mcpu=cortex-a72" "gas/arm: cortex-a72 feat-crc"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a72" "gas/arm: cortex-a72 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a72+crypto" "gas/arm: cortex-a72 exts"
+    gas_test_old "feat-crc.s" "-mcpu=cortex-a73" "gas/arm: cortex-a73 feat-crc"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a73" "gas/arm: cortex-a73 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a73+crypto" "gas/arm: cortex-a73 exts"
+    gas_test_old "feat-crc.s" "-mcpu=exynos-m1" "gas/arm: exynos-m1 feat-crc"
+    gas_test_old "feat-simd.s" "-mcpu=exynos-m1" "gas/arm: exynos-m1 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=exynos-m1+crypto" "gas/arm: exynos-m1 exts"
+    gas_test_old "feat-simd.s" "-mcpu=xgene1" "gas/arm: xgene1 feat-simd"
+    gas_test_old "feat-crc.s" "-mcpu=cortex-r52" "gas/arm: cortex-r52 feat-crc"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-r52" "gas/arm: cortex-r52 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-r52+nofp.dp" "gas/arm: cortex-r52 exts"
+    gas_test_old "feat-crc.s" "-mcpu=cortex-r52plus" "gas/arm: cortex-r52plus feat-crc"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-r52plus" "gas/arm: cortex-r52plus feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-r52plus+nofp.dp" "gas/arm: cortex-r52plus exts"
+    gas_test_old "feat-dsp.s" "-mcpu=cortex-m33" "gas/arm: cortex-m33 feat-dsp"
+    gas_test_old "feat-fp-vfpv5.s" "-mcpu=cortex-m33" "gas/arm: cortex-m33 feat-fp-vfpv5"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-m33+nofp+nodsp" "gas/arm: cortex-m33 exts"
+    gas_test_old "feat-dsp.s" "-mcpu=cortex-m35p" "gas/arm: cortex-m35p feat-dsp"
+    gas_test_old "feat-fp-vfpv5.s" "-mcpu=cortex-m35p" "gas/arm: cortex-m35p feat-fp-vfpv5"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-m35p+nofp+nodsp" "gas/arm: cortex-m35p exts"
+    gas_test_old "feat-pacbti.s" "-mcpu=cortex-m52" "gas/arm: cortex-m52 feat-pacbti"
+    gas_test_old "feat-mve.fp.s" "-mcpu=cortex-m52" "gas/arm: cortex-m52 feat-mve.fp"
+    gas_test_old "feat-fp.dp.s" "-mcpu=cortex-m52" "gas/arm: cortex-m52 feat-fp.dp"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-m52+nopacbti+nomve.fp+nomve+nofp+nodsp" "gas/arm: cortex-m52 exts"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-m52+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7" "gas/arm: cortex-m52 exts"
+    gas_test_old "feat-mve.fp.s" "-mcpu=cortex-m55" "gas/arm: cortex-m55 feat-mve.fp"
+    gas_test_old "feat-fp.dp.s" "-mcpu=cortex-m55" "gas/arm: cortex-m55 feat-fp.dp"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-m55+nomve.fp+nomve+nofp+nodsp" "gas/arm: cortex-m55 exts"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-m55+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7" "gas/arm: cortex-m55 exts"
+    gas_test_old "feat-pacbti.s" "-mcpu=cortex-m85" "gas/arm: cortex-m85 feat-pacbti"
+    gas_test_old "feat-mve.fp.s" "-mcpu=cortex-m85" "gas/arm: cortex-m85 feat-mve.fp"
+    gas_test_old "feat-fp.dp.s" "-mcpu=cortex-m85" "gas/arm: cortex-m85 feat-fp.dp"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-m85+nopacbti+nomve.fp+nomve+nofp+nodsp" "gas/arm: cortex-m85 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-a55" "gas/arm: cortex-a55 feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a55" "gas/arm: cortex-a55 feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a55+nofp" "gas/arm: cortex-a55 exts"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a55+crypto" "gas/arm: cortex-a55 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-a75" "gas/arm: cortex-a75 feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a75" "gas/arm: cortex-a75 feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a75+crypto" "gas/arm: cortex-a75 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-a76" "gas/arm: cortex-a76 feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a76" "gas/arm: cortex-a76 feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a76+crypto" "gas/arm: cortex-a76 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-a76ae" "gas/arm: cortex-a76ae feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a76ae" "gas/arm: cortex-a76ae feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a76ae+crypto" "gas/arm: cortex-a76ae exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-a77" "gas/arm: cortex-a77 feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a77" "gas/arm: cortex-a77 feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a77+crypto" "gas/arm: cortex-a77 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-a78" "gas/arm: cortex-a78 feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a78" "gas/arm: cortex-a78 feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a78+crypto" "gas/arm: cortex-a78 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-a78ae" "gas/arm: cortex-a78ae feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a78ae" "gas/arm: cortex-a78ae feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a78ae+crypto" "gas/arm: cortex-a78ae exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-a78c" "gas/arm: cortex-a78c feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a78c" "gas/arm: cortex-a78c feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a78c+crypto" "gas/arm: cortex-a78c exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-x1" "gas/arm: cortex-x1 feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-x1" "gas/arm: cortex-x1 feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-x1+crypto" "gas/arm: cortex-x1 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-x1c" "gas/arm: cortex-x1c feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-x1c" "gas/arm: cortex-x1c feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-x1c+crypto" "gas/arm: cortex-x1c exts"
+    gas_test_old "feat-fp16.s" "-mcpu=neoverse-n1" "gas/arm: neoverse-n1 feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=neoverse-n1" "gas/arm: neoverse-n1 feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=neoverse-n1+crypto" "gas/arm: neoverse-n1 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=neoverse-v1" "gas/arm: neoverse-v1 feat-fp16"
+    gas_test_old "feat-bf16.s" "-mcpu=neoverse-v1" "gas/arm: neoverse-v1 feat-bf16"
+    gas_test_old "feat-i8mm.s" "-mcpu=neoverse-v1" "gas/arm: neoverse-v1 feat-i8mm"
+    gas_test_old "nop-asm.s" "-mcpu=neoverse-v1+crypto" "gas/arm: neoverse-v1 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-a710" "gas/arm: cortex-a710 feat-fp16"
+    gas_test_old "feat-bf16.s" "-mcpu=cortex-a710" "gas/arm: cortex-a710 feat-bf16"
+    gas_test_old "feat-i8mm.s" "-mcpu=cortex-a710" "gas/arm: cortex-a710 feat-i8mm"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a710+crypto" "gas/arm: cortex-a710 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=neoverse-n2" "gas/arm: neoverse-n2 feat-fp16"
+    gas_test_old "feat-bf16.s" "-mcpu=neoverse-n2" "gas/arm: neoverse-n2 feat-bf16"
+    gas_test_old "feat-i8mm.s" "-mcpu=neoverse-n2" "gas/arm: neoverse-n2 feat-i8mm"
+    gas_test_old "nop-asm.s" "-mcpu=neoverse-n2+crypto" "gas/arm: neoverse-n2 exts"
+}
diff --git a/gas/testsuite/gas/arm/feat-bf16.s b/gas/testsuite/gas/arm/feat-bf16.s
new file mode 100644
index 00000000000..46fc48ba567
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-bf16.s
@@ -0,0 +1,5 @@
+.syntax unified
+.thumb
+
+@ feat FP16
+vdot.bf16 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/feat-crc.s b/gas/testsuite/gas/arm/feat-crc.s
new file mode 100644
index 00000000000..671ac14ebcb
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-crc.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat CRC
+crc32w  r0, r0, r1
diff --git a/gas/testsuite/gas/arm/feat-dotprod.s b/gas/testsuite/gas/arm/feat-dotprod.s
new file mode 100644
index 00000000000..775c3ba4c02
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-dotprod.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat DOTPROD
+vudot.u8 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/feat-dsp.s b/gas/testsuite/gas/arm/feat-dsp.s
new file mode 100644
index 00000000000..2f54c7327d1
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-dsp.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat DSP
+smlad   r0, r1, r2, r3
diff --git a/gas/testsuite/gas/arm/feat-fp-vfpv3.s b/gas/testsuite/gas/arm/feat-fp-vfpv3.s
new file mode 100644
index 00000000000..4435db35690
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-fp-vfpv3.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat FP (VFP-v3)
+vmla.f32 s0, s1, s2
diff --git a/gas/testsuite/gas/arm/feat-fp-vfpv5.s b/gas/testsuite/gas/arm/feat-fp-vfpv5.s
new file mode 100644
index 00000000000..13a2e7aca9e
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-fp-vfpv5.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat FP (VFP-v5)
+vfma.f32 s0, s1, s2
diff --git a/gas/testsuite/gas/arm/feat-fp.dp.s b/gas/testsuite/gas/arm/feat-fp.dp.s
new file mode 100644
index 00000000000..34b68cd8603
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-fp.dp.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat FP.DP
+vadd.f64 d0, d1, d2
diff --git a/gas/testsuite/gas/arm/feat-fp.s b/gas/testsuite/gas/arm/feat-fp.s
new file mode 100644
index 00000000000..5cf49af0e9f
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-fp.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat FP
+vadd.f32 s0, s1, s2
diff --git a/gas/testsuite/gas/arm/feat-fp16.s b/gas/testsuite/gas/arm/feat-fp16.s
new file mode 100644
index 00000000000..6780678e8ca
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-fp16.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat FP16
+vadd.f16 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/feat-i8mm.s b/gas/testsuite/gas/arm/feat-i8mm.s
new file mode 100644
index 00000000000..bb3818726a8
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-i8mm.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat I8MM
+vusmmla.s8  q6, q7, q8
diff --git a/gas/testsuite/gas/arm/feat-idiv.s b/gas/testsuite/gas/arm/feat-idiv.s
new file mode 100644
index 00000000000..8b289fa817d
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-idiv.s
@@ -0,0 +1,3 @@
+.syntax unified
+
+sdiv r0, r1, r2
diff --git a/gas/testsuite/gas/arm/feat-mp.s b/gas/testsuite/gas/arm/feat-mp.s
new file mode 100644
index 00000000000..db365d7f282
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-mp.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat MP
+ldrex r0, [r1]
diff --git a/gas/testsuite/gas/arm/feat-mve.fp.s b/gas/testsuite/gas/arm/feat-mve.fp.s
new file mode 100644
index 00000000000..81c23300dc3
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-mve.fp.s
@@ -0,0 +1,5 @@
+.syntax unified
+.thumb
+
+@ MVE.FP
+vmul.f32 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/feat-neon-fp16.s b/gas/testsuite/gas/arm/feat-neon-fp16.s
new file mode 100644
index 00000000000..55ab08553bf
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-neon-fp16.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat NEON-FP16
+vadd.f16 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/feat-pacbti.s b/gas/testsuite/gas/arm/feat-pacbti.s
new file mode 100644
index 00000000000..2399f0ca230
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-pacbti.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ PACBTI
+pac     r12, lr, sp
diff --git a/gas/testsuite/gas/arm/feat-sec.s b/gas/testsuite/gas/arm/feat-sec.s
new file mode 100644
index 00000000000..bdb516a30f4
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-sec.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat SEC
+smc     #0
diff --git a/gas/testsuite/gas/arm/feat-simd.s b/gas/testsuite/gas/arm/feat-simd.s
new file mode 100644
index 00000000000..871f5490902
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-simd.s
@@ -0,0 +1,5 @@
+.syntax unified
+.text
+
+@ feat SIMD
+vadd.i32 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s b/gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s
new file mode 100644
index 00000000000..41ccd2d9414
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat VFP3-D16-FP16
+vcvtt.f16.f32 s0, s1
-- 
2.43.0


From gnutoolsweekly@gmail.com  Mon Jun  8 20:56:02 2026
From: gnutoolsweekly@gmail.com (GNU Tools weekly)
Date: Mon, 8 Jun 2026 13:56:02 -0700
Subject: GNU Tools Weekly News Week 41 (June 7, 2026)
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GNU Tools Weekly News Week 41 (June 7, 2026)

Release updates for GNU toolchain:
 *  GCC 15 branch is frozen for GCC 15.3.0 release
  * https://inbox.sourceware.org/gcc/r5sqpn09-8rp9-on1p-8057-s6r27567po33@fhfr.qr/
 * GCC 15.3.0 RC1 was done
  * https://inbox.sourceware.org/gcc/69201op6-q894-on55-5r62-32p5498pp1sr@fhfr.qr/
 * Schedule for the [glibc] 2.44 release
  * https://inbox.sourceware.org/libc-alpha/2jU_525XQE24wF-uVam5ug@gentoo.org/

GNU toolchain conference reminders:
 * FOSSY 2026 toolchain track North America, Aug 6-9 (Vancouver, Canada)
 * GNU Tools Cauldron 2026, Fri-Sun, October 2-4 (Prague, Czechia)
  * https://gcc.gnu.org/wiki/cauldron2026
  * https://conf.gnu-tools-cauldron.org/prg26/cfp
 * Toolchains Track at LPC 2026, October 7th (Prague, Czechia)
  * https://lpc.events/event/20/abstracts/

General/big GNU toolchain news (including sourceware news):
 * GCC AI policy working group - 2026-06-05
  * https://inbox.sourceware.org/gcc/CAH6eHdTQYgaaGJomvr1fgoCJazJZb3hRuT+fgJ_BZriQBFANng@mail.gmail.com/
  * http://gcc.gnu.org/wiki/working-group-ai-policy

GCC easy issue to tackle of the week:
 * MAX(x, -1) can use orr with ash operand (aarch64)
  * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125640
  * This one is different from previous weeks; a target specific improvement
    * the Compile Farm has a few aarch64 machines that can be used for
building/testing on
    * https://gcc.gnu.org/wiki/CompileFarm
  * Reach out to Andrea Pinski <andrew.pinski@oss.qualcomm.com> for
mentoring on this issue.
  * Previous ones are listed on https://gcc.gnu.org/wiki/EasyIssuesOfTheWeek

GCC commits:
 * https://gcc.gnu.org/r17-1051 - r17-1416 :  365 commits
 * Summary of Ada changes (Thanks Marc)
  * Bug fixes and code cleanup
  * Document the Ref attribute + other documentation cleanup
  * Adjust some compiler diagnostics
  * Implement AI12-0331 Binding Interpretation
  * Flare's constructor fix and improvements
  * Support for Constant_Reference in Iterable aspect and update
corresponding documentation.
  * Fix conformance with RM where an incorrect exception was raised in
some IO  procedures.
 * Removal of all of the -Wstrict-overflow code
  * https://gcc.gnu.org/r17-1051 ... https://gcc.gnu.org/r17-1058 and
https://gcc.gnu.org/r17-1151
 * Rust FE merge
  * https://gcc.gnu.org/r17-1072 ... https://gcc.gnu.org/r17-1090
 * RISC-V: Add zvfofp8min ISA extension support
  * https://gcc.gnu.org/r17-1226-g8bef821de3b31c
 * aarch64: Make Uc[ij] constraints public
  * https://gcc.gnu.org/r17-1254-g090f3e78a10b5c
 * RISC-V: Add XuanTie C908 tuning and scheduler model
  * https://gcc.gnu.org/r17-1270-g980ea5fb524173
 * cselim: Allow middle_bb to have more than one statement
  * https://gcc.gnu.org/r17-1273-g391ee229b737eb
 * Add __builtin_{bswap,bitreverse}g type-generic builtins
  * https://gcc.gnu.org/r17-1367-g9ab08d664545bc
 * forge: Add a prototype CODEOWNERS file
  * https://gcc.gnu.org/r17-1378-g293f343e2ce8b6

GCC discussion:
 *

GCC bugzilla stats
 * 115 new issues filed
 * 75 issues closed

glibc commits:
 * riscv: Add RVV memcmp, memccpy, memchr, strchr, and strrchr for
both multiarch and non-multiarch builds
  * https://sourceware.org/cgit/glibc/log/?id=2efc7026287273b4b3a1ce1a7b27791d3d860a5c&qt=range&q=c275c424b324ea525a526812ba2b4a56d47bfe61...2efc7026287273b4b3a1ce1a7b27791d3d860a5c
 *
glibc discussion:
 *
binutils/gdb commits:
 * gdb/aarch64: record/replay support for LRCPC3
  * https://sourceware.org/cgit/binutils-gdb/commit/?id=ec6bbd2e0cb4d141db9048b0b5d5c0bcaa66c284
 *
gdb discussion:
 * RFC: prototype of C extensions using the Python limited API
  * https://inbox.sourceware.org/gdb/21479c1d-3a9a-4ae2-bc1a-5dc19871f275@arm.com/

binutils discussion:
 *

From sam@gentoo.org  Mon Jun  8 22:55:49 2026
From: sam@gentoo.org (Sam James)
Date: Mon, 08 Jun 2026 23:55:49 +0100
Subject: GNU Binutils release 2.46.1 is now available
Message-ID: <87y0gohcay.fsf@gentoo.org>

Hi,

We are pleased to announce that version 2.46.1 of the GNU Binutils
project sources have been released and are now available for download at:

    https://ftp.gnu.org/gnu/binutils
    https://sourceware.org/pub/binutils/releases/

This release is signed by my key:

  pub   rsa4096/0x1F3D03348DB1A3E2 2020-03-04 [C]
        Key fingerprint = 5EF3 A411 71BB 77E6 110E  D2D0 1F3D 0334 8DB1 A3E2
  uid                   [ultimate] Sam James <sam@cmpct.info>
  uid                   [ultimate] Sam James <sam@gentoo.org>
  uid                   [ultimate] Sam James <sjames@sourceware.org>
        Key fingerprint = 60EA 4FBF FB83 5333 9CAA  D4F2 F492 2810 EEA0 483B
        Key fingerprint = DF1D 4946 63A9 7AC5 66CA  42B2 58AC 1BFA 75E5 6A76
        Key fingerprint = 922B A006 C9D9 A556 0F62  6473 870C 05CA 5294 50D3
        Key fingerprint = 165E 63C6 75E6 63F7 CCFD  E923 8771 8F61 0A3F 8A87
        Key fingerprint = 25A6 BB88 DD9B 764C 6B55  41C2 7384 09F5 20DF 9190
        Key fingerprint = CA59 4D4A 1F00 898E 3019  3C54 5861 1564 C7C4 D9D4

You can obtain my key via:

  gpg --recv-keys 5EF3A41171BB77E6110ED2D01F3D03348DB1A3E2

Or as a last resort to find the key, you can try the official GNU
keyring:

  wget -q https://ftp.gnu.org/gnu/gnu-keyring.gpg
  gpg --keyring gnu-keyring.gpg --verify binutils-2.46.1.tar.gz.sig
(etc)

This is a point release over the previous 2.46 version, containing bug
fixes.

Our thanks go out to all of the binutils contributors, past and
present, for helping to make this release possible.

Here is a list of the bugs that have been fixed:
     PR34028
     PR34088
     PR34125

sam
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From sam@gentoo.org  Tue Jun  9 01:19:42 2026
From: sam@gentoo.org (Sam James)
Date: Tue, 09 Jun 2026 02:19:42 +0100
Subject: Planned binutils-2.46.1 release
In-Reply-To: <agQ8EH3YIJ6C2dUs@squeak.grove.modra.org>
References: <87o6ilgdrj.fsf@gentoo.org> <87se7wfp9f.fsf@gentoo.org>
 <agQ8EH3YIJ6C2dUs@squeak.grove.modra.org>
Message-ID: <877bo8h5n5.fsf@gentoo.org>

Alan Modra <amodra@gmail.com> writes:

> On Tue, May 12, 2026 at 07:37:16PM +0100, Sam James wrote:
>> Sam James <sam@gentoo.org> writes:
>> 
>> > Hi all,
>> >
>> > I plan to make a point release for binutils-2.46 in a few days,
>> > motivated by the C23/glibc-2.43 fixes for const correctness, as the 2.46
>> > release fails to build w/ -Werror enabled by default [0].
>> >
>> > Please look to see if any other fixes should be backported to
>> > binutils-2_46-branch.
>> >
>> > Right now, there are fixes there for:
>> > * PR34028
>> > * PR34088
>> > * PR34125
>> >
>> > I don't think there's anything else which needs to go in but I may well
>> > have missed something. Thanks in advance.
>> 
>> Maybe this one, given it makes the migration from v2->v3 much nicer:
>> 
>> commit 7c80233f4d47c2508d8984bdcfc644b9a6e7bf9a
>> Author:     Alan Modra <amodra@gmail.com>
>> AuthorDate: Fri Mar 13 08:55:04 2026 +1030
>> Commit:     Alan Modra <amodra@gmail.com>
>> CommitDate: Fri Mar 13 08:55:04 2026 +1030
>> 
>>     check sframe version in _bfd_elf_parse_sframe
>>     ...
>
> Fair enough.

Thanks for handling it Alan, and sorry for taking a while.

>
>> It would need a slight tweak to apply cleanly or we just include
>> 9eae5ed721cd117c492fcb4516724bf093d4ea2d and
>> 3949fb481a6739dc1f4dc5fad09d7646c90af3d2 as well.
>
> As a general principle I don't recommend backporting fuzzing fixes or
> "not freed before exit" type memory leak fixes, unless backporting
> them makes it a lot easier to backport some other wanted fix.

Ack.

>
>> Anyway, any opinions Alan or Indu?
>> 
>> >
>> > [0] https://inbox.sourceware.org/binutils/c4e611d0-2ef2-4495-8623-7ec82df3f101@gmail.com/
>> >
>> > sam
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From evgeny.karpov@arm.com  Tue Jun  9 07:19:51 2026
From: evgeny.karpov@arm.com (Evgeny Karpov)
Date: Tue, 9 Jun 2026 09:19:51 +0200
Subject: [PATCH v7 3/3] aarch64: Implement Structured Exception Handling
 (SEH) on AArch64
In-Reply-To: <41b74ae8-7d3c-485e-9428-5a2e726500ca@arm.com>
References: <20260319111638.93074-1-evgeny.karpov@arm.com>
 <20260319111638.93074-4-evgeny.karpov@arm.com>
 <41b74ae8-7d3c-485e-9428-5a2e726500ca@arm.com>
Message-ID: <aie-l4-Kkq6ZpROJ@arm.com>

On Thu, 26 Mar 2026, Saurabh Jha wrote:
> > +
> > +      seh_ctx_cur->handler.X_op = O_constant;
> > +      seh_ctx_cur->handler.X_add_number = 0;
> > +
> > +      if (strcasecmp (symbol_name, "@0") == 0
> > +	  || strcasecmp (symbol_name, "@null") == 0)
> > +	;
>
> If we're not doing anything in this if body, why do we have it? Is it to be
> able to write the bottom conditionals in an easier way?yhn

It makes sense to change. The condition will be rewritten.

> > +  return true;
> > +}
> > +
> > +/* Write out the xdata information for one function.  */
> > +static void
> > +seh_aarch64_write_function_xdata (struct seh_aarch64_context *seh_ctx)
> > +{
> 
> Is there a way to break down this function? Perhaps around your conditionals
> inside the while (true) loop?

xdata record writing will be moved to a separate function.

> > +   pdata record is not implemented yet.  */
> > +
> > +#ifndef OBJ_COFF_SEH_AARCH64_H
> > +#define OBJ_COFF_SEH_AARCH64_H
> > +
> > +typedef enum seh_aarch64_unwind_types
> > +{
> 
> Can you add a link to the documentation of the unwind types?

The link to the documentation will be added.

Regards,
Evgeny


From ro@CeBiTec.Uni-Bielefeld.DE  Tue Jun  9 08:03:58 2026
From: ro@CeBiTec.Uni-Bielefeld.DE (Rainer Orth)
Date: Tue, 09 Jun 2026 10:03:58 +0200
Subject: [PATCH] gprof: Fix tests on Solaris [PR34237]
Message-ID: <yddldconnrl.fsf@CeBiTec.Uni-Bielefeld.DE>

The gprof tests FAIL on Solaris:

tst-gmon-gprof.sh ../gprof tst-gmon
--- expected
+++ actual
@@ -1,3 +1,4 @@
 f1 2000
 f2 1000
 f3 1
+main 1
FAIL

main is included in the call graph, probably because Solaris still uses
the original BSD gmon.out format.

This patch allows for that difference.  To distinguish between targets
with non-default handling, $target is passed to the test scripts.

As detailed in the PR, the powerpc with function descriptors special
case only applies to AIX, so that variant is guarded accordingly.

Tested on amd64-pc-solaris2.11, sparcv9-sun-solaris2.11, and
x86_64-pc-linux-gnu.

Ok for trunk?

	Rainer

-- 
-----------------------------------------------------------------------------
Rainer Orth, Center for Biotechnology, Bielefeld University


2026-06-08  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>

	gprof:
	PR gprof/34237
	* testsuite/Makefile.am (tst-gmon-gprof.out): Pass $(target) to
	tst-gmon-gprof.sh.
	(tst-gmon-gprof-l.out): Likewise.
	(tst-gmon-gprof-l2.out): Likewise.
	* testsuite/Makefile.in: Regenerate.

	* testsuite/tst-gmon-gprof.sh (expected_dot): Remove.
	<*-*-solaris2*>: Allow main in execution counters.
	<powerpc-*-aix* | rs6000-*-aix*>: Handle function descriptor case here.
	* testsuite/tst-gmon-gprof-l.sh: Likewise.
	* testsuite/tst-gmon-gprof-l2.sh: Likewise.

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From sivan.shani@arm.com  Tue Jun  9 10:39:42 2026
From: sivan.shani@arm.com (Sivan Shani)
Date: Tue, 9 Jun 2026 10:39:42 +0000
Subject: [PATCH v3] gas: arm - support CPU-specific extensions with -mcpu
In-Reply-To: <20260608145251.37337-1-sivan.shani@arm.com>
References: <20260608145251.37337-1-sivan.shani@arm.com>
Message-ID: <20260609104035.700121-1-sivan.shani@arm.com>

Add extension tables for -mcpu, similar to -march, allowing
CPU-specific extensions to be enabled and disabled using +ext and
+noext modifiers.

Update ARM CPU feature definitions to match GCC CPU baselines and
add tests covering supported CPU extension modifiers and feature
availability.


This is the 3'd patch:
Fixing a test file (attr-cpu-directive.d)

---
 gas/config/tc-arm.c                         | 687 +++++++++++++++-----
 gas/testsuite/gas/arm/attr-cpu-directive.d  |   2 +
 gas/testsuite/gas/arm/command-line-mcpu.exp | 134 ++++
 gas/testsuite/gas/arm/feat-bf16.s           |   5 +
 gas/testsuite/gas/arm/feat-crc.s            |   4 +
 gas/testsuite/gas/arm/feat-dotprod.s        |   4 +
 gas/testsuite/gas/arm/feat-dsp.s            |   4 +
 gas/testsuite/gas/arm/feat-fp-vfpv3.s       |   4 +
 gas/testsuite/gas/arm/feat-fp-vfpv5.s       |   4 +
 gas/testsuite/gas/arm/feat-fp.dp.s          |   4 +
 gas/testsuite/gas/arm/feat-fp.s             |   4 +
 gas/testsuite/gas/arm/feat-fp16.s           |   4 +
 gas/testsuite/gas/arm/feat-i8mm.s           |   4 +
 gas/testsuite/gas/arm/feat-idiv.s           |   3 +
 gas/testsuite/gas/arm/feat-mp.s             |   4 +
 gas/testsuite/gas/arm/feat-mve.fp.s         |   5 +
 gas/testsuite/gas/arm/feat-neon-fp16.s      |   4 +
 gas/testsuite/gas/arm/feat-pacbti.s         |   4 +
 gas/testsuite/gas/arm/feat-sec.s            |   4 +
 gas/testsuite/gas/arm/feat-simd.s           |   5 +
 gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s |   4 +
 21 files changed, 742 insertions(+), 155 deletions(-)
 create mode 100644 gas/testsuite/gas/arm/command-line-mcpu.exp
 create mode 100644 gas/testsuite/gas/arm/feat-bf16.s
 create mode 100644 gas/testsuite/gas/arm/feat-crc.s
 create mode 100644 gas/testsuite/gas/arm/feat-dotprod.s
 create mode 100644 gas/testsuite/gas/arm/feat-dsp.s
 create mode 100644 gas/testsuite/gas/arm/feat-fp-vfpv3.s
 create mode 100644 gas/testsuite/gas/arm/feat-fp-vfpv5.s
 create mode 100644 gas/testsuite/gas/arm/feat-fp.dp.s
 create mode 100644 gas/testsuite/gas/arm/feat-fp.s
 create mode 100644 gas/testsuite/gas/arm/feat-fp16.s
 create mode 100644 gas/testsuite/gas/arm/feat-i8mm.s
 create mode 100644 gas/testsuite/gas/arm/feat-idiv.s
 create mode 100644 gas/testsuite/gas/arm/feat-mp.s
 create mode 100644 gas/testsuite/gas/arm/feat-mve.fp.s
 create mode 100644 gas/testsuite/gas/arm/feat-neon-fp16.s
 create mode 100644 gas/testsuite/gas/arm/feat-pacbti.s
 create mode 100644 gas/testsuite/gas/arm/feat-sec.s
 create mode 100644 gas/testsuite/gas/arm/feat-simd.s
 create mode 100644 gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 3ff29542411..ef9b878dffc 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -30495,6 +30495,14 @@ const struct arm_legacy_option_table arm_legacy_opts[] =
   {NULL, NULL, ARM_ARCH_NONE, NULL}
 };
 
+struct arm_ext_table
+{
+  const char *		  name;
+  size_t		  name_len;
+  const arm_feature_set	  merge;
+  const arm_feature_set	  clear;
+};
+
 struct arm_cpu_option_table
 {
   const char *           name;
@@ -30507,11 +30515,339 @@ struct arm_cpu_option_table
   /* The canonical name of the CPU, or NULL to use NAME converted to upper
      case.  */
   const char *           canonical_name;
+  const struct arm_ext_table *	ext_table;
+};
+
+/* Used to add support for +E and +noE extension.  */
+#define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
+/* Used to add support for a +E extension.  */
+#define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
+/* Used to add support for a +noE extension.  */
+#define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
+
+#define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
+			    ~0 & ~FPU_ENDIAN_PURE)
+#define ALL_FP_MVE_FP ARM_FEATURE (0, (ARM_EXT2_FP16_INST		   \
+					| ARM_EXT2_FP16_FML		   \
+					| ARM_EXT2_MVE_FP),		   \
+				    ~0 & ~FPU_ENDIAN_PURE)
+#define ALL_SIMD ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA |     \
+				     FPU_NEON_EXT_ARMV8 | FPU_NEON_EXT_RDMA | \
+				     FPU_NEON_EXT_DOTPROD)
+
+#define CDE_EXTENSIONS \
+  ARM_ADD ("cdecp0", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE0)), \
+  ARM_ADD ("cdecp1", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE1)), \
+  ARM_ADD ("cdecp2", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE2)), \
+  ARM_ADD ("cdecp3", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE3)), \
+  ARM_ADD ("cdecp4", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE4)), \
+  ARM_ADD ("cdecp5", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE5)), \
+  ARM_ADD ("cdecp6", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE6)), \
+  ARM_ADD ("cdecp7", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE7))
+
+/* -mcpu extensions.  */
+static const struct arm_ext_table cortex_a5_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  ARM_REMOVE ("simd", ALL_SIMD),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a7_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  ARM_REMOVE ("simd", ALL_SIMD),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a8_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a9_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  ARM_REMOVE ("simd", ALL_SIMD),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a12_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a15_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a17_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_r5_ext_table[] =
+{
+  ARM_REMOVE ("fp",    ALL_FP),
+  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
+		      | FPU_VFP_EXT_ARMV8)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_r7_ext_table[] =
+{
+  ARM_REMOVE ("fp",    ALL_FP),
+  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
+		      | FPU_VFP_EXT_ARMV8)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_r8_ext_table[] =
+{
+  ARM_REMOVE ("fp",    ALL_FP),
+  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
+		      | FPU_VFP_EXT_ARMV8)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m4_ext_table[] =
+{
+  ARM_REMOVE ("fp",    ALL_FP),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m7_ext_table[] =
+{
+  ARM_REMOVE ("fp",    ALL_FP),
+  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
+		      | FPU_VFP_EXT_ARMV8)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a32_ext_table[] =
+{
+  ARM_REMOVE ("fp",     ALL_FP),
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a35_ext_table[] =
+{
+  ARM_REMOVE ("fp",     ALL_FP),
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a53_ext_table[] =
+{
+  ARM_REMOVE ("fp",     ALL_FP),
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a57_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a72_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a73_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table exynos_m1_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_r52_ext_table[] =
+{
+  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_D32 | FPU_VFP_EXT_ARMV8
+			| FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA
+			| FPU_NEON_EXT_ARMV8 | FPU_NEON_EXT_RDMA
+			| FPU_NEON_EXT_DOTPROD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_r52plus_ext_table[] =
+{
+  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_D32 | FPU_VFP_EXT_ARMV8
+			| FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA
+			| FPU_NEON_EXT_ARMV8 | FPU_NEON_EXT_RDMA
+			| FPU_NEON_EXT_DOTPROD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m33_ext_table[] =
+{
+  ARM_REMOVE ("fp",  ALL_FP),
+  ARM_REMOVE ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m35p_ext_table[] =
+{
+  ARM_REMOVE ("fp",  ALL_FP),
+  ARM_REMOVE ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m52_ext_table[] =
+{
+  ARM_REMOVE ("pacbti", ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI)),
+  ARM_REMOVE ("mve.fp", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP)),
+  ARM_REMOVE ("mve",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+  ARM_REMOVE ("fp",     ALL_FP_MVE_FP),
+  ARM_REMOVE ("dsp",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+  CDE_EXTENSIONS,
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m55_ext_table[] =
+{
+  ARM_REMOVE ("mve.fp", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP)),
+  ARM_REMOVE ("mve",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+  ARM_REMOVE ("fp",     ALL_FP_MVE_FP),
+  ARM_REMOVE ("dsp",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+  CDE_EXTENSIONS,
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m85_ext_table[] =
+{
+  ARM_REMOVE ("pacbti", ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI)),
+  ARM_REMOVE ("mve.fp", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP)),
+  ARM_REMOVE ("mve",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+  ARM_REMOVE ("fp",     ALL_FP_MVE_FP),
+  ARM_REMOVE ("dsp",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a55_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a75_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a76_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a76ae_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a77_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a78_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a78ae_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a78c_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_x1_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_x1c_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table neoverse_n1_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table neoverse_v1_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a710_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table neoverse_n2_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
+		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
 };
 
 /* This list should, at a minimum, contain all the cpu names
    recognized by GCC.  */
-#define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
+#define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN, NULL }
+#define ARM_CPU_OPT2(N, CN, V, E, DF, ext) \
+  { N, sizeof (N) - 1, V, E, DF, CN, ext##_ext_table }
 
 static const struct arm_cpu_option_table arm_cpus[] =
 {
@@ -30764,113 +31100,162 @@ static const struct arm_cpu_option_table arm_cpus[] =
   ARM_CPU_OPT ("arm1176jzf-s",	  NULL,		       ARM_ARCH_V6KZ,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_VFP_V2),
-  ARM_CPU_OPT ("cortex-a5",	  "Cortex-A5",	       ARM_ARCH_V7A,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
-	       FPU_ARCH_SOFTVFP),
-  ARM_CPU_OPT ("cortex-a7",	  "Cortex-A7",	       ARM_ARCH_V7VE,
-	       ARM_ARCH_NONE,
-	       FPU_ARCH_NEON_VFP_V4),
-  ARM_CPU_OPT ("cortex-a8",	  "Cortex-A8",	       ARM_ARCH_V7A,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
-	       ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
-  ARM_CPU_OPT ("cortex-a9",	  "Cortex-A9",	       ARM_ARCH_V7A,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
-	       ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
-  ARM_CPU_OPT ("cortex-a12",	  "Cortex-A12",	       ARM_ARCH_V7VE,
-	       ARM_ARCH_NONE,
-	       FPU_ARCH_NEON_VFP_V4),
-  ARM_CPU_OPT ("cortex-a15",	  "Cortex-A15",	       ARM_ARCH_V7VE,
-	       ARM_ARCH_NONE,
-	       FPU_ARCH_NEON_VFP_V4),
-  ARM_CPU_OPT ("cortex-a17",	  "Cortex-A17",	       ARM_ARCH_V7VE,
-	       ARM_ARCH_NONE,
-	       FPU_ARCH_NEON_VFP_V4),
-  ARM_CPU_OPT ("cortex-a32",	  "Cortex-A32",	       ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a35",	  "Cortex-A35",	       ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a53",	  "Cortex-A53",	       ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a55",    "Cortex-A55",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
-  ARM_CPU_OPT ("cortex-a57",	  "Cortex-A57",	       ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a72",	  "Cortex-A72",	       ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	      FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a73",	  "Cortex-A73",	       ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	      FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a75",    "Cortex-A75",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
-  ARM_CPU_OPT ("cortex-a76",    "Cortex-A76",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
-  ARM_CPU_OPT ("cortex-a76ae",    "Cortex-A76AE",      ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
-  ARM_CPU_OPT ("cortex-a77",    "Cortex-A77",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
-  ARM_CPU_OPT ("cortex-a78",   "Cortex-A78",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
-	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a78ae",   "Cortex-A78AE",	   ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
-	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a78c",   "Cortex-A78C",	   ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
-	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a710",   "Cortex-A710",	   ARM_ARCH_V9A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
-				    | ARM_EXT2_BF16
-				    | ARM_EXT2_I8MM),
-	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("ares",    "Ares",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
+  ARM_CPU_OPT2 ("cortex-a5",	  "Cortex-A5",	       ARM_ARCH_V7A,
+	       ARM_FEATURE (ARM_EXT_MP | ARM_EXT_SEC,
+	       ARM_EXT2_FP16_INST,
+	       FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA),
+	       FPU_ARCH_NEON_VFP_V4,
+	       cortex_a5),
+  ARM_CPU_OPT2 ("cortex-a7",	  "Cortex-A7",	       ARM_ARCH_V7VE,
+	       ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1 |
+	       FPU_NEON_EXT_FMA),
+	       FPU_ARCH_NEON_VFP_V4,
+	       cortex_a7),
+  ARM_CPU_OPT2 ("cortex-a8",	  "Cortex-A8",	       ARM_ARCH_V7A,
+	       ARM_FEATURE_LOW (ARM_EXT_SEC, FPU_VFP_V3 | FPU_NEON_EXT_V1),
+	       ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1),
+	       cortex_a8),
+  ARM_CPU_OPT2 ("cortex-a9",	  "Cortex-A9",	       ARM_ARCH_V7A,
+	       ARM_FEATURE (ARM_EXT_MP | ARM_EXT_SEC,
+	       ARM_EXT2_FP16_INST,
+	       FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA),
+	       FPU_ARCH_NEON_VFP_V4,
+	       cortex_a9),
+  ARM_CPU_OPT2 ("cortex-a12",	  "Cortex-A12",	       ARM_ARCH_V7VE,
+	       ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1 |
+	       FPU_NEON_EXT_FMA),
+	       FPU_ARCH_NEON_VFP_V4,
+	       cortex_a12),
+  ARM_CPU_OPT2 ("cortex-a15",	  "Cortex-A15",	       ARM_ARCH_V7VE,
+	       ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1 |
+	       FPU_NEON_EXT_FMA),
+	       FPU_ARCH_NEON_VFP_V4,
+	       cortex_a15),
+  ARM_CPU_OPT2 ("cortex-a17",	  "Cortex-A17",	       ARM_ARCH_V7VE,
+	       ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1 |
+	       FPU_NEON_EXT_FMA),
+	       FPU_ARCH_NEON_VFP_V4,
+	       cortex_a17),
+  ARM_CPU_OPT2 ("cortex-a32",	  "Cortex-A32",	       ARM_ARCH_V8A,
+	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+	       FPU_ARCH_NEON_VFP_ARMV8,
+	       cortex_a32),
+  ARM_CPU_OPT2 ("cortex-a35",	  "Cortex-A35",	       ARM_ARCH_V8A,
+	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+	       FPU_ARCH_NEON_VFP_ARMV8,
+	       cortex_a35),
+  ARM_CPU_OPT2 ("cortex-a53",	  "Cortex-A53",	       ARM_ARCH_V8A,
+	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+	       FPU_ARCH_NEON_VFP_ARMV8,
+	       cortex_a53),
+  ARM_CPU_OPT2 ("cortex-a55",    "Cortex-A55",	       ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       cortex_a55),
+  ARM_CPU_OPT2 ("cortex-a57",	  "Cortex-A57",	       ARM_ARCH_V8A,
+	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+	       FPU_ARCH_NEON_VFP_ARMV8,
+	       cortex_a57),
+  ARM_CPU_OPT2 ("cortex-a72",	  "Cortex-A72",	       ARM_ARCH_V8A,
+	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+	       FPU_ARCH_NEON_VFP_ARMV8,
+	       cortex_a72),
+  ARM_CPU_OPT2 ("cortex-a73",	  "Cortex-A73",	       ARM_ARCH_V8A,
+	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+	       FPU_ARCH_NEON_VFP_ARMV8,
+	       cortex_a73),
+  ARM_CPU_OPT2 ("cortex-a75",    "Cortex-A75",	       ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       cortex_a75),
+  ARM_CPU_OPT2 ("cortex-a76",    "Cortex-A76",	       ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       cortex_a76),
+  ARM_CPU_OPT2 ("cortex-a76ae",    "Cortex-A76AE",      ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       cortex_a76ae),
+  ARM_CPU_OPT2 ("cortex-a77",    "Cortex-A77",	       ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       cortex_a77),
+  ARM_CPU_OPT2 ("cortex-a78",   "Cortex-A78",	       ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       cortex_a78),
+  ARM_CPU_OPT2 ("cortex-a78ae",   "Cortex-A78AE",	   ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       cortex_a78ae),
+  ARM_CPU_OPT2 ("cortex-a78c",   "Cortex-A78C",	   ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       cortex_a78c),
   ARM_CPU_OPT ("cortex-r4",	  "Cortex-R4",	       ARM_ARCH_V7R,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-r4f",	  "Cortex-R4F",	       ARM_ARCH_V7R,
-	       ARM_ARCH_NONE,
-	       FPU_ARCH_VFP_V3D16),
-  ARM_CPU_OPT ("cortex-r5",	  "Cortex-R5",	       ARM_ARCH_V7R,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
-	       FPU_ARCH_SOFTVFP),
-  ARM_CPU_OPT ("cortex-r7",	  "Cortex-R7",	       ARM_ARCH_V7R,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
-	       FPU_ARCH_VFP_V3D16),
-  ARM_CPU_OPT ("cortex-r8",	  "Cortex-R8",	       ARM_ARCH_V7R,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
+	       FPU_ARCH_VFP_V3D16,
 	       FPU_ARCH_VFP_V3D16),
-  ARM_CPU_OPT ("cortex-r52",	  "Cortex-R52",	       ARM_ARCH_V8R,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	      FPU_ARCH_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-r52plus",	  "Cortex-R52+",	       ARM_ARCH_V8R,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	      FPU_ARCH_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-m35p",	  "Cortex-M35P",       ARM_ARCH_V8M_MAIN,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
-	       FPU_ARCH_SOFTVFP),
-  ARM_CPU_OPT ("cortex-m33",	  "Cortex-M33",	       ARM_ARCH_V8M_MAIN,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
-	       FPU_ARCH_SOFTVFP),
+  ARM_CPU_OPT2 ("cortex-r5",	  "Cortex-R5",	       ARM_ARCH_V7R,
+	       ARM_FEATURE (ARM_EXT_ADIV, 0, FPU_VFP_V3),
+	       FPU_ARCH_VFP_V3,
+	       cortex_r5),
+  ARM_CPU_OPT2 ("cortex-r7",	  "Cortex-R7",	       ARM_ARCH_V7R,
+	       ARM_FEATURE (ARM_EXT_ADIV, 0, FPU_VFP_V3D16 | FPU_VFP_EXT_FP16),
+	       FPU_ARCH_VFP_V3D16_FP16,
+	       cortex_r7),
+  ARM_CPU_OPT2 ("cortex-r8",	  "Cortex-R8",	       ARM_ARCH_V7R,
+	       ARM_FEATURE (ARM_EXT_ADIV, 0, FPU_VFP_V3D16 | FPU_VFP_EXT_FP16),
+	       FPU_ARCH_VFP_V3D16_FP16,
+	       cortex_r8),
+  ARM_CPU_OPT2 ("cortex-r52",	  "Cortex-R52",	       ARM_ARCH_V8R,
+	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+         FPU_ARCH_NEON_VFP_ARMV8,
+	       cortex_r52),
+  ARM_CPU_OPT2 ("cortex-r52plus",	  "Cortex-R52+",	ARM_ARCH_V8R,
+	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+         FPU_ARCH_NEON_VFP_ARMV8,
+	       cortex_r52plus),
+  ARM_CPU_OPT2 ("cortex-m85",	 "Cortex-M85",	       ARM_ARCH_V8_1M_MAIN,
+	       ARM_FEATURE_ALL(ARM_AEXT_V8M_MAIN_DSP,
+	       ARM_EXT2_FP16_INST | ARM_EXT2_MVE | ARM_EXT2_MVE_FP,
+	       ARM_EXT3_PACBTI,
+	       FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA),
+	       FPU_ARCH_SOFTVFP,
+	       cortex_m85),
+  ARM_CPU_OPT2 ("cortex-m55",	 "Cortex-M55",	       ARM_ARCH_V8_1M_MAIN,
+	       ARM_FEATURE_ALL(ARM_AEXT_V8M_MAIN_DSP,
+	       ARM_EXT2_FP16_INST | ARM_EXT2_MVE | ARM_EXT2_MVE_FP,
+	       0, FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA),
+	       FPU_ARCH_SOFTVFP,
+	       cortex_m55),
+  ARM_CPU_OPT2 ("cortex-m52",	 "Cortex-M52",	       ARM_ARCH_V8_1M_MAIN,
+	       ARM_FEATURE_ALL (ARM_AEXT_V8M_MAIN_DSP,
+	       ARM_EXT2_FP16_INST | ARM_EXT2_MVE | ARM_EXT2_MVE_FP,
+	       ARM_EXT3_PACBTI,
+	       FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA),
+	       FPU_ARCH_SOFTVFP,
+	       cortex_m52),
+  ARM_CPU_OPT2 ("cortex-m35p",	  "Cortex-M35P",       ARM_ARCH_V8M_MAIN,
+	       ARM_FEATURE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP, FPU_VFP_V4D16),
+	       FPU_ARCH_VFP_V3D16,
+	       cortex_m35p),
+  ARM_CPU_OPT2 ("cortex-m33",	  "Cortex-M33",	       ARM_ARCH_V8M_MAIN,
+	       ARM_FEATURE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP, FPU_VFP_V4D16),
+	       FPU_ARCH_VFP_V3D16, cortex_m33),
   ARM_CPU_OPT ("cortex-m23",	  "Cortex-M23",	       ARM_ARCH_V8M_BASE,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_SOFTVFP),
-  ARM_CPU_OPT ("cortex-m7",	  "Cortex-M7",	       ARM_ARCH_V7EM,
-	       ARM_ARCH_NONE,
-	       FPU_ARCH_SOFTVFP),
-  ARM_CPU_OPT ("cortex-m4",	  "Cortex-M4",	       ARM_ARCH_V7EM,
-	       ARM_ARCH_NONE,
-	       FPU_ARCH_SOFTVFP),
+  ARM_CPU_OPT2 ("cortex-m7",	  "Cortex-M7",	       ARM_ARCH_V7EM,
+	       ARM_FEATURE_COPROC (FPU_VFP_V5D16),
+	       FPU_ARCH_VFP_V5D16,
+	       cortex_m7),
+  ARM_CPU_OPT2 ("cortex-m4",	  "Cortex-M4",	       ARM_ARCH_V7EM,
+	       ARM_FEATURE_COPROC (FPU_VFP_V4_SP_D16),
+	       FPU_ARCH_VFP_V4_SP_D16,
+	       cortex_m4),
   ARM_CPU_OPT ("cortex-m3",	  "Cortex-M3",	       ARM_ARCH_V7M,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_SOFTVFP),
@@ -30883,28 +31268,47 @@ static const struct arm_cpu_option_table arm_cpus[] =
   ARM_CPU_OPT ("cortex-m0plus",	  "Cortex-M0+",	       ARM_ARCH_V6SM,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_SOFTVFP),
-  ARM_CPU_OPT ("cortex-x1",   "Cortex-X1",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
-	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-x1c",   "Cortex-X1C",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
-	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("exynos-m1",	  "Samsung Exynos M1", ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("neoverse-n1",    "Neoverse N1",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
-  ARM_CPU_OPT ("neoverse-n2",	 "Neoverse N2",	       ARM_ARCH_V8_5A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
-				    | ARM_EXT2_BF16
-				    | ARM_EXT2_I8MM),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4),
-  ARM_CPU_OPT ("neoverse-v1", "Neoverse V1", ARM_ARCH_V8_4A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
-				    | ARM_EXT2_BF16
-				    | ARM_EXT2_I8MM),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4),
+  ARM_CPU_OPT2 ("cortex-x1",   "Cortex-X1",	       ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       cortex_x1),
+  ARM_CPU_OPT2 ("cortex-x1c",   "Cortex-X1C",	       ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       cortex_x1c),
+  ARM_CPU_OPT2 ("exynos-m1",	  "Samsung Exynos M1", ARM_ARCH_V8A,
+	       ARM_FEATURE (0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+         FPU_ARCH_NEON_VFP_ARMV8,
+	       exynos_m1),
+  ARM_CPU_OPT2 ("neoverse-n1",	 "Neoverse N1",	       ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       neoverse_n1),
+  ARM_CPU_OPT2 ("ares",    "Ares",	       ARM_ARCH_V8_2A,
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       neoverse_n1),
+  ARM_CPU_OPT2 ("neoverse-n2",	 "Neoverse N2",	       ARM_ARCH_V9A,
+	       ARM_FEATURE(0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML |
+	       ARM_EXT2_BF16 | ARM_EXT2_I8MM,
+	       FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8 |
+	       FPU_NEON_EXT_DOTPROD | FPU_NEON_EXT_RDMA),
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       neoverse_n2),
+  ARM_CPU_OPT2 ("cortex-a710",	 "Cortex-A710",	   ARM_ARCH_V9A,
+	       ARM_FEATURE(0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML |
+		              ARM_EXT2_BF16 | ARM_EXT2_I8MM,
+			      FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8 |
+			      FPU_NEON_EXT_DOTPROD | FPU_NEON_EXT_RDMA),
+	       FPU_ARCH_VFP_V5_SP_D16,
+	       cortex_a710),
+  ARM_CPU_OPT2 ("neoverse-v1",	 "Neoverse V1",	       ARM_ARCH_V8_4A,
+	       ARM_FEATURE(0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML |
+			      ARM_EXT2_BF16 | ARM_EXT2_I8MM,
+			      FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8 |
+			      FPU_NEON_EXT_DOTPROD),
+	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+	       neoverse_v1),
   /* ??? XSCALE is really an architecture.  */
   ARM_CPU_OPT ("xscale",	  NULL,		       ARM_ARCH_XSCALE,
 	       ARM_ARCH_NONE,
@@ -30928,31 +31332,24 @@ static const struct arm_cpu_option_table arm_cpus[] =
 
   /* Marvell processors.  */
   ARM_CPU_OPT ("marvell-pj4",	  NULL,		       ARM_ARCH_V7A,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
-	       FPU_ARCH_VFP_V3D16),
+	       ARM_FEATURE (ARM_EXT_MP | ARM_EXT_SEC, 0, FPU_VFP_V3),
+	       FPU_ARCH_VFP_V3),
   ARM_CPU_OPT ("marvell-whitney", NULL,		       ARM_ARCH_V7A,
 	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
 	       FPU_ARCH_NEON_VFP_V4),
 
   /* APM X-Gene family.  */
   ARM_CPU_OPT ("xgene1",	  "APM X-Gene 1",      ARM_ARCH_V8A,
-	       ARM_ARCH_NONE,
+	       ARM_FEATURE (0, 0, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
 	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
   ARM_CPU_OPT ("xgene2",	  "APM X-Gene 2",      ARM_ARCH_V8A,
 	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
 	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
 
-  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL, NULL }
 };
 #undef ARM_CPU_OPT
-
-struct arm_ext_table
-{
-  const char *		  name;
-  size_t		  name_len;
-  const arm_feature_set	  merge;
-  const arm_feature_set	  clear;
-};
+#undef ARM_CPU_OPT2
 
 struct arm_arch_option_table
 {
@@ -30963,16 +31360,6 @@ struct arm_arch_option_table
   const struct arm_ext_table *	ext_table;
 };
 
-/* Used to add support for +E and +noE extension.  */
-#define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
-/* Used to add support for a +E extension.  */
-#define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
-/* Used to add support for a +noE extension.  */
-#define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
-
-#define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
-			    ~0 & ~FPU_ENDIAN_PURE)
-
 static const struct arm_ext_table armv5te_ext_table[] =
 {
   ARM_EXT ("fp", FPU_ARCH_VFP_V2, ALL_FP),
@@ -31169,16 +31556,6 @@ static const struct arm_ext_table armv9a_ext_table[] =
 #define armv94a_ext_table armv93a_ext_table
 #define armv95a_ext_table armv94a_ext_table
 
-#define CDE_EXTENSIONS \
-  ARM_ADD ("cdecp0", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE0)), \
-  ARM_ADD ("cdecp1", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE1)), \
-  ARM_ADD ("cdecp2", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE2)), \
-  ARM_ADD ("cdecp3", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE3)), \
-  ARM_ADD ("cdecp4", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE4)), \
-  ARM_ADD ("cdecp5", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE5)), \
-  ARM_ADD ("cdecp6", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE6)), \
-  ARM_ADD ("cdecp7", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE7))
-
 static const struct arm_ext_table armv8m_main_ext_table[] =
 {
   ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP),
@@ -31755,7 +32132,7 @@ arm_parse_cpu (const char *str)
 	  }
 
 	if (ext != NULL)
-	  return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, NULL);
+	  return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, opt->ext_table);
 
 	return true;
       }
diff --git a/gas/testsuite/gas/arm/attr-cpu-directive.d b/gas/testsuite/gas/arm/attr-cpu-directive.d
index a2ab435fc0a..62a07adb4de 100644
--- a/gas/testsuite/gas/arm/attr-cpu-directive.d
+++ b/gas/testsuite/gas/arm/attr-cpu-directive.d
@@ -12,4 +12,6 @@ File Attributes
   Tag_CPU_arch_profile: Application
   Tag_ARM_ISA_use: Yes
   Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3
+  Tag_Advanced_SIMD_arch: NEONv1
   Tag_Virtualization_use: TrustZone
diff --git a/gas/testsuite/gas/arm/command-line-mcpu.exp b/gas/testsuite/gas/arm/command-line-mcpu.exp
new file mode 100644
index 00000000000..fc52296f882
--- /dev/null
+++ b/gas/testsuite/gas/arm/command-line-mcpu.exp
@@ -0,0 +1,134 @@
+
+if {[istarget arm*-*-*]} {
+    gas_test_old "feat-mp.s" "-mcpu=cortex-a5" "gas/arm: cortex-a5 feat-mp"
+    gas_test_old "feat-sec.s" "-mcpu=cortex-a5" "gas/arm: cortex-a5 feat-sec"
+    gas_test_old "feat-neon-fp16.s" "-mcpu=cortex-a5" "gas/arm: cortex-a5 feat-neon-fp16"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a5+nofp+nosimd" "gas/arm: cortex-a5 exts"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a7" "gas/arm: cortex-a7 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a7+nofp+nosimd" "gas/arm: cortex-a7 exts"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a8" "gas/arm: cortex-a8 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a8+nofp" "gas/arm: cortex-a8 exts"
+    gas_test_old "feat-mp.s" "-mcpu=cortex-a9" "gas/arm: cortex-a9 feat-mp"
+    gas_test_old "feat-sec.s" "-mcpu=cortex-a9" "gas/arm: cortex-a9 feat-sec"
+    gas_test_old "feat-neon-fp16.s" "-mcpu=cortex-a9" "gas/arm: cortex-a9 feat-neon-fp16"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a9+nofp+nosimd" "gas/arm: cortex-a9 exts"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a12" "gas/arm: cortex-a12 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a12+nofp" "gas/arm: cortex-a12 exts"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a15" "gas/arm: cortex-a15 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a15+nofp" "gas/arm: cortex-a15 exts"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a17" "gas/arm: cortex-a17 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a17+nofp" "gas/arm: cortex-a17 exts"
+    gas_test_old "feat-mp.s" "-mcpu=marvell-pj4" "gas/arm: marvell-pj4 feat-mp"
+    gas_test_old "feat-sec.s" "-mcpu=marvell-pj4" "gas/arm: marvell-pj4 feat-sec"
+    gas_test_old "feat-fp-vfpv3.s" "-mcpu=marvell-pj4" "gas/arm: marvell-pj4 feat-fp-vfpv3"
+    gas_test_old "feat-fp-vfpv3.s" "-mcpu=cortex-r4f" "gas/arm: cortex-r4f feat-fp-vfpv3"
+    gas_test_old "feat-fp-vfpv3.s" "-mcpu=cortex-r5" "gas/arm: cortex-r5 feat-fp-vfpv3"
+    gas_test_old "feat-idiv.s" "-mcpu=cortex-r5" "gas/arm: cortex-r5 feat-idiv"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-r5+nofp+nofp.dp" "gas/arm: cortex-r5 exts"
+    gas_test_old "feat-idiv.s" "-mcpu=cortex-r7" "gas/arm: cortex-r7 feat-idiv"
+    gas_test_old "feat-vfpv3-d16-fp16.s" "-mcpu=cortex-r7" "gas/arm: cortex-r7 feat-vfpv3-d16-fp16"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-r7+nofp+nofp.dp" "gas/arm: cortex-r7 exts"
+    gas_test_old "feat-idiv.s" "-mcpu=cortex-r8" "gas/arm: cortex-r8 feat-idiv"
+    gas_test_old "feat-vfpv3-d16-fp16.s" "-mcpu=cortex-r8" "gas/arm: cortex-r8 feat-vfpv3-d16-fp16"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-r8+nofp+nofp.dp" "gas/arm: cortex-r8 exts"
+    gas_test_old "feat-fp-vfpv3.s" "-mcpu=cortex-m4" "gas/arm: cortex-m4 feat-fp-vfpv3"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-m4+nofp" "gas/arm: cortex-m4 exts"
+    gas_test_old "feat-fp.dp.s" "-mcpu=cortex-m7" "gas/arm: cortex-m7 feat-fp.dp"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-m7+nofp+nofp.dp" "gas/arm: cortex-m7 exts"
+    gas_test_old "feat-crc.s" "-mcpu=cortex-a32" "gas/arm: cortex-a32 feat-crc"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a32" "gas/arm: cortex-a32 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a32+nofp" "gas/arm: cortex-a32 exts"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a32+crypto" "gas/arm: cortex-a32 exts"
+    gas_test_old "feat-crc.s" "-mcpu=cortex-a35" "gas/arm: cortex-a35 feat-crc"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a35" "gas/arm: cortex-a35 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a35+nofp" "gas/arm: cortex-a35 exts"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a35+crypto" "gas/arm: cortex-a35 exts"
+    gas_test_old "feat-crc.s" "-mcpu=cortex-a53" "gas/arm: cortex-a53 feat-crc"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a53" "gas/arm: cortex-a53 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a53+nofp" "gas/arm: cortex-a53 exts"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a53+crypto" "gas/arm: cortex-a53 exts"
+    gas_test_old "feat-crc.s" "-mcpu=cortex-a57" "gas/arm: cortex-a57 feat-crc"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a57" "gas/arm: cortex-a57 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a57+crypto" "gas/arm: cortex-a57 exts"
+    gas_test_old "feat-crc.s" "-mcpu=cortex-a72" "gas/arm: cortex-a72 feat-crc"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a72" "gas/arm: cortex-a72 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a72+crypto" "gas/arm: cortex-a72 exts"
+    gas_test_old "feat-crc.s" "-mcpu=cortex-a73" "gas/arm: cortex-a73 feat-crc"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-a73" "gas/arm: cortex-a73 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a73+crypto" "gas/arm: cortex-a73 exts"
+    gas_test_old "feat-crc.s" "-mcpu=exynos-m1" "gas/arm: exynos-m1 feat-crc"
+    gas_test_old "feat-simd.s" "-mcpu=exynos-m1" "gas/arm: exynos-m1 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=exynos-m1+crypto" "gas/arm: exynos-m1 exts"
+    gas_test_old "feat-simd.s" "-mcpu=xgene1" "gas/arm: xgene1 feat-simd"
+    gas_test_old "feat-crc.s" "-mcpu=cortex-r52" "gas/arm: cortex-r52 feat-crc"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-r52" "gas/arm: cortex-r52 feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-r52+nofp.dp" "gas/arm: cortex-r52 exts"
+    gas_test_old "feat-crc.s" "-mcpu=cortex-r52plus" "gas/arm: cortex-r52plus feat-crc"
+    gas_test_old "feat-simd.s" "-mcpu=cortex-r52plus" "gas/arm: cortex-r52plus feat-simd"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-r52plus+nofp.dp" "gas/arm: cortex-r52plus exts"
+    gas_test_old "feat-dsp.s" "-mcpu=cortex-m33" "gas/arm: cortex-m33 feat-dsp"
+    gas_test_old "feat-fp-vfpv5.s" "-mcpu=cortex-m33" "gas/arm: cortex-m33 feat-fp-vfpv5"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-m33+nofp+nodsp" "gas/arm: cortex-m33 exts"
+    gas_test_old "feat-dsp.s" "-mcpu=cortex-m35p" "gas/arm: cortex-m35p feat-dsp"
+    gas_test_old "feat-fp-vfpv5.s" "-mcpu=cortex-m35p" "gas/arm: cortex-m35p feat-fp-vfpv5"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-m35p+nofp+nodsp" "gas/arm: cortex-m35p exts"
+    gas_test_old "feat-pacbti.s" "-mcpu=cortex-m52" "gas/arm: cortex-m52 feat-pacbti"
+    gas_test_old "feat-mve.fp.s" "-mcpu=cortex-m52" "gas/arm: cortex-m52 feat-mve.fp"
+    gas_test_old "feat-fp.dp.s" "-mcpu=cortex-m52" "gas/arm: cortex-m52 feat-fp.dp"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-m52+nopacbti+nomve.fp+nomve+nofp+nodsp" "gas/arm: cortex-m52 exts"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-m52+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7" "gas/arm: cortex-m52 exts"
+    gas_test_old "feat-mve.fp.s" "-mcpu=cortex-m55" "gas/arm: cortex-m55 feat-mve.fp"
+    gas_test_old "feat-fp.dp.s" "-mcpu=cortex-m55" "gas/arm: cortex-m55 feat-fp.dp"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-m55+nomve.fp+nomve+nofp+nodsp" "gas/arm: cortex-m55 exts"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-m55+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7" "gas/arm: cortex-m55 exts"
+    gas_test_old "feat-pacbti.s" "-mcpu=cortex-m85" "gas/arm: cortex-m85 feat-pacbti"
+    gas_test_old "feat-mve.fp.s" "-mcpu=cortex-m85" "gas/arm: cortex-m85 feat-mve.fp"
+    gas_test_old "feat-fp.dp.s" "-mcpu=cortex-m85" "gas/arm: cortex-m85 feat-fp.dp"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-m85+nopacbti+nomve.fp+nomve+nofp+nodsp" "gas/arm: cortex-m85 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-a55" "gas/arm: cortex-a55 feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a55" "gas/arm: cortex-a55 feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a55+nofp" "gas/arm: cortex-a55 exts"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a55+crypto" "gas/arm: cortex-a55 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-a75" "gas/arm: cortex-a75 feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a75" "gas/arm: cortex-a75 feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a75+crypto" "gas/arm: cortex-a75 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-a76" "gas/arm: cortex-a76 feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a76" "gas/arm: cortex-a76 feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a76+crypto" "gas/arm: cortex-a76 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-a76ae" "gas/arm: cortex-a76ae feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a76ae" "gas/arm: cortex-a76ae feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a76ae+crypto" "gas/arm: cortex-a76ae exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-a77" "gas/arm: cortex-a77 feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a77" "gas/arm: cortex-a77 feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a77+crypto" "gas/arm: cortex-a77 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-a78" "gas/arm: cortex-a78 feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a78" "gas/arm: cortex-a78 feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a78+crypto" "gas/arm: cortex-a78 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-a78ae" "gas/arm: cortex-a78ae feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a78ae" "gas/arm: cortex-a78ae feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a78ae+crypto" "gas/arm: cortex-a78ae exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-a78c" "gas/arm: cortex-a78c feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a78c" "gas/arm: cortex-a78c feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a78c+crypto" "gas/arm: cortex-a78c exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-x1" "gas/arm: cortex-x1 feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-x1" "gas/arm: cortex-x1 feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-x1+crypto" "gas/arm: cortex-x1 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-x1c" "gas/arm: cortex-x1c feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=cortex-x1c" "gas/arm: cortex-x1c feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-x1c+crypto" "gas/arm: cortex-x1c exts"
+    gas_test_old "feat-fp16.s" "-mcpu=neoverse-n1" "gas/arm: neoverse-n1 feat-fp16"
+    gas_test_old "feat-dotprod.s" "-mcpu=neoverse-n1" "gas/arm: neoverse-n1 feat-dotprod"
+    gas_test_old "nop-asm.s" "-mcpu=neoverse-n1+crypto" "gas/arm: neoverse-n1 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=neoverse-v1" "gas/arm: neoverse-v1 feat-fp16"
+    gas_test_old "feat-bf16.s" "-mcpu=neoverse-v1" "gas/arm: neoverse-v1 feat-bf16"
+    gas_test_old "feat-i8mm.s" "-mcpu=neoverse-v1" "gas/arm: neoverse-v1 feat-i8mm"
+    gas_test_old "nop-asm.s" "-mcpu=neoverse-v1+crypto" "gas/arm: neoverse-v1 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=cortex-a710" "gas/arm: cortex-a710 feat-fp16"
+    gas_test_old "feat-bf16.s" "-mcpu=cortex-a710" "gas/arm: cortex-a710 feat-bf16"
+    gas_test_old "feat-i8mm.s" "-mcpu=cortex-a710" "gas/arm: cortex-a710 feat-i8mm"
+    gas_test_old "nop-asm.s" "-mcpu=cortex-a710+crypto" "gas/arm: cortex-a710 exts"
+    gas_test_old "feat-fp16.s" "-mcpu=neoverse-n2" "gas/arm: neoverse-n2 feat-fp16"
+    gas_test_old "feat-bf16.s" "-mcpu=neoverse-n2" "gas/arm: neoverse-n2 feat-bf16"
+    gas_test_old "feat-i8mm.s" "-mcpu=neoverse-n2" "gas/arm: neoverse-n2 feat-i8mm"
+    gas_test_old "nop-asm.s" "-mcpu=neoverse-n2+crypto" "gas/arm: neoverse-n2 exts"
+}
diff --git a/gas/testsuite/gas/arm/feat-bf16.s b/gas/testsuite/gas/arm/feat-bf16.s
new file mode 100644
index 00000000000..46fc48ba567
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-bf16.s
@@ -0,0 +1,5 @@
+.syntax unified
+.thumb
+
+@ feat FP16
+vdot.bf16 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/feat-crc.s b/gas/testsuite/gas/arm/feat-crc.s
new file mode 100644
index 00000000000..671ac14ebcb
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-crc.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat CRC
+crc32w  r0, r0, r1
diff --git a/gas/testsuite/gas/arm/feat-dotprod.s b/gas/testsuite/gas/arm/feat-dotprod.s
new file mode 100644
index 00000000000..775c3ba4c02
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-dotprod.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat DOTPROD
+vudot.u8 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/feat-dsp.s b/gas/testsuite/gas/arm/feat-dsp.s
new file mode 100644
index 00000000000..2f54c7327d1
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-dsp.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat DSP
+smlad   r0, r1, r2, r3
diff --git a/gas/testsuite/gas/arm/feat-fp-vfpv3.s b/gas/testsuite/gas/arm/feat-fp-vfpv3.s
new file mode 100644
index 00000000000..4435db35690
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-fp-vfpv3.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat FP (VFP-v3)
+vmla.f32 s0, s1, s2
diff --git a/gas/testsuite/gas/arm/feat-fp-vfpv5.s b/gas/testsuite/gas/arm/feat-fp-vfpv5.s
new file mode 100644
index 00000000000..13a2e7aca9e
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-fp-vfpv5.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat FP (VFP-v5)
+vfma.f32 s0, s1, s2
diff --git a/gas/testsuite/gas/arm/feat-fp.dp.s b/gas/testsuite/gas/arm/feat-fp.dp.s
new file mode 100644
index 00000000000..34b68cd8603
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-fp.dp.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat FP.DP
+vadd.f64 d0, d1, d2
diff --git a/gas/testsuite/gas/arm/feat-fp.s b/gas/testsuite/gas/arm/feat-fp.s
new file mode 100644
index 00000000000..5cf49af0e9f
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-fp.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat FP
+vadd.f32 s0, s1, s2
diff --git a/gas/testsuite/gas/arm/feat-fp16.s b/gas/testsuite/gas/arm/feat-fp16.s
new file mode 100644
index 00000000000..6780678e8ca
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-fp16.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat FP16
+vadd.f16 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/feat-i8mm.s b/gas/testsuite/gas/arm/feat-i8mm.s
new file mode 100644
index 00000000000..bb3818726a8
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-i8mm.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat I8MM
+vusmmla.s8  q6, q7, q8
diff --git a/gas/testsuite/gas/arm/feat-idiv.s b/gas/testsuite/gas/arm/feat-idiv.s
new file mode 100644
index 00000000000..8b289fa817d
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-idiv.s
@@ -0,0 +1,3 @@
+.syntax unified
+
+sdiv r0, r1, r2
diff --git a/gas/testsuite/gas/arm/feat-mp.s b/gas/testsuite/gas/arm/feat-mp.s
new file mode 100644
index 00000000000..db365d7f282
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-mp.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat MP
+ldrex r0, [r1]
diff --git a/gas/testsuite/gas/arm/feat-mve.fp.s b/gas/testsuite/gas/arm/feat-mve.fp.s
new file mode 100644
index 00000000000..81c23300dc3
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-mve.fp.s
@@ -0,0 +1,5 @@
+.syntax unified
+.thumb
+
+@ MVE.FP
+vmul.f32 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/feat-neon-fp16.s b/gas/testsuite/gas/arm/feat-neon-fp16.s
new file mode 100644
index 00000000000..55ab08553bf
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-neon-fp16.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat NEON-FP16
+vadd.f16 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/feat-pacbti.s b/gas/testsuite/gas/arm/feat-pacbti.s
new file mode 100644
index 00000000000..2399f0ca230
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-pacbti.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ PACBTI
+pac     r12, lr, sp
diff --git a/gas/testsuite/gas/arm/feat-sec.s b/gas/testsuite/gas/arm/feat-sec.s
new file mode 100644
index 00000000000..bdb516a30f4
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-sec.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat SEC
+smc     #0
diff --git a/gas/testsuite/gas/arm/feat-simd.s b/gas/testsuite/gas/arm/feat-simd.s
new file mode 100644
index 00000000000..871f5490902
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-simd.s
@@ -0,0 +1,5 @@
+.syntax unified
+.text
+
+@ feat SIMD
+vadd.i32 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s b/gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s
new file mode 100644
index 00000000000..41ccd2d9414
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat VFP3-D16-FP16
+vcvtt.f16.f32 s0, s1
-- 
2.43.0


From aburgess@redhat.com  Tue Jun  9 10:52:17 2026
From: aburgess@redhat.com (Andrew Burgess)
Date: Tue,  9 Jun 2026 11:52:17 +0100
Subject: [PATCH] libiberty: sync with gcc commit df3510f80e7c02d9
Message-ID: <ff87d7cb74f9d3d3b81aeca0a979d3dcc1531567.1781002240.git.aburgess@redhat.com>

From: Dhruv Chawla <dhruvc@nvidia.com>

Sync the libiberty/ directory with gcc commit
df3510f80e7c02d9c19d7cb33759cd925880f53a.  This pulls in the following
gcc commits and the associated updates to 'libiberty/ChangeLog':

  * 06fb00cb66d libiberty: Fix typos in various files
  * fbf903e5b9f Re-flow lines made longer than 80 characters by typo fixes
  * cfb945957ee Regenerate some autoconf configure scripts after recent spelling fixes.
  * bc4d9b6aeb3 libiberty: avoid exponential back reference issue in D demangler

I have retained the changes that are in the following binutils-gdb
commit, which are not in gcc:

  commit 219822fd5db6305592b45677a3b38c02b523360e
  Date:   Tue Apr 9 06:39:21 2024 -0700

    mmap: Avoid the sanitizer configure check failure
---
 libiberty/ChangeLog                     | 59 +++++++++++++++++++++++++
 libiberty/bcopy.c                       |  2 +-
 libiberty/bsearch.c                     |  2 +-
 libiberty/bsearch_r.c                   |  2 +-
 libiberty/configure                     |  2 +-
 libiberty/configure.ac                  |  2 +-
 libiberty/cp-demangle.c                 |  6 +--
 libiberty/d-demangle.c                  | 55 +++++++++++++++++++++--
 libiberty/dyn-string.c                  |  4 +-
 libiberty/ldirname.c                    |  2 +-
 libiberty/make-relative-prefix.c        |  2 +-
 libiberty/obstacks.texi                 |  2 +-
 libiberty/pex-win32.c                   |  6 +--
 libiberty/random.c                      |  4 +-
 libiberty/regex.c                       | 20 ++++-----
 libiberty/sigsetmask.c                  |  2 +-
 libiberty/simple-object-elf.c           |  6 +--
 libiberty/simple-object-mach-o.c        | 10 ++---
 libiberty/strsignal.c                   |  4 +-
 libiberty/testsuite/d-demangle-expected | 12 +++++
 20 files changed, 161 insertions(+), 43 deletions(-)

diff --git a/libiberty/ChangeLog b/libiberty/ChangeLog
index 7de0bb4d254..e60b5951ea4 100644
--- a/libiberty/ChangeLog
+++ b/libiberty/ChangeLog
@@ -1,3 +1,62 @@
+2026-06-07  Andrew Burgess  <aburgess@redhat.com>
+
+	* d-demangle.c (struct dlang_info::options): New field,
+	carries options passed to the demangler.
+	(struct dlang_info::num_backrefs): Count total number of back
+	referenced types that have been processed.
+	(struct dlang_info::backref_depth): Count the depth of
+	recursive back references.
+	(dlang_type_backref): Track recursive back reference depth,
+	and the total number of back references encountered.  Bail out
+	early if the total number gets too high.
+	(dlang_demangle_init_info): Initialise new 'struct dlang_info'
+	fields.
+	(dlang_demangle): Pass demangler options to
+	dlang_demangle_init_info.
+	* testsuite/d-demangle-expected: Add new test.
+
+2026-06-01  Jakub Jelinek  <jakub@redhat.com>
+
+	* configure: Regenerate.
+
+2026-05-30  Dhruv Chawla  <dhruvc@nvidia.com>
+
+	* simple-object-mach-o.c (simple_object_mach_o_write_segment): Reflow
+	long line.
+
+2026-05-30  Dhruv Chawla  <dhruvc@nvidia.com>
+
+	* bcopy.c: Fix typos.
+	* bsearch.c: Likewise.
+	* bsearch_r.c: Likewise.
+	* configure.ac: Likewise.
+	* cp-demangle.c (d_print_comp_inner): Likewise.
+	(d_print_comp): Likewise.
+	* d-demangle.c (dlang_identifier): Likewise.
+	* dyn-string.c: Likewise.
+	* ldirname.c: Likewise.
+	* make-relative-prefix.c (make_relative_prefix_1): Likewise.
+	* obstacks.texi: Likewise.
+	* pex-win32.c (argv_to_cmdline): Likewise.
+	(spawn_script): Likewise.
+	* random.c (random): Likewise.
+	(setstate): Likewise.
+	* regex.c (WIDE_CHAR_SUPPORT): Likewise.
+	(convert_mbs_to_wcs): Likewise.
+	(PREFIX): Likewise.
+	(wcs_compile_range): Likewise.
+	(count_mbs_length): Likewise.
+	(wcs_re_match_2_internal): Likewise.
+	(byte_re_match_2_internal): Likewise.
+	* sigsetmask.c: Likewise.
+	* simple-object-elf.c (SHT_SYMTAB_SHNDX): Likewise.
+	(STV_HIDDEN): Likewise.
+	(simple_object_elf_copy_lto_debug_sections): Likewise.
+	* simple-object-mach-o.c (struct mach_o_header_32): Likewise.
+	(struct mach_o_header_64): Likewise.
+	(simple_object_mach_o_write_segment): Likewise.
+	* strsignal.c (defined): Likewise.
+
 2026-03-05  Jakub Jelinek  <jakub@redhat.com>
 
 	PR target/124365
diff --git a/libiberty/bcopy.c b/libiberty/bcopy.c
index f9b7a8acd5c..914b698d225 100644
--- a/libiberty/bcopy.c
+++ b/libiberty/bcopy.c
@@ -1,4 +1,4 @@
-/* bcopy -- copy memory regions of arbitary length
+/* bcopy -- copy memory regions of arbitrary length
 
 @deftypefn Supplemental void bcopy (char *@var{in}, char *@var{out}, int @var{length})
 
diff --git a/libiberty/bsearch.c b/libiberty/bsearch.c
index 18158b9591b..eb7e1778b4b 100644
--- a/libiberty/bsearch.c
+++ b/libiberty/bsearch.c
@@ -60,7 +60,7 @@ is respectively less than, matching, or greater than the array member.
  * is odd, moving left simply involves halving lim: e.g., when lim
  * is 5 we look at item 2, so we change lim to 2 so that we will
  * look at items 0 & 1.  If lim is even, the same applies.  If lim
- * is odd, moving right again involes halving lim, this time moving
+ * is odd, moving right again involves halving lim, this time moving
  * the base up one item past p: e.g., when lim is 5 we change base
  * to item 3 and make lim 2 so that we will look at items 3 and 4.
  * If lim is even, however, we have to shrink it by one before
diff --git a/libiberty/bsearch_r.c b/libiberty/bsearch_r.c
index 2a2ca6f5e23..42c9e45c1aa 100644
--- a/libiberty/bsearch_r.c
+++ b/libiberty/bsearch_r.c
@@ -61,7 +61,7 @@ is respectively less than, matching, or greater than the array member.
  * is odd, moving left simply involves halving lim: e.g., when lim
  * is 5 we look at item 2, so we change lim to 2 so that we will
  * look at items 0 & 1.  If lim is even, the same applies.  If lim
- * is odd, moving right again involes halving lim, this time moving
+ * is odd, moving right again involves halving lim, this time moving
  * the base up one item past p: e.g., when lim is 5 we change base
  * to item 3 and make lim 2 so that we will look at items 3 and 4.
  * If lim is even, however, we have to shrink it by one before
diff --git a/libiberty/configure b/libiberty/configure
index 4c72b5a9283..379a3cfa9c3 100755
--- a/libiberty/configure
+++ b/libiberty/configure
@@ -6234,7 +6234,7 @@ _ACEOF
 
 
 
-# Check for presense of long long
+# Check for presence of long long
 ac_fn_c_check_type "$LINENO" "long long" "ac_cv_type_long_long" "$ac_includes_default"
 if test "x$ac_cv_type_long_long" = xyes; then :
 
diff --git a/libiberty/configure.ac b/libiberty/configure.ac
index 199fa192fe4..03b835ce828 100644
--- a/libiberty/configure.ac
+++ b/libiberty/configure.ac
@@ -321,7 +321,7 @@ AC_CHECK_SIZEOF([int])
 AC_CHECK_SIZEOF([long])
 AC_CHECK_SIZEOF([size_t])
 
-# Check for presense of long long
+# Check for presence of long long
 AC_CHECK_TYPE([long long],
   [AC_DEFINE(HAVE_LONG_LONG, 1, [Define if you have the `long long' type.]) AC_CHECK_SIZEOF([long long])],
   [])
diff --git a/libiberty/cp-demangle.c b/libiberty/cp-demangle.c
index 5e6571d419b..5f08ef8946a 100644
--- a/libiberty/cp-demangle.c
+++ b/libiberty/cp-demangle.c
@@ -82,7 +82,7 @@
 
    IN_GLIBCPP_V3
       If defined, this file defines only __cxa_demangle() and
-      __gcclibcxx_demangle_callback(), and no other publically visible
+      __gcclibcxx_demangle_callback(), and no other publicly visible
       functions or variables.
 
    STANDALONE_DEMANGLER
@@ -5590,7 +5590,7 @@ d_print_comp_inner (struct d_print_info *dpi, int options,
 		const struct d_component_stack *dcse;
 		int found_self_or_parent = 0;
 
-		/* This traversal is reentering SUB as a substition.
+		/* This traversal is reentering SUB as a substitution.
 		   If we are not beneath SUB or DC in the tree then we
 		   need to restore SUB's template stack temporarily.  */
 		for (dcse = dpi->component_stack; dcse != NULL;
@@ -6390,7 +6390,7 @@ d_print_comp (struct d_print_info *dpi, int options,
   dpi->recursion--;
 }
 
-/* Print a Java dentifier.  For Java we try to handle encoded extended
+/* Print a Java identifier.  For Java we try to handle encoded extended
    Unicode characters.  The C++ ABI doesn't mention Unicode encoding,
    so we don't it for C++.  Characters are encoded as
    __U<hex-char>+_.  */
diff --git a/libiberty/d-demangle.c b/libiberty/d-demangle.c
index f059f5690bb..9d55a1f2ccc 100644
--- a/libiberty/d-demangle.c
+++ b/libiberty/d-demangle.c
@@ -175,8 +175,33 @@ struct dlang_info
 {
   /* The string we are demangling.  */
   const char *s;
+
+  /* The options passed to the demangler.  */
+  int options;
+
   /* The index of the last back reference.  */
   int last_backref;
+
+  /* The total number of back referenced types, including nested back
+     referenced types.  This is reset to zero each time a back
+     reference is processed at the "top level" (i.e. not a nested back
+     reference).
+
+     Cases have been encountered where a back reference type includes
+     references to other back reference types, which include further
+     back references.  This was observed to a depth of 57.  If each
+     layer only references the layer before twice then the innermost
+     string will be duplicated 2^57 times!
+
+     We count the number of nested back references and compare this to
+     the recursion limit, even though this isn't strictly recursion.  */
+  int num_backrefs;
+
+  /* Track the depth of back references.  Depth 0 is considered the
+     top level.  When we encounter a back reference at this depth the
+     NUM_BACKREFS field is reset to 0.  At greater depths,
+     NUM_BACKREFS will be incremented.  */
+  int backref_depth;
 };
 
 /* Pass as the LEN to dlang_parse_template if symbol length is not known.  */
@@ -411,6 +436,24 @@ dlang_type_backref (string *decl, const char *mangled, struct dlang_info *info,
   if (mangled - info->s >= info->last_backref)
     return NULL;
 
+  /* A back reference might point to a type that itself contains back
+     references, which might themselves contain back references.
+     There might not be recursion going on, but we can run into
+     problems of exponential growth caused by the inner type appearing
+     to be referenced 10s of millions of times.  */
+  if (info->backref_depth > 0)
+    {
+      if ((info->options & DMGL_NO_RECURSE_LIMIT) == 0
+	  && info->num_backrefs > DEMANGLE_RECURSION_LIMIT)
+	return NULL;
+
+      info->num_backrefs++;
+    }
+  else
+    info->num_backrefs = 0;
+
+  info->backref_depth++;
+
   int save_refpos = info->last_backref;
   info->last_backref = mangled - info->s;
 
@@ -424,6 +467,7 @@ dlang_type_backref (string *decl, const char *mangled, struct dlang_info *info,
     backref = dlang_type (decl, backref, info);
 
   info->last_backref = save_refpos;
+  info->backref_depth--;
 
   if (backref == NULL)
     return NULL;
@@ -1067,7 +1111,7 @@ dlang_identifier (string *decl, const char *mangled, struct dlang_info *info)
 }
 
 /* Extract the plain identifier from MANGLED and prepend/append it to DECL
-   with special treatment for some magic compiler generted symbols.
+   with special treatment for some magic compiler generated symbols.
    Return the remaining string on success or NULL on failure.  */
 static const char *
 dlang_lname (string *decl, const char *mangled, unsigned long len)
@@ -1931,17 +1975,20 @@ dlang_parse_template (string *decl, const char *mangled,
 /* Initialize the information structure we use to pass around information.  */
 static void
 dlang_demangle_init_info (const char *mangled, int last_backref,
-			  struct dlang_info *info)
+			  int options, struct dlang_info *info)
 {
   info->s = mangled;
+  info->options = options;
   info->last_backref = last_backref;
+  info->num_backrefs = 0;
+  info->backref_depth = 0;
 }
 
 /* Extract and demangle the symbol in MANGLED.  Returns the demangled
    signature on success or NULL on failure.  */
 
 char *
-dlang_demangle (const char *mangled, int option ATTRIBUTE_UNUSED)
+dlang_demangle (const char *mangled, int options)
 {
   string decl;
   char *demangled = NULL;
@@ -1962,7 +2009,7 @@ dlang_demangle (const char *mangled, int option ATTRIBUTE_UNUSED)
     {
       struct dlang_info info;
 
-      dlang_demangle_init_info (mangled, strlen (mangled), &info);
+      dlang_demangle_init_info (mangled, strlen (mangled), options, &info);
       mangled = dlang_parse_mangle (&decl, mangled, &info);
 
       /* Check that the entire symbol was successfully demangled.  */
diff --git a/libiberty/dyn-string.c b/libiberty/dyn-string.c
index 8f0a566ed23..6dfb3646847 100644
--- a/libiberty/dyn-string.c
+++ b/libiberty/dyn-string.c
@@ -49,8 +49,8 @@ Boston, MA 02110-1301, USA.  */
    function can be used with a dyn_string struct on the stack or
    embedded in another object.  The contents of the string itself
    are still dynamically allocated.  The string initially is capable
-   of holding at least SPACE characeters, including the terminating
-   NUL.  If SPACE is 0, it will silently be increated to 1.  
+   of holding at least SPACE characters, including the terminating
+   NUL.  If SPACE is 0, it will silently be increased to 1.  
 
    If RETURN_ON_ALLOCATION_FAILURE is defined and memory allocation
    fails, returns 0.  Otherwise returns 1.  */
diff --git a/libiberty/ldirname.c b/libiberty/ldirname.c
index c5e17a80ca4..2b9985c16cd 100644
--- a/libiberty/ldirname.c
+++ b/libiberty/ldirname.c
@@ -26,7 +26,7 @@ Given a pointer to a string containing a typical pathname
 (@samp{/usr/src/cmd/ls/ls.c} for example), returns a string containing the
 passed string up to, but not including, the final directory separator.
 
-If the given pathname doesn't contain a directory separator then this funtion
+If the given pathname doesn't contain a directory separator then this function
 returns the empty string; this includes an empty given pathname.  @code{NULL}
 is returned on memory allocation error.
 
diff --git a/libiberty/make-relative-prefix.c b/libiberty/make-relative-prefix.c
index 58cab574151..05b52c2f2a1 100644
--- a/libiberty/make-relative-prefix.c
+++ b/libiberty/make-relative-prefix.c
@@ -410,7 +410,7 @@ make_relative_prefix_1 (const char *progname, const char *bin_prefix,
 /* Do the full job, including symlink resolution.
    This path will find files installed in the same place as the
    program even when a soft link has been made to the program
-   from somwhere else. */
+   from somewhere else. */
 
 char *
 make_relative_prefix (const char *progname, const char *bin_prefix,
diff --git a/libiberty/obstacks.texi b/libiberty/obstacks.texi
index 37d26c90f1b..9bea973bee2 100644
--- a/libiberty/obstacks.texi
+++ b/libiberty/obstacks.texi
@@ -695,7 +695,7 @@ Summary of Obstacks
 @var{chunk_size} bytes.
 
 @item int obstack_specify_allocation (struct obstack *@var{obstack-ptr}, size_t chunk_size, size_t alignment, void *(*chunkfun) (size_t), void (*freefun) (void *))
-Initialize use of an obstack, specifying intial chunk size, chunk
+Initialize use of an obstack, specifying initial chunk size, chunk
 alignment, and memory allocation functions.
 
 @item int obstack_specify_allocation_with_arg (struct obstack *@var{obstack-ptr}, size_t chunk_size, size_t alignment, void *(*chunkfun) (void *, size_t), void (*freefun) (void *, void *), void *arg)
diff --git a/libiberty/pex-win32.c b/libiberty/pex-win32.c
index 2ba9b69b830..8ea4e7f822a 100644
--- a/libiberty/pex-win32.c
+++ b/libiberty/pex-win32.c
@@ -350,7 +350,7 @@ argv_to_cmdline (char *const *argv)
       /* We only quote arguments that contain spaces, \t or " characters to
 	 prevent wasting 2 chars per argument of the CreateProcess 32k char
 	 limit.  We need only escape embedded double-quotes and immediately
-	 preceeding backslash characters.  A sequence of backslach characters
+	 preceding backslash characters.  A sequence of backslach characters
 	 that is not followed by a double quote character will not be
 	 escaped.  */
       needs_quotes = 0;
@@ -363,7 +363,7 @@ argv_to_cmdline (char *const *argv)
 
 	  if (argv[i][j] == '"')
 	    {
-	      /* Escape preceeding backslashes.  */
+	      /* Escape preceding backslashes.  */
 	      for (k = j - 1; k >= 0 && argv[i][k] == '\\'; k--)
 		cmdline_len++;
 	      /* Escape the quote character.  */
@@ -695,7 +695,7 @@ spawn_script (struct pex_obj *obj,
   int fd = _open (executable, _O_RDONLY);
 
   /* Try to open script, check header format, extract interpreter path,
-     and spawn script using that interpretter. */
+     and spawn script using that interpreter. */
   if (fd >= 0)
     {
       char buf[MAX_PATH + 5];
diff --git a/libiberty/random.c b/libiberty/random.c
index cd0b7399e73..38c4317c5d1 100644
--- a/libiberty/random.c
+++ b/libiberty/random.c
@@ -88,7 +88,7 @@ long int random (void);
    then initialized to contain information for random number generation with
    that much state information.  Good sizes for the amount of state
    information are 32, 64, 128, and 256 bytes.  The state can be switched by
-   calling the setstate() function with the same array as was initiallized
+   calling the setstate() function with the same array as was initialized
    with initstate().  By default, the package runs with 128 bytes of state
    information and generates far better random numbers than a linear
    congruential generator.  If the amount of state information is less than
@@ -362,7 +362,7 @@ setstate (void *arg_state)
 
 /* If we are using the trivial TYPE_0 R.N.G., just do the old linear
    congruential bit.  Otherwise, we do our fancy trinomial stuff, which is the
-   same in all ther other cases due to all the global variables that have been
+   same in all the other cases due to all the global variables that have been
    set up.  The basic operation is to add the number at the rear pointer into
    the one at the front pointer.  Then both pointers are advanced to the next
    location cyclically in the table.  The value returned is the sum generated,
diff --git a/libiberty/regex.c b/libiberty/regex.c
index 459911eaa14..2379fe9eda7 100644
--- a/libiberty/regex.c
+++ b/libiberty/regex.c
@@ -58,7 +58,7 @@
 
 # define WIDE_CHAR_SUPPORT (HAVE_WCTYPE_H && HAVE_WCHAR_H && HAVE_BTOWC)
 
-/* For platform which support the ISO C amendement 1 functionality we
+/* For platform which support the ISO C amendment 1 functionality we
    support user defined character classes.  */
 # if defined _LIBC || WIDE_CHAR_SUPPORT
 /* Solaris 2.5 has a bug: <wchar.h> must be included before <wctype.h>.  */
@@ -1235,7 +1235,7 @@ printchar (int c)
 
 # ifdef WCHAR
 /* This  convert a multibyte string to a wide character string.
-   And write their correspondances to offset_buffer(see below)
+   And write their correspondences to offset_buffer(see below)
    and write whether each wchar_t is binary data to is_binary.
    This assume invalid multibyte sequences as binary data.
    We assume offset_buffer and is_binary is already allocated
@@ -1247,7 +1247,7 @@ static size_t convert_mbs_to_wcs (CHAR_T *dest, const unsigned char* src,
 static size_t
 convert_mbs_to_wcs (CHAR_T *dest, const unsigned char*src, size_t len,
                     int *offset_buffer, char *is_binary)
-     /* It hold correspondances between src(char string) and
+     /* It hold correspondences between src(char string) and
 	dest(wchar_t string) for optimization.
 	e.g. src  = "xxxyzz"
              dest = {'X', 'Y', 'Z'}
@@ -1281,7 +1281,7 @@ convert_mbs_to_wcs (CHAR_T *dest, const unsigned char*src, size_t len,
 
       if (consumed <= 0)
 	/* failed to convert. maybe src contains binary data.
-	   So we consume 1 byte manualy.  */
+	   So we consume 1 byte manually.  */
 	{
 	  *pdest = *psrc;
 	  consumed = 1;
@@ -2174,7 +2174,7 @@ typedef struct
 # ifndef DEFINED_ONCE
 #  if defined _LIBC || WIDE_CHAR_SUPPORT
 /* The GNU C library provides support for user-defined character classes
-   and the functions from ISO C amendement 1.  */
+   and the functions from ISO C amendment 1.  */
 #   ifdef CHARCLASS_NAME_MAX
 #    define CHAR_CLASS_MAX_LENGTH CHARCLASS_NAME_MAX
 #   else
@@ -3416,7 +3416,7 @@ PREFIX(regex_compile) (const char *ARG_PREFIX(pattern),
 				  int32_t idx2 = table[ch];
 				  size_t len = weights[idx2];
 
-				  /* Test whether the lenghts match.  */
+				  /* Test whether the lengths match.  */
 				  if (weights[idx] == len)
 				    {
 				      /* They do.  New compare the bytes of
@@ -4389,7 +4389,7 @@ wcs_compile_range (CHAR_T range_start_char, const CHAR_T **p_ptr,
 	{
 	  /* range_start is a collating symbol.  */
 	  int32_t *wextra;
-	  /* Retreive the index and get collation sequence value.  */
+	  /* Retrieve the index and get collation sequence value.  */
 	  wextra = (int32_t*)(extra + char_set[-range_start_char]);
 	  start_val = wextra[1 + *wextra];
 	}
@@ -5502,7 +5502,7 @@ count_mbs_length(int *offset_buffer, int length)
     return 0;
 
   /* If there are no multibyte character, offset_buffer[i] == i.
-   Optmize for this case.  */
+   Optimize for this case.  */
   if (offset_buffer[length] == length)
     return length;
 
@@ -5538,7 +5538,7 @@ wcs_re_match_2_internal (struct re_pattern_buffer *bufp,
 			 struct re_registers *regs,
                          int stop,
      /* string1 == string2 == NULL means string1/2, size1/2 and
-	mbs_offset1/2 need seting up in this function.  */
+	mbs_offset1/2 need setting up in this function.  */
      /* We need wchar_t* buffers correspond to cstring1, cstring2.  */
                          wchar_t *string1, int size1,
                          wchar_t *string2, int size2,
@@ -5739,7 +5739,7 @@ byte_re_match_2_internal (struct re_pattern_buffer *bufp,
      fill them with converted string.  */
   if (string1 == NULL && string2 == NULL)
     {
-      /* We need seting up buffers here.  */
+      /* We need setting up buffers here.  */
 
       /* We must free wcs buffers in this function.  */
       cant_free_wcs_buf = 0;
diff --git a/libiberty/sigsetmask.c b/libiberty/sigsetmask.c
index f7a24246d1f..d4f27cf6c42 100644
--- a/libiberty/sigsetmask.c
+++ b/libiberty/sigsetmask.c
@@ -1,7 +1,7 @@
 /* Version of sigsetmask.c
    Written by Steve Chamberlain (sac@cygnus.com).
    Contributed by Cygnus Support.
-   This file is in the public doamin. */
+   This file is in the public domain. */
 
 /*
 
diff --git a/libiberty/simple-object-elf.c b/libiberty/simple-object-elf.c
index ef6ec8619c1..bde62304954 100644
--- a/libiberty/simple-object-elf.c
+++ b/libiberty/simple-object-elf.c
@@ -198,7 +198,7 @@ typedef struct {
 #define SHT_RELA	4		/* Relocation entries with addends */
 #define SHT_REL		9		/* Relocation entries, no addends */
 #define SHT_GROUP	17		/* Section contains a section group */
-#define SHT_SYMTAB_SHNDX 18		/* Extended section indeces */
+#define SHT_SYMTAB_SHNDX 18		/* Extended section indices */
 
 /* Values for sh_flags field.  */
 
@@ -246,7 +246,7 @@ typedef struct
 #define STB_WEAK	2	/* Weak global */
 
 #define STV_DEFAULT	0	/* Visibility is specified by binding type */
-#define STV_HIDDEN	2	/* Can only be seen inside currect component */
+#define STV_HIDDEN	2	/* Can only be seen inside current component */
 
 /* Functions to fetch and store different ELF types, depending on the
    endianness and size.  */
@@ -1512,7 +1512,7 @@ simple_object_elf_copy_lto_debug_sections (simple_object_read *sobj,
 		 of __gnu_lto_slim symbol.  */
 	      if (st_shndx == SHN_COMMON)
 		discard = 1;
-	      /* We also need to remove symbols refering to sections
+	      /* We also need to remove symbols referring to sections
 		 we'll eventually remove as with fat LTO objects
 		 we otherwise get duplicate symbols at final link
 		 (with GNU ld, gold is fine and ignores symbols in
diff --git a/libiberty/simple-object-mach-o.c b/libiberty/simple-object-mach-o.c
index 0897a3edf7d..c6dfe697497 100644
--- a/libiberty/simple-object-mach-o.c
+++ b/libiberty/simple-object-mach-o.c
@@ -53,7 +53,7 @@ struct mach_o_header_32
   unsigned char filetype[4];	/* Type of file.  */
   unsigned char ncmds[4];	/* Number of load commands.  */
   unsigned char sizeofcmds[4];	/* Total size of load commands.  */
-  unsigned char flags[4];	/* Flags for special featues.  */
+  unsigned char flags[4];	/* Flags for special features.  */
 };
 
 /* Mach-O header (64-bit version).  */
@@ -66,7 +66,7 @@ struct mach_o_header_64
   unsigned char filetype[4];	/* Type of file.  */
   unsigned char ncmds[4];	/* Number of load commands.  */
   unsigned char sizeofcmds[4];	/* Total size of load commands.  */
-  unsigned char flags[4];	/* Flags for special featues.  */
+  unsigned char flags[4];	/* Flags for special features.  */
   unsigned char reserved[4];	/* Reserved.  Duh.  */
 };
 
@@ -1194,8 +1194,8 @@ simple_object_mach_o_write_segment (simple_object_write *sobj, int descriptor,
       unsigned int i;
 
       /* Write the section header for the wrapper.  */
-      /* Account for any initial aligment - which becomes the alignment for this
-	 created section.  */
+      /* Account for any initial alignment - which becomes the alignment for
+	 this created section.  */
 
       secsize = (offset - index[0]);
       if (!simple_object_mach_o_write_section_header (sobj, descriptor,
@@ -1208,7 +1208,7 @@ simple_object_mach_o_write_segment (simple_object_write *sobj, int descriptor,
 						      errmsg, err))
 	return 0;
 
-      /* Subtract the wrapper section start from the begining of each sub
+      /* Subtract the wrapper section start from the beginning of each sub
 	 section.  */
 
       for (i = 1; i < nsects_in; ++i)
diff --git a/libiberty/strsignal.c b/libiberty/strsignal.c
index 36b41f17e12..33254ca8a23 100644
--- a/libiberty/strsignal.c
+++ b/libiberty/strsignal.c
@@ -152,7 +152,7 @@ static const struct signal_info signal_table[] =
 #endif
 #if defined (SIGIO)
   /* "I/O pending" has also been suggested, but is misleading since the
-     signal only happens when the process has asked for it, not everytime
+     signal only happens when the process has asked for it, not every time
      I/O is pending. */
   ENTRY(SIGIO, "SIGIO", "I/O possible"),
 #endif
@@ -208,7 +208,7 @@ static const struct signal_info signal_table[] =
   ENTRY(SIGGRANT, "SIGGRANT", "Monitor mode granted"),
 #endif
 #if defined (SIGRETRACT)
-  ENTRY(SIGRETRACT, "SIGRETRACT", "Need to relinguish monitor mode"),
+  ENTRY(SIGRETRACT, "SIGRETRACT", "Need to relinquish monitor mode"),
 #endif
 #if defined (SIGMSG)
   ENTRY(SIGMSG, "SIGMSG", "Monitor mode data available"),
diff --git a/libiberty/testsuite/d-demangle-expected b/libiberty/testsuite/d-demangle-expected
index cfbdf2a52cb..8c671b62316 100644
--- a/libiberty/testsuite/d-demangle-expected
+++ b/libiberty/testsuite/d-demangle-expected
@@ -1475,3 +1475,15 @@ demangle.anonymous.foo
 --format=auto
 _D8demangle9anonymous03fooZ
 demangle.anonymous.foo
+#
+# This symbol was seen in the wild.  It has a pattern of back
+# references that result in exponential growth, with the innermost
+# type being referenced 10s of millions of times.  We use the
+# demangler's recursion limit to place a hard cap on back reference
+# usage, which causes the demangler to safely bail out before
+# consuming an excessive amount of memory.  Trying to demangle this
+# without the recursion limit in place will eventually cause the OOM
+# killer to kick in.
+--format=dlang
[encoded data, 5394 characters]

base-commit: 4562eab73d375e57f3c5a67f62d2678d7730d7ab
-- 
2.25.4


From aburgess@redhat.com  Tue Jun  9 11:13:10 2026
From: aburgess@redhat.com (Andrew Burgess)
Date: Tue, 09 Jun 2026 12:13:10 +0100
Subject: [PATCH] libiberty: sync with gcc commit df3510f80e7c02d9
In-Reply-To: <ff87d7cb74f9d3d3b81aeca0a979d3dcc1531567.1781002240.git.aburgess@redhat.com>
References: <ff87d7cb74f9d3d3b81aeca0a979d3dcc1531567.1781002240.git.aburgess@redhat.com>
Message-ID: <87a4t4q855.fsf@redhat.com>

Andrew Burgess <aburgess@redhat.com> writes:

> From: Dhruv Chawla <dhruvc@nvidia.com>

Apologies Dhruv, due to how I pulled the patches from gcc to
binutils-gdb, you ended up as the author in my local branch, which I
failed to spot prior to sending the email out.

I've updated the author to myself now, so this back-port will not be
blamed on you :)

Thanks,
Andrew


From Wilco.Dijkstra@arm.com  Tue Jun  9 12:25:04 2026
From: Wilco.Dijkstra@arm.com (Wilco Dijkstra)
Date: Tue, 9 Jun 2026 12:25:04 +0000
Subject: [PATCH] AArch64 gas: Block section relative symbols in GOT
 relocations [PR30788]
In-Reply-To: <PAWPR08MB8982EA96A85A9846678CCFB5830B2@PAWPR08MB8982.eurprd08.prod.outlook.com>
References: <PAWPR08MB8982EA96A85A9846678CCFB5830B2@PAWPR08MB8982.eurprd08.prod.outlook.com>
Message-ID: <DB3PR08MB89864BF5C914D6D555BB1868831D2@DB3PR08MB8986.eurprd08.prod.outlook.com>


ping

________________________________________
From:?Wilco Dijkstra <Wilco.Dijkstra@arm.com>
Sent:?26 May 2026 19:37
To:?Alice Carlotti <Alice.Carlotti@arm.com>; Richard Earnshaw <Richard.Earnshaw@arm.com>
Cc:?binutils@sourceware.org <binutils@sourceware.org>
Subject:?[PATCH] AArch64 gas: Block section relative symbols in GOT relocations [PR30788]
?

By default, GAS changes GOT relocations of local symbols into section relative.
This is incorrect since GOT relocations do not support offsets.? Update
aarch64_fix_adjustable() to explicitly disallow this for GOT relocations.
This fixes PR30788.

---

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index fb58bcca9b1059e5d4d831a0a8ea9a33d05deaba..9632a5b2a015b38f2d35fa2f569093b9b52790f9 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10389,6 +10389,19 @@ aarch64_fix_adjustable (fixS *fixp)
?? if (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION)
???? return false;
?
+? /* GOT relocations cannot have an offset or use section-relative symbols.? */
+? if (fixp->fx_r_type == BFD_RELOC_AARCH64_ADR_GOT_PAGE
+????? || fixp->fx_r_type == BFD_RELOC_AARCH64_GOT_LD_PREL19
+????? || fixp->fx_r_type == BFD_RELOC_AARCH64_LD_GOT_LO12_NC
+????? || fixp->fx_r_type == BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
+????? || fixp->fx_r_type == BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
+????? || fixp->fx_r_type == BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
+????? || fixp->fx_r_type == BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
+????? || fixp->fx_r_type == BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
+????? || fixp->fx_r_type == BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
+????? || fixp->fx_r_type == BFD_RELOC_AARCH64_MOVW_GOTOFF_G1)
+??? return false;
+
?? return true;
?}
?
diff --git a/gas/testsuite/gas/aarch64/reloc-insn.d b/gas/testsuite/gas/aarch64/reloc-insn.d
index dc73bd2832a2e802fa93b99f733752ee453d9826..3fcb28dce3c2b864643f5a189b8cd4fadb91b64f 100644
--- a/gas/testsuite/gas/aarch64/reloc-insn.d
+++ b/gas/testsuite/gas/aarch64/reloc-insn.d
@@ -159,9 +159,9 @@ Disassembly of section \.text:
? 18c:? 39400001???????? ldrb??? w1, \[x0\]
? 190:? d65f03c0???????? ret
? 194:? f94001bc???????? ldr???? x28, \[x13\]
-?????????????????????? 194: R_AARCH64_LD64_GOTPAGE_LO15??????? \.data
+?????????????????????? 194: R_AARCH64_LD64_GOTPAGE_LO15??????? dummy
? 198:? f9400000???????? ldr???? x0, \[x0\]
-?????????????????????? 198: R_AARCH64_LD64_GOTOFF_LO15 .data
+?????????????????????? 198: R_AARCH64_LD64_GOTOFF_LO15 dummy
?
?000000000000019c <llit>:
? 19c:? deadf00d???????? \.word? 0xdeadf00d

From hyc@symas.com  Tue Jun  9 13:45:37 2026
From: hyc@symas.com (Howard Chu)
Date: Tue, 9 Jun 2026 14:45:37 +0100
Subject: Planned binutils-2.46.1 release
In-Reply-To: <877bo8h5n5.fsf@gentoo.org>
References: <87o6ilgdrj.fsf@gentoo.org> <87se7wfp9f.fsf@gentoo.org>
 <agQ8EH3YIJ6C2dUs@squeak.grove.modra.org> <877bo8h5n5.fsf@gentoo.org>
Message-ID: <988b682a-94f9-47b9-8624-d34621d85635@symas.com>

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA512

Sam James wrote:
>> On Tue, May 12, 2026 at 07:37:16PM +0100, Sam James wrote:
>>> Sam James <sam@gentoo.org> writes:
>>> 
>>>> Hi all,
>>>> 
>>>> I plan to make a point release for binutils-2.46 in a few days, motivated by the C23/glibc-2.43 fixes for const correctness, as the 2.46 release
>>>> fails to build w/ -Werror enabled by default [0].
>>>> 
>>>> Please look to see if any other fixes should be backported to binutils-2_46-branch.

Would be nice to see the fix for this rolled in.

https://sourceware.org/bugzilla/show_bug.cgi?id=34204

- -- 
  -- Howard Chu
  CTO, Symas Corp.           http://www.symas.com
  Director, Highland Sun     http://highlandsun.com/hyc/
  Chief Architect, OpenLDAP  http://www.openldap.org/project/
-----BEGIN PGP SIGNATURE-----

iF0EAREKAB0WIQSUBGGam6fLX3meDqH9KnC0SrEbpwUCaigZAQAKCRD9KnC0SrEb
p3iLAJ9L3xA9KaaHAh2sYZ/bI2zngbHcngCfbhtAt1BXJm5dT2JA9kD/dEjv1ig=
=FUiK
-----END PGP SIGNATURE-----

From sam@gentoo.org  Tue Jun  9 15:03:26 2026
From: sam@gentoo.org (Sam James)
Date: Tue, 09 Jun 2026 16:03:26 +0100
Subject: Planned binutils-2.46.1 release
In-Reply-To: <988b682a-94f9-47b9-8624-d34621d85635@symas.com>
References: <87o6ilgdrj.fsf@gentoo.org> <87se7wfp9f.fsf@gentoo.org>
 <agQ8EH3YIJ6C2dUs@squeak.grove.modra.org> <877bo8h5n5.fsf@gentoo.org>
 <988b682a-94f9-47b9-8624-d34621d85635@symas.com>
Message-ID: <87h5nbg3i9.fsf@gentoo.org>

Howard Chu <hyc@symas.com> writes:

> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA512
>
> Sam James wrote:
>>> On Tue, May 12, 2026 at 07:37:16PM +0100, Sam James wrote:
>>>> Sam James <sam@gentoo.org> writes:
>>>> 
>>>>> Hi all,
>>>>> 
>>>>> I plan to make a point release for binutils-2.46 in a few days, motivated by the C23/glibc-2.43 fixes for const correctness, as the 2.46 release
>>>>> fails to build w/ -Werror enabled by default [0].
>>>>> 
>>>>> Please look to see if any other fixes should be backported to binutils-2_46-branch.
>
> Would be nice to see the fix for this rolled in.

It's not yet on master but I cc'd Alan on the bug and commented. Thanks.

>
> https://sourceware.org/bugzilla/show_bug.cgi?id=34204
>
> - -- 
>   -- Howard Chu
>   CTO, Symas Corp.           http://www.symas.com
>   Director, Highland Sun     http://highlandsun.com/hyc/
>   Chief Architect, OpenLDAP  http://www.openldap.org/project/
> -----BEGIN PGP SIGNATURE-----
>
> iF0EAREKAB0WIQSUBGGam6fLX3meDqH9KnC0SrEbpwUCaigZAQAKCRD9KnC0SrEb
> p3iLAJ9L3xA9KaaHAh2sYZ/bI2zngbHcngCfbhtAt1BXJm5dT2JA9kD/dEjv1ig=
> =FUiK
> -----END PGP SIGNATURE-----
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From jiawei@iscas.ac.cn  Tue Jun  9 15:38:43 2026
From: jiawei@iscas.ac.cn (Jiawei)
Date: Tue,  9 Jun 2026 23:38:43 +0800
Subject: [RFC 1/2] RISC-V: Add Zvdota extension classes
Message-ID: <20260609153844.538604-1-jiawei@iscas.ac.cn>

This patch adds assembler/disassembler support for the RISC-V Zvdota
family of extensions [1], which compute a dot product between two vector
register groups.

The Zvdota extension family includes the following extensions:

Zvqwdota8i: dot product of 8-bit integers with 32-bit accumulation.
Zvqwdota16i: dot product of 16-bit integers with 64-bit accumulation.
Zvfwdota16bf: dot product of bfloat16 floating-point numbers with
32-bit accumulation.
Zvfqwdota8f: dot product of 8-bit floating-point numbers with
32-bit accumulation.

Zvdota also uses the vtype alternative format bit, altfmt, which is bit 8
of the vtype CSR. This patch adds symbolic e8alt and e16alt vsew
constants for vsetvli/vsetivli so that assembly code can select the
alternative element formats required by these dot-product instructions.

[1] https://github.com/riscv/riscv-isa-manual/blob/zvbdot/src/zvdota.adoc

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): New implies.
	(riscv_supported_std_z_ext): New extensions.
	(riscv_multi_subset_supports): Ditto.
	(riscv_multi_subset_supports_ext): Ditto.

gas/ChangeLog:

	* NEWS: Add zvqwdota8i, zvqwdota16i, zvfwdota16bf and
	zvfqwdota8f extensions.
	* config/tc-riscv.c (riscv_vsew_altfmt): New vsew altfmt
	constants array for e8alt and e16alt.
	(riscv_vtype_altfmt_supported): New function.
	(my_getVsetvliExpression): Ditto.
	* testsuite/gas/riscv/march-help.l: New test.
	* testsuite/gas/riscv/vector-vtype-altfmt.d: Ditto.
	* testsuite/gas/riscv/vector-vtype-altfmt.s: Ditto.
	* testsuite/gas/riscv/zvdota.d: Ditto.
	* testsuite/gas/riscv/zvdota.s: Ditto.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VQWDOTAU_VV, MASK_VQWDOTAU_VV): New
	encoding.
	(MATCH_VQWDOTAS_VV, MASK_VQWDOTAS_VV): Ditto.
	(MATCH_VFWDOTA_VV, MASK_VFWDOTA_VV): Ditto.
	(MATCH_VFQWDOTA_VV, MASK_VFQWDOTA_VV): Ditto.
	(MATCH_VFQWDOTA_ALT_VV, MASK_VFQWDOTA_ALT_VV): Ditto.
	(DECLARE_INSN): New declarations.
	* opcode/riscv.h (OP_MASK_VTYPE_ALTFMT, OP_SH_VTYPE_ALTFMT):
	New vtype altfmt.
	(enum riscv_insn_class): New extension classes.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Add altfmt support.
	* riscv-opc.c (riscv_opcodes): New instructions.

---
 bfd/elfxx-riscv.c                             | 29 ++++++++++++++
 gas/NEWS                                      |  3 ++
 gas/config/tc-riscv.c                         | 38 +++++++++++++++++--
 gas/testsuite/gas/riscv/march-help.l          |  4 ++
 gas/testsuite/gas/riscv/vector-vtype-altfmt.d | 15 ++++++++
 gas/testsuite/gas/riscv/vector-vtype-altfmt.s |  7 ++++
 gas/testsuite/gas/riscv/zvdota.d              | 19 ++++++++++
 gas/testsuite/gas/riscv/zvdota.s              | 11 ++++++
 include/opcode/riscv-opc.h                    | 17 +++++++++
 include/opcode/riscv.h                        |  7 ++++
 opcodes/riscv-dis.c                           | 22 ++++++++---
 opcodes/riscv-opc.c                           |  7 ++++
 12 files changed, 170 insertions(+), 9 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/vector-vtype-altfmt.d
 create mode 100644 gas/testsuite/gas/riscv/vector-vtype-altfmt.s
 create mode 100644 gas/testsuite/gas/riscv/zvdota.d
 create mode 100644 gas/testsuite/gas/riscv/zvdota.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 67fbf0f72ca..7714e5dcd49 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1234,6 +1234,10 @@ static const struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zvfhmin", "+zve32f", check_implicit_always},
   {"zvfbfwma", "+zve32f,+zfbfmin", check_implicit_always},
   {"zvfbfmin", "+zve32f", check_implicit_always},
+  {"zvfqwdota8f", "+zve32f", check_implicit_always},
+  {"zvfwdota16bf", "+zve32f", check_implicit_always},
+  {"zvqwdota8i", "+zve32x", check_implicit_always},
+  {"zvqwdota16i", "+zve64x", check_implicit_always},
   {"zve64d", "+d,+zve64f", check_implicit_always},
   {"zve64f", "+zve32f,+zve64x,+zvl64b", check_implicit_always},
   {"zve32f", "+f,+zve32x,+zvl32b", check_implicit_always},
@@ -1517,6 +1521,8 @@ static const struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvfbfwma",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvfh",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvfhmin",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"zvfqwdota8f",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"zvfwdota16bf",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvkb",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvkg",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvkn",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
@@ -1531,6 +1537,8 @@ static const struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvksg",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvksc",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvkt",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"zvqwdota8i",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"zvqwdota16i",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
@@ -2970,6 +2978,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zvfbfmin");
     case INSN_CLASS_ZVFBFWMA:
       return riscv_subset_supports (rps, "zvfbfwma");
+    case INSN_CLASS_ZVFQWDOTA8F:
+      return riscv_subset_supports (rps, "zvfqwdota8f");
+    case INSN_CLASS_ZVFWDOTA16BF:
+      return riscv_subset_supports (rps, "zvfwdota16bf");
     case INSN_CLASS_ZVKB:
       return riscv_subset_supports (rps, "zvkb");
     case INSN_CLASS_ZVKG:
@@ -2983,6 +2995,13 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zvksed");
     case INSN_CLASS_ZVKSH:
       return riscv_subset_supports (rps, "zvksh");
+    case INSN_CLASS_ZVQWDOTA8I:
+      return riscv_subset_supports (rps, "zvqwdota8i");
+    case INSN_CLASS_ZVQWDOTA16I:
+      return riscv_subset_supports (rps, "zvqwdota16i");
+    case INSN_CLASS_ZVQWDOTA8I_OR_ZVQWDOTA16I:
+      return (riscv_subset_supports (rps, "zvqwdota8i")
+	      || riscv_subset_supports (rps, "zvqwdota16i"));
     case INSN_CLASS_ZCB:
       return riscv_subset_supports (rps, "zcb");
     case INSN_CLASS_ZCB_AND_ZBB:
@@ -3286,6 +3305,10 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "zvfbfmin";
     case INSN_CLASS_ZVFBFWMA:
       return "zvfbfwma";
+    case INSN_CLASS_ZVFQWDOTA8F:
+      return "zvfqwdota8f";
+    case INSN_CLASS_ZVFWDOTA16BF:
+      return "zvfwdota16bf";
     case INSN_CLASS_ZVKB:
       return _("zvkb");
     case INSN_CLASS_ZVKG:
@@ -3298,6 +3321,12 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zvksed");
     case INSN_CLASS_ZVKSH:
       return _("zvksh");
+    case INSN_CLASS_ZVQWDOTA8I:
+      return "zvqwdota8i";
+    case INSN_CLASS_ZVQWDOTA16I:
+      return "zvqwdota16i";
+    case INSN_CLASS_ZVQWDOTA8I_OR_ZVQWDOTA16I:
+      return _("zvqwdota8i' or `zvqwdota16i");
     case INSN_CLASS_ZCB:
       return "zcb";
     case INSN_CLASS_ZCB_AND_ZBA:
diff --git a/gas/NEWS b/gas/NEWS
index e384d1135c0..ddb7983aea0 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,8 @@
 -*- text -*-
 
+* Add support for RISC-V standard extensions:
+  zvqwdota8i, zvqwdota16i, zvfwdota16bf and zvfqwdota8f v1.0.
+
 Changes in 2.46:
 
 * Add support for AMD Zen6 processor.
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index be3501930b3..42397933662 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -2644,6 +2644,23 @@ my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
   return my_getSmallExpression (ep, reloc, str, percent_op_null);
 }
 
+/* The vsetvli/vsetivli vsew altfmt constants.  */
+static const char * const riscv_vsew_altfmt[] =
+{
+  "e8alt", "e16alt"
+};
+
+static bool
+riscv_vtype_altfmt_supported (void)
+{
+  return (riscv_subset_supports (&riscv_rps_as, "zvfbfa")
+	  || riscv_subset_supports (&riscv_rps_as, "zvfofp8min")
+	  || riscv_subset_supports (&riscv_rps_as, "zvfqwdota8f")
+	  || riscv_subset_supports (&riscv_rps_as, "zvfwdota16bf")
+	  || riscv_subset_supports (&riscv_rps_as, "zvqwdota8i")
+	  || riscv_subset_supports (&riscv_rps_as, "zvqwdota16i"));
+}
+
 /* Parse string STR as a vsetvli operand.  Store the expression in *EP.
    On exit, EXPR_PARSE_END points to the first character after the
    expression.  */
@@ -2652,11 +2669,25 @@ static void
 my_getVsetvliExpression (expressionS *ep, char *str)
 {
   unsigned int vsew_value = 0, vlmul_value = 0;
-  unsigned int vta_value = 0, vma_value = 0;
+  unsigned int vta_value = 0, vma_value = 0, altfmt_value = 0;
   bool vsew_found = false, vlmul_found = false;
   bool vta_found = false, vma_found = false;
 
-  if (arg_lookup (&str, riscv_vsew, ARRAY_SIZE (riscv_vsew), &vsew_value))
+  if (arg_lookup (&str, riscv_vsew_altfmt,
+		  ARRAY_SIZE (riscv_vsew_altfmt), &vsew_value))
+    {
+      if (*str == ',')
+	++str;
+      if (vsew_found)
+	as_bad (_("multiple vsew constants"));
+      if (!riscv_vtype_altfmt_supported ())
+	as_bad (_("symbolic vtype altfmt requires `zvfbfa', "
+		  "`zvfofp8min' or a `zvdota' extension"));
+      altfmt_value = 1 << OP_SH_VTYPE_ALTFMT;
+      vsew_found = true;
+    }
+  if (!vsew_found
+      && arg_lookup (&str, riscv_vsew, ARRAY_SIZE (riscv_vsew), &vsew_value))
     {
       if (*str == ',')
 	++str;
@@ -2695,7 +2726,8 @@ my_getVsetvliExpression (expressionS *ep, char *str)
       ep->X_add_number = (vlmul_value << OP_SH_VLMUL)
 			 | (vsew_value << OP_SH_VSEW)
 			 | (vta_value << OP_SH_VTA)
-			 | (vma_value << OP_SH_VMA);
+			 | (vma_value << OP_SH_VMA)
+			 | altfmt_value;
       expr_parse_end = str;
     }
   else
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 0ce2f896735..51e830c021b 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -74,6 +74,8 @@ All available -march extensions for RISC-V:
 	zvfbfwma                                1.0
 	zvfh                                    1.0
 	zvfhmin                                 1.0
+	zvfqwdota8f                             1.0
+	zvfwdota16bf                            1.0
 	zvkb                                    1.0
 	zvkg                                    1.0
 	zvkn                                    1.0
@@ -88,6 +90,8 @@ All available -march extensions for RISC-V:
 	zvksg                                   1.0
 	zvksc                                   1.0
 	zvkt                                    1.0
+	zvqwdota8i                              1.0
+	zvqwdota16i                             1.0
 	zvl32b                                  1.0
 	zvl64b                                  1.0
 	zvl128b                                 1.0
diff --git a/gas/testsuite/gas/riscv/vector-vtype-altfmt.d b/gas/testsuite/gas/riscv/vector-vtype-altfmt.d
new file mode 100644
index 00000000000..85255b22c6a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/vector-vtype-altfmt.d
@@ -0,0 +1,15 @@
+#as: -march=rv32i_zvqwdota8i
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+1c0572d7[ 	]+vsetvli[ 	]+t0,a0,e8alt,m1,ta,ma
+[ 	]+[0-9a-f]+:[ 	]+1c8572d7[ 	]+vsetvli[ 	]+t0,a0,e16alt,m1,ta,ma
+[ 	]+[0-9a-f]+:[ 	]+dc0572d7[ 	]+vsetivli[ 	]+t0,10,e8alt,m1,ta,ma
+[ 	]+[0-9a-f]+:[ 	]+dc8572d7[ 	]+vsetivli[ 	]+t0,10,e16alt,m1,ta,ma
+[ 	]+[0-9a-f]+:[ 	]+1d0572d7[ 	]+vsetvli[ 	]+t0,a0,464
+[ 	]+[0-9a-f]+:[ 	]+1d8572d7[ 	]+vsetvli[ 	]+t0,a0,472
diff --git a/gas/testsuite/gas/riscv/vector-vtype-altfmt.s b/gas/testsuite/gas/riscv/vector-vtype-altfmt.s
new file mode 100644
index 00000000000..db76a5278ca
--- /dev/null
+++ b/gas/testsuite/gas/riscv/vector-vtype-altfmt.s
@@ -0,0 +1,7 @@
+target:
+	vsetvli t0, a0, e8alt, m1, ta, ma
+	vsetvli t0, a0, e16alt, m1, ta, ma
+	vsetivli t0, 10, e8alt, m1, ta, ma
+	vsetivli t0, 10, e16alt, m1, ta, ma
+	vsetvli t0, a0, 0x1d0
+	vsetvli t0, a0, 0x1d8
diff --git a/gas/testsuite/gas/riscv/zvdota.d b/gas/testsuite/gas/riscv/zvdota.d
new file mode 100644
index 00000000000..155510926c7
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvdota.d
@@ -0,0 +1,19 @@
+#as: -march=rv64gc_zvqwdota8i_zvqwdota16i_zvfwdota16bf_zvfqwdota8f
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+9a860277[ 	]+vqwdotau.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+98860277[ 	]+vqwdotau.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+9e860277[ 	]+vqwdotas.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+9c860277[ 	]+vqwdotas.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+92861277[ 	]+vfwdota.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+90861277[ 	]+vfwdota.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+9a861277[ 	]+vfqwdota.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+98861277[ 	]+vfqwdota.vv[ 	]+v4,v8,v12,v0.t
+[ 	]+[0-9a-f]+:[ 	]+9e861277[ 	]+vfqwdota.alt.vv[ 	]+v4,v8,v12
+[ 	]+[0-9a-f]+:[ 	]+9c861277[ 	]+vfqwdota.alt.vv[ 	]+v4,v8,v12,v0.t
diff --git a/gas/testsuite/gas/riscv/zvdota.s b/gas/testsuite/gas/riscv/zvdota.s
new file mode 100644
index 00000000000..d32856426e5
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvdota.s
@@ -0,0 +1,11 @@
+target:
+	vqwdotau.vv v4, v8, v12
+	vqwdotau.vv v4, v8, v12, v0.t
+	vqwdotas.vv v4, v8, v12
+	vqwdotas.vv v4, v8, v12, v0.t
+	vfwdota.vv v4, v8, v12
+	vfwdota.vv v4, v8, v12, v0.t
+	vfqwdota.vv v4, v8, v12
+	vfqwdota.vv v4, v8, v12, v0.t
+	vfqwdota.alt.vv v4, v8, v12
+	vfqwdota.alt.vv v4, v8, v12, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 6f2775c6152..359b4f64ab8 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2549,6 +2549,17 @@
 #define MASK_VFWMACCBF16_VF 0xfc00707f
 #define MATCH_VFWMACCBF16_VV 0xec001057
 #define MASK_VFWMACCBF16_VV 0xfc00707f
+/* Zvdota instructions.  */
+#define MATCH_VQWDOTAU_VV 0x98000077
+#define MASK_VQWDOTAU_VV 0xfc00707f
+#define MATCH_VQWDOTAS_VV 0x9c000077
+#define MASK_VQWDOTAS_VV 0xfc00707f
+#define MATCH_VFWDOTA_VV 0x90001077
+#define MASK_VFWDOTA_VV 0xfc00707f
+#define MATCH_VFQWDOTA_VV 0x98001077
+#define MASK_VFQWDOTA_VV 0xfc00707f
+#define MATCH_VFQWDOTA_ALT_VV 0x9c001077
+#define MASK_VFQWDOTA_ALT_VV 0xfc00707f
 /* Vendor-specific (CORE-V) Xcvmac instructions.  */
 #define MATCH_CV_MAC       0x9000302b
 #define MASK_CV_MAC        0xfe00707f
@@ -4795,6 +4806,12 @@ DECLARE_INSN(VFWCVTBF16_F_F_V, MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V)
 /* Zvfbfwma instructions.  */
 DECLARE_INSN(VFWMACCBF16_VF, MATCH_VFWMACCBF16_VF, MASK_VFWMACCBF16_VF)
 DECLARE_INSN(VFWMACCBF16_VV, MATCH_VFWMACCBF16_VV, MASK_VFWMACCBF16_VV)
+/* Zvdota instructions.  */
+DECLARE_INSN(vqwdotau_vv, MATCH_VQWDOTAU_VV, MASK_VQWDOTAU_VV)
+DECLARE_INSN(vqwdotas_vv, MATCH_VQWDOTAS_VV, MASK_VQWDOTAS_VV)
+DECLARE_INSN(vfwdota_vv, MATCH_VFWDOTA_VV, MASK_VFWDOTA_VV)
+DECLARE_INSN(vfqwdota_vv, MATCH_VFQWDOTA_VV, MASK_VFQWDOTA_VV)
+DECLARE_INSN(vfqwdota_alt_vv, MATCH_VFQWDOTA_ALT_VV, MASK_VFQWDOTA_ALT_VV)
 /* Zvbb/Zvkb instructions.  */
 DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV)
 DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index de105f5df8b..59bc09e4780 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -371,6 +371,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
 #define OP_SH_VTA		6
 #define OP_MASK_VMA		0x1
 #define OP_SH_VMA		7
+#define OP_MASK_VTYPE_ALTFMT	0x1
+#define OP_SH_VTYPE_ALTFMT	8
 #define OP_MASK_VWD		0x1
 #define OP_SH_VWD		26
 
@@ -546,12 +548,17 @@ enum riscv_insn_class
   INSN_CLASS_ZVBC,
   INSN_CLASS_ZVFBFMIN,
   INSN_CLASS_ZVFBFWMA,
+  INSN_CLASS_ZVFQWDOTA8F,
+  INSN_CLASS_ZVFWDOTA16BF,
   INSN_CLASS_ZVKB,
   INSN_CLASS_ZVKG,
   INSN_CLASS_ZVKNED,
   INSN_CLASS_ZVKNHA_OR_ZVKNHB,
   INSN_CLASS_ZVKSED,
   INSN_CLASS_ZVKSH,
+  INSN_CLASS_ZVQWDOTA8I,
+  INSN_CLASS_ZVQWDOTA16I,
+  INSN_CLASS_ZVQWDOTA8I_OR_ZVQWDOTA16I,
   INSN_CLASS_ZICFISS,
   INSN_CLASS_ZICFISS_AND_ZCMOP,
   INSN_CLASS_ZICFILP,
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index eda802ff420..6ccccd864f2 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -453,7 +453,9 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 		unsigned int imm_vsew = EXTRACT_OPERAND (VSEW, imm);
 		unsigned int imm_vta = EXTRACT_OPERAND (VTA, imm);
 		unsigned int imm_vma = EXTRACT_OPERAND (VMA, imm);
-		unsigned int imm_vtype_res = (imm >> 8);
+		unsigned int imm_vtype_altfmt
+		  = EXTRACT_OPERAND (VTYPE_ALTFMT, imm);
+		unsigned int imm_vtype_res = (imm >> 9);
 
 		if (imm_vsew < ARRAY_SIZE (riscv_vsew)
 		    && imm_vlmul < ARRAY_SIZE (riscv_vlmul)
@@ -461,11 +463,19 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 		    && imm_vma < ARRAY_SIZE (riscv_vma)
 		    && !imm_vtype_res
 		    && riscv_vsew[imm_vsew] != NULL
-		    && riscv_vlmul[imm_vlmul] != NULL)
-		  print (info->stream, dis_style_text, "%s,%s,%s,%s",
-			 riscv_vsew[imm_vsew],
-			 riscv_vlmul[imm_vlmul], riscv_vta[imm_vta],
-			 riscv_vma[imm_vma]);
+		    && riscv_vlmul[imm_vlmul] != NULL
+		    && (!imm_vtype_altfmt || imm_vsew < 2))
+		  {
+		    if (imm_vtype_altfmt)
+		      print (info->stream, dis_style_text, "%salt",
+			     riscv_vsew[imm_vsew]);
+		    else
+		      print (info->stream, dis_style_text, "%s",
+			     riscv_vsew[imm_vsew]);
+		    print (info->stream, dis_style_text, ",%s,%s,%s",
+			   riscv_vlmul[imm_vlmul], riscv_vta[imm_vta],
+			   riscv_vma[imm_vma]);
+		  }
 		else
 		  print (info->stream, dis_style_immediate, "%d", imm);
 	      }
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index ba155335878..3c4e4b19af5 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2226,6 +2226,13 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vfwmaccbf16.vf",  0, INSN_CLASS_ZVFBFWMA, "Vd,S,VtVm",  MATCH_VFWMACCBF16_VF, MASK_VFWMACCBF16_VF, match_opcode, 0},
 {"vfwmaccbf16.vv",  0, INSN_CLASS_ZVFBFWMA, "Vd,Vs,VtVm", MATCH_VFWMACCBF16_VV, MASK_VFWMACCBF16_VV, match_opcode, 0},
 
+/* Zvdota instructions.  */
+{"vqwdotau.vv", 0, INSN_CLASS_ZVQWDOTA8I_OR_ZVQWDOTA16I, "Vd,Vt,VsVm", MATCH_VQWDOTAU_VV, MASK_VQWDOTAU_VV, match_opcode, 0},
+{"vqwdotas.vv", 0, INSN_CLASS_ZVQWDOTA8I_OR_ZVQWDOTA16I, "Vd,Vt,VsVm", MATCH_VQWDOTAS_VV, MASK_VQWDOTAS_VV, match_opcode, 0},
+{"vfwdota.vv",  0, INSN_CLASS_ZVFWDOTA16BF, "Vd,Vt,VsVm", MATCH_VFWDOTA_VV, MASK_VFWDOTA_VV, match_opcode, 0},
+{"vfqwdota.vv", 0, INSN_CLASS_ZVFQWDOTA8F, "Vd,Vt,VsVm", MATCH_VFQWDOTA_VV, MASK_VFQWDOTA_VV, match_opcode, 0},
+{"vfqwdota.alt.vv", 0, INSN_CLASS_ZVFQWDOTA8F, "Vd,Vt,VsVm", MATCH_VFQWDOTA_ALT_VV, MASK_VFQWDOTA_ALT_VV, match_opcode, 0},
+
 /* Zvbb/Zvkb instructions.  */
 {"vandn.vv",   0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VANDN_VV, MASK_VANDN_VV, match_opcode, 0},
 {"vandn.vx",   0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VANDN_VX, MASK_VANDN_VX, match_opcode, 0},
-- 
2.43.0


From jiawei@iscas.ac.cn  Tue Jun  9 15:38:44 2026
From: jiawei@iscas.ac.cn (Jiawei)
Date: Tue,  9 Jun 2026 23:38:44 +0800
Subject: [RFC 2/2] RISC-V: Add Zvbdota extension support
In-Reply-To: <20260609153844.538604-1-jiawei@iscas.ac.cn>
References: <20260609153844.538604-1-jiawei@iscas.ac.cn>
Message-ID: <20260609153844.538604-2-jiawei@iscas.ac.cn>

This patch supports the RISC-V Zvbdota family of batched dot-product
extensions [1].

Compared to the non-batched Zvdota family, Zvbdota computes up to eight
dot products at a time.  These instructions use an EMUL=8 `vs2` vector
register group and a scaled-by-8 `ci` immediate encoded in `vs2[2:0]`.
This patch adds assembler/disassembler support for those additional
operand constraints.

The Zvbdota extension family includes the following extensions:

* Zvqwbdota8i: batched dot product of 8-bit integers with 32-bit
  accumulation.
* Zvqwbdota16i: batched dot product of 16-bit integers with 64-bit
  accumulation.
* Zvfwbdota16bf: batched dot product of bfloat16 floating-point numbers
  with 32-bit accumulation.
* Zvfqwbdota8f: batched dot product of 8-bit floating-point numbers with
  32-bit accumulation.
* Zvfbdota32f: batched dot product of 32-bit single-precision
  floating-point numbers with 32-bit accumulation.

[1] https://github.com/riscv/riscv-isa-manual/blob/zvbdot/src/zvdota.adoc


bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): New implies.
	(riscv_supported_std_z_ext): New extensions.
	(riscv_multi_subset_supports): Ditto.
	(riscv_multi_subset_supports_ext): Ditto.

gas/ChangeLog:

	* NEWS: Add zvqwbdota8i, zvqwbdota16i, zvfwbdota16bf,
	zvfqwbdota8f and zvfbdota32f extensions.
	* config/tc-riscv.c (validate_riscv_insn): Add Zvbdota operand
	type 'q' and 'r' bits validation.
	(riscv_vtype_altfmt_supported): Add Zvbdota extensions.
	(my_getVsetvliExpression): Update altfmt error message.
	(riscv_ip): Add 'q' operand for VS2 EMUL=8 alignment check
	and 'r' operand for ci immediate.
	* testsuite/gas/riscv/march-help.l: Ditto.
	* testsuite/gas/riscv/zvbdota.d: New test.
	* testsuite/gas/riscv/zvbdota.s: Ditto.
	* testsuite/gas/riscv/zvbdota-operands-fail.d: Ditto.
	* testsuite/gas/riscv/zvbdota-operands-fail.l: Ditto.
	* testsuite/gas/riscv/zvbdota-operands-fail.s: Ditto.
	* testsuite/gas/riscv/zvbdota-zvqwbdota16i.d: Ditto.
	* testsuite/gas/riscv/zvbdota-zvqwbdota16i.s: Ditto.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VQWBDOTAU_VV, MASK_VQWBDOTAU_VV):
	New encoding.
	(MATCH_VQWBDOTAS_VV, MASK_VQWBDOTAS_VV): Ditto.
	(MATCH_VFWBDOTA_VV, MASK_VFWBDOTA_VV): Ditto.
	(MATCH_VFQWBDOTA_VV, MASK_VFQWBDOTA_VV): Ditto.
	(MATCH_VFQWBDOTA_ALT_VV, MASK_VFQWBDOTA_ALT_VV): Ditto.
	(MATCH_VFBDOTA_VV, MASK_VFBDOTA_VV): Ditto.
	(DECLARE_INSN): New declarations.
	* opcode/riscv.h (enum riscv_insn_class): New extension classes.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Add 'q' and 'r' operand types
	for Zvbdota.
	* riscv-opc.c (riscv_opcodes): New instructions.

---
 bfd/elfxx-riscv.c                             | 35 ++++++++++++++++++
 gas/NEWS                                      |  5 ++-
 gas/config/tc-riscv.c                         | 37 ++++++++++++++++++-
 gas/testsuite/gas/riscv/march-help.l          |  5 +++
 .../gas/riscv/zvbdota-operands-fail.d         |  3 ++
 .../gas/riscv/zvbdota-operands-fail.l         |  4 ++
 .../gas/riscv/zvbdota-operands-fail.s         |  4 ++
 .../gas/riscv/zvbdota-zvqwbdota16i.d          | 11 ++++++
 .../gas/riscv/zvbdota-zvqwbdota16i.s          |  3 ++
 gas/testsuite/gas/riscv/zvbdota.d             | 23 ++++++++++++
 gas/testsuite/gas/riscv/zvbdota.s             | 15 ++++++++
 include/opcode/riscv-opc.h                    | 20 ++++++++++
 include/opcode/riscv.h                        |  6 +++
 opcodes/riscv-dis.c                           | 11 ++++++
 opcodes/riscv-opc.c                           |  8 ++++
 15 files changed, 187 insertions(+), 3 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/zvbdota-operands-fail.d
 create mode 100644 gas/testsuite/gas/riscv/zvbdota-operands-fail.l
 create mode 100644 gas/testsuite/gas/riscv/zvbdota-operands-fail.s
 create mode 100644 gas/testsuite/gas/riscv/zvbdota-zvqwbdota16i.d
 create mode 100644 gas/testsuite/gas/riscv/zvbdota-zvqwbdota16i.s
 create mode 100644 gas/testsuite/gas/riscv/zvbdota.d
 create mode 100644 gas/testsuite/gas/riscv/zvbdota.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 7714e5dcd49..afe7073ddb7 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1234,8 +1234,13 @@ static const struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zvfhmin", "+zve32f", check_implicit_always},
   {"zvfbfwma", "+zve32f,+zfbfmin", check_implicit_always},
   {"zvfbfmin", "+zve32f", check_implicit_always},
+  {"zvfbdota32f", "+zve32f", check_implicit_always},
+  {"zvfqwbdota8f", "+zve32f", check_implicit_always},
   {"zvfqwdota8f", "+zve32f", check_implicit_always},
+  {"zvfwbdota16bf", "+zve32f", check_implicit_always},
   {"zvfwdota16bf", "+zve32f", check_implicit_always},
+  {"zvqwbdota8i", "+zve32x", check_implicit_always},
+  {"zvqwbdota16i", "+zve64x", check_implicit_always},
   {"zvqwdota8i", "+zve32x", check_implicit_always},
   {"zvqwdota16i", "+zve64x", check_implicit_always},
   {"zve64d", "+d,+zve64f", check_implicit_always},
@@ -1517,11 +1522,14 @@ static const struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zve64d",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvbb",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvbc",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"zvfbdota32f",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvfbfmin",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvfbfwma",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvfh",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvfhmin",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"zvfqwbdota8f",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvfqwdota8f",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"zvfwbdota16bf",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvfwdota16bf",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvkb",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvkg",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
@@ -1537,6 +1545,8 @@ static const struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvksg",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvksc",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvkt",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"zvqwbdota8i",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"zvqwbdota16i",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvqwdota8i",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvqwdota16i",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
@@ -2978,8 +2988,14 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zvfbfmin");
     case INSN_CLASS_ZVFBFWMA:
       return riscv_subset_supports (rps, "zvfbfwma");
+    case INSN_CLASS_ZVFBDOTA32F:
+      return riscv_subset_supports (rps, "zvfbdota32f");
+    case INSN_CLASS_ZVFQWBDOTA8F:
+      return riscv_subset_supports (rps, "zvfqwbdota8f");
     case INSN_CLASS_ZVFQWDOTA8F:
       return riscv_subset_supports (rps, "zvfqwdota8f");
+    case INSN_CLASS_ZVFWBDOTA16BF:
+      return riscv_subset_supports (rps, "zvfwbdota16bf");
     case INSN_CLASS_ZVFWDOTA16BF:
       return riscv_subset_supports (rps, "zvfwdota16bf");
     case INSN_CLASS_ZVKB:
@@ -2995,6 +3011,13 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zvksed");
     case INSN_CLASS_ZVKSH:
       return riscv_subset_supports (rps, "zvksh");
+    case INSN_CLASS_ZVQWBDOTA8I:
+      return riscv_subset_supports (rps, "zvqwbdota8i");
+    case INSN_CLASS_ZVQWBDOTA16I:
+      return riscv_subset_supports (rps, "zvqwbdota16i");
+    case INSN_CLASS_ZVQWBDOTA8I_OR_ZVQWBDOTA16I:
+      return (riscv_subset_supports (rps, "zvqwbdota8i")
+	      || riscv_subset_supports (rps, "zvqwbdota16i"));
     case INSN_CLASS_ZVQWDOTA8I:
       return riscv_subset_supports (rps, "zvqwdota8i");
     case INSN_CLASS_ZVQWDOTA16I:
@@ -3305,8 +3328,14 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "zvfbfmin";
     case INSN_CLASS_ZVFBFWMA:
       return "zvfbfwma";
+    case INSN_CLASS_ZVFBDOTA32F:
+      return "zvfbdota32f";
+    case INSN_CLASS_ZVFQWBDOTA8F:
+      return "zvfqwbdota8f";
     case INSN_CLASS_ZVFQWDOTA8F:
       return "zvfqwdota8f";
+    case INSN_CLASS_ZVFWBDOTA16BF:
+      return "zvfwbdota16bf";
     case INSN_CLASS_ZVFWDOTA16BF:
       return "zvfwdota16bf";
     case INSN_CLASS_ZVKB:
@@ -3321,6 +3350,12 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zvksed");
     case INSN_CLASS_ZVKSH:
       return _("zvksh");
+    case INSN_CLASS_ZVQWBDOTA8I:
+      return "zvqwbdota8i";
+    case INSN_CLASS_ZVQWBDOTA16I:
+      return "zvqwbdota16i";
+    case INSN_CLASS_ZVQWBDOTA8I_OR_ZVQWBDOTA16I:
+      return _("zvqwbdota8i' or `zvqwbdota16i");
     case INSN_CLASS_ZVQWDOTA8I:
       return "zvqwdota8i";
     case INSN_CLASS_ZVQWDOTA16I:
diff --git a/gas/NEWS b/gas/NEWS
index ddb7983aea0..253f25a4691 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,7 +1,8 @@
 -*- text -*-
 
-* Add support for RISC-V standard extensions:
-  zvqwdota8i, zvqwdota16i, zvfwdota16bf and zvfqwdota8f v1.0.
+* Add support for RISC-V extensions:
+  zvqwdota8i, zvqwdota16i, zvfwdota16bf, zvfqwdota8f, zvqwbdota8i,
+  zvqwbdota16i, zvfwbdota16bf, zvfqwbdota8f and zvfbdota32f v1.0.
 
 Changes in 2.46:
 
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 42397933662..03d9efa770e 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1568,6 +1568,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 	    case 'e': USE_BITS (OP_MASK_VWD, OP_SH_VWD); break;
 	    case 's': USE_BITS (OP_MASK_VS1, OP_SH_VS1); break;
 	    case 't': USE_BITS (OP_MASK_VS2, OP_SH_VS2); break;
+	    case 'q': USE_BITS (0x3, OP_SH_VS2 + 3); break;
+	    case 'r': USE_BITS (0x7, OP_SH_VS2); break;
 	    case 'u': USE_BITS (OP_MASK_VS1, OP_SH_VS1);
 		      USE_BITS (OP_MASK_VS2, OP_SH_VS2); break;
 	    case 'v': USE_BITS (OP_MASK_VD, OP_SH_VD);
@@ -2655,8 +2657,12 @@ riscv_vtype_altfmt_supported (void)
 {
   return (riscv_subset_supports (&riscv_rps_as, "zvfbfa")
 	  || riscv_subset_supports (&riscv_rps_as, "zvfofp8min")
+	  || riscv_subset_supports (&riscv_rps_as, "zvfqwbdota8f")
 	  || riscv_subset_supports (&riscv_rps_as, "zvfqwdota8f")
+	  || riscv_subset_supports (&riscv_rps_as, "zvfwbdota16bf")
 	  || riscv_subset_supports (&riscv_rps_as, "zvfwdota16bf")
+	  || riscv_subset_supports (&riscv_rps_as, "zvqwbdota8i")
+	  || riscv_subset_supports (&riscv_rps_as, "zvqwbdota16i")
 	  || riscv_subset_supports (&riscv_rps_as, "zvqwdota8i")
 	  || riscv_subset_supports (&riscv_rps_as, "zvqwdota16i"));
 }
@@ -2682,7 +2688,7 @@ my_getVsetvliExpression (expressionS *ep, char *str)
 	as_bad (_("multiple vsew constants"));
       if (!riscv_vtype_altfmt_supported ())
 	as_bad (_("symbolic vtype altfmt requires `zvfbfa', "
-		  "`zvfofp8min' or a `zvdota' extension"));
+		  "`zvfofp8min' or an altfmt dot-product extension"));
       altfmt_value = 1 << OP_SH_VTYPE_ALTFMT;
       vsew_found = true;
     }
@@ -3338,6 +3344,35 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		  INSERT_OPERAND (VS2, *ip, regno);
 		  continue;
 
+		case 'q': /* Zvbdota VS2 group base.  */
+		  if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
+		    break;
+		  if (regno & 0x7)
+		    as_bad (_("vector register must be aligned to an "
+			      "EMUL=8 group"));
+		  INSERT_BITS (ip->insn_opcode, regno & 0x18, 0x18,
+			       OP_SH_VS2);
+		  continue;
+
+		case 'r': /* Zvbdota ci immediate in VS2.  */
+		  {
+		    offsetT ci;
+
+		    my_getExpression (imm_expr, asarg, force_reloc);
+		    check_absolute_expr (ip, imm_expr, false);
+		    ci = imm_expr->X_add_number;
+		    if (ci < 0 || ci > 56 || (ci & 0x7))
+		      {
+			as_bad (_("bad value for Zvbdota ci immediate field, "
+				  "value must be a multiple of 8 in 0..56"));
+			ci = 0;
+		      }
+		    INSERT_BITS (ip->insn_opcode, ci / 8, 0x7, OP_SH_VS2);
+		    imm_expr->X_op = O_absent;
+		    asarg = expr_parse_end;
+		    continue;
+		  }
+
 		case 'u': /* VS1 == VS2 */
 		  if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
 		    break;
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 51e830c021b..0550d0d605a 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -70,11 +70,14 @@ All available -march extensions for RISC-V:
 	zve64d                                  1.0
 	zvbb                                    1.0
 	zvbc                                    1.0
+	zvfbdota32f                             1.0
 	zvfbfmin                                1.0
 	zvfbfwma                                1.0
 	zvfh                                    1.0
 	zvfhmin                                 1.0
+	zvfqwbdota8f                            1.0
 	zvfqwdota8f                             1.0
+	zvfwbdota16bf                           1.0
 	zvfwdota16bf                            1.0
 	zvkb                                    1.0
 	zvkg                                    1.0
@@ -90,6 +93,8 @@ All available -march extensions for RISC-V:
 	zvksg                                   1.0
 	zvksc                                   1.0
 	zvkt                                    1.0
+	zvqwbdota8i                             1.0
+	zvqwbdota16i                            1.0
 	zvqwdota8i                              1.0
 	zvqwdota16i                             1.0
 	zvl32b                                  1.0
diff --git a/gas/testsuite/gas/riscv/zvbdota-operands-fail.d b/gas/testsuite/gas/riscv/zvbdota-operands-fail.d
new file mode 100644
index 00000000000..32028f6bb8c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbdota-operands-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv64gc_zvqwbdota8i
+#source: zvbdota-operands-fail.s
+#error_output: zvbdota-operands-fail.l
diff --git a/gas/testsuite/gas/riscv/zvbdota-operands-fail.l b/gas/testsuite/gas/riscv/zvbdota-operands-fail.l
new file mode 100644
index 00000000000..6ba8dfca2e8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbdota-operands-fail.l
@@ -0,0 +1,4 @@
+.*: Assembler messages:
+.*: Error: vector register must be aligned to an EMUL=8 group
+.*: Error: bad value for Zvbdota ci immediate field, value must be a multiple of 8 in 0..56
+.*: Error: bad value for Zvbdota ci immediate field, value must be a multiple of 8 in 0..56
diff --git a/gas/testsuite/gas/riscv/zvbdota-operands-fail.s b/gas/testsuite/gas/riscv/zvbdota-operands-fail.s
new file mode 100644
index 00000000000..0709892db8d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbdota-operands-fail.s
@@ -0,0 +1,4 @@
+target:
+	vqwbdotas.vv v16, v9, v31, 0
+	vqwbdotas.vv v16, v8, v31, 4
+	vqwbdotas.vv v16, v8, v31, 64
diff --git a/gas/testsuite/gas/riscv/zvbdota-zvqwbdota16i.d b/gas/testsuite/gas/riscv/zvbdota-zvqwbdota16i.d
new file mode 100644
index 00000000000..349cd81f759
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbdota-zvqwbdota16i.d
@@ -0,0 +1,11 @@
+#as: -march=rv64gc_zvqwbdota16i
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+ba8f8877[ 	]+vqwbdotau.vv[ 	]+v16,v8,v31,0
+[ 	]+[0-9a-f]+:[ 	]+be9f8877[ 	]+vqwbdotas.vv[ 	]+v16,v8,v31,8
diff --git a/gas/testsuite/gas/riscv/zvbdota-zvqwbdota16i.s b/gas/testsuite/gas/riscv/zvbdota-zvqwbdota16i.s
new file mode 100644
index 00000000000..1a5bb4ef4bc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbdota-zvqwbdota16i.s
@@ -0,0 +1,3 @@
+target:
+	vqwbdotau.vv v16, v8, v31, 0
+	vqwbdotas.vv v16, v8, v31, 8
diff --git a/gas/testsuite/gas/riscv/zvbdota.d b/gas/testsuite/gas/riscv/zvbdota.d
new file mode 100644
index 00000000000..63fa13853fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbdota.d
@@ -0,0 +1,23 @@
+#as: -march=rv64gc_zvqwbdota8i_zvqwbdota16i_zvfwbdota16bf_zvfqwbdota8f_zvfbdota32f
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+ba8f8877[ 	]+vqwbdotau.vv[ 	]+v16,v8,v31,0
+[ 	]+[0-9a-f]+:[ 	]+ba9f8877[ 	]+vqwbdotau.vv[ 	]+v16,v8,v31,8
+[ 	]+[0-9a-f]+:[ 	]+be8f8877[ 	]+vqwbdotas.vv[ 	]+v16,v8,v31,0
+[ 	]+[0-9a-f]+:[ 	]+be9f8877[ 	]+vqwbdotas.vv[ 	]+v16,v8,v31,8
+[ 	]+[0-9a-f]+:[ 	]+b28f9877[ 	]+vfwbdota.vv[ 	]+v16,v8,v31,0
+[ 	]+[0-9a-f]+:[ 	]+b29f9877[ 	]+vfwbdota.vv[ 	]+v16,v8,v31,8
+[ 	]+[0-9a-f]+:[ 	]+ba8f9877[ 	]+vfqwbdota.vv[ 	]+v16,v8,v31,0
+[ 	]+[0-9a-f]+:[ 	]+ba9f9877[ 	]+vfqwbdota.vv[ 	]+v16,v8,v31,8
+[ 	]+[0-9a-f]+:[ 	]+be8f9877[ 	]+vfqwbdota.alt.vv[ 	]+v16,v8,v31,0
+[ 	]+[0-9a-f]+:[ 	]+be9f9877[ 	]+vfqwbdota.alt.vv[ 	]+v16,v8,v31,8
+[ 	]+[0-9a-f]+:[ 	]+ae8f9877[ 	]+vfbdota.vv[ 	]+v16,v8,v31,0
+[ 	]+[0-9a-f]+:[ 	]+ae9f9877[ 	]+vfbdota.vv[ 	]+v16,v8,v31,8
+[ 	]+[0-9a-f]+:[ 	]+bc8f8877[ 	]+vqwbdotas.vv[ 	]+v16,v8,v31,0,v0.t
+[ 	]+[0-9a-f]+:[ 	]+b89f9877[ 	]+vfqwbdota.vv[ 	]+v16,v8,v31,8,v0.t
diff --git a/gas/testsuite/gas/riscv/zvbdota.s b/gas/testsuite/gas/riscv/zvbdota.s
new file mode 100644
index 00000000000..c87975a4cc9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbdota.s
@@ -0,0 +1,15 @@
+target:
+	vqwbdotau.vv v16, v8, v31, 0
+	vqwbdotau.vv v16, v8, v31, 8
+	vqwbdotas.vv v16, v8, v31, 0
+	vqwbdotas.vv v16, v8, v31, 8
+	vfwbdota.vv v16, v8, v31, 0
+	vfwbdota.vv v16, v8, v31, 8
+	vfqwbdota.vv v16, v8, v31, 0
+	vfqwbdota.vv v16, v8, v31, 8
+	vfqwbdota.alt.vv v16, v8, v31, 0
+	vfqwbdota.alt.vv v16, v8, v31, 8
+	vfbdota.vv v16, v8, v31, 0
+	vfbdota.vv v16, v8, v31, 8
+	vqwbdotas.vv v16, v8, v31, 0, v0.t
+	vfqwbdota.vv v16, v8, v31, 8, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 359b4f64ab8..b59c85584c9 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2560,6 +2560,19 @@
 #define MASK_VFQWDOTA_VV 0xfc00707f
 #define MATCH_VFQWDOTA_ALT_VV 0x9c001077
 #define MASK_VFQWDOTA_ALT_VV 0xfc00707f
+/* Zvbdota instructions.  */
+#define MATCH_VQWBDOTAU_VV 0xb8000077
+#define MASK_VQWBDOTAU_VV 0xfc00707f
+#define MATCH_VQWBDOTAS_VV 0xbc000077
+#define MASK_VQWBDOTAS_VV 0xfc00707f
+#define MATCH_VFWBDOTA_VV 0xb0001077
+#define MASK_VFWBDOTA_VV 0xfc00707f
+#define MATCH_VFQWBDOTA_VV 0xb8001077
+#define MASK_VFQWBDOTA_VV 0xfc00707f
+#define MATCH_VFQWBDOTA_ALT_VV 0xbc001077
+#define MASK_VFQWBDOTA_ALT_VV 0xfc00707f
+#define MATCH_VFBDOTA_VV 0xac001077
+#define MASK_VFBDOTA_VV 0xfc00707f
 /* Vendor-specific (CORE-V) Xcvmac instructions.  */
 #define MATCH_CV_MAC       0x9000302b
 #define MASK_CV_MAC        0xfe00707f
@@ -4812,6 +4825,13 @@ DECLARE_INSN(vqwdotas_vv, MATCH_VQWDOTAS_VV, MASK_VQWDOTAS_VV)
 DECLARE_INSN(vfwdota_vv, MATCH_VFWDOTA_VV, MASK_VFWDOTA_VV)
 DECLARE_INSN(vfqwdota_vv, MATCH_VFQWDOTA_VV, MASK_VFQWDOTA_VV)
 DECLARE_INSN(vfqwdota_alt_vv, MATCH_VFQWDOTA_ALT_VV, MASK_VFQWDOTA_ALT_VV)
+/* Zvbdota instructions.  */
+DECLARE_INSN(vqwbdotau_vv, MATCH_VQWBDOTAU_VV, MASK_VQWBDOTAU_VV)
+DECLARE_INSN(vqwbdotas_vv, MATCH_VQWBDOTAS_VV, MASK_VQWBDOTAS_VV)
+DECLARE_INSN(vfwbdota_vv, MATCH_VFWBDOTA_VV, MASK_VFWBDOTA_VV)
+DECLARE_INSN(vfqwbdota_vv, MATCH_VFQWBDOTA_VV, MASK_VFQWBDOTA_VV)
+DECLARE_INSN(vfqwbdota_alt_vv, MATCH_VFQWBDOTA_ALT_VV, MASK_VFQWBDOTA_ALT_VV)
+DECLARE_INSN(vfbdota_vv, MATCH_VFBDOTA_VV, MASK_VFBDOTA_VV)
 /* Zvbb/Zvkb instructions.  */
 DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV)
 DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 59bc09e4780..82f8fd40881 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -548,7 +548,10 @@ enum riscv_insn_class
   INSN_CLASS_ZVBC,
   INSN_CLASS_ZVFBFMIN,
   INSN_CLASS_ZVFBFWMA,
+  INSN_CLASS_ZVFBDOTA32F,
+  INSN_CLASS_ZVFQWBDOTA8F,
   INSN_CLASS_ZVFQWDOTA8F,
+  INSN_CLASS_ZVFWBDOTA16BF,
   INSN_CLASS_ZVFWDOTA16BF,
   INSN_CLASS_ZVKB,
   INSN_CLASS_ZVKG,
@@ -556,6 +559,9 @@ enum riscv_insn_class
   INSN_CLASS_ZVKNHA_OR_ZVKNHB,
   INSN_CLASS_ZVKSED,
   INSN_CLASS_ZVKSH,
+  INSN_CLASS_ZVQWBDOTA8I,
+  INSN_CLASS_ZVQWBDOTA16I,
+  INSN_CLASS_ZVQWBDOTA8I_OR_ZVQWBDOTA16I,
   INSN_CLASS_ZVQWDOTA8I,
   INSN_CLASS_ZVQWDOTA16I,
   INSN_CLASS_ZVQWDOTA8I_OR_ZVQWDOTA16I,
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 6ccccd864f2..c3da5f2960e 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -440,6 +440,17 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	      print (info->stream, dis_style_register, "%s",
 		     riscv_vecr_names_numeric[EXTRACT_OPERAND (VS2, l)]);
 	      break;
+	    case 'q':
+	      {
+		unsigned int vs2 = EXTRACT_OPERAND (VS2, l);
+		print (info->stream, dis_style_register, "%s",
+		       riscv_vecr_names_numeric[vs2 & 0x18]);
+	      }
+	      break;
+	    case 'r':
+	      print (info->stream, dis_style_immediate, "%u",
+		     (unsigned int) (EXTRACT_OPERAND (VS2, l) & 0x7) * 8);
+	      break;
 	    case '0':
 	      print (info->stream, dis_style_register, "%s",
 		     riscv_vecr_names_numeric[0]);
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 3c4e4b19af5..472abb8b744 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2233,6 +2233,14 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vfqwdota.vv", 0, INSN_CLASS_ZVFQWDOTA8F, "Vd,Vt,VsVm", MATCH_VFQWDOTA_VV, MASK_VFQWDOTA_VV, match_opcode, 0},
 {"vfqwdota.alt.vv", 0, INSN_CLASS_ZVFQWDOTA8F, "Vd,Vt,VsVm", MATCH_VFQWDOTA_ALT_VV, MASK_VFQWDOTA_ALT_VV, match_opcode, 0},
 
+/* Zvbdota instructions.  */
+{"vqwbdotau.vv", 0, INSN_CLASS_ZVQWBDOTA8I_OR_ZVQWBDOTA16I, "Vd,Vq,Vs,VrVm", MATCH_VQWBDOTAU_VV, MASK_VQWBDOTAU_VV, match_opcode, 0},
+{"vqwbdotas.vv", 0, INSN_CLASS_ZVQWBDOTA8I_OR_ZVQWBDOTA16I, "Vd,Vq,Vs,VrVm", MATCH_VQWBDOTAS_VV, MASK_VQWBDOTAS_VV, match_opcode, 0},
+{"vfwbdota.vv",  0, INSN_CLASS_ZVFWBDOTA16BF, "Vd,Vq,Vs,VrVm", MATCH_VFWBDOTA_VV, MASK_VFWBDOTA_VV, match_opcode, 0},
+{"vfqwbdota.vv", 0, INSN_CLASS_ZVFQWBDOTA8F, "Vd,Vq,Vs,VrVm", MATCH_VFQWBDOTA_VV, MASK_VFQWBDOTA_VV, match_opcode, 0},
+{"vfqwbdota.alt.vv", 0, INSN_CLASS_ZVFQWBDOTA8F, "Vd,Vq,Vs,VrVm", MATCH_VFQWBDOTA_ALT_VV, MASK_VFQWBDOTA_ALT_VV, match_opcode, 0},
+{"vfbdota.vv",   0, INSN_CLASS_ZVFBDOTA32F, "Vd,Vq,Vs,VrVm", MATCH_VFBDOTA_VV, MASK_VFBDOTA_VV, match_opcode, 0},
+
 /* Zvbb/Zvkb instructions.  */
 {"vandn.vv",   0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VANDN_VV, MASK_VANDN_VV, match_opcode, 0},
 {"vandn.vx",   0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VANDN_VX, MASK_VANDN_VX, match_opcode, 0},
-- 
2.43.0


From hjl.tools@gmail.com  Wed Jun 10 00:28:42 2026
From: hjl.tools@gmail.com (H.J. Lu)
Date: Wed, 10 Jun 2026 08:28:42 +0800
Subject: Planned binutils-2.46.1 release
In-Reply-To: <87h5nbg3i9.fsf@gentoo.org>
References: <87o6ilgdrj.fsf@gentoo.org> <87se7wfp9f.fsf@gentoo.org>
 <agQ8EH3YIJ6C2dUs@squeak.grove.modra.org> <877bo8h5n5.fsf@gentoo.org>
 <988b682a-94f9-47b9-8624-d34621d85635@symas.com> <87h5nbg3i9.fsf@gentoo.org>
Message-ID: <CAMe9rOqOwVNKb83banyPMuJytX3rWxLChWeNVBCEZXLq9pRmGw@mail.gmail.com>

Can we backport the fix for

https://sourceware.org/bugzilla/show_bug.cgi?id=34171

H.J.

On Tue, Jun 9, 2026, 11:04?PM Sam James <sam@gentoo.org> wrote:

> Howard Chu <hyc@symas.com> writes:
>
> > -----BEGIN PGP SIGNED MESSAGE-----
> > Hash: SHA512
> >
> > Sam James wrote:
> >>> On Tue, May 12, 2026 at 07:37:16PM +0100, Sam James wrote:
> >>>> Sam James <sam@gentoo.org> writes:
> >>>>
> >>>>> Hi all,
> >>>>>
> >>>>> I plan to make a point release for binutils-2.46 in a few days,
> motivated by the C23/glibc-2.43 fixes for const correctness, as the 2.46
> release
> >>>>> fails to build w/ -Werror enabled by default [0].
> >>>>>
> >>>>> Please look to see if any other fixes should be backported to
> binutils-2_46-branch.
> >
> > Would be nice to see the fix for this rolled in.
>
> It's not yet on master but I cc'd Alan on the bug and commented. Thanks.
>
> >
> > https://sourceware.org/bugzilla/show_bug.cgi?id=34204
> >
> > - --
> >   -- Howard Chu
> >   CTO, Symas Corp.           http://www.symas.com
> >   Director, Highland Sun     http://highlandsun.com/hyc/
> >   Chief Architect, OpenLDAP  http://www.openldap.org/project/
> > -----BEGIN PGP SIGNATURE-----
> >
> > iF0EAREKAB0WIQSUBGGam6fLX3meDqH9KnC0SrEbpwUCaigZAQAKCRD9KnC0SrEb
> > p3iLAJ9L3xA9KaaHAh2sYZ/bI2zngbHcngCfbhtAt1BXJm5dT2JA9kD/dEjv1ig=
> > =FUiK
> > -----END PGP SIGNATURE-----
>
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From sam@gentoo.org  Wed Jun 10 03:38:23 2026
From: sam@gentoo.org (Sam James)
Date: Wed, 10 Jun 2026 04:38:23 +0100
Subject: Planned binutils-2.46.1 release
In-Reply-To: <CAMe9rOqOwVNKb83banyPMuJytX3rWxLChWeNVBCEZXLq9pRmGw@mail.gmail.com>
References: <87o6ilgdrj.fsf@gentoo.org> <87se7wfp9f.fsf@gentoo.org>
 <agQ8EH3YIJ6C2dUs@squeak.grove.modra.org> <877bo8h5n5.fsf@gentoo.org>
 <988b682a-94f9-47b9-8624-d34621d85635@symas.com>
 <87h5nbg3i9.fsf@gentoo.org>
 <CAMe9rOqOwVNKb83banyPMuJytX3rWxLChWeNVBCEZXLq9pRmGw@mail.gmail.com>
Message-ID: <87qzmfdpzk.fsf@gentoo.org>

"H.J. Lu" <hjl.tools@gmail.com> writes:

> Can we backport the fix for
>
> https://sourceware.org/bugzilla/show_bug.cgi?id=34171

Yes, please do put it on the branch.

I already made 2.46.1 (as I was a bit slow already and told Nick I'd do
it a around mid-May), but if there is a need for 2.46.2, it could be
included then.

>
> H.J.
>
> On Tue, Jun 9, 2026, 11:04?PM Sam James <sam@gentoo.org> wrote:
>
>  Howard Chu <hyc@symas.com> writes:
>
>  > -----BEGIN PGP SIGNED MESSAGE-----
>  > Hash: SHA512
>  >
>  > Sam James wrote:
>  >>> On Tue, May 12, 2026 at 07:37:16PM +0100, Sam James wrote:
>  >>>> Sam James <sam@gentoo.org> writes:
>  >>>> 
>  >>>>> Hi all,
>  >>>>> 
>  >>>>> I plan to make a point release for binutils-2.46 in a few days, motivated by the C23/glibc-2.43 fixes for const
>  correctness, as the 2.46 release
>  >>>>> fails to build w/ -Werror enabled by default [0].
>  >>>>> 
>  >>>>> Please look to see if any other fixes should be backported to binutils-2_46-branch.
>  >
>  > Would be nice to see the fix for this rolled in.
>
>  It's not yet on master but I cc'd Alan on the bug and commented. Thanks.
>
>  >
>  > https://sourceware.org/bugzilla/show_bug.cgi?id=34204
>  >
>  > - -- 
>  >   -- Howard Chu
>  >   CTO, Symas Corp.           http://www.symas.com
>  >   Director, Highland Sun     http://highlandsun.com/hyc/
>  >   Chief Architect, OpenLDAP  http://www.openldap.org/project/
>  > -----BEGIN PGP SIGNATURE-----
>  >
>  > iF0EAREKAB0WIQSUBGGam6fLX3meDqH9KnC0SrEbpwUCaigZAQAKCRD9KnC0SrEb
>  > p3iLAJ9L3xA9KaaHAh2sYZ/bI2zngbHcngCfbhtAt1BXJm5dT2JA9kD/dEjv1ig=
>  > =FUiK
>  > -----END PGP SIGNATURE-----
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From amodra@gmail.com  Wed Jun 10 06:25:50 2026
From: amodra@gmail.com (Alan Modra)
Date: Wed, 10 Jun 2026 15:55:50 +0930
Subject: PR 34204 dlltool SEGVs with --exclude-symbols
Message-ID: <aikDbvvehVGe3-BW@squeak.grove.modra.org>

This fixes a segfault introduced by commit 45a7f5a29de7 which didn't
take into account that there was a use of leading_underscore in option
processing.

	PR 34204
	* dlltool.c (struct string_list): Make string a flexible array
	member.
	(add_excludes): Adjust to suit.  Extract code adding underscore
	and informing..
	(underscore_excludes): ..to here.  New function.
	(main): Call underscore_excludes.

diff --git a/binutils/dlltool.c b/binutils/dlltool.c
index f4ee894de1b..67839632a43 100644
--- a/binutils/dlltool.c
+++ b/binutils/dlltool.c
@@ -789,7 +789,7 @@ export_type;
 struct string_list
 {
   struct string_list *next;
-  char *string;
+  char string[];
 };
 
 static struct string_list *excludes;
@@ -1460,23 +1460,37 @@ add_excludes (const char *new_excludes)
   exclude_string = strtok (local_copy, ",:");
   for (; exclude_string; exclude_string = strtok (NULL, ",:"))
     {
-      struct string_list *new_exclude = xmalloc (sizeof (*new_exclude));
-      /* Don't add a leading underscore for fastcall symbols.  */
-      if (*exclude_string == '@')
-	new_exclude->string = xstrdup (exclude_string);
-      else
-	new_exclude->string = xasprintf ("%s%s", leading_underscore,
-					 exclude_string);
+      size_t len = strlen (exclude_string);
+      /* Allocate extra byte for possible underscore.  */
+      struct string_list *new_exclude = xmalloc (sizeof (*new_exclude)
+						 + len + 2);
+      memcpy (new_exclude->string, exclude_string, len + 1);
       new_exclude->next = excludes;
       excludes = new_exclude;
-
-      /* xgettext:c-format */
-      inform (_("Excluding symbol: %s"), exclude_string);
     }
 
   free (local_copy);
 }
 
+/* Prefix symbols on the excludes list with an underscore.  */
+
+static void
+underscore_excludes (void)
+{
+  for (struct string_list *ex = excludes; ex; ex = ex->next)
+    {
+      /* Don't add a leading underscore for fastcall symbols.  */
+      if (*ex->string != '@' && *leading_underscore)
+	{
+	  size_t len = strlen (ex->string);
+	  memmove (ex->string + 1, ex->string, len + 1);
+	  *ex->string = *leading_underscore;
+	}
+      /* xgettext:c-format */
+      inform (_("Excluding symbol: %s"), ex->string);
+    }
+}
+
 /* See if STRING is on the list of symbols to exclude.  */
 
 static bool
@@ -4065,6 +4079,8 @@ main (int ac, char **av)
   if (do_default_excludes)
     set_default_excludes ();
 
+  underscore_excludes ();
+
   if (def_file)
     process_def_file (def_file);
 

-- 
Alan Modra

From jbeulich@suse.com  Wed Jun 10 09:27:13 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Wed, 10 Jun 2026 11:27:13 +0200
Subject: Using .macro argument in .error message?
In-Reply-To: <7bfb02e7-d3cd-4c89-a5b7-bdb7e598d7a2@gjlay.de>
References: <7bfb02e7-d3cd-4c89-a5b7-bdb7e598d7a2@gjlay.de>
Message-ID: <9be37f12-b10f-4f22-8b06-3fb302252e36@suse.com>

On 07.06.2026 21:16, Georg-Johann Lay via Binutils wrote:
> Test case err.sx:
> 
> .macro Test data
>      .if \data < 0
>          .error "value \data is negative"
>      .endif
> .endm
> 
>      Test -1
> 
> 
> $ avr-as err.sx -v
> GNU assembler version 2.45.50 (avr) using BFD version (GNU Binutils) 
> 2.45.50.20250718
> err.sx: Assembler messages:
> err.sx: Warning: unknown escape '\d' in string; ignored
> err.sx:3: Error: value -1 is negative
> err.sx:7:  Info: macro invoked from here
> 
> While the printed error message is as expected, there is a spurious
> warning about using \d in the string.
> 
> What am I missing?
> 
> As far as I understand, the .error message /must/ be "-quoted.

Indeed. But AVR is one of the few targets which enable this extra
warning. Why that is or whether it could be changed requires AVR
knowledge, which I don#t have. There's also a surprising set of
characters for which the warning would never appear. I don't know
the history of that set, but it feels pretty arbitrary.

Jan

From avr@gjlay.de  Wed Jun 10 09:54:31 2026
From: avr@gjlay.de (Georg-Johann Lay)
Date: Wed, 10 Jun 2026 11:54:31 +0200
Subject: Using .macro argument in .error message?
In-Reply-To: <9be37f12-b10f-4f22-8b06-3fb302252e36@suse.com>
References: <7bfb02e7-d3cd-4c89-a5b7-bdb7e598d7a2@gjlay.de>
 <9be37f12-b10f-4f22-8b06-3fb302252e36@suse.com>
Message-ID: <f319074e-a8ed-4e0d-8326-4dab9ce178d0@gjlay.de>

Am 10.06.26 um 11:27 schrieb Jan Beulich:
> On 07.06.2026 21:16, Georg-Johann Lay via Binutils wrote:
>> Test case err.sx:
>>
>> .macro Test data
>>       .if \data < 0
>>           .error "value \data is negative"
>>       .endif
>> .endm
>>
>>       Test -1
>>
>>
>> $ avr-as err.sx -v
>> GNU assembler version 2.45.50 (avr) using BFD version (GNU Binutils)
>> 2.45.50.20250718
>> err.sx: Assembler messages:
>> err.sx: Warning: unknown escape '\d' in string; ignored
>> err.sx:3: Error: value -1 is negative
>> err.sx:7:  Info: macro invoked from here
>>
>> While the printed error message is as expected, there is a spurious
>> warning about using \d in the string.
>>
>> What am I missing?
>>
>> As far as I understand, the .error message /must/ be "-quoted.
> 
> Indeed. But AVR is one of the few targets which enable this extra
> warning. Why that is or whether it could be changed requires AVR
> knowledge, which I don#t have. There's also a surprising set of
> characters for which the warning would never appear. I don't know
> the history of that set, but it feels pretty arbitrary.
> 
> Jan

Okay, I didn't even notice that it's target specific... The only
related place I could find is in gas/config/tc-avr.h:

/* If you define this macro, GAS will warn about the use of
    nonstandard escape sequences in a string.  */
#define ONLY_STANDARD_ESCAPES

Though whatever the behavior wrt. fishy escapes is, resolution
of macro arguments shoud run prior to that, no?

At least if macro param resolution in strings is supported
to begin with; which appears to be the case.

Johann


From nickc@redhat.com  Wed Jun 10 14:02:24 2026
From: nickc@redhat.com (Nick Clifton)
Date: Wed, 10 Jun 2026 15:02:24 +0100
Subject: RFC: Extending the Glibc CNA to handle GNU Binutils CVEs
Message-ID: <87v7bq7atr.fsf@redhat.com>

Hi Guys,

Over the last decade or so almost all of the Binutils bugs which have
achieved Common Vulnerability and Exposures [1] status have been
bogus.  In the sense they whilst they are bugs, they are not ones that
could be exploited by an attacker to compromise a system or a network.
This is a problem - for me and for other people who maintain the
binutils package in distributions - because any CVE that gets filed
has to be carefully examined and potentially will cause a lot of work
back-porting the fix to all the supported releases.

Recent updates to the SECURITY.txt document should help to reduce the
number of CVEs that actually have to be fixed by distribution
maintainers but it would be better if the CVEs were never created in
the first place.

To this end therefore we are looking into extending the scope of the
current glibc CVE Numbering Authority [2] so that it will also handle
Binutils bugs.  This should be a relatively process and it would mean
that the glibc CNA security team can review submitted binutils bug
reports and actually decide if they really do meet the criteria for
being assigned a CVE rating.  It will also help that the glibc folks
are familiar with the binutils and what the tools do.

My question to you guys then is:

  * Are there any concerns or objections to this idea ?

Cheers
  Nick

PS. Extending the scope of the CNA will also mean that there is the
possibility for interested contributors to become members of the CNA
security review team.  (It looks really good on a C.V.)

PPS. In the future, if this change is successful, it may also be
possible to extend the CNA to cover GCC and GDB.  In that way we could
have the whole toolchain covered by knowledgeable reviewers who can
make sure that when a CVE is assigned, it really does represent a
threat that needs to fixed as quickly and as widely as possible.


[1] - https://www.cve.org/
[2] - https://www.cve.org/PartnerInformation/ListofPartners/partner/glibc


From alice.carlotti@arm.com  Wed Jun 10 14:17:31 2026
From: alice.carlotti@arm.com (Alice Carlotti)
Date: Wed, 10 Jun 2026 15:17:31 +0100
Subject: [PATCH 0/5] aarch64: Remove aarch64_field_kind indirection
In-Reply-To: <e627eee9-d8b8-48f0-9aac-4ee1fe6f68c4@arm.com>
References: <b07af6ec-a74a-8c90-a2c7-38c03664b882@e124511.cambridge.arm.com>
 <e627eee9-d8b8-48f0-9aac-4ee1fe6f68c4@arm.com>
Message-ID: <e771542d-b6e0-ec19-e3f2-5be3ea1671db@e124511.cambridge.arm.com>

On Fri, May 29, 2026 at 04:00:14PM +0100, Richard Earnshaw (foss) wrote:
> On 20/05/2026 13:08, Alice Carlotti wrote:
> > This patch series remove the aarch64_field_kind enum, and replaces uses of the
> > enum with direct use of aarch64_field structs instead.  I think this improves
> > readability overall, and might also be a marginal performance improvement.
> > 
> > Passing aarch64_field as function arguments causes GCC to emit this note:
> > 
> >   note: parameter passing for argument of type ?aarch64_field?
> > {aka ?struct aarch64_field?} changed in GCC 9.1
> 
> That depends on which files generate this warning.  Does this function form part of an API that would be exported if/when libopcodes is made into an installed library?

The affected functions are gen_sub_field, insert_field, insert_fields and
extract_field.  They are static inline functions that are only used internally.
The warning is actually inaccurate, and is only emitted in GCC 9 and GCC 10.
It was subsequently tightened in r11-8226-g49813aad3292f7.

> 
> If not, then we probably don't care.  We also don't care if it only occurs when this is used as part of the code used to build the auto-generated code.
> 
> I think there's an option to gcc to suppress the warning (-Wabi?).  Perhaps one way to suppress the warning would be with a pragma; that would be preferable to disabling it on the command line, since that might lead to other cases that do matter not being reported.

I'd be inclined to just leave this as is, given that it only affects old GCC
versions, but if we wanted to mask the warning we could add something like:

+ #if GCC_VERSION >= 9000
+ #pragma GCC diagnostic push
+ #pragma GCC diagnostic ignored "-Wpsabi"
+ #endif
...
+ #if GCC_VERSION >= 9000
+ #pragma GCC diagnostic pop
+ #endif


Alice

> 
> 
> > 
> > Is this a problem?  Should I find some way to avoid this note being emitted?
> > 
> > 
> > As an interim measure, I've retained some of the aarch64_field_kind enum names
> > as macros that expand to corresponding the aarch64_field value.  I've
> > deliberately chosen not to inline all of these remaining uses immediately, as
> > in many cases I intend to either add comments or rework the surrounding code
> > first.  After this patch series, there would be 76 macros remaining (not
> > counting the FLD_CONST_* macros), out of 216 original enum values.
> > 
> > 
> > Does this approach look ok?
> > 
> > Thanks,
> > Alice
> 
> R.

From collin.funk1@gmail.com  Wed Jun 10 14:34:36 2026
From: collin.funk1@gmail.com (Collin Funk)
Date: Wed, 10 Jun 2026 07:34:36 -0700
Subject: RFC: Extending the Glibc CNA to handle GNU Binutils CVEs
In-Reply-To: <87v7bq7atr.fsf@redhat.com> (Nick Clifton's message of "Wed, 10
 Jun 2026 15:02:24 +0100")
References: <87v7bq7atr.fsf@redhat.com>
Message-ID: <m11peewjk3.fsf@gmail.com>

Nick Clifton <nickc@redhat.com> writes:

> Hi Guys,
>
> Over the last decade or so almost all of the Binutils bugs which have
> achieved Common Vulnerability and Exposures [1] status have been
> bogus.  In the sense they whilst they are bugs, they are not ones that
> could be exploited by an attacker to compromise a system or a network.
> This is a problem - for me and for other people who maintain the
> binutils package in distributions - because any CVE that gets filed
> has to be carefully examined and potentially will cause a lot of work
> back-porting the fix to all the supported releases.
>
> Recent updates to the SECURITY.txt document should help to reduce the
> number of CVEs that actually have to be fixed by distribution
> maintainers but it would be better if the CVEs were never created in
> the first place.
>
> To this end therefore we are looking into extending the scope of the
> current glibc CVE Numbering Authority [2] so that it will also handle
> Binutils bugs.  This should be a relatively process and it would mean
> that the glibc CNA security team can review submitted binutils bug
> reports and actually decide if they really do meet the criteria for
> being assigned a CVE rating.  It will also help that the glibc folks
> are familiar with the binutils and what the tools do.
>
> My question to you guys then is:
>
>   * Are there any concerns or objections to this idea ?

That sounds like a good idea to me.

I briefly considered suggesting GNU become a CNA after noticing some
bogus CVEs filed in Bison and some mostly inactive GNU projects. I never
ended up doing it since those calmed down, but they were annoying
nonetheless.

Collin

From jemarch@gnu.org  Wed Jun 10 15:00:28 2026
From: jemarch@gnu.org (Jose E. Marchesi)
Date: Wed, 10 Jun 2026 17:00:28 +0200
Subject: RFC: Extending the Glibc CNA to handle GNU Binutils CVEs
In-Reply-To: <87v7bq7atr.fsf@redhat.com>
References: <87v7bq7atr.fsf@redhat.com>
Message-ID: <87jys61lv7.fsf@gnu.org>


> Hi Guys,
>
> Over the last decade or so almost all of the Binutils bugs which have
> achieved Common Vulnerability and Exposures [1] status have been
> bogus.  In the sense they whilst they are bugs, they are not ones that
> could be exploited by an attacker to compromise a system or a network.
> This is a problem - for me and for other people who maintain the
> binutils package in distributions - because any CVE that gets filed
> has to be carefully examined and potentially will cause a lot of work
> back-porting the fix to all the supported releases.
>
> Recent updates to the SECURITY.txt document should help to reduce the
> number of CVEs that actually have to be fixed by distribution
> maintainers but it would be better if the CVEs were never created in
> the first place.
>
> To this end therefore we are looking into extending the scope of the
> current glibc CVE Numbering Authority [2] so that it will also handle
> Binutils bugs.  This should be a relatively process and it would mean
> that the glibc CNA security team can review submitted binutils bug
> reports and actually decide if they really do meet the criteria for
> being assigned a CVE rating.  It will also help that the glibc folks
> are familiar with the binutils and what the tools do.
>
> My question to you guys then is:
>
>   * Are there any concerns or objections to this idea ?

I think this would be great.. provided the glibc CNA chaps are willing
to do it, of course 8-)

> Cheers
>   Nick
>
> PS. Extending the scope of the CNA will also mean that there is the
> possibility for interested contributors to become members of the CNA
> security review team.  (It looks really good on a C.V.)
>
> PPS. In the future, if this change is successful, it may also be
> possible to extend the CNA to cover GCC and GDB.  In that way we could
> have the whole toolchain covered by knowledgeable reviewers who can
> make sure that when a CVE is assigned, it really does represent a
> threat that needs to fixed as quickly and as widely as possible.

Yeah!

>
>
> [1] - https://www.cve.org/
> [2] - https://www.cve.org/PartnerInformation/ListofPartners/partner/glibc

From Richard.Earnshaw@arm.com  Wed Jun 10 17:28:25 2026
From: Richard.Earnshaw@arm.com (Richard Earnshaw (foss))
Date: Wed, 10 Jun 2026 18:28:25 +0100
Subject: [PATCH] AArch64 gas: Block section relative symbols in GOT
 relocations [PR30788]
In-Reply-To: <PAWPR08MB8982B0075AF2F0CF9C51BADC83082@PAWPR08MB8982.eurprd08.prod.outlook.com>
References: <PAWPR08MB8982EA96A85A9846678CCFB5830B2@PAWPR08MB8982.eurprd08.prod.outlook.com>
 <da73b869-98e0-4c6a-8ea2-ee25d4fb74f9@arm.com>
 <PAWPR08MB8982B0075AF2F0CF9C51BADC83082@PAWPR08MB8982.eurprd08.prod.outlook.com>
Message-ID: <d6dd8e41-21ce-4a9b-837b-c5e54d51cd00@arm.com>

On 27/05/2026 14:07, Wilco Dijkstra wrote:
> Hi Richard,
> 
>> The Arm equivalent of this function also has checks for TLS and VTABLE relocs as well.? Do we need something similar here?
> 
> TLS is already checked separately in adjust_reloc_syms().
> 
> I don't believe any other GOT relocations are supported for AArch64. The list in
> bfd/bfd.h does not cover eg. R_AARCH64_GOTPCREL32, neither is there any
> assembler syntax defined for data relocations involving the GOT.
> 
> Cheers,
> Wilco

After some extensive archaeology it's now clear that we don't care about the VTABLE stuff.  In fact, I'm amazed that we didn't expunge that entirely some years ago - we certainly blew away all the tests for it.

OK.

R.

From sam@gentoo.org  Wed Jun 10 18:31:10 2026
From: sam@gentoo.org (Sam James)
Date: Wed, 10 Jun 2026 19:31:10 +0100
Subject: RFC: Extending the Glibc CNA to handle GNU Binutils CVEs
In-Reply-To: <87v7bq7atr.fsf@redhat.com>
References: <87v7bq7atr.fsf@redhat.com>
Message-ID: <874ijadz81.fsf@gentoo.org>

Nick Clifton <nickc@redhat.com> writes:

> Hi Guys,

Hi Nick,

>
> Over the last decade or so almost all of the Binutils bugs which have
> achieved Common Vulnerability and Exposures [1] status have been
> bogus.  In the sense they whilst they are bugs, they are not ones that
> could be exploited by an attacker to compromise a system or a network.
> This is a problem - for me and for other people who maintain the
> binutils package in distributions - because any CVE that gets filed
> has to be carefully examined and potentially will cause a lot of work
> back-porting the fix to all the supported releases.
>
> Recent updates to the SECURITY.txt document should help to reduce the
> number of CVEs that actually have to be fixed by distribution
> maintainers but it would be better if the CVEs were never created in
> the first place.
>
> To this end therefore we are looking into extending the scope of the
> current glibc CVE Numbering Authority [2] so that it will also handle
> Binutils bugs.  This should be a relatively process and it would mean
> that the glibc CNA security team can review submitted binutils bug
> reports and actually decide if they really do meet the criteria for
> being assigned a CVE rating.  It will also help that the glibc folks
> are familiar with the binutils and what the tools do.
>
> My question to you guys then is:
>
>   * Are there any concerns or objections to this idea ?

I'm on board with the idea, as long as the intent is to reject many of
the things which currently get CVEs assigned, as they do not agree with
our SECURTIY.txt policy.

Also of course assuming the team has room to support us. But it sounds
like it could help and avoid downstreams wasting time on bogus
CVEs. They've been a problem for years but it got worse like with all
projects lately thanks to recent developments.

>
> Cheers
>   Nick
>
> PS. Extending the scope of the CNA will also mean that there is the
> possibility for interested contributors to become members of the CNA
> security review team.  (It looks really good on a C.V.)
>
> PPS. In the future, if this change is successful, it may also be
> possible to extend the CNA to cover GCC and GDB.  In that way we could
> have the whole toolchain covered by knowledgeable reviewers who can
> make sure that when a CVE is assigned, it really does represent a
> threat that needs to fixed as quickly and as widely as possible.

Yes, this is a great point.

>
>
> [1] - https://www.cve.org/
> [2] - https://www.cve.org/PartnerInformation/ListofPartners/partner/glibc

sam
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From avr@gjlay.de  Wed Jun 10 19:14:38 2026
From: avr@gjlay.de (Georg-Johann Lay)
Date: Wed, 10 Jun 2026 21:14:38 +0200
Subject: [patch, avr] Support .gnu_attribute 4 (Tag_GNU_AVR_VTABLE_AS) for
 vtable address spaces
Message-ID: <ed106d30-4fae-4585-8543-9450cf545b1a@gjlay.de>

The expected, upcoming support for ISO/IEC TR 18037 "Embedded C"
named address spaces in G++ would allow to put C++ virtual tables
into such address spaces, see https://gcc.gnu.org/PR69549

Currently, vtables are in the generic address space, which wastes
RAM on cores that locate .rodata in RAM.

Any change of vtables' address space is an ABI change, and
therefore it would be nice to have a feature that checks that
all object files linked into an app are using the same vtable AS.

The patch below introduces .gnu_attribute 4 (Tag_GNU_AVR_VTABLE_AS).

This mail is a request for a pre-approval of the patch.

I don't intend to apply it until it is clear that it's really
of any use and not dead code.  Sadly, PR69549 is only progressing
at a glacial pace, so it may take yet another 10 year before
G++ can handle named address spaces --- or it may never learn it.

The patch is for trunk.


Johann

--

AVR: Add support for .gnu_attribute 4 (Tag_GNU_AVR_VTABLE_AS).

The expected, upcoming support for ISO/IEC TR 18037 "Embedded C"
named address spaces in G++ would allow to put C++ virtual tables
into such address spaces, see https://gcc.gnu.org/PR69549

The current address space used for vtables is the generic one,
which means that RAM is wasted on machines where .rodata is
located in RAM.

Named address spaces in G++ would allow users to chose an address space
that suits their requirements, e.g. by means of a new command-line
option and hooks like TARGET_ADDR_SPACE_FOR_ARTIFICIAL_RODATA.

However, in contrast to current user-selectable address spaces,
placing vtables in a different address space is an ABI change,
so that a means to detect ABI violations is highly appreciated.

The feature of choice is .gnu_attribute 4 (Tag_GNU_AVR_VTABLE_AS)
which would tag an object file with one of the following values:

0 (Val_GNU_AVR_VTABLE_NONE) for files that neither define nor access 
vtables.
1 (Val_GNU_AVR_VTABLE_RAM) for files that use the generic address space.
2 (Val_GNU_AVR_VTABLE_FLASH) the file uses the 16-bit address space __flash.
3 (Val_GNU_AVR_VTABLE_FLASH1) the file uses the 16-bit address space 
__flash1.
4 (Val_GNU_AVR_VTABLE_FLASH2) the file uses the 16-bit address space 
__flash2.
5 (Val_GNU_AVR_VTABLE_FLASH3) the file uses the 16-bit address space 
__flash3.
6 (Val_GNU_AVR_VTABLE_FLASH4) the file uses the 16-bit address space 
__flash4.
7 (Val_GNU_AVR_VTABLE_FLASH5) the file uses the 16-bit address space 
__flash5.
8 (Val_GNU_AVR_VTABLE_FLASHX) the file uses the 24-bit address space 
__flashx.

- A tag value of zero is compatible with all other tag values.

- Two non-zero tag values are compatible iff they are the same.

include/
	* elf/avr.h (libiberty.h): Include for ARRAY_SIZE.
	(Tag_GNU_AVR_VTABLE_AS = 4): New enum.
	(Val_GNU_AVR_VTABLE_NONE, Val_GNU_AVR_VTABLE_RAM)
	(Val_GNU_AVR_VTABLE_FLASH, Val_GNU_AVR_VTABLE_FLASH1)
	(Val_GNU_AVR_VTABLE_FLASH2, Val_GNU_AVR_VTABLE_FLASH3)
	(Val_GNU_AVR_VTABLE_FLASH4, Val_GNU_AVR_VTABLE_FLASH5)
	(Val_GNU_AVR_VTABLE_FLASHX, Val_GNU_AVR_VTABLE_Sentinel): New
	enum values for Tag_GNU_AVR_VTABLE_AS.
	(avr_tag_vtable_as_name): New static function.

bfd/
	* elf32-avr.h (bfd_avr_elf_merge_private_bfd_data): New proto.
	* elf32-avr.c (libiberty.h): Include for ARRAY_SIZE.
	(avr_elf_merge_obj_attributes): New static function.
	(bfd_avr_elf_merge_private_bfd_data): New function that calls it.
	(bfd_elf32_bfd_merge_private_bfd_data): Define to
	bfd_avr_elf_merge_private_bfd_data.

gas/
	* doc/as.texi (GNU Object Attributes) [AVR Attributes]: New subsection.
	* config/tc-avr.h (avr_md_finish): New proto.
	(md_finish): Define to avr_md_finish.
	* config/tc-avr.c (avr_md_finish): New function to
	sanity-check Tag_GNU_AVR_VTABLE_AS.

ld/
	* testsuite/ld-avr/attr-gnu-4-1.s: New source.
	* testsuite/ld-avr/attr-gnu-4-2.s: New source.
	* testsuite/ld-avr/attr-gnu-4-1.d: New test.
	* testsuite/ld-avr/attr-gnu-4-2.d: New test.
	* testsuite/ld-avr/attr-gnu-4-1_2.d: New test.

binutils/
	* readelf.c (display_avr_gnu_attribute): New static function.
	(process_arch_specific) <EM_AVR>: Call process_attributes
	with display_avr_gnu_attribute as a callback.
-------------- next part --------------
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From amodra@gmail.com  Wed Jun 10 22:50:10 2026
From: amodra@gmail.com (Alan Modra)
Date: Thu, 11 Jun 2026 08:20:10 +0930
Subject: [PATCH v1] LoongArch: Fix relaxation alignment with ld -r (PR
 33236)
In-Reply-To: <06cdfca7-556e-454a-b469-a2f05455fbdd@loongson.cn>
References: <20260529074340.943231-1-mengqinggang@loongson.cn>
 <06cdfca7-556e-454a-b469-a2f05455fbdd@loongson.cn>
Message-ID: <ainqIgsbGvrSXCYh@squeak.grove.modra.org>

On Mon, Jun 08, 2026 at 02:24:01PM +0800, mengqinggang wrote:
> > diff --git a/ld/ldlang.c b/ld/ldlang.c
> > index 48dd33a49bb..8c3c287a3a0 100644
> > --- a/ld/ldlang.c
> > +++ b/ld/ldlang.c
> > @@ -5769,6 +5769,10 @@ size_input_section
> >       {
> >         bfd_size_type alignment_needed;
> > +      bool synthesize_align = bfd_link_relocatable (&link_info)
> > +			      && (i->flags & SEC_CODE) != 0
> > +			      && bfd_get_arch (i->owner) == bfd_arch_loongarch;
> > +
> >         /* Align this section first to the input sections requirement,
> >   	 then to the output section's requirement.  If this alignment
> >   	 is greater than any seen before, then record it too.  Perform
> > @@ -5788,7 +5792,9 @@ size_input_section
> >         alignment_needed = align_power (dot, i->alignment_power) - dot;
> > -      if (alignment_needed != 0)
> > +      /* If synthesized ALIGN may be needed, add one align section
> > +	 and one align relocation and disable the default handling.  */
> > +      if (alignment_needed != 0 && ! synthesize_align)
> >   	{
> >   	  insert_pad (this_ptr, fill, TO_SIZE (alignment_needed), o, dot);
> >   	  dot += alignment_needed;

Architecture specific code isn't supposed to be in ldlang.c.  Yes, I
know there is a bfd_arch_tic54x test in there.  I don't like that one
either.

I haven't looked too deeply into what your patch does, but I think you
should be able to stop ldlang.c:size_input_section padding by changing
the input section alignment_power in add_align_section (and tweak
loongarch_add_align_relocs to not use the sec->alignment_power but
instead align_sec->size).

-- 
Alan Modra

From amodra@gmail.com  Wed Jun 10 23:10:51 2026
From: amodra@gmail.com (Alan Modra)
Date: Thu, 11 Jun 2026 08:40:51 +0930
Subject: [PATCH] gprof: Fix tests on Solaris [PR34237]
In-Reply-To: <yddldconnrl.fsf@CeBiTec.Uni-Bielefeld.DE>
References: <yddldconnrl.fsf@CeBiTec.Uni-Bielefeld.DE>
Message-ID: <ainu-wv6-pwNuS-j@squeak.grove.modra.org>

On Tue, Jun 09, 2026 at 10:03:58AM +0200, Rainer Orth wrote:
> 	gprof:
> 	PR gprof/34237
> 	* testsuite/Makefile.am (tst-gmon-gprof.out): Pass $(target) to
> 	tst-gmon-gprof.sh.
> 	(tst-gmon-gprof-l.out): Likewise.
> 	(tst-gmon-gprof-l2.out): Likewise.
> 	* testsuite/Makefile.in: Regenerate.
> 
> 	* testsuite/tst-gmon-gprof.sh (expected_dot): Remove.
> 	<*-*-solaris2*>: Allow main in execution counters.
> 	<powerpc-*-aix* | rs6000-*-aix*>: Handle function descriptor case here.
> 	* testsuite/tst-gmon-gprof-l.sh: Likewise.
> 	* testsuite/tst-gmon-gprof-l2.sh: Likewise.

OK.

-- 
Alan Modra

From amodra@gmail.com  Wed Jun 10 23:38:27 2026
From: amodra@gmail.com (Alan Modra)
Date: Thu, 11 Jun 2026 09:08:27 +0930
Subject: [PATCH] ld: doc: Use consistent language for 'PE target'-only
 options
In-Reply-To: <20260604132237.5508-1-jon.turney@dronecode.org.uk>
References: <20260604132237.5508-1-jon.turney@dronecode.org.uk>
Message-ID: <ain1c7YTKzkCFC-l@squeak.grove.modra.org>

On Thu, Jun 04, 2026 at 02:22:37PM +0100, Jon Turney wrote:
> 	* ld.texi (Options): Use consistent language for 'PE target'-only
> 	options.

Applied, thanks.

-- 
Alan Modra

From eager@eagercon.com  Thu Jun 11 00:39:12 2026
From: eager@eagercon.com (Michael Eager)
Date: Wed, 10 Jun 2026 17:39:12 -0700
Subject: [PATCH v2] gdb/MicroBlaze: Add support for native linux gdb
In-Reply-To: <CAL1P33xEtR7-N8XCN61oCrx-WPmgHJj1qJ7x3ksiLivdr_J9FA@mail.gmail.com>
References: <CAL1P33wvSyEkqa5KC8QH3KRN1hGGn2-H6sE59rRjsrLibprvKg@mail.gmail.com>
 <874ijq5knu.fsf@tromey.com>
 <CAL1P33xHUSaXLnKbph89ev0-Fr+izVcAEBU62sUPJ8ujHKdjbw@mail.gmail.com>
 <e8675182-6e41-431b-8f1a-4c867ab38e33@eagerm.com>
 <CAL1P33xEtR7-N8XCN61oCrx-WPmgHJj1qJ7x3ksiLivdr_J9FA@mail.gmail.com>
Message-ID: <09e2a40b-2f9f-4f8e-af31-0235baf61acd@eagercon.com>

Hi Gopi --

I (or more accurately, git) fixed several whitespace issues.

Since this is a revised patch, has it been retested?


On 6/1/26 10:05 PM, Gopi Kumar Bulusu wrote:
> namaskaaram
> 
> Attached is the updated patch. All the changes suggested on PATCH v1
> have been made and tested.
> 
> I did not remove the (sal.line != 0) check as it seemed trivial.
> However, I can make that a separate patch if necessary.
> 
> Our sysadm In the process of setting up a git compatible email - the
> process may take more time; until then appreciate your patience with
> the attachments.
> 
> Important Note:
> 
> 1) gdb appears to have an elaborate scheme to handle C++ exceptions
> and "tunnel" them through exception unaware C code. This code is with
> readline. Anytime
> an error is discovered (even a syntax error) by a module,
> gdb_exception_error() thrown is tunneled through readline using the
> TRY_SJLJ/CATCH_SJLJ macros
> implemented using setjmp/longjmp.
> 
> 2) There is an issue that I came across while testing; native gdb goes
> into an infinite loop when handling errors. I analyzed it and found it
> to be an obvious glibc
> sysdeps/unix/sysv/linux/microblaze/____longjmp_chk.S issue and
> reported it to AMD. It is possible I missed out a glibc patch; At this
> time - this is not a gdb issue.
> 
> 3) Plan to follow through [2] and ensure a gcc/glibc defect report is
> created if needed.
> 
> dhanyavaadaaha
> gopi
> 
> On Tue, Jun 2, 2026 at 5:58?AM Michael Eager <eager@eagerm.com> wrote:
>>
>> Please post an updated patch for review.
>>
>> On 5/31/26 11:38 PM, Gopi Kumar Bulusu wrote:
>>> On Fri, May 29, 2026 at 8:26?PM Tom Tromey <tom@tromey.com> wrote:
>>>>
>>>>>>>>> Gopi Kumar Bulusu <gopi@sankhya.com> writes:
>>>>
>>>>> Attached is a patch to add native linux support for gdb including
>>>>> cache target support..
>>>>
>>>> Thanks for the patch.
>>>>
>>>> I read through it and have some nits.  There's nothing very serious
>>>> except this:
>>>>
>>>>> The original sources for the patch come from Xilinx/AMD Yocto git
>>>>> repository (2025.2)
>>>>
>>>> Who wrote them and are they covered by the copyright assignment?
>>>>
>>>> This is the most important consideration, the patch can't land without
>>>> this being clear.
>>>
>>> This work is being performed under a contract with Xilinx/AMD as
>>> confirmed in a different response to
>>> Simon and therefore covered by the copyright assignment.
>>>
>>> I will make the changes as described below and retest.
>>>
>>> Approved for commit ?
>>>
>>> dhanyavaadaaha
>>> gopi
>>>
>>>>
>>>>>   From a3328b4cdfc58783b5f290f22255b36e26a6fb14 Mon Sep 17 00:00:00 2001
>>>>> From: Gopi Kumar Bulusu <gopi@sankhya.com>
>>>>> Date: Thu, 7 May 2026 17:47:40 +0530
>>>>> Subject: [PATCH] gdb/MicroBlaze: Add support for native linux gdb
>>>>
>>>> It's best to just git send-email rather than using an attachment.
>>>>
>>>>>       bfd/ChangeLog:
>>>>
>>>>>       * elf32-microblaze.c (microblaze_elf_grok_prstatus): New function.
>>>>>         (microblaze_elf_grok_psinfo): Likewise.
>>>>
>>>>>       gdb/ChangeLog:
>>>>
>>>>>       * Makefile.in (HFILES_NO_SRCDIR): Add microblaze-linux-tdep.h
>>>>>         ALLDEPFILES: Add microblaze-linux-nat.c
>>>>
>>>> gdb doesn't use ChangeLogs any more and this text should all be removed.
>>>>
>>>>> +#define MICROBLAZE_TARGET_HAS_GETREGS 0
>>>>> +#define MICROBLAZE_TARGET_HAS_SETREGS 0
>>>>
>>>> This seems weird:
>>>>
>>>>> +/* Wrapper function around ptrace.  */
>>>>> +
>>>>> +static void
>>>>> +fetch_target_gp_regs (int tid, elf_gregset_t *gregs)
>>>>> +{
>>>>> +  elf_greg_t *gregp = *gregs;
>>>>> +
>>>>> +#if MICROBLAZE_TARGET_HAS_GETREGS
>>>>> +  if (ptrace (PTRACE_GETREGS, tid, 0, (long) gregp) < 0)
>>>>> +    {
>>>>> +      perror_with_name (_("Couldn't get registers"));
>>>>> +      return;
>>>>> +    }
>>>>> +#error "this configuration did not work during testing"
>>>>
>>>> Normally we don't put new dead code into gdb.
>>>>
>>>> I think this and the defines could just be replaced with a comment
>>>> explaining that PTRACE_GETREGS doesn't work on this platform.
>>>>
>>>>> +++ b/gdb/microblaze-linux-tdep.h
>>>>> @@ -0,0 +1,24 @@
>>>>> +/* Target-dependent code for GNU/Linux on MicroBlaze.
>>>>> +
>>>>> +   Copyright (C) 2021-2026 Free Software Foundation, Inc.
>>>>> +
>>>>> +   This file is part of GDB.
>>>>> +
>>>>> +   This program is free software; you can redistribute it and/or modify
>>>>> +   it under the terms of the GNU General Public License as published by
>>>>> +   the Free Software Foundation; either version 3 of the License, or
>>>>> +   (at your option) any later version.
>>>>> +
>>>>> +   This program is distributed in the hope that it will be useful,
>>>>> +   but WITHOUT ANY WARRANTY; without even the implied warranty of
>>>>> +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>>>>> +   GNU General Public License for more details.
>>>>> +
>>>>> +   You should have received a copy of the GNU General Public License
>>>>> +   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
>>>>> +#ifndef MICROBLAZE_LINUX_TDEP_H
>>>>> +#define MICROBLAZE_LINUX_TDEP_H
>>>>> + /* Target descriptions.  */
>>>>> + extern struct target_desc *tdesc_microblaze_linux;
>>>>
>>>> Blank line between the #define and the comment.
>>>>
>>>> Also this define should have a slightly different name, see
>>>> check-include-guards.py.
>>>>
>>>>>           non_stack_instruction_found = 0;
>>>>> +          cache->register_offsets[rd] = -imm;
>>>>>           continue;
>>>>
>>>> Indentation looks wrong, probably not using tabs.
>>>>
>>>>> @@ -399,8 +400,7 @@ microblaze_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
>>>>>        {
>>>>>          sal = find_sal_for_pc (func_start, 0);
>>>>
>>>>> -      if (sal.end < func_end
>>>>> -       && start_pc <= sal.end)
>>>>> +      if (sal.line != 0 && sal.end <= func_end  && start_pc <= sal.end)
>>>>>         start_pc = sal.end;
>>>>
>>>> No objection from me but this seems somewhat unrelated.
>>>>
>>>>
>>>>>      /* Call for side effects.  */
>>>>> -  get_frame_func (next_frame);
>>>>> +  cache->pc = get_frame_func (next_frame);
>>>>
>>>> Please remove that comment as it is now wrong.
>>>>
>>>>> +  if (regnum == MICROBLAZE_SP_REGNUM)
>>>>> +        regnum = 1;
>>>>
>>>> Wrong indentation.
>>>>
>>>>> +  if (regnum == -1) {
>>>>> +    int i;
>>>>> +
>>>>> +    for (i = 0; i < MICROBLAZE_REDR_REGNUM; i++) {
>>>>> +      regcache->raw_supply (i, regs + i * MICROBLAZE_REGISTER_SIZE);
>>>>> +    }
>>>>
>>>> Wrong brace placement in this hunk.
>>>>
>>>>> +  cb (".reg", tdep->sizeof_gregset, tdep->sizeof_gregset, tdep->gregset, NULL,
>>>>> +      cb_data);
>>>>
>>>> Normally in new code we're using 'nullptr' now.  Best would be to go
>>>> through the whole patch and check for this.  You don't have to fix
>>>> pre-existing code that is using NULL though.
>>>>
>>>>>      gdbarch *gdbarch
>>>>>        = gdbarch_alloc (&info, gdbarch_tdep_up (new microblaze_gdbarch_tdep));
>>>>
>>>>> +  microblaze_gdbarch_tdep *tdep
>>>>> +    = gdbarch_tdep<microblaze_gdbarch_tdep> (gdbarch);
>>>>> +
>>>>> +  tdep->gregset = NULL;
>>>>> +  tdep->sizeof_gregset = 0;
>>>>> +  tdep->fpregset = NULL;
>>>>> +  tdep->sizeof_fpregset = 0;
>>>>
>>>> Here it would be better to just add inline initializers to the new
>>>> fields in microblaze_gdbarch_tdep.  Then they'll automatically be
>>>> initialized by the 'new'.
>>>>
>>>> Tom
>>>
>>

-- 
Michael Eager


From gopi@sankhya.com  Thu Jun 11 01:19:21 2026
From: gopi@sankhya.com (Gopi Kumar Bulusu)
Date: Thu, 11 Jun 2026 06:49:21 +0530
Subject: [PATCH v2] gdb/MicroBlaze: Add support for native linux gdb
In-Reply-To: <09e2a40b-2f9f-4f8e-af31-0235baf61acd@eagercon.com>
References: <CAL1P33wvSyEkqa5KC8QH3KRN1hGGn2-H6sE59rRjsrLibprvKg@mail.gmail.com>
 <874ijq5knu.fsf@tromey.com>
 <CAL1P33xHUSaXLnKbph89ev0-Fr+izVcAEBU62sUPJ8ujHKdjbw@mail.gmail.com>
 <e8675182-6e41-431b-8f1a-4c867ab38e33@eagerm.com>
 <CAL1P33xEtR7-N8XCN61oCrx-WPmgHJj1qJ7x3ksiLivdr_J9FA@mail.gmail.com>
 <09e2a40b-2f9f-4f8e-af31-0235baf61acd@eagercon.com>
Message-ID: <CAL1P33wZrnkuH+Tw+Ur0ULmcjbdHiWCV_ufVs5o6RtQa4EeBGQ@mail.gmail.com>

namaskaaram

On Thu, Jun 11, 2026, 6:09 AM Michael Eager <eager@eagercon.com> wrote:

> Hi Gopi --
>
> I (or more accurately, git) fixed several whitespace issues.
>

Please share. I did check all the whitespace issues flagged by git-diff.


> Since this is a revised patch, has it been retested?
>


Yes, it has been retested.

dhanyavaadaaha
gopi


> On 6/1/26 10:05 PM, Gopi Kumar Bulusu wrote:
> > namaskaaram
> >
> > Attached is the updated patch. All the changes suggested on PATCH v1
> > have been made and tested.
> >
> > I did not remove the (sal.line != 0) check as it seemed trivial.
> > However, I can make that a separate patch if necessary.
> >
> > Our sysadm In the process of setting up a git compatible email - the
> > process may take more time; until then appreciate your patience with
> > the attachments.
> >
> > Important Note:
> >
> > 1) gdb appears to have an elaborate scheme to handle C++ exceptions
> > and "tunnel" them through exception unaware C code. This code is with
> > readline. Anytime
> > an error is discovered (even a syntax error) by a module,
> > gdb_exception_error() thrown is tunneled through readline using the
> > TRY_SJLJ/CATCH_SJLJ macros
> > implemented using setjmp/longjmp.
> >
> > 2) There is an issue that I came across while testing; native gdb goes
> > into an infinite loop when handling errors. I analyzed it and found it
> > to be an obvious glibc
> > sysdeps/unix/sysv/linux/microblaze/____longjmp_chk.S issue and
> > reported it to AMD. It is possible I missed out a glibc patch; At this
> > time - this is not a gdb issue.
> >
> > 3) Plan to follow through [2] and ensure a gcc/glibc defect report is
> > created if needed.
> >
> > dhanyavaadaaha
> > gopi
> >
> > On Tue, Jun 2, 2026 at 5:58?AM Michael Eager <eager@eagerm.com> wrote:
> >>
> >> Please post an updated patch for review.
> >>
> >> On 5/31/26 11:38 PM, Gopi Kumar Bulusu wrote:
> >>> On Fri, May 29, 2026 at 8:26?PM Tom Tromey <tom@tromey.com> wrote:
> >>>>
> >>>>>>>>> Gopi Kumar Bulusu <gopi@sankhya.com> writes:
> >>>>
> >>>>> Attached is a patch to add native linux support for gdb including
> >>>>> cache target support..
> >>>>
> >>>> Thanks for the patch.
> >>>>
> >>>> I read through it and have some nits.  There's nothing very serious
> >>>> except this:
> >>>>
> >>>>> The original sources for the patch come from Xilinx/AMD Yocto git
> >>>>> repository (2025.2)
> >>>>
> >>>> Who wrote them and are they covered by the copyright assignment?
> >>>>
> >>>> This is the most important consideration, the patch can't land without
> >>>> this being clear.
> >>>
> >>> This work is being performed under a contract with Xilinx/AMD as
> >>> confirmed in a different response to
> >>> Simon and therefore covered by the copyright assignment.
> >>>
> >>> I will make the changes as described below and retest.
> >>>
> >>> Approved for commit ?
> >>>
> >>> dhanyavaadaaha
> >>> gopi
> >>>
> >>>>
> >>>>>   From a3328b4cdfc58783b5f290f22255b36e26a6fb14 Mon Sep 17 00:00:00
> 2001
> >>>>> From: Gopi Kumar Bulusu <gopi@sankhya.com>
> >>>>> Date: Thu, 7 May 2026 17:47:40 +0530
> >>>>> Subject: [PATCH] gdb/MicroBlaze: Add support for native linux gdb
> >>>>
> >>>> It's best to just git send-email rather than using an attachment.
> >>>>
> >>>>>       bfd/ChangeLog:
> >>>>
> >>>>>       * elf32-microblaze.c (microblaze_elf_grok_prstatus): New
> function.
> >>>>>         (microblaze_elf_grok_psinfo): Likewise.
> >>>>
> >>>>>       gdb/ChangeLog:
> >>>>
> >>>>>       * Makefile.in (HFILES_NO_SRCDIR): Add microblaze-linux-tdep.h
> >>>>>         ALLDEPFILES: Add microblaze-linux-nat.c
> >>>>
> >>>> gdb doesn't use ChangeLogs any more and this text should all be
> removed.
> >>>>
> >>>>> +#define MICROBLAZE_TARGET_HAS_GETREGS 0
> >>>>> +#define MICROBLAZE_TARGET_HAS_SETREGS 0
> >>>>
> >>>> This seems weird:
> >>>>
> >>>>> +/* Wrapper function around ptrace.  */
> >>>>> +
> >>>>> +static void
> >>>>> +fetch_target_gp_regs (int tid, elf_gregset_t *gregs)
> >>>>> +{
> >>>>> +  elf_greg_t *gregp = *gregs;
> >>>>> +
> >>>>> +#if MICROBLAZE_TARGET_HAS_GETREGS
> >>>>> +  if (ptrace (PTRACE_GETREGS, tid, 0, (long) gregp) < 0)
> >>>>> +    {
> >>>>> +      perror_with_name (_("Couldn't get registers"));
> >>>>> +      return;
> >>>>> +    }
> >>>>> +#error "this configuration did not work during testing"
> >>>>
> >>>> Normally we don't put new dead code into gdb.
> >>>>
> >>>> I think this and the defines could just be replaced with a comment
> >>>> explaining that PTRACE_GETREGS doesn't work on this platform.
> >>>>
> >>>>> +++ b/gdb/microblaze-linux-tdep.h
> >>>>> @@ -0,0 +1,24 @@
> >>>>> +/* Target-dependent code for GNU/Linux on MicroBlaze.
> >>>>> +
> >>>>> +   Copyright (C) 2021-2026 Free Software Foundation, Inc.
> >>>>> +
> >>>>> +   This file is part of GDB.
> >>>>> +
> >>>>> +   This program is free software; you can redistribute it and/or
> modify
> >>>>> +   it under the terms of the GNU General Public License as
> published by
> >>>>> +   the Free Software Foundation; either version 3 of the License, or
> >>>>> +   (at your option) any later version.
> >>>>> +
> >>>>> +   This program is distributed in the hope that it will be useful,
> >>>>> +   but WITHOUT ANY WARRANTY; without even the implied warranty of
> >>>>> +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> >>>>> +   GNU General Public License for more details.
> >>>>> +
> >>>>> +   You should have received a copy of the GNU General Public License
> >>>>> +   along with this program.  If not, see <
> http://www.gnu.org/licenses/>.  */
> >>>>> +#ifndef MICROBLAZE_LINUX_TDEP_H
> >>>>> +#define MICROBLAZE_LINUX_TDEP_H
> >>>>> + /* Target descriptions.  */
> >>>>> + extern struct target_desc *tdesc_microblaze_linux;
> >>>>
> >>>> Blank line between the #define and the comment.
> >>>>
> >>>> Also this define should have a slightly different name, see
> >>>> check-include-guards.py.
> >>>>
> >>>>>           non_stack_instruction_found = 0;
> >>>>> +          cache->register_offsets[rd] = -imm;
> >>>>>           continue;
> >>>>
> >>>> Indentation looks wrong, probably not using tabs.
> >>>>
> >>>>> @@ -399,8 +400,7 @@ microblaze_skip_prologue (struct gdbarch
> *gdbarch, CORE_ADDR start_pc)
> >>>>>        {
> >>>>>          sal = find_sal_for_pc (func_start, 0);
> >>>>
> >>>>> -      if (sal.end < func_end
> >>>>> -       && start_pc <= sal.end)
> >>>>> +      if (sal.line != 0 && sal.end <= func_end  && start_pc <=
> sal.end)
> >>>>>         start_pc = sal.end;
> >>>>
> >>>> No objection from me but this seems somewhat unrelated.
> >>>>
> >>>>
> >>>>>      /* Call for side effects.  */
> >>>>> -  get_frame_func (next_frame);
> >>>>> +  cache->pc = get_frame_func (next_frame);
> >>>>
> >>>> Please remove that comment as it is now wrong.
> >>>>
> >>>>> +  if (regnum == MICROBLAZE_SP_REGNUM)
> >>>>> +        regnum = 1;
> >>>>
> >>>> Wrong indentation.
> >>>>
> >>>>> +  if (regnum == -1) {
> >>>>> +    int i;
> >>>>> +
> >>>>> +    for (i = 0; i < MICROBLAZE_REDR_REGNUM; i++) {
> >>>>> +      regcache->raw_supply (i, regs + i * MICROBLAZE_REGISTER_SIZE);
> >>>>> +    }
> >>>>
> >>>> Wrong brace placement in this hunk.
> >>>>
> >>>>> +  cb (".reg", tdep->sizeof_gregset, tdep->sizeof_gregset,
> tdep->gregset, NULL,
> >>>>> +      cb_data);
> >>>>
> >>>> Normally in new code we're using 'nullptr' now.  Best would be to go
> >>>> through the whole patch and check for this.  You don't have to fix
> >>>> pre-existing code that is using NULL though.
> >>>>
> >>>>>      gdbarch *gdbarch
> >>>>>        = gdbarch_alloc (&info, gdbarch_tdep_up (new
> microblaze_gdbarch_tdep));
> >>>>
> >>>>> +  microblaze_gdbarch_tdep *tdep
> >>>>> +    = gdbarch_tdep<microblaze_gdbarch_tdep> (gdbarch);
> >>>>> +
> >>>>> +  tdep->gregset = NULL;
> >>>>> +  tdep->sizeof_gregset = 0;
> >>>>> +  tdep->fpregset = NULL;
> >>>>> +  tdep->sizeof_fpregset = 0;
> >>>>
> >>>> Here it would be better to just add inline initializers to the new
> >>>> fields in microblaze_gdbarch_tdep.  Then they'll automatically be
> >>>> initialized by the 'new'.
> >>>>
> >>>> Tom
> >>>
> >>
>
> --
> Michael Eager
>
>
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From simark@simark.ca  Thu Jun 11 01:41:11 2026
From: simark@simark.ca (Simon Marchi)
Date: Wed, 10 Jun 2026 21:41:11 -0400
Subject: [PATCH v2] gdb/MicroBlaze: Add support for native linux gdb
In-Reply-To: <CAL1P33wZrnkuH+Tw+Ur0ULmcjbdHiWCV_ufVs5o6RtQa4EeBGQ@mail.gmail.com>
References: <CAL1P33wvSyEkqa5KC8QH3KRN1hGGn2-H6sE59rRjsrLibprvKg@mail.gmail.com>
 <874ijq5knu.fsf@tromey.com>
 <CAL1P33xHUSaXLnKbph89ev0-Fr+izVcAEBU62sUPJ8ujHKdjbw@mail.gmail.com>
 <e8675182-6e41-431b-8f1a-4c867ab38e33@eagerm.com>
 <CAL1P33xEtR7-N8XCN61oCrx-WPmgHJj1qJ7x3ksiLivdr_J9FA@mail.gmail.com>
 <09e2a40b-2f9f-4f8e-af31-0235baf61acd@eagercon.com>
 <CAL1P33wZrnkuH+Tw+Ur0ULmcjbdHiWCV_ufVs5o6RtQa4EeBGQ@mail.gmail.com>
Message-ID: <4f2b9910-6366-44c8-b468-59a27183597c@simark.ca>

On 6/10/26 9:19 PM, Gopi Kumar Bulusu wrote:
> 
> namaskaaram 
> 
> On Thu, Jun 11, 2026, 6:09 AM Michael Eager <eager@eagercon.com <mailto:eager@eagercon.com>> wrote:
> 
>     Hi Gopi --
> 
>     I (or more accurately, git) fixed several whitespace issues.
> 
> 
> Please share. I did check all the whitespace issues flagged by git-diff.

For whitespaces, I suggest to install pre-commit, there is a hook that
checks it.  See:

https://sourceware.org/gdb/wiki/DeveloperTips#Setting_up_pre-commit

Simon

From gopi@sankhya.com  Thu Jun 11 01:44:20 2026
From: gopi@sankhya.com (Gopi Kumar Bulusu)
Date: Thu, 11 Jun 2026 07:14:20 +0530
Subject: [PATCH v2] gdb/MicroBlaze: Add support for native linux gdb
In-Reply-To: <4f2b9910-6366-44c8-b468-59a27183597c@simark.ca>
References: <CAL1P33wvSyEkqa5KC8QH3KRN1hGGn2-H6sE59rRjsrLibprvKg@mail.gmail.com>
 <874ijq5knu.fsf@tromey.com>
 <CAL1P33xHUSaXLnKbph89ev0-Fr+izVcAEBU62sUPJ8ujHKdjbw@mail.gmail.com>
 <e8675182-6e41-431b-8f1a-4c867ab38e33@eagerm.com>
 <CAL1P33xEtR7-N8XCN61oCrx-WPmgHJj1qJ7x3ksiLivdr_J9FA@mail.gmail.com>
 <09e2a40b-2f9f-4f8e-af31-0235baf61acd@eagercon.com>
 <CAL1P33wZrnkuH+Tw+Ur0ULmcjbdHiWCV_ufVs5o6RtQa4EeBGQ@mail.gmail.com>
 <4f2b9910-6366-44c8-b468-59a27183597c@simark.ca>
Message-ID: <CAL1P33wqEW3yZGwdMJsV3dWqqc4ZhxL=11zQsa=-S-OUisrW+A@mail.gmail.com>

namaskaaram

On Thu, Jun 11, 2026, 7:11 AM Simon Marchi <simark@simark.ca> wrote:

> On 6/10/26 9:19 PM, Gopi Kumar Bulusu wrote:
> >
> > namaskaaram
> >
> > On Thu, Jun 11, 2026, 6:09 AM Michael Eager <eager@eagercon.com <mailto:
> eager@eagercon.com>> wrote:
> >
> >     Hi Gopi --
> >
> >     I (or more accurately, git) fixed several whitespace issues.
> >
> >
> > Please share. I did check all the whitespace issues flagged by git-diff.
>
> For whitespaces, I suggest to install pre-commit, there is a hook that
> checks it.  See:
>
> https://sourceware.org/gdb/wiki/DeveloperTips#Setting_up_pre-commit


Thanks, I will install  it.

dhanyavaadaaha
gopi


> Simon
>
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From mengqinggang@loongson.cn  Thu Jun 11 01:55:52 2026
From: mengqinggang@loongson.cn (mengqinggang)
Date: Thu, 11 Jun 2026 09:55:52 +0800
Subject: [PATCH v1] LoongArch: Fix relaxation alignment with ld -r (PR
 33236)
In-Reply-To: <ainqIgsbGvrSXCYh@squeak.grove.modra.org>
References: <20260529074340.943231-1-mengqinggang@loongson.cn>
 <06cdfca7-556e-454a-b469-a2f05455fbdd@loongson.cn>
 <ainqIgsbGvrSXCYh@squeak.grove.modra.org>
Message-ID: <4b9c223c-9e70-443d-8a8d-e49eb1a5735c@loongson.cn>

Thanks for your feedback. I will make changes based on your advice.


? 2026/6/11 06:50, Alan Modra ??:
> On Mon, Jun 08, 2026 at 02:24:01PM +0800, mengqinggang wrote:
>>> diff --git a/ld/ldlang.c b/ld/ldlang.c
>>> index 48dd33a49bb..8c3c287a3a0 100644
>>> --- a/ld/ldlang.c
>>> +++ b/ld/ldlang.c
>>> @@ -5769,6 +5769,10 @@ size_input_section
>>>        {
>>>          bfd_size_type alignment_needed;
>>> +      bool synthesize_align = bfd_link_relocatable (&link_info)
>>> +			      && (i->flags & SEC_CODE) != 0
>>> +			      && bfd_get_arch (i->owner) == bfd_arch_loongarch;
>>> +
>>>          /* Align this section first to the input sections requirement,
>>>    	 then to the output section's requirement.  If this alignment
>>>    	 is greater than any seen before, then record it too.  Perform
>>> @@ -5788,7 +5792,9 @@ size_input_section
>>>          alignment_needed = align_power (dot, i->alignment_power) - dot;
>>> -      if (alignment_needed != 0)
>>> +      /* If synthesized ALIGN may be needed, add one align section
>>> +	 and one align relocation and disable the default handling.  */
>>> +      if (alignment_needed != 0 && ! synthesize_align)
>>>    	{
>>>    	  insert_pad (this_ptr, fill, TO_SIZE (alignment_needed), o, dot);
>>>    	  dot += alignment_needed;
> Architecture specific code isn't supposed to be in ldlang.c.  Yes, I
> know there is a bfd_arch_tic54x test in there.  I don't like that one
> either.
>
> I haven't looked too deeply into what your patch does, but I think you
> should be able to stop ldlang.c:size_input_section padding by changing
> the input section alignment_power in add_align_section (and tweak
> loongarch_add_align_relocs to not use the sec->alignment_power but
> instead align_sec->size).
>
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From amodra@gmail.com  Thu Jun 11 07:08:10 2026
From: amodra@gmail.com (Alan Modra)
Date: Thu, 11 Jun 2026 16:38:10 +0930
Subject: mips-coff: mips_reflo_reloc buffer overflow
Message-ID: <aipe2n8ea-4plQm4@squeak.grove.modra.org>

Like commit c2cb1bfb901e, but for mips-coff.  Make the hi reloc list
per-section rather than per-file, since fuzzers can generate objects
with cross-section refs where the hi reloc section data is freed
before the lo relocs are processed.

Also properly sanity check the hi reloc offset.

	* libecoff.h (struct ecoff_tdata): Move mips_refhi_list to..
	(struct ecoff_section_tdata): ..here.
	(ecoff_section_data): Remove unused abfd arg.
	* coff-alpha.c (alpha_relocate_section): Update ecoff_section_data.
	* coff-mips.c (mips_refhi_reloc): Use bfd_reloc_offset_in_range.
	Allocate ecoff_section_data as necessary.  Use that instead of
	bfd tdata.
	(mips_reflo_reloc): Adjust to suit tdata change.
	* ecoff.c (_bfd_ecoff_bfd_free_cached_info): Likewise.

diff --git a/bfd/coff-alpha.c b/bfd/coff-alpha.c
index 0396a1fd9fc..35677e9a933 100644
--- a/bfd/coff-alpha.c
+++ b/bfd/coff-alpha.c
@@ -1445,7 +1445,7 @@ alpha_relocate_section (bfd *output_bfd,
 
       /* Make sure we have a section data structure to which we can
 	 hang on to the gp value we pick for the section.  */
-      lita_sec_data = ecoff_section_data (input_bfd, lita_sec);
+      lita_sec_data = ecoff_section_data (lita_sec);
       if (lita_sec_data == NULL)
 	{
 	  lita_sec_data = bfd_zalloc (input_bfd, sizeof (*lita_sec_data));
diff --git a/bfd/coff-mips.c b/bfd/coff-mips.c
index 85abe9f4360..35848d94ca1 100644
--- a/bfd/coff-mips.c
+++ b/bfd/coff-mips.c
@@ -460,17 +460,29 @@ mips_refhi_reloc (bfd *abfd,
   relocation += symbol->section->output_offset;
   relocation += reloc_entry->addend;
 
-  if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
+  bfd_size_type octet = (reloc_entry->address
+			 * OCTETS_PER_BYTE (abfd, input_section));
+  if (!bfd_reloc_offset_in_range (reloc_entry->howto, abfd,
+				  input_section, octet))
     return bfd_reloc_outofrange;
 
+  struct ecoff_section_tdata *sdata = ecoff_section_data (input_section);
+  if (sdata == NULL)
+    {
+      sdata = bfd_zalloc (abfd, sizeof (*sdata));
+      if (sdata == NULL)
+	return bfd_reloc_outofrange;
+      input_section->used_by_bfd = sdata;
+    }
+
   /* Save the information, and let REFLO do the actual relocation.  */
-  n = (struct mips_hi *) bfd_malloc ((bfd_size_type) sizeof *n);
+  n = bfd_malloc (sizeof (*n));
   if (n == NULL)
     return bfd_reloc_outofrange;
   n->addr = (bfd_byte *) data + reloc_entry->address;
   n->addend = relocation;
-  n->next = ecoff_data (abfd)->mips_refhi_list;
-  ecoff_data (abfd)->mips_refhi_list = n;
+  n->next = sdata->mips_refhi_list;
+  sdata->mips_refhi_list = n;
 
   if (output_bfd != (bfd *) NULL)
     reloc_entry->address += input_section->output_offset;
@@ -491,11 +503,11 @@ mips_reflo_reloc (bfd *abfd,
 		  bfd *output_bfd,
 		  char **error_message)
 {
-  if (ecoff_data (abfd)->mips_refhi_list != NULL)
+  struct ecoff_section_tdata *sdata = ecoff_section_data (input_section);
+  if (sdata != NULL)
     {
-      struct mips_hi *l;
+      struct mips_hi *l = sdata->mips_refhi_list;
 
-      l = ecoff_data (abfd)->mips_refhi_list;
       while (l != NULL)
 	{
 	  unsigned long insn;
@@ -537,8 +549,7 @@ mips_reflo_reloc (bfd *abfd,
 	  free (l);
 	  l = next;
 	}
-
-      ecoff_data (abfd)->mips_refhi_list = NULL;
+      sdata->mips_refhi_list = NULL;
     }
 
   /* Now do the REFLO reloc in the usual way.  */
diff --git a/bfd/ecoff.c b/bfd/ecoff.c
index cd56a46c460..906fe44725e 100644
--- a/bfd/ecoff.c
+++ b/bfd/ecoff.c
@@ -117,11 +117,18 @@ _bfd_ecoff_bfd_free_cached_info (bfd *abfd)
   if (bfd_get_format (abfd) == bfd_object
       && (tdata = ecoff_data (abfd)) != NULL)
     {
-      while (tdata->mips_refhi_list != NULL)
+      for (asection *sec = abfd->sections; sec != NULL; sec = sec->next)
 	{
-	  struct mips_hi *ref = tdata->mips_refhi_list;
-	  tdata->mips_refhi_list = ref->next;
-	  free (ref);
+	  struct ecoff_section_tdata *sdata = ecoff_section_data (sec);
+	  if (sdata != NULL)
+	    {
+	      while (sdata->mips_refhi_list != NULL)
+		{
+		  struct mips_hi *ref = sdata->mips_refhi_list;
+		  sdata->mips_refhi_list = ref->next;
+		  free (ref);
+		}
+	    }
 	}
       _bfd_ecoff_free_ecoff_debug_info (&tdata->debug_info);
     }
diff --git a/bfd/libecoff.h b/bfd/libecoff.h
index 1d781c7d309..25619b7346c 100644
--- a/bfd/libecoff.h
+++ b/bfd/libecoff.h
@@ -153,9 +153,6 @@ typedef struct ecoff_tdata
      particular ECOFF file.  This is not valid until
      ecoff_compute_section_file_positions is called.  */
   bool rdata_in_text;
-
-  /* Used by coff-mips.c to track REFHI relocs for pairing with REFLO.  */
-  struct mips_hi *mips_refhi_list;
 } ecoff_data_type;
 
 /* Each canonical asymbol really looks like this.  */
@@ -201,10 +198,13 @@ struct ecoff_section_tdata
      we need to keep track of the gp values that we picked for each
      input .lita section . */
   bfd_vma gp;
+
+  /* Used by coff-mips.c to track REFHI relocs for pairing with REFLO.  */
+  struct mips_hi *mips_refhi_list;
 };
 
 /* An accessor macro for the ecoff_section_tdata structure.  */
-#define ecoff_section_data(abfd, sec) \
+#define ecoff_section_data(sec) \
   ((struct ecoff_section_tdata *) (sec)->used_by_bfd)
 
 /* ECOFF linker hash table entries.  */

-- 
Alan Modra

From builder@sourceware.org  Thu Jun 11 08:34:17 2026
From: builder@sourceware.org (builder@sourceware.org)
Date: Thu, 11 Jun 2026 08:34:17 +0000
Subject: =?utf-8?q?=E2=98=BA_Buildbot_=28Sourceware=29=3A_binutils-gdb_-_build_successful_=28master=29?=
Message-ID: <20260611083418.083AE4BA540B@sourceware.org>

A restored build has been detected on builder binutils-solaris11-amd64 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/369/builds/16

Build state: build successful
Revision: c52a3e86835f40dc4048e038f3cec6b97dba69fb
Worker: solaris11-amd64
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>, Andrew Burgess <aburgess@redhat.com>, Etienne Brateau <etienne.brateau@gmail.com>, GDB Administrator <gdbadmin@sourceware.org>, Jon Turney <jon.turney@dronecode.org.uk>, Markus Metzger <markus.t.metzger@intel.com>, Matthieu Longo <matthieu.longo@arm.com>, Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>, S?bastien Darche <sdarche@efficios.com>, Tom Tromey <tromey@adacore.com>, Tom de Vries <tdevries@suse.de>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/3/logs/config_log

- 4: make ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/4/logs/stdio
        - warnings (31): https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/4/logs/warnings__31_

- 5: make check ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/5/logs/stdio
        - ld.sum: https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/5/logs/ld_sum
        - ld.log: https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/5/logs/ld_log
        - gas.sum: https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/5/logs/gas_sum
        - gas.log: https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/5/logs/gas_log
        - gprof.log: https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/5/logs/gprof_log
        - binutils.sum: https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/5/logs/binutils_sum
        - binutils.log: https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/5/logs/binutils_log
        - libsframe.sum: https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/5/logs/libsframe_sum
        - libsframe.log: https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/5/logs/libsframe_log
        - libctf.sum: https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/5/logs/libctf_sum
        - libctf.log: https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/5/logs/libctf_log
        - warnings (15): https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/5/logs/warnings__15_

- 6: prep ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/6/logs/stdio

- 7: collect system versions ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/7/logs/stdio

- 8: fetch .bunsen.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/8/logs/stdio

- 9: build bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/9/logs/stdio

- 10: fetch bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/10/logs/stdio

- 11: unpack bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/11/logs/stdio

- 12: pass .bunsen.source.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/12/logs/stdio

- 13: upload to bunsen ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/13/logs/stdio

- 14: clean up ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/14/logs/stdio

- 15: rm -rf binutils-build_1 ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/369/builds/16/steps/15/logs/stdio


From evgeny.karpov@arm.com  Thu Jun 11 10:53:52 2026
From: evgeny.karpov@arm.com (Evgeny Karpov)
Date: Thu, 11 Jun 2026 12:53:52 +0200
Subject: [PATCH v7 3/3] aarch64: Implement Structured Exception Handling
 (SEH) on AArch64
In-Reply-To: <aie-l4-Kkq6ZpROJ@arm.com>
Message-ID: <aiqTwE35VjTbqiYK@arm.com>

On Thu, 16 Apr 2026, Alice Carlotti wrote:
> > and pdata/xdata SEH records are emitted from md_finish.
> > 
> > When .pdata/.xdata is emitted, the function size is required.
> > Function sizes are calculated as late as possible, and the code segment needs
> > to be relaxed to be able to calculate the function sizes.
> > 
> > Initially, obj_coff_generate_pdata was declared in write_object_file.
> 
> I think you mean "called in write_object_file".

Yes, it will be fixed.
 
> > Before the change, obj_coff_generate_pdata was used only to validate
> > syntax, which was sufficient for that purpose. However, that location
> > seems incorrect, as it is too late to emit .pdata/.xdata records
> > in the AArch64 case.
> > 
> > md_finish has been declared for AArch64 and extended with
> > seh_aarch64_write_data to emit .pdata/.xdata records after all
> > assembly has been completed.
> > 
> > Signed-off-by: Evgeny Karpov <evgeny@kmaps.co>
> 
> Some general remarks:
> 
> - Epilogue/epilog and prologue/prolog in various names.  We should be
>   consistent with Microsoft's description, so remove the "ue"s.
> 
> - It hard to know whether the input parsing is correct when this patch doesn't
>   include any tests or documentation for the assembler directives.

As it was mentioned in another message, prologue and epilogue will be used.
The patch series has been validated with CI tests. These tests will be added to binutils.

obj-coff-seh-aarch64.h contains a description for the assembler directives and 
obj-coff-seh-aarch64.cpp provides the link to the documentation.
One more link will be added to obj-coff-seh-aarch64.h.

> > +  unsigned code_bits;
> > +  unsigned code;
> > +  unsigned offset_right_shift;
> > +  unsigned offset;
> > +  unsigned reg_right_shift;
> > +  unsigned reg_offset;
> > +  unsigned size;
> 
> The non-pointer members can all use 'unsigned char'.
> 
> The word "offset" has two different meanings here - how about using
> offset_addend and reg_addend instead?
> 
> Specifying the shift direction in the names is unnecessary.
> 
> Also see below about field ordering.

unsigned char will be used instead.
offset will be renamed to offset_addend and reg_offset to reg_addend.
Shift direction will be removed.

> > +};
> > +
> > +static const struct aarch64_unwind_code_pack_info
> > +aarch64_unwind_code_pack_data[] = {
> > +/* Unwind codes packing for AArch64 is described at
> 
> Nit: s/is/are/, and I think this comment belongs above the array type rather
> than inside the braces.
> 
> These codes are for the non-packed unwind format, so 'pack' should be dropped
> from the names and description.  You could also add that the array is indexed
> by the seh_aarch64_unwind_types enum.

It will be fixed and moved slightly higher.
The type will be renamed and the description will be extended.
 
> > +   https://learn.microsoft.com/en-us/cpp/build/arm64-exception-handling?view=msvc-170#unwind-codes
> > +   and calculated in seh_aarch64_add_unwind_element function.  */
> > +  {
> > +    .directive = NULL, .offset_bits = 5, .reg_bits = 0,
> > +    .code_bits = 3, .code = AARCH64_UNOP_ALLOCS, .offset_right_shift = 4,
> > +    .offset = 0, .reg_right_shift = 0, .reg_offset = 0, .size = 1
> > +  },
> 
> I find this layout rather difficult to read.  Reordering the field definitions
> and adding more line breaks would help - for example:
> 
> +  {
> +    .directive = NULL,
> +    .size = 1,
> +    .code_bits = 3, .code = AARCH64_UNOP_ALLOCS,
> +    .offset_bits = 5, .offset_shift = 4, .offset_addend = 0,
> +    .reg_bits = 0, .reg_shift = 0, .reg_addend = 0
> +  },
> 
> The AARCH64_UNOP_* defines add a level of indirection without (in my eyes)
> improving clarity, so I'd drop those (but add in a comment with the unwind code
> name when this can't be deduced from the directive).
> 
> Members that are NULL or 0 can be empty initialised.  If you also eliminate the
> code_bits member (reducing the struct size to 16 bytes), then this reduces the
> above example to:
> 
> +  {
> +    /* alloc_s */
> +    .size = 1, .code = 0b000,
> +    .offset_bits = 5, .offset_right_shift = 4,
> +  },
 
The reordering will be done.
AARCH64_UNOP_ will be removed.
Members that are NULL or 0 will be removed.
 
> > +static void
> > +seh_aarch64_add_unwind_element (const seh_aarch64_unwind_types unwind_type,
> > +				unsigned offset, unsigned reg)
> > +{
> > +  gas_assert (in_seh_proc);
> > +
> > +  const struct aarch64_unwind_code_pack_info *unwind_code_pack_info
> 
> This variable could just be called 'info'; the shorter name makes the rest of
> the function much more readable.

unwind_code_pack_info will be renamed to info.

> > +      + unwind_code_pack_info->size) > AARCH64_MAX_UNWIND_CODES_SIZE)
> > +    as_bad (_("no unwind element available."));
> > +
> > +  seh_aarch64_unwind_code *aarch64_element;
> > +  aarch64_element = seh_ctx_cur->unwind_codes
> > +		    + seh_ctx_cur->unwind_codes_count++;
> > +  aarch64_element->value = 0;
> 
> I think these four lines would be better placed at the end of the function
> (after computing the value).  We also don't need to specify aarch64 in a local
> variable name.

aarch64_element will be renamed to element and 4 lines will be moved to the end of the function.

> > +    {
> > +      reg = (reg >> unwind_code_pack_info->reg_right_shift)
> > +	    - unwind_code_pack_info->reg_offset;
> > +      reg &= (1 << unwind_code_pack_info->reg_bits) - 1;
> > +      aarch64_element->value |= reg << value_offset_bits;
> > +      value_offset_bits += unwind_code_pack_info->reg_bits;
> > +    }
> 
> Instead of silently masking out overflowing bits in offset/reg, I think it
> would be better to explicitly check and reject.

The code will be extended with a validation for offset and reg.
 
> > +
> > +  if (unwind_code_pack_info->code_bits)
> > +    {
> > +      unsigned code = unwind_code_pack_info->code;
> > +      code &= (1 << unwind_code_pack_info->code_bits) - 1;
> > +      aarch64_element->value |= code << value_offset_bits;
> 
> I think the whole function flows a bit better if you build the value starting
> from the code.  I'd suggest the following (to replace these three if blocks):
> 
> if (offset & ~(((1 << info->offset_bits) - 1) << info->offset_shift))
>   as_bad (...)
> if (reg & ~(((1 << info->reg_bits) - 1) << info->reg_shift))
>   as_bad (...)
> 
> value = info->code;
> if (info->reg_bits)
>   value = (value << info->reg_bits)
> 	  | ((reg - info->reg_addend) >> info->reg_shift)
> if (info->offset_bits)
>   value = (value << info->offset_bits)
> 	  | ((offset - info->offset_addend) >> info->offset_shift)
> 
> 
> (The 'if's are actually unnecessary here, but they might make the code a bit
> clearer.  This also makes the 'code_bits' value unused, so you could drop that.)

It makes sense to drop the condition for code_bits.
The rest will be slightly changed as it requires value_offset_bits.

> > +{
> > +  if (!verify_context (".seh_startepilogue")
> > +      || !seh_validate_seg (".seh_startepilogue"))
> > +    return;
> > +  demand_empty_rest_of_line ();
> > +
> > +  const unsigned max_epilogue_scopes = AARCH64_MAX_EPILOGUE_SCOPES;
> 
> This could be inlined into the condition.

Ok. It will be inlined.

> > +	    S_GET_NAME (epilogue_start_addr));
> > +
> > +  if (seh_ctx_cur->epilogue_scopes_count
> > +      >= seh_ctx_cur->epilogue_scopes_capacity)
> > +    {
> > +      const unsigned initial_capacity = 32;
> 
> This variable could be inlined.

It makes sense to keep const unsigned defined to keep meaning for the value.

> > +
> > +  char *symbol_name = NULL;
> > +  unsigned reg = -1;
> > +
> > +  if (unwind_code_pack_info->reg_bits)
> > +    {
> > +      char name_end = get_symbol_name (&symbol_name);
> 
> We should check the first character - is it required to match the register
> name?

The check for the register name will be added and unwinding code will be
extended with reg_type.

> > +    }
> > +
> > +  unsigned unwind_bytes_offset = 0;
> > +  for (unsigned i = 0; i < seh_ctx->unwind_codes_count; ++i)
> > +    {
> > +      const seh_aarch64_unwind_code *code = seh_ctx->unwind_codes
> > +					    + i;
> 
> Why is this line wrapped?  I think up to 79 chars is ok.

It will be changed.

> > +      /*  emit unwind code bytes in big endian.  */
> > +      number_to_chars_bigendian (frag_more (byte_count), code->value,
> > +				 byte_count);
> > +      total_byte_count += byte_count;
> > +    }
> > +
> > +    /* handle word alignment.  */
> 
> nit: Capital H

The uppercase will be used.

> > +    unsigned required_padding = (4 - total_byte_count % 4) % 4;
> 
> This could just be:
> 
> +    unsigned required_padding = (- total_byte_count) % 4;

A good point. It will be updated.

> > +    if (required_padding)
> > +      {
> > +	/* Use AARCH64_UNOP_NOP for alignment.  */
> > +	const uint32_t nop_chain = (AARCH64_UNOP_NOP << 24)
> > +				   | (AARCH64_UNOP_NOP << 16)
> > +				   | (AARCH64_UNOP_NOP << 8)
> > +				   | AARCH64_UNOP_NOP;
> 
> How about removing the define and using:
> 
> +	/* Use the nop unwind code for alignment.  */
> +	const uint32_t nop_chain = 0xe3e3e3e3;

Ok, it will be changed.

> > +  addressT start_offset, end_offset;
> > +  start_frag = symbol_get_frag_and_value (seh_ctx->start_addr, &start_offset);
> > +  end_frag = symbol_get_frag_and_value (seh_ctx->end_addr, &end_offset);
> > +
> > +  intptr_t func_size = end_frag->fr_address + end_offset
> > +		       - start_frag->fr_address - start_offset;
> > +  if (func_size < 0)
> 
> Does this always hold when the function size "has not been evaluated"?

Yes, it makes sense to stop compilation when function size cannot be properly calculated.
It means the assembler has an internal issue and should be fixed.

> > +  /* The large functions should be split into fragments smaller than 1MB with
> > +     4 bytes alignment.
> > +     https://learn.microsoft.com/en-us/cpp/build/arm64-exception-handling?view=msvc-170#large-functions.  */
> > +  const unsigned max_frag_size = (1 << 20) - 4;
> > +  const bool is_fragmented_function = func_size > max_frag_size;
> > +
> > +  /* [first_fragment_scope, last_fragment_scope).  */
> 
> This comment is in the wrong place.

The comment will be removed to avoid the confusion.

> > +  while (true)
> > +    {
> > +      fragment->xdata_addr = symbol_temp_new_now ();
> > +      fragment->offset = fragment_offset;
> > +      fragment->next = NULL;
> > +
> > +      uintptr_t frag_size = func_size - fragment_offset;
> 
> I think it would be marginally better to use a frag_end variable instead of
> frag_size.

It is hard to say. frag_size looks more readable than frag_end and represents
the size of the current fragment.

> > +		  break;
> > +		}
> > +
> > +	      if (scope->epilogue_start_offset >= fragment_offset)
> > +		last_fragment_scope = i + 1;
> > +	    }
> > +	}
> 
> You're missing handling for too many epilogs or too many code words.

Unwind capacity is handled in seh_aarch64_add_unwind_element,
and epilogue capacity is handled in obj_coff_seh_startepilogue,
by AARCH64_MAX_UNWIND_CODES_SIZE and AARCH64_MAX_EPILOGUE_SCOPES.

> > +		  scope = scopes + first_fragment_scope;
> > +		  header->ext_epilogue_count = scope->epilogue_start_index;
> > +		}
> > +	    }
> > +	  md_number_to_chars (frag_more (4),
> > +			      seh_ctx->xdata_header_value, 4);
> > +	}
> 
> I think it might be clearer if this header emission were split off into a
> separated function.  It might also help to avoid tying the internal struct
> layout to the on disk format (and perhaps just passing it as separate
> arguments).

xdata record writing will be moved to a separate function.

> > +	break;
> > +
> > +      fragment->next = XCNEW (seh_aarch64_func_fragment);
> > +      fragment = fragment->next;
> > +    }
> > +
> > +  subseg_set (save_seg, save_subseg);
> 
> I've struggled to follow this function; please add some inline comments to explain the flow (and/ore refactor it to make the flow clearer).

The comments will be added.

> > +
> > +/* SEH COFF AArch64 implementation partially intersects with the x64
> > +   version, however it has a different extension to the unwind codes.
> > +   It emits SEH data to pdata and xdata sections.  In some cases SEH
> > +   data could be emitted to a packed record in the pdata section
> > +   without the need for data in the xdata section.  However, the packed
> > +   pdata record is not implemented yet.  */
> 
> Can we have a separate list of things that aren't yet supported (at least as a
> separate paragraph).  As well as packed unwind data, I think this includes:
> - Support for SVE/SME (at least, I think that's what the unimplemented unwind
>   codes are used for);
> - Reuse of identical unwind code sequences.

Ok, it makes sense.
"Reuse of identical unwind code sequences" is not applicable for 
aarch64-w64-mingw32.
The description will be extended with text below.

/* The current implementation does not include:
   - Packed pdata record.
   - Support for AdvSIMD and SVE.
   - Handling for pacibsp.  */

> > +
> > +  subsegT subsection;
> > +
> > +  union {
> > +    seh_aarch64_xdata_header xdata_header;
> > +    valueT xdata_header_value;
> > +  };
> 
> I think this type punning is incorrect for a big endian host, and there might
> be other portability issues beyond this.  Type punning to a struct of two
> uint32_t values is more likely to work, but that's still not guaranteed by the
> C standard to be correct, so it might be best just to build uint32_t values
> from the individual bitfields piece by piece.

The big endian host should be supported properly by md_number_to_chars that is used
for emitting pdata/xdata records.

> >  enum pointer_auth_key {
> >    AARCH64_PAUTH_KEY_A,
> > @@ -363,6 +368,7 @@ extern void aarch64_handle_align (struct frag *);
> >  extern int tc_aarch64_regname_to_dw2regnum (char *regname);
> >  extern void tc_aarch64_frame_initial_instructions (void);
> >  extern bool aarch64_fix_adjustable (struct fix *);
> > +extern void seh_aarch64_write_data (void);
> 
> Should this declaration be gated by OBJ_COFF?

seh_aarch64_write_data will be moved under OBJ_COFF scope.

Regards,
Evgeny


From mark@klomp.org  Thu Jun 11 10:38:35 2026
From: mark@klomp.org (Mark Wielaard)
Date: Thu, 11 Jun 2026 12:38:35 +0200
Subject: Sourceware budget and funding 2026/2027, Fri 12, 15:00 UTC
Message-ID: <20260611103835.GH14081@gnu.wildebeest.org>

Hi all,

Tomorrow is the second Friday of the month, so it is time for the
Sourceware Open Office again.

Based on last months budget discussions and last years financial
overview the Sourceware Project Leadership Committee wrote up an
ambitious budget and funding proposal for 2026/2027, see below. Lets
discuss if this matches community expectations and what the most
effective way is to drive this fundraising campaign.

Friday June 12, from 15:00 UTC to 16:00 UTC
At #overseers on irc.libera.chat

$ date -d "Fri Jun 12 15:00 UTC 2026"

We ended the previous year with the successful completion of our
infrastructure hardware refresh cycle
https://sourceware.org/sourceware-wiki/servers-and-services-2026/
Doubling of individual donations and increased (corporate) "in-kind"
support for hosting and networking support.

For the 2026/2027 fiscal year, we would like to shift our budget focus
to spend less on "iron" and more on "services and people". We would
like to finally provide financial support/compensation to our partner
OSUOSL. Hire payed staff/consultants to help with services upgrades
and VM migrations. And look into funding upstream Forgejo
improvements.

Our budget and funding targets three "layers" of sponsors. Individual
sponsors, Corporate sponsors and Grant Makers.

* Individual Sponsors: "Empowering the Maintainers"
  Independence and a worry-free developer experience

  Individual developers and contributors who rely on Sourceware for
  their daily work. Sourceware is the worry-free home for the tools
  you build and use every day. Our focus is on making your workflow
  faster, more secure and something you don't have to think about. It
  is just there. Thanks to your help we moved to a modern, VM-first
  infrastructure and are experimenting with a dedicated Forge to
  streamline collaboration. Your small, monthly contributions are the
  lifeblood of our independence, ensuring that the core infrastructure
  remains community-run and developer-focused.

- Target $4,000-$6,000
  $500 Domain fees, banking, and essential operational overhead.
  $1,000 Contribution toward OSUOSL colocation and bandwidth.
  $3,000 Forgejo improvements
  $1,500 Emergency hardware replacement fund.

* Corporate Sponsors: "Securing the Global Supply Chain"
  Infrastructure security and accelerating engineering velocity

  Sourceware hosts the projects at the very heart of the Free Software
  supply chain. We are seeking corporate partners to help us
  professionalize our security posture. By sponsoring Sourceware, you
  aren?t just donating; you are insuring the integrity of the tools
  your business is built upon. Our focus is on modernizing, isolating,
  and automating our services to stay ahead of the evolving
  cybersecurity landscape. And eliminating administrative tasks so
  engineers can focus on their projects.

- Target $4,000-$12,000
  4x $2,500-$4,000 Consultants to upgrade, VM isolation and automation
                   for bugzilla, public-inbox, patchwork and buildbot.
- In kind donations of builder machines and server hosting

* Grant Makers: "Sustainable Infrastructure for the Next 25 Years"
  Sustainability, Governance, and Global Impact

  Sourceware provides the foundational infrastructure that has
  anchored the core Free Software toolchain and developer tools for
  over 25 years. We are seeking institutional partners to help us
  preserve this deep institutional knowledge and safeguard the digital
  commons for the next quarter century. As a member project of the
  Software Freedom Conservancy, we pair our historical expertise with
  professional asset stewardship and independent community
  governance. Through our collaboration with corporate partners and
  the Open Source Lab (OSUOSL) we provide Free Infrastructure for Free
  Software projects. Grant funding will empower us to scale this
  critical cooperation, formalize our standard operating procedures,
  and transfer decades of technical expertise to the next generation
  of admins and developers.

- Target $20,000-$40,000 To hire a part-time Junior System
  Administrator (potentially in partnership with OSUOSL). This role
  will document Standard Operating Procedures (SOPs), handle daily
  administrative tasks, and ensure the long-term sustainability of the
  infrastructure.

Our Mission https://sourceware.org/mission.html
Security Vision https://sourceware.org/sourceware-security-vision.html
25-Year Roadmap https://sourceware.org/sourceware-25-roadmap.html

Sourceware looking backward, looking forward:
https://inbox.sourceware.org/overseers/20260510223754.GR1219@gnu.wildebeest.org
And the yearly (financial) overview:
https://inbox.sourceware.org/overseers/20260516203206.GR1219@gnu.wildebeest.org

Sourceware relies on cooperation among a broad diversity of core
toolchain and developer tool projects, hackers, organizations,
ideas, and communication styles. The monthly Sourceware Open Office
meetings are one way of coming together as a community and discuss
our shared development infrastructure. For other ways to participate
see https://sourceware.org/mission.html#organization

Keep Sourceware worry-free, friendly and independent by donating
https://sourceware.org/donate.html support our fiscal sponser SFC
https://sfconservancy.org/sustainer and/or support OSUOSL for
hosting Free Software projects https://osuosl.org/donate/

Do you or your company want to sponsor Sourceware plans financially
https://sourceware.org/sourceware-security-vision.html#plans
donate hardware or services then contact us at sponsor@sourceware.org


From eager@eagercon.com  Thu Jun 11 12:52:14 2026
From: eager@eagercon.com (Michael Eager)
Date: Thu, 11 Jun 2026 05:52:14 -0700
Subject: [PATCH v2] gdb/MicroBlaze: Add support for native linux gdb
In-Reply-To: <CAL1P33wZrnkuH+Tw+Ur0ULmcjbdHiWCV_ufVs5o6RtQa4EeBGQ@mail.gmail.com>
References: <CAL1P33wvSyEkqa5KC8QH3KRN1hGGn2-H6sE59rRjsrLibprvKg@mail.gmail.com>
 <874ijq5knu.fsf@tromey.com>
 <CAL1P33xHUSaXLnKbph89ev0-Fr+izVcAEBU62sUPJ8ujHKdjbw@mail.gmail.com>
 <e8675182-6e41-431b-8f1a-4c867ab38e33@eagerm.com>
 <CAL1P33xEtR7-N8XCN61oCrx-WPmgHJj1qJ7x3ksiLivdr_J9FA@mail.gmail.com>
 <09e2a40b-2f9f-4f8e-af31-0235baf61acd@eagercon.com>
 <CAL1P33wZrnkuH+Tw+Ur0ULmcjbdHiWCV_ufVs5o6RtQa4EeBGQ@mail.gmail.com>
Message-ID: <74cafbc7-e490-4954-a613-aba92b59d26a@eagercon.com>

Committed d62f64e17

On 6/10/26 6:19 PM, Gopi Kumar Bulusu wrote:
> 
> namaskaaram
> 
> On Thu, Jun 11, 2026, 6:09 AM Michael Eager <eager@eagercon.com 
> <mailto:eager@eagercon.com>> wrote:
> 
>     Hi Gopi --
> 
>     I (or more accurately, git) fixed several whitespace issues.
> 
> 
> Please share. I did check all the whitespace issues flagged by git-diff.
> 
> 
>     Since this is a revised patch, has it been retested?
> 
> 
> 
> Yes, it has been retested.
> 
> dhanyavaadaaha
> gopi
> 
> 
>     On 6/1/26 10:05 PM, Gopi Kumar Bulusu wrote:
>      > namaskaaram
>      >
>      > Attached is the updated patch. All the changes suggested on PATCH v1
>      > have been made and tested.
>      >
>      > I did not remove the (sal.line != 0) check as it seemed trivial.
>      > However, I can make that a separate patch if necessary.
>      >
>      > Our sysadm In the process of setting up a git compatible email - the
>      > process may take more time; until then appreciate your patience with
>      > the attachments.
>      >
>      > Important Note:
>      >
>      > 1) gdb appears to have an elaborate scheme to handle C++ exceptions
>      > and "tunnel" them through exception unaware C code. This code is with
>      > readline. Anytime
>      > an error is discovered (even a syntax error) by a module,
>      > gdb_exception_error() thrown is tunneled through readline using the
>      > TRY_SJLJ/CATCH_SJLJ macros
>      > implemented using setjmp/longjmp.
>      >
>      > 2) There is an issue that I came across while testing; native gdb
>     goes
>      > into an infinite loop when handling errors. I analyzed it and
>     found it
>      > to be an obvious glibc
>      > sysdeps/unix/sysv/linux/microblaze/____longjmp_chk.S issue and
>      > reported it to AMD. It is possible I missed out a glibc patch; At
>     this
>      > time - this is not a gdb issue.
>      >
>      > 3) Plan to follow through [2] and ensure a gcc/glibc defect report is
>      > created if needed.
>      >
>      > dhanyavaadaaha
>      > gopi
>      >
>      > On Tue, Jun 2, 2026 at 5:58?AM Michael Eager <eager@eagerm.com
>     <mailto:eager@eagerm.com>> wrote:
>      >>
>      >> Please post an updated patch for review.
>      >>
>      >> On 5/31/26 11:38 PM, Gopi Kumar Bulusu wrote:
>      >>> On Fri, May 29, 2026 at 8:26?PM Tom Tromey <tom@tromey.com
>     <mailto:tom@tromey.com>> wrote:
>      >>>>
>      >>>>>>>>> Gopi Kumar Bulusu <gopi@sankhya.com
>     <mailto:gopi@sankhya.com>> writes:
>      >>>>
>      >>>>> Attached is a patch to add native linux support for gdb including
>      >>>>> cache target support..
>      >>>>
>      >>>> Thanks for the patch.
>      >>>>
>      >>>> I read through it and have some nits.? There's nothing very
>     serious
>      >>>> except this:
>      >>>>
>      >>>>> The original sources for the patch come from Xilinx/AMD Yocto git
>      >>>>> repository (2025.2)
>      >>>>
>      >>>> Who wrote them and are they covered by the copyright assignment?
>      >>>>
>      >>>> This is the most important consideration, the patch can't land
>     without
>      >>>> this being clear.
>      >>>
>      >>> This work is being performed under a contract with Xilinx/AMD as
>      >>> confirmed in a different response to
>      >>> Simon and therefore covered by the copyright assignment.
>      >>>
>      >>> I will make the changes as described below and retest.
>      >>>
>      >>> Approved for commit ?
>      >>>
>      >>> dhanyavaadaaha
>      >>> gopi
>      >>>
>      >>>>
>      >>>>>? ?From a3328b4cdfc58783b5f290f22255b36e26a6fb14 Mon Sep 17
>     00:00:00 2001
>      >>>>> From: Gopi Kumar Bulusu <gopi@sankhya.com
>     <mailto:gopi@sankhya.com>>
>      >>>>> Date: Thu, 7 May 2026 17:47:40 +0530
>      >>>>> Subject: [PATCH] gdb/MicroBlaze: Add support for native linux gdb
>      >>>>
>      >>>> It's best to just git send-email rather than using an attachment.
>      >>>>
>      >>>>>? ? ? ?bfd/ChangeLog:
>      >>>>
>      >>>>>? ? ? ?* elf32-microblaze.c (microblaze_elf_grok_prstatus):
>     New function.
>      >>>>>? ? ? ? ?(microblaze_elf_grok_psinfo): Likewise.
>      >>>>
>      >>>>>? ? ? ?gdb/ChangeLog:
>      >>>>
>      >>>>>? ? ? ?* Makefile.in (HFILES_NO_SRCDIR): Add microblaze-linux-
>     tdep.h
>      >>>>>? ? ? ? ?ALLDEPFILES: Add microblaze-linux-nat.c
>      >>>>
>      >>>> gdb doesn't use ChangeLogs any more and this text should all
>     be removed.
>      >>>>
>      >>>>> +#define MICROBLAZE_TARGET_HAS_GETREGS 0
>      >>>>> +#define MICROBLAZE_TARGET_HAS_SETREGS 0
>      >>>>
>      >>>> This seems weird:
>      >>>>
>      >>>>> +/* Wrapper function around ptrace.? */
>      >>>>> +
>      >>>>> +static void
>      >>>>> +fetch_target_gp_regs (int tid, elf_gregset_t *gregs)
>      >>>>> +{
>      >>>>> +? elf_greg_t *gregp = *gregs;
>      >>>>> +
>      >>>>> +#if MICROBLAZE_TARGET_HAS_GETREGS
>      >>>>> +? if (ptrace (PTRACE_GETREGS, tid, 0, (long) gregp) < 0)
>      >>>>> +? ? {
>      >>>>> +? ? ? perror_with_name (_("Couldn't get registers"));
>      >>>>> +? ? ? return;
>      >>>>> +? ? }
>      >>>>> +#error "this configuration did not work during testing"
>      >>>>
>      >>>> Normally we don't put new dead code into gdb.
>      >>>>
>      >>>> I think this and the defines could just be replaced with a comment
>      >>>> explaining that PTRACE_GETREGS doesn't work on this platform.
>      >>>>
>      >>>>> +++ b/gdb/microblaze-linux-tdep.h
>      >>>>> @@ -0,0 +1,24 @@
>      >>>>> +/* Target-dependent code for GNU/Linux on MicroBlaze.
>      >>>>> +
>      >>>>> +? ?Copyright (C) 2021-2026 Free Software Foundation, Inc.
>      >>>>> +
>      >>>>> +? ?This file is part of GDB.
>      >>>>> +
>      >>>>> +? ?This program is free software; you can redistribute it
>     and/or modify
>      >>>>> +? ?it under the terms of the GNU General Public License as
>     published by
>      >>>>> +? ?the Free Software Foundation; either version 3 of the
>     License, or
>      >>>>> +? ?(at your option) any later version.
>      >>>>> +
>      >>>>> +? ?This program is distributed in the hope that it will be
>     useful,
>      >>>>> +? ?but WITHOUT ANY WARRANTY; without even the implied
>     warranty of
>      >>>>> +? ?MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.? See the
>      >>>>> +? ?GNU General Public License for more details.
>      >>>>> +
>      >>>>> +? ?You should have received a copy of the GNU General Public
>     License
>      >>>>> +? ?along with this program.? If not, see <http://
>     www.gnu.org/licenses/ <http://www.gnu.org/licenses/>>.? */
>      >>>>> +#ifndef MICROBLAZE_LINUX_TDEP_H
>      >>>>> +#define MICROBLAZE_LINUX_TDEP_H
>      >>>>> + /* Target descriptions.? */
>      >>>>> + extern struct target_desc *tdesc_microblaze_linux;
>      >>>>
>      >>>> Blank line between the #define and the comment.
>      >>>>
>      >>>> Also this define should have a slightly different name, see
>      >>>> check-include-guards.py.
>      >>>>
>      >>>>>? ? ? ? ? ?non_stack_instruction_found = 0;
>      >>>>> +? ? ? ? ? cache->register_offsets[rd] = -imm;
>      >>>>>? ? ? ? ? ?continue;
>      >>>>
>      >>>> Indentation looks wrong, probably not using tabs.
>      >>>>
>      >>>>> @@ -399,8 +400,7 @@ microblaze_skip_prologue (struct gdbarch
>     *gdbarch, CORE_ADDR start_pc)
>      >>>>>? ? ? ? {
>      >>>>>? ? ? ? ? sal = find_sal_for_pc (func_start, 0);
>      >>>>
>      >>>>> -? ? ? if (sal.end < func_end
>      >>>>> -? ? ? ?&& start_pc <= sal.end)
>      >>>>> +? ? ? if (sal.line != 0 && sal.end <= func_end? && start_pc
>     <= sal.end)
>      >>>>>? ? ? ? ?start_pc = sal.end;
>      >>>>
>      >>>> No objection from me but this seems somewhat unrelated.
>      >>>>
>      >>>>
>      >>>>>? ? ? /* Call for side effects.? */
>      >>>>> -? get_frame_func (next_frame);
>      >>>>> +? cache->pc = get_frame_func (next_frame);
>      >>>>
>      >>>> Please remove that comment as it is now wrong.
>      >>>>
>      >>>>> +? if (regnum == MICROBLAZE_SP_REGNUM)
>      >>>>> +? ? ? ? regnum = 1;
>      >>>>
>      >>>> Wrong indentation.
>      >>>>
>      >>>>> +? if (regnum == -1) {
>      >>>>> +? ? int i;
>      >>>>> +
>      >>>>> +? ? for (i = 0; i < MICROBLAZE_REDR_REGNUM; i++) {
>      >>>>> +? ? ? regcache->raw_supply (i, regs + i *
>     MICROBLAZE_REGISTER_SIZE);
>      >>>>> +? ? }
>      >>>>
>      >>>> Wrong brace placement in this hunk.
>      >>>>
>      >>>>> +? cb (".reg", tdep->sizeof_gregset, tdep->sizeof_gregset,
>     tdep->gregset, NULL,
>      >>>>> +? ? ? cb_data);
>      >>>>
>      >>>> Normally in new code we're using 'nullptr' now.? Best would be
>     to go
>      >>>> through the whole patch and check for this.? You don't have to fix
>      >>>> pre-existing code that is using NULL though.
>      >>>>
>      >>>>>? ? ? gdbarch *gdbarch
>      >>>>>? ? ? ? = gdbarch_alloc (&info, gdbarch_tdep_up (new
>     microblaze_gdbarch_tdep));
>      >>>>
>      >>>>> +? microblaze_gdbarch_tdep *tdep
>      >>>>> +? ? = gdbarch_tdep<microblaze_gdbarch_tdep> (gdbarch);
>      >>>>> +
>      >>>>> +? tdep->gregset = NULL;
>      >>>>> +? tdep->sizeof_gregset = 0;
>      >>>>> +? tdep->fpregset = NULL;
>      >>>>> +? tdep->sizeof_fpregset = 0;
>      >>>>
>      >>>> Here it would be better to just add inline initializers to the new
>      >>>> fields in microblaze_gdbarch_tdep.? Then they'll automatically be
>      >>>> initialized by the 'new'.
>      >>>>
>      >>>> Tom
>      >>>
>      >>
> 
>     -- 
>     Michael Eager
> 

-- 
Michael Eager


From jbeulich@suse.com  Thu Jun 11 13:22:32 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Thu, 11 Jun 2026 15:22:32 +0200
Subject: Using .macro argument in .error message?
In-Reply-To: <f319074e-a8ed-4e0d-8326-4dab9ce178d0@gjlay.de>
References: <7bfb02e7-d3cd-4c89-a5b7-bdb7e598d7a2@gjlay.de>
 <9be37f12-b10f-4f22-8b06-3fb302252e36@suse.com>
 <f319074e-a8ed-4e0d-8326-4dab9ce178d0@gjlay.de>
Message-ID: <06ccb560-58df-40ad-aa53-8ba778835c6d@suse.com>

On 10.06.2026 11:54, Georg-Johann Lay wrote:
> Am 10.06.26 um 11:27 schrieb Jan Beulich:
>> On 07.06.2026 21:16, Georg-Johann Lay via Binutils wrote:
>>> Test case err.sx:
>>>
>>> .macro Test data
>>> ????? .if \data < 0
>>> ????????? .error "value \data is negative"
>>> ????? .endif
>>> .endm
>>>
>>> ????? Test -1
>>>
>>>
>>> $ avr-as err.sx -v
>>> GNU assembler version 2.45.50 (avr) using BFD version (GNU Binutils)
>>> 2.45.50.20250718
>>> err.sx: Assembler messages:
>>> err.sx: Warning: unknown escape '\d' in string; ignored
>>> err.sx:3: Error: value -1 is negative
>>> err.sx:7:? Info: macro invoked from here
>>>
>>> While the printed error message is as expected, there is a spurious
>>> warning about using \d in the string.
>>>
>>> What am I missing?
>>>
>>> As far as I understand, the .error message /must/ be "-quoted.
>>
>> Indeed. But AVR is one of the few targets which enable this extra
>> warning. Why that is or whether it could be changed requires AVR
>> knowledge, which I don#t have. There's also a surprising set of
>> characters for which the warning would never appear. I don't know
>> the history of that set, but it feels pretty arbitrary.
>>
>> Jan
> 
> Okay, I didn't even notice that it's target specific... The only
> related place I could find is in gas/config/tc-avr.h:
> 
> /* If you define this macro, GAS will warn about the use of
> ?? nonstandard escape sequences in a string.? */
> #define ONLY_STANDARD_ESCAPES

This is it, yes.

> Though whatever the behavior wrt. fishy escapes is, resolution
> of macro arguments shoud run prior to that, no?

No. Macros are processed after the scrubber (aka "pre-processor") has
done its work.

Jan

From avr@gjlay.de  Thu Jun 11 13:42:43 2026
From: avr@gjlay.de (Georg-Johann Lay)
Date: Thu, 11 Jun 2026 15:42:43 +0200
Subject: Using .macro argument in .error message?
In-Reply-To: <06ccb560-58df-40ad-aa53-8ba778835c6d@suse.com>
References: <7bfb02e7-d3cd-4c89-a5b7-bdb7e598d7a2@gjlay.de>
 <9be37f12-b10f-4f22-8b06-3fb302252e36@suse.com>
 <f319074e-a8ed-4e0d-8326-4dab9ce178d0@gjlay.de>
 <06ccb560-58df-40ad-aa53-8ba778835c6d@suse.com>
Message-ID: <09392a0b-35f8-4048-a20b-82cca728f647@gjlay.de>

Am 11.06.26 um 15:22 schrieb Jan Beulich:
> On 10.06.2026 11:54, Georg-Johann Lay wrote:
>> Am 10.06.26 um 11:27 schrieb Jan Beulich:
>>> On 07.06.2026 21:16, Georg-Johann Lay via Binutils wrote:
>>>> Test case err.sx:
>>>>
>>>> .macro Test data
>>>>  ????? .if \data < 0
>>>>  ????????? .error "value \data is negative"
>>>>  ????? .endif
>>>> .endm
>>>>
>>>>  ????? Test -1
>>>>
>>>> $ avr-as err.sx -v
>>>> GNU assembler version 2.45.50 (avr) using BFD version (GNU Binutils)
>>>> 2.45.50.20250718
>>>> err.sx: Assembler messages:
>>>> err.sx: Warning: unknown escape '\d' in string; ignored
>>>> err.sx:3: Error: value -1 is negative
>>>> err.sx:7:? Info: macro invoked from here
>>>>
>>>> While the printed error message is as expected, there is a spurious
>>>> warning about using \d in the string.
>>>>
>>>> What am I missing?
>>>>
>>>> As far as I understand, the .error message /must/ be "-quoted.
>>>
>>> Indeed. But AVR is one of the few targets which enable this extra
>>> warning. Why that is or whether it could be changed requires AVR
>>> knowledge, which I don#t have. There's also a surprising set of
>>> characters for which the warning would never appear. I don't know
>>> the history of that set, but it feels pretty arbitrary.
>>>
>>> Jan
>>
>> Okay, I didn't even notice that it's target specific... The only
>> related place I could find is in gas/config/tc-avr.h:
>>
>> /* If you define this macro, GAS will warn about the use of
>>  ?? nonstandard escape sequences in a string.? */
>> #define ONLY_STANDARD_ESCAPES
> 
> This is it, yes.
> 
>> Though whatever the behavior wrt. fishy escapes is, resolution
>> of macro arguments shoud run prior to that, no?
> 
> No. Macros are processed after the scrubber (aka "pre-processor") has
> done its work.
> 
> Jan

Whatever the technical limitations are; such a warning makes just no sense.

Johann


From rearnsha@arm.com  Thu Jun 11 13:50:13 2026
From: rearnsha@arm.com (Richard Earnshaw)
Date: Thu, 11 Jun 2026 14:50:13 +0100
Subject: [PATCH] gas: deprecate .vtable_entry and .vtable_inherit
Message-ID: <20260611135013.3534885-1-rearnsha@arm.com>

These ELF directives were a GNU extension to support the C++ ABI
that was in use before the introduction of the generic C++ ABI in
GCC-3.0.  They're obsolete now and many newer targets simply
do not provide the back-end support for them.

Flag them as deprecated in the NEWS file, and remove the documentation
for them.  Warn (once) if the directive is used in a source file.
---
 gas/NEWS             |  6 ++++++
 gas/config/obj-elf.c | 16 ++++++++++++++++
 gas/doc/as.texi      |  8 ++++++++
 3 files changed, 30 insertions(+)

diff --git a/gas/NEWS b/gas/NEWS
index e384d1135c0..bcbc575cbc0 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,4 +1,10 @@
 -*- text -*-
+Changes in 2.47:
+
+* The legacy .vtable_entry and .vtable_inherit directives that were
+  needed for versions of gcc prior to gcc-3.0 (when the generic C++
+  ABI was adopted) are now considered obsolete.  They are now deprecated
+  and will be removed in a future release.
 
 Changes in 2.46:
 
diff --git a/gas/config/obj-elf.c b/gas/config/obj-elf.c
index 09a224147e9..6850cab1902 100644
--- a/gas/config/obj-elf.c
+++ b/gas/config/obj-elf.c
@@ -2019,6 +2019,14 @@ obj_elf_get_vtable_inherit (void)
 void
 obj_elf_vtable_inherit (int ignore ATTRIBUTE_UNUSED)
 {
+  static bool warned = false;
+
+  if (!warned)
+    {
+      warned = true;
+      as_warn(".vtable_inherit has been deprecated");
+    }
+
   (void) obj_elf_get_vtable_inherit ();
 }
 
@@ -2061,6 +2069,14 @@ obj_elf_get_vtable_entry (void)
 void
 obj_elf_vtable_entry (int ignore ATTRIBUTE_UNUSED)
 {
+  static bool warned = false;
+
+  if (!warned)
+    {
+      warned = true;
+      as_warn("'.vtable_entry' has been deprecated");
+    }
+
   (void) obj_elf_get_vtable_entry ();
 }
 
diff --git a/gas/doc/as.texi b/gas/doc/as.texi
index 5c80a3100dc..3c4d20bd7d4 100644
--- a/gas/doc/as.texi
+++ b/gas/doc/as.texi
@@ -4724,8 +4724,11 @@ Some machine configurations provide additional directives.
 
 @ifset ELF
 * Version::                     @code{.version "@var{string}"}
+@ignore
 * VTableEntry::                 @code{.vtable_entry @var{table}, @var{offset}}
 * VTableInherit::               @code{.vtable_inherit @var{child}, @var{parent}}
+@end ignore
+
 @end ifset
 
 * Warnif::			@code{.warnif @var{expression}}
@@ -7796,7 +7799,11 @@ This directive creates a @code{.note} section and places into it an ELF
 formatted note of type NT_VERSION.  The note's name is set to @code{string}.
 @end ifset
 
+@ignore
 @ifset ELF
+@c .vtable_entry and .vtable_inherit were for the C++ implementation
+@c that predated the generic C++ ABI.  They're obsolete now, so
+@c don't include them in the documentation.
 @node VTableEntry
 @section @code{.vtable_entry @var{table}, @var{offset}}
 
@@ -7813,6 +7820,7 @@ This directive finds the symbol @code{child} and finds or creates the symbol
 parent whose addend is the value of the child symbol.  As a special case the
 parent name of @code{0} is treated as referring to the @code{*ABS*} section.
 @end ifset
+@end ignore
 
 @node Warnif
 @section @code{.warnif "@var{expression}"}
-- 
2.43.0


From jbeulich@suse.com  Thu Jun 11 14:18:41 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Thu, 11 Jun 2026 16:18:41 +0200
Subject: Using .macro argument in .error message?
In-Reply-To: <09392a0b-35f8-4048-a20b-82cca728f647@gjlay.de>
References: <7bfb02e7-d3cd-4c89-a5b7-bdb7e598d7a2@gjlay.de>
 <9be37f12-b10f-4f22-8b06-3fb302252e36@suse.com>
 <f319074e-a8ed-4e0d-8326-4dab9ce178d0@gjlay.de>
 <06ccb560-58df-40ad-aa53-8ba778835c6d@suse.com>
 <09392a0b-35f8-4048-a20b-82cca728f647@gjlay.de>
Message-ID: <e2e677be-e3b5-49bd-8933-2d135ab66b6b@suse.com>

On 11.06.2026 15:42, Georg-Johann Lay wrote:
> Am 11.06.26 um 15:22 schrieb Jan Beulich:
>> On 10.06.2026 11:54, Georg-Johann Lay wrote:
>>> Am 10.06.26 um 11:27 schrieb Jan Beulich:
>>>> On 07.06.2026 21:16, Georg-Johann Lay via Binutils wrote:
>>>>> Test case err.sx:
>>>>>
>>>>> .macro Test data
>>>>> ?????? .if \data < 0
>>>>> ?????????? .error "value \data is negative"
>>>>> ?????? .endif
>>>>> .endm
>>>>>
>>>>> ?????? Test -1
>>>>>
>>>>> $ avr-as err.sx -v
>>>>> GNU assembler version 2.45.50 (avr) using BFD version (GNU Binutils)
>>>>> 2.45.50.20250718
>>>>> err.sx: Assembler messages:
>>>>> err.sx: Warning: unknown escape '\d' in string; ignored
>>>>> err.sx:3: Error: value -1 is negative
>>>>> err.sx:7:? Info: macro invoked from here
>>>>>
>>>>> While the printed error message is as expected, there is a spurious
>>>>> warning about using \d in the string.
>>>>>
>>>>> What am I missing?
>>>>>
>>>>> As far as I understand, the .error message /must/ be "-quoted.
>>>>
>>>> Indeed. But AVR is one of the few targets which enable this extra
>>>> warning. Why that is or whether it could be changed requires AVR
>>>> knowledge, which I don#t have. There's also a surprising set of
>>>> characters for which the warning would never appear. I don't know
>>>> the history of that set, but it feels pretty arbitrary.
>>>
>>> Okay, I didn't even notice that it's target specific... The only
>>> related place I could find is in gas/config/tc-avr.h:
>>>
>>> /* If you define this macro, GAS will warn about the use of
>>> ??? nonstandard escape sequences in a string.? */
>>> #define ONLY_STANDARD_ESCAPES
>>
>> This is it, yes.
>>
>>> Though whatever the behavior wrt. fishy escapes is, resolution
>>> of macro arguments shoud run prior to that, no?
>>
>> No. Macros are processed after the scrubber (aka "pre-processor") has
>> done its work.
> 
> Whatever the technical limitations are; such a warning makes just no sense.

The person who had added it likely was of a different opinion. I'm pretty sure
things can be improved, and feel free to send a patch, but justifying such a
change will likely require some archeology, not just saying "makes no sense".
In particular the architecture's native assembler's behavior also needs taking
into account.

Jan

From avr@gjlay.de  Thu Jun 11 14:54:12 2026
From: avr@gjlay.de (Georg-Johann Lay)
Date: Thu, 11 Jun 2026 16:54:12 +0200
Subject: Using .macro argument in .error message?
In-Reply-To: <e2e677be-e3b5-49bd-8933-2d135ab66b6b@suse.com>
References: <7bfb02e7-d3cd-4c89-a5b7-bdb7e598d7a2@gjlay.de>
 <9be37f12-b10f-4f22-8b06-3fb302252e36@suse.com>
 <f319074e-a8ed-4e0d-8326-4dab9ce178d0@gjlay.de>
 <06ccb560-58df-40ad-aa53-8ba778835c6d@suse.com>
 <09392a0b-35f8-4048-a20b-82cca728f647@gjlay.de>
 <e2e677be-e3b5-49bd-8933-2d135ab66b6b@suse.com>
Message-ID: <2c27cdd3-e04e-44c6-9a4b-997afb19c768@gjlay.de>

Am 11.06.26 um 16:18 schrieb Jan Beulich:
> On 11.06.2026 15:42, Georg-Johann Lay wrote:
>> Am 11.06.26 um 15:22 schrieb Jan Beulich:
>>> On 10.06.2026 11:54, Georg-Johann Lay wrote:
>>>> Am 10.06.26 um 11:27 schrieb Jan Beulich:
>>>>> On 07.06.2026 21:16, Georg-Johann Lay via Binutils wrote:
>>>>>> Test case err.sx:
>>>>>>
>>>>>> .macro Test data
>>>>>>  ?????? .if \data < 0
>>>>>>  ?????????? .error "value \data is negative"
>>>>>>  ?????? .endif
>>>>>> .endm
>>>>>>
>>>>>>  ?????? Test -1
>>>>>>
>>>>>> $ avr-as err.sx -v
>>>>>> GNU assembler version 2.45.50 (avr) using BFD version (GNU Binutils)
>>>>>> 2.45.50.20250718
>>>>>> err.sx: Assembler messages:
>>>>>> err.sx: Warning: unknown escape '\d' in string; ignored
>>>>>> err.sx:3: Error: value -1 is negative
>>>>>> err.sx:7:? Info: macro invoked from here
>>>>>>
>>>>>> While the printed error message is as expected, there is a spurious
>>>>>> warning about using \d in the string.
>>>>>>
>>>>>> What am I missing?
>>>>>>
>>>>>> As far as I understand, the .error message /must/ be "-quoted.
>>>>>
>>>>> Indeed. But AVR is one of the few targets which enable this extra
>>>>> warning. Why that is or whether it could be changed requires AVR
>>>>> knowledge, which I don#t have. There's also a surprising set of
>>>>> characters for which the warning would never appear. I don't know
>>>>> the history of that set, but it feels pretty arbitrary.
>>>>
>>>> Okay, I didn't even notice that it's target specific... The only
>>>> related place I could find is in gas/config/tc-avr.h:
>>>>
>>>> /* If you define this macro, GAS will warn about the use of
>>>>  ??? nonstandard escape sequences in a string.? */
>>>> #define ONLY_STANDARD_ESCAPES
>>>
>>> This is it, yes.
>>>
>>>> Though whatever the behavior wrt. fishy escapes is, resolution
>>>> of macro arguments should run prior to that, no?
>>>
>>> No. Macros are processed after the scrubber (aka "pre-processor") has
>>> done its work.
>>
>> Whatever the technical limitations are; such a warning makes just no sense.
> 
> The person who had added it likely was of a different opinion. I'm pretty sure
> things can be improved, and feel free to send a patch, but justifying such a
> change will likely require some archeology, not just saying "makes no sense".

What I am trying to say is that warning for an unrecognized escape
sequence isn't very helpful when the sequence is NOT an escape sequence
to begin with.  In the example, \data is treated as a .macro parameter,
so there is no unknown escape sequence `\d' anywhere.

> In particular the architecture's native assembler's behavior also needs taking
> into account.
> 
> Jan

What you mean by "native assembler"?

avr-as is the only AVR assembler used by GCC.
There are other assemblers like avra or avrasm2, but they are 
incompatible in many regards.

Johann


From jbeulich@suse.com  Thu Jun 11 15:17:09 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Thu, 11 Jun 2026 17:17:09 +0200
Subject: Using .macro argument in .error message?
In-Reply-To: <2c27cdd3-e04e-44c6-9a4b-997afb19c768@gjlay.de>
References: <7bfb02e7-d3cd-4c89-a5b7-bdb7e598d7a2@gjlay.de>
 <9be37f12-b10f-4f22-8b06-3fb302252e36@suse.com>
 <f319074e-a8ed-4e0d-8326-4dab9ce178d0@gjlay.de>
 <06ccb560-58df-40ad-aa53-8ba778835c6d@suse.com>
 <09392a0b-35f8-4048-a20b-82cca728f647@gjlay.de>
 <e2e677be-e3b5-49bd-8933-2d135ab66b6b@suse.com>
 <2c27cdd3-e04e-44c6-9a4b-997afb19c768@gjlay.de>
Message-ID: <1ffffdfd-51f6-4ca8-a439-bb58579bf5f1@suse.com>

On 11.06.2026 16:54, Georg-Johann Lay wrote:
> Am 11.06.26 um 16:18 schrieb Jan Beulich:
>> On 11.06.2026 15:42, Georg-Johann Lay wrote:
>>> Am 11.06.26 um 15:22 schrieb Jan Beulich:
>>>> On 10.06.2026 11:54, Georg-Johann Lay wrote:
>>>>> Am 10.06.26 um 11:27 schrieb Jan Beulich:
>>>>>> On 07.06.2026 21:16, Georg-Johann Lay via Binutils wrote:
>>>>>>> Test case err.sx:
>>>>>>>
>>>>>>> .macro Test data
>>>>>>> ??????? .if \data < 0
>>>>>>> ??????????? .error "value \data is negative"
>>>>>>> ??????? .endif
>>>>>>> .endm
>>>>>>>
>>>>>>> ??????? Test -1
>>>>>>>
>>>>>>> $ avr-as err.sx -v
>>>>>>> GNU assembler version 2.45.50 (avr) using BFD version (GNU Binutils)
>>>>>>> 2.45.50.20250718
>>>>>>> err.sx: Assembler messages:
>>>>>>> err.sx: Warning: unknown escape '\d' in string; ignored
>>>>>>> err.sx:3: Error: value -1 is negative
>>>>>>> err.sx:7:? Info: macro invoked from here
>>>>>>>
>>>>>>> While the printed error message is as expected, there is a spurious
>>>>>>> warning about using \d in the string.
>>>>>>>
>>>>>>> What am I missing?
>>>>>>>
>>>>>>> As far as I understand, the .error message /must/ be "-quoted.
>>>>>>
>>>>>> Indeed. But AVR is one of the few targets which enable this extra
>>>>>> warning. Why that is or whether it could be changed requires AVR
>>>>>> knowledge, which I don#t have. There's also a surprising set of
>>>>>> characters for which the warning would never appear. I don't know
>>>>>> the history of that set, but it feels pretty arbitrary.
>>>>>
>>>>> Okay, I didn't even notice that it's target specific... The only
>>>>> related place I could find is in gas/config/tc-avr.h:
>>>>>
>>>>> /* If you define this macro, GAS will warn about the use of
>>>>> ???? nonstandard escape sequences in a string.? */
>>>>> #define ONLY_STANDARD_ESCAPES
>>>>
>>>> This is it, yes.
>>>>
>>>>> Though whatever the behavior wrt. fishy escapes is, resolution
>>>>> of macro arguments should run prior to that, no?
>>>>
>>>> No. Macros are processed after the scrubber (aka "pre-processor") has
>>>> done its work.
>>>
>>> Whatever the technical limitations are; such a warning makes just no sense.
>>
>> The person who had added it likely was of a different opinion. I'm pretty sure
>> things can be improved, and feel free to send a patch, but justifying such a
>> change will likely require some archeology, not just saying "makes no sense".
> 
> What I am trying to say is that warning for an unrecognized escape
> sequence isn't very helpful when the sequence is NOT an escape sequence
> to begin with.? In the example, \data is treated as a .macro parameter,
> so there is no unknown escape sequence `\d' anywhere.

The scrubber can't know this is a macro parameter reference.

>> In particular the architecture's native assembler's behavior also needs taking
>> into account.
> 
> What you mean by "native assembler"?
> 
> avr-as is the only AVR assembler used by GCC.
> There are other assemblers like avra or avrasm2, but they are incompatible in many regards.

Well. The setting of ONLY_STANDARD_ESCAPES for AVR must have a reason. While those
other assemblers may be incompatible in various regards, maybe use of that option
was an attempt to achieve at least some compatibility? (FTAOD - I'm wildly
guessing, as I know nothing about the AVR port.)

Jan

From avr@gjlay.de  Thu Jun 11 16:14:09 2026
From: avr@gjlay.de (Georg-Johann Lay)
Date: Thu, 11 Jun 2026 18:14:09 +0200
Subject: Using .macro argument in .error message?
In-Reply-To: <1ffffdfd-51f6-4ca8-a439-bb58579bf5f1@suse.com>
References: <7bfb02e7-d3cd-4c89-a5b7-bdb7e598d7a2@gjlay.de>
 <9be37f12-b10f-4f22-8b06-3fb302252e36@suse.com>
 <f319074e-a8ed-4e0d-8326-4dab9ce178d0@gjlay.de>
 <06ccb560-58df-40ad-aa53-8ba778835c6d@suse.com>
 <09392a0b-35f8-4048-a20b-82cca728f647@gjlay.de>
 <e2e677be-e3b5-49bd-8933-2d135ab66b6b@suse.com>
 <2c27cdd3-e04e-44c6-9a4b-997afb19c768@gjlay.de>
 <1ffffdfd-51f6-4ca8-a439-bb58579bf5f1@suse.com>
Message-ID: <12be9047-9cdd-455b-878a-07ae6df39a07@gjlay.de>

Am 11.06.26 um 17:17 schrieb Jan Beulich:
> On 11.06.2026 16:54, Georg-Johann Lay wrote:
>> Am 11.06.26 um 16:18 schrieb Jan Beulich:
>>> On 11.06.2026 15:42, Georg-Johann Lay wrote:
>>>> Am 11.06.26 um 15:22 schrieb Jan Beulich:
>>>>> On 10.06.2026 11:54, Georg-Johann Lay wrote:
>>>>>> Am 10.06.26 um 11:27 schrieb Jan Beulich:
>>>>>>> On 07.06.2026 21:16, Georg-Johann Lay via Binutils wrote:
>>>>>>>> Test case err.sx:
>>>>>>>>
>>>>>>>> .macro Test data
>>>>>>>>  ??????? .if \data < 0
>>>>>>>>  ??????????? .error "value \data is negative"
>>>>>>>>  ??????? .endif
>>>>>>>> .endm
>>>>>>>>
>>>>>>>>  ??????? Test -1
>>>>>>>>
>>>>>>>> $ avr-as err.sx -v
>>>>>>>> GNU assembler version 2.45.50 (avr) using BFD version (GNU Binutils)
>>>>>>>> 2.45.50.20250718
>>>>>>>> err.sx: Assembler messages:
>>>>>>>> err.sx: Warning: unknown escape '\d' in string; ignored
>>>>>>>> err.sx:3: Error: value -1 is negative
>>>>>>>> err.sx:7:? Info: macro invoked from here
>>>>>>>>
>>>>>>>> While the printed error message is as expected, there is a spurious
>>>>>>>> warning about using \d in the string.
>>>>>>>>
>>>>>>>> What am I missing?
>>>>>>>>
>>>>>>>> As far as I understand, the .error message /must/ be "-quoted.
>>>>>>>
>>>>>>> Indeed. But AVR is one of the few targets which enable this extra
>>>>>>> warning. Why that is or whether it could be changed requires AVR
>>>>>>> knowledge, which I don#t have. There's also a surprising set of
>>>>>>> characters for which the warning would never appear. I don't know
>>>>>>> the history of that set, but it feels pretty arbitrary.
>>>>>>
>>>>>> Okay, I didn't even notice that it's target specific... The only
>>>>>> related place I could find is in gas/config/tc-avr.h:
>>>>>>
>>>>>> /* If you define this macro, GAS will warn about the use of
>>>>>>  ???? nonstandard escape sequences in a string.? */
>>>>>> #define ONLY_STANDARD_ESCAPES
>>>>>
>>>>> This is it, yes.
>>>>>
>>>>>> Though whatever the behavior wrt. fishy escapes is, resolution
>>>>>> of macro arguments should run prior to that, no?
>>>>>
>>>>> No. Macros are processed after the scrubber (aka "pre-processor") has
>>>>> done its work.
>>>>
>>>> Whatever the technical limitations are; such a warning makes just no sense.
>>>
>>> The person who had added it likely was of a different opinion. I'm pretty sure
>>> things can be improved, and feel free to send a patch, but justifying such a
>>> change will likely require some archeology, not just saying "makes no sense".
>>
>> What I am trying to say is that warning for an unrecognized escape
>> sequence isn't very helpful when the sequence is NOT an escape sequence
>> to begin with.? In the example, \data is treated as a .macro parameter,
>> so there is no unknown escape sequence `\d' anywhere.
> 
> The scrubber can't know this is a macro parameter reference.

I understand that the artifact is due to some gas internals finesse.

But that doesn't help the user's experience in any way.

And it's still fine to warn for unrecognized escapes when there /are/
unrecognized escapes, so the tc-avr.h choice makes sense IMHO.

Johann


From amodra@gmail.com  Thu Jun 11 23:47:59 2026
From: amodra@gmail.com (Alan Modra)
Date: Fri, 12 Jun 2026 09:17:59 +0930
Subject: PR 30308 yet again
Message-ID: <aitJL9_GZ0Nl0SVk@squeak.grove.modra.org>

Commit cc28c46227cd removed the symbol_resolving recursion guards in
i386_intel_simplify_symbol.  The testcases we'd considered then just
involved simple equates, handled by symbol_equated_to.  However, more
complex expressions can also cause unbounded recursion.  This patch
restores the recursion guards.

	* config/tc-i386-intel.c (i386_intel_simplify_symbol): Add
	recursion guards.
	* testsuite/gas/i386/intel-equ-loop.s,
	* testsuite/gas/i386/intel-equ-loop.l: Extend testcase.

diff --git a/gas/config/tc-i386-intel.c b/gas/config/tc-i386-intel.c
index 77b61d426bc..21d3a333182 100644
--- a/gas/config/tc-i386-intel.c
+++ b/gas/config/tc-i386-intel.c
@@ -383,6 +383,9 @@ i386_intel_simplify_register (expressionS *e)
 static symbolS *
 i386_intel_simplify_symbol (symbolS *sym)
 {
+  if (symbol_resolving_p (sym))
+    return sym;
+
   symbolS *orig = sym;
   offsetT off;
   sym = symbol_equated_to (sym, &off);
@@ -405,7 +408,9 @@ i386_intel_simplify_symbol (symbolS *sym)
   expressionS *e = symbol_get_value_expression (sym);
   expressionS exp;
   memcpy (&exp, e, sizeof exp);
+  symbol_mark_resolving (sym);
   int ret = i386_intel_simplify (&exp);
+  symbol_clear_resolving (sym);
   if (ret == 0)
     return NULL;
 
diff --git a/gas/testsuite/gas/i386/intel-equ-loop.l b/gas/testsuite/gas/i386/intel-equ-loop.l
index 76ca03a43df..90dfa9623db 100644
--- a/gas/testsuite/gas/i386/intel-equ-loop.l
+++ b/gas/testsuite/gas/i386/intel-equ-loop.l
@@ -5,4 +5,6 @@
 .*: Error: can't resolve .*
 .*: Error: symbol definition loop .*
 .*: Error: can't resolve .*
+.*: Error: symbol definition loop .*
+.*: Error: can't resolve .*
 #pass
diff --git a/gas/testsuite/gas/i386/intel-equ-loop.s b/gas/testsuite/gas/i386/intel-equ-loop.s
index bb0cce8f413..02b2d3f44ff 100644
--- a/gas/testsuite/gas/i386/intel-equ-loop.s
+++ b/gas/testsuite/gas/i386/intel-equ-loop.s
@@ -14,3 +14,7 @@
 	d = 1
 	e = 2
 	mov eax, [x]
+
+	f = g + 1
+	g = f - 1
+	mov eax, [f]

-- 
Alan Modra

From jbeulich@suse.com  Fri Jun 12 06:38:15 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 12 Jun 2026 08:38:15 +0200
Subject: Using .macro argument in .error message?
In-Reply-To: <12be9047-9cdd-455b-878a-07ae6df39a07@gjlay.de>
References: <7bfb02e7-d3cd-4c89-a5b7-bdb7e598d7a2@gjlay.de>
 <9be37f12-b10f-4f22-8b06-3fb302252e36@suse.com>
 <f319074e-a8ed-4e0d-8326-4dab9ce178d0@gjlay.de>
 <06ccb560-58df-40ad-aa53-8ba778835c6d@suse.com>
 <09392a0b-35f8-4048-a20b-82cca728f647@gjlay.de>
 <e2e677be-e3b5-49bd-8933-2d135ab66b6b@suse.com>
 <2c27cdd3-e04e-44c6-9a4b-997afb19c768@gjlay.de>
 <1ffffdfd-51f6-4ca8-a439-bb58579bf5f1@suse.com>
 <12be9047-9cdd-455b-878a-07ae6df39a07@gjlay.de>
Message-ID: <4f6dea15-c2ee-41fe-bf1d-994aec784787@suse.com>

On 11.06.2026 18:14, Georg-Johann Lay via Binutils wrote:
> Am 11.06.26 um 17:17 schrieb Jan Beulich:
>> On 11.06.2026 16:54, Georg-Johann Lay wrote:
>>> Am 11.06.26 um 16:18 schrieb Jan Beulich:
>>>> On 11.06.2026 15:42, Georg-Johann Lay wrote:
>>>>> Am 11.06.26 um 15:22 schrieb Jan Beulich:
>>>>>> On 10.06.2026 11:54, Georg-Johann Lay wrote:
>>>>>>> Am 10.06.26 um 11:27 schrieb Jan Beulich:
>>>>>>>> On 07.06.2026 21:16, Georg-Johann Lay via Binutils wrote:
>>>>>>>>> Test case err.sx:
>>>>>>>>>
>>>>>>>>> .macro Test data
>>>>>>>>>  ??????? .if \data < 0
>>>>>>>>>  ??????????? .error "value \data is negative"
>>>>>>>>>  ??????? .endif
>>>>>>>>> .endm
>>>>>>>>>
>>>>>>>>>  ??????? Test -1
>>>>>>>>>
>>>>>>>>> $ avr-as err.sx -v
>>>>>>>>> GNU assembler version 2.45.50 (avr) using BFD version (GNU Binutils)
>>>>>>>>> 2.45.50.20250718
>>>>>>>>> err.sx: Assembler messages:
>>>>>>>>> err.sx: Warning: unknown escape '\d' in string; ignored
>>>>>>>>> err.sx:3: Error: value -1 is negative
>>>>>>>>> err.sx:7:? Info: macro invoked from here
>>>>>>>>>
>>>>>>>>> While the printed error message is as expected, there is a spurious
>>>>>>>>> warning about using \d in the string.
>>>>>>>>>
>>>>>>>>> What am I missing?
>>>>>>>>>
>>>>>>>>> As far as I understand, the .error message /must/ be "-quoted.
>>>>>>>>
>>>>>>>> Indeed. But AVR is one of the few targets which enable this extra
>>>>>>>> warning. Why that is or whether it could be changed requires AVR
>>>>>>>> knowledge, which I don#t have. There's also a surprising set of
>>>>>>>> characters for which the warning would never appear. I don't know
>>>>>>>> the history of that set, but it feels pretty arbitrary.
>>>>>>>
>>>>>>> Okay, I didn't even notice that it's target specific... The only
>>>>>>> related place I could find is in gas/config/tc-avr.h:
>>>>>>>
>>>>>>> /* If you define this macro, GAS will warn about the use of
>>>>>>>  ???? nonstandard escape sequences in a string.? */
>>>>>>> #define ONLY_STANDARD_ESCAPES
>>>>>>
>>>>>> This is it, yes.
>>>>>>
>>>>>>> Though whatever the behavior wrt. fishy escapes is, resolution
>>>>>>> of macro arguments should run prior to that, no?
>>>>>>
>>>>>> No. Macros are processed after the scrubber (aka "pre-processor") has
>>>>>> done its work.
>>>>>
>>>>> Whatever the technical limitations are; such a warning makes just no sense.
>>>>
>>>> The person who had added it likely was of a different opinion. I'm pretty sure
>>>> things can be improved, and feel free to send a patch, but justifying such a
>>>> change will likely require some archeology, not just saying "makes no sense".
>>>
>>> What I am trying to say is that warning for an unrecognized escape
>>> sequence isn't very helpful when the sequence is NOT an escape sequence
>>> to begin with.? In the example, \data is treated as a .macro parameter,
>>> so there is no unknown escape sequence `\d' anywhere.
>>
>> The scrubber can't know this is a macro parameter reference.
> 
> I understand that the artifact is due to some gas internals finesse.
> 
> But that doesn't help the user's experience in any way.

Well, yes, but see below - we need a concrete proposal for how to change
that.

> And it's still fine to warn for unrecognized escapes when there /are/
> unrecognized escapes, so the tc-avr.h choice makes sense IMHO.

And how do you suggest the scrubber distinguish

	.error "value \data is negative"

used in a macro from this used outside (or even inside, but with "data"
not being a macro parameter)?

Just to mention, there more anomalies here - at least:
- For perhaps a small set of targets: While the "quotechar" static variable
  allows for string quotation by other than '"', the case labels
  circumventing the warning only (and potentially wrongly) cover '"'.
- Only octal digits (and lower case 'f' and 'b') are excluded.
To me the only viable solution looks to be to drop that warning altogether;
this would then limit reporting to next_char_of_string(). Yet then there
must have been a reason that it was added. And more targets than just AVR
would be affected. (I'll see about doing the necessary archeology. Which
may lead to nothing. In the meantime, could you add a respective entry to
our bugzilla?)

Jan

From jbeulich@suse.com  Fri Jun 12 06:42:43 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 12 Jun 2026 08:42:43 +0200
Subject: [PATCH] gas: deprecate .vtable_entry and .vtable_inherit
In-Reply-To: <20260611135013.3534885-1-rearnsha@arm.com>
References: <20260611135013.3534885-1-rearnsha@arm.com>
Message-ID: <ed214c8d-db53-44d9-b04c-84a47e26628b@suse.com>

On 11.06.2026 15:50, Richard Earnshaw wrote:
> These ELF directives were a GNU extension to support the C++ ABI
> that was in use before the introduction of the generic C++ ABI in
> GCC-3.0.  They're obsolete now and many newer targets simply
> do not provide the back-end support for them.
> 
> Flag them as deprecated in the NEWS file, and remove the documentation
> for them.  Warn (once) if the directive is used in a source file.

Okay with ...

> --- a/gas/NEWS
> +++ b/gas/NEWS
> @@ -1,4 +1,10 @@
>  -*- text -*-
> +Changes in 2.47:

... this line omitted. See e.g. commit 48df1644d270 as to when these lines
are intended to appear.

Jan

From jbeulich@suse.com  Fri Jun 12 07:12:20 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 12 Jun 2026 09:12:20 +0200
Subject: RISC-V: riscv_parse_subset_t's isa_spec is only parser input
In-Reply-To: <aiYO316-VvHZHqhT@squeak.grove.modra.org>
References: <aiYO316-VvHZHqhT@squeak.grove.modra.org>
Message-ID: <012425f0-db9c-4bc7-826a-83e2f0c5d4a4@suse.com>

On 08.06.2026 02:37, Alan Modra wrote:
> check_compiler_available fails with a ld segfault linking
> int main (void) { return 0; }
> 
> Program received signal SIGSEGV, Segmentation fault.
> 0x0000000000466a64 in riscv_parse_add_subset (rps=rps@entry=0x7fffffffd450, subset=subset@entry=0x962ca0 "zaamo", major=-1, minor=-1, implicit=implicit@entry=true) at /home/alan/src/binutils-gdb/bfd/elfxx-riscv.c:1947
> 1947	    riscv_get_default_ext_version (*rps->isa_spec, subset,
> (gdb) p rps->isa_spec
> $1 = (const enum riscv_spec_class *) 0x0
> 
> This was triggered when calling riscv_merge_attributes for crti.o
> which had
> (gdb) p ibfd->tdata.elf_obj_data->known_obj_attributes[OBJ_ATTR_PROC][Tag_RISCV_arch]
> $5 = {type = 2, i = 0, s = 0x97e4c0 "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0"}
> 
> Fix the segfault by reinstating a NULL check removed with commit
> 413cf36d8e81

Thanks for fixing this. What I'm puzzled by is that my testsuite runs didn't
hit this case.

Jan

> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1942,8 +1942,9 @@ riscv_parse_add_subset (riscv_parse_subset_t *rps,
>    int major_version = major;
>    int minor_version = minor;
>  
> -  if (major_version == RISCV_UNKNOWN_VERSION
> +  if ((major_version == RISCV_UNKNOWN_VERSION
>         || minor_version == RISCV_UNKNOWN_VERSION)
> +      && rps->isa_spec != NULL)
>      riscv_get_default_ext_version (*rps->isa_spec, subset,
>  				   &major_version, &minor_version);
>  
> 


From Richard.Earnshaw@arm.com  Fri Jun 12 09:37:20 2026
From: Richard.Earnshaw@arm.com (Richard Earnshaw)
Date: Fri, 12 Jun 2026 10:37:20 +0100
Subject: [PATCH] gas: deprecate .vtable_entry and .vtable_inherit
In-Reply-To: <ed214c8d-db53-44d9-b04c-84a47e26628b@suse.com>
References: <20260611135013.3534885-1-rearnsha@arm.com>
 <ed214c8d-db53-44d9-b04c-84a47e26628b@suse.com>
Message-ID: <9c10f429-c84a-4c40-9a93-90214b60d96b@arm.com>

On 12/06/2026 07:42, Jan Beulich wrote:
> On 11.06.2026 15:50, Richard Earnshaw wrote:
>> These ELF directives were a GNU extension to support the C++ ABI
>> that was in use before the introduction of the generic C++ ABI in
>> GCC-3.0.  They're obsolete now and many newer targets simply
>> do not provide the back-end support for them.
>>
>> Flag them as deprecated in the NEWS file, and remove the documentation
>> for them.  Warn (once) if the directive is used in a source file.
> 
> Okay with ...
> 
>> --- a/gas/NEWS
>> +++ b/gas/NEWS
>> @@ -1,4 +1,10 @@
>>   -*- text -*-
>> +Changes in 2.47:
> 
> ... this line omitted. See e.g. commit 48df1644d270 as to when these lines
> are intended to appear.
> 
> Jan

OK, thanks.  Fixed and pushed.
R.

From avr@gjlay.de  Fri Jun 12 15:16:54 2026
From: avr@gjlay.de (Georg-Johann Lay)
Date: Fri, 12 Jun 2026 17:16:54 +0200
Subject: Using .macro argument in .error message?
In-Reply-To: <4f6dea15-c2ee-41fe-bf1d-994aec784787@suse.com>
References: <7bfb02e7-d3cd-4c89-a5b7-bdb7e598d7a2@gjlay.de>
 <9be37f12-b10f-4f22-8b06-3fb302252e36@suse.com>
 <f319074e-a8ed-4e0d-8326-4dab9ce178d0@gjlay.de>
 <06ccb560-58df-40ad-aa53-8ba778835c6d@suse.com>
 <09392a0b-35f8-4048-a20b-82cca728f647@gjlay.de>
 <e2e677be-e3b5-49bd-8933-2d135ab66b6b@suse.com>
 <2c27cdd3-e04e-44c6-9a4b-997afb19c768@gjlay.de>
 <1ffffdfd-51f6-4ca8-a439-bb58579bf5f1@suse.com>
 <12be9047-9cdd-455b-878a-07ae6df39a07@gjlay.de>
 <4f6dea15-c2ee-41fe-bf1d-994aec784787@suse.com>
Message-ID: <36212f12-4630-47ee-bc9a-3153e8be4605@gjlay.de>

Am 12.06.26 um 08:38 schrieb Jan Beulich:
> On 11.06.2026 18:14, Georg-Johann Lay via Binutils wrote:
>> Am 11.06.26 um 17:17 schrieb Jan Beulich:
>>> On 11.06.2026 16:54, Georg-Johann Lay wrote:
>>>> Am 11.06.26 um 16:18 schrieb Jan Beulich:
>>>>> On 11.06.2026 15:42, Georg-Johann Lay wrote:
>>>>>> Am 11.06.26 um 15:22 schrieb Jan Beulich:
>>>>>>> On 10.06.2026 11:54, Georg-Johann Lay wrote:
>>>>>>>> Am 10.06.26 um 11:27 schrieb Jan Beulich:
>>>>>>>>> On 07.06.2026 21:16, Georg-Johann Lay via Binutils wrote:
>>>>>>>>>> Test case err.sx:
>>>>>>>>>>
>>>>>>>>>> .macro Test data
>>>>>>>>>>   ??????? .if \data < 0
>>>>>>>>>>   ??????????? .error "value \data is negative"
>>>>>>>>>>   ??????? .endif
>>>>>>>>>> .endm
>>>>>>>>>>
>>>>>>>>>>   ??????? Test -1
>>>>>>>>>>
>>>>>>>>>> $ avr-as err.sx -v
>>>>>>>>>> GNU assembler version 2.45.50 (avr) using BFD version (GNU Binutils)
>>>>>>>>>> 2.45.50.20250718
>>>>>>>>>> err.sx: Assembler messages:
>>>>>>>>>> err.sx: Warning: unknown escape '\d' in string; ignored
>>>>>>>>>> err.sx:3: Error: value -1 is negative
>>>>>>>>>> err.sx:7:? Info: macro invoked from here
>>>>>>>>>>
>>>>>>>>>> While the printed error message is as expected, there is a spurious
>>>>>>>>>> warning about using \d in the string.
>>>>>>>>>>
>>>>>>>>>> What am I missing?
>>>>>>>>>>
>>>>>>>>>> As far as I understand, the .error message /must/ be "-quoted.
>>>>>>>>>
>>>>>>>>> Indeed. But AVR is one of the few targets which enable this extra
>>>>>>>>> warning. Why that is or whether it could be changed requires AVR
>>>>>>>>> knowledge, which I don#t have. There's also a surprising set of
>>>>>>>>> characters for which the warning would never appear. I don't know
>>>>>>>>> the history of that set, but it feels pretty arbitrary.
>>>>>>>>
>>>>>>>> Okay, I didn't even notice that it's target specific... The only
>>>>>>>> related place I could find is in gas/config/tc-avr.h:
>>>>>>>>
>>>>>>>> /* If you define this macro, GAS will warn about the use of
>>>>>>>>   ???? nonstandard escape sequences in a string.? */
>>>>>>>> #define ONLY_STANDARD_ESCAPES
>>>>>>>
>>>>>>> This is it, yes.
>>>>>>>
>>>>>>>> Though whatever the behavior wrt. fishy escapes is, resolution
>>>>>>>> of macro arguments should run prior to that, no?
>>>>>>>
>>>>>>> No. Macros are processed after the scrubber (aka "pre-processor") has
>>>>>>> done its work.
>>>>>>
>>>>>> Whatever the technical limitations are; such a warning makes just no sense.
>>>>>
>>>>> The person who had added it likely was of a different opinion. I'm pretty sure
>>>>> things can be improved, and feel free to send a patch, but justifying such a
>>>>> change will likely require some archeology, not just saying "makes no sense".
>>>>
>>>> What I am trying to say is that warning for an unrecognized escape
>>>> sequence isn't very helpful when the sequence is NOT an escape sequence
>>>> to begin with.? In the example, \data is treated as a .macro parameter,
>>>> so there is no unknown escape sequence `\d' anywhere.
>>>
>>> The scrubber can't know this is a macro parameter reference.
>>
>> I understand that the artifact is due to some gas internals finesse.
>>
>> But that doesn't help the user's experience in any way.
> 
> Well, yes, but see below - we need a concrete proposal for how to change
> that.
> 
>> And it's still fine to warn for unrecognized escapes when there /are/
>> unrecognized escapes, so the tc-avr.h choice makes sense IMHO.
> 
> And how do you suggest the scrubber distinguish
> 
> 	.error "value \data is negative"
> 
> used in a macro from this used outside (or even inside, but with "data"
> not being a macro parameter)?

Wearing a user's hat:

1) A string is a string.

Just like in C, a string should be a string.  And that's actually
what the docs say on \:

| \ anything-else
|     Any other character when escaped by \ gives a warning, but
|     assembles as if the ?\? was not present. The idea is that if
|     you used an escape sequence you clearly didn?t want the literal
|     interpretation of the following character. However as has no
|     other interpretation, so as knows it is giving you the wrong
|     code and warns you of the fact.

https://sourceware.org/binutils/docs/as/Strings.html

That is, your

 > .error "value \data is negative"

should issue a warning and print "value data is negative".

CPP doesn't touch string literals in macro resolution, so when you
want a macro argument as (a part of) a string, then you have to
stringify it with #.  As far as I know, there is nothing like
stringification in .macro.  Assuming that a char like ^ works
on all platforms (or is provided by, say, tc-<target>.h),
making \data as a part of a string would then be:

.error "value "^\data" is negative"

This would resolve any ambiguities, and it would follow
GAS's own documentation.

Unfortunately, even though .macro nowhere says that param
resolution applies within strings, it mentions

| .print "\bar \baz"

in a .macro.  To make things even worse, " may have semantics that
don't don't means sting delimitation, like in

| .macro  sum from=0, to=5
|     .long  \from
|     .if    \to-\from
|         sum "(\from+1)",\to
|     .endif
| .endm


| [...] individual arguments will need to be enclosed in [...] double
| quote " characters. The latter may be the only viable option in
| certain situations, as only double quotes are actually stripped while
| establishing arguments.

And it would require that concatenating strings did work.  While

|  .string "con""cat"

works outside .macro, it throws an error within .macro.

So this is all a bit of a mess, and I don't see a way to resolve it.
Lest alone considering compatibility with previous versions of Binutils.

Johann

> Just to mention, there more anomalies here - at least:
> - For perhaps a small set of targets: While the "quotechar" static variable
>    allows for string quotation by other than '"', the case labels
>    circumventing the warning only (and potentially wrongly) cover '"'.
> - Only octal digits (and lower case 'f' and 'b') are excluded.
> To me the only viable solution looks to be to drop that warning altogether;
> this would then limit reporting to next_char_of_string(). Yet then there
> must have been a reason that it was added. And more targets than just AVR
> would be affected. (I'll see about doing the necessary archeology. Which
> may lead to nothing. In the meantime, could you add a respective entry to
> our bugzilla?)
> 
> Jan


From dje.gcc@gmail.com  Fri Jun 12 19:24:49 2026
From: dje.gcc@gmail.com (David Edelsohn)
Date: Fri, 12 Jun 2026 15:24:49 -0400
Subject: =?UTF-8?Q?Nominations_for_Anthropic=E2=80=99s_Claude_for_Open_Source?=
 =?UTF-8?Q?_program?=
Message-ID: <CAGWvnykaUiiAPY8sMFAGu83ObWzChqp1Jk8BDwjy7tFedkd0Bg@mail.gmail.com>

Developers,

Anthropic is generously offering 6 months of Claude Max 20x to Free and Open
Source Software projects to support the FOSS ecosystem. These tools can be
incredibly helpful with reviewing upstream code, evaluating the conformance
of
a particular interface to a standard, or just for your own learning and
exploring the implementation of the project or subsystem.

If you are an established, active contributor to the GNU Toolchain and are
interested in having access to Claude Max 20x under Anthropic?s Claude for
Open
Source program, please respond to this email thread with a short
description of
how you would utilize the access and the potential impact on the GNU
Toolchain.
The program's slots are limited and Carlos O'Donell and I plan to review the
proposals. Please keep in mind that these are individual grants from
Anthropic
to you personally. If you are approved you?ll get an email from Anthropic
with
further instructions.

While the current GNU Project policy is not to accept LLM-generated content
in
the projects, that still leaves other uses like bug triage, patch review,
and
research as ways to use these tools.

Cheers, David

P.S. This is not an endorsement of Anthropic, Claude or LLMs. We dislike
having to say it, but please don?t use this thread as a platform to express
your personal opinions about the companies or about AI?s impact on the
world.
-------------- next part --------------
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From andrew.pinski@oss.qualcomm.com  Fri Jun 12 19:34:12 2026
From: andrew.pinski@oss.qualcomm.com (Andrew Pinski)
Date: Fri, 12 Jun 2026 12:34:12 -0700
Subject: =?UTF-8?Q?Re=3A_Nominations_for_Anthropic=E2=80=99s_Claude_for_Open_So?=
 =?UTF-8?Q?urce_program?=
In-Reply-To: <CAGWvnykaUiiAPY8sMFAGu83ObWzChqp1Jk8BDwjy7tFedkd0Bg@mail.gmail.com>
References: <CAGWvnykaUiiAPY8sMFAGu83ObWzChqp1Jk8BDwjy7tFedkd0Bg@mail.gmail.com>
Message-ID: <CALvbMcBvEN3jkfBVnXHNu_C538jFdC8vLTz7ZNkNDwc=vvP0mw@mail.gmail.com>

On Fri, Jun 12, 2026 at 12:25?PM David Edelsohn via Gcc <gcc@gcc.gnu.org> wrote:
>
> Developers,
>
> Anthropic is generously offering 6 months of Claude Max 20x to Free and Open
> Source Software projects to support the FOSS ecosystem. These tools can be
> incredibly helpful with reviewing upstream code, evaluating the conformance
> of
> a particular interface to a standard, or just for your own learning and
> exploring the implementation of the project or subsystem.
>
> If you are an established, active contributor to the GNU Toolchain and are
> interested in having access to Claude Max 20x under Anthropic?s Claude for
> Open
> Source program, please respond to this email thread with a short
> description of
> how you would utilize the access and the potential impact on the GNU
> Toolchain.
> The program's slots are limited and Carlos O'Donell and I plan to review the
> proposals. Please keep in mind that these are individual grants from
> Anthropic
> to you personally. If you are approved you?ll get an email from Anthropic
> with
> further instructions.
>
> While the current GNU Project policy is not to accept LLM-generated content
> in
> the projects, that still leaves other uses like bug triage, patch review,
> and
> research as ways to use these tools.
>
> Cheers, David
>
> P.S. This is not an endorsement of Anthropic, Claude or LLMs. We dislike
> having to say it, but please don?t use this thread as a platform to express
> your personal opinions about the companies or about AI?s impact on the
> world.

Note coverity has been offering the free (for almost lifetime rather
than just 6months). For use of their static analysis tool online.
Can we please keep this kind of emails out of the development mailing
lists? Static analysis is more useful than LLMs and their impact is
free.

From i@maskray.me  Sat Jun 13 04:49:12 2026
From: i@maskray.me (Fangrui Song)
Date: Fri, 12 Jun 2026 21:49:12 -0700
Subject: [PATCH v3] gas: add --reloc-section-sym={all, internal, none}
 option for ELF
In-Reply-To: <CAN30aBE8hRqOUoo5zPNkcnSuPxy5Ox1yL5NN4CeOLiUu3vmMtA@mail.gmail.com>
References: <20260228061955.23818-1-i@maskray.me>
 <88097170-c97c-4388-81bc-a2b5e53a89ef@suse.com>
 <CAN30aBE8hRqOUoo5zPNkcnSuPxy5Ox1yL5NN4CeOLiUu3vmMtA@mail.gmail.com>
Message-ID: <CAN30aBG7V0wmurYvQqHOi2GOuyuit9shhdb6uX=GJgNMAbm1pg@mail.gmail.com>

On Sat, May 16, 2026 at 12:38?AM Fangrui Song <i@maskray.me> wrote:
>
> On Fri, May 15, 2026 at 5:05?AM Jan Beulich <jbeulich@suse.com> wrote:
> >
> > On 28.02.2026 07:19, Fangrui Song wrote:
> > > From: Fangrui Song <maskray@sourceware.org>
> > >
> > > When generating relocations for non-ifunc local symbols that satisfies
> > > several conditions, GAS converts them to reference the section symbol
> > > (STT_SECTION) instead, folding the original symbol's offset into the
> > > addend.  This allows the original local symbol to be omitted from
> > > .symtab, but the STT_SECTION symbol itself must be present, so the
> > > conversion saves .symtab entries only when a section has more than one
> > > local symbol referenced by relocations.
> > >
> > > Add --reloc-section-sym to control this conversion:
> > >
> > > - all (default): convert all eligible local symbols
> > > - internal: only convert compiler-generated locals (.L prefix)
> > > - none: never convert; keep all symbols as-is in relocations
> > >
> > > This is useful for debugging and for tools that benefit from preserved
> > > symbol names.
> > >
> > > PR gas/33885
> >
> > Okay, provided you checked the new tests pass for a wide range of targets.
> > In particular ...
>
> Thanks for taking a look.
>
> > > --- /dev/null
> > > +++ b/gas/testsuite/gas/elf/reloc-section-sym-all.d
> > > @@ -0,0 +1,12 @@
> > > +#source: reloc-section-sym.s
> > > +#as: --reloc-section-sym=all
> > > +#objdump: -rsj .data
> > > +#name: reloc-section-sym=all
> > > +
> > > +.*: +file format .*
> > > +
> > > +RELOCATION RECORDS FOR \[\.data\]:
> > > +OFFSET +TYPE +VALUE
> > > +0*0 [^ ]+ +\.text.*
> > > +0*4 [^ ]+ +\.text.*
> > > +#pass
> > > --- /dev/null
> > > +++ b/gas/testsuite/gas/elf/reloc-section-sym-internal.d
> > > @@ -0,0 +1,12 @@
> > > +#source: reloc-section-sym.s
> > > +#as: --reloc-section-sym=internal
> > > +#objdump: -rsj .data
> > > +#name: reloc-section-sym=internal
> > > +
> > > +.*: +file format .*
> > > +
> > > +RELOCATION RECORDS FOR \[\.data\]:
> > > +OFFSET +TYPE +VALUE
> > > +0*0 [^ ]+ +local.*
> > > +0*4 [^ ]+ +\.text.*
> > > +#pass
> > > --- /dev/null
> > > +++ b/gas/testsuite/gas/elf/reloc-section-sym-none.d
> > > @@ -0,0 +1,12 @@
> > > +#source: reloc-section-sym.s
> > > +#as: --reloc-section-sym=none
> > > +#objdump: -rsj .data
> > > +#name: reloc-section-sym=none
> > > +
> > > +.*: +file format .*
> > > +
> > > +RELOCATION RECORDS FOR \[\.data\]:
> > > +OFFSET +TYPE +VALUE
> > > +0*0 [^ ]+ +local.*
> > > +0*4 [^ ]+ +\.Ltemp.*
> > > +#pass
> > > --- /dev/null
> > > +++ b/gas/testsuite/gas/elf/reloc-section-sym.s
> > > @@ -0,0 +1,9 @@
> > > +     .text
> > > +local:
> > > +     .byte 0
> > > +.Ltemp:
> > > +     .byte 0
> > > +
> > > +     .data
> > > +     .long local + 16
> > > +     .long .Ltemp + 16
> >
> > ... here I wonder whether .dc.a wouldn't be the more portable directive to
> > use when it comes to relocations.
>
> With .long the relocation offset is target-agnostic. section5.s uses
> .long relocations as well, so I think .long relocations is portable.
>
> > > --- /dev/null
> > > +++ b/gas/testsuite/gas/i386/reloc-section-sym.s
> > > @@ -0,0 +1,14 @@
> > > +     .text
> > > +     nop
> > > +local:
> > > +     .byte 0
> >
> > Better "nop" here as well, just like ...
>
> I think `.byte 0` doesn't hurt here...
> .byte 0/int3/nop is to introduce some nuance. While it probably
> doesn't matter for this particular test, it helps in other tests when
> using objdump -s.
>
> > > +.Ltemp:
> > > +     nop
> >
> > ... you have it here?
> >
> > Which further reminds me to ask why in the generic test you don't use .nop
> > in favor of .byte.
> >
> > Jan
>
> I didn't realize that .nop is portable. However, .nop introduces
> target-dependent offsets, which is exactly what we want to avoid in a
> generic test.
> Sticking to explicit offsets like 0/4/8 IMHO is clearer than using .*

Hi Jan, are you happy with the patch as is ? :)

From amodra@gmail.com  Sat Jun 13 06:48:25 2026
From: amodra@gmail.com (Alan Modra)
Date: Sat, 13 Jun 2026 16:18:25 +0930
Subject: check bfd_alloc/bfd_malloc return in elflink.c
Message-ID: <aiz9Oe59t8FzY7Jx@squeak.grove.modra.org>

Add checks in a couple of places for a non-NULL return.  While we're
at it, don't use sprintf to concatenate two strings.

	* elflink.c (bfd_elf_link_record_dynamic_symbol): Check than
	bfd_malloc returns non-NULL.
	(get_dynamic_reloc_section_name): Similarly check bfd_alloc.
	Replace sprintf with two memcpys.  Remove old_name NULL check.

diff --git a/bfd/elflink.c b/bfd/elflink.c
index 3c4332b549a..290fc5f2031 100644
--- a/bfd/elflink.c
+++ b/bfd/elflink.c
@@ -653,6 +653,8 @@ bfd_elf_link_record_dynamic_symbol (struct bfd_link_info *info,
       if (p != NULL)
 	{
 	  unversioned_name = bfd_malloc (p - name + 1);
+	  if (unversioned_name == NULL)
+	    return false;
 	  memcpy (unversioned_name, name, p - name);
 	  unversioned_name[p - name] = 0;
 	  name = unversioned_name;
@@ -15569,16 +15571,16 @@ get_dynamic_reloc_section_name (bfd *       abfd,
 				asection *  sec,
 				bool is_rela)
 {
-  char *name;
-  const char *old_name = bfd_section_name (sec);
   const char *prefix = is_rela ? ".rela" : ".rel";
-
-  if (old_name == NULL)
+  size_t plen = is_rela ? 5 : 4;
+  const char *old_name = bfd_section_name (sec);
+  size_t nlen = strlen (old_name);
+  char *name = bfd_alloc (abfd, plen + nlen + 1);
+  if (name == NULL)
     return NULL;
 
-  name = bfd_alloc (abfd, strlen (prefix) + strlen (old_name) + 1);
-  sprintf (name, "%s%s", prefix, old_name);
-
+  memcpy (name, prefix, plen);
+  memcpy (name + plen, old_name, nlen + 1);
   return name;
 }
 

-- 
Alan Modra

From amodra@gmail.com  Sat Jun 13 06:48:54 2026
From: amodra@gmail.com (Alan Modra)
Date: Sat, 13 Jun 2026 16:18:54 +0930
Subject: oss-fuzz: vms-alpha segfault in image_write_section
Message-ID: <aiz9Vn-M-AAD-CQo@squeak.grove.modra.org>

Yet another case where a fuzzed object file triggers a crash in the
vms-alpha support.

	* vms-alpha.c (image_write_section): Don't segfault on NULL
	image_section.

diff --git a/bfd/vms-alpha.c b/bfd/vms-alpha.c
index 8454ab6ebdc..24b05f90bea 100644
--- a/bfd/vms-alpha.c
+++ b/bfd/vms-alpha.c
@@ -1603,7 +1603,8 @@ image_write_section (bfd *abfd)
 {
   asection *sec = PRIV (image_section);
 
-  if ((sec->flags & SEC_IN_MEMORY) != 0 && sec->contents == NULL)
+  if (sec == NULL
+      || ((sec->flags & SEC_IN_MEMORY) != 0 && sec->contents == NULL))
     return NULL;
   return sec;
 }

-- 
Alan Modra

From amodra@gmail.com  Sat Jun 13 07:09:48 2026
From: amodra@gmail.com (Alan Modra)
Date: Sat, 13 Jun 2026 16:39:48 +0930
Subject: RISC-V: riscv_parse_subset_t's isa_spec is only parser input
In-Reply-To: <012425f0-db9c-4bc7-826a-83e2f0c5d4a4@suse.com>
References: <aiYO316-VvHZHqhT@squeak.grove.modra.org>
 <012425f0-db9c-4bc7-826a-83e2f0c5d4a4@suse.com>
Message-ID: <ai0CPChJqw1dATd5@squeak.grove.modra.org>

On Fri, Jun 12, 2026 at 09:12:20AM +0200, Jan Beulich wrote:
> On 08.06.2026 02:37, Alan Modra wrote:
> > check_compiler_available fails with a ld segfault linking
> > int main (void) { return 0; }
> > 
> > Program received signal SIGSEGV, Segmentation fault.
> > 0x0000000000466a64 in riscv_parse_add_subset (rps=rps@entry=0x7fffffffd450, subset=subset@entry=0x962ca0 "zaamo", major=-1, minor=-1, implicit=implicit@entry=true) at /home/alan/src/binutils-gdb/bfd/elfxx-riscv.c:1947
> > 1947	    riscv_get_default_ext_version (*rps->isa_spec, subset,
> > (gdb) p rps->isa_spec
> > $1 = (const enum riscv_spec_class *) 0x0
> > 
> > This was triggered when calling riscv_merge_attributes for crti.o
> > which had
> > (gdb) p ibfd->tdata.elf_obj_data->known_obj_attributes[OBJ_ATTR_PROC][Tag_RISCV_arch]
> > $5 = {type = 2, i = 0, s = 0x97e4c0 "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0"}
> > 
> > Fix the segfault by reinstating a NULL check removed with commit
> > 413cf36d8e81
> 
> Thanks for fixing this. What I'm puzzled by is that my testsuite runs didn't
> hit this case.

You'd need to have a riscv64-linux-gnu toolchain installed, with a
glibc that happened to be built with the triggering attribute.  And
you'd have to notice a silent segfault (apart from a log message)
that disabled all riscv64-linux-gnu tests using the target compiler.

> Jan
> 
> > --- a/bfd/elfxx-riscv.c
> > +++ b/bfd/elfxx-riscv.c
> > @@ -1942,8 +1942,9 @@ riscv_parse_add_subset (riscv_parse_subset_t *rps,
> >    int major_version = major;
> >    int minor_version = minor;
> >  
> > -  if (major_version == RISCV_UNKNOWN_VERSION
> > +  if ((major_version == RISCV_UNKNOWN_VERSION
> >         || minor_version == RISCV_UNKNOWN_VERSION)
> > +      && rps->isa_spec != NULL)
> >      riscv_get_default_ext_version (*rps->isa_spec, subset,
> >  				   &major_version, &minor_version);
> >  
> > 

-- 
Alan Modra

From builder@sourceware.org  Sat Jun 13 07:12:44 2026
From: builder@sourceware.org (builder@sourceware.org)
Date: Sat, 13 Jun 2026 07:12:44 +0000
Subject: =?utf-8?q?=E2=98=BA_Buildbot_=28Sourceware=29=3A_binutils-gdb_-_build_successful_=28master=29?=
Message-ID: <20260613071244.922EF4BA543C@sourceware.org>

A restored build has been detected on builder binutils-solaris11-i386 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/364/builds/23

Build state: build successful
Revision: e0fe0e3abde305a34de82134b7d8a7fa153d1897
Worker: solaris11-amd64
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>, Andrew Burgess <aburgess@redhat.com>, Etienne Brateau <etienne.brateau@gmail.com>, GDB Administrator <gdbadmin@sourceware.org>, Gopi Kumar Bulusu <gopi@sankhya.com>, Jon Turney <jon.turney@dronecode.org.uk>, Lancelot SIX <lancelot.six@amd.com>, Markus Metzger <markus.t.metzger@intel.com>, Matthieu Longo <matthieu.longo@arm.com>, Pedro Alves <pedro@palves.net>, Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>, Richard Earnshaw <rearnsha@arm.com>, S?bastien Darche <sdarche@efficios.com>, Tom Tromey <tromey@adacore.com>, Tom de Vries <tdevries@suse.de>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/3/logs/config_log

- 4: make ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/4/logs/stdio
        - warnings (33): https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/4/logs/warnings__33_

- 5: make check ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/5/logs/stdio
        - ld.sum: https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/5/logs/ld_sum
        - ld.log: https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/5/logs/ld_log
        - gas.sum: https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/5/logs/gas_sum
        - gas.log: https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/5/logs/gas_log
        - gprof.log: https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/5/logs/gprof_log
        - binutils.sum: https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/5/logs/binutils_sum
        - binutils.log: https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/5/logs/binutils_log
        - libsframe.sum: https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/5/logs/libsframe_sum
        - libsframe.log: https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/5/logs/libsframe_log
        - libctf.sum: https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/5/logs/libctf_sum
        - libctf.log: https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/5/logs/libctf_log
        - warnings (15): https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/5/logs/warnings__15_

- 6: prep ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/6/logs/stdio

- 7: collect system versions ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/7/logs/stdio

- 8: fetch .bunsen.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/8/logs/stdio

- 9: build bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/9/logs/stdio

- 10: fetch bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/10/logs/stdio

- 11: unpack bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/11/logs/stdio

- 12: pass .bunsen.source.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/12/logs/stdio

- 13: upload to bunsen ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/13/logs/stdio

- 14: clean up ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/14/logs/stdio

- 15: rm -rf binutils-build_1 ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/364/builds/23/steps/15/logs/stdio


From avr@gjlay.de  Sun Jun 14 15:31:27 2026
From: avr@gjlay.de (Georg-Johann Lay)
Date: Sun, 14 Jun 2026 17:31:27 +0200
Subject: [patch, avr, v2] RFC: Support .gnu_attribute 4
 (Tag_GNU_AVR_VTABLE_AS) for vtable address spaces
Message-ID: <6ec995a2-ee57-46c8-af8e-f5389e812fca@gjlay.de>

This is an updated version of the .gnu_attribute Tag_GNU_AVR_VTABLE_AS
proposal

https://sourceware.org/pipermail/binutils/2026-June/149591.html

 > The expected, upcoming support for ISO/IEC TR 18037 "Embedded C"
 > named address spaces in G++ would allow to put C++ virtual tables
 > into such address spaces, see https://gcc.gnu.org/PR69549
 >
 > Currently, vtables are in the generic address space, which wastes
 > RAM on cores that locate .rodata in RAM.
 >
 > Any change of vtables' address space is an ABI change, and
 > therefore it would be nice to have a feature that checks that
 > all object files linked into an app are using the same vtable AS.
 >
 > The patch below introduces .gnu_attribute 4 (Tag_GNU_AVR_VTABLE_AS).
 >
 > This mail is a request for a pre-approval of the patch.
 >
 > I don't intend to apply it until it is clear that it's really
 > of any use and not dead code.  Sadly, PR69549 is only progressing
 > at a glacial pace, so it may take yet another 10 year before
 > G++ can handle named address spaces --- or it may never learn it.
 >
 > The patch is for trunk.

The difference is that GAS doesn't error on unknown attribute values,
preparing for possible future extensions.

Johann

--

AVR: Add support for .gnu_attribute 4 (Tag_GNU_AVR_VTABLE_AS).

The expected, upcoming support for ISO/IEC TR 18037 "Embedded C"
named address spaces in G++ would allow to put C++ virtual tables
into such address spaces, see https://gcc.gnu.org/PR69549

The current address space used for vtables is the generic one,
which means that RAM is wasted on machines where .rodata is
located in RAM.

Named address spaces in G++ would allow users to chose an address space
that suits their requirements, e.g. by means of a new command-line
option and GCC hooks like TARGET_ADDR_SPACE_FOR_ARTIFICIAL_RODATA.

However, in contrast to current user-selectable address spaces,
placing vtables in a different address space is an ABI change,
so that a means to detect ABI violations is highly appreciated.

The feature of choice is .gnu_attribute 4 (Tag_GNU_AVR_VTABLE_AS)
which would tag an object file with one of the following values:

0 (Val_GNU_AVR_VTABLE_NONE) for files that neither define nor access 
vtables.
1 (Val_GNU_AVR_VTABLE_RAM) for files that use the generic address space.
2 (Val_GNU_AVR_VTABLE_FLASH) the file uses the 16-bit address space __flash.
3 (Val_GNU_AVR_VTABLE_FLASH1) the file uses the 16-bit address space 
__flash1.
4 (Val_GNU_AVR_VTABLE_FLASH2) the file uses the 16-bit address space 
__flash2.
5 (Val_GNU_AVR_VTABLE_FLASH3) the file uses the 16-bit address space 
__flash3.
6 (Val_GNU_AVR_VTABLE_FLASH4) the file uses the 16-bit address space 
__flash4.
7 (Val_GNU_AVR_VTABLE_FLASH5) the file uses the 16-bit address space 
__flash5.
8 (Val_GNU_AVR_VTABLE_FLASHX) the file uses the 24-bit address space 
__flashx.

- A tag value of zero is compatible with all other tag values.

- Two non-zero tag values are compatible iff they are the same.

Unknown tag values are silently accepted an treated just like the values
above so as to allow for compatibility with future extensions.

include/
	* elf/avr.h (libiberty.h): Include for ARRAY_SIZE.
	(Tag_GNU_AVR_VTABLE_AS = 4): New enum.
	(Val_GNU_AVR_VTABLE_NONE, Val_GNU_AVR_VTABLE_RAM)
	(Val_GNU_AVR_VTABLE_FLASH, Val_GNU_AVR_VTABLE_FLASH1)
	(Val_GNU_AVR_VTABLE_FLASH2, Val_GNU_AVR_VTABLE_FLASH3)
	(Val_GNU_AVR_VTABLE_FLASH4, Val_GNU_AVR_VTABLE_FLASH5)
	(Val_GNU_AVR_VTABLE_FLASHX, Val_GNU_AVR_VTABLE_Sentinel): New
	enum values for Tag_GNU_AVR_VTABLE_AS.
	(avr_tag_vtable_as_name): New static function.

bfd/
	* elf32-avr.h (bfd_avr_elf_merge_private_bfd_data): New proto.
	* elf32-avr.c (libiberty.h): Include for ARRAY_SIZE.
	(avr_elf_merge_obj_attributes): New static function.
	(bfd_avr_elf_merge_private_bfd_data): New function that calls it.
	(bfd_elf32_bfd_merge_private_bfd_data): Define to
	bfd_avr_elf_merge_private_bfd_data.

gas/
	* doc/as.texi (GNU Object Attributes) [AVR Attributes]: New subsection.

ld/
	* testsuite/ld-avr/attr-gnu-4-1.s: New source.
	* testsuite/ld-avr/attr-gnu-4-2.s: New source.
	* testsuite/ld-avr/attr-gnu-4-1.d: New test.
	* testsuite/ld-avr/attr-gnu-4-2.d: New test.
	* testsuite/ld-avr/attr-gnu-4-1_2.d: New test.

binutils/
	* readelf.c (display_avr_gnu_attribute): New static function.
	(process_arch_specific) <EM_AVR>: Call process_attributes
	with display_avr_gnu_attribute as a callback.

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From mark@klomp.org  Sun Jun 14 22:59:10 2026
From: mark@klomp.org (Mark Wielaard)
Date: Mon, 15 Jun 2026 00:59:10 +0200
Subject: Sourceware budget and funding 2026/2027, Fri 12, 15:00 UTC
In-Reply-To: <20260611103835.GH14081@gnu.wildebeest.org>
References: <20260611103835.GH14081@gnu.wildebeest.org>
Message-ID: <20260614225910.GA14303@gnu.wildebeest.org>

Hi all,

On Thu, Jun 11, 2026 at 12:38:35PM +0200, Mark Wielaard wrote:
> Based on last months budget discussions and last years financial
> overview the Sourceware Project Leadership Committee wrote up an
> ambitious budget and funding proposal for 2026/2027, see below. Lets
> discuss if this matches community expectations and what the most
> effective way is to drive this fundraising campaign.

For those that couldn't attend here is a summary.

It looked liked emails with lots of dollar signs and asking for money
go into spam filters, so not everybody had seen the Sourceware PLC
financials overview. It is also here now:
https://sourceware.org/financials.html

The PLC document is based on the financials from 2025/2026 and the
looking forward/looking backward discussions last month:
https://inbox.sourceware.org/20260516203206.GR1219@gnu.wildebeest.org/
https://inbox.sourceware.org/20260510223754.GR1219@gnu.wildebeest.org/

Switching from metal to people is a good funding goal. Especially
dodging RAM prices right now :)

There were some worries that there aren't enough "tasks" listed for
corporations to fund explicitly. But ideally sponsorships are not
targetted, they are general funding for the project (to make managing
the money better and easier for the project). But if there was
specific contract work that would be relevant for companies, we could
consider that separately.

We currently have items listed per funding "source" and only list the
tasks we believe we can do this year. But it would be good to list all
the work we want to get done (over multiple years). We do list more
under https://sourceware.org/sourceware-security-vision.html#plans
Modernizing account processes, Release upload process improvements,
Hardware keys, Security audit. It might be useful to just list them
all.

Question about spelling out the financial assumptions. For those
forgejo additions we assume $60/hour (total budget for a week work),
for upgrade/migration/automation tickets, we assume $80/hour (total
budget 3 to 6 days of work), for the junior sysadmin (at the end) we
assume $40/hour (total budget for 2.5 days for 6 to 12 months). Many
of the SFC contractors are around $40/hour, we have to do special
approvals if it's over $100/hour. People in north america/australia
are often about $75/hour. It is normal for people to charge much lower
rates for nonprofits.

We might want to consider corporate sponsorship "levels". the
Reproducible Builds team (who is another SFC project) uses
that. https://reproducible-builds.org/donate/#benefits-of-sponsorship
https://reproducible-builds.org/who/sponsors/
Then a corporation would fund for a specific "level" and not for a
specific task/contract.

In general people seem to agree you have to start somewhere and the
current estimates are OK, but on the low end. We can be even more
ambitious, ask for more than what we currently believe we can spend in
a year and see if some individuals, corporatations or grant maker
surprises us.

We currently have a healthy reserve. We could operate for one or two
years without any additional income. And for our minimal baseline we
just depend on individual sponsors and some corporate in-kind
(hosting) support.

What is next?

- Create a new sponsors page that lists incentives, levels and "bonus"
  targets.
- Link it all together with the financials and donate pages.
- Find Sourceware Ambassadors to drive the fundraising campaign.

From jbeulich@suse.com  Mon Jun 15 06:44:47 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Mon, 15 Jun 2026 08:44:47 +0200
Subject: [PATCH v3] gas: add --reloc-section-sym={all, internal, none}
 option for ELF
In-Reply-To: <CAN30aBG7V0wmurYvQqHOi2GOuyuit9shhdb6uX=GJgNMAbm1pg@mail.gmail.com>
References: <20260228061955.23818-1-i@maskray.me>
 <88097170-c97c-4388-81bc-a2b5e53a89ef@suse.com>
 <CAN30aBE8hRqOUoo5zPNkcnSuPxy5Ox1yL5NN4CeOLiUu3vmMtA@mail.gmail.com>
 <CAN30aBG7V0wmurYvQqHOi2GOuyuit9shhdb6uX=GJgNMAbm1pg@mail.gmail.com>
Message-ID: <5935afac-a2f5-405c-83a6-eff4bddd69f8@suse.com>

On 13.06.2026 06:49, Fangrui Song wrote:
> On Sat, May 16, 2026 at 12:38?AM Fangrui Song <i@maskray.me> wrote:
>> On Fri, May 15, 2026 at 5:05?AM Jan Beulich <jbeulich@suse.com> wrote:
>>> On 28.02.2026 07:19, Fangrui Song wrote:
>>>> From: Fangrui Song <maskray@sourceware.org>
>>>>
>>>> When generating relocations for non-ifunc local symbols that satisfies
>>>> several conditions, GAS converts them to reference the section symbol
>>>> (STT_SECTION) instead, folding the original symbol's offset into the
>>>> addend.  This allows the original local symbol to be omitted from
>>>> .symtab, but the STT_SECTION symbol itself must be present, so the
>>>> conversion saves .symtab entries only when a section has more than one
>>>> local symbol referenced by relocations.
>>>>
>>>> Add --reloc-section-sym to control this conversion:
>>>>
>>>> - all (default): convert all eligible local symbols
>>>> - internal: only convert compiler-generated locals (.L prefix)
>>>> - none: never convert; keep all symbols as-is in relocations
>>>>
>>>> This is useful for debugging and for tools that benefit from preserved
>>>> symbol names.
>>>>
>>>> PR gas/33885
>>>
>>> Okay, provided you checked the new tests pass for a wide range of targets.

This remains as a prereq to approval.

>>> In particular ...
>>
>> Thanks for taking a look.
>>
>>>> --- /dev/null
>>>> +++ b/gas/testsuite/gas/elf/reloc-section-sym-all.d
>>>> @@ -0,0 +1,12 @@
>>>> +#source: reloc-section-sym.s
>>>> +#as: --reloc-section-sym=all
>>>> +#objdump: -rsj .data
>>>> +#name: reloc-section-sym=all
>>>> +
>>>> +.*: +file format .*
>>>> +
>>>> +RELOCATION RECORDS FOR \[\.data\]:
>>>> +OFFSET +TYPE +VALUE
>>>> +0*0 [^ ]+ +\.text.*
>>>> +0*4 [^ ]+ +\.text.*
>>>> +#pass
>>>> --- /dev/null
>>>> +++ b/gas/testsuite/gas/elf/reloc-section-sym-internal.d
>>>> @@ -0,0 +1,12 @@
>>>> +#source: reloc-section-sym.s
>>>> +#as: --reloc-section-sym=internal
>>>> +#objdump: -rsj .data
>>>> +#name: reloc-section-sym=internal
>>>> +
>>>> +.*: +file format .*
>>>> +
>>>> +RELOCATION RECORDS FOR \[\.data\]:
>>>> +OFFSET +TYPE +VALUE
>>>> +0*0 [^ ]+ +local.*
>>>> +0*4 [^ ]+ +\.text.*
>>>> +#pass
>>>> --- /dev/null
>>>> +++ b/gas/testsuite/gas/elf/reloc-section-sym-none.d
>>>> @@ -0,0 +1,12 @@
>>>> +#source: reloc-section-sym.s
>>>> +#as: --reloc-section-sym=none
>>>> +#objdump: -rsj .data
>>>> +#name: reloc-section-sym=none
>>>> +
>>>> +.*: +file format .*
>>>> +
>>>> +RELOCATION RECORDS FOR \[\.data\]:
>>>> +OFFSET +TYPE +VALUE
>>>> +0*0 [^ ]+ +local.*
>>>> +0*4 [^ ]+ +\.Ltemp.*
>>>> +#pass
>>>> --- /dev/null
>>>> +++ b/gas/testsuite/gas/elf/reloc-section-sym.s
>>>> @@ -0,0 +1,9 @@
>>>> +     .text
>>>> +local:
>>>> +     .byte 0
>>>> +.Ltemp:
>>>> +     .byte 0
>>>> +
>>>> +     .data
>>>> +     .long local + 16
>>>> +     .long .Ltemp + 16
>>>
>>> ... here I wonder whether .dc.a wouldn't be the more portable directive to
>>> use when it comes to relocations.
>>
>> With .long the relocation offset is target-agnostic. section5.s uses
>> .long relocations as well, so I think .long relocations is portable.
>>
>>>> --- /dev/null
>>>> +++ b/gas/testsuite/gas/i386/reloc-section-sym.s
>>>> @@ -0,0 +1,14 @@
>>>> +     .text
>>>> +     nop
>>>> +local:
>>>> +     .byte 0
>>>
>>> Better "nop" here as well, just like ...
>>
>> I think `.byte 0` doesn't hurt here...
>> .byte 0/int3/nop is to introduce some nuance. While it probably
>> doesn't matter for this particular test, it helps in other tests when
>> using objdump -s.
>>
>>>> +.Ltemp:
>>>> +     nop
>>>
>>> ... you have it here?
>>>
>>> Which further reminds me to ask why in the generic test you don't use .nop
>>> in favor of .byte.
>>>
>>> Jan
>>
>> I didn't realize that .nop is portable. However, .nop introduces
>> target-dependent offsets, which is exactly what we want to avoid in a
>> generic test.
>> Sticking to explicit offsets like 0/4/8 IMHO is clearer than using .*
> 
> Hi Jan, are you happy with the patch as is ? :)

Not really, no. .byte in .text isn't very nice. Can't you use .bss in place
of .text, if you want to avoid using .nop?`

Jan

From gnutoolsweekly@gmail.com  Mon Jun 15 07:21:50 2026
From: gnutoolsweekly@gmail.com (GNU Tools weekly)
Date: Mon, 15 Jun 2026 00:21:50 -0700
Subject: GNU Tools Weekly News Week 42 (June 14, 2026)
In-Reply-To: <CAHt=NyMQqSikhJAd2inR4X8=D-1pWZwxGJtxwb3GwhfwuuWLvg@mail.gmail.com>
References: <CAHt=NyPpC47e6400=ZxqwJ5W5B2ABmhUZk+SWsRKSTdxVu4SVA@mail.gmail.com>
 <CAHt=NyPnAeEzUoCVUFVDErpM7C+ieaNti8HxSwi-nJD-anSBuQ@mail.gmail.com>
 <CAHt=NyOxTmdRe6oysAQJxoCA=qAwSKZTOAe4NQn1ZMYF9OhmoQ@mail.gmail.com>
 <CAHt=NyNKa=eQ8ytymevK-r_Zz5p_DhzOzpYC35YLdqzJ4XhgMQ@mail.gmail.com>
 <CAHt=NyNXXPShoxuBUdL5zK_XMU4tkjnuf00C_3Sgor9pOQEiVA@mail.gmail.com>
 <CAHt=NyO8g64b7LBuAOUM2m5E_ruuKV8osytFvseDUz--XaHNjA@mail.gmail.com>
 <CAHt=NyMASMc-5h9zYqH1L3Scbx2oJ6i-RzAS7Eb-WPbQqCmyuQ@mail.gmail.com>
 <CAHt=NyPaAZhqc3WSi1_WMBr=uZmZL=Jc2jwgQibeR1n6xwqyKA@mail.gmail.com>
 <CAHt=NyPntsf9FjtMa2p+vFEDPMkq62J5R4fzK7+qbSDtPUNR_Q@mail.gmail.com>
 <CAHt=NyPsn0jFHzwsxeLrQM6Ha+oktc2o9ZKFu=xJkHy1CjxwSQ@mail.gmail.com>
 <CAHt=NyORRFiB8Jy1sK6rAfJJy+XiV0RTGHZaXJuM4Bd5SkRkEw@mail.gmail.com>
 <CAHt=NyP8xPvZ3+Ugh9rzp2R=qcW+oxNcU3RgUQFdeVM7kHR9bA@mail.gmail.com>
 <CAHt=NyMO-bGXqi_9QcWY6+QoUycSqFLipON6nw-KRTOJvS45pw@mail.gmail.com>
 <CAHt=NyPM=1hX72U+3cShS55bTzaGHg_sXcO1yONOVqanC_NsvQ@mail.gmail.com>
 <CAHt=NyPC4okeNg3HX3DWM4eV5Q8SJ7tV2Vzj===QftzBhTOupQ@mail.gmail.com>
 <CAHt=NyOHu7=XXWBWLnvvFsg63cOVuVYPUz5c-fQw05wT2=rUBw@mail.gmail.com>
 <CAHt=NyNPrZdOeUgEJG_3_ma0OSJUDjOA=co_FbvQr=FSurqdMA@mail.gmail.com>
 <CAHt=NyOACt0uHs3a0XEGf9_saq_MkW_XQw=uegOtPUPm6t8qYg@mail.gmail.com>
 <CAHt=NyNUyUiehSd4ZvQuFGrRm2X4vUBmUssA-+FpfPvey2vnKA@mail.gmail.com>
 <CAHt=NyPh7WCXgNAoi+Cb+Ae+vEqc_tVZ3KJDUEiD7osid-OZvA@mail.gmail.com>
 <CAHt=NyP07x=0qgHDP9Fx7Uwix_ZW3=94yGUTuJShNE8NAAE=kA@mail.gmail.com>
 <CAHt=NyNhJhGsdDq1u-ByQs=C_dZOD8bssxc+pEydHvP=A2O9_w@mail.gmail.com>
 <CAHt=NyOUyeBwKufE75Jn3MmcndHJnPrajhP4Pse+d0DA0eaa6w@mail.gmail.com>
 <CAHt=NyMt0Y0yL1Xrzt-i1TVWjjX_kEWhsvYE0yKDYSDAwz8XSQ@mail.gmail.com>
 <CAHt=NyNGFEZq=+MzzR3scJRpMPLey0NgoHuTnQBz50yP_vfjXQ@mail.gmail.com>
 <CAHt=NyN1HLULR_wFt5NU2N6jw_L8XTrm64PufwhCfVkdFgSaAQ@mail.gmail.com>
 <CAHt=NyO6evRk0DbxBHD-QnOpf9RsUri5cMBNDOsVtm_kkTc76w@mail.gmail.com>
 <CAHt=NyMe32SEHNGf0A=cfeimQXYzfB1Mxo9crhT0WX9dPnJTAA@mail.gmail.com>
 <CAHt=NyN5g2Um4gDB7rjfiTKPuSs5R7w5Qsym9errGO7U2tz6tg@mail.gmail.com>
 <CAHt=NyNjxhyARZEbMHihV5U1AsUwaJwP8QZx6MiL8AV0wXe=Yg@mail.gmail.com>
 <CAHt=NyPk0yxTt+TA3GNDV75+1Pb-Q11Ps-8FXF0aUTCEHax08g@mail.gmail.com>
 <CAHt=NyP1bySRnwNQABx4K6ktyhUXR=BjXvWcP9342RQjtFNgvw@mail.gmail.com>
 <CAHt=NyPgGdtW+CC8COxpCTQgiGwf827FgD_1jV=XRfcCZ__0Hw@mail.gmail.com>
 <CAHt=NyPX=1drCFkU_b7kCP_JmWYHtZAejKh4U1ia6j+MgmYEEQ@mail.gmail.com>
 <CAHt=NyNvCGuc=HTF72YSj3wkReQpOvNEfkGzn2NFUZKK9e8-CQ@mail.gmail.com>
 <CAHt=NyNWPV6FMbzGQe+b+ifm=T3OZ5R7-3MwGu4odFkuO-OAzQ@mail.gmail.com>
 <CAHt=NyPLDnHzbsV8xc7TC9Us9Djg6sDMo+QqKpbg0Kgnp6MzRw@mail.gmail.com>
 <CAHt=NyN_knMJeN3pGqHbpNbjknFt-Vw+0u3AeR2jChdHX7wG1w@mail.gmail.com>
 <CAHt=NyMQqSikhJAd2inR4X8=D-1pWZwxGJtxwb3GwhfwuuWLvg@mail.gmail.com>
Message-ID: <CAHt=NyNonbJn-qYgZy4UR54x_0g39iMtzGreWj+mp5sM2wJyOg@mail.gmail.com>

GNU Tools Weekly News Week 42 (June 14, 2026)

Release updates for GNU toolchain:
 * GCC 15.3.0 was released
  * https://inbox.sourceware.org/gcc/p8nq1983-qn01-7814-3p76-13n5r9q755q2@fhfr.qr/
 * GNU binutils 2.46.1 was released
  * https://inbox.sourceware.org/binutils/87y0gohcay.fsf@gentoo.org/

GNU toolchain conference reminders:
 * FOSSY 2026 toolchain track North America, Aug 6-9 (Vancouver, Canada)
 * GNU Tools Cauldron 2026, Fri-Sun, October 2-4 (Prague, Czechia)
  * https://gcc.gnu.org/wiki/cauldron2026
  * https://conf.gnu-tools-cauldron.org/prg26/cfp
 * Toolchains Track at LPC 2026, October 7th (Prague, Czechia)
  * https://lpc.events/event/20/abstracts/


General/big GNU toolchain news (including sourceware news):
 * Sourceware budget and funding 2026/2027, Fri 12, 15:00 UTC
  * notes from the meeting:
https://inbox.sourceware.org/gcc/20260614225910.GA14303@gnu.wildebeest.org/

GCC easy issue to tackle of the week (2 this week):
  * `(x == MAX_VALUE) ? y : MIN<x, y>` -> MIN<x,y>
   * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125700
   * Reach out to Andrea Pinski <andrew.pinski@oss.qualcomm.com> for
mentoring on this issue.
 * Improve RISC-V sequence for conditional xor with a constant
   * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125731
   * Reach out to Jeff Law <jeffrey.law@oss.qualcomm.com> for
mentoring on this issue.
* Previous ones are listed on https://gcc.gnu.org/wiki/EasyIssuesOfTheWeek

GCC commits:
 * https://gcc.gnu.org/r17-1417 - r17-1559 :  143 commits
 * aarch64: Add support for FEAT_SSVE_BitPerm and some other intrsinics
  * https://gcc.gnu.org/r17-1424-g548b39f569a308 ... r17-1428-g5da2ddf4ef8d94
 * aarch64: Use MOVI for low?64?bit integer SIMD constant vectors
  * https://gcc.gnu.org/r17-1491-gf152cf1734f808
 * ranger: Refine modulo range operations with fixed quotient
  * https://gcc.gnu.org/r17-1493-gcd52e71e8aea25
 * phiopt: Allow factoring out of more than just single operand operations
  * https://gcc.gnu.org/r17-1507-gc43fed44d9ac34
 * driver: Spill long COLLECT_GCC_OPTIONS to a response file
  * https://gcc.gnu.org/r17-1526-g619a5e5586759a
 * match: Optimize (~a) >> a to -1 for signed a
  * https://gcc.gnu.org/r17-1527-gb3ade4e315e5ba
 * match: Add bitop reduction simplifications against zero
  * https://gcc.gnu.org/r17-1543-gcee985872c4976

GCC discussion:
 *

GCC bugzilla stats
 *  138 new issues filed
 *  70 issues closed

binutils/gdb commits:
 * gdb/MicroBlaze: Add support for native linux gdb:
  * https://sourceware.org/cgit/binutils-gdb/commit/?id=d62f64e17b33fb76653fa0c008c61b782d07f8ec
 *
gdb discussion:
 * RFC: prototype of C extensions using the Python limited API (continued)
  * https://inbox.sourceware.org/gdb/21479c1d-3a9a-4ae2-bc1a-5dc19871f275@arm.com/
binutils discussion:
  *

glibc commits:
*
glibc discussion:
 *

From zhuangqiubin@linux.spacemit.com  Mon Jun 15 08:19:01 2026
From: zhuangqiubin@linux.spacemit.com (Mark Zhuang)
Date: Mon, 15 Jun 2026 16:19:01 +0800
Subject: [PATCH v6 1/2] RISC-V: Add SpacemiT vendor extension xsmtvdot
In-Reply-To: <b9da157e-9a4d-4988-8478-487cad3850d9@iscas.ac.cn>
References: <b9da157e-9a4d-4988-8478-487cad3850d9@iscas.ac.cn>
Message-ID: <20260615081901.1991388-1-zhuangqiubin@linux.spacemit.com>

Hi Jan,

This patch series has received a Reviewed-by from Jiawei. Could you
please take a look and commit it when you have time? I'm happy to make
any further changes if needed.

Thanks,
Mark

From jbeulich@suse.com  Mon Jun 15 08:25:26 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Mon, 15 Jun 2026 10:25:26 +0200
Subject: [PATCH v6 1/2] RISC-V: Add SpacemiT vendor extension xsmtvdot
In-Reply-To: <20260615081901.1991388-1-zhuangqiubin@linux.spacemit.com>
References: <b9da157e-9a4d-4988-8478-487cad3850d9@iscas.ac.cn>
 <20260615081901.1991388-1-zhuangqiubin@linux.spacemit.com>
Message-ID: <0ca5423e-3712-4f84-abaf-fb24586d6b4b@suse.com>

On 15.06.2026 10:19, Mark Zhuang wrote:
> This patch series has received a Reviewed-by from Jiawei. Could you
> please take a look and commit it when you have time? I'm happy to make
> any further changes if needed.

Hmm, no, not really. I'm not a RISC-V maintainer (adding them to Cc), and
for arch-specific new code it should imo really be them to take care.

I'm sorry, Jan

From jbeulich@suse.com  Mon Jun 15 08:39:00 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Mon, 15 Jun 2026 10:39:00 +0200
Subject: [RFC 1/2] RISC-V: Add Zvdota extension classes
In-Reply-To: <20260609153844.538604-1-jiawei@iscas.ac.cn>
References: <20260609153844.538604-1-jiawei@iscas.ac.cn>
Message-ID: <0d0b3cd4-8358-4497-b168-b1409296941b@suse.com>

On 09.06.2026 17:38, Jiawei wrote:
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zvdota.d
> @@ -0,0 +1,19 @@
> +#as: -march=rv64gc_zvqwdota8i_zvqwdota16i_zvfwdota16bf_zvfqwdota8f

As can be seen very "neatly" here, the need to specify effectively every
insn's extension separately (really only one of zvqwdota8i and zvqwdota16i
should be necessary to spell out) is getting unwieldy. The situation is
even worse with what patch 2 adds. Could we consider a shorthand zvdota
here (and zvbdota in patch 2), covering all extensions in one go?

> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -2226,6 +2226,13 @@ const struct riscv_opcode riscv_opcodes[] =
>  {"vfwmaccbf16.vf",  0, INSN_CLASS_ZVFBFWMA, "Vd,S,VtVm",  MATCH_VFWMACCBF16_VF, MASK_VFWMACCBF16_VF, match_opcode, 0},
>  {"vfwmaccbf16.vv",  0, INSN_CLASS_ZVFBFWMA, "Vd,Vs,VtVm", MATCH_VFWMACCBF16_VV, MASK_VFWMACCBF16_VV, match_opcode, 0},
>  
> +/* Zvdota instructions.  */
> +{"vqwdotau.vv", 0, INSN_CLASS_ZVQWDOTA8I_OR_ZVQWDOTA16I, "Vd,Vt,VsVm", MATCH_VQWDOTAU_VV, MASK_VQWDOTAU_VV, match_opcode, 0},
> +{"vqwdotas.vv", 0, INSN_CLASS_ZVQWDOTA8I_OR_ZVQWDOTA16I, "Vd,Vt,VsVm", MATCH_VQWDOTAS_VV, MASK_VQWDOTAS_VV, match_opcode, 0},
> +{"vfwdota.vv",  0, INSN_CLASS_ZVFWDOTA16BF, "Vd,Vt,VsVm", MATCH_VFWDOTA_VV, MASK_VFWDOTA_VV, match_opcode, 0},
> +{"vfqwdota.vv", 0, INSN_CLASS_ZVFQWDOTA8F, "Vd,Vt,VsVm", MATCH_VFQWDOTA_VV, MASK_VFQWDOTA_VV, match_opcode, 0},
> +{"vfqwdota.alt.vv", 0, INSN_CLASS_ZVFQWDOTA8F, "Vd,Vt,VsVm", MATCH_VFQWDOTA_ALT_VV, MASK_VFQWDOTA_ALT_VV, match_opcode, 0},

I'm glad I didn't commit my "RISC-V: add dedicated vector arithmetic .insn
forms" yet. Prior to this series only a very limited set of OP-VE encodings
were in use (in mvv iirc). Now ivv and fvv encodings appear as well, hence
I think we want to re-consider what we discussed regarding the RFC that I
continue to have in that patch: It may end up being better then if the
major opcode also needs spelling out in the .insn operands. Then the new
forms here could be encoded that same way, right from the beginning.

For reference, I've locally extended that RFC remark like this:

"RFC: OP-VE reuses (at least) OPMVV, so "mvv" would end up ambiguous if we
      wanted to also introduce insn forms there; with Zvdota and Zvbdota
      "ivv" and "fvv" also become used under that same major opcode. Otoh
      I wanted to avoid having O7 as the first operand everywhere. An
      option might be to distinguish future OP-VE ones (in the once
      supposed P extension encoding space iirc) by e.g. prefixing with P,
      or - derived from OP-VE - with E. Yet that would likely end up being
      a fully redundant set in the long run."

It is really unfortunate that none of the RISC-V maintainers has voiced
any opinion so far ...

Jan

From ro@CeBiTec.Uni-Bielefeld.DE  Mon Jun 15 09:20:39 2026
From: ro@CeBiTec.Uni-Bielefeld.DE (Rainer Orth)
Date: Mon, 15 Jun 2026 11:20:39 +0200
Subject: [PATCH] ld: xfail pr29655 on SPARC [PR34151]
Message-ID: <yddv7bkkvmg.fsf@CeBiTec.Uni-Bielefeld.DE>

As described in PR ld/34151, the recent "Build pr29655" test FAILs on
SPARC, both Solaris and Linux.

Until this is fixed, this patch xfail's the test.

Tested on sparc{v9,}-sun-solaris2.11, sparc{64,}-unknown-linux-gnu, and
amd64-pc-solaris2.11.

Ok for trunk?


This failure is the only one keeping the Solaris/SPARC buildbots from
going green.  To allow them to easily report future issues, it would be
good if this could go in.

Besides, Frank reported in the PR that RISC-V shows the same failure.  I
wonder how to deal with that?  I guess it would be best to file a
separate PR for that.

Thanks.
	Rainer

-- 
-----------------------------------------------------------------------------
Rainer Orth, Center for Biotechnology, Bielefeld University


2026-06-14  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>

	ld:
	* testsuite/ld-elf/shared.exp (Build pr29655): xfail on SPARC.

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From zhuangqiubin@linux.spacemit.com  Mon Jun 15 09:45:28 2026
From: zhuangqiubin@linux.spacemit.com (Mark Zhuang)
Date: Mon, 15 Jun 2026 17:45:28 +0800
Subject: [PATCH v6 1/2] RISC-V: Add SpacemiT vendor extension xsmtvdot
In-Reply-To: <0ca5423e-3712-4f84-abaf-fb24586d6b4b@suse.com>
References: <0ca5423e-3712-4f84-abaf-fb24586d6b4b@suse.com>
Message-ID: <20260615094528.2016824-1-zhuangqiubin@linux.spacemit.com>

Hi Jan,

Thanks for the clarification -- much appreciated.

Just to be clear, I know you're not a RISC-V maintainer. I only reached out
because the RISC-V maintainers have been less active lately, and I
sincerely didn't mean to add to your workload.

I fully agree this should go through them, and will wait for their
availability to handle the patch.

Thanks again!

Best,
Mark

From mark@klomp.org  Mon Jun 15 11:35:26 2026
From: mark@klomp.org (Mark Wielaard)
Date: Mon, 15 Jun 2026 13:35:26 +0200
Subject: Nominations for =?UTF-8?Q?Anthropic=E2=80=99s?= Claude for Open
 Source program
In-Reply-To: <CALvbMcBvEN3jkfBVnXHNu_C538jFdC8vLTz7ZNkNDwc=vvP0mw@mail.gmail.com>
References: <CAGWvnykaUiiAPY8sMFAGu83ObWzChqp1Jk8BDwjy7tFedkd0Bg@mail.gmail.com>
 <CALvbMcBvEN3jkfBVnXHNu_C538jFdC8vLTz7ZNkNDwc=vvP0mw@mail.gmail.com>
Message-ID: <975369a4f85805256fbe60909cc6d6a51e5d4099.camel@klomp.org>

Hi,

On Fri, 2026-06-12 at 12:34 -0700, Andrew Pinski via Gcc wrote:
> On Fri, Jun 12, 2026 at 12:25?PM David Edelsohn via Gcc <gcc@gcc.gnu.org> wrote:
> > please respond to this email thread with a short description of
> > how you would utilize the access and the potential impact on the GNU
> > Toolchain. The program's slots are limited and Carlos O'Donell and
> > I plan to review the proposals.
> > [...]
> > P.S. This is not an endorsement of Anthropic, Claude or LLMs. We dislike
> > having to say it, but please don?t use this thread as a platform to express
> > your personal opinions about the companies or about AI?s impact on the
> > world.
> 
> Can we please keep this kind of emails out of the development mailing
> lists?

Yes. Even if you say it isn't an endorsement of (proprietary, saas)
LLMs, it certainly reads like one. Please stop this.

Thanks,

Mark

From dje.gcc@gmail.com  Mon Jun 15 14:42:10 2026
From: dje.gcc@gmail.com (David Edelsohn)
Date: Mon, 15 Jun 2026 10:42:10 -0400
Subject: =?UTF-8?Q?Re=3A_Nominations_for_Anthropic=E2=80=99s_Claude_for_Open_So?=
 =?UTF-8?Q?urce_program?=
In-Reply-To: <975369a4f85805256fbe60909cc6d6a51e5d4099.camel@klomp.org>
References: <CAGWvnykaUiiAPY8sMFAGu83ObWzChqp1Jk8BDwjy7tFedkd0Bg@mail.gmail.com>
 <CALvbMcBvEN3jkfBVnXHNu_C538jFdC8vLTz7ZNkNDwc=vvP0mw@mail.gmail.com>
 <975369a4f85805256fbe60909cc6d6a51e5d4099.camel@klomp.org>
Message-ID: <CAGWvny=kvhXNiV_gB5=oyx_H=W=VA8ARyBSgpjBwAc=-PTWzDw@mail.gmail.com>

On Mon, Jun 15, 2026 at 7:35?AM Mark Wielaard <mark@klomp.org> wrote:

> Hi,
>
> On Fri, 2026-06-12 at 12:34 -0700, Andrew Pinski via Gcc wrote:
> > On Fri, Jun 12, 2026 at 12:25?PM David Edelsohn via Gcc <gcc@gcc.gnu.org>
> wrote:
> > > please respond to this email thread with a short description of
> > > how you would utilize the access and the potential impact on the GNU
> > > Toolchain. The program's slots are limited and Carlos O'Donell and
> > > I plan to review the proposals.
> > > [...]
> > > P.S. This is not an endorsement of Anthropic, Claude or LLMs. We
> dislike
> > > having to say it, but please don?t use this thread as a platform to
> express
> > > your personal opinions about the companies or about AI?s impact on the
> > > world.
> >
> > Can we please keep this kind of emails out of the development mailing
> > lists?
>
> Yes. Even if you say it isn't an endorsement of (proprietary, saas)
> LLMs, it certainly reads like one. Please stop this.
>

Emails to this list are permitted so long as they are on topic, and meet
the community code of conduct.

Asking politely to stay on topic is appropriate.

Telling the community what it should or should not do or what is permitted
to be discussed is not appropriate.  You and Andrew are not the arbiters of
speech on the GCC, Binutils, GLIBC, and GDB mailing lists.  Please stop.
This intimidation and silencing tactic is not appropriate.

Thanks, David


> Thanks,
>
> Mark
>
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From Wilco.Dijkstra@arm.com  Mon Jun 15 15:04:42 2026
From: Wilco.Dijkstra@arm.com (Wilco Dijkstra)
Date: Mon, 15 Jun 2026 15:04:42 +0000
Subject: [PATCH] AArch64 gas: Block section relative symbols in GOT
 relocations [PR30788]
In-Reply-To: <d6dd8e41-21ce-4a9b-837b-c5e54d51cd00@arm.com>
References: <PAWPR08MB8982EA96A85A9846678CCFB5830B2@PAWPR08MB8982.eurprd08.prod.outlook.com>
 <da73b869-98e0-4c6a-8ea2-ee25d4fb74f9@arm.com>
 <PAWPR08MB8982B0075AF2F0CF9C51BADC83082@PAWPR08MB8982.eurprd08.prod.outlook.com>
 <d6dd8e41-21ce-4a9b-837b-c5e54d51cd00@arm.com>
Message-ID: <PAWPR08MB8982E0055215376A1CD03B0F83E62@PAWPR08MB8982.eurprd08.prod.outlook.com>

Hi Richard/Alice,

> After some extensive archaeology it's now clear that we don't care about the VTABLE stuff.? In fact, I'm amazed that we didn't expunge that entirely some years ago - we certainly blew away all the tests for it.
>
> OK.

Since I don't have write access, could someone commit this for me, please?

Cheers,
Wilco

From rearnsha@arm.com  Mon Jun 15 15:57:31 2026
From: rearnsha@arm.com (Richard Earnshaw)
Date: Mon, 15 Jun 2026 16:57:31 +0100
Subject: [committed] Port expandargstr from gcc/libiberty
Message-ID: <20260615155731.2965355-1-rearnsha@arm.com>

From: Richard.Earnshaw@arm.com

Sync recent changes to libiberty.

include/ChangeLog:

	* libiberty.h (expandargstr): Declare.

libiberty/ChangeLog:

	* argv.c (expandargstr): New function.

Signed-off-by: Sunil Dora <sunilkumar.dora@windriver.com>
---

Committing as obvious.

diff --git a/include/libiberty.h b/include/libiberty.h
index ae0e94bc4c5..e905f2cf190 100644
--- a/include/libiberty.h
+++ b/include/libiberty.h
@@ -94,6 +94,11 @@ extern int writeargv (char * const *, FILE *);
 
 extern int countargv (char * const *);
 
+/* Expand VAL as a response file if it begins with '@' and return the
+   result as a shell-quoted string.  */
+
+extern char *expandargstr (const char *, const char *);
+
 /* Return the last component of a path name.  Note that we can't use a
    prototype here because the parameter is declared inconsistently
    across different systems, sometimes as "char *" and sometimes as
diff --git a/libiberty/argv.c b/libiberty/argv.c
index 64127f70c99..35e2750c5ff 100644
--- a/libiberty/argv.c
+++ b/libiberty/argv.c
@@ -492,6 +492,81 @@ countargv (char * const *argv)
   return argc;
 }
 
+/*
+
+@deftypefn Extension {char *} expandargstr @
+  (const char *@var{progname}, const char *@var{val})
+
+Expand @var{val} as a response file via @code{expandargv} if it begins
+with @samp{@@}, using @var{progname} as @code{argv[0]}, and return the
+expanded option list as a shell-quoted string.  Returns a newly
+allocated string.
+
+@end deftypefn
+
+*/
+
+char *
+expandargstr (const char *progname, const char *val)
+{
+  int argc = 2;
+  char **argv;
+  char **orig;
+  size_t len;
+  char *buf;
+  char *p;
+  int i;
+
+  if (val[0] != '@')
+    return xstrdup (val);
+
+  argv = (char **) xcalloc (3, sizeof (char *));
+  orig = argv;
+  argv[0] = xstrdup (progname);
+  argv[1] = xstrdup (val);
+  argv[2] = NULL;
+  expandargv (&argc, &argv);
+  if (argv != orig)
+    freeargv (orig);
+
+  len = 1;
+  for (i = 1; argv[i] != NULL; i++)
+    {
+      const char *q;
+      if (i > 1)
+	len++;
+      len += 2;
+      for (q = argv[i]; *q; q++)
+	len += (*q == '\'') ? 4 : 1;
+    }
+
+  buf = (char *) xmalloc (len);
+  p = buf;
+  for (i = 1; argv[i] != NULL; i++)
+    {
+      const char *q;
+      if (i > 1)
+	*p++ = ' ';
+      *p++ = '\'';
+      for (q = argv[i]; *q; q++)
+	{
+	  if (*q == '\'')
+	    {
+	      *p++ = '\'';
+	      *p++ = '\\';
+	      *p++ = '\'';
+	      *p++ = '\'';
+	    }
+	  else
+	    *p++ = *q;
+	}
+      *p++ = '\'';
+    }
+  *p = '\0';
+  freeargv (argv);
+  return buf;
+}
+
 #ifdef MAIN
 
 /* Simple little test driver. */
-- 
2.43.0


From pinskia@gmail.com  Mon Jun 15 16:04:55 2026
From: pinskia@gmail.com (Andrew Pinski)
Date: Mon, 15 Jun 2026 09:04:55 -0700
Subject: =?UTF-8?Q?Re=3A_Nominations_for_Anthropic=E2=80=99s_Claude_for_Open_So?=
 =?UTF-8?Q?urce_program?=
In-Reply-To: <CAGWvny=kvhXNiV_gB5=oyx_H=W=VA8ARyBSgpjBwAc=-PTWzDw@mail.gmail.com>
References: <CAGWvnykaUiiAPY8sMFAGu83ObWzChqp1Jk8BDwjy7tFedkd0Bg@mail.gmail.com>
 <CALvbMcBvEN3jkfBVnXHNu_C538jFdC8vLTz7ZNkNDwc=vvP0mw@mail.gmail.com>
 <975369a4f85805256fbe60909cc6d6a51e5d4099.camel@klomp.org>
 <CAGWvny=kvhXNiV_gB5=oyx_H=W=VA8ARyBSgpjBwAc=-PTWzDw@mail.gmail.com>
Message-ID: <CA+=Sn1kXqPED3bh1Ns_+VZ1OvUmGbM2FPN5z6dwO1bybG+0pqg@mail.gmail.com>

On Mon, Jun 15, 2026, 7:43?AM David Edelsohn <dje.gcc@gmail.com> wrote:

> On Mon, Jun 15, 2026 at 7:35?AM Mark Wielaard <mark@klomp.org> wrote:
>
>> Hi,
>>
>> On Fri, 2026-06-12 at 12:34 -0700, Andrew Pinski via Gcc wrote:
>> > On Fri, Jun 12, 2026 at 12:25?PM David Edelsohn via Gcc <
>> gcc@gcc.gnu.org> wrote:
>> > > please respond to this email thread with a short description of
>> > > how you would utilize the access and the potential impact on the GNU
>> > > Toolchain. The program's slots are limited and Carlos O'Donell and
>> > > I plan to review the proposals.
>> > > [...]
>> > > P.S. This is not an endorsement of Anthropic, Claude or LLMs. We
>> dislike
>> > > having to say it, but please don?t use this thread as a platform to
>> express
>> > > your personal opinions about the companies or about AI?s impact on the
>> > > world.
>> >
>> > Can we please keep this kind of emails out of the development mailing
>> > lists?
>>
>> Yes. Even if you say it isn't an endorsement of (proprietary, saas)
>> LLMs, it certainly reads like one. Please stop this.
>>
>
> Emails to this list are permitted so long as they are on topic, and meet
> the community code of conduct.
>

Except the original email does not meet community ethics of the list.



> Asking politely to stay on topic is appropriate.
>
> Telling the community what it should or should not do or what is permitted
> to be discussed is not appropriate.  You and Andrew are not the arbiters of
> speech on the GCC, Binutils, GLIBC, and GDB mailing lists.  Please stop.
> This intimidation and silencing tactic is not appropriate.
>


Saying ethics of such company and its software usage is offtopic for this
thread does not make it offtopic for the community. Your ask in itself is
intimidating to many and was very inappropriate.
If this kind of offer came from anyone else, many of us still think the
offer is offtopic for the community lists. And Saying your email is on
topic means there will/can be a flood gate of similar offers. I am not sure
that was your intention.

Also in the past there was some asking if posting jobs were OK, and the
community at the time decided no. This kind of offer should be in the same
category as that.

Thanks
Andrea









> Thanks, David
>
>
>> Thanks,
>>
>> Mark
>>
>
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From evgeny.karpov@arm.com  Mon Jun 15 16:06:45 2026
From: evgeny.karpov@arm.com (Evgeny Karpov)
Date: Mon, 15 Jun 2026 18:06:45 +0200
Subject: [PATCH v8 0/1] Implement Structured Exception Handling (SEH) on
 AArch64
Message-ID: <20260615160646.87169-1-evgeny.karpov@arm.com>

Hello,

Thank you for reviewing and upstreaming some patches from v7!
v8 contains SEH tests, refactoring based on comments for v7, more conditions
to validate correctness. The patch series has been reduced to one patch after
merging:

[PATCH v7 1/3] Adjust pdata function table entries sorting for AArch64
[PATCH v7 2/3] Extract SEH shared helpers into separate file.

Changes in v8:
- Refactor and simplify some conditions.
- Move .xdata record writing to a separate
  function (seh_aarch64_emit_xdata_record).
- Add documentation link to obj-coff-seh-aarch64.h.
- Add a minor change to the patch description.
- Use only prologue/epilogue.
- Add SEH tests.
- Use unsigned char instead of unsigned for aarch64_unwind_info.
- Rename offset/reg_offset to offset_addend/reg_addend.
- Remove shift direction from the names.
- Correct typos and comments locations.
- Add more comments and extend some of them.
- Reorder aarch64_unwind_code_data declarations.
- Remove AARCH64_UNOP_* and use code inside the declaration.
- Remove members that are NULL or 0.
- Rename unwind_code_pack_info to info.
- Rename aarch64_element to element and move 4 lines to the end of the function.
- Add validations for offset and reg.
- Drop the condition for code_bits.
- Inline some constants to the conditions.
- Check the register name for SEH directives.
- Modify style by changing line wrapping.
- Optimize some calculations.
- Remove some comments to avoid confusion.
- Add clarification for missing implementation.
- Move seh_aarch64_write_data under OBJ_COFF scope.
- Support .seh_code to simplify porting from x86_64.

Changes in v7 2026-03-19:
- Rename sort_x64_pdata to sort_pdata.
- Move obj_coff_seh_do_final implementation to a separate function.
- Merge patch 3/4 with 4/4.
https://sourceware.org/pipermail/binutils/2026-March/148657.html

Changes in v6 2026-03-11:
- Revert changes in frag_offset_ignore_align_p.
- Relax the code segment to be able to calculate the function sizes.
- Add seh_function_size that implements the calculation of the function size
  and replace frag_offset_ignore_align_p call with this implementation.
https://sourceware.org/pipermail/binutils/2026-March/148488.html

Changes in v5 2026-02-24:
- In many places int, uint32_t and int32_t have been replaced to unsigned.
- Refactor and move SEH aarch64 implementation to separate files.
- Replace uintptr_t with bfd_vma.
- Update comments.
- Add dedicated initializers.
- Move some variables inside loops.
- Fix the definition for packing some unwinding codes.
- Add description to seh commands.
- Rename prolog_instruction_count to prolog_insn_count.
- Relocate variable initilization closer to place of use.
- Add unwind_ prefix to unwind type enumerator.
https://sourceware.org/pipermail/binutils/2026-February/148332.html

Changes in v3(v4) 2025-08-14:
- Make the AArch64 implementation fully static.
- Fix ARM64_MAX_UNWIND_CODES and introduce AARCH64_MAX_UNWIND_CODES_SIZE.
- Add validation for the epilogue_scope array.
- Add an upper bound for the register number.
- Exclude changes in md_do_align.
- Refactor the AArch64 SEH implementation to emit .pdata/.xdata records at
  the end of assembly.
- Declare md_finish for AArch64 to trigger obj_coff_generate_pdata.
- Support different fragment ordering in frag_offset_ignore_align_p
- Change signed to unsigned.
- Replace Arm64 / arm64 with AArch64 / aarch64.
- Add references to the official documentation to clarify
  implementation.
- Add static and aarch64_ prefix.
- Rebase onto the current master.
- Fix comments.
- Correct code style and naming.
https://sourceware.org/pipermail/binutils/2025-August/143401.html

Changes in v2 2025-05-09:
- Add guards for different architectures
- Fix code style issues and typos
- Move Arm64-specific code to pdata/xdata functions
- Prefer unsigned int over uint32_t in some places
- Revert memory release to the original implementation
- Refactor long function fragmentation
- Fix the function size calculation issue related to code alignment
https://sourceware.org/pipermail/binutils/2025-May/140961.html

v1 2025-04-09:
This patch series supports the GCC patch series that implements SEH
support for the aarch64-w64-mingw32 target.
https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669003.html
The patch series has been tested by applying internal tests and passing
all Boost library tests that involve exception handling.
https://sourceware.org/pipermail/binutils/2025-April/140495.html

Regards,
Evgeny

Evgeny Karpov (1):
  aarch64: Implement Structured Exception Handling (SEH) on AArch64

 gas/config/obj-coff-seh-aarch64.c             | 971 ++++++++++++++++++
 gas/config/obj-coff-seh-aarch64.h             | 251 +++++
 gas/config/obj-coff-seh-shared.c              |   8 +-
 gas/config/obj-coff.c                         |   4 +
 gas/config/tc-aarch64.c                       |  10 +
 gas/config/tc-aarch64.h                       |   6 +
 gas/testsuite/gas/pe/pe.exp                   |   3 +
 gas/testsuite/gas/pe/seh-aarch64-error.l      | 110 ++
 gas/testsuite/gas/pe/seh-aarch64-error.s      | 128 +++
 gas/testsuite/gas/pe/seh-aarch64-large-func.d |  53 +
 gas/testsuite/gas/pe/seh-aarch64-large-func.s |  13 +
 gas/testsuite/gas/pe/seh-aarch64.d            |  66 ++
 gas/testsuite/gas/pe/seh-aarch64.s            |  49 +
 gas/write.c                                   |   2 +-
 gas/write.h                                   |   1 +
 15 files changed, 1673 insertions(+), 2 deletions(-)
 create mode 100644 gas/config/obj-coff-seh-aarch64.c
 create mode 100644 gas/config/obj-coff-seh-aarch64.h
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64-error.l
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64-error.s
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64-large-func.d
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64-large-func.s
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64.d
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64.s


From evgeny.karpov@arm.com  Mon Jun 15 16:06:46 2026
From: evgeny.karpov@arm.com (Evgeny Karpov)
Date: Mon, 15 Jun 2026 18:06:46 +0200
Subject: [PATCH v8 1/1] aarch64: Implement Structured Exception Handling (SEH)
 on AArch64
In-Reply-To: <20260615160646.87169-1-evgeny.karpov@arm.com>
References: <20260615160646.87169-1-evgeny.karpov@arm.com>
Message-ID: <20260615160646.87169-2-evgeny.karpov@arm.com>

The patch reuses shared helpers for SEH and implements SEH on AArch64.
The implementation is based on
(https://learn.microsoft.com/en-us/cpp/build/arm64-exception-handling?view=msvc-170)
and pdata/xdata SEH records are emitted from md_finish.

When .pdata/.xdata is emitted, the function size is required.
Function sizes are calculated as late as possible, and the code segment needs
to be relaxed to be able to calculate the function sizes.

Initially, obj_coff_generate_pdata was called in write_object_file.
Before the change, obj_coff_generate_pdata was used only to validate
syntax, which was sufficient for that purpose. However, that location
seems incorrect, as it is too late to emit .pdata/.xdata records
in the AArch64 case.

md_finish has been declared for AArch64 and extended with
seh_aarch64_write_data to emit .pdata/.xdata records after all
assembly has been completed.

Signed-off-by: Evgeny Karpov <evgeny@kmaps.co>

gas/ChangeLog:
	* gas/config/obj-coff-seh-shared.c (defined): Update.
	(struct seh_seg_list): Use seh_context_t.
	* gas/config/obj-coff.c (defined): Update.
	* gas/config/tc-aarch64.c (defined): Add OBJ_COFF guard.
	(aarch64_md_finish): Add.
	* gas/config/tc-aarch64.h (defined): Add OBJ_COFF guard.
	(md_finish): Add.
	(aarch64_md_finish): Add.
	(seh_aarch64_write_data): Add.
	* testsuite/gas/pe/pe.exp: Add SEH tests.
	* write.c: Update.
	* write.h (subsegs_finish_section): Update.
	* config/obj-coff-seh-aarch64.c: New file.
	* config/obj-coff-seh-aarch64.h: New file.
	* testsuite/gas/pe/seh-aarch64-error.l: New test.
	* testsuite/gas/pe/seh-aarch64-error.s: New test.
	* testsuite/gas/pe/seh-aarch64-large-func.d: New test.
	* testsuite/gas/pe/seh-aarch64-large-func.s: New test.
	* testsuite/gas/pe/seh-aarch64.d: New test.
	* testsuite/gas/pe/seh-aarch64.s: New test.
---
 gas/config/obj-coff-seh-aarch64.c             | 971 ++++++++++++++++++
 gas/config/obj-coff-seh-aarch64.h             | 251 +++++
 gas/config/obj-coff-seh-shared.c              |   8 +-
 gas/config/obj-coff.c                         |   4 +
 gas/config/tc-aarch64.c                       |  10 +
 gas/config/tc-aarch64.h                       |   6 +
 gas/testsuite/gas/pe/pe.exp                   |   3 +
 gas/testsuite/gas/pe/seh-aarch64-error.l      | 110 ++
 gas/testsuite/gas/pe/seh-aarch64-error.s      | 128 +++
 gas/testsuite/gas/pe/seh-aarch64-large-func.d |  53 +
 gas/testsuite/gas/pe/seh-aarch64-large-func.s |  13 +
 gas/testsuite/gas/pe/seh-aarch64.d            |  66 ++
 gas/testsuite/gas/pe/seh-aarch64.s            |  49 +
 gas/write.c                                   |   2 +-
 gas/write.h                                   |   1 +
 15 files changed, 1673 insertions(+), 2 deletions(-)
 create mode 100644 gas/config/obj-coff-seh-aarch64.c
 create mode 100644 gas/config/obj-coff-seh-aarch64.h
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64-error.l
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64-error.s
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64-large-func.d
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64-large-func.s
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64.d
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64.s

diff --git a/gas/config/obj-coff-seh-aarch64.c b/gas/config/obj-coff-seh-aarch64.c
new file mode 100644
index 00000000000..b0d32c72d01
--- /dev/null
+++ b/gas/config/obj-coff-seh-aarch64.c
@@ -0,0 +1,971 @@
+/* SEH .pdata/.xdata COFF object file format on AArch64
+   Copyright (C) 2026 Free Software Foundation, Inc.
+
+   This file is part of GAS.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#include "obj-coff-seh-aarch64.h"
+
+static struct seh_aarch64_context *seh_ctx_root = NULL;
+static bool in_seh_proc = false;
+
+struct aarch64_unwind_info {
+  const char *directive;
+  char reg_type;
+  unsigned char offset_bits;
+  unsigned char reg_bits;
+  unsigned char reg_max;
+  unsigned char code_bits;
+  unsigned char code;
+  unsigned char offset_shift;
+  unsigned char offset_addend;
+  unsigned char reg_shift;
+  unsigned char reg_addend;
+  unsigned char size;
+};
+
+/* Unwind codes format for AArch64 are described at
+   https://learn.microsoft.com/en-us/cpp/build/arm64-exception-handling?view=msvc-170#unwind-codes
+   and calculated in seh_aarch64_add_unwind_element function.
+   aarch64_unwind_code_data is indexed by the seh_aarch64_unwind_types enum.  */
+
+static const struct aarch64_unwind_info
+aarch64_unwind_code_data[] = {
+  {
+    .size = 1,
+    .code_bits = 3, .code = 0b000U,
+    .offset_bits = 5, .offset_shift = 4
+  },
+  {
+    .size = 2,
+    .code_bits = 5, .code = 0b11000U,
+    .offset_bits = 11, .offset_shift = 4
+  },
+  {
+    .size = 4,
+    .code_bits = 8, .code = 0b11100000U,
+    .offset_bits = 24, .offset_shift = 4
+  },
+  {
+    .directive = ".seh_save_reg",
+    .size = 2,
+    .code_bits = 6, .code = 0b110100U,
+    .offset_bits = 6, .offset_shift = 3,
+    .reg_bits = 4, .reg_addend = 19, .reg_type = 'x'
+  },
+  {
+    .directive = ".seh_save_reg_x",
+    .size = 2,
+    .code_bits = 7, .code = 0b1101010U,
+    .offset_bits = 5, .offset_shift = 3, .offset_addend = 1,
+    .reg_bits = 4, .reg_addend = 19, .reg_type = 'x'
+  },
+  {
+    .directive = ".seh_save_regp",
+    .size = 2,
+    .code_bits = 6, .code = 0b110010U,
+    .offset_bits = 6, .offset_shift = 3,
+    .reg_bits = 4, .reg_addend = 19, .reg_type = 'x', .reg_max = 29
+  },
+  {
+    .directive = ".seh_save_regp_x",
+    .size = 2,
+    .code_bits = 6, .code = 0b110011U,
+    .offset_bits = 6, .offset_shift = 3, .offset_addend = 1,
+    .reg_bits = 4, .reg_addend = 19, .reg_type = 'x', .reg_max = 29
+  },
+  {
+    .directive = ".seh_save_fregp",
+    .size = 2,
+    .code_bits = 7, .code = 0b1101100U,
+    .offset_bits = 6, .offset_shift = 3,
+    .reg_bits = 3, .reg_addend = 8, .reg_type = 'd'
+  },
+  {
+    .directive = ".seh_save_fregp_x",
+    .size = 2,
+    .code_bits = 7, .code = 0b1101101U,
+    .offset_bits = 6, .offset_shift = 3, .offset_addend = 1,
+    .reg_bits = 3, .reg_addend = 8, .reg_type = 'd'
+  },
+  {
+    .directive = ".seh_save_freg",
+    .size = 2,
+    .code_bits = 7, .code = 0b1101110U,
+    .offset_bits = 6, .offset_shift = 3,
+    .reg_bits = 3, .reg_addend = 8, .reg_type = 'd'
+  },
+  {
+    .directive = ".seh_save_freg_x",
+    .size = 2,
+    .code_bits = 8, .code = 0b11011110U,
+    .offset_bits = 5, .offset_shift = 3, .offset_addend = 1,
+    .reg_bits = 3, .reg_addend = 8, .reg_type = 'd'
+  },
+  {
+    .directive = ".seh_save_lrpair",
+    .size = 2,
+    .code_bits = 7, .code = 0b1101011U,
+    .offset_bits = 6, .offset_shift = 3,
+    .reg_bits = 3, .reg_shift = 1, .reg_addend = 19, .reg_type = 'x'
+  },
+  {
+    .directive = ".seh_save_fplr",
+    .size = 1,
+    .code_bits = 2, .code = 0b01U,
+    .offset_bits = 6, .offset_shift = 3
+  },
+  {
+    .directive = ".seh_save_fplr_x",
+    .size = 1,
+    .code_bits = 2, .code = 0b10U,
+    .offset_bits = 6, .offset_shift = 3, .offset_addend = 1
+  },
+  {
+    .directive = ".seh_save_r19r20_x",
+    .size = 1,
+    .code_bits = 3, .code = 0b001U,
+    .offset_bits = 5, .offset_shift = 3
+  },
+  {
+    .directive = ".seh_add_fp",
+    .size = 2,
+    .code_bits = 8, .code = 0b11100010U,
+    .offset_bits = 8, .offset_shift = 3
+  },
+  {
+    .directive = ".seh_set_fp",
+    .size = 1,
+    .code_bits = 8, .code = 0b11100001U
+  },
+  {
+    .directive = ".seh_save_next",
+    .size = 1,
+    .code_bits = 8, .code = 0b11100110U
+  },
+  {
+    .directive = ".seh_nop",
+    .size = 1,
+    .code_bits = 8, .code = 0b11100011U
+  },
+  {
+    .directive = ".seh_pac_sign_lr",
+    .size = 1,
+    .code_bits = 8, .code = 0b11111100U
+  },
+  {
+    .size = 1,
+    .code_bits = 8, .code = 0b11100100U
+  },
+};
+
+/* Set for current context the default handler.  */
+static void
+obj_coff_seh_handler (const int what ATTRIBUTE_UNUSED)
+{
+  char *symbol_name;
+  char name_end;
+
+  if (!verify_context (".seh_handler"))
+    return;
+
+  if (*input_line_pointer == 0 || *input_line_pointer == '\n')
+    as_bad (_(".seh_handler requires a handler"));
+
+  SKIP_WHITESPACE ();
+
+  if (*input_line_pointer == '@')
+    {
+      name_end = get_symbol_name (&symbol_name);
+
+      seh_ctx_cur->handler.X_op = O_constant;
+      seh_ctx_cur->handler.X_add_number = 0;
+
+      if (strcasecmp (symbol_name, "@1") == 0)
+	seh_ctx_cur->handler.X_add_number = 1;
+      else if (strcasecmp (symbol_name, "@0")
+	       && strcasecmp (symbol_name, "@null"))
+	as_bad (_("unknown constant value '%s' for handler"), symbol_name);
+
+      (void) restore_line_pointer (name_end);
+    }
+  else
+    expression (&seh_ctx_cur->handler);
+
+  seh_ctx_cur->handler_data.X_op = O_constant;
+  seh_ctx_cur->handler_data.X_add_number = 0;
+  seh_ctx_cur->xdata_header.x = 1;
+
+  while (skip_whitespace_and_comma (0))
+    {
+      name_end = get_symbol_name (&symbol_name);
+      (void) restore_line_pointer (name_end);
+    }
+}
+
+/* Switch to subsection for handler data for exception region.  */
+static void
+obj_coff_seh_handlerdata (const int what ATTRIBUTE_UNUSED)
+{
+  demand_empty_rest_of_line ();
+
+  switch_xdata (seh_ctx_cur->subsection + 1, seh_ctx_cur->code_seg);
+  seh_ctx_cur->handler_data_xdata_addr = symbol_temp_new_now();
+}
+
+/* Switch back to the code section.  */
+static void
+obj_coff_seh_code (int ignored ATTRIBUTE_UNUSED)
+{
+  subseg_set (seh_ctx_cur->code_seg, 0);
+}
+
+/* Obtain available unwind element.  */
+static void
+seh_aarch64_add_unwind_element (const seh_aarch64_unwind_types unwind_type,
+				unsigned offset, unsigned reg)
+{
+  const struct aarch64_unwind_info *info
+    = aarch64_unwind_code_data + unwind_type;
+  unsigned value_offset_bits = 0;
+
+  if ((seh_ctx_cur->unwind_codes_byte_count
+      + info->size) > AARCH64_MAX_UNWIND_CODES_SIZE)
+    as_bad (_("no unwind element available."));
+
+  unsigned value = 0;
+
+  if (info->offset_bits)
+    {
+      const unsigned divided_by = 1u << info->offset_shift;
+      if (offset & (divided_by - 1))
+	as_bad (_("offset should be divided by %u"), divided_by);
+      offset = (offset >> info->offset_shift) - info->offset_addend;
+      if (offset >= (1u << info->offset_bits))
+	as_bad (_("offset overflows expected range"));
+      value |= offset << value_offset_bits;
+      value_offset_bits += info->offset_bits;
+    }
+
+  if (info->reg_bits)
+    {
+      const unsigned regn_divided_by = 1u << info->reg_shift;
+      reg -= info->reg_addend;
+      if (reg & (regn_divided_by - 1))
+	as_bad (_("unexpected register number"));
+      reg >>= info->reg_shift;
+      if (reg >= (1u << info->reg_bits))
+	as_bad (_("unexpected register number"));
+      value |= reg << value_offset_bits;
+      value_offset_bits += info->reg_bits;
+    }
+
+  const unsigned code = info->code;
+  gas_assert (code < (1u << info->code_bits));
+  value |= code << value_offset_bits;
+
+  seh_aarch64_unwind_code *element;
+  element = seh_ctx_cur->unwind_codes + seh_ctx_cur->unwind_codes_count++;
+  element->type = unwind_type;
+  element->value = value;
+
+  seh_ctx_cur->unwind_codes_byte_count += info->size;
+}
+
+/* Mark begin of new context.  */
+static void
+obj_coff_seh_proc (const int what ATTRIBUTE_UNUSED)
+{
+  char *symbol_name;
+  char name_end;
+
+  if (in_seh_proc)
+    as_bad (_("previous SEH entry not closed (missing .seh_endproc)"));
+
+  if (*input_line_pointer == 0 || *input_line_pointer == '\n')
+    as_bad (_(".seh_proc requires function label name"));
+
+
+  if (!seh_ctx_root)
+  {
+    seh_ctx_root = XCNEW (seh_context);
+    seh_ctx_cur = seh_ctx_root;
+  }
+  else
+  {
+    seh_ctx_cur->next = XCNEW (seh_context);
+    seh_ctx_cur = seh_ctx_cur->next;
+  }
+
+  seh_ctx_cur->next = NULL;
+  seh_ctx_cur->code_seg = now_seg;
+
+  /* The current implementation always use a pair of .pdata and .xdata
+     records.  */
+  const bool use_xdata = true;
+
+  if (use_xdata)
+    {
+      x_segcur = seh_hash_find_or_make (seh_ctx_cur->code_seg, ".xdata");
+      seh_ctx_cur->subsection = x_segcur->subseg;
+      x_segcur->subseg += 2;
+
+      /* Initialize an empty .xdata record.  */
+      seh_ctx_cur->unwind_codes_count = 0;
+      seh_ctx_cur->unwind_codes_byte_count = 0;
+      seh_ctx_cur->epilogue_scopes_count = 0;
+      seh_ctx_cur->epilogue_scopes_capacity = 0;
+      seh_ctx_cur->epilogue_scopes = NULL;
+      seh_ctx_cur->xdata_header.x = 0;
+    }
+
+  SKIP_WHITESPACE ();
+
+  name_end = get_symbol_name (&symbol_name);
+  seh_ctx_cur->func_name = xstrdup (symbol_name);
+  (void) restore_line_pointer (name_end);
+
+  demand_empty_rest_of_line ();
+
+  seh_ctx_cur->start_addr = symbol_temp_new_now ();
+  in_seh_proc = true;
+}
+
+/* Mark end of prologue for current context.  */
+static void
+obj_coff_seh_endprologue (const int what ATTRIBUTE_UNUSED)
+{
+  if (!verify_context (".seh_endprologue")
+      || !seh_validate_seg (".seh_endprologue"))
+    return;
+  demand_empty_rest_of_line ();
+
+  if (seh_ctx_cur->endprologue_addr != NULL)
+    as_warn (_("duplicate .seh_endprologue in .seh_proc block"));
+  else
+    seh_ctx_cur->endprologue_addr = symbol_temp_new_now ();
+
+  /* Unwind codes need to be reversed.  */
+  for (unsigned i = 0, n = seh_ctx_cur->unwind_codes_count; i < n / 2; ++i)
+    {
+      seh_aarch64_unwind_code *unwind_codes = seh_ctx_cur->unwind_codes;
+      const seh_aarch64_unwind_code temp = unwind_codes[i];
+      unwind_codes[i] = unwind_codes[n-i-1];
+      unwind_codes[n-i-1] = temp;
+    }
+
+   seh_aarch64_add_unwind_element (unwind_end, 0, 0);
+}
+
+/* Mark end of current context.  */
+static void
+obj_coff_seh_endproc (const int what ATTRIBUTE_UNUSED)
+{
+  demand_empty_rest_of_line ();
+  if (!in_seh_proc)
+    {
+      as_bad (_(".seh_endproc used without .seh_proc"));
+      return;
+    }
+
+  seh_validate_seg (".seh_endproc");
+
+  seh_ctx_cur->end_addr = symbol_temp_new_now ();
+  in_seh_proc = false;
+}
+
+static void
+obj_coff_seh_startepilogue (const int what ATTRIBUTE_UNUSED)
+{
+  if (!verify_context (".seh_startepilogue")
+      || !seh_validate_seg (".seh_startepilogue"))
+    return;
+  demand_empty_rest_of_line ();
+
+  if (seh_ctx_cur->epilogue_scopes_count >= AARCH64_MAX_EPILOGUE_SCOPES)
+    as_bad (_("no epilogue scopes available."));
+
+  symbolS *epilogue_start_addr = symbol_temp_new_now ();
+  expressionS exp;
+  exp.X_op = O_subtract;
+  exp.X_add_symbol = epilogue_start_addr;
+  exp.X_op_symbol = seh_ctx_cur->start_addr;
+  exp.X_add_number = 0;
+
+  if (!resolve_expression (&exp) || exp.X_op != O_constant
+      || exp.X_add_number < 0)
+    as_bad (_(".seh_startepilogue offset expression for %s "
+	    "does not evaluate to a non-negative constant"),
+	    S_GET_NAME (epilogue_start_addr));
+
+  if (seh_ctx_cur->epilogue_scopes_count
+      >= seh_ctx_cur->epilogue_scopes_capacity)
+    {
+      const unsigned initial_capacity = 32;
+      if (seh_ctx_cur->epilogue_scopes_capacity)
+	seh_ctx_cur->epilogue_scopes_capacity *= 2;
+      else
+	seh_ctx_cur->epilogue_scopes_capacity = initial_capacity;
+
+      seh_ctx_cur->epilogue_scopes
+	= XRESIZEVEC (seh_aarch64_epilogue_scope, seh_ctx_cur->epilogue_scopes,
+		     seh_ctx_cur->epilogue_scopes_capacity);
+    }
+
+  seh_aarch64_epilogue_scope *epilogue_scope = seh_ctx_cur->epilogue_scopes
+    + seh_ctx_cur->epilogue_scopes_count;
+  epilogue_scope->epilogue_start_offset = exp.X_add_number / 4;
+  epilogue_scope->reserved = 0;
+  epilogue_scope->epilogue_start_index = 0;
+  seh_ctx_cur->epilogue_scopes_count++;
+}
+
+static void
+obj_coff_seh_endepilogue (const int what ATTRIBUTE_UNUSED)
+{
+  if (!verify_context (".seh_endepilogue")
+      || !seh_validate_seg (".seh_endepilogue"))
+    return;
+
+  demand_empty_rest_of_line ();
+
+  expressionS exp;
+  symbolS *epilogue_end_addr = symbol_temp_new_now ();
+  exp.X_op = O_subtract;
+  exp.X_add_symbol = epilogue_end_addr;
+  exp.X_op_symbol = seh_ctx_cur->start_addr;
+  exp.X_add_number = 0;
+
+  if (!resolve_expression (&exp) || exp.X_op != O_constant
+      || exp.X_add_number < 0)
+    as_bad (_(".seh_endepilogue offset expression for %s "
+	    "does not evaluate to a non-negative constant"),
+	    S_GET_NAME (epilogue_end_addr));
+
+   seh_aarch64_epilogue_scope *epilogue_scope = seh_ctx_cur->epilogue_scopes
+     + seh_ctx_cur->epilogue_scopes_count - 1;
+
+   epilogue_scope->epilogue_end_offset = exp.X_add_number;
+
+  /* End code.  */
+  seh_aarch64_add_unwind_element (unwind_end, 0, 0);
+}
+
+/* End-of-file hook.  */
+static void
+free_seh_ctx (struct seh_aarch64_context *seh_ctx)
+{
+  free (seh_ctx->func_name);
+  const seh_aarch64_func_fragment *fragment = seh_ctx->func_fragment.next;
+  while (fragment)
+    {
+      const seh_aarch64_func_fragment *next = fragment->next;
+      XDELETE (fragment);
+      fragment = next;
+    }
+  XDELETEVEC (seh_ctx->epilogue_scopes);
+  free (seh_ctx);
+}
+
+static void
+obj_coff_seh_save_reg (const int type)
+{
+  gas_assert (type >= 0 && type <= unwind_last_type);
+
+  const struct aarch64_unwind_info *info
+    = aarch64_unwind_code_data + type;
+
+  SKIP_WHITESPACE ();
+
+  char *symbol_name = NULL;
+  unsigned reg = -1;
+
+  if (info->reg_bits)
+    {
+      char name_end = get_symbol_name (&symbol_name);
+      if (info->reg_type != *symbol_name)
+	as_bad ("unexpected register name");
+
+      reg = atoi (symbol_name + 1);
+      (void) restore_line_pointer (name_end);
+
+      if (!skip_whitespace_and_comma (1))
+	return;
+
+      const unsigned reg_max = info->reg_max ? info->reg_max: 30;
+      if (reg > reg_max)
+	as_bad (_("unexpected register number"));
+    }
+
+  offsetT off = -1;
+  if (info->offset_bits)
+    {
+      off = get_absolute_expression ();
+
+      if (off < 0)
+	as_bad (_("offset is negative"));
+    }
+
+  demand_empty_rest_of_line ();
+
+  if (!in_seh_proc)
+  {
+    as_bad (_("SEH entry has not been found (missing .seh_proc)"));
+    return;
+  }
+
+  if (!info->directive || !seh_validate_seg (info->directive))
+    return;
+
+  seh_aarch64_add_unwind_element (type, off, reg);
+}
+
+/* Add a stack-allocation token to current context.  */
+static void
+obj_coff_seh_stackalloc (const int what ATTRIBUTE_UNUSED)
+{
+  const offsetT off = get_absolute_expression ();
+  demand_empty_rest_of_line ();
+
+  if (!in_seh_proc)
+    {
+      as_bad (_("SEH entry has not been found (missing .seh_proc)"));
+      return;
+    }
+
+  if (off < 0x200)
+    seh_aarch64_add_unwind_element (unwind_alloc_s, off, 0);
+  else if (off < 0x8000)
+    seh_aarch64_add_unwind_element (unwind_alloc_m, off, 0);
+  else if (off < 0x10000000)
+    seh_aarch64_add_unwind_element (unwind_alloc_l, off, 0);
+  else
+    as_bad (_(".seh_stackalloc offset is out of range"));
+}
+
+/* Data writing routines.  */
+static void
+seh_aarch64_emit_epilogue_scopes (const seh_context *seh_ctx,
+				  const uint64_t fragment_offset,
+				  const unsigned prologue_size,
+				  const unsigned first_fragment_scope,
+				  const unsigned last_fragment_scope,
+				  const bool has_phantom_prologue)
+{
+  unsigned start_index_offset = 0;
+  const seh_aarch64_epilogue_scope *scopes = seh_ctx->epilogue_scopes;
+  if (first_fragment_scope < seh_ctx->epilogue_scopes_count)
+    start_index_offset = scopes[first_fragment_scope].epilogue_start_index
+			 - prologue_size;
+  if (has_phantom_prologue)
+    {
+      if (start_index_offset == 0)
+	as_bad (_("start index offset for the epilogue cannot be 0 when "
+		"phantom prologue is used"));
+      --start_index_offset;
+    }
+
+  for (unsigned i = first_fragment_scope; i < last_fragment_scope; ++i)
+    {
+      seh_aarch64_epilogue_scope scope = seh_ctx->epilogue_scopes[i];
+      scope.epilogue_start_offset_reduced = (scope.epilogue_start_offset
+					    - fragment_offset) >> 2;
+      scope.epilogue_start_index -= start_index_offset;
+      uint32_t scope_code;
+      memcpy (&scope_code, &scope, sizeof (scope_code));
+      md_number_to_chars (frag_more (4), scope_code, 4);
+    }
+}
+
+static void
+seh_aarch64_emit_unwind_codes (const seh_context *seh_ctx,
+			       const unsigned prologue_size,
+			       const unsigned first_epilogue_index,
+			       const unsigned last_epilogue_index,
+			       const bool has_phantom_prologue)
+{
+  unsigned total_byte_count = 0;
+
+  if (has_phantom_prologue)
+    {
+      ++total_byte_count;
+      const unsigned endc_code = 0b11100101U;
+      md_number_to_chars (frag_more (1), endc_code, 1);
+    }
+
+  unsigned unwind_bytes_offset = 0;
+  for (unsigned i = 0; i < seh_ctx->unwind_codes_count; ++i)
+    {
+      const seh_aarch64_unwind_code *code = seh_ctx->unwind_codes + i;
+      const unsigned byte_count
+	= aarch64_unwind_code_data[code->type].size;
+      unwind_bytes_offset += byte_count;
+
+      if (unwind_bytes_offset > last_epilogue_index)
+	break;
+
+      if (unwind_bytes_offset > prologue_size
+	  && unwind_bytes_offset <= first_epilogue_index)
+	continue;
+
+      /*  emit unwind code bytes in big endian.  */
+      number_to_chars_bigendian (frag_more (byte_count), code->value,
+				 byte_count);
+      total_byte_count += byte_count;
+    }
+
+    /* Handle word alignment.  */
+    const unsigned required_padding = (-total_byte_count) % 4;
+    if (required_padding)
+      {
+	/* Use the nop unwind code for alignment.  */
+	const uint32_t nop_chain = 0xe3e3e3e3;
+
+	md_number_to_chars (frag_more (required_padding), nop_chain,
+			    required_padding);
+      }
+}
+
+static void
+seh_aarch64_emit_xdata_record(struct seh_aarch64_context *seh_ctx,
+			      const uintptr_t frag_size,
+			      const uintptr_t fragment_offset,
+			      const unsigned header_size,
+			      const unsigned prologue_size,
+			      const unsigned prologue_insn_count,
+			      const bool has_phantom_prologue,
+			      const unsigned first_fragment_scope,
+			      const unsigned last_fragment_scope,
+			      const unsigned first_epilogue_index,
+			      const unsigned last_epilogue_index)
+{
+  const seh_aarch64_xdata_header *header = &seh_ctx->xdata_header;
+  md_number_to_chars (frag_more (header_size), seh_ctx->xdata_header_value,
+		      header_size);
+
+  if (header->ext_epilogue_count && !header->e)
+    {
+      seh_aarch64_emit_epilogue_scopes (seh_ctx,
+					fragment_offset, prologue_size,
+					first_fragment_scope,
+					last_fragment_scope,
+					has_phantom_prologue);
+      if (has_phantom_prologue)
+	{
+	  const uint32_t epilogue_start_index_encoded = 1 << 22;
+	  const uint32_t epilogue_start_offset_encoded
+	    = (frag_size - prologue_insn_count * 4) >> 2;
+	  md_number_to_chars (frag_more (4),
+			      epilogue_start_index_encoded
+			      | epilogue_start_offset_encoded, 4);
+	}
+    }
+
+  if (header->ext_code_words)
+    seh_aarch64_emit_unwind_codes (seh_ctx, prologue_size, first_epilogue_index,
+				   last_epilogue_index, has_phantom_prologue);
+
+  if (header->x == 1)
+    {
+      if (seh_ctx->handler.X_op == O_symbol)
+	seh_ctx->handler.X_op = O_symbol_rva;
+
+      emit_expr (&seh_ctx->handler, 4);
+
+      /* Emit the fragment offset.  */
+      md_number_to_chars (frag_more (4), fragment_offset, 4);
+
+      /* Use the same SEH handler data for all fragments.
+	 The SEH handler data is emitted after the last fragment.  */
+      expressionS exp;
+      memset (&exp, 0, sizeof (expressionS));
+      exp.X_op = O_symbol_rva;
+      exp.X_add_symbol = seh_ctx->handler_data_xdata_addr;
+      emit_expr (&exp, 4);
+    }
+}
+
+static bool
+seh_function_size (const struct seh_aarch64_context *seh_ctx,
+		  uintptr_t *size)
+{
+  fragS *start_frag, *end_frag;
+  addressT start_offset, end_offset;
+  start_frag = symbol_get_frag_and_value (seh_ctx->start_addr, &start_offset);
+  end_frag = symbol_get_frag_and_value (seh_ctx->end_addr, &end_offset);
+
+  intptr_t func_size = end_frag->fr_address + end_offset
+		       - start_frag->fr_address - start_offset;
+  if (func_size < 0)
+    return false;
+
+  *size = func_size;
+  return true;
+}
+
+/* Write out the xdata information for one function.  */
+static void
+seh_aarch64_write_function_xdata (struct seh_aarch64_context *seh_ctx)
+{
+  if (!seh_ctx->unwind_codes_byte_count)
+    return;
+
+  const segT save_seg = now_seg;
+  const subsegT save_subseg = now_subseg;
+
+  switch_xdata (seh_ctx->subsection, seh_ctx->code_seg);
+
+  /* Set 4-byte alignment.  */
+  frag_align (2, 0, 0);
+
+  uintptr_t func_size = 0;
+  if (!seh_function_size (seh_ctx, &func_size))
+    {
+      as_bad (_("the function size for %s has not been evaluated"),
+	      seh_ctx->func_name);
+      return;
+    }
+
+  /* The large functions should be split into fragments smaller than 1MB with
+     4 bytes alignment.
+     https://learn.microsoft.com/en-us/cpp/build/arm64-exception-handling?view=msvc-170#large-functions.  */
+  const unsigned max_frag_size = (1 << 20) - 4;
+  const bool is_fragmented_function = func_size > max_frag_size;
+
+  unsigned prologue_insn_count = 0;
+  for (unsigned i = 0; i < seh_ctx->unwind_codes_count; ++i)
+    {
+      if (seh_ctx->unwind_codes[i].type == unwind_end)
+	{
+	  prologue_insn_count = i + 1;
+	  break;
+	}
+    }
+
+  unsigned prologue_size = seh_ctx->unwind_codes_byte_count;
+
+  seh_aarch64_func_fragment *fragment;
+  fragment = &seh_ctx->func_fragment;
+  uintptr_t fragment_offset = 0;
+  unsigned first_fragment_scope = 0;
+  unsigned last_fragment_scope = 0;
+
+  /* Large functions (>= 1MB) will be split into multiple fragments.
+     However, it is expected the most of the functions will have only one
+     fragment. This loop iterates fragments and emit them.  */
+  while (true)
+    {
+      fragment->xdata_addr = symbol_temp_new_now ();
+      fragment->offset = fragment_offset;
+      fragment->next = NULL;
+
+      /* Calculate current fragment size.  */
+      uintptr_t frag_size = func_size - fragment_offset;
+      if (frag_size > max_frag_size)
+	frag_size = max_frag_size;
+
+      const bool is_last_frag = (fragment_offset + frag_size) == func_size;
+
+      /* If it is a fragmented function, the epilogue range should be calculated
+	 and will be emitted for the current fragment, otherwise all epilogues
+	 will be emitted.  */
+      if (!is_fragmented_function)
+	last_fragment_scope = seh_ctx->epilogue_scopes_count;
+      else
+	{
+	  first_fragment_scope = last_fragment_scope;
+	  for (unsigned i = first_fragment_scope;
+	       i < seh_ctx->epilogue_scopes_count; ++i)
+	    {
+	      const seh_aarch64_epilogue_scope *scope
+		= seh_ctx->epilogue_scopes;
+	      scope += i;
+	      if (scope->epilogue_start_offset >= (fragment_offset + frag_size))
+		break;
+
+	      if (scope->epilogue_end_offset >= (fragment_offset + frag_size))
+		{
+		  frag_size = scope->epilogue_start_offset - fragment_offset;
+		  break;
+		}
+
+	      if (scope->epilogue_start_offset >= fragment_offset)
+		last_fragment_scope = i + 1;
+	    }
+	}
+
+      seh_aarch64_xdata_header *header = &seh_ctx->xdata_header;
+      const seh_aarch64_epilogue_scope *scopes = seh_ctx->epilogue_scopes;
+
+      /* Initialize the .xdata record.  */
+      const uint32_t func_length_encoded = frag_size >> 2;
+      header->func_length = func_length_encoded;
+      header->vers = 0;
+      header->e = 0;
+      header->code_words = 0;
+      header->epilogue_count = 0;
+
+      header->ext_code_words = 0;
+      header->ext_epilogue_count = last_fragment_scope
+				   - first_fragment_scope;
+      header->reserved = 0;
+
+      /* Calculate epilogue indexes for the current fragment.  */
+      unsigned first_epilogue_index = 0;
+      unsigned last_epilogue_index = 0;
+      if (!header->ext_epilogue_count)
+	{
+	  first_epilogue_index = prologue_size;
+	  last_epilogue_index = prologue_size;
+	}
+      else
+	{
+	  const seh_aarch64_epilogue_scope *scope;
+	  scope = scopes + first_fragment_scope;
+	  first_epilogue_index = scope->epilogue_start_index;
+	  last_epilogue_index = seh_ctx->unwind_codes_byte_count;
+	}
+
+      /* Calculate how many unwind bytes will be emitted in .xdata record.  */
+      unsigned unwind_bytes = prologue_size;
+
+      /* Check if current fragment has a phantom prologue. If yes, then
+	 the unwinding size should be adjusted.  */
+      const bool has_phantom_prologue = is_fragmented_function && is_last_frag;
+      if (has_phantom_prologue && unwind_bytes)
+	{
+	  /* One more epilogue scope and unwind code are emitted with phantom
+	     prologue.  */
+	  unwind_bytes += 1;
+	  ++header->ext_epilogue_count;
+	}
+
+      /* Calculate the number of code words with 4-byte alignment.  */
+      header->ext_code_words = (unwind_bytes + 3) / 4;
+
+      /* Check if short or extended header for a .xdata record should be
+	 used.  */
+      unsigned header_size = 8;
+      if ((header->ext_code_words != 0 || header->ext_epilogue_count != 0)
+	  && header->ext_code_words < 32
+	  && header->ext_epilogue_count < 32)
+	{
+	  header_size = 4;
+	  header->code_words = header->ext_code_words;
+	  header->epilogue_count = header->ext_epilogue_count;
+	  if (header->epilogue_count == 1)
+	    {
+	      header->e = 1;
+	      if (has_phantom_prologue)
+		header->ext_epilogue_count = 0;
+	      else
+		{
+		  const seh_aarch64_epilogue_scope *scope;
+		  scope = scopes + first_fragment_scope;
+		  header->ext_epilogue_count = scope->epilogue_start_index;
+		}
+	    }
+	}
+
+      /* Emit a .xdata record for the current fragment.  */
+      seh_aarch64_emit_xdata_record(seh_ctx, frag_size, fragment_offset,
+				    header_size,
+				    prologue_size, prologue_insn_count,
+				    has_phantom_prologue,
+				    first_fragment_scope, last_fragment_scope,
+				    first_epilogue_index, last_epilogue_index);
+
+      fragment_offset += frag_size;
+      /* Exit the loop if it is the latest fragment.  */
+      if (is_last_frag)
+	break;
+
+      /* Allocate a new fragment that will be used also for emitting a .pdata
+	 record.  */
+      fragment->next = XCNEW (seh_aarch64_func_fragment);
+      fragment = fragment->next;
+    }
+
+  subseg_set (save_seg, save_subseg);
+}
+
+/* Write out pdata for one function.  */
+static void
+seh_aarch64_write_function_pdata (const seh_context *seh_ctx)
+{
+  expressionS exp;
+  const segT save_seg = now_seg;
+  const subsegT save_subseg = now_subseg;
+  memset (&exp, 0, sizeof (expressionS));
+  switch_pdata (seh_ctx->code_seg);
+
+  if (seh_ctx->unwind_codes_byte_count)
+    {
+      const seh_aarch64_func_fragment *fragment = &seh_ctx->func_fragment;
+      while (fragment)
+	{
+	  exp.X_op = O_symbol_rva;
+	  exp.X_add_number = fragment->offset;
+	  exp.X_add_symbol = seh_ctx->start_addr;
+	  emit_expr (&exp, 4);
+
+	  exp.X_op = O_symbol_rva;
+	  /* TODO: Implementing packed unwind data.  */
+	  exp.X_add_number = 0;
+	  exp.X_add_symbol = fragment->xdata_addr;
+	  emit_expr (&exp, 4);
+	  fragment = fragment->next;
+	}
+    }
+
+  subseg_set (save_seg, save_subseg);
+}
+
+void
+seh_aarch64_write_data (void)
+{
+  if (in_seh_proc)
+  {
+    as_bad (_("open SEH entry at end of file (missing .seh_endproc)"));
+    return;
+  }
+
+  if (!seh_ctx_root)
+    return;
+
+  struct seh_aarch64_context *seh_ctx = seh_ctx_root;
+  seh_ctx_root = NULL;
+
+  /* Relax the segment to be able to calculate the function sizes.  */
+  subsegs_finish_section (seh_ctx->code_seg);
+  const segment_info_type *seginfo = seg_info (seh_ctx->code_seg);
+  relax_segment (seginfo->frchainP->frch_root, seh_ctx->code_seg, 0);
+
+  while (seh_ctx)
+  {
+    seh_aarch64_write_function_xdata (seh_ctx);
+    seh_aarch64_write_function_pdata (seh_ctx);
+    struct seh_aarch64_context *next = seh_ctx->next;
+    free_seh_ctx (seh_ctx);
+    seh_ctx = next;
+  }
+}
+
+void
+obj_coff_seh_do_final (void)
+{
+}
diff --git a/gas/config/obj-coff-seh-aarch64.h b/gas/config/obj-coff-seh-aarch64.h
new file mode 100644
index 00000000000..226e40c2312
--- /dev/null
+++ b/gas/config/obj-coff-seh-aarch64.h
@@ -0,0 +1,251 @@
+/* SEH .pdata/.xdata COFF object file format on AArch64
+   Copyright (C) 2026 Free Software Foundation, Inc.
+
+   This file is part of GAS.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+/* SEH COFF AArch64 implementation partially intersects with the x64
+   version, however it has a different extension to the unwind codes.
+   It emits SEH data to pdata and xdata sections.  In some cases SEH
+   data could be emitted to a packed record in the pdata section
+   without the need for data in the xdata section.  However, the packed
+   pdata record is not implemented yet.
+
+   The current implementation does not include:
+   - Packed .pdata record.
+   - Support for AdvSIMD and SVE.
+   - Epilogue start index different than 0.  */
+
+#ifndef OBJ_COFF_SEH_AARCH64_H
+#define OBJ_COFF_SEH_AARCH64_H
+
+/* Unwind codes for AArch64 are described at
+   https://learn.microsoft.com/en-us/cpp/build/arm64-exception-handling?view=msvc-170#unwind-codes.  */
+
+typedef enum seh_aarch64_unwind_types
+{
+  unwind_alloc_s,
+  unwind_alloc_m,
+  unwind_alloc_l,
+  unwind_save_reg,
+  unwind_save_reg_x,
+  unwind_save_regp,
+  unwind_save_regp_x,
+  unwind_save_fregp,
+  unwind_save_fregp_x,
+  unwind_save_freg,
+  unwind_save_freg_x,
+  unwind_save_lrpair,
+  unwind_save_fplr,
+  unwind_save_fplr_x,
+  unwind_save_r19r20_x,
+  unwind_add_fp,
+  unwind_set_fp,
+  unwind_save_next,
+  unwind_nop,
+  unwind_pac_sign_lr,
+  unwind_end,
+  unwind_end_c,
+  unwind_last_type = unwind_end_c
+} seh_aarch64_unwind_types;
+
+#define SEH_CMDS						      \
+  /* Start a function that contains SEH.  */			      \
+  {"seh_proc", obj_coff_seh_proc, 0},				      \
+								      \
+  /* End a function that contains SEH.  */			      \
+  {"seh_endproc", obj_coff_seh_endproc, 0},			      \
+								      \
+  /* End a SEH prologue with unwinding codes.  */			      \
+  {"seh_endprologue", obj_coff_seh_endprologue, 0},		      \
+								      \
+  /* Allocate stack.  */					      \
+  {"seh_stackalloc", obj_coff_seh_stackalloc, 0},		      \
+								      \
+  /* Set a SEH handler.  */					      \
+  {"seh_handler", obj_coff_seh_handler, 0},			      \
+								      \
+  /* Set a SEH handler data.  */				      \
+  {"seh_handlerdata", obj_coff_seh_handlerdata, 0},		      \
+								      \
+  /* Switch back to the code section.  */			      \
+  {"seh_code", obj_coff_seh_code, 0},				      \
+								      \
+  /* Start a SEH epilogue.  */					      \
+  {"seh_startepilogue", obj_coff_seh_startepilogue, 0},		      \
+								      \
+  /* End a SEH epilogue.  */					      \
+  {"seh_endepilogue", obj_coff_seh_endepilogue, 0},		      \
+								      \
+  /* Save an 'x' register.  */					      \
+  {"seh_save_reg", obj_coff_seh_save_reg, unwind_save_reg},	      \
+								      \
+  /* Save an 'x' register with a pre-indexed offset.  */	      \
+  {"seh_save_reg_x", obj_coff_seh_save_reg, unwind_save_reg_x},	      \
+								      \
+  /* Save an 'x' register pair.  */				      \
+  {"seh_save_regp", obj_coff_seh_save_reg, unwind_save_regp},	      \
+								      \
+  /* Save an 'x' register pair with a pre-indexed offset.  */	      \
+  {"seh_save_regp_x", obj_coff_seh_save_reg, unwind_save_regp_x},     \
+								      \
+  /* Save an 'x' register and lr.  */				      \
+  {"seh_save_lrpair", obj_coff_seh_save_reg, unwind_save_lrpair},     \
+								      \
+  /* Save a 'd' register pair.  */				      \
+  {"seh_save_fregp", obj_coff_seh_save_reg, unwind_save_fregp},	      \
+								      \
+  /* Save a 'd' register pair with a pre-indexed offset.  */	      \
+  {"seh_save_fregp_x", obj_coff_seh_save_reg, unwind_save_fregp_x},   \
+								      \
+  /* Save a 'd' register.  */					      \
+  {"seh_save_freg", obj_coff_seh_save_reg, unwind_save_freg},	      \
+								      \
+  /* Save a 'd' register with a pre-indexed offset.  */		      \
+  {"seh_save_freg_x", obj_coff_seh_save_reg, unwind_save_freg_x},     \
+								      \
+  /* Save fp and lr registers.  */				      \
+  {"seh_save_fplr", obj_coff_seh_save_reg, unwind_save_fplr},	      \
+								      \
+  /* Save fp and lr registers with a pre-indexed offset.  */	      \
+  {"seh_save_fplr_x", obj_coff_seh_save_reg, unwind_save_fplr_x},     \
+								      \
+  /* Save x19 and x20 registers with a pre-indexed offset.  */	      \
+  {"seh_save_r19r20_x", obj_coff_seh_save_reg, unwind_save_r19r20_x}, \
+								      \
+  /* Set fp by sp + offset.  */					      \
+  {"seh_add_fp", obj_coff_seh_save_reg, unwind_add_fp},		      \
+								      \
+  /* Unwind operation is not required.  */			      \
+  {"seh_nop", obj_coff_seh_save_reg, unwind_nop},		      \
+								      \
+  /* Sign the return address in lr with pacibsp.  */		      \
+  {"seh_pac_sign_lr", obj_coff_seh_save_reg, unwind_pac_sign_lr},     \
+								      \
+  /* Set fp by sp.  */						      \
+  {"seh_set_fp", obj_coff_seh_save_reg, unwind_set_fp},		      \
+								      \
+  /* Save next register pair.  */				      \
+  {"seh_save_next", obj_coff_seh_save_reg, unwind_save_next},
+
+/* AArch64 exceptions handling and unwinding structures.
+   https://learn.microsoft.com/en-us/cpp/build/arm64-exception-handling#pdata-records.  */
+
+typedef struct seh_aarch64_unwind_code
+{
+  unsigned value;
+  seh_aarch64_unwind_types type;
+} seh_aarch64_unwind_code;
+
+typedef struct seh_aarch64_packed_unwind_data
+{
+  uint32_t flag : 2;
+  uint32_t func_length : 11;
+  uint32_t frame_size : 9;
+  uint32_t cr : 2;
+  uint32_t h : 1;
+  uint32_t regI : 4;
+  uint32_t regF : 3;
+} seh_aarch64_packed_unwind_data;
+
+typedef struct seh_aarch64_except_info
+{
+  uint32_t flag : 2;
+  uint32_t except_info_rva : 30;
+} seh_aarch64_except_info;
+
+typedef union seh_aarch64_unwind_info
+{
+  seh_aarch64_except_info except_info;
+  seh_aarch64_packed_unwind_data packed_unwind_data;
+} seh_aarch64_unwind_info;
+
+typedef struct seh_aarch64_xdata_header
+{
+  uint32_t func_length : 18;
+  uint32_t vers : 2;
+  uint32_t x : 1;
+  uint32_t e : 1;
+  uint32_t epilogue_count : 5;
+  uint32_t code_words : 5;
+  uint32_t ext_epilogue_count : 16;
+  uint32_t ext_code_words : 8;
+  uint32_t reserved : 8;
+} seh_aarch64_xdata_header;
+
+typedef struct seh_aarch64_epilogue_scope
+{
+  uint32_t epilogue_start_offset_reduced : 18;
+  uint32_t reserved : 4;
+  uint32_t epilogue_start_index : 10;
+  bfd_vma epilogue_start_offset;
+  bfd_vma epilogue_end_offset;
+} seh_aarch64_epilogue_scope;
+
+typedef struct seh_aarch64_func_fragment
+{
+  bfd_vma offset;
+  symbolS *xdata_addr;
+  struct seh_aarch64_func_fragment *next;
+} seh_aarch64_func_fragment;
+
+/* AARCH64_MAX_UNWIND_CODES is limited by
+   seh_aarch64_xdata_header::ext_code_words.  */
+#define AARCH64_MAX_UNWIND_CODES (255 * 4)
+#define AARCH64_MAX_UNWIND_CODES_SIZE (255 * 4)
+/* AARCH64_MAX_EPILOGUE_SCOPES is limited by
+   seh_aarch64_xdata_header::ext_epilogue_count.  */
+#define AARCH64_MAX_EPILOGUE_SCOPES 65535
+
+typedef struct seh_aarch64_context
+{
+  struct seh_aarch64_context *next;
+
+  /* Initial code-segment.  */
+  segT code_seg;
+  /* Function name.  */
+  char *func_name;
+  /* BeginAddress.  */
+  symbolS *start_addr;
+  /* EndAddress.  */
+  symbolS *end_addr;
+  /* PrologueEnd.  */
+  symbolS *endprologue_addr;
+
+  symbolS *handler_data_xdata_addr;
+  /* ExceptionHandler.  */
+  expressionS handler;
+  /* ExceptionHandlerData.  */
+  expressionS handler_data;
+
+  subsegT subsection;
+
+  union {
+    seh_aarch64_xdata_header xdata_header;
+    valueT xdata_header_value;
+  };
+  unsigned unwind_codes_count;
+  unsigned unwind_codes_byte_count;
+  seh_aarch64_unwind_code unwind_codes[AARCH64_MAX_UNWIND_CODES];
+  unsigned epilogue_scopes_count;
+  unsigned epilogue_scopes_capacity;
+  seh_aarch64_epilogue_scope *epilogue_scopes;
+  /* The function fragments.  */
+  seh_aarch64_func_fragment func_fragment;
+} seh_context;
+
+#endif /* OBJ_COFF_SEH_AARCH64_H.  */
diff --git a/gas/config/obj-coff-seh-shared.c b/gas/config/obj-coff-seh-shared.c
index 717a7d345ef..b99a6bb67ee 100644
--- a/gas/config/obj-coff-seh-shared.c
+++ b/gas/config/obj-coff-seh-shared.c
@@ -19,7 +19,13 @@
    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
    02110-1301, USA.  */
 
+#if defined (COFFAARCH64)
+#include "obj-coff-seh-aarch64.h"
+typedef struct seh_aarch64_context seh_context_t;
+#else
 #include "obj-coff-seh.h"
+typedef struct seh_context seh_context_t;
+#endif
 
 /* Private segment collection list.  */
 struct seh_seg_list {
@@ -28,7 +34,7 @@ struct seh_seg_list {
   char *seg_name;
 };
 
-static struct seh_context *seh_ctx_cur = NULL;
+static seh_context_t *seh_ctx_cur = NULL;
 
 static htab_t seh_hash;
 
diff --git a/gas/config/obj-coff.c b/gas/config/obj-coff.c
index 7732c0af911..b08295019d8 100644
--- a/gas/config/obj-coff.c
+++ b/gas/config/obj-coff.c
@@ -55,7 +55,11 @@ static const char weak_altprefix[] = ".weak.";
 #endif /* TE_PE */
 
 #include "obj-coff-seh-shared.c"
+#if defined (COFFAARCH64)
+#include "obj-coff-seh-aarch64.c"
+#else
 #include "obj-coff-seh.c"
+#endif
 
 typedef struct
   {
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index fb58bcca9b1..c672f284a48 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10459,6 +10459,16 @@ aarch64_cleanup (void)
     }
 }
 
+#if defined (OBJ_COFF)
+/* Called after all assembly has been done.  */
+
+void
+aarch64_md_finish (void)
+{
+  seh_aarch64_write_data();
+}
+#endif /* OBJ_COFF.  */
+
 #ifdef OBJ_ELF
 /* Remove any excess mapping symbols generated for alignment frags in
    SEC.  We may have created a mapping symbol before a zero byte
diff --git a/gas/config/tc-aarch64.h b/gas/config/tc-aarch64.h
index d1fb4c9058b..6446ac8efb8 100644
--- a/gas/config/tc-aarch64.h
+++ b/gas/config/tc-aarch64.h
@@ -82,6 +82,12 @@ struct aarch64_fix
 
 #define tc_frob_section(S) aarch64_frob_section (S)
 
+#if defined (OBJ_COFF)
+#define md_finish aarch64_md_finish
+extern void aarch64_md_finish (void);
+extern void seh_aarch64_write_data (void);
+#endif
+
 /* The key used to sign a function's return address.  */
 enum pointer_auth_key {
   AARCH64_PAUTH_KEY_A,
diff --git a/gas/testsuite/gas/pe/pe.exp b/gas/testsuite/gas/pe/pe.exp
index e25de3cfa9d..cc7701587ac 100644
--- a/gas/testsuite/gas/pe/pe.exp
+++ b/gas/testsuite/gas/pe/pe.exp
@@ -63,6 +63,9 @@ if ([istarget "x86_64-*-mingw*"]) then {
 # This test is only for AArch64
 if {[istarget "aarch64-*-pe*"] || [istarget "aarch64-*-mingw*"]} {
 	run_dump_test "pe-aarch64"
+	run_dump_test "seh-aarch64"
+	run_dump_test "seh-aarch64-large-func"
+	run_list_test "seh-aarch64-error" ""
 }
 
 # Big obj
diff --git a/gas/testsuite/gas/pe/seh-aarch64-error.l b/gas/testsuite/gas/pe/seh-aarch64-error.l
new file mode 100644
index 00000000000..2d7f2c055f6
--- /dev/null
+++ b/gas/testsuite/gas/pe/seh-aarch64-error.l
@@ -0,0 +1,110 @@
+.*: Assembler messages:
+.*:2: Error: .seh_endprologue used outside of .seh_proc block
+.*:3: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:4: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:5: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:6: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:7: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:8: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:9: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:10: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:11: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:12: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:13: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:14: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:15: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:16: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:17: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:18: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:19: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:20: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:21: Error: .seh_endproc used without .seh_proc
+.*:23: Error: .seh_proc requires function label name
+.*:24: Error: previous SEH entry not closed \(missing .seh_endproc\)
+.*:29: Error: offset overflows expected range
+.*:30: Error: offset should be divided by 16
+.*:31: Error: .seh_stackalloc offset is out of range
+.*:33: Error: unexpected register number
+.*:34: Error: unexpected register number
+.*:35: Error: unexpected register name
+.*:36: Error: offset is negative
+.*:36: Error: offset overflows expected range
+.*:38: Error: offset should be divided by 8
+.*:39: Error: offset overflows expected range
+.*:41: Error: unexpected register number
+.*:42: Error: unexpected register number
+.*:43: Error: unexpected register name
+.*:44: Error: offset is negative
+.*:44: Error: offset overflows expected range
+.*:46: Error: offset should be divided by 8
+.*:47: Error: offset overflows expected range
+.*:49: Error: unexpected register number
+.*:50: Error: unexpected register number
+.*:51: Error: unexpected register name
+.*:52: Error: unexpected register number
+.*:53: Error: offset is negative
+.*:53: Error: offset overflows expected range
+.*:55: Error: offset should be divided by 8
+.*:56: Error: offset overflows expected range
+.*:58: Error: unexpected register number
+.*:59: Error: unexpected register number
+.*:60: Error: unexpected register name
+.*:61: Error: unexpected register number
+.*:62: Error: offset is negative
+.*:62: Error: offset overflows expected range
+.*:64: Error: offset should be divided by 8
+.*:65: Error: offset overflows expected range
+.*:67: Error: unexpected register number
+.*:67: Error: unexpected register number
+.*:68: Error: unexpected register number
+.*:69: Error: unexpected register name
+.*:70: Error: unexpected register number
+.*:71: Error: offset is negative
+.*:71: Error: offset overflows expected range
+.*:73: Error: offset should be divided by 8
+.*:74: Error: offset overflows expected range
+.*:76: Error: unexpected register number
+.*:77: Error: unexpected register number
+.*:78: Error: unexpected register name
+.*:79: Error: offset is negative
+.*:79: Error: offset overflows expected range
+.*:81: Error: offset should be divided by 8
+.*:82: Error: offset overflows expected range
+.*:84: Error: unexpected register number
+.*:85: Error: unexpected register number
+.*:86: Error: unexpected register name
+.*:87: Error: offset is negative
+.*:87: Error: offset overflows expected range
+.*:89: Error: offset should be divided by 8
+.*:90: Error: offset overflows expected range
+.*:92: Error: unexpected register number
+.*:93: Error: unexpected register number
+.*:94: Error: unexpected register name
+.*:95: Error: offset is negative
+.*:95: Error: offset overflows expected range
+.*:97: Error: offset should be divided by 8
+.*:98: Error: offset overflows expected range
+.*:100: Error: unexpected register number
+.*:101: Error: unexpected register number
+.*:102: Error: unexpected register name
+.*:103: Error: offset is negative
+.*:103: Error: offset overflows expected range
+.*:105: Error: offset should be divided by 8
+.*:106: Error: offset overflows expected range
+.*:108: Error: offset is negative
+.*:108: Error: offset overflows expected range
+.*:110: Error: offset should be divided by 8
+.*:111: Error: offset overflows expected range
+.*:113: Error: offset is negative
+.*:113: Error: offset overflows expected range
+.*:115: Error: offset should be divided by 8
+.*:116: Error: offset overflows expected range
+.*:118: Error: offset is negative
+.*:118: Error: offset overflows expected range
+.*:120: Error: offset should be divided by 8
+.*:121: Error: offset overflows expected range
+.*:123: Error: offset is negative
+.*:123: Error: offset overflows expected range
+.*:125: Error: offset should be divided by 8
+.*:126: Error: offset overflows expected range
+.*: Error: open SEH entry at end of file \(missing .seh_endproc\)
diff --git a/gas/testsuite/gas/pe/seh-aarch64-error.s b/gas/testsuite/gas/pe/seh-aarch64-error.s
new file mode 100644
index 00000000000..dc4118b7390
--- /dev/null
+++ b/gas/testsuite/gas/pe/seh-aarch64-error.s
@@ -0,0 +1,128 @@
+	.text
+	.seh_endprologue
+	.seh_stackalloc 16
+	.seh_save_reg x19, 0
+	.seh_save_reg_x x19, 16
+	.seh_save_regp x19, 32
+	.seh_save_regp_x x19, 48
+	.seh_save_lrpair x19, 64
+	.seh_save_fregp d8, 80
+	.seh_save_fregp_x d8, 96
+	.seh_save_freg d8, 112
+	.seh_save_freg_x d8, 128
+	.seh_save_fplr 144
+	.seh_save_fplr_x 160
+	.seh_save_r19r20_x 176
+	.seh_add_fp 192
+	.seh_nop
+	.seh_pac_sign_lr
+	.seh_set_fp
+	.seh_save_next
+	.seh_endproc
+
+	.seh_proc
+	.seh_proc foo
+	.seh_endproc
+
+	.seh_proc foo
+
+	.seh_stackalloc -16
+	.seh_stackalloc 268435455
+	.seh_stackalloc 268435456
+
+	.seh_save_reg x18, 0
+	.seh_save_reg x31, 0
+	.seh_save_reg d19, 0
+	.seh_save_reg x19, -8
+	.seh_save_reg x19, 504
+	.seh_save_reg x19, 511
+	.seh_save_reg x19, 512
+
+	.seh_save_reg_x x18, 16
+	.seh_save_reg_x x31, 16
+	.seh_save_reg_x d19, 16
+	.seh_save_reg_x x19, -8
+	.seh_save_reg_x x19, 256
+	.seh_save_reg_x x19, 263
+	.seh_save_reg_x x19, 264
+
+	.seh_save_regp x18, 32
+	.seh_save_regp x31, 32
+	.seh_save_regp d19, 32
+	.seh_save_regp x30, 32
+	.seh_save_regp x19, -8
+	.seh_save_regp x19, 504
+	.seh_save_regp x19, 511
+	.seh_save_regp x19, 512
+
+	.seh_save_regp_x x18, 48
+	.seh_save_regp_x x31, 48
+	.seh_save_regp_x d19, 48
+	.seh_save_regp_x x30, 48
+	.seh_save_regp_x x19, -8
+	.seh_save_regp_x x19, 512
+	.seh_save_regp_x x19, 519
+	.seh_save_regp_x x19, 520
+
+	.seh_save_lrpair x18, 64
+	.seh_save_lrpair x31, 64
+	.seh_save_lrpair d19, 64
+	.seh_save_lrpair x20, 64
+	.seh_save_lrpair x19, -8
+	.seh_save_lrpair x19, 504
+	.seh_save_lrpair x19, 511
+	.seh_save_lrpair x19, 512
+
+	.seh_save_fregp d7, 80
+	.seh_save_fregp d16, 80
+	.seh_save_fregp x8, 80
+	.seh_save_fregp d8, -8
+	.seh_save_fregp d8, 504
+	.seh_save_fregp d8, 511
+	.seh_save_fregp d8, 512
+
+	.seh_save_fregp_x d7, 96
+	.seh_save_fregp_x d16, 96
+	.seh_save_fregp_x x8, 96
+	.seh_save_fregp_x d8, -8
+	.seh_save_fregp_x d8, 512
+	.seh_save_fregp_x d8, 519
+	.seh_save_fregp_x d8, 520
+
+	.seh_save_freg d7, 112
+	.seh_save_freg d16, 112
+	.seh_save_freg x8, 112
+	.seh_save_freg d8, -8
+	.seh_save_freg d8, 504
+	.seh_save_freg d8, 511
+	.seh_save_freg d8, 512
+
+	.seh_save_freg_x d7, 128
+	.seh_save_freg_x d16, 128
+	.seh_save_freg_x x8, 128
+	.seh_save_freg_x d8, -8
+	.seh_save_freg_x d8, 256
+	.seh_save_freg_x d8, 263
+	.seh_save_freg_x d8, 264
+
+	.seh_save_fplr -8
+	.seh_save_fplr 504
+	.seh_save_fplr 511
+	.seh_save_fplr 512
+
+	.seh_save_fplr_x -8
+	.seh_save_fplr_x 512
+	.seh_save_fplr_x 519
+	.seh_save_fplr_x 520
+
+	.seh_save_r19r20_x -8
+	.seh_save_r19r20_x 248
+	.seh_save_r19r20_x 255
+	.seh_save_r19r20_x 256
+
+	.seh_add_fp -8
+	.seh_add_fp 2040
+	.seh_add_fp 2047
+	.seh_add_fp 2048
+
+	.seh_endprologue
diff --git a/gas/testsuite/gas/pe/seh-aarch64-large-func.d b/gas/testsuite/gas/pe/seh-aarch64-large-func.d
new file mode 100644
index 00000000000..61338de5145
--- /dev/null
+++ b/gas/testsuite/gas/pe/seh-aarch64-large-func.d
@@ -0,0 +1,53 @@
+#objdump: -s -j .xdata
+#name: PEP aarch64 SEH large function
+
+.*:     file format pe-aarch64-little
+
+Contents of section .xdata:
+
+# .xdata SEH record
+# 0x0813ffff  code-words: 1
+#             epilogue-count: 0
+#             single-epilogue-in-header: 0
+#             exception-data: 1
+#             version: 0
+#             function-size: 1048572
+# 0x01         .seh_stackalloc 16
+# 0xe4        end
+# 0xe3        nop
+# 0xe3        nop
+# 0x00000000  seh-handler
+# 0x00000000  fragment-offset
+# 0x0000003c  seh-handle-data-address
+# 0x0813ffff  code-words: 1
+#             epilogue-count: 0
+#             single-epilogue-in-header: 0
+#             exception-data: 1
+#             version: 0
+#             function-size: 1048572
+# 0x01        .seh_stackalloc 16
+# 0xe4        end
+# 0xe3        nop
+# 0xe3        nop
+# 0x00000000  seh-handler
+# 0x000ffffc  fragment-offset
+# 0x0000003c  seh-handle-data-address
+# 0x087002ca  code-words: 1
+#             epilogue-count: 0
+#             single-epilogue-in-header: 0
+#             exception-data: 1
+#             version: 0
+#             function-size: 2856
+# 0xe5        end_c
+# 0x01         .seh_stackalloc 16
+# 0xe4        end
+# 0xe3        nop
+# 0x00000000  seh-handler
+# 0x001ffff8  fragment-offset
+# 0x0000003c  seh-handle-data-address
+# 0x00000001  long 1 (seh_handlerdata)
+
+ 0000 ffff1308 01e4e3e3 00000000 00000000  .*
+ 0010 3c000000 ffff1308 01e4e3e3 00000000  .*
+ 0020 fcff0f00 3c000000 ca027008 e501e4e3  .*
+ 0030 00000000 f8ff1f00 3c000000 01000000  .*
\ No newline at end of file
diff --git a/gas/testsuite/gas/pe/seh-aarch64-large-func.s b/gas/testsuite/gas/pe/seh-aarch64-large-func.s
new file mode 100644
index 00000000000..4e7d4772b65
--- /dev/null
+++ b/gas/testsuite/gas/pe/seh-aarch64-large-func.s
@@ -0,0 +1,13 @@
+	.text
+	.seh_proc	foo
+foo:
+	.seh_stackalloc 16
+	.seh_endprologue
+	.rept 2100000 / 4
+	nop
+	.endr
+	.seh_handler _ZN9exception6handleEPvS0_S0_S0_, @except
+	.seh_handlerdata
+	.long 1
+	.seh_code
+	.seh_endproc
diff --git a/gas/testsuite/gas/pe/seh-aarch64.d b/gas/testsuite/gas/pe/seh-aarch64.d
new file mode 100644
index 00000000000..218366ab6b0
--- /dev/null
+++ b/gas/testsuite/gas/pe/seh-aarch64.d
@@ -0,0 +1,66 @@
+#objdump: -s -j .xdata
+#name: PEP aarch64 SEH
+
+.*:     file format pe-aarch64-little
+
+Contents of section .xdata:
+
+# .xdata SEH record
+# 0x98700000  code-words: 19
+#             epilogue-count: 1
+#             single-epilogue-in-header: 1
+#             exception-data: 1
+#             version: 0
+#             function-size: 0
+# 0xe6        .seh_save_next
+# 0xe1        .seh_save_fp
+# 0xfc        .seh_pac_sign_lr
+# 0xe3        .seh_nop
+# 0xe218      .seh_add_fp 192
+# 0x36        .seh_save_r19r20_x 176
+# 0x93        .seh_save_fplr_x 160
+# 0x52        .seh_save_fplr 144
+# 0xdeef      .seh_save_freg_x d15, 128
+# 0xde2f      .seh_save_freg_x d9, 128
+# 0xde0f      .seh_save_freg_x d8, 128
+# 0xddce      .seh_save_freg d15, 112
+# 0xdc4e      .seh_save_freg d9, 112
+# 0xdc0e      .seh_save_freg d8, 112
+# 0xdbcb      .seh_save_fregp_x d15, 96
+# 0xda4b      .seh_save_fregp_x d9, 96
+# 0xda0b      .seh_save_fregp_x d8, 96
+# 0xd9ca      .seh_save_fregp d15, 80
+# 0xd84a      .seh_save_fregp d9, 80
+# 0xd80a      .seh_save_fregp d8, 80
+# 0xd748      .seh_save_lrpair x29, 64
+# 0xd648      .seh_save_lrpair x21, 64
+# 0xd608      .seh_save_lrpair x19, 64
+# 0xce85      .seh_save_regp_x x29, 48
+# 0xcc45      .seh_save_regp_x x20, 48
+# 0xcc05      .seh_save_regp_x x19, 48
+# 0xca84      .seh_save_regp x29, 32
+# 0xc844      .seh_save_regp x20, 32
+# 0xc804      .seh_save_regp x19, 32
+# 0xd561      .seh_save_reg_x x30, 16
+# 0xd421      .seh_save_reg_x x20, 16
+# 0xd401      .seh_save_reg_x x19, 16
+# 0xd2c0      .seh_save_reg x30, 0
+# 0xd040      .seh_save_reg x20, 0
+# 0xd000      .seh_save_reg x19, 0
+# 0xe0ffffff  .seh_stackalloc 268435440
+# 0xe0000800  .seh_stackalloc 32768
+# 0xc020      .seh_stackalloc 512
+# 0x01        .seh_stackalloc 16
+# 0xe4        nop
+# 0xe4        nop
+# 0x00000000  seh-handler
+# 0x00000000  fragment-offset
+# 0x0000005c  seh-handle-data-address
+# 0x00000001  long 1 (seh_handlerdata)
+
+ 0000 00007098 e6e1fce3 e2183693 52deefde  .*
+ 0010 2fde0fdd cedc4edc 0edbcbda 4bda0bd9  .*
+ 0020 cad84ad8 0ad748d6 48d608ce 85cc45cc  .*
+ 0030 05ca84c8 44c804d5 61d421d4 01d2c0d0  .*
+ 0040 40d000e0 ffffffe0 000800c0 2001e4e4  .*
+ 0050 00000000 00000000 5c000000 01000000  .*
\ No newline at end of file
diff --git a/gas/testsuite/gas/pe/seh-aarch64.s b/gas/testsuite/gas/pe/seh-aarch64.s
new file mode 100644
index 00000000000..5868a7f57dc
--- /dev/null
+++ b/gas/testsuite/gas/pe/seh-aarch64.s
@@ -0,0 +1,49 @@
+	.text
+	.seh_proc	foo
+	.seh_stackalloc 16
+	.seh_stackalloc 512
+	.seh_stackalloc 32768
+	.seh_stackalloc 268435440
+	.seh_save_reg x19, 0
+	.seh_save_reg x20, 0
+	.seh_save_reg x30, 0
+	.seh_save_reg_x x19, 16
+	.seh_save_reg_x x20, 16
+	.seh_save_reg_x x30, 16
+	.seh_save_regp x19, 32
+	.seh_save_regp x20, 32
+	.seh_save_regp x29, 32
+	.seh_save_regp_x x19, 48
+	.seh_save_regp_x x20, 48
+	.seh_save_regp_x x29, 48
+	.seh_save_lrpair x19, 64
+	.seh_save_lrpair x21, 64
+	.seh_save_lrpair x29, 64
+	.seh_save_fregp d8, 80
+	.seh_save_fregp d9, 80
+	.seh_save_fregp d15, 80
+	.seh_save_fregp_x d8, 96
+	.seh_save_fregp_x d9, 96
+	.seh_save_fregp_x d15, 96
+	.seh_save_freg d8, 112
+	.seh_save_freg d9, 112
+	.seh_save_freg d15, 112
+	.seh_save_freg_x d8, 128
+	.seh_save_freg_x d9, 128
+	.seh_save_freg_x d15, 128
+	.seh_save_fplr 144
+	.seh_save_fplr_x 160
+	.seh_save_r19r20_x 176
+	.seh_add_fp 192
+	.seh_nop
+	.seh_pac_sign_lr
+	.seh_set_fp
+	.seh_save_next
+	.seh_endprologue
+	.seh_handler _ZN9exception6handleEPvS0_S0_S0_, @except
+	.seh_handlerdata
+	.long 1
+	.seh_code
+	.seh_startepilogue
+	.seh_endepilogue
+	.seh_endproc
diff --git a/gas/write.c b/gas/write.c
index 9514c3df42e..b1a0d00a275 100644
--- a/gas/write.c
+++ b/gas/write.c
@@ -1839,7 +1839,7 @@ set_symtab (void)
 #endif
 #endif
 
-static void
+void
 subsegs_finish_section (asection *s)
 {
   struct frchain *frchainP;
diff --git a/gas/write.h b/gas/write.h
index bc5260a2efd..69072cd57e2 100644
--- a/gas/write.h
+++ b/gas/write.h
@@ -191,5 +191,6 @@ extern void as_bad_subtract (fixS *);
 struct segment_info_struct;
 extern fragS *get_frag_for_address (fragS *, const struct segment_info_struct *,
 				    addressT);
+extern void subsegs_finish_section (asection *);
 
 #endif /* __write_h__ */

From dje.gcc@gmail.com  Mon Jun 15 16:53:23 2026
From: dje.gcc@gmail.com (David Edelsohn)
Date: Mon, 15 Jun 2026 12:53:23 -0400
Subject: =?UTF-8?Q?Re=3A_Nominations_for_Anthropic=E2=80=99s_Claude_for_Open_So?=
 =?UTF-8?Q?urce_program?=
In-Reply-To: <CA+=Sn1kXqPED3bh1Ns_+VZ1OvUmGbM2FPN5z6dwO1bybG+0pqg@mail.gmail.com>
References: <CAGWvnykaUiiAPY8sMFAGu83ObWzChqp1Jk8BDwjy7tFedkd0Bg@mail.gmail.com>
 <CALvbMcBvEN3jkfBVnXHNu_C538jFdC8vLTz7ZNkNDwc=vvP0mw@mail.gmail.com>
 <975369a4f85805256fbe60909cc6d6a51e5d4099.camel@klomp.org>
 <CAGWvny=kvhXNiV_gB5=oyx_H=W=VA8ARyBSgpjBwAc=-PTWzDw@mail.gmail.com>
 <CA+=Sn1kXqPED3bh1Ns_+VZ1OvUmGbM2FPN5z6dwO1bybG+0pqg@mail.gmail.com>
Message-ID: <CAGWvnyk1x47jPWs3ML01J-TrgKt8ByALj3HzPpZodVS_73VSBg@mail.gmail.com>

On Mon, Jun 15, 2026 at 12:05?PM Andrew Pinski <pinskia@gmail.com> wrote:

>
>
> On Mon, Jun 15, 2026, 7:43?AM David Edelsohn <dje.gcc@gmail.com> wrote:
>
>> On Mon, Jun 15, 2026 at 7:35?AM Mark Wielaard <mark@klomp.org> wrote:
>>
>>> Hi,
>>>
>>> On Fri, 2026-06-12 at 12:34 -0700, Andrew Pinski via Gcc wrote:
>>> > On Fri, Jun 12, 2026 at 12:25?PM David Edelsohn via Gcc <
>>> gcc@gcc.gnu.org> wrote:
>>> > > please respond to this email thread with a short description of
>>> > > how you would utilize the access and the potential impact on the GNU
>>> > > Toolchain. The program's slots are limited and Carlos O'Donell and
>>> > > I plan to review the proposals.
>>> > > [...]
>>> > > P.S. This is not an endorsement of Anthropic, Claude or LLMs. We
>>> dislike
>>> > > having to say it, but please don?t use this thread as a platform to
>>> express
>>> > > your personal opinions about the companies or about AI?s impact on
>>> the
>>> > > world.
>>> >
>>> > Can we please keep this kind of emails out of the development mailing
>>> > lists?
>>>
>>> Yes. Even if you say it isn't an endorsement of (proprietary, saas)
>>> LLMs, it certainly reads like one. Please stop this.
>>>
>>
>> Emails to this list are permitted so long as they are on topic, and meet
>> the community code of conduct.
>>
>
> Except the original email does not meet community ethics of the list.
>
>
>
>> Asking politely to stay on topic is appropriate.
>>
>> Telling the community what it should or should not do or what is
>> permitted to be discussed is not appropriate.  You and Andrew are not the
>> arbiters of speech on the GCC, Binutils, GLIBC, and GDB mailing lists.
>> Please stop.  This intimidation and silencing tactic is not appropriate.
>>
>
>
> Saying ethics of such company and its software usage is offtopic for this
> thread does not make it offtopic for the community. Your ask in itself is
> intimidating to many and was very inappropriate.
> If this kind of offer came from anyone else, many of us still think the
> offer is offtopic for the community lists. And Saying your email is on
> topic means there will/can be a flood gate of similar offers. I am not sure
> that was your intention.
>
> Also in the past there was some asking if posting jobs were OK, and the
> community at the time decided no. This kind of offer should be in the same
> category as that.
>

Andrew,

We have conversations on these mailing lists about the use of
other proprietary tools that help with the development and debugging of
Free Software and the GNU Toolchain.  We have conversations about SPEC CPU,
Plum Hall, Perennial, Nullstone, etc.  We have conversations about building
and debugging the GNU Toolchain with proprietary compilers, assemblers,
linkers, debuggers, C Libraries, Math libraries, SIMD libraries, BLAS
libraries, etc.  We have conversations about the GNU Toolchain targeting
proprietary assemblers, linkers, libraries, operating systems, and computer
architectures.

While we prefer GNU/Linux and Free Software applications, we do not hijack
every technical discussion for a political conversation about the ethics of
those companies and their products.  The other conversations don't descend
into debates about ethics and this thread should not.  Members of the GNU
Toolchain community are free to ignore tools, products and opportunities
that they don't wish to utilize, while maintaining support for a wide
variety of platforms as targeted by the GNU Toolchain.

The GNU Project has other mailing lists for conversations about ethics and
politics.  Please use those mailing lists for those topics. We are not
going to turn the GNU Toolchain community and its communication forums into
purity tests.

Thanks, David


>
> Thanks
> Andrea
>
>
>
>
>
>
>
>
>
>> Thanks, David
>>
>>
>>> Thanks,
>>>
>>> Mark
>>>
>>
-------------- next part --------------
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From oliva@gnu.org  Mon Jun 15 20:15:24 2026
From: oliva@gnu.org (Alexandre Oliva)
Date: Mon, 15 Jun 2026 17:15:24 -0300
Subject: Nominations for =?utf-8?Q?Anthropic=E2=80=99s?= Claude for Open
 Source program
In-Reply-To: <CAGWvnyk1x47jPWs3ML01J-TrgKt8ByALj3HzPpZodVS_73VSBg@mail.gmail.com>
 (David Edelsohn's message of "Mon, 15 Jun 2026 12:53:23 -0400")
References: <CAGWvnykaUiiAPY8sMFAGu83ObWzChqp1Jk8BDwjy7tFedkd0Bg@mail.gmail.com>
 <CALvbMcBvEN3jkfBVnXHNu_C538jFdC8vLTz7ZNkNDwc=vvP0mw@mail.gmail.com>
 <975369a4f85805256fbe60909cc6d6a51e5d4099.camel@klomp.org>
 <CAGWvny=kvhXNiV_gB5=oyx_H=W=VA8ARyBSgpjBwAc=-PTWzDw@mail.gmail.com>
 <CA+=Sn1kXqPED3bh1Ns_+VZ1OvUmGbM2FPN5z6dwO1bybG+0pqg@mail.gmail.com>
 <CAGWvnyk1x47jPWs3ML01J-TrgKt8ByALj3HzPpZodVS_73VSBg@mail.gmail.com>
Message-ID: <ortsr31rxf.fsf@lxoliva.fsfla.org>

On Jun 15, 2026, David Edelsohn <dje.gcc@gmail.com> wrote:

> We have conversations on these mailing lists about the use of
> other proprietary tools that help with the development and debugging of
> Free Software and the GNU Toolchain.  We have conversations about SPEC CPU,
> Plum Hall, Perennial, Nullstone, etc.  We have conversations about building
> and debugging the GNU Toolchain with proprietary compilers, assemblers,
> linkers, debuggers, C Libraries, Math libraries, SIMD libraries, BLAS
> libraries, etc.  We have conversations about the GNU Toolchain targeting
> proprietary assemblers, linkers, libraries, operating systems, and computer
> architectures.

These are all cases of "I and my customer are lusers of Bate, and I want
to make GCC work better with Bate".  It doesn't invite or push anyone to
surrender one's freedom to Bate's supplier.

When people engage in advertising and pushing addictive (thus
freedom-depriving) drugs on GNU fora, that's an entirely different
situation.  Let's not pretend they're similar, please.  The correct
response must be to push back: it's spam, unsolicited advertisement, and
it should have been blocked as such; it's also a trap on top of that,
because it's SaaSS.

-- 
Alexandre Oliva, happy hacker            https://blog.lx.oliva.nom.br/
Free Software Activist     FSFLA co-founder     GNU Toolchain Engineer
Learn the truth about Richard Stallman at https://stallmansupport.org/

From oliva@gnu.org  Mon Jun 15 20:19:06 2026
From: oliva@gnu.org (Alexandre Oliva)
Date: Mon, 15 Jun 2026 17:19:06 -0300
Subject: Nominations for =?utf-8?Q?Anthropic=E2=80=99s?= Claude for Open
 Source program
In-Reply-To: <CAGWvnykaUiiAPY8sMFAGu83ObWzChqp1Jk8BDwjy7tFedkd0Bg@mail.gmail.com>
 (David Edelsohn's message of "Fri, 12 Jun 2026 15:24:49 -0400")
References: <CAGWvnykaUiiAPY8sMFAGu83ObWzChqp1Jk8BDwjy7tFedkd0Bg@mail.gmail.com>
Message-ID: <orpl1r1rr9.fsf@lxoliva.fsfla.org>

On Jun 12, 2026, David Edelsohn <dje.gcc@gmail.com> wrote:

> Anthropic is generously offering 6 months of Claude Max 20x to Free and Open
> Source Software projects to support the FOSS ecosystem.

You seem to have mispelled "poison" as "support".

I'd rather not contribute to this advertisement campaign for dis-SaaSS.
IMHO it doesn't belong in our communication channels.  At all.  It's an
embarrassment.

That said, since the harm is already done, I feel a duty to volunteer to
use up one of the available slots.

I have no intent whatsoever of using it.  I probably wouldn't be able to
as much as activate it anyway, as I'm sure it would involve some nonfree
software, in addition to SaaSS.

My purpose in applying for it is to spare someone else from being baited
into becoming a victim of this attack on our freedoms and on our ability
to think autonomously, and while at that to spare our tools from a
little additional pollution by these dis-services that would otherwise
likely take place.

I encourage others to apply with similar purposes, to defend our
freedom-loving communities from this attack aided by insiders.  Some
might wish to disguise their applications, to increase their odds of
going through.  This is self-defense against an unethical attack.


I posted a similar response to an identical advertisement posted to the
glibc list.  I am applying for two slots, one for GCC, one for glibc.
If that's ok, I'd like to apply for one for binutils and one for GDB as
well.

-- 
Alexandre Oliva, happy hacker            https://blog.lx.oliva.nom.br/
Free Software Activist     FSFLA co-founder     GNU Toolchain Engineer
Learn the truth about Richard Stallman at https://stallmansupport.org/

From amodra@gmail.com  Mon Jun 15 23:33:04 2026
From: amodra@gmail.com (Alan Modra)
Date: Tue, 16 Jun 2026 09:03:04 +0930
Subject: [PATCH] ld: xfail pr29655 on SPARC [PR34151]
In-Reply-To: <yddv7bkkvmg.fsf@CeBiTec.Uni-Bielefeld.DE>
References: <yddv7bkkvmg.fsf@CeBiTec.Uni-Bielefeld.DE>
Message-ID: <ajCLsFV7ERW0C_Gj@squeak.grove.modra.org>

On Mon, Jun 15, 2026 at 11:20:39AM +0200, Rainer Orth wrote:
> As described in PR ld/34151, the recent "Build pr29655" test FAILs on
> SPARC, both Solaris and Linux.
> 
> Until this is fixed, this patch xfail's the test.
> 
> Tested on sparc{v9,}-sun-solaris2.11, sparc{64,}-unknown-linux-gnu, and
> amd64-pc-solaris2.11.
> 
> Ok for trunk?

OK.

> This failure is the only one keeping the Solaris/SPARC buildbots from
> going green.  To allow them to easily report future issues, it would be
> good if this could go in.
> 
> Besides, Frank reported in the PR that RISC-V shows the same failure.  I
> wonder how to deal with that?  I guess it would be best to file a
> separate PR for that.
> 
> Thanks.
> 	Rainer
> 
> -- 
> -----------------------------------------------------------------------------
> Rainer Orth, Center for Biotechnology, Bielefeld University
> 
> 
> 2026-06-14  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
> 
> 	ld:
> 	* testsuite/ld-elf/shared.exp (Build pr29655): xfail on SPARC.
> 

> # HG changeset patch
> # Parent  e141951be61bea33828b504b5eceba9499e14d0e
> ld: xfail pr29655 on SPARC [PR34151]
> 
> diff --git a/ld/testsuite/ld-elf/shared.exp b/ld/testsuite/ld-elf/shared.exp
> --- a/ld/testsuite/ld-elf/shared.exp
> +++ b/ld/testsuite/ld-elf/shared.exp
> @@ -1878,6 +1878,8 @@ run_cc_link_tests [list \
>  # PR 29655 (cont.): Check that in PIC code linked as PDE taking the address
>  # of a function defined in a DSO results in the function address (from GOT)
>  # and not the "canonical PLT" address from the PDE.
> +# PR ld/34151
> +setup_xfail sparc*-*-*
>  run_cc_link_tests [list \
>      [list \
>  	"Build pr29655" \


-- 
Alan Modra

From bjarniig@simnet.is  Tue Jun 16 01:43:28 2026
From: bjarniig@simnet.is (Bjarni Ingi Gislason)
Date: Tue, 16 Jun 2026 01:43:28 +0000
Subject: man pages: trailing whitespace
Message-ID: <178157395057.8184.14774637816344761355.reportbug@kassi.invalid.is>

Package: binutils-common
Version: 2.46.50.20260608-1
Severity: minor

  Additional remarks.

  Mails from me to "submit@bugs.debian.org" are no longer acknowledged.  A
Debian maintainer told me, that he would contact the mail administrator
about me not wanting to send bugs upstream.

-.-

Dear Maintainer,

>From "/usr/share/doc/debian/bug-reporting.txt.gz":

  Don't file bugs upstream

   If you file a bug in Debian, don't send a copy to the upstream software
   maintainers yourself, as it is possible that the bug exists only in
   Debian. If necessary, the maintainer of the package will forward the
   bug upstream.

-.-

  For forwarding bug reports to upstream see:

https://www.debian.org/Bugs/Developer#forward

-.-

  "Handling bug reports" in
http://people.debian.org/~enrico/dcg/ch03s02.html

-.-

  I do not send reports upstream if I have to get an account there.
The Debian maintainers have one already.

  If I get a negative (or no) response from upstream, I send henceforth
bugs to Debian.

-.-

   * What led up to the situation?

     Checking for defects with a new version

test-[g|n]roff -mandoc -t -K utf8 -rF0 -rHY=0 -rCHECKSTYLE=0 -ww -z < "man page"

  [Use 

grep -n -e ' $' -e '\\~$' -e ' \\f.$' -e ' \\"' <file>

  to find (most) trailing spaces.]

  ["test-groff" is a script in the repository for "groff"; is not shipped]
(local copy and "troff" slightly changed by me).

  [The fate of "test-nroff" was decided in groff bug #55941.]

   * What was the outcome of this action?

troff:/tmp/gz.roff.z83u75:433: warning: trailing whitespace [-w trail]
/usr/share/man/man1/ar.1.gz

troff:/tmp/gz.roff.ew7kC5:1346: warning: trailing whitespace [-w trail]
/usr/share/man/man1/as.1.gz

troff:/tmp/gz.roff.ntZMhK:322: warning: trailing whitespace [-w trail]
troff:/tmp/gz.roff.ntZMhK:327: warning: trailing whitespace [-w trail]
troff:/tmp/gz.roff.ntZMhK:2601: warning: trailing whitespace [-w trail]
troff:/tmp/gz.roff.ntZMhK:3020: warning: trailing whitespace [-w trail]
/usr/share/man/man1/ld.bfd.1.gz

troff:/tmp/gz.roff.p8EVtB:411: warning: trailing whitespace [-w trail]
/usr/share/man/man1/nm.1.gz

troff:/tmp/gz.roff.mU8u94:263: warning: trailing whitespace [-w trail]
troff:/tmp/gz.roff.mU8u94:985: warning: trailing whitespace [-w trail]
/usr/share/man/man1/objdump.1.gz

troff:/tmp/gz.roff.PkiLNx:307: warning: trailing whitespace [-w trail]
troff:/tmp/gz.roff.PkiLNx:560: warning: trailing whitespace [-w trail]
/usr/share/man/man1/readelf.1.gz

troff:/tmp/gz.roff.BHDQao:143: warning: trailing whitespace [-w trail]
troff:/tmp/gz.roff.BHDQao:144: warning: trailing whitespace [-w trail]
/usr/share/man/man1/size.1.gz

troff:/tmp/gz.roff.Urc0FU:150: warning: trailing whitespace [-w trail]
/usr/share/man/man1/strings.1.gz

   * What outcome did you expect instead?

     No output (no warnings).

-.-

  General remarks and further material, if a diff-file exist, are in the
attachments.


-- System Information:
Debian Release: forky/sid
  APT prefers testing
  APT policy: (500, 'testing')
Architecture: amd64 (x86_64)

Kernel: Linux 7.0.10+deb14-amd64 (SMP w/2 CPU threads; PREEMPT)
Locale: LANG=is_IS.iso88591, LC_CTYPE=is_IS.iso88591 (charmap=ISO-8859-1), LANGUAGE not set
Shell: /bin/sh linked to /usr/bin/dash
Init: sysvinit (via /sbin/init)

-- no debconf information
-------------- next part --------------
  Check the output from "lintian" in the Debian distribution.

  Any program (person), that produces man pages, should check the output
for defects by using (both groff and nroff)

[gn]roff -mandoc -t -ww -b -z -K utf8 <man page>

  To find most trailing spaces use

grep -n -e ' $' -e ' \\f.$' -e ' \\"' <man page>

  The same goes for man pages that are used as an input.

-.-

  For a style guide use

  mandoc -T lint

-.-

  For general input conventions consult the man page "nroff(7)" (item
"Input conventions") or the Texinfo manual about the same item.

-.-

  Any "autogenerator" should check its products with the above mentioned
'groff', 'mandoc', and additionally with 'nroff ...'.

  It should also check its input files for too long (> 80) lines.

  This is just a simple quality control measure.

  The "autogenerator" may have to be corrected to get a better man page,
the source file may, and any additional file may.

-.-

  Common defects:

  Not removing trailing spaces (in in- and output).
  The reason for these trailing spaces should be found and eliminated.

  "git" has a "tool" to point out whitespace,
see for example "git-apply(1)" and git-config(1)")

-.-

  Not beginning each input sentence on a new line.

Line length and patch size should thus be reduced when that has been fixed.

  The script "reportbug" uses 'quoted-printable' encoding when a line is
longer than 1024 characters in an 'ascii' file.

  See man-pages(7), item "semantic newline".

-.-

The difference between the formatted output of the original
and patched file can be seen with:

  nroff -mandoc <file1> > <out1>
  nroff -mandoc <file2> > <out2>
  diff -d -u <out1> <out2>

and for groff, using

\"printf '%s\n%s\n' '.kern 0' '.ss 12 0' | groff -mandoc -Z - \"

instead of 'nroff -mandoc'

  Add the option '-t', if the file contains a table.

  Read the output from 'diff -d -u ...' with 'less -R' or similar.

-.-.

  If 'man' (man-db) is used to check the manual for warnings,
the following must be set:

  The option "-warnings=w"

  The environmental variable:

export MAN_KEEP_STDERR=yes (or any non-empty value)

  or

  (produce only warnings):

export MANROFFOPT="-ww -b -z"

export MAN_KEEP_STDERR=yes (or any non-empty value)

-.-
-------------- next part --------------
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From jbeulich@suse.com  Tue Jun 16 05:53:33 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Tue, 16 Jun 2026 07:53:33 +0200
Subject: [PATCH v8 1/1] aarch64: Implement Structured Exception Handling
 (SEH) on AArch64
In-Reply-To: <20260615160646.87169-2-evgeny.karpov@arm.com>
References: <20260615160646.87169-1-evgeny.karpov@arm.com>
 <20260615160646.87169-2-evgeny.karpov@arm.com>
Message-ID: <33858db3-31f0-4749-942e-0878d1d0306b@suse.com>

On 15.06.2026 18:06, Evgeny Karpov wrote:
> The patch reuses shared helpers for SEH and implements SEH on AArch64.
> The implementation is based on
> (https://learn.microsoft.com/en-us/cpp/build/arm64-exception-handling?view=msvc-170)
> and pdata/xdata SEH records are emitted from md_finish.
> 
> When .pdata/.xdata is emitted, the function size is required.
> Function sizes are calculated as late as possible, and the code segment needs
> to be relaxed to be able to calculate the function sizes.
> 
> Initially, obj_coff_generate_pdata was called in write_object_file.
> Before the change, obj_coff_generate_pdata was used only to validate
> syntax, which was sufficient for that purpose. However, that location
> seems incorrect, as it is too late to emit .pdata/.xdata records
> in the AArch64 case.
> 
> md_finish has been declared for AArch64 and extended with
> seh_aarch64_write_data to emit .pdata/.xdata records after all
> assembly has been completed.
> 
> Signed-off-by: Evgeny Karpov <evgeny@kmaps.co>

This wants approval from an Arm64 maintainer. Just one nit:

> --- /dev/null
> +++ b/gas/config/obj-coff-seh-aarch64.h
> @@ -0,0 +1,251 @@
> +/* SEH .pdata/.xdata COFF object file format on AArch64
> +   Copyright (C) 2026 Free Software Foundation, Inc.
> +
> +   This file is part of GAS.
> +
> +   GAS is free software; you can redistribute it and/or modify
> +   it under the terms of the GNU General Public License as published by
> +   the Free Software Foundation; either version 3, or (at your option)
> +   any later version.
> +
> +   GAS is distributed in the hope that it will be useful,
> +   but WITHOUT ANY WARRANTY; without even the implied warranty of
> +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +   GNU General Public License for more details.
> +
> +   You should have received a copy of the GNU General Public License
> +   along with GAS; see the file COPYING.  If not, write to the Free
> +   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
> +   02110-1301, USA.  */
> +
> +/* SEH COFF AArch64 implementation partially intersects with the x64
> +   version, however it has a different extension to the unwind codes.
> +   It emits SEH data to pdata and xdata sections.  In some cases SEH
> +   data could be emitted to a packed record in the pdata section
> +   without the need for data in the xdata section.  However, the packed
> +   pdata record is not implemented yet.
> +
> +   The current implementation does not include:
> +   - Packed .pdata record.
> +   - Support for AdvSIMD and SVE.
> +   - Epilogue start index different than 0.  */
> +
> +#ifndef OBJ_COFF_SEH_AARCH64_H
> +#define OBJ_COFF_SEH_AARCH64_H
> +
> +/* Unwind codes for AArch64 are described at
> +   https://learn.microsoft.com/en-us/cpp/build/arm64-exception-handling?view=msvc-170#unwind-codes.  */
> +
> +typedef enum seh_aarch64_unwind_types
> +{
> +  unwind_alloc_s,
> +  unwind_alloc_m,
> +  unwind_alloc_l,
> +  unwind_save_reg,
> +  unwind_save_reg_x,
> +  unwind_save_regp,
> +  unwind_save_regp_x,
> +  unwind_save_fregp,
> +  unwind_save_fregp_x,
> +  unwind_save_freg,
> +  unwind_save_freg_x,
> +  unwind_save_lrpair,
> +  unwind_save_fplr,
> +  unwind_save_fplr_x,
> +  unwind_save_r19r20_x,
> +  unwind_add_fp,
> +  unwind_set_fp,
> +  unwind_save_next,
> +  unwind_nop,
> +  unwind_pac_sign_lr,
> +  unwind_end,
> +  unwind_end_c,
> +  unwind_last_type = unwind_end_c
> +} seh_aarch64_unwind_types;
> +
> +#define SEH_CMDS						      \
> +  /* Start a function that contains SEH.  */			      \
> +  {"seh_proc", obj_coff_seh_proc, 0},				      \
> +								      \
> +  /* End a function that contains SEH.  */			      \
> +  {"seh_endproc", obj_coff_seh_endproc, 0},			      \
> +								      \
> +  /* End a SEH prologue with unwinding codes.  */			      \
> +  {"seh_endprologue", obj_coff_seh_endprologue, 0},		      \
> +								      \
> +  /* Allocate stack.  */					      \
> +  {"seh_stackalloc", obj_coff_seh_stackalloc, 0},		      \
> +								      \
> +  /* Set a SEH handler.  */					      \
> +  {"seh_handler", obj_coff_seh_handler, 0},			      \
> +								      \
> +  /* Set a SEH handler data.  */				      \
> +  {"seh_handlerdata", obj_coff_seh_handlerdata, 0},		      \
> +								      \
> +  /* Switch back to the code section.  */			      \
> +  {"seh_code", obj_coff_seh_code, 0},				      \
> +								      \
> +  /* Start a SEH epilogue.  */					      \
> +  {"seh_startepilogue", obj_coff_seh_startepilogue, 0},		      \
> +								      \
> +  /* End a SEH epilogue.  */					      \
> +  {"seh_endepilogue", obj_coff_seh_endepilogue, 0},		      \
> +								      \
> +  /* Save an 'x' register.  */					      \
> +  {"seh_save_reg", obj_coff_seh_save_reg, unwind_save_reg},	      \
> +								      \
> +  /* Save an 'x' register with a pre-indexed offset.  */	      \
> +  {"seh_save_reg_x", obj_coff_seh_save_reg, unwind_save_reg_x},	      \
> +								      \
> +  /* Save an 'x' register pair.  */				      \
> +  {"seh_save_regp", obj_coff_seh_save_reg, unwind_save_regp},	      \
> +								      \
> +  /* Save an 'x' register pair with a pre-indexed offset.  */	      \
> +  {"seh_save_regp_x", obj_coff_seh_save_reg, unwind_save_regp_x},     \
> +								      \
> +  /* Save an 'x' register and lr.  */				      \
> +  {"seh_save_lrpair", obj_coff_seh_save_reg, unwind_save_lrpair},     \
> +								      \
> +  /* Save a 'd' register pair.  */				      \
> +  {"seh_save_fregp", obj_coff_seh_save_reg, unwind_save_fregp},	      \
> +								      \
> +  /* Save a 'd' register pair with a pre-indexed offset.  */	      \
> +  {"seh_save_fregp_x", obj_coff_seh_save_reg, unwind_save_fregp_x},   \
> +								      \
> +  /* Save a 'd' register.  */					      \
> +  {"seh_save_freg", obj_coff_seh_save_reg, unwind_save_freg},	      \
> +								      \
> +  /* Save a 'd' register with a pre-indexed offset.  */		      \
> +  {"seh_save_freg_x", obj_coff_seh_save_reg, unwind_save_freg_x},     \
> +								      \
> +  /* Save fp and lr registers.  */				      \
> +  {"seh_save_fplr", obj_coff_seh_save_reg, unwind_save_fplr},	      \
> +								      \
> +  /* Save fp and lr registers with a pre-indexed offset.  */	      \
> +  {"seh_save_fplr_x", obj_coff_seh_save_reg, unwind_save_fplr_x},     \
> +								      \
> +  /* Save x19 and x20 registers with a pre-indexed offset.  */	      \
> +  {"seh_save_r19r20_x", obj_coff_seh_save_reg, unwind_save_r19r20_x}, \
> +								      \
> +  /* Set fp by sp + offset.  */					      \
> +  {"seh_add_fp", obj_coff_seh_save_reg, unwind_add_fp},		      \
> +								      \
> +  /* Unwind operation is not required.  */			      \
> +  {"seh_nop", obj_coff_seh_save_reg, unwind_nop},		      \
> +								      \
> +  /* Sign the return address in lr with pacibsp.  */		      \
> +  {"seh_pac_sign_lr", obj_coff_seh_save_reg, unwind_pac_sign_lr},     \
> +								      \
> +  /* Set fp by sp.  */						      \
> +  {"seh_set_fp", obj_coff_seh_save_reg, unwind_set_fp},		      \
> +								      \
> +  /* Save next register pair.  */				      \
> +  {"seh_save_next", obj_coff_seh_save_reg, unwind_save_next},

Can the backslashes here please all align properly? (It looks worse than it
is in reply context here, but there look to be quite a few genuine issues.)

Jan

From builder@sourceware.org  Tue Jun 16 07:33:29 2026
From: builder@sourceware.org (builder@sourceware.org)
Date: Tue, 16 Jun 2026 07:33:29 +0000
Subject: =?utf-8?q?=E2=98=BA_Buildbot_=28Sourceware=29=3A_binutils-gdb_-_build_successful_=28master=29?=
Message-ID: <20260616073329.92CB348FDC80@sourceware.org>

A restored build has been detected on builder binutils-solaris11-sparc while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/365/builds/39

Build state: build successful
Revision: a3ccc1836915eb694ac0f9b97ebb345bf7c83597
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>, Andrew Burgess <aburgess@redhat.com>, Etienne Brateau <etienne.brateau@gmail.com>, GDB Administrator <gdbadmin@sourceware.org>, Gopi Kumar Bulusu <gopi@sankhya.com>, Jon Turney <jon.turney@dronecode.org.uk>, Lancelot SIX <lancelot.six@amd.com>, Markus Metzger <markus.t.metzger@intel.com>, Matthieu Longo <matthieu.longo@arm.com>, Pedro Alves <pedro@palves.net>, Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>, Richard Earnshaw <rearnsha@arm.com>, Sunil Dora <sunilkumar.dora@windriver.com>, S?bastien Darche <sdarche@efficios.com>, Tom Tromey <tromey@adacore.com>, Tom de Vries <tdevries@suse.de>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/39/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
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- 3: configure ( success )
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- 4: make ( warnings )
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- 5: make check ( warnings )
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        - gas.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/39/steps/5/logs/gas_log
        - gprof.log: https://builder.sourceware.org/buildbot/#/builders/365/builds/39/steps/5/logs/gprof_log
        - binutils.sum: https://builder.sourceware.org/buildbot/#/builders/365/builds/39/steps/5/logs/binutils_sum
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        - libctf.sum: https://builder.sourceware.org/buildbot/#/builders/365/builds/39/steps/5/logs/libctf_sum
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- 6: prep ( success )
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- 8: fetch .bunsen.* ( success )
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- 9: build bunsen.cpio.gz ( success )
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- 10: fetch bunsen.cpio.gz ( success )
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- 11: unpack bunsen.cpio.gz ( success )
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- 12: pass .bunsen.source.* ( success )
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- 13: upload to bunsen ( success )
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- 14: clean up ( success )
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        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/39/steps/14/logs/stdio

- 15: rm -rf binutils-build_1 ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/365/builds/39/steps/15/logs/stdio

A restored build has been detected on builder binutils-solaris11-sparcv9 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/370/builds/33

Build state: build successful
Revision: a3ccc1836915eb694ac0f9b97ebb345bf7c83597
Worker: solaris11-sparcv9
Build Reason: (unknown)
Blamelist: Alan Modra <amodra@gmail.com>, Andrew Burgess <aburgess@redhat.com>, Etienne Brateau <etienne.brateau@gmail.com>, GDB Administrator <gdbadmin@sourceware.org>, Gopi Kumar Bulusu <gopi@sankhya.com>, Jon Turney <jon.turney@dronecode.org.uk>, Lancelot SIX <lancelot.six@amd.com>, Markus Metzger <markus.t.metzger@intel.com>, Matthieu Longo <matthieu.longo@arm.com>, Pedro Alves <pedro@palves.net>, Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>, Richard Earnshaw <rearnsha@arm.com>, Sunil Dora <sunilkumar.dora@windriver.com>, S?bastien Darche <sdarche@efficios.com>, Tom Tromey <tromey@adacore.com>, Tom de Vries <tdevries@suse.de>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/2/logs/stdio

- 3: configure ( success )
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        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/3/logs/config_log

- 4: make ( warnings )
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        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/4/logs/stdio
        - warnings (31): https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/4/logs/warnings__31_

- 5: make check ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/5/logs/stdio
        - ld.sum: https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/5/logs/ld_sum
        - ld.log: https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/5/logs/ld_log
        - gas.sum: https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/5/logs/gas_sum
        - gas.log: https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/5/logs/gas_log
        - gprof.log: https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/5/logs/gprof_log
        - binutils.sum: https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/5/logs/binutils_sum
        - binutils.log: https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/5/logs/binutils_log
        - libsframe.sum: https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/5/logs/libsframe_sum
        - libsframe.log: https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/5/logs/libsframe_log
        - libctf.sum: https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/5/logs/libctf_sum
        - libctf.log: https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/5/logs/libctf_log
        - warnings (15): https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/5/logs/warnings__15_

- 6: prep ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/6/logs/stdio

- 7: collect system versions ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/7/logs/stdio

- 8: fetch .bunsen.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/8/logs/stdio

- 9: build bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/9/logs/stdio

- 10: fetch bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/10/logs/stdio

- 11: unpack bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/11/logs/stdio

- 12: pass .bunsen.source.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/12/logs/stdio

- 13: upload to bunsen ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/13/logs/stdio

- 14: clean up ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/14/logs/stdio

- 15: rm -rf binutils-build_1 ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/370/builds/33/steps/15/logs/stdio


From jiawei@iscas.ac.cn  Tue Jun 16 08:29:36 2026
From: jiawei@iscas.ac.cn (Jiawei)
Date: Tue, 16 Jun 2026 16:29:36 +0800
Subject: [RFC 1/2] RISC-V: Add Zvdota extension classes
In-Reply-To: <0d0b3cd4-8358-4497-b168-b1409296941b@suse.com>
References: <20260609153844.538604-1-jiawei@iscas.ac.cn>
 <0d0b3cd4-8358-4497-b168-b1409296941b@suse.com>
Message-ID: <cd961258-afd2-4726-846f-7b27c8b875c3@iscas.ac.cn>

On 2026/6/15 16:39, Jan Beulich wrote:
> On 09.06.2026 17:38, Jiawei wrote:
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/zvdota.d
>> @@ -0,0 +1,19 @@
>> +#as: -march=rv64gc_zvqwdota8i_zvqwdota16i_zvfwdota16bf_zvfqwdota8f
> As can be seen very "neatly" here, the need to specify effectively every
> insn's extension separately (really only one of zvqwdota8i and zvqwdota16i
> should be necessary to spell out) is getting unwieldy. The situation is
> even worse with what patch 2 adds. Could we consider a shorthand zvdota
> here (and zvbdota in patch 2), covering all extensions in one go?

Hi Jan,

Thanks for the suggestion.

Yes, I agree. I will add zvdota and zvbdota as roll-up names in v2:

zvdota -> zvqwdota8i + zvqwdota16i + zvfwdota16bf + zvfqwdota8f
zvbdota -> zvqwbdota8i + zvqwbdota16i + zvfwbdota16bf
+ zvfqwbdota8f + zvfbdota32f

The individual extensions will remain available, and the instruction
entries will continue to be gated by the individual extension classes.
The roll-up names will just imply the corresponding individual extensions,
so existing per-instruction gating does not need to change.

I will also update the tests to use -march=..._zvdota and
-march=..._zvbdota in the main coverage tests, while keeping small tests
for the shared integer encodings where needed.

I can also?propose the corresponding Zvdota/Zvbdota dependency expansions

in the ISA?spec, similar to how the RISC-V B extension is defined in 
terms of its

component?extensions. That way binutils would not be the only place defining

these?aliases.

>> --- a/opcodes/riscv-opc.c
>> +++ b/opcodes/riscv-opc.c
>> @@ -2226,6 +2226,13 @@ const struct riscv_opcode riscv_opcodes[] =
>>   {"vfwmaccbf16.vf",  0, INSN_CLASS_ZVFBFWMA, "Vd,S,VtVm",  MATCH_VFWMACCBF16_VF, MASK_VFWMACCBF16_VF, match_opcode, 0},
>>   {"vfwmaccbf16.vv",  0, INSN_CLASS_ZVFBFWMA, "Vd,Vs,VtVm", MATCH_VFWMACCBF16_VV, MASK_VFWMACCBF16_VV, match_opcode, 0},
>>   
>> +/* Zvdota instructions.  */
>> +{"vqwdotau.vv", 0, INSN_CLASS_ZVQWDOTA8I_OR_ZVQWDOTA16I, "Vd,Vt,VsVm", MATCH_VQWDOTAU_VV, MASK_VQWDOTAU_VV, match_opcode, 0},
>> +{"vqwdotas.vv", 0, INSN_CLASS_ZVQWDOTA8I_OR_ZVQWDOTA16I, "Vd,Vt,VsVm", MATCH_VQWDOTAS_VV, MASK_VQWDOTAS_VV, match_opcode, 0},
>> +{"vfwdota.vv",  0, INSN_CLASS_ZVFWDOTA16BF, "Vd,Vt,VsVm", MATCH_VFWDOTA_VV, MASK_VFWDOTA_VV, match_opcode, 0},
>> +{"vfqwdota.vv", 0, INSN_CLASS_ZVFQWDOTA8F, "Vd,Vt,VsVm", MATCH_VFQWDOTA_VV, MASK_VFQWDOTA_VV, match_opcode, 0},
>> +{"vfqwdota.alt.vv", 0, INSN_CLASS_ZVFQWDOTA8F, "Vd,Vt,VsVm", MATCH_VFQWDOTA_ALT_VV, MASK_VFQWDOTA_ALT_VV, match_opcode, 0},
> I'm glad I didn't commit my "RISC-V: add dedicated vector arithmetic .insn
> forms" yet. Prior to this series only a very limited set of OP-VE encodings
> were in use (in mvv iirc). Now ivv and fvv encodings appear as well, hence
> I think we want to re-consider what we discussed regarding the RFC that I
> continue to have in that patch: It may end up being better then if the
> major opcode also needs spelling out in the .insn operands. Then the new
> forms here could be encoded that same way, right from the beginning.
>
> For reference, I've locally extended that RFC remark like this:
>
> "RFC: OP-VE reuses (at least) OPMVV, so "mvv" would end up ambiguous if we
>        wanted to also introduce insn forms there; with Zvdota and Zvbdota
>        "ivv" and "fvv" also become used under that same major opcode. Otoh
>        I wanted to avoid having O7 as the first operand everywhere. An
>        option might be to distinguish future OP-VE ones (in the once
>        supposed P extension encoding space iirc) by e.g. prefixing with P,
>        or - derived from OP-VE - with E. Yet that would likely end up being
>        a fully redundant set in the long run."
>
> It is really unfortunate that none of the RISC-V maintainers has voiced
> any opinion so far ...
>
> Jan

Regarding the .insn OP-VE forms: this series only adds named opcodes and
does not introduce new .insn forms. But I agree that Zvdota/Zvbdota add
more evidence that the future OP-VE .insn syntax should account for ivv
and fvv-style encodings under the 0x77 major opcode as well.

Thanks,
Jiawei
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From ro@CeBiTec.Uni-Bielefeld.DE  Tue Jun 16 08:40:55 2026
From: ro@CeBiTec.Uni-Bielefeld.DE (Rainer Orth)
Date: Tue, 16 Jun 2026 10:40:55 +0200
Subject: Issues with Solaris buildbots
In-Reply-To: <yddldcppfyz.fsf@CeBiTec.Uni-Bielefeld.DE> (Rainer Orth's message
 of "Mon, 08 Jun 2026 10:57:08 +0200")
References: <yddldcppfyz.fsf@CeBiTec.Uni-Bielefeld.DE>
Message-ID: <yddtsr2j2so.fsf@CeBiTec.Uni-Bielefeld.DE>

Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> writes:

> I've now set up 4 Solaris binutils buildbots for 32 and 64-bit
> Solaris/SPARC and x86.  There are two issues that cause the bots to be red:
>
> * The gprof tests FAIL as described in
>
> 	PR gprof/34237
>         gprof tests FAIL on Solaris
>
>   This went unnoticed before because this testsuite alone doesn't use
>   DejaGnu.
>
>   I suspect this is due to Solaris still using the original BSD gmon.out
>   format.  If so, the test scripts could expect that line, similarly to
>   the powerpc special case.

This has now been fixed.  Besides, the bot uncovered that profiling on
32-bit Solaris/x86 had been broken for a decade:

	libgcc: Fix _mcount on 32-bit Solaris/x86 [PR38239]
        https://gcc.gnu.org/pipermail/gcc-patches/2026-June/720299.html

The fix is in GCC trunk now and locally on the buildbots.

> * Recently, the new pr29655 test FAILs on SPARC:
>
> 	PR ld/34151
>         pr29655 FAILs on SPARC
>
>   Fixing this seems to be quite involved.  I wonder if we could just
>   xfail the test for now so the bots are actually useful.

The xfail just went in, turning all four buildbots green for the first
time.

Thanks a lot to everyone involved both in getting binutils into shape
and the buildbots up and running.

	Rainer

-- 
-----------------------------------------------------------------------------
Rainer Orth, Center for Biotechnology, Bielefeld University

From sam@gentoo.org  Tue Jun 16 12:05:12 2026
From: sam@gentoo.org (Sam James)
Date: Tue, 16 Jun 2026 13:05:12 +0100
Subject: Issues with Solaris buildbots
In-Reply-To: <yddtsr2j2so.fsf@CeBiTec.Uni-Bielefeld.DE>
References: <yddldcppfyz.fsf@CeBiTec.Uni-Bielefeld.DE>
 <yddtsr2j2so.fsf@CeBiTec.Uni-Bielefeld.DE>
Message-ID: <87qzm66687.fsf@gentoo.org>

Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> writes:

> Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE> writes:
>
>> I've now set up 4 Solaris binutils buildbots for 32 and 64-bit
>> Solaris/SPARC and x86.  There are two issues that cause the bots to be red:
>>
>> * The gprof tests FAIL as described in
>>
>> 	PR gprof/34237
>>         gprof tests FAIL on Solaris
>>
>>   This went unnoticed before because this testsuite alone doesn't use
>>   DejaGnu.
>>
>>   I suspect this is due to Solaris still using the original BSD gmon.out
>>   format.  If so, the test scripts could expect that line, similarly to
>>   the powerpc special case.
>
> This has now been fixed.  Besides, the bot uncovered that profiling on
> 32-bit Solaris/x86 had been broken for a decade:
>
> 	libgcc: Fix _mcount on 32-bit Solaris/x86 [PR38239]
>         https://gcc.gnu.org/pipermail/gcc-patches/2026-June/720299.html
>
> The fix is in GCC trunk now and locally on the buildbots.
>
>> * Recently, the new pr29655 test FAILs on SPARC:
>>
>> 	PR ld/34151
>>         pr29655 FAILs on SPARC
>>
>>   Fixing this seems to be quite involved.  I wonder if we could just
>>   xfail the test for now so the bots are actually useful.
>
> The xfail just went in, turning all four buildbots green for the first
> time.
>
> Thanks a lot to everyone involved both in getting binutils into shape
> and the buildbots up and running.

And thank you as well, this is great to have finally.

>
> 	Rainer
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From Richard.Earnshaw@arm.com  Tue Jun 16 13:11:53 2026
From: Richard.Earnshaw@arm.com (Richard Earnshaw (foss))
Date: Tue, 16 Jun 2026 14:11:53 +0100
Subject: [PATCH] AArch64 gas: Block section relative symbols in GOT
 relocations [PR30788]
In-Reply-To: <PAWPR08MB8982E0055215376A1CD03B0F83E62@PAWPR08MB8982.eurprd08.prod.outlook.com>
References: <PAWPR08MB8982EA96A85A9846678CCFB5830B2@PAWPR08MB8982.eurprd08.prod.outlook.com>
 <da73b869-98e0-4c6a-8ea2-ee25d4fb74f9@arm.com>
 <PAWPR08MB8982B0075AF2F0CF9C51BADC83082@PAWPR08MB8982.eurprd08.prod.outlook.com>
 <d6dd8e41-21ce-4a9b-837b-c5e54d51cd00@arm.com>
 <PAWPR08MB8982E0055215376A1CD03B0F83E62@PAWPR08MB8982.eurprd08.prod.outlook.com>
Message-ID: <4888be33-52b9-4e57-bb3b-a87774b86b21@arm.com>

On 15/06/2026 16:04, Wilco Dijkstra wrote:
> Hi Richard/Alice,
> 
>> After some extensive archaeology it's now clear that we don't care about the VTABLE stuff.? In fact, I'm amazed that we didn't expunge that entirely some years ago - we certainly blew away all the tests for it.
>>
>> OK.
> 
> Since I don't have write access, could someone commit this for me, please?
> 
> Cheers,
> Wilco

Done.  Thanks once again.

R.

From chigot@adacore.com  Tue Jun 16 14:12:06 2026
From: chigot@adacore.com (=?UTF-8?Q?Cl=C3=A9ment_Chigot?=)
Date: Tue, 16 Jun 2026 16:12:06 +0200
Subject: [PATCH] ld/testsuite: add support for remote testing in ld-cdtest
In-Reply-To: <20260529135252.2094804-1-chigot@adacore.com>
References: <20260529135252.2094804-1-chigot@adacore.com>
Message-ID: <CAJ307Eh2qzm1uc+yJoPSEt3LbYBM0bfwQo2fyTxVJS2H5jmP4Q@mail.gmail.com>

On Fri, May 29, 2026 at 3:52?PM Cl?ment Chigot <chigot@adacore.com> wrote:
>
> This converts the existing to code to use "remote_load" allowing
> execution on both native and remote targets.
>
> The "diff" between the output and the expected result has been
> transformed to the usual regexp_diff. The previous could have been
> transformed into `remote_exec build diff` but tends to be fickled with
> new lines.
> ---
>  ld/testsuite/ld-cdtest/cdtest-nrv.dat | 26 ++++----
>  ld/testsuite/ld-cdtest/cdtest.dat     | 30 ++++-----
>  ld/testsuite/ld-cdtest/cdtest.exp     | 96 +++++++++++++--------------
>  3 files changed, 73 insertions(+), 79 deletions(-)
>
> diff --git a/ld/testsuite/ld-cdtest/cdtest-nrv.dat b/ld/testsuite/ld-cdtest/cdtest-nrv.dat
> index d3f871ff108..76fcbaa03d4 100644
> --- a/ld/testsuite/ld-cdtest/cdtest-nrv.dat
> +++ b/ld/testsuite/ld-cdtest/cdtest-nrv.dat
> @@ -1,13 +1,13 @@
> -Constructing Foo(1) "static_foo"
> -Constructing Foo(2) "static_foo"
> -Constructing Foo(3) "automatic_foo"
> -Constructing Foo(4) "default-foo"
> -Constructing Foo(5) "other_foo1"
> -Constructing Foo(6) "other_foo2"
> -Copying Foo(5) "other_foo1" to Foo(6)
> -Destructing Foo(6) "other_foo1" (remaining foos: 5)
> -Destructing Foo(5) "other_foo1" (remaining foos: 4)
> -Destructing Foo(4) "default-foo" (remaining foos: 3)
> -Destructing Foo(3) "automatic_foo" (remaining foos: 2)
> -Destructing Foo(2) "static_foo" (remaining foos: 1)
> -Destructing Foo(1) "static_foo" (remaining foos: 0)
> +Constructing Foo\(1\) "static_foo"
> +Constructing Foo\(2\) "static_foo"
> +Constructing Foo\(3\) "automatic_foo"
> +Constructing Foo\(4\) "default-foo"
> +Constructing Foo\(5\) "other_foo1"
> +Constructing Foo\(6\) "other_foo2"
> +Copying Foo\(5\) "other_foo1" to Foo\(6\)
> +Destructing Foo\(6\) "other_foo1" \(remaining foos: 5\)
> +Destructing Foo\(5\) "other_foo1" \(remaining foos: 4\)
> +Destructing Foo\(4\) "default-foo" \(remaining foos: 3\)
> +Destructing Foo\(3\) "automatic_foo" \(remaining foos: 2\)
> +Destructing Foo\(2\) "static_foo" \(remaining foos: 1\)
> +Destructing Foo\(1\) "static_foo" \(remaining foos: 0\)
> diff --git a/ld/testsuite/ld-cdtest/cdtest.dat b/ld/testsuite/ld-cdtest/cdtest.dat
> index 39be0dbc2c7..c0bdffb3c26 100644
> --- a/ld/testsuite/ld-cdtest/cdtest.dat
> +++ b/ld/testsuite/ld-cdtest/cdtest.dat
> @@ -1,15 +1,15 @@
> -Constructing Foo(1) "static_foo"
> -Constructing Foo(2) "static_foo"
> -Constructing Foo(3) "automatic_foo"
> -Constructing Foo(4) "default-foo"
> -Initializing Foo(5) "default-foo" with Foo(4)
> -Destructing Foo(4) "default-foo" (remaining foos: 4)
> -Constructing Foo(5) "other_foo1"
> -Constructing Foo(6) "other_foo2"
> -Copying Foo(5) "other_foo1" to Foo(6)
> -Destructing Foo(6) "other_foo1" (remaining foos: 5)
> -Destructing Foo(5) "other_foo1" (remaining foos: 4)
> -Destructing Foo(5) "default-foo" (remaining foos: 3)
> -Destructing Foo(3) "automatic_foo" (remaining foos: 2)
> -Destructing Foo(2) "static_foo" (remaining foos: 1)
> -Destructing Foo(1) "static_foo" (remaining foos: 0)
> +Constructing Foo\(1\) "static_foo"
> +Constructing Foo\(2\) "static_foo"
> +Constructing Foo\(3\) "automatic_foo"
> +Constructing Foo\(4\) "default-foo"
> +Initializing Foo\(5\) "default-foo" with Foo\(4\)
> +Destructing Foo\(4\) "default-foo" \(remaining foos: 4\)
> +Constructing Foo\(5\) "other_foo1"
> +Constructing Foo\(6\) "other_foo2"
> +Copying Foo\(5\) "other_foo1" to Foo\(6\)
> +Destructing Foo\(6\) "other_foo1" \(remaining foos: 5\)
> +Destructing Foo\(5\) "other_foo1" \(remaining foos: 4\)
> +Destructing Foo\(5\) "default-foo" \(remaining foos: 3\)
> +Destructing Foo\(3\) "automatic_foo" \(remaining foos: 2\)
> +Destructing Foo\(2\) "static_foo" \(remaining foos: 1\)
> +Destructing Foo\(1\) "static_foo" \(remaining foos: 0\)
> diff --git a/ld/testsuite/ld-cdtest/cdtest.exp b/ld/testsuite/ld-cdtest/cdtest.exp
> index 89fdd581abb..ccfcbaf226a 100644
> --- a/ld/testsuite/ld-cdtest/cdtest.exp
> +++ b/ld/testsuite/ld-cdtest/cdtest.exp
> @@ -27,11 +27,6 @@
>  set test1 "cdtest"
>  set test2 "cdtest with -Ur"
>
> -# This test requires running the executable generated by ld.
> -if ![isnative] {
> -    return
> -}
> -
>  if { [which $CXX_FOR_TARGET] == 0 } {
>      untested $test1
>      untested $test2
> @@ -51,44 +46,39 @@ set expected_output "$srcdir/$subdir/cdtest.dat"
>  if ![ld_link $CC_FOR_TARGET tmpdir/cdtest "$CFLAGS_FOR_TARGET tmpdir/cdtest-foo.o tmpdir/cdtest-bar.o tmpdir/cdtest-main.o"] {
>      fail $test1
>  } else {
> -    send_log   "tmpdir/cdtest >tmpdir/cdtest.out\n"
> -    verbose    "tmpdir/cdtest >tmpdir/cdtest.out"
> -    catch "exec tmpdir/cdtest >tmpdir/cdtest.out" exec_output
> +    set failed 0
>
> -    if ![string match "" $exec_output] then {
> +    send_log "Running: tmpdir/cdtest\n"
> +    verbose "Running: tmpdir/cdtest"
> +    set state [remote_load target tmpdir/cdtest]
> +    set status [lindex $state 0]
> +    set exec_output [lindex $state 1]
> +
> +    if { $status != "pass"  } {
>         send_log "$exec_output\n"
>         verbose "$exec_output" 1
> -
> -       fail $test1
> +       set failed 1
>      } else {
> -       send_log   "diff tmpdir/cdtest.out $expected_output\n"
> -       verbose    "diff tmpdir/cdtest.out $expected_output"
> -       catch "exec diff tmpdir/cdtest.out $expected_output" exec_output
> -       set exec_output [prune_warnings $exec_output]
> -
> -       if ![string match "" $exec_output] then {
> -           send_log "$exec_output\n"
> -           verbose  "$exec_output" 1
> +       set output_filename "tmpdir/cdtest.out"
> +       set_file_contents $output_filename $exec_output
>
> +       send_log [file_contents $output_filename]
> +       verbose [file_contents $output_filename] 2
> +       if [regexp_diff $output_filename $expected_output] {
>             send_log "Checking against Named Return Value optimization\n"
>             verbose  "Checking against Named Return Value optimization" 1
>
>             set expected_output "$srcdir/$subdir/cdtest-nrv.dat"
> -
> -           send_log   "diff tmpdir/cdtest.out $expected_output\n"
> -           verbose    "diff tmpdir/cdtest.out $expected_output"
> -           catch "exec diff tmpdir/cdtest.out $expected_output" exec_output
> -           set exec_output [prune_warnings $exec_output]
> +           if [regexp_diff $output_filename $expected_output] {
> +               set failed 1
> +           }
>         }
> +    }
>
> -       if [string match "" $exec_output] then {
> -           pass $test1
> -       } else {
> -           send_log "$exec_output\n"
> -           verbose  "$exec_output" 1
> -
> -           fail $test1
> -       }
> +    if { $failed != 0 } {
> +       fail $test1
> +    } else {
> +       pass $test1
>      }
>  }
>
> @@ -103,29 +93,33 @@ if ![ld_relocate $ld tmpdir/cdtest.o {-Ur tmpdir/cdtest-foo.o tmpdir/cdtest-bar.
>      if ![ld_link $CC_FOR_TARGET tmpdir/cdtest "$CFLAGS_FOR_TARGET tmpdir/cdtest.o"] {
>         fail $test2

There is a minor mistake here, it should be "set failed 1". Otherwise,
we get a duplicate FAIL.
@Alan Modra  still ok for master ?

>      } else {
> -       send_log   "tmpdir/cdtest >tmpdir/cdtest.out\n"
> -       verbose    "tmpdir/cdtest >tmpdir/cdtest.out"
> -       catch "exec tmpdir/cdtest >tmpdir/cdtest.out" exec_output
> +       set failed 0
>
> -       if ![string match "" $exec_output] then {
> -           send_log "$exec_output\n"
> -           verbose  "$exec_output" 1
> +       send_log "Running: tmpdir/cdtest\n"
> +       verbose "Running: tmpdir/cdtest"
> +       set state [remote_load target tmpdir/cdtest]
> +       set status [lindex $state 0]
> +       set exec_output [lindex $state 1]
>
> -           fail $test2
> +       if { $status != "pass" } {
> +           send_log "$exec_output\n"
> +           verbose "$exec_output" 1
> +           set failed 1
>         } else {
> -           send_log   "diff tmpdir/cdtest.out $expected_output\n"
> -           verbose    "diff tmpdir/cdtest.out $expected_output"
> -           catch "exec diff tmpdir/cdtest.out $expected_output" exec_output
> -           set exec_output [prune_warnings $exec_output]
> -
> -           if [string match "" $exec_output] then {
> -               pass $test2
> -           } else {
> -               send_log "$exec_output\n"
> -               verbose  "$exec_output" 1
> -
> -               fail $test2
> +           set output_filename "tmpdir/cdtest.out"
> +           set_file_contents $output_filename $exec_output
> +
> +           send_log [file_contents $output_filename]
> +           verbose [file_contents $output_filename] 2
> +           if [regexp_diff $output_filename $expected_output] {
> +               set failed 1
>             }
>         }
>      }
> +
> +    if { $failed != 0 } {
> +       fail $test2
> +    } else {
> +       pass $test2
> +    }
>  }
> --
> 2.43.0
>

From Richard.Earnshaw@arm.com  Tue Jun 16 14:30:14 2026
From: Richard.Earnshaw@arm.com (Richard Earnshaw (foss))
Date: Tue, 16 Jun 2026 15:30:14 +0100
Subject: [PATCH v3] gas: arm - support CPU-specific extensions with -mcpu
In-Reply-To: <20260609104035.700121-1-sivan.shani@arm.com>
References: <20260608145251.37337-1-sivan.shani@arm.com>
 <20260609104035.700121-1-sivan.shani@arm.com>
Message-ID: <2846ac09-3590-409d-8ecf-cc385c8929e8@arm.com>

On 09/06/2026 11:39, Sivan Shani wrote:
> Add extension tables for -mcpu, similar to -march, allowing
> CPU-specific extensions to be enabled and disabled using +ext and
> +noext modifiers.
> 
> Update ARM CPU feature definitions to match GCC CPU baselines and
> add tests covering supported CPU extension modifiers and feature
> availability.
> 
> 
> This is the 3'd patch:
> Fixing a test file (attr-cpu-directive.d)
> 
> ---
>  gas/config/tc-arm.c                         | 687 +++++++++++++++-----
>  gas/testsuite/gas/arm/attr-cpu-directive.d  |   2 +
>  gas/testsuite/gas/arm/command-line-mcpu.exp | 134 ++++
>  gas/testsuite/gas/arm/feat-bf16.s           |   5 +
>  gas/testsuite/gas/arm/feat-crc.s            |   4 +
>  gas/testsuite/gas/arm/feat-dotprod.s        |   4 +
>  gas/testsuite/gas/arm/feat-dsp.s            |   4 +
>  gas/testsuite/gas/arm/feat-fp-vfpv3.s       |   4 +
>  gas/testsuite/gas/arm/feat-fp-vfpv5.s       |   4 +
>  gas/testsuite/gas/arm/feat-fp.dp.s          |   4 +
>  gas/testsuite/gas/arm/feat-fp.s             |   4 +
>  gas/testsuite/gas/arm/feat-fp16.s           |   4 +
>  gas/testsuite/gas/arm/feat-i8mm.s           |   4 +
>  gas/testsuite/gas/arm/feat-idiv.s           |   3 +
>  gas/testsuite/gas/arm/feat-mp.s             |   4 +
>  gas/testsuite/gas/arm/feat-mve.fp.s         |   5 +
>  gas/testsuite/gas/arm/feat-neon-fp16.s      |   4 +
>  gas/testsuite/gas/arm/feat-pacbti.s         |   4 +
>  gas/testsuite/gas/arm/feat-sec.s            |   4 +
>  gas/testsuite/gas/arm/feat-simd.s           |   5 +
>  gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s |   4 +
>  21 files changed, 742 insertions(+), 155 deletions(-)
>  create mode 100644 gas/testsuite/gas/arm/command-line-mcpu.exp
>  create mode 100644 gas/testsuite/gas/arm/feat-bf16.s
>  create mode 100644 gas/testsuite/gas/arm/feat-crc.s
>  create mode 100644 gas/testsuite/gas/arm/feat-dotprod.s
>  create mode 100644 gas/testsuite/gas/arm/feat-dsp.s
>  create mode 100644 gas/testsuite/gas/arm/feat-fp-vfpv3.s
>  create mode 100644 gas/testsuite/gas/arm/feat-fp-vfpv5.s
>  create mode 100644 gas/testsuite/gas/arm/feat-fp.dp.s
>  create mode 100644 gas/testsuite/gas/arm/feat-fp.s
>  create mode 100644 gas/testsuite/gas/arm/feat-fp16.s
>  create mode 100644 gas/testsuite/gas/arm/feat-i8mm.s
>  create mode 100644 gas/testsuite/gas/arm/feat-idiv.s
>  create mode 100644 gas/testsuite/gas/arm/feat-mp.s
>  create mode 100644 gas/testsuite/gas/arm/feat-mve.fp.s
>  create mode 100644 gas/testsuite/gas/arm/feat-neon-fp16.s
>  create mode 100644 gas/testsuite/gas/arm/feat-pacbti.s
>  create mode 100644 gas/testsuite/gas/arm/feat-sec.s
>  create mode 100644 gas/testsuite/gas/arm/feat-simd.s
>  create mode 100644 gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s
> 
> diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
> index 3ff29542411..ef9b878dffc 100644
> --- a/gas/config/tc-arm.c
> +++ b/gas/config/tc-arm.c
> @@ -30495,6 +30495,14 @@ const struct arm_legacy_option_table arm_legacy_opts[] =
>    {NULL, NULL, ARM_ARCH_NONE, NULL}
>  };
>  
> +struct arm_ext_table
> +{
> +  const char *		  name;
> +  size_t		  name_len;
> +  const arm_feature_set	  merge;
> +  const arm_feature_set	  clear;
> +};
> +
>  struct arm_cpu_option_table
>  {
>    const char *           name;
> @@ -30507,11 +30515,339 @@ struct arm_cpu_option_table
>    /* The canonical name of the CPU, or NULL to use NAME converted to upper
>       case.  */
>    const char *           canonical_name;
> +  const struct arm_ext_table *	ext_table;
> +};
> +
> +/* Used to add support for +E and +noE extension.  */
> +#define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
> +/* Used to add support for a +E extension.  */
> +#define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
> +/* Used to add support for a +noE extension.  */
> +#define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
> +
> +#define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
> +			    ~0 & ~FPU_ENDIAN_PURE)
> +#define ALL_FP_MVE_FP ARM_FEATURE (0, (ARM_EXT2_FP16_INST		   \
> +					| ARM_EXT2_FP16_FML		   \
> +					| ARM_EXT2_MVE_FP),		   \
> +				    ~0 & ~FPU_ENDIAN_PURE)

When I load this file in my editor, this line isn't indented properly

> +#define ALL_SIMD ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA |     \
> +				     FPU_NEON_EXT_ARMV8 | FPU_NEON_EXT_RDMA | \
> +				     FPU_NEON_EXT_DOTPROD)
> +

operators should appear at the start of continuation lines, not the end of the previous line.  So
xxxx (bar
      | morebar)

> +#define CDE_EXTENSIONS \
> +  ARM_ADD ("cdecp0", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE0)), \
> +  ARM_ADD ("cdecp1", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE1)), \
> +  ARM_ADD ("cdecp2", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE2)), \
> +  ARM_ADD ("cdecp3", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE3)), \
> +  ARM_ADD ("cdecp4", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE4)), \
> +  ARM_ADD ("cdecp5", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE5)), \
> +  ARM_ADD ("cdecp6", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE6)), \
> +  ARM_ADD ("cdecp7", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE7))
> +
> +/* -mcpu extensions.  */
> +static const struct arm_ext_table cortex_a5_ext_table[] =
> +{
> +  ARM_REMOVE ("fp", ALL_FP),
> +  ARM_REMOVE ("simd", ALL_SIMD),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a7_ext_table[] =
> +{
> +  ARM_REMOVE ("fp", ALL_FP),
> +  ARM_REMOVE ("simd", ALL_SIMD),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a8_ext_table[] =
> +{
> +  ARM_REMOVE ("fp", ALL_FP),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a9_ext_table[] =
> +{
> +  ARM_REMOVE ("fp", ALL_FP),
> +  ARM_REMOVE ("simd", ALL_SIMD),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a12_ext_table[] =
> +{
> +  ARM_REMOVE ("fp", ALL_FP),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a15_ext_table[] =
> +{
> +  ARM_REMOVE ("fp", ALL_FP),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a17_ext_table[] =
> +{
> +  ARM_REMOVE ("fp", ALL_FP),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_r5_ext_table[] =
> +{
> +  ARM_REMOVE ("fp",    ALL_FP),
> +  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
> +		      | FPU_VFP_EXT_ARMV8)),
This should be indented to the opening parenthesis of the ..._COPROC parenthesis.  Similarly below.  Also look out for more cases of operators at the end of lines.


> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_r7_ext_table[] =
> +{
> +  ARM_REMOVE ("fp",    ALL_FP),
> +  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
> +		      | FPU_VFP_EXT_ARMV8)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_r8_ext_table[] =
> +{
> +  ARM_REMOVE ("fp",    ALL_FP),
> +  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
> +		      | FPU_VFP_EXT_ARMV8)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_m4_ext_table[] =
> +{
> +  ARM_REMOVE ("fp",    ALL_FP),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_m7_ext_table[] =
> +{
> +  ARM_REMOVE ("fp",    ALL_FP),
> +  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
> +		      | FPU_VFP_EXT_ARMV8)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a32_ext_table[] =
> +{
> +  ARM_REMOVE ("fp",     ALL_FP),
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
> +		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a35_ext_table[] =
> +{
> +  ARM_REMOVE ("fp",     ALL_FP),
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
> +		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a53_ext_table[] =
> +{
> +  ARM_REMOVE ("fp",     ALL_FP),
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
> +		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a57_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
> +		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a72_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
> +		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a73_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
> +		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table exynos_m1_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
> +		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_r52_ext_table[] =
> +{
> +  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_D32 | FPU_VFP_EXT_ARMV8
> +			| FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA
> +			| FPU_NEON_EXT_ARMV8 | FPU_NEON_EXT_RDMA
> +			| FPU_NEON_EXT_DOTPROD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_r52plus_ext_table[] =
> +{
> +  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_D32 | FPU_VFP_EXT_ARMV8
> +			| FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA
> +			| FPU_NEON_EXT_ARMV8 | FPU_NEON_EXT_RDMA
> +			| FPU_NEON_EXT_DOTPROD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_m33_ext_table[] =
> +{
> +  ARM_REMOVE ("fp",  ALL_FP),
> +  ARM_REMOVE ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_m35p_ext_table[] =
> +{
> +  ARM_REMOVE ("fp",  ALL_FP),
> +  ARM_REMOVE ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_m52_ext_table[] =
> +{
> +  ARM_REMOVE ("pacbti", ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI)),
> +  ARM_REMOVE ("mve.fp", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP)),
> +  ARM_REMOVE ("mve",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
> +  ARM_REMOVE ("fp",     ALL_FP_MVE_FP),
> +  ARM_REMOVE ("dsp",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
> +  CDE_EXTENSIONS,
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_m55_ext_table[] =
> +{
> +  ARM_REMOVE ("mve.fp", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP)),
> +  ARM_REMOVE ("mve",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
> +  ARM_REMOVE ("fp",     ALL_FP_MVE_FP),
> +  ARM_REMOVE ("dsp",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
> +  CDE_EXTENSIONS,
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_m85_ext_table[] =
> +{
> +  ARM_REMOVE ("pacbti", ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI)),
> +  ARM_REMOVE ("mve.fp", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP)),
> +  ARM_REMOVE ("mve",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
> +  ARM_REMOVE ("fp",     ALL_FP_MVE_FP),
> +  ARM_REMOVE ("dsp",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a55_ext_table[] =
> +{
> +  ARM_REMOVE ("fp", ALL_FP),
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
> +		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a75_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
> +		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a76_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
> +		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a76ae_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
> +		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a77_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
> +		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a78_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
> +		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a78ae_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
> +		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a78c_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
> +		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_x1_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
> +		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_x1c_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
> +		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table neoverse_n1_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
> +		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table neoverse_v1_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
> +		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a710_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
> +		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table neoverse_n2_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8 |
> +		     FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
>  };
>  
>  /* This list should, at a minimum, contain all the cpu names
>     recognized by GCC.  */
> -#define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
> +#define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN, NULL }
> +#define ARM_CPU_OPT2(N, CN, V, E, DF, ext) \
> +  { N, sizeof (N) - 1, V, E, DF, CN, ext##_ext_table }
>  
>  static const struct arm_cpu_option_table arm_cpus[] =
>  {
> @@ -30764,113 +31100,162 @@ static const struct arm_cpu_option_table arm_cpus[] =
>    ARM_CPU_OPT ("arm1176jzf-s",	  NULL,		       ARM_ARCH_V6KZ,
>  	       ARM_ARCH_NONE,
>  	       FPU_ARCH_VFP_V2),
> -  ARM_CPU_OPT ("cortex-a5",	  "Cortex-A5",	       ARM_ARCH_V7A,
> -	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
> -	       FPU_ARCH_SOFTVFP),
> -  ARM_CPU_OPT ("cortex-a7",	  "Cortex-A7",	       ARM_ARCH_V7VE,
> -	       ARM_ARCH_NONE,
> -	       FPU_ARCH_NEON_VFP_V4),
> -  ARM_CPU_OPT ("cortex-a8",	  "Cortex-A8",	       ARM_ARCH_V7A,
> -	       ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
> -	       ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
> -  ARM_CPU_OPT ("cortex-a9",	  "Cortex-A9",	       ARM_ARCH_V7A,
> -	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
> -	       ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
> -  ARM_CPU_OPT ("cortex-a12",	  "Cortex-A12",	       ARM_ARCH_V7VE,
> -	       ARM_ARCH_NONE,
> -	       FPU_ARCH_NEON_VFP_V4),
> -  ARM_CPU_OPT ("cortex-a15",	  "Cortex-A15",	       ARM_ARCH_V7VE,
> -	       ARM_ARCH_NONE,
> -	       FPU_ARCH_NEON_VFP_V4),
> -  ARM_CPU_OPT ("cortex-a17",	  "Cortex-A17",	       ARM_ARCH_V7VE,
> -	       ARM_ARCH_NONE,
> -	       FPU_ARCH_NEON_VFP_V4),
> -  ARM_CPU_OPT ("cortex-a32",	  "Cortex-A32",	       ARM_ARCH_V8A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("cortex-a35",	  "Cortex-A35",	       ARM_ARCH_V8A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("cortex-a53",	  "Cortex-A53",	       ARM_ARCH_V8A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("cortex-a55",    "Cortex-A55",	       ARM_ARCH_V8_2A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
> -  ARM_CPU_OPT ("cortex-a57",	  "Cortex-A57",	       ARM_ARCH_V8A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("cortex-a72",	  "Cortex-A72",	       ARM_ARCH_V8A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
> -	      FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("cortex-a73",	  "Cortex-A73",	       ARM_ARCH_V8A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
> -	      FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("cortex-a75",    "Cortex-A75",	       ARM_ARCH_V8_2A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
> -  ARM_CPU_OPT ("cortex-a76",    "Cortex-A76",	       ARM_ARCH_V8_2A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
> -  ARM_CPU_OPT ("cortex-a76ae",    "Cortex-A76AE",      ARM_ARCH_V8_2A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
> -  ARM_CPU_OPT ("cortex-a77",    "Cortex-A77",	       ARM_ARCH_V8_2A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
> -  ARM_CPU_OPT ("cortex-a78",   "Cortex-A78",	       ARM_ARCH_V8_2A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
> -	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("cortex-a78ae",   "Cortex-A78AE",	   ARM_ARCH_V8_2A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
> -	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("cortex-a78c",   "Cortex-A78C",	   ARM_ARCH_V8_2A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
> -	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("cortex-a710",   "Cortex-A710",	   ARM_ARCH_V9A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
> -				    | ARM_EXT2_BF16
> -				    | ARM_EXT2_I8MM),
> -	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("ares",    "Ares",	       ARM_ARCH_V8_2A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
> +  ARM_CPU_OPT2 ("cortex-a5",	  "Cortex-A5",	       ARM_ARCH_V7A,
> +	       ARM_FEATURE (ARM_EXT_MP | ARM_EXT_SEC,
> +	       ARM_EXT2_FP16_INST,
> +	       FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA),
> +	       FPU_ARCH_NEON_VFP_V4,
> +	       cortex_a5),
> +  ARM_CPU_OPT2 ("cortex-a7",	  "Cortex-A7",	       ARM_ARCH_V7VE,
> +	       ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1 |
> +	       FPU_NEON_EXT_FMA),
> +	       FPU_ARCH_NEON_VFP_V4,
> +	       cortex_a7),
> +  ARM_CPU_OPT2 ("cortex-a8",	  "Cortex-A8",	       ARM_ARCH_V7A,
> +	       ARM_FEATURE_LOW (ARM_EXT_SEC, FPU_VFP_V3 | FPU_NEON_EXT_V1),
> +	       ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1),
> +	       cortex_a8),
> +  ARM_CPU_OPT2 ("cortex-a9",	  "Cortex-A9",	       ARM_ARCH_V7A,
> +	       ARM_FEATURE (ARM_EXT_MP | ARM_EXT_SEC,
> +	       ARM_EXT2_FP16_INST,
> +	       FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA),
> +	       FPU_ARCH_NEON_VFP_V4,
> +	       cortex_a9),
> +  ARM_CPU_OPT2 ("cortex-a12",	  "Cortex-A12",	       ARM_ARCH_V7VE,
> +	       ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1 |
> +	       FPU_NEON_EXT_FMA),
> +	       FPU_ARCH_NEON_VFP_V4,
> +	       cortex_a12),
> +  ARM_CPU_OPT2 ("cortex-a15",	  "Cortex-A15",	       ARM_ARCH_V7VE,
> +	       ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1 |
> +	       FPU_NEON_EXT_FMA),
> +	       FPU_ARCH_NEON_VFP_V4,
> +	       cortex_a15),
> +  ARM_CPU_OPT2 ("cortex-a17",	  "Cortex-A17",	       ARM_ARCH_V7VE,
> +	       ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1 |
> +	       FPU_NEON_EXT_FMA),
> +	       FPU_ARCH_NEON_VFP_V4,
> +	       cortex_a17),
> +  ARM_CPU_OPT2 ("cortex-a32",	  "Cortex-A32",	       ARM_ARCH_V8A,
> +	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
> +	       FPU_ARCH_NEON_VFP_ARMV8,
> +	       cortex_a32),
> +  ARM_CPU_OPT2 ("cortex-a35",	  "Cortex-A35",	       ARM_ARCH_V8A,
> +	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
> +	       FPU_ARCH_NEON_VFP_ARMV8,
> +	       cortex_a35),
> +  ARM_CPU_OPT2 ("cortex-a53",	  "Cortex-A53",	       ARM_ARCH_V8A,
> +	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
> +	       FPU_ARCH_NEON_VFP_ARMV8,
> +	       cortex_a53),
> +  ARM_CPU_OPT2 ("cortex-a55",    "Cortex-A55",	       ARM_ARCH_V8_2A,
> +	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +	       cortex_a55),
> +  ARM_CPU_OPT2 ("cortex-a57",	  "Cortex-A57",	       ARM_ARCH_V8A,
> +	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
> +	       FPU_ARCH_NEON_VFP_ARMV8,
> +	       cortex_a57),
> +  ARM_CPU_OPT2 ("cortex-a72",	  "Cortex-A72",	       ARM_ARCH_V8A,
> +	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
> +	       FPU_ARCH_NEON_VFP_ARMV8,
> +	       cortex_a72),
> +  ARM_CPU_OPT2 ("cortex-a73",	  "Cortex-A73",	       ARM_ARCH_V8A,
> +	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
> +	       FPU_ARCH_NEON_VFP_ARMV8,
> +	       cortex_a73),
> +  ARM_CPU_OPT2 ("cortex-a75",    "Cortex-A75",	       ARM_ARCH_V8_2A,
> +	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +	       cortex_a75),
> +  ARM_CPU_OPT2 ("cortex-a76",    "Cortex-A76",	       ARM_ARCH_V8_2A,
> +	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +	       FPU_ARCH_VFP_V5_SP_D16,
> +	       cortex_a76),
> +  ARM_CPU_OPT2 ("cortex-a76ae",    "Cortex-A76AE",      ARM_ARCH_V8_2A,
> +	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +	       FPU_ARCH_VFP_V5_SP_D16,
> +	       cortex_a76ae),
> +  ARM_CPU_OPT2 ("cortex-a77",    "Cortex-A77",	       ARM_ARCH_V8_2A,
> +	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +	       FPU_ARCH_VFP_V5_SP_D16,
> +	       cortex_a77),
> +  ARM_CPU_OPT2 ("cortex-a78",   "Cortex-A78",	       ARM_ARCH_V8_2A,
> +	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +	       FPU_ARCH_VFP_V5_SP_D16,
> +	       cortex_a78),
> +  ARM_CPU_OPT2 ("cortex-a78ae",   "Cortex-A78AE",	   ARM_ARCH_V8_2A,
> +	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +	       FPU_ARCH_VFP_V5_SP_D16,
> +	       cortex_a78ae),
> +  ARM_CPU_OPT2 ("cortex-a78c",   "Cortex-A78C",	   ARM_ARCH_V8_2A,
> +	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +	       FPU_ARCH_VFP_V5_SP_D16,
> +	       cortex_a78c),
>    ARM_CPU_OPT ("cortex-r4",	  "Cortex-R4",	       ARM_ARCH_V7R,
>  	       ARM_ARCH_NONE,
>  	       FPU_ARCH_SOFTVFP),
>    ARM_CPU_OPT ("cortex-r4f",	  "Cortex-R4F",	       ARM_ARCH_V7R,
> -	       ARM_ARCH_NONE,
> -	       FPU_ARCH_VFP_V3D16),
> -  ARM_CPU_OPT ("cortex-r5",	  "Cortex-R5",	       ARM_ARCH_V7R,
> -	       ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
> -	       FPU_ARCH_SOFTVFP),
> -  ARM_CPU_OPT ("cortex-r7",	  "Cortex-R7",	       ARM_ARCH_V7R,
> -	       ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
> -	       FPU_ARCH_VFP_V3D16),
> -  ARM_CPU_OPT ("cortex-r8",	  "Cortex-R8",	       ARM_ARCH_V7R,
> -	       ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
> +	       FPU_ARCH_VFP_V3D16,
>  	       FPU_ARCH_VFP_V3D16),
> -  ARM_CPU_OPT ("cortex-r52",	  "Cortex-R52",	       ARM_ARCH_V8R,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
> -	      FPU_ARCH_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("cortex-r52plus",	  "Cortex-R52+",	       ARM_ARCH_V8R,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
> -	      FPU_ARCH_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("cortex-m35p",	  "Cortex-M35P",       ARM_ARCH_V8M_MAIN,
> -	       ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
> -	       FPU_ARCH_SOFTVFP),
> -  ARM_CPU_OPT ("cortex-m33",	  "Cortex-M33",	       ARM_ARCH_V8M_MAIN,
> -	       ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
> -	       FPU_ARCH_SOFTVFP),
> +  ARM_CPU_OPT2 ("cortex-r5",	  "Cortex-R5",	       ARM_ARCH_V7R,
> +	       ARM_FEATURE (ARM_EXT_ADIV, 0, FPU_VFP_V3),
> +	       FPU_ARCH_VFP_V3,
> +	       cortex_r5),
> +  ARM_CPU_OPT2 ("cortex-r7",	  "Cortex-R7",	       ARM_ARCH_V7R,
> +	       ARM_FEATURE (ARM_EXT_ADIV, 0, FPU_VFP_V3D16 | FPU_VFP_EXT_FP16),
> +	       FPU_ARCH_VFP_V3D16_FP16,
> +	       cortex_r7),
> +  ARM_CPU_OPT2 ("cortex-r8",	  "Cortex-R8",	       ARM_ARCH_V7R,
> +	       ARM_FEATURE (ARM_EXT_ADIV, 0, FPU_VFP_V3D16 | FPU_VFP_EXT_FP16),
> +	       FPU_ARCH_VFP_V3D16_FP16,
> +	       cortex_r8),
> +  ARM_CPU_OPT2 ("cortex-r52",	  "Cortex-R52",	       ARM_ARCH_V8R,
> +	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
> +         FPU_ARCH_NEON_VFP_ARMV8,
> +	       cortex_r52),
> +  ARM_CPU_OPT2 ("cortex-r52plus",	  "Cortex-R52+",	ARM_ARCH_V8R,
> +	       ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
> +         FPU_ARCH_NEON_VFP_ARMV8,
> +	       cortex_r52plus),
> +  ARM_CPU_OPT2 ("cortex-m85",	 "Cortex-M85",	       ARM_ARCH_V8_1M_MAIN,
> +	       ARM_FEATURE_ALL(ARM_AEXT_V8M_MAIN_DSP,
> +	       ARM_EXT2_FP16_INST | ARM_EXT2_MVE | ARM_EXT2_MVE_FP,
> +	       ARM_EXT3_PACBTI,
> +	       FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA),
> +	       FPU_ARCH_SOFTVFP,
> +	       cortex_m85),
> +  ARM_CPU_OPT2 ("cortex-m55",	 "Cortex-M55",	       ARM_ARCH_V8_1M_MAIN,
> +	       ARM_FEATURE_ALL(ARM_AEXT_V8M_MAIN_DSP,
> +	       ARM_EXT2_FP16_INST | ARM_EXT2_MVE | ARM_EXT2_MVE_FP,
> +	       0, FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA),
> +	       FPU_ARCH_SOFTVFP,
> +	       cortex_m55),
> +  ARM_CPU_OPT2 ("cortex-m52",	 "Cortex-M52",	       ARM_ARCH_V8_1M_MAIN,
> +	       ARM_FEATURE_ALL (ARM_AEXT_V8M_MAIN_DSP,
> +	       ARM_EXT2_FP16_INST | ARM_EXT2_MVE | ARM_EXT2_MVE_FP,
> +	       ARM_EXT3_PACBTI,
> +	       FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA),
> +	       FPU_ARCH_SOFTVFP,
> +	       cortex_m52),
> +  ARM_CPU_OPT2 ("cortex-m35p",	  "Cortex-M35P",       ARM_ARCH_V8M_MAIN,
> +	       ARM_FEATURE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP, FPU_VFP_V4D16),
> +	       FPU_ARCH_VFP_V3D16,
> +	       cortex_m35p),
> +  ARM_CPU_OPT2 ("cortex-m33",	  "Cortex-M33",	       ARM_ARCH_V8M_MAIN,
> +	       ARM_FEATURE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP, FPU_VFP_V4D16),
> +	       FPU_ARCH_VFP_V3D16, cortex_m33),
>    ARM_CPU_OPT ("cortex-m23",	  "Cortex-M23",	       ARM_ARCH_V8M_BASE,
>  	       ARM_ARCH_NONE,
>  	       FPU_ARCH_SOFTVFP),
> -  ARM_CPU_OPT ("cortex-m7",	  "Cortex-M7",	       ARM_ARCH_V7EM,
> -	       ARM_ARCH_NONE,
> -	       FPU_ARCH_SOFTVFP),
> -  ARM_CPU_OPT ("cortex-m4",	  "Cortex-M4",	       ARM_ARCH_V7EM,
> -	       ARM_ARCH_NONE,
> -	       FPU_ARCH_SOFTVFP),
> +  ARM_CPU_OPT2 ("cortex-m7",	  "Cortex-M7",	       ARM_ARCH_V7EM,
> +	       ARM_FEATURE_COPROC (FPU_VFP_V5D16),
More indentation issues here and below, ARM_CPU_OPT2 is longer than ARM_CPU_OPT.

> +	       FPU_ARCH_VFP_V5D16,
> +	       cortex_m7),
> +  ARM_CPU_OPT2 ("cortex-m4",	  "Cortex-M4",	       ARM_ARCH_V7EM,
> +	       ARM_FEATURE_COPROC (FPU_VFP_V4_SP_D16),
> +	       FPU_ARCH_VFP_V4_SP_D16,
> +	       cortex_m4),
>    ARM_CPU_OPT ("cortex-m3",	  "Cortex-M3",	       ARM_ARCH_V7M,
>  	       ARM_ARCH_NONE,
>  	       FPU_ARCH_SOFTVFP),
> @@ -30883,28 +31268,47 @@ static const struct arm_cpu_option_table arm_cpus[] =
>    ARM_CPU_OPT ("cortex-m0plus",	  "Cortex-M0+",	       ARM_ARCH_V6SM,
>  	       ARM_ARCH_NONE,
>  	       FPU_ARCH_SOFTVFP),
> -  ARM_CPU_OPT ("cortex-x1",   "Cortex-X1",	       ARM_ARCH_V8_2A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
> -	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("cortex-x1c",   "Cortex-X1C",	       ARM_ARCH_V8_2A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
> -	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("exynos-m1",	  "Samsung Exynos M1", ARM_ARCH_V8A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("neoverse-n1",    "Neoverse N1",	       ARM_ARCH_V8_2A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
> -  ARM_CPU_OPT ("neoverse-n2",	 "Neoverse N2",	       ARM_ARCH_V8_5A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
> -				    | ARM_EXT2_BF16
> -				    | ARM_EXT2_I8MM),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4),
> -  ARM_CPU_OPT ("neoverse-v1", "Neoverse V1", ARM_ARCH_V8_4A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
> -				    | ARM_EXT2_BF16
> -				    | ARM_EXT2_I8MM),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4),
> +  ARM_CPU_OPT2 ("cortex-x1",   "Cortex-X1",	       ARM_ARCH_V8_2A,
> +	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +	       FPU_ARCH_VFP_V5_SP_D16,
> +	       cortex_x1),
> +  ARM_CPU_OPT2 ("cortex-x1c",   "Cortex-X1C",	       ARM_ARCH_V8_2A,
> +	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +	       FPU_ARCH_VFP_V5_SP_D16,
> +	       cortex_x1c),
> +  ARM_CPU_OPT2 ("exynos-m1",	  "Samsung Exynos M1", ARM_ARCH_V8A,
> +	       ARM_FEATURE (0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
> +         FPU_ARCH_NEON_VFP_ARMV8,
> +	       exynos_m1),
> +  ARM_CPU_OPT2 ("neoverse-n1",	 "Neoverse N1",	       ARM_ARCH_V8_2A,
> +	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +	       FPU_ARCH_VFP_V5_SP_D16,
> +	       neoverse_n1),
> +  ARM_CPU_OPT2 ("ares",    "Ares",	       ARM_ARCH_V8_2A,
> +	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +	       FPU_ARCH_VFP_V5_SP_D16,
> +	       neoverse_n1),
> +  ARM_CPU_OPT2 ("neoverse-n2",	 "Neoverse N2",	       ARM_ARCH_V9A,
> +	       ARM_FEATURE(0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML |
> +	       ARM_EXT2_BF16 | ARM_EXT2_I8MM,
> +	       FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8 |
> +	       FPU_NEON_EXT_DOTPROD | FPU_NEON_EXT_RDMA),
> +	       FPU_ARCH_VFP_V5_SP_D16,
> +	       neoverse_n2),

This should be written something like:
  ARM_CPU_OPT2 ("neoverse-n2",	 "Neoverse N2",	       ARM_ARCH_V9A,
	        ARM_FEATURE(0, (ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML
			        | ARM_EXT2_BF16 | ARM_EXT2_I8MM),
	 		    (FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8
			     | FPU_NEON_EXT_DOTPROD | FPU_NEON_EXT_RDMA),
	        FPU_ARCH_VFP_V5_SP_D16,
	        neoverse_n2),

Note the use of additional parenthesis around the parameter that is broken across more than one line.  But it might be better to have the long argument on a line, or lines, of its own:

  ARM_CPU_OPT2 ("neoverse-n2",	 "Neoverse N2",	       ARM_ARCH_V9A,
	        ARM_FEATURE(0,
			    (ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML
			     | ARM_EXT2_BF16 | ARM_EXT2_I8MM),
	 		    (FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8
			     | FPU_NEON_EXT_DOTPROD | FPU_NEON_EXT_RDMA),
	        FPU_ARCH_VFP_V5_SP_D16,
	        neoverse_n2),

this makes the parameters easier to identify.

> +  ARM_CPU_OPT2 ("cortex-a710",	 "Cortex-A710",	   ARM_ARCH_V9A,
> +	       ARM_FEATURE(0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML |
> +		              ARM_EXT2_BF16 | ARM_EXT2_I8MM,
> +			      FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8 |
> +			      FPU_NEON_EXT_DOTPROD | FPU_NEON_EXT_RDMA),
> +	       FPU_ARCH_VFP_V5_SP_D16,
> +	       cortex_a710),
> +  ARM_CPU_OPT2 ("neoverse-v1",	 "Neoverse V1",	       ARM_ARCH_V8_4A,
> +	       ARM_FEATURE(0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML |
> +			      ARM_EXT2_BF16 | ARM_EXT2_I8MM,
> +			      FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8 |
> +			      FPU_NEON_EXT_DOTPROD),
> +	       FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +	       neoverse_v1),
>    /* ??? XSCALE is really an architecture.  */
>    ARM_CPU_OPT ("xscale",	  NULL,		       ARM_ARCH_XSCALE,
>  	       ARM_ARCH_NONE,
> @@ -30928,31 +31332,24 @@ static const struct arm_cpu_option_table arm_cpus[] =
>  
>    /* Marvell processors.  */
>    ARM_CPU_OPT ("marvell-pj4",	  NULL,		       ARM_ARCH_V7A,
> -	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
> -	       FPU_ARCH_VFP_V3D16),
> +	       ARM_FEATURE (ARM_EXT_MP | ARM_EXT_SEC, 0, FPU_VFP_V3),
> +	       FPU_ARCH_VFP_V3),
>    ARM_CPU_OPT ("marvell-whitney", NULL,		       ARM_ARCH_V7A,
>  	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
>  	       FPU_ARCH_NEON_VFP_V4),
>  
>    /* APM X-Gene family.  */
>    ARM_CPU_OPT ("xgene1",	  "APM X-Gene 1",      ARM_ARCH_V8A,
> -	       ARM_ARCH_NONE,
> +	       ARM_FEATURE (0, 0, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
>  	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
>    ARM_CPU_OPT ("xgene2",	  "APM X-Gene 2",      ARM_ARCH_V8A,
>  	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
>  	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
>  
> -  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL, NULL }
>  };
>  #undef ARM_CPU_OPT
> -
> -struct arm_ext_table
> -{
> -  const char *		  name;
> -  size_t		  name_len;
> -  const arm_feature_set	  merge;
> -  const arm_feature_set	  clear;
> -};
> +#undef ARM_CPU_OPT2
>  
>  struct arm_arch_option_table
>  {
> @@ -30963,16 +31360,6 @@ struct arm_arch_option_table
>    const struct arm_ext_table *	ext_table;
>  };
>  
> -/* Used to add support for +E and +noE extension.  */
> -#define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
> -/* Used to add support for a +E extension.  */
> -#define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
> -/* Used to add support for a +noE extension.  */
> -#define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
> -
> -#define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
> -			    ~0 & ~FPU_ENDIAN_PURE)
> -
>  static const struct arm_ext_table armv5te_ext_table[] =
>  {
>    ARM_EXT ("fp", FPU_ARCH_VFP_V2, ALL_FP),
> @@ -31169,16 +31556,6 @@ static const struct arm_ext_table armv9a_ext_table[] =
>  #define armv94a_ext_table armv93a_ext_table
>  #define armv95a_ext_table armv94a_ext_table
>  
> -#define CDE_EXTENSIONS \
> -  ARM_ADD ("cdecp0", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE0)), \
> -  ARM_ADD ("cdecp1", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE1)), \
> -  ARM_ADD ("cdecp2", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE2)), \
> -  ARM_ADD ("cdecp3", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE3)), \
> -  ARM_ADD ("cdecp4", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE4)), \
> -  ARM_ADD ("cdecp5", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE5)), \
> -  ARM_ADD ("cdecp6", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE6)), \
> -  ARM_ADD ("cdecp7", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE7))
> -
>  static const struct arm_ext_table armv8m_main_ext_table[] =
>  {
>    ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP),
> @@ -31755,7 +32132,7 @@ arm_parse_cpu (const char *str)
>  	  }
>  
>  	if (ext != NULL)
> -	  return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, NULL);
> +	  return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, opt->ext_table);
>  
>  	return true;
>        }
> diff --git a/gas/testsuite/gas/arm/attr-cpu-directive.d b/gas/testsuite/gas/arm/attr-cpu-directive.d
> index a2ab435fc0a..62a07adb4de 100644
> --- a/gas/testsuite/gas/arm/attr-cpu-directive.d
> +++ b/gas/testsuite/gas/arm/attr-cpu-directive.d
> @@ -12,4 +12,6 @@ File Attributes
>    Tag_CPU_arch_profile: Application
>    Tag_ARM_ISA_use: Yes
>    Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: VFPv3
> +  Tag_Advanced_SIMD_arch: NEONv1
>    Tag_Virtualization_use: TrustZone
> diff --git a/gas/testsuite/gas/arm/command-line-mcpu.exp b/gas/testsuite/gas/arm/command-line-mcpu.exp
> new file mode 100644
> index 00000000000..fc52296f882
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/command-line-mcpu.exp
> @@ -0,0 +1,134 @@
> +
> +if {[istarget arm*-*-*]} {
> +    gas_test_old "feat-mp.s" "-mcpu=cortex-a5" "gas/arm: cortex-a5 feat-mp"
> +    gas_test_old "feat-sec.s" "-mcpu=cortex-a5" "gas/arm: cortex-a5 feat-sec"
> +    gas_test_old "feat-neon-fp16.s" "-mcpu=cortex-a5" "gas/arm: cortex-a5 feat-neon-fp16"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-a5+nofp+nosimd" "gas/arm: cortex-a5 exts"
> +    gas_test_old "feat-simd.s" "-mcpu=cortex-a7" "gas/arm: cortex-a7 feat-simd"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-a7+nofp+nosimd" "gas/arm: cortex-a7 exts"
> +    gas_test_old "feat-simd.s" "-mcpu=cortex-a8" "gas/arm: cortex-a8 feat-simd"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-a8+nofp" "gas/arm: cortex-a8 exts"
> +    gas_test_old "feat-mp.s" "-mcpu=cortex-a9" "gas/arm: cortex-a9 feat-mp"
> +    gas_test_old "feat-sec.s" "-mcpu=cortex-a9" "gas/arm: cortex-a9 feat-sec"
> +    gas_test_old "feat-neon-fp16.s" "-mcpu=cortex-a9" "gas/arm: cortex-a9 feat-neon-fp16"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-a9+nofp+nosimd" "gas/arm: cortex-a9 exts"
> +    gas_test_old "feat-simd.s" "-mcpu=cortex-a12" "gas/arm: cortex-a12 feat-simd"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-a12+nofp" "gas/arm: cortex-a12 exts"
> +    gas_test_old "feat-simd.s" "-mcpu=cortex-a15" "gas/arm: cortex-a15 feat-simd"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-a15+nofp" "gas/arm: cortex-a15 exts"
> +    gas_test_old "feat-simd.s" "-mcpu=cortex-a17" "gas/arm: cortex-a17 feat-simd"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-a17+nofp" "gas/arm: cortex-a17 exts"
> +    gas_test_old "feat-mp.s" "-mcpu=marvell-pj4" "gas/arm: marvell-pj4 feat-mp"
> +    gas_test_old "feat-sec.s" "-mcpu=marvell-pj4" "gas/arm: marvell-pj4 feat-sec"
> +    gas_test_old "feat-fp-vfpv3.s" "-mcpu=marvell-pj4" "gas/arm: marvell-pj4 feat-fp-vfpv3"
> +    gas_test_old "feat-fp-vfpv3.s" "-mcpu=cortex-r4f" "gas/arm: cortex-r4f feat-fp-vfpv3"
> +    gas_test_old "feat-fp-vfpv3.s" "-mcpu=cortex-r5" "gas/arm: cortex-r5 feat-fp-vfpv3"
> +    gas_test_old "feat-idiv.s" "-mcpu=cortex-r5" "gas/arm: cortex-r5 feat-idiv"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-r5+nofp+nofp.dp" "gas/arm: cortex-r5 exts"
> +    gas_test_old "feat-idiv.s" "-mcpu=cortex-r7" "gas/arm: cortex-r7 feat-idiv"
> +    gas_test_old "feat-vfpv3-d16-fp16.s" "-mcpu=cortex-r7" "gas/arm: cortex-r7 feat-vfpv3-d16-fp16"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-r7+nofp+nofp.dp" "gas/arm: cortex-r7 exts"
> +    gas_test_old "feat-idiv.s" "-mcpu=cortex-r8" "gas/arm: cortex-r8 feat-idiv"
> +    gas_test_old "feat-vfpv3-d16-fp16.s" "-mcpu=cortex-r8" "gas/arm: cortex-r8 feat-vfpv3-d16-fp16"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-r8+nofp+nofp.dp" "gas/arm: cortex-r8 exts"
> +    gas_test_old "feat-fp-vfpv3.s" "-mcpu=cortex-m4" "gas/arm: cortex-m4 feat-fp-vfpv3"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-m4+nofp" "gas/arm: cortex-m4 exts"
> +    gas_test_old "feat-fp.dp.s" "-mcpu=cortex-m7" "gas/arm: cortex-m7 feat-fp.dp"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-m7+nofp+nofp.dp" "gas/arm: cortex-m7 exts"
> +    gas_test_old "feat-crc.s" "-mcpu=cortex-a32" "gas/arm: cortex-a32 feat-crc"
> +    gas_test_old "feat-simd.s" "-mcpu=cortex-a32" "gas/arm: cortex-a32 feat-simd"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-a32+nofp" "gas/arm: cortex-a32 exts"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-a32+crypto" "gas/arm: cortex-a32 exts"
> +    gas_test_old "feat-crc.s" "-mcpu=cortex-a35" "gas/arm: cortex-a35 feat-crc"
> +    gas_test_old "feat-simd.s" "-mcpu=cortex-a35" "gas/arm: cortex-a35 feat-simd"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-a35+nofp" "gas/arm: cortex-a35 exts"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-a35+crypto" "gas/arm: cortex-a35 exts"
> +    gas_test_old "feat-crc.s" "-mcpu=cortex-a53" "gas/arm: cortex-a53 feat-crc"
> +    gas_test_old "feat-simd.s" "-mcpu=cortex-a53" "gas/arm: cortex-a53 feat-simd"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-a53+nofp" "gas/arm: cortex-a53 exts"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-a53+crypto" "gas/arm: cortex-a53 exts"
> +    gas_test_old "feat-crc.s" "-mcpu=cortex-a57" "gas/arm: cortex-a57 feat-crc"
> +    gas_test_old "feat-simd.s" "-mcpu=cortex-a57" "gas/arm: cortex-a57 feat-simd"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-a57+crypto" "gas/arm: cortex-a57 exts"
> +    gas_test_old "feat-crc.s" "-mcpu=cortex-a72" "gas/arm: cortex-a72 feat-crc"
> +    gas_test_old "feat-simd.s" "-mcpu=cortex-a72" "gas/arm: cortex-a72 feat-simd"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-a72+crypto" "gas/arm: cortex-a72 exts"
> +    gas_test_old "feat-crc.s" "-mcpu=cortex-a73" "gas/arm: cortex-a73 feat-crc"
> +    gas_test_old "feat-simd.s" "-mcpu=cortex-a73" "gas/arm: cortex-a73 feat-simd"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-a73+crypto" "gas/arm: cortex-a73 exts"
> +    gas_test_old "feat-crc.s" "-mcpu=exynos-m1" "gas/arm: exynos-m1 feat-crc"
> +    gas_test_old "feat-simd.s" "-mcpu=exynos-m1" "gas/arm: exynos-m1 feat-simd"
> +    gas_test_old "nop-asm.s" "-mcpu=exynos-m1+crypto" "gas/arm: exynos-m1 exts"
> +    gas_test_old "feat-simd.s" "-mcpu=xgene1" "gas/arm: xgene1 feat-simd"
> +    gas_test_old "feat-crc.s" "-mcpu=cortex-r52" "gas/arm: cortex-r52 feat-crc"
> +    gas_test_old "feat-simd.s" "-mcpu=cortex-r52" "gas/arm: cortex-r52 feat-simd"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-r52+nofp.dp" "gas/arm: cortex-r52 exts"
> +    gas_test_old "feat-crc.s" "-mcpu=cortex-r52plus" "gas/arm: cortex-r52plus feat-crc"
> +    gas_test_old "feat-simd.s" "-mcpu=cortex-r52plus" "gas/arm: cortex-r52plus feat-simd"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-r52plus+nofp.dp" "gas/arm: cortex-r52plus exts"
> +    gas_test_old "feat-dsp.s" "-mcpu=cortex-m33" "gas/arm: cortex-m33 feat-dsp"
> +    gas_test_old "feat-fp-vfpv5.s" "-mcpu=cortex-m33" "gas/arm: cortex-m33 feat-fp-vfpv5"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-m33+nofp+nodsp" "gas/arm: cortex-m33 exts"
> +    gas_test_old "feat-dsp.s" "-mcpu=cortex-m35p" "gas/arm: cortex-m35p feat-dsp"
> +    gas_test_old "feat-fp-vfpv5.s" "-mcpu=cortex-m35p" "gas/arm: cortex-m35p feat-fp-vfpv5"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-m35p+nofp+nodsp" "gas/arm: cortex-m35p exts"
> +    gas_test_old "feat-pacbti.s" "-mcpu=cortex-m52" "gas/arm: cortex-m52 feat-pacbti"
> +    gas_test_old "feat-mve.fp.s" "-mcpu=cortex-m52" "gas/arm: cortex-m52 feat-mve.fp"
> +    gas_test_old "feat-fp.dp.s" "-mcpu=cortex-m52" "gas/arm: cortex-m52 feat-fp.dp"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-m52+nopacbti+nomve.fp+nomve+nofp+nodsp" "gas/arm: cortex-m52 exts"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-m52+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7" "gas/arm: cortex-m52 exts"
> +    gas_test_old "feat-mve.fp.s" "-mcpu=cortex-m55" "gas/arm: cortex-m55 feat-mve.fp"
> +    gas_test_old "feat-fp.dp.s" "-mcpu=cortex-m55" "gas/arm: cortex-m55 feat-fp.dp"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-m55+nomve.fp+nomve+nofp+nodsp" "gas/arm: cortex-m55 exts"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-m55+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7" "gas/arm: cortex-m55 exts"
> +    gas_test_old "feat-pacbti.s" "-mcpu=cortex-m85" "gas/arm: cortex-m85 feat-pacbti"
> +    gas_test_old "feat-mve.fp.s" "-mcpu=cortex-m85" "gas/arm: cortex-m85 feat-mve.fp"
> +    gas_test_old "feat-fp.dp.s" "-mcpu=cortex-m85" "gas/arm: cortex-m85 feat-fp.dp"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-m85+nopacbti+nomve.fp+nomve+nofp+nodsp" "gas/arm: cortex-m85 exts"
> +    gas_test_old "feat-fp16.s" "-mcpu=cortex-a55" "gas/arm: cortex-a55 feat-fp16"
> +    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a55" "gas/arm: cortex-a55 feat-dotprod"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-a55+nofp" "gas/arm: cortex-a55 exts"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-a55+crypto" "gas/arm: cortex-a55 exts"
> +    gas_test_old "feat-fp16.s" "-mcpu=cortex-a75" "gas/arm: cortex-a75 feat-fp16"
> +    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a75" "gas/arm: cortex-a75 feat-dotprod"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-a75+crypto" "gas/arm: cortex-a75 exts"
> +    gas_test_old "feat-fp16.s" "-mcpu=cortex-a76" "gas/arm: cortex-a76 feat-fp16"
> +    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a76" "gas/arm: cortex-a76 feat-dotprod"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-a76+crypto" "gas/arm: cortex-a76 exts"
> +    gas_test_old "feat-fp16.s" "-mcpu=cortex-a76ae" "gas/arm: cortex-a76ae feat-fp16"
> +    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a76ae" "gas/arm: cortex-a76ae feat-dotprod"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-a76ae+crypto" "gas/arm: cortex-a76ae exts"
> +    gas_test_old "feat-fp16.s" "-mcpu=cortex-a77" "gas/arm: cortex-a77 feat-fp16"
> +    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a77" "gas/arm: cortex-a77 feat-dotprod"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-a77+crypto" "gas/arm: cortex-a77 exts"
> +    gas_test_old "feat-fp16.s" "-mcpu=cortex-a78" "gas/arm: cortex-a78 feat-fp16"
> +    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a78" "gas/arm: cortex-a78 feat-dotprod"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-a78+crypto" "gas/arm: cortex-a78 exts"
> +    gas_test_old "feat-fp16.s" "-mcpu=cortex-a78ae" "gas/arm: cortex-a78ae feat-fp16"
> +    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a78ae" "gas/arm: cortex-a78ae feat-dotprod"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-a78ae+crypto" "gas/arm: cortex-a78ae exts"
> +    gas_test_old "feat-fp16.s" "-mcpu=cortex-a78c" "gas/arm: cortex-a78c feat-fp16"
> +    gas_test_old "feat-dotprod.s" "-mcpu=cortex-a78c" "gas/arm: cortex-a78c feat-dotprod"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-a78c+crypto" "gas/arm: cortex-a78c exts"
> +    gas_test_old "feat-fp16.s" "-mcpu=cortex-x1" "gas/arm: cortex-x1 feat-fp16"
> +    gas_test_old "feat-dotprod.s" "-mcpu=cortex-x1" "gas/arm: cortex-x1 feat-dotprod"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-x1+crypto" "gas/arm: cortex-x1 exts"
> +    gas_test_old "feat-fp16.s" "-mcpu=cortex-x1c" "gas/arm: cortex-x1c feat-fp16"
> +    gas_test_old "feat-dotprod.s" "-mcpu=cortex-x1c" "gas/arm: cortex-x1c feat-dotprod"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-x1c+crypto" "gas/arm: cortex-x1c exts"
> +    gas_test_old "feat-fp16.s" "-mcpu=neoverse-n1" "gas/arm: neoverse-n1 feat-fp16"
> +    gas_test_old "feat-dotprod.s" "-mcpu=neoverse-n1" "gas/arm: neoverse-n1 feat-dotprod"
> +    gas_test_old "nop-asm.s" "-mcpu=neoverse-n1+crypto" "gas/arm: neoverse-n1 exts"
> +    gas_test_old "feat-fp16.s" "-mcpu=neoverse-v1" "gas/arm: neoverse-v1 feat-fp16"
> +    gas_test_old "feat-bf16.s" "-mcpu=neoverse-v1" "gas/arm: neoverse-v1 feat-bf16"
> +    gas_test_old "feat-i8mm.s" "-mcpu=neoverse-v1" "gas/arm: neoverse-v1 feat-i8mm"
> +    gas_test_old "nop-asm.s" "-mcpu=neoverse-v1+crypto" "gas/arm: neoverse-v1 exts"
> +    gas_test_old "feat-fp16.s" "-mcpu=cortex-a710" "gas/arm: cortex-a710 feat-fp16"
> +    gas_test_old "feat-bf16.s" "-mcpu=cortex-a710" "gas/arm: cortex-a710 feat-bf16"
> +    gas_test_old "feat-i8mm.s" "-mcpu=cortex-a710" "gas/arm: cortex-a710 feat-i8mm"
> +    gas_test_old "nop-asm.s" "-mcpu=cortex-a710+crypto" "gas/arm: cortex-a710 exts"
> +    gas_test_old "feat-fp16.s" "-mcpu=neoverse-n2" "gas/arm: neoverse-n2 feat-fp16"
> +    gas_test_old "feat-bf16.s" "-mcpu=neoverse-n2" "gas/arm: neoverse-n2 feat-bf16"
> +    gas_test_old "feat-i8mm.s" "-mcpu=neoverse-n2" "gas/arm: neoverse-n2 feat-i8mm"
> +    gas_test_old "nop-asm.s" "-mcpu=neoverse-n2+crypto" "gas/arm: neoverse-n2 exts"
> +}

It seems odd to be adding new tests using 'gas_test_old'.  I think it would be better to add some dump tests which can then also check that the correct build attributes are added (much like the attr-cpu-directive test does).

> diff --git a/gas/testsuite/gas/arm/feat-bf16.s b/gas/testsuite/gas/arm/feat-bf16.s
> new file mode 100644
> index 00000000000..46fc48ba567
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-bf16.s
> @@ -0,0 +1,5 @@
> +.syntax unified
> +.thumb
> +
> +@ feat FP16
> +vdot.bf16 q0, q1, q2
> diff --git a/gas/testsuite/gas/arm/feat-crc.s b/gas/testsuite/gas/arm/feat-crc.s
> new file mode 100644
> index 00000000000..671ac14ebcb
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-crc.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ feat CRC
> +crc32w  r0, r0, r1
> diff --git a/gas/testsuite/gas/arm/feat-dotprod.s b/gas/testsuite/gas/arm/feat-dotprod.s
> new file mode 100644
> index 00000000000..775c3ba4c02
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-dotprod.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ feat DOTPROD
> +vudot.u8 q0, q1, q2
> diff --git a/gas/testsuite/gas/arm/feat-dsp.s b/gas/testsuite/gas/arm/feat-dsp.s
> new file mode 100644
> index 00000000000..2f54c7327d1
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-dsp.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ feat DSP
> +smlad   r0, r1, r2, r3
> diff --git a/gas/testsuite/gas/arm/feat-fp-vfpv3.s b/gas/testsuite/gas/arm/feat-fp-vfpv3.s
> new file mode 100644
> index 00000000000..4435db35690
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-fp-vfpv3.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ feat FP (VFP-v3)
> +vmla.f32 s0, s1, s2
> diff --git a/gas/testsuite/gas/arm/feat-fp-vfpv5.s b/gas/testsuite/gas/arm/feat-fp-vfpv5.s
> new file mode 100644
> index 00000000000..13a2e7aca9e
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-fp-vfpv5.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ feat FP (VFP-v5)
> +vfma.f32 s0, s1, s2
> diff --git a/gas/testsuite/gas/arm/feat-fp.dp.s b/gas/testsuite/gas/arm/feat-fp.dp.s
> new file mode 100644
> index 00000000000..34b68cd8603
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-fp.dp.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ feat FP.DP
> +vadd.f64 d0, d1, d2
> diff --git a/gas/testsuite/gas/arm/feat-fp.s b/gas/testsuite/gas/arm/feat-fp.s
> new file mode 100644
> index 00000000000..5cf49af0e9f
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-fp.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ feat FP
> +vadd.f32 s0, s1, s2
> diff --git a/gas/testsuite/gas/arm/feat-fp16.s b/gas/testsuite/gas/arm/feat-fp16.s
> new file mode 100644
> index 00000000000..6780678e8ca
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-fp16.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ feat FP16
> +vadd.f16 q0, q1, q2
> diff --git a/gas/testsuite/gas/arm/feat-i8mm.s b/gas/testsuite/gas/arm/feat-i8mm.s
> new file mode 100644
> index 00000000000..bb3818726a8
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-i8mm.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ feat I8MM
> +vusmmla.s8  q6, q7, q8
> diff --git a/gas/testsuite/gas/arm/feat-idiv.s b/gas/testsuite/gas/arm/feat-idiv.s
> new file mode 100644
> index 00000000000..8b289fa817d
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-idiv.s
> @@ -0,0 +1,3 @@
> +.syntax unified
> +
> +sdiv r0, r1, r2
> diff --git a/gas/testsuite/gas/arm/feat-mp.s b/gas/testsuite/gas/arm/feat-mp.s
> new file mode 100644
> index 00000000000..db365d7f282
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-mp.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ feat MP
> +ldrex r0, [r1]
> diff --git a/gas/testsuite/gas/arm/feat-mve.fp.s b/gas/testsuite/gas/arm/feat-mve.fp.s
> new file mode 100644
> index 00000000000..81c23300dc3
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-mve.fp.s
> @@ -0,0 +1,5 @@
> +.syntax unified
> +.thumb
> +
> +@ MVE.FP
> +vmul.f32 q0, q1, q2
> diff --git a/gas/testsuite/gas/arm/feat-neon-fp16.s b/gas/testsuite/gas/arm/feat-neon-fp16.s
> new file mode 100644
> index 00000000000..55ab08553bf
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-neon-fp16.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ feat NEON-FP16
> +vadd.f16 q0, q1, q2
> diff --git a/gas/testsuite/gas/arm/feat-pacbti.s b/gas/testsuite/gas/arm/feat-pacbti.s
> new file mode 100644
> index 00000000000..2399f0ca230
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-pacbti.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ PACBTI
> +pac     r12, lr, sp
> diff --git a/gas/testsuite/gas/arm/feat-sec.s b/gas/testsuite/gas/arm/feat-sec.s
> new file mode 100644
> index 00000000000..bdb516a30f4
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-sec.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ feat SEC
> +smc     #0
> diff --git a/gas/testsuite/gas/arm/feat-simd.s b/gas/testsuite/gas/arm/feat-simd.s
> new file mode 100644
> index 00000000000..871f5490902
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-simd.s
> @@ -0,0 +1,5 @@
> +.syntax unified
> +.text
> +
> +@ feat SIMD
> +vadd.i32 q0, q1, q2
> diff --git a/gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s b/gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s
> new file mode 100644
> index 00000000000..41ccd2d9414
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ feat VFP3-D16-FP16
> +vcvtt.f16.f32 s0, s1

R.

From gnutoolsweekly@gmail.com  Tue Jun 16 16:01:19 2026
From: gnutoolsweekly@gmail.com (GNU Tools weekly)
Date: Tue, 16 Jun 2026 09:01:19 -0700
Subject: Easy issue of the weekly
Message-ID: <CAHt=NyMdNWnLi8C-_97GgZf=+HHcVDZ_ktPHfb8f3yjqgK1jDQ@mail.gmail.com>

I mentioned when this was first posted about adding this to the
newsletter in Feburary
(https://inbox.sourceware.org/libc-alpha/CAHt=NyNhJhGsdDq1u-ByQs=C_dZOD8bssxc+pEydHvP=A2O9_w@mail.gmail.com/)
but I want to remind everyone that anyone is welcome to send me issues
to highlight and mentor. And that it is not limited to GCC issues
(glibc, gdb, binutils issues are all welcome). We can do more than 1
issue a week (like this past week). If there is a moderate issue you
want to highlight for someone to tackle it can be added as an
"moderate issue for the month". Or even a bigger harder issue we can
do it as a "hard issue for the year"; though those might be easier
sell for GSoC rather than the newsletter.

You can either email them to this email or to
andrew.pinski@oss.qualcomm.com or add them to the proposal section of
https://gcc.gnu.org/wiki/EasyIssuesOfTheWeek .

Thanks

From Richard.Earnshaw@arm.com  Tue Jun 16 16:06:47 2026
From: Richard.Earnshaw@arm.com (Richard Earnshaw (foss))
Date: Tue, 16 Jun 2026 17:06:47 +0100
Subject: [PATCH v8 1/1] aarch64: Implement Structured Exception Handling
 (SEH) on AArch64
In-Reply-To: <20260615160646.87169-2-evgeny.karpov@arm.com>
References: <20260615160646.87169-1-evgeny.karpov@arm.com>
 <20260615160646.87169-2-evgeny.karpov@arm.com>
Message-ID: <8c321c17-0fdf-4983-832d-0f1259bf0496@arm.com>

A couple of nits in addition to Jan's comments, but this is ok once those are fixed.

R.

On 15/06/2026 17:06, Evgeny Karpov wrote:
> The patch reuses shared helpers for SEH and implements SEH on AArch64.
> The implementation is based on
> (https://learn.microsoft.com/en-us/cpp/build/arm64-exception-handling?view=msvc-170)
> and pdata/xdata SEH records are emitted from md_finish.
> 
> When .pdata/.xdata is emitted, the function size is required.
> Function sizes are calculated as late as possible, and the code segment needs
> to be relaxed to be able to calculate the function sizes.
> 
> Initially, obj_coff_generate_pdata was called in write_object_file.
> Before the change, obj_coff_generate_pdata was used only to validate
> syntax, which was sufficient for that purpose. However, that location
> seems incorrect, as it is too late to emit .pdata/.xdata records
> in the AArch64 case.
> 
> md_finish has been declared for AArch64 and extended with
> seh_aarch64_write_data to emit .pdata/.xdata records after all
> assembly has been completed.
> 
> Signed-off-by: Evgeny Karpov <evgeny@kmaps.co>
> 
> gas/ChangeLog:
> 	* gas/config/obj-coff-seh-shared.c (defined): Update.
> 	(struct seh_seg_list): Use seh_context_t.
> 	* gas/config/obj-coff.c (defined): Update.
> 	* gas/config/tc-aarch64.c (defined): Add OBJ_COFF guard.
> 	(aarch64_md_finish): Add.
> 	* gas/config/tc-aarch64.h (defined): Add OBJ_COFF guard.
> 	(md_finish): Add.
> 	(aarch64_md_finish): Add.
> 	(seh_aarch64_write_data): Add.
> 	* testsuite/gas/pe/pe.exp: Add SEH tests.
> 	* write.c: Update.
> 	* write.h (subsegs_finish_section): Update.
> 	* config/obj-coff-seh-aarch64.c: New file.
> 	* config/obj-coff-seh-aarch64.h: New file.
> 	* testsuite/gas/pe/seh-aarch64-error.l: New test.
> 	* testsuite/gas/pe/seh-aarch64-error.s: New test.
> 	* testsuite/gas/pe/seh-aarch64-large-func.d: New test.
> 	* testsuite/gas/pe/seh-aarch64-large-func.s: New test.
> 	* testsuite/gas/pe/seh-aarch64.d: New test.
> 	* testsuite/gas/pe/seh-aarch64.s: New test.
> ---
>  gas/config/obj-coff-seh-aarch64.c             | 971 ++++++++++++++++++
>  gas/config/obj-coff-seh-aarch64.h             | 251 +++++
>  gas/config/obj-coff-seh-shared.c              |   8 +-
>  gas/config/obj-coff.c                         |   4 +
>  gas/config/tc-aarch64.c                       |  10 +
>  gas/config/tc-aarch64.h                       |   6 +
>  gas/testsuite/gas/pe/pe.exp                   |   3 +
>  gas/testsuite/gas/pe/seh-aarch64-error.l      | 110 ++
>  gas/testsuite/gas/pe/seh-aarch64-error.s      | 128 +++
>  gas/testsuite/gas/pe/seh-aarch64-large-func.d |  53 +
>  gas/testsuite/gas/pe/seh-aarch64-large-func.s |  13 +
>  gas/testsuite/gas/pe/seh-aarch64.d            |  66 ++
>  gas/testsuite/gas/pe/seh-aarch64.s            |  49 +
>  gas/write.c                                   |   2 +-
>  gas/write.h                                   |   1 +
>  15 files changed, 1673 insertions(+), 2 deletions(-)
>  create mode 100644 gas/config/obj-coff-seh-aarch64.c
>  create mode 100644 gas/config/obj-coff-seh-aarch64.h
>  create mode 100644 gas/testsuite/gas/pe/seh-aarch64-error.l
>  create mode 100644 gas/testsuite/gas/pe/seh-aarch64-error.s
>  create mode 100644 gas/testsuite/gas/pe/seh-aarch64-large-func.d
>  create mode 100644 gas/testsuite/gas/pe/seh-aarch64-large-func.s
>  create mode 100644 gas/testsuite/gas/pe/seh-aarch64.d
>  create mode 100644 gas/testsuite/gas/pe/seh-aarch64.s
> 
> diff --git a/gas/config/obj-coff-seh-aarch64.c b/gas/config/obj-coff-seh-aarch64.c
> new file mode 100644
> index 00000000000..b0d32c72d01
> --- /dev/null
> +++ b/gas/config/obj-coff-seh-aarch64.c
> @@ -0,0 +1,971 @@
> +/* SEH .pdata/.xdata COFF object file format on AArch64
> +   Copyright (C) 2026 Free Software Foundation, Inc.
> +
> +   This file is part of GAS.
> +
> +   GAS is free software; you can redistribute it and/or modify
> +   it under the terms of the GNU General Public License as published by
> +   the Free Software Foundation; either version 3, or (at your option)
> +   any later version.
> +
> +   GAS is distributed in the hope that it will be useful,
> +   but WITHOUT ANY WARRANTY; without even the implied warranty of
> +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +   GNU General Public License for more details.
> +
> +   You should have received a copy of the GNU General Public License
> +   along with GAS; see the file COPYING.  If not, write to the Free
> +   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
> +   02110-1301, USA.  */
> +
> +#include "obj-coff-seh-aarch64.h"
> +
> +static struct seh_aarch64_context *seh_ctx_root = NULL;
> +static bool in_seh_proc = false;
> +
> +struct aarch64_unwind_info {
> +  const char *directive;
> +  char reg_type;
> +  unsigned char offset_bits;
> +  unsigned char reg_bits;
> +  unsigned char reg_max;
> +  unsigned char code_bits;
> +  unsigned char code;
> +  unsigned char offset_shift;
> +  unsigned char offset_addend;
> +  unsigned char reg_shift;
> +  unsigned char reg_addend;
> +  unsigned char size;
> +};
> +
> +/* Unwind codes format for AArch64 are described at
> +   https://learn.microsoft.com/en-us/cpp/build/arm64-exception-handling?view=msvc-170#unwind-codes

I think we should avoid deep links like this in source code - they have a nasty habit of stopping working at some point in the future, especially given this seems to refer to a specific version of msvc.  A reasonable search engine will find a current link pretty quickly, so I don't think a full link is necessary.

> +   and calculated in seh_aarch64_add_unwind_element function.
> +   aarch64_unwind_code_data is indexed by the seh_aarch64_unwind_types enum.  */
> +
> +static const struct aarch64_unwind_info
> +aarch64_unwind_code_data[] = {
> +  {
> +    .size = 1,
> +    .code_bits = 3, .code = 0b000U,

0b as a prefix is (I believe) new in C23 (although many older versions of gcc support it).  I think we try to make code compatible with c11 compilers, so please use hex.  See eg PR28882.

> +    .offset_bits = 5, .offset_shift = 4
> +  },
> +  {
> +    .size = 2,
> +    .code_bits = 5, .code = 0b11000U,
> +    .offset_bits = 11, .offset_shift = 4
> +  },
> +  {
> +    .size = 4,
> +    .code_bits = 8, .code = 0b11100000U,
> +    .offset_bits = 24, .offset_shift = 4
> +  },
> +  {
> +    .directive = ".seh_save_reg",
> +    .size = 2,
> +    .code_bits = 6, .code = 0b110100U,
> +    .offset_bits = 6, .offset_shift = 3,
> +    .reg_bits = 4, .reg_addend = 19, .reg_type = 'x'
> +  },
> +  {
> +    .directive = ".seh_save_reg_x",
> +    .size = 2,
> +    .code_bits = 7, .code = 0b1101010U,
> +    .offset_bits = 5, .offset_shift = 3, .offset_addend = 1,
> +    .reg_bits = 4, .reg_addend = 19, .reg_type = 'x'
> +  },
> +  {
> +    .directive = ".seh_save_regp",
> +    .size = 2,
> +    .code_bits = 6, .code = 0b110010U,
> +    .offset_bits = 6, .offset_shift = 3,
> +    .reg_bits = 4, .reg_addend = 19, .reg_type = 'x', .reg_max = 29
> +  },
> +  {
> +    .directive = ".seh_save_regp_x",
> +    .size = 2,
> +    .code_bits = 6, .code = 0b110011U,
> +    .offset_bits = 6, .offset_shift = 3, .offset_addend = 1,
> +    .reg_bits = 4, .reg_addend = 19, .reg_type = 'x', .reg_max = 29
> +  },
> +  {
> +    .directive = ".seh_save_fregp",
> +    .size = 2,
> +    .code_bits = 7, .code = 0b1101100U,
> +    .offset_bits = 6, .offset_shift = 3,
> +    .reg_bits = 3, .reg_addend = 8, .reg_type = 'd'
> +  },
> +  {
> +    .directive = ".seh_save_fregp_x",
> +    .size = 2,
> +    .code_bits = 7, .code = 0b1101101U,
> +    .offset_bits = 6, .offset_shift = 3, .offset_addend = 1,
> +    .reg_bits = 3, .reg_addend = 8, .reg_type = 'd'
> +  },
> +  {
> +    .directive = ".seh_save_freg",
> +    .size = 2,
> +    .code_bits = 7, .code = 0b1101110U,
> +    .offset_bits = 6, .offset_shift = 3,
> +    .reg_bits = 3, .reg_addend = 8, .reg_type = 'd'
> +  },
> +  {
> +    .directive = ".seh_save_freg_x",
> +    .size = 2,
> +    .code_bits = 8, .code = 0b11011110U,
> +    .offset_bits = 5, .offset_shift = 3, .offset_addend = 1,
> +    .reg_bits = 3, .reg_addend = 8, .reg_type = 'd'
> +  },
> +  {
> +    .directive = ".seh_save_lrpair",
> +    .size = 2,
> +    .code_bits = 7, .code = 0b1101011U,
> +    .offset_bits = 6, .offset_shift = 3,
> +    .reg_bits = 3, .reg_shift = 1, .reg_addend = 19, .reg_type = 'x'
> +  },
> +  {
> +    .directive = ".seh_save_fplr",
> +    .size = 1,
> +    .code_bits = 2, .code = 0b01U,
> +    .offset_bits = 6, .offset_shift = 3
> +  },
> +  {
> +    .directive = ".seh_save_fplr_x",
> +    .size = 1,
> +    .code_bits = 2, .code = 0b10U,
> +    .offset_bits = 6, .offset_shift = 3, .offset_addend = 1
> +  },
> +  {
> +    .directive = ".seh_save_r19r20_x",
> +    .size = 1,
> +    .code_bits = 3, .code = 0b001U,
> +    .offset_bits = 5, .offset_shift = 3
> +  },
> +  {
> +    .directive = ".seh_add_fp",
> +    .size = 2,
> +    .code_bits = 8, .code = 0b11100010U,
> +    .offset_bits = 8, .offset_shift = 3
> +  },
> +  {
> +    .directive = ".seh_set_fp",
> +    .size = 1,
> +    .code_bits = 8, .code = 0b11100001U
> +  },
> +  {
> +    .directive = ".seh_save_next",
> +    .size = 1,
> +    .code_bits = 8, .code = 0b11100110U
> +  },
> +  {
> +    .directive = ".seh_nop",
> +    .size = 1,
> +    .code_bits = 8, .code = 0b11100011U
> +  },
> +  {
> +    .directive = ".seh_pac_sign_lr",
> +    .size = 1,
> +    .code_bits = 8, .code = 0b11111100U
> +  },
> +  {
> +    .size = 1,
> +    .code_bits = 8, .code = 0b11100100U
> +  },
> +};
> +
> +/* Set for current context the default handler.  */
> +static void
> +obj_coff_seh_handler (const int what ATTRIBUTE_UNUSED)
> +{
> +  char *symbol_name;
> +  char name_end;
> +
> +  if (!verify_context (".seh_handler"))
> +    return;
> +
> +  if (*input_line_pointer == 0 || *input_line_pointer == '\n')
> +    as_bad (_(".seh_handler requires a handler"));
> +
> +  SKIP_WHITESPACE ();
> +
> +  if (*input_line_pointer == '@')
> +    {
> +      name_end = get_symbol_name (&symbol_name);
> +
> +      seh_ctx_cur->handler.X_op = O_constant;
> +      seh_ctx_cur->handler.X_add_number = 0;
> +
> +      if (strcasecmp (symbol_name, "@1") == 0)
> +	seh_ctx_cur->handler.X_add_number = 1;
> +      else if (strcasecmp (symbol_name, "@0")
> +	       && strcasecmp (symbol_name, "@null"))
> +	as_bad (_("unknown constant value '%s' for handler"), symbol_name);
> +
> +      (void) restore_line_pointer (name_end);
> +    }
> +  else
> +    expression (&seh_ctx_cur->handler);
> +
> +  seh_ctx_cur->handler_data.X_op = O_constant;
> +  seh_ctx_cur->handler_data.X_add_number = 0;
> +  seh_ctx_cur->xdata_header.x = 1;
> +
> +  while (skip_whitespace_and_comma (0))
> +    {
> +      name_end = get_symbol_name (&symbol_name);
> +      (void) restore_line_pointer (name_end);
> +    }
> +}
> +
> +/* Switch to subsection for handler data for exception region.  */
> +static void
> +obj_coff_seh_handlerdata (const int what ATTRIBUTE_UNUSED)
> +{
> +  demand_empty_rest_of_line ();
> +
> +  switch_xdata (seh_ctx_cur->subsection + 1, seh_ctx_cur->code_seg);
> +  seh_ctx_cur->handler_data_xdata_addr = symbol_temp_new_now();
> +}
> +
> +/* Switch back to the code section.  */
> +static void
> +obj_coff_seh_code (int ignored ATTRIBUTE_UNUSED)
> +{
> +  subseg_set (seh_ctx_cur->code_seg, 0);
> +}
> +
> +/* Obtain available unwind element.  */
> +static void
> +seh_aarch64_add_unwind_element (const seh_aarch64_unwind_types unwind_type,
> +				unsigned offset, unsigned reg)
> +{
> +  const struct aarch64_unwind_info *info
> +    = aarch64_unwind_code_data + unwind_type;
> +  unsigned value_offset_bits = 0;
> +
> +  if ((seh_ctx_cur->unwind_codes_byte_count
> +      + info->size) > AARCH64_MAX_UNWIND_CODES_SIZE)
> +    as_bad (_("no unwind element available."));
> +
> +  unsigned value = 0;
> +
> +  if (info->offset_bits)
> +    {
> +      const unsigned divided_by = 1u << info->offset_shift;
> +      if (offset & (divided_by - 1))
> +	as_bad (_("offset should be divided by %u"), divided_by);
> +      offset = (offset >> info->offset_shift) - info->offset_addend;
> +      if (offset >= (1u << info->offset_bits))
> +	as_bad (_("offset overflows expected range"));
> +      value |= offset << value_offset_bits;
> +      value_offset_bits += info->offset_bits;
> +    }
> +
> +  if (info->reg_bits)
> +    {
> +      const unsigned regn_divided_by = 1u << info->reg_shift;
> +      reg -= info->reg_addend;
> +      if (reg & (regn_divided_by - 1))
> +	as_bad (_("unexpected register number"));
> +      reg >>= info->reg_shift;
> +      if (reg >= (1u << info->reg_bits))
> +	as_bad (_("unexpected register number"));
> +      value |= reg << value_offset_bits;
> +      value_offset_bits += info->reg_bits;
> +    }
> +
> +  const unsigned code = info->code;
> +  gas_assert (code < (1u << info->code_bits));
> +  value |= code << value_offset_bits;
> +
> +  seh_aarch64_unwind_code *element;
> +  element = seh_ctx_cur->unwind_codes + seh_ctx_cur->unwind_codes_count++;
> +  element->type = unwind_type;
> +  element->value = value;
> +
> +  seh_ctx_cur->unwind_codes_byte_count += info->size;
> +}
> +
> +/* Mark begin of new context.  */
> +static void
> +obj_coff_seh_proc (const int what ATTRIBUTE_UNUSED)
> +{
> +  char *symbol_name;
> +  char name_end;
> +
> +  if (in_seh_proc)
> +    as_bad (_("previous SEH entry not closed (missing .seh_endproc)"));
> +
> +  if (*input_line_pointer == 0 || *input_line_pointer == '\n')
> +    as_bad (_(".seh_proc requires function label name"));
> +
> +
> +  if (!seh_ctx_root)
> +  {
> +    seh_ctx_root = XCNEW (seh_context);
> +    seh_ctx_cur = seh_ctx_root;
> +  }
> +  else
> +  {
> +    seh_ctx_cur->next = XCNEW (seh_context);
> +    seh_ctx_cur = seh_ctx_cur->next;
> +  }
> +
> +  seh_ctx_cur->next = NULL;
> +  seh_ctx_cur->code_seg = now_seg;
> +
> +  /* The current implementation always use a pair of .pdata and .xdata
> +     records.  */
> +  const bool use_xdata = true;
> +
> +  if (use_xdata)
> +    {
> +      x_segcur = seh_hash_find_or_make (seh_ctx_cur->code_seg, ".xdata");
> +      seh_ctx_cur->subsection = x_segcur->subseg;
> +      x_segcur->subseg += 2;
> +
> +      /* Initialize an empty .xdata record.  */
> +      seh_ctx_cur->unwind_codes_count = 0;
> +      seh_ctx_cur->unwind_codes_byte_count = 0;
> +      seh_ctx_cur->epilogue_scopes_count = 0;
> +      seh_ctx_cur->epilogue_scopes_capacity = 0;
> +      seh_ctx_cur->epilogue_scopes = NULL;
> +      seh_ctx_cur->xdata_header.x = 0;
> +    }
> +
> +  SKIP_WHITESPACE ();
> +
> +  name_end = get_symbol_name (&symbol_name);
> +  seh_ctx_cur->func_name = xstrdup (symbol_name);
> +  (void) restore_line_pointer (name_end);
> +
> +  demand_empty_rest_of_line ();
> +
> +  seh_ctx_cur->start_addr = symbol_temp_new_now ();
> +  in_seh_proc = true;
> +}
> +
> +/* Mark end of prologue for current context.  */
> +static void
> +obj_coff_seh_endprologue (const int what ATTRIBUTE_UNUSED)
> +{
> +  if (!verify_context (".seh_endprologue")
> +      || !seh_validate_seg (".seh_endprologue"))
> +    return;
> +  demand_empty_rest_of_line ();
> +
> +  if (seh_ctx_cur->endprologue_addr != NULL)
> +    as_warn (_("duplicate .seh_endprologue in .seh_proc block"));
> +  else
> +    seh_ctx_cur->endprologue_addr = symbol_temp_new_now ();
> +
> +  /* Unwind codes need to be reversed.  */
> +  for (unsigned i = 0, n = seh_ctx_cur->unwind_codes_count; i < n / 2; ++i)
> +    {
> +      seh_aarch64_unwind_code *unwind_codes = seh_ctx_cur->unwind_codes;
> +      const seh_aarch64_unwind_code temp = unwind_codes[i];
> +      unwind_codes[i] = unwind_codes[n-i-1];
> +      unwind_codes[n-i-1] = temp;
> +    }
> +
> +   seh_aarch64_add_unwind_element (unwind_end, 0, 0);
> +}
> +
> +/* Mark end of current context.  */
> +static void
> +obj_coff_seh_endproc (const int what ATTRIBUTE_UNUSED)
> +{
> +  demand_empty_rest_of_line ();
> +  if (!in_seh_proc)
> +    {
> +      as_bad (_(".seh_endproc used without .seh_proc"));
> +      return;
> +    }
> +
> +  seh_validate_seg (".seh_endproc");
> +
> +  seh_ctx_cur->end_addr = symbol_temp_new_now ();
> +  in_seh_proc = false;
> +}
> +
> +static void
> +obj_coff_seh_startepilogue (const int what ATTRIBUTE_UNUSED)
> +{
> +  if (!verify_context (".seh_startepilogue")
> +      || !seh_validate_seg (".seh_startepilogue"))
> +    return;
> +  demand_empty_rest_of_line ();
> +
> +  if (seh_ctx_cur->epilogue_scopes_count >= AARCH64_MAX_EPILOGUE_SCOPES)
> +    as_bad (_("no epilogue scopes available."));
> +
> +  symbolS *epilogue_start_addr = symbol_temp_new_now ();
> +  expressionS exp;
> +  exp.X_op = O_subtract;
> +  exp.X_add_symbol = epilogue_start_addr;
> +  exp.X_op_symbol = seh_ctx_cur->start_addr;
> +  exp.X_add_number = 0;
> +
> +  if (!resolve_expression (&exp) || exp.X_op != O_constant
> +      || exp.X_add_number < 0)
> +    as_bad (_(".seh_startepilogue offset expression for %s "
> +	    "does not evaluate to a non-negative constant"),
> +	    S_GET_NAME (epilogue_start_addr));
> +
> +  if (seh_ctx_cur->epilogue_scopes_count
> +      >= seh_ctx_cur->epilogue_scopes_capacity)
> +    {
> +      const unsigned initial_capacity = 32;
> +      if (seh_ctx_cur->epilogue_scopes_capacity)
> +	seh_ctx_cur->epilogue_scopes_capacity *= 2;
> +      else
> +	seh_ctx_cur->epilogue_scopes_capacity = initial_capacity;
> +
> +      seh_ctx_cur->epilogue_scopes
> +	= XRESIZEVEC (seh_aarch64_epilogue_scope, seh_ctx_cur->epilogue_scopes,
> +		     seh_ctx_cur->epilogue_scopes_capacity);
> +    }
> +
> +  seh_aarch64_epilogue_scope *epilogue_scope = seh_ctx_cur->epilogue_scopes
> +    + seh_ctx_cur->epilogue_scopes_count;
> +  epilogue_scope->epilogue_start_offset = exp.X_add_number / 4;
> +  epilogue_scope->reserved = 0;
> +  epilogue_scope->epilogue_start_index = 0;
> +  seh_ctx_cur->epilogue_scopes_count++;
> +}
> +
> +static void
> +obj_coff_seh_endepilogue (const int what ATTRIBUTE_UNUSED)
> +{
> +  if (!verify_context (".seh_endepilogue")
> +      || !seh_validate_seg (".seh_endepilogue"))
> +    return;
> +
> +  demand_empty_rest_of_line ();
> +
> +  expressionS exp;
> +  symbolS *epilogue_end_addr = symbol_temp_new_now ();
> +  exp.X_op = O_subtract;
> +  exp.X_add_symbol = epilogue_end_addr;
> +  exp.X_op_symbol = seh_ctx_cur->start_addr;
> +  exp.X_add_number = 0;
> +
> +  if (!resolve_expression (&exp) || exp.X_op != O_constant
> +      || exp.X_add_number < 0)
> +    as_bad (_(".seh_endepilogue offset expression for %s "
> +	    "does not evaluate to a non-negative constant"),
> +	    S_GET_NAME (epilogue_end_addr));
> +
> +   seh_aarch64_epilogue_scope *epilogue_scope = seh_ctx_cur->epilogue_scopes
> +     + seh_ctx_cur->epilogue_scopes_count - 1;
> +
> +   epilogue_scope->epilogue_end_offset = exp.X_add_number;
> +
> +  /* End code.  */
> +  seh_aarch64_add_unwind_element (unwind_end, 0, 0);
> +}
> +
> +/* End-of-file hook.  */
> +static void
> +free_seh_ctx (struct seh_aarch64_context *seh_ctx)
> +{
> +  free (seh_ctx->func_name);
> +  const seh_aarch64_func_fragment *fragment = seh_ctx->func_fragment.next;
> +  while (fragment)
> +    {
> +      const seh_aarch64_func_fragment *next = fragment->next;
> +      XDELETE (fragment);
> +      fragment = next;
> +    }
> +  XDELETEVEC (seh_ctx->epilogue_scopes);
> +  free (seh_ctx);
> +}
> +
> +static void
> +obj_coff_seh_save_reg (const int type)
> +{
> +  gas_assert (type >= 0 && type <= unwind_last_type);
> +
> +  const struct aarch64_unwind_info *info
> +    = aarch64_unwind_code_data + type;
> +
> +  SKIP_WHITESPACE ();
> +
> +  char *symbol_name = NULL;
> +  unsigned reg = -1;
> +
> +  if (info->reg_bits)
> +    {
> +      char name_end = get_symbol_name (&symbol_name);
> +      if (info->reg_type != *symbol_name)
> +	as_bad ("unexpected register name");
> +
> +      reg = atoi (symbol_name + 1);
> +      (void) restore_line_pointer (name_end);
> +
> +      if (!skip_whitespace_and_comma (1))
> +	return;
> +
> +      const unsigned reg_max = info->reg_max ? info->reg_max: 30;
> +      if (reg > reg_max)
> +	as_bad (_("unexpected register number"));
> +    }
> +
> +  offsetT off = -1;
> +  if (info->offset_bits)
> +    {
> +      off = get_absolute_expression ();
> +
> +      if (off < 0)
> +	as_bad (_("offset is negative"));
> +    }
> +
> +  demand_empty_rest_of_line ();
> +
> +  if (!in_seh_proc)
> +  {
> +    as_bad (_("SEH entry has not been found (missing .seh_proc)"));
> +    return;
> +  }
> +
> +  if (!info->directive || !seh_validate_seg (info->directive))
> +    return;
> +
> +  seh_aarch64_add_unwind_element (type, off, reg);
> +}
> +
> +/* Add a stack-allocation token to current context.  */
> +static void
> +obj_coff_seh_stackalloc (const int what ATTRIBUTE_UNUSED)
> +{
> +  const offsetT off = get_absolute_expression ();
> +  demand_empty_rest_of_line ();
> +
> +  if (!in_seh_proc)
> +    {
> +      as_bad (_("SEH entry has not been found (missing .seh_proc)"));
> +      return;
> +    }
> +
> +  if (off < 0x200)
> +    seh_aarch64_add_unwind_element (unwind_alloc_s, off, 0);
> +  else if (off < 0x8000)
> +    seh_aarch64_add_unwind_element (unwind_alloc_m, off, 0);
> +  else if (off < 0x10000000)
> +    seh_aarch64_add_unwind_element (unwind_alloc_l, off, 0);
> +  else
> +    as_bad (_(".seh_stackalloc offset is out of range"));
> +}
> +
> +/* Data writing routines.  */
> +static void
> +seh_aarch64_emit_epilogue_scopes (const seh_context *seh_ctx,
> +				  const uint64_t fragment_offset,
> +				  const unsigned prologue_size,
> +				  const unsigned first_fragment_scope,
> +				  const unsigned last_fragment_scope,
> +				  const bool has_phantom_prologue)
> +{
> +  unsigned start_index_offset = 0;
> +  const seh_aarch64_epilogue_scope *scopes = seh_ctx->epilogue_scopes;
> +  if (first_fragment_scope < seh_ctx->epilogue_scopes_count)
> +    start_index_offset = scopes[first_fragment_scope].epilogue_start_index
> +			 - prologue_size;
> +  if (has_phantom_prologue)
> +    {
> +      if (start_index_offset == 0)
> +	as_bad (_("start index offset for the epilogue cannot be 0 when "
> +		"phantom prologue is used"));
> +      --start_index_offset;
> +    }
> +
> +  for (unsigned i = first_fragment_scope; i < last_fragment_scope; ++i)
> +    {
> +      seh_aarch64_epilogue_scope scope = seh_ctx->epilogue_scopes[i];
> +      scope.epilogue_start_offset_reduced = (scope.epilogue_start_offset
> +					    - fragment_offset) >> 2;
> +      scope.epilogue_start_index -= start_index_offset;
> +      uint32_t scope_code;
> +      memcpy (&scope_code, &scope, sizeof (scope_code));
> +      md_number_to_chars (frag_more (4), scope_code, 4);
> +    }
> +}
> +
> +static void
> +seh_aarch64_emit_unwind_codes (const seh_context *seh_ctx,
> +			       const unsigned prologue_size,
> +			       const unsigned first_epilogue_index,
> +			       const unsigned last_epilogue_index,
> +			       const bool has_phantom_prologue)
> +{
> +  unsigned total_byte_count = 0;
> +
> +  if (has_phantom_prologue)
> +    {
> +      ++total_byte_count;
> +      const unsigned endc_code = 0b11100101U;

Another binary literal.

> +      md_number_to_chars (frag_more (1), endc_code, 1);
> +    }
> +
> +  unsigned unwind_bytes_offset = 0;
> +  for (unsigned i = 0; i < seh_ctx->unwind_codes_count; ++i)
> +    {
> +      const seh_aarch64_unwind_code *code = seh_ctx->unwind_codes + i;
> +      const unsigned byte_count
> +	= aarch64_unwind_code_data[code->type].size;
> +      unwind_bytes_offset += byte_count;
> +
> +      if (unwind_bytes_offset > last_epilogue_index)
> +	break;
> +
> +      if (unwind_bytes_offset > prologue_size
> +	  && unwind_bytes_offset <= first_epilogue_index)
> +	continue;
> +
> +      /*  emit unwind code bytes in big endian.  */
> +      number_to_chars_bigendian (frag_more (byte_count), code->value,
> +				 byte_count);
> +      total_byte_count += byte_count;
> +    }
> +
> +    /* Handle word alignment.  */
> +    const unsigned required_padding = (-total_byte_count) % 4;
> +    if (required_padding)
> +      {
> +	/* Use the nop unwind code for alignment.  */
> +	const uint32_t nop_chain = 0xe3e3e3e3;
> +
> +	md_number_to_chars (frag_more (required_padding), nop_chain,
> +			    required_padding);
> +      }
> +}
> +
> +static void
> +seh_aarch64_emit_xdata_record(struct seh_aarch64_context *seh_ctx,

nit: space before parenthesis.

> +			      const uintptr_t frag_size,
> +			      const uintptr_t fragment_offset,
> +			      const unsigned header_size,
> +			      const unsigned prologue_size,
> +			      const unsigned prologue_insn_count,
> +			      const bool has_phantom_prologue,
> +			      const unsigned first_fragment_scope,
> +			      const unsigned last_fragment_scope,
> +			      const unsigned first_epilogue_index,
> +			      const unsigned last_epilogue_index)
> +{
> +  const seh_aarch64_xdata_header *header = &seh_ctx->xdata_header;
> +  md_number_to_chars (frag_more (header_size), seh_ctx->xdata_header_value,
> +		      header_size);
> +
> +  if (header->ext_epilogue_count && !header->e)
> +    {
> +      seh_aarch64_emit_epilogue_scopes (seh_ctx,
> +					fragment_offset, prologue_size,
> +					first_fragment_scope,
> +					last_fragment_scope,
> +					has_phantom_prologue);
> +      if (has_phantom_prologue)
> +	{
> +	  const uint32_t epilogue_start_index_encoded = 1 << 22;
> +	  const uint32_t epilogue_start_offset_encoded
> +	    = (frag_size - prologue_insn_count * 4) >> 2;
> +	  md_number_to_chars (frag_more (4),
> +			      epilogue_start_index_encoded
> +			      | epilogue_start_offset_encoded, 4);
> +	}
> +    }
> +
> +  if (header->ext_code_words)
> +    seh_aarch64_emit_unwind_codes (seh_ctx, prologue_size, first_epilogue_index,
> +				   last_epilogue_index, has_phantom_prologue);
> +
> +  if (header->x == 1)
> +    {
> +      if (seh_ctx->handler.X_op == O_symbol)
> +	seh_ctx->handler.X_op = O_symbol_rva;
> +
> +      emit_expr (&seh_ctx->handler, 4);
> +
> +      /* Emit the fragment offset.  */
> +      md_number_to_chars (frag_more (4), fragment_offset, 4);
> +
> +      /* Use the same SEH handler data for all fragments.
> +	 The SEH handler data is emitted after the last fragment.  */
> +      expressionS exp;
> +      memset (&exp, 0, sizeof (expressionS));
> +      exp.X_op = O_symbol_rva;
> +      exp.X_add_symbol = seh_ctx->handler_data_xdata_addr;
> +      emit_expr (&exp, 4);
> +    }
> +}
> +
> +static bool
> +seh_function_size (const struct seh_aarch64_context *seh_ctx,
> +		  uintptr_t *size)
> +{
> +  fragS *start_frag, *end_frag;
> +  addressT start_offset, end_offset;
> +  start_frag = symbol_get_frag_and_value (seh_ctx->start_addr, &start_offset);
> +  end_frag = symbol_get_frag_and_value (seh_ctx->end_addr, &end_offset);
> +
> +  intptr_t func_size = end_frag->fr_address + end_offset
> +		       - start_frag->fr_address - start_offset;
> +  if (func_size < 0)
> +    return false;
> +
> +  *size = func_size;
> +  return true;
> +}
> +
> +/* Write out the xdata information for one function.  */
> +static void
> +seh_aarch64_write_function_xdata (struct seh_aarch64_context *seh_ctx)
> +{
> +  if (!seh_ctx->unwind_codes_byte_count)
> +    return;
> +
> +  const segT save_seg = now_seg;
> +  const subsegT save_subseg = now_subseg;
> +
> +  switch_xdata (seh_ctx->subsection, seh_ctx->code_seg);
> +
> +  /* Set 4-byte alignment.  */
> +  frag_align (2, 0, 0);
> +
> +  uintptr_t func_size = 0;
> +  if (!seh_function_size (seh_ctx, &func_size))
> +    {
> +      as_bad (_("the function size for %s has not been evaluated"),
> +	      seh_ctx->func_name);
> +      return;
> +    }
> +
> +  /* The large functions should be split into fragments smaller than 1MB with
> +     4 bytes alignment.
> +     https://learn.microsoft.com/en-us/cpp/build/arm64-exception-handling?view=msvc-170#large-functions.  */
> +  const unsigned max_frag_size = (1 << 20) - 4;
> +  const bool is_fragmented_function = func_size > max_frag_size;
> +
> +  unsigned prologue_insn_count = 0;
> +  for (unsigned i = 0; i < seh_ctx->unwind_codes_count; ++i)
> +    {
> +      if (seh_ctx->unwind_codes[i].type == unwind_end)
> +	{
> +	  prologue_insn_count = i + 1;
> +	  break;
> +	}
> +    }
> +
> +  unsigned prologue_size = seh_ctx->unwind_codes_byte_count;
> +
> +  seh_aarch64_func_fragment *fragment;
> +  fragment = &seh_ctx->func_fragment;
> +  uintptr_t fragment_offset = 0;
> +  unsigned first_fragment_scope = 0;
> +  unsigned last_fragment_scope = 0;
> +
> +  /* Large functions (>= 1MB) will be split into multiple fragments.
> +     However, it is expected the most of the functions will have only one
> +     fragment. This loop iterates fragments and emit them.  */
> +  while (true)
> +    {
> +      fragment->xdata_addr = symbol_temp_new_now ();
> +      fragment->offset = fragment_offset;
> +      fragment->next = NULL;
> +
> +      /* Calculate current fragment size.  */
> +      uintptr_t frag_size = func_size - fragment_offset;
> +      if (frag_size > max_frag_size)
> +	frag_size = max_frag_size;
> +
> +      const bool is_last_frag = (fragment_offset + frag_size) == func_size;
> +
> +      /* If it is a fragmented function, the epilogue range should be calculated
> +	 and will be emitted for the current fragment, otherwise all epilogues
> +	 will be emitted.  */
> +      if (!is_fragmented_function)
> +	last_fragment_scope = seh_ctx->epilogue_scopes_count;
> +      else
> +	{
> +	  first_fragment_scope = last_fragment_scope;
> +	  for (unsigned i = first_fragment_scope;
> +	       i < seh_ctx->epilogue_scopes_count; ++i)
> +	    {
> +	      const seh_aarch64_epilogue_scope *scope
> +		= seh_ctx->epilogue_scopes;
> +	      scope += i;
> +	      if (scope->epilogue_start_offset >= (fragment_offset + frag_size))
> +		break;
> +
> +	      if (scope->epilogue_end_offset >= (fragment_offset + frag_size))
> +		{
> +		  frag_size = scope->epilogue_start_offset - fragment_offset;
> +		  break;
> +		}
> +
> +	      if (scope->epilogue_start_offset >= fragment_offset)
> +		last_fragment_scope = i + 1;
> +	    }
> +	}
> +
> +      seh_aarch64_xdata_header *header = &seh_ctx->xdata_header;
> +      const seh_aarch64_epilogue_scope *scopes = seh_ctx->epilogue_scopes;
> +
> +      /* Initialize the .xdata record.  */
> +      const uint32_t func_length_encoded = frag_size >> 2;
> +      header->func_length = func_length_encoded;
> +      header->vers = 0;
> +      header->e = 0;
> +      header->code_words = 0;
> +      header->epilogue_count = 0;
> +
> +      header->ext_code_words = 0;
> +      header->ext_epilogue_count = last_fragment_scope
> +				   - first_fragment_scope;
> +      header->reserved = 0;
> +
> +      /* Calculate epilogue indexes for the current fragment.  */
> +      unsigned first_epilogue_index = 0;
> +      unsigned last_epilogue_index = 0;
> +      if (!header->ext_epilogue_count)
> +	{
> +	  first_epilogue_index = prologue_size;
> +	  last_epilogue_index = prologue_size;
> +	}
> +      else
> +	{
> +	  const seh_aarch64_epilogue_scope *scope;
> +	  scope = scopes + first_fragment_scope;
> +	  first_epilogue_index = scope->epilogue_start_index;
> +	  last_epilogue_index = seh_ctx->unwind_codes_byte_count;
> +	}
> +
> +      /* Calculate how many unwind bytes will be emitted in .xdata record.  */
> +      unsigned unwind_bytes = prologue_size;
> +
> +      /* Check if current fragment has a phantom prologue. If yes, then
> +	 the unwinding size should be adjusted.  */
> +      const bool has_phantom_prologue = is_fragmented_function && is_last_frag;
> +      if (has_phantom_prologue && unwind_bytes)
> +	{
> +	  /* One more epilogue scope and unwind code are emitted with phantom
> +	     prologue.  */
> +	  unwind_bytes += 1;
> +	  ++header->ext_epilogue_count;
> +	}
> +
> +      /* Calculate the number of code words with 4-byte alignment.  */
> +      header->ext_code_words = (unwind_bytes + 3) / 4;
> +
> +      /* Check if short or extended header for a .xdata record should be
> +	 used.  */
> +      unsigned header_size = 8;
> +      if ((header->ext_code_words != 0 || header->ext_epilogue_count != 0)
> +	  && header->ext_code_words < 32
> +	  && header->ext_epilogue_count < 32)
> +	{
> +	  header_size = 4;
> +	  header->code_words = header->ext_code_words;
> +	  header->epilogue_count = header->ext_epilogue_count;
> +	  if (header->epilogue_count == 1)
> +	    {
> +	      header->e = 1;
> +	      if (has_phantom_prologue)
> +		header->ext_epilogue_count = 0;
> +	      else
> +		{
> +		  const seh_aarch64_epilogue_scope *scope;
> +		  scope = scopes + first_fragment_scope;
> +		  header->ext_epilogue_count = scope->epilogue_start_index;
> +		}
> +	    }
> +	}
> +
> +      /* Emit a .xdata record for the current fragment.  */
> +      seh_aarch64_emit_xdata_record(seh_ctx, frag_size, fragment_offset,
> +				    header_size,
> +				    prologue_size, prologue_insn_count,
> +				    has_phantom_prologue,
> +				    first_fragment_scope, last_fragment_scope,
> +				    first_epilogue_index, last_epilogue_index);
> +
> +      fragment_offset += frag_size;
> +      /* Exit the loop if it is the latest fragment.  */
> +      if (is_last_frag)
> +	break;
> +
> +      /* Allocate a new fragment that will be used also for emitting a .pdata
> +	 record.  */
> +      fragment->next = XCNEW (seh_aarch64_func_fragment);
> +      fragment = fragment->next;
> +    }
> +
> +  subseg_set (save_seg, save_subseg);
> +}
> +
> +/* Write out pdata for one function.  */
> +static void
> +seh_aarch64_write_function_pdata (const seh_context *seh_ctx)
> +{
> +  expressionS exp;
> +  const segT save_seg = now_seg;
> +  const subsegT save_subseg = now_subseg;
> +  memset (&exp, 0, sizeof (expressionS));
> +  switch_pdata (seh_ctx->code_seg);
> +
> +  if (seh_ctx->unwind_codes_byte_count)
> +    {
> +      const seh_aarch64_func_fragment *fragment = &seh_ctx->func_fragment;
> +      while (fragment)
> +	{
> +	  exp.X_op = O_symbol_rva;
> +	  exp.X_add_number = fragment->offset;
> +	  exp.X_add_symbol = seh_ctx->start_addr;
> +	  emit_expr (&exp, 4);
> +
> +	  exp.X_op = O_symbol_rva;
> +	  /* TODO: Implementing packed unwind data.  */
> +	  exp.X_add_number = 0;
> +	  exp.X_add_symbol = fragment->xdata_addr;
> +	  emit_expr (&exp, 4);
> +	  fragment = fragment->next;
> +	}
> +    }
> +
> +  subseg_set (save_seg, save_subseg);
> +}
> +
> +void
> +seh_aarch64_write_data (void)
> +{
> +  if (in_seh_proc)
> +  {
> +    as_bad (_("open SEH entry at end of file (missing .seh_endproc)"));
> +    return;
> +  }
> +
> +  if (!seh_ctx_root)
> +    return;
> +
> +  struct seh_aarch64_context *seh_ctx = seh_ctx_root;
> +  seh_ctx_root = NULL;
> +
> +  /* Relax the segment to be able to calculate the function sizes.  */
> +  subsegs_finish_section (seh_ctx->code_seg);
> +  const segment_info_type *seginfo = seg_info (seh_ctx->code_seg);
> +  relax_segment (seginfo->frchainP->frch_root, seh_ctx->code_seg, 0);
> +
> +  while (seh_ctx)
> +  {
> +    seh_aarch64_write_function_xdata (seh_ctx);
> +    seh_aarch64_write_function_pdata (seh_ctx);
> +    struct seh_aarch64_context *next = seh_ctx->next;
> +    free_seh_ctx (seh_ctx);
> +    seh_ctx = next;
> +  }
> +}
> +
> +void
> +obj_coff_seh_do_final (void)
> +{
> +}
> diff --git a/gas/config/obj-coff-seh-aarch64.h b/gas/config/obj-coff-seh-aarch64.h
> new file mode 100644
> index 00000000000..226e40c2312
> --- /dev/null
> +++ b/gas/config/obj-coff-seh-aarch64.h
> @@ -0,0 +1,251 @@
> +/* SEH .pdata/.xdata COFF object file format on AArch64
> +   Copyright (C) 2026 Free Software Foundation, Inc.
> +
> +   This file is part of GAS.
> +
> +   GAS is free software; you can redistribute it and/or modify
> +   it under the terms of the GNU General Public License as published by
> +   the Free Software Foundation; either version 3, or (at your option)
> +   any later version.
> +
> +   GAS is distributed in the hope that it will be useful,
> +   but WITHOUT ANY WARRANTY; without even the implied warranty of
> +   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> +   GNU General Public License for more details.
> +
> +   You should have received a copy of the GNU General Public License
> +   along with GAS; see the file COPYING.  If not, write to the Free
> +   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
> +   02110-1301, USA.  */
> +
> +/* SEH COFF AArch64 implementation partially intersects with the x64
> +   version, however it has a different extension to the unwind codes.
> +   It emits SEH data to pdata and xdata sections.  In some cases SEH
> +   data could be emitted to a packed record in the pdata section
> +   without the need for data in the xdata section.  However, the packed
> +   pdata record is not implemented yet.
> +
> +   The current implementation does not include:
> +   - Packed .pdata record.
> +   - Support for AdvSIMD and SVE.
> +   - Epilogue start index different than 0.  */
> +
> +#ifndef OBJ_COFF_SEH_AARCH64_H
> +#define OBJ_COFF_SEH_AARCH64_H
> +
> +/* Unwind codes for AArch64 are described at
> +   https://learn.microsoft.com/en-us/cpp/build/arm64-exception-handling?view=msvc-170#unwind-codes.  */
> +
> +typedef enum seh_aarch64_unwind_types
> +{
> +  unwind_alloc_s,
> +  unwind_alloc_m,
> +  unwind_alloc_l,
> +  unwind_save_reg,
> +  unwind_save_reg_x,
> +  unwind_save_regp,
> +  unwind_save_regp_x,
> +  unwind_save_fregp,
> +  unwind_save_fregp_x,
> +  unwind_save_freg,
> +  unwind_save_freg_x,
> +  unwind_save_lrpair,
> +  unwind_save_fplr,
> +  unwind_save_fplr_x,
> +  unwind_save_r19r20_x,
> +  unwind_add_fp,
> +  unwind_set_fp,
> +  unwind_save_next,
> +  unwind_nop,
> +  unwind_pac_sign_lr,
> +  unwind_end,
> +  unwind_end_c,
> +  unwind_last_type = unwind_end_c
> +} seh_aarch64_unwind_types;
> +
> +#define SEH_CMDS						      \
> +  /* Start a function that contains SEH.  */			      \
> +  {"seh_proc", obj_coff_seh_proc, 0},				      \
> +								      \
> +  /* End a function that contains SEH.  */			      \
> +  {"seh_endproc", obj_coff_seh_endproc, 0},			      \
> +								      \
> +  /* End a SEH prologue with unwinding codes.  */			      \
> +  {"seh_endprologue", obj_coff_seh_endprologue, 0},		      \
> +								      \
> +  /* Allocate stack.  */					      \
> +  {"seh_stackalloc", obj_coff_seh_stackalloc, 0},		      \
> +								      \
> +  /* Set a SEH handler.  */					      \
> +  {"seh_handler", obj_coff_seh_handler, 0},			      \
> +								      \
> +  /* Set a SEH handler data.  */				      \
> +  {"seh_handlerdata", obj_coff_seh_handlerdata, 0},		      \
> +								      \
> +  /* Switch back to the code section.  */			      \
> +  {"seh_code", obj_coff_seh_code, 0},				      \
> +								      \
> +  /* Start a SEH epilogue.  */					      \
> +  {"seh_startepilogue", obj_coff_seh_startepilogue, 0},		      \
> +								      \
> +  /* End a SEH epilogue.  */					      \
> +  {"seh_endepilogue", obj_coff_seh_endepilogue, 0},		      \
> +								      \
> +  /* Save an 'x' register.  */					      \
> +  {"seh_save_reg", obj_coff_seh_save_reg, unwind_save_reg},	      \
> +								      \
> +  /* Save an 'x' register with a pre-indexed offset.  */	      \
> +  {"seh_save_reg_x", obj_coff_seh_save_reg, unwind_save_reg_x},	      \
> +								      \
> +  /* Save an 'x' register pair.  */				      \
> +  {"seh_save_regp", obj_coff_seh_save_reg, unwind_save_regp},	      \
> +								      \
> +  /* Save an 'x' register pair with a pre-indexed offset.  */	      \
> +  {"seh_save_regp_x", obj_coff_seh_save_reg, unwind_save_regp_x},     \
> +								      \
> +  /* Save an 'x' register and lr.  */				      \
> +  {"seh_save_lrpair", obj_coff_seh_save_reg, unwind_save_lrpair},     \
> +								      \
> +  /* Save a 'd' register pair.  */				      \
> +  {"seh_save_fregp", obj_coff_seh_save_reg, unwind_save_fregp},	      \
> +								      \
> +  /* Save a 'd' register pair with a pre-indexed offset.  */	      \
> +  {"seh_save_fregp_x", obj_coff_seh_save_reg, unwind_save_fregp_x},   \
> +								      \
> +  /* Save a 'd' register.  */					      \
> +  {"seh_save_freg", obj_coff_seh_save_reg, unwind_save_freg},	      \
> +								      \
> +  /* Save a 'd' register with a pre-indexed offset.  */		      \
> +  {"seh_save_freg_x", obj_coff_seh_save_reg, unwind_save_freg_x},     \
> +								      \
> +  /* Save fp and lr registers.  */				      \
> +  {"seh_save_fplr", obj_coff_seh_save_reg, unwind_save_fplr},	      \
> +								      \
> +  /* Save fp and lr registers with a pre-indexed offset.  */	      \
> +  {"seh_save_fplr_x", obj_coff_seh_save_reg, unwind_save_fplr_x},     \
> +								      \
> +  /* Save x19 and x20 registers with a pre-indexed offset.  */	      \
> +  {"seh_save_r19r20_x", obj_coff_seh_save_reg, unwind_save_r19r20_x}, \
> +								      \
> +  /* Set fp by sp + offset.  */					      \
> +  {"seh_add_fp", obj_coff_seh_save_reg, unwind_add_fp},		      \
> +								      \
> +  /* Unwind operation is not required.  */			      \
> +  {"seh_nop", obj_coff_seh_save_reg, unwind_nop},		      \
> +								      \
> +  /* Sign the return address in lr with pacibsp.  */		      \
> +  {"seh_pac_sign_lr", obj_coff_seh_save_reg, unwind_pac_sign_lr},     \
> +								      \
> +  /* Set fp by sp.  */						      \
> +  {"seh_set_fp", obj_coff_seh_save_reg, unwind_set_fp},		      \
> +								      \
> +  /* Save next register pair.  */				      \
> +  {"seh_save_next", obj_coff_seh_save_reg, unwind_save_next},
> +
> +/* AArch64 exceptions handling and unwinding structures.
> +   https://learn.microsoft.com/en-us/cpp/build/arm64-exception-handling#pdata-records.  */
> +
> +typedef struct seh_aarch64_unwind_code
> +{
> +  unsigned value;
> +  seh_aarch64_unwind_types type;
> +} seh_aarch64_unwind_code;
> +
> +typedef struct seh_aarch64_packed_unwind_data
> +{
> +  uint32_t flag : 2;
> +  uint32_t func_length : 11;
> +  uint32_t frame_size : 9;
> +  uint32_t cr : 2;
> +  uint32_t h : 1;
> +  uint32_t regI : 4;
> +  uint32_t regF : 3;
> +} seh_aarch64_packed_unwind_data;
> +
> +typedef struct seh_aarch64_except_info
> +{
> +  uint32_t flag : 2;
> +  uint32_t except_info_rva : 30;
> +} seh_aarch64_except_info;
> +
> +typedef union seh_aarch64_unwind_info
> +{
> +  seh_aarch64_except_info except_info;
> +  seh_aarch64_packed_unwind_data packed_unwind_data;
> +} seh_aarch64_unwind_info;
> +
> +typedef struct seh_aarch64_xdata_header
> +{
> +  uint32_t func_length : 18;
> +  uint32_t vers : 2;
> +  uint32_t x : 1;
> +  uint32_t e : 1;
> +  uint32_t epilogue_count : 5;
> +  uint32_t code_words : 5;
> +  uint32_t ext_epilogue_count : 16;
> +  uint32_t ext_code_words : 8;
> +  uint32_t reserved : 8;
> +} seh_aarch64_xdata_header;
> +
> +typedef struct seh_aarch64_epilogue_scope
> +{
> +  uint32_t epilogue_start_offset_reduced : 18;
> +  uint32_t reserved : 4;
> +  uint32_t epilogue_start_index : 10;
> +  bfd_vma epilogue_start_offset;
> +  bfd_vma epilogue_end_offset;
> +} seh_aarch64_epilogue_scope;
> +
> +typedef struct seh_aarch64_func_fragment
> +{
> +  bfd_vma offset;
> +  symbolS *xdata_addr;
> +  struct seh_aarch64_func_fragment *next;
> +} seh_aarch64_func_fragment;
> +
> +/* AARCH64_MAX_UNWIND_CODES is limited by
> +   seh_aarch64_xdata_header::ext_code_words.  */
> +#define AARCH64_MAX_UNWIND_CODES (255 * 4)
> +#define AARCH64_MAX_UNWIND_CODES_SIZE (255 * 4)
> +/* AARCH64_MAX_EPILOGUE_SCOPES is limited by
> +   seh_aarch64_xdata_header::ext_epilogue_count.  */
> +#define AARCH64_MAX_EPILOGUE_SCOPES 65535
> +
> +typedef struct seh_aarch64_context
> +{
> +  struct seh_aarch64_context *next;
> +
> +  /* Initial code-segment.  */
> +  segT code_seg;
> +  /* Function name.  */
> +  char *func_name;
> +  /* BeginAddress.  */
> +  symbolS *start_addr;
> +  /* EndAddress.  */
> +  symbolS *end_addr;
> +  /* PrologueEnd.  */
> +  symbolS *endprologue_addr;
> +
> +  symbolS *handler_data_xdata_addr;
> +  /* ExceptionHandler.  */
> +  expressionS handler;
> +  /* ExceptionHandlerData.  */
> +  expressionS handler_data;
> +
> +  subsegT subsection;
> +
> +  union {
> +    seh_aarch64_xdata_header xdata_header;
> +    valueT xdata_header_value;
> +  };
> +  unsigned unwind_codes_count;
> +  unsigned unwind_codes_byte_count;
> +  seh_aarch64_unwind_code unwind_codes[AARCH64_MAX_UNWIND_CODES];
> +  unsigned epilogue_scopes_count;
> +  unsigned epilogue_scopes_capacity;
> +  seh_aarch64_epilogue_scope *epilogue_scopes;
> +  /* The function fragments.  */
> +  seh_aarch64_func_fragment func_fragment;
> +} seh_context;
> +
> +#endif /* OBJ_COFF_SEH_AARCH64_H.  */
> diff --git a/gas/config/obj-coff-seh-shared.c b/gas/config/obj-coff-seh-shared.c
> index 717a7d345ef..b99a6bb67ee 100644
> --- a/gas/config/obj-coff-seh-shared.c
> +++ b/gas/config/obj-coff-seh-shared.c
> @@ -19,7 +19,13 @@
>     Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
>     02110-1301, USA.  */
>  
> +#if defined (COFFAARCH64)
> +#include "obj-coff-seh-aarch64.h"
> +typedef struct seh_aarch64_context seh_context_t;
> +#else
>  #include "obj-coff-seh.h"
> +typedef struct seh_context seh_context_t;
> +#endif
>  
>  /* Private segment collection list.  */
>  struct seh_seg_list {
> @@ -28,7 +34,7 @@ struct seh_seg_list {
>    char *seg_name;
>  };
>  
> -static struct seh_context *seh_ctx_cur = NULL;
> +static seh_context_t *seh_ctx_cur = NULL;
>  
>  static htab_t seh_hash;
>  
> diff --git a/gas/config/obj-coff.c b/gas/config/obj-coff.c
> index 7732c0af911..b08295019d8 100644
> --- a/gas/config/obj-coff.c
> +++ b/gas/config/obj-coff.c
> @@ -55,7 +55,11 @@ static const char weak_altprefix[] = ".weak.";
>  #endif /* TE_PE */
>  
>  #include "obj-coff-seh-shared.c"
> +#if defined (COFFAARCH64)
> +#include "obj-coff-seh-aarch64.c"
> +#else
>  #include "obj-coff-seh.c"
> +#endif
>  
>  typedef struct
>    {
> diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
> index fb58bcca9b1..c672f284a48 100644
> --- a/gas/config/tc-aarch64.c
> +++ b/gas/config/tc-aarch64.c
> @@ -10459,6 +10459,16 @@ aarch64_cleanup (void)
>      }
>  }
>  
> +#if defined (OBJ_COFF)
> +/* Called after all assembly has been done.  */
> +
> +void
> +aarch64_md_finish (void)
> +{
> +  seh_aarch64_write_data();
> +}
> +#endif /* OBJ_COFF.  */
> +
>  #ifdef OBJ_ELF
>  /* Remove any excess mapping symbols generated for alignment frags in
>     SEC.  We may have created a mapping symbol before a zero byte
> diff --git a/gas/config/tc-aarch64.h b/gas/config/tc-aarch64.h
> index d1fb4c9058b..6446ac8efb8 100644
> --- a/gas/config/tc-aarch64.h
> +++ b/gas/config/tc-aarch64.h
> @@ -82,6 +82,12 @@ struct aarch64_fix
>  
>  #define tc_frob_section(S) aarch64_frob_section (S)
>  
> +#if defined (OBJ_COFF)
> +#define md_finish aarch64_md_finish
> +extern void aarch64_md_finish (void);
> +extern void seh_aarch64_write_data (void);
> +#endif
> +
>  /* The key used to sign a function's return address.  */
>  enum pointer_auth_key {
>    AARCH64_PAUTH_KEY_A,
> diff --git a/gas/testsuite/gas/pe/pe.exp b/gas/testsuite/gas/pe/pe.exp
> index e25de3cfa9d..cc7701587ac 100644
> --- a/gas/testsuite/gas/pe/pe.exp
> +++ b/gas/testsuite/gas/pe/pe.exp
> @@ -63,6 +63,9 @@ if ([istarget "x86_64-*-mingw*"]) then {
>  # This test is only for AArch64
>  if {[istarget "aarch64-*-pe*"] || [istarget "aarch64-*-mingw*"]} {
>  	run_dump_test "pe-aarch64"
> +	run_dump_test "seh-aarch64"
> +	run_dump_test "seh-aarch64-large-func"
> +	run_list_test "seh-aarch64-error" ""
>  }
>  
>  # Big obj
> diff --git a/gas/testsuite/gas/pe/seh-aarch64-error.l b/gas/testsuite/gas/pe/seh-aarch64-error.l
> new file mode 100644
> index 00000000000..2d7f2c055f6
> --- /dev/null
> +++ b/gas/testsuite/gas/pe/seh-aarch64-error.l
> @@ -0,0 +1,110 @@
> +.*: Assembler messages:
> +.*:2: Error: .seh_endprologue used outside of .seh_proc block
> +.*:3: Error: SEH entry has not been found \(missing .seh_proc\)
> +.*:4: Error: SEH entry has not been found \(missing .seh_proc\)
> +.*:5: Error: SEH entry has not been found \(missing .seh_proc\)
> +.*:6: Error: SEH entry has not been found \(missing .seh_proc\)
> +.*:7: Error: SEH entry has not been found \(missing .seh_proc\)
> +.*:8: Error: SEH entry has not been found \(missing .seh_proc\)
> +.*:9: Error: SEH entry has not been found \(missing .seh_proc\)
> +.*:10: Error: SEH entry has not been found \(missing .seh_proc\)
> +.*:11: Error: SEH entry has not been found \(missing .seh_proc\)
> +.*:12: Error: SEH entry has not been found \(missing .seh_proc\)
> +.*:13: Error: SEH entry has not been found \(missing .seh_proc\)
> +.*:14: Error: SEH entry has not been found \(missing .seh_proc\)
> +.*:15: Error: SEH entry has not been found \(missing .seh_proc\)
> +.*:16: Error: SEH entry has not been found \(missing .seh_proc\)
> +.*:17: Error: SEH entry has not been found \(missing .seh_proc\)
> +.*:18: Error: SEH entry has not been found \(missing .seh_proc\)
> +.*:19: Error: SEH entry has not been found \(missing .seh_proc\)
> +.*:20: Error: SEH entry has not been found \(missing .seh_proc\)
> +.*:21: Error: .seh_endproc used without .seh_proc
> +.*:23: Error: .seh_proc requires function label name
> +.*:24: Error: previous SEH entry not closed \(missing .seh_endproc\)
> +.*:29: Error: offset overflows expected range
> +.*:30: Error: offset should be divided by 16
> +.*:31: Error: .seh_stackalloc offset is out of range
> +.*:33: Error: unexpected register number
> +.*:34: Error: unexpected register number
> +.*:35: Error: unexpected register name
> +.*:36: Error: offset is negative
> +.*:36: Error: offset overflows expected range
> +.*:38: Error: offset should be divided by 8
> +.*:39: Error: offset overflows expected range
> +.*:41: Error: unexpected register number
> +.*:42: Error: unexpected register number
> +.*:43: Error: unexpected register name
> +.*:44: Error: offset is negative
> +.*:44: Error: offset overflows expected range
> +.*:46: Error: offset should be divided by 8
> +.*:47: Error: offset overflows expected range
> +.*:49: Error: unexpected register number
> +.*:50: Error: unexpected register number
> +.*:51: Error: unexpected register name
> +.*:52: Error: unexpected register number
> +.*:53: Error: offset is negative
> +.*:53: Error: offset overflows expected range
> +.*:55: Error: offset should be divided by 8
> +.*:56: Error: offset overflows expected range
> +.*:58: Error: unexpected register number
> +.*:59: Error: unexpected register number
> +.*:60: Error: unexpected register name
> +.*:61: Error: unexpected register number
> +.*:62: Error: offset is negative
> +.*:62: Error: offset overflows expected range
> +.*:64: Error: offset should be divided by 8
> +.*:65: Error: offset overflows expected range
> +.*:67: Error: unexpected register number
> +.*:67: Error: unexpected register number
> +.*:68: Error: unexpected register number
> +.*:69: Error: unexpected register name
> +.*:70: Error: unexpected register number
> +.*:71: Error: offset is negative
> +.*:71: Error: offset overflows expected range
> +.*:73: Error: offset should be divided by 8
> +.*:74: Error: offset overflows expected range
> +.*:76: Error: unexpected register number
> +.*:77: Error: unexpected register number
> +.*:78: Error: unexpected register name
> +.*:79: Error: offset is negative
> +.*:79: Error: offset overflows expected range
> +.*:81: Error: offset should be divided by 8
> +.*:82: Error: offset overflows expected range
> +.*:84: Error: unexpected register number
> +.*:85: Error: unexpected register number
> +.*:86: Error: unexpected register name
> +.*:87: Error: offset is negative
> +.*:87: Error: offset overflows expected range
> +.*:89: Error: offset should be divided by 8
> +.*:90: Error: offset overflows expected range
> +.*:92: Error: unexpected register number
> +.*:93: Error: unexpected register number
> +.*:94: Error: unexpected register name
> +.*:95: Error: offset is negative
> +.*:95: Error: offset overflows expected range
> +.*:97: Error: offset should be divided by 8
> +.*:98: Error: offset overflows expected range
> +.*:100: Error: unexpected register number
> +.*:101: Error: unexpected register number
> +.*:102: Error: unexpected register name
> +.*:103: Error: offset is negative
> +.*:103: Error: offset overflows expected range
> +.*:105: Error: offset should be divided by 8
> +.*:106: Error: offset overflows expected range
> +.*:108: Error: offset is negative
> +.*:108: Error: offset overflows expected range
> +.*:110: Error: offset should be divided by 8
> +.*:111: Error: offset overflows expected range
> +.*:113: Error: offset is negative
> +.*:113: Error: offset overflows expected range
> +.*:115: Error: offset should be divided by 8
> +.*:116: Error: offset overflows expected range
> +.*:118: Error: offset is negative
> +.*:118: Error: offset overflows expected range
> +.*:120: Error: offset should be divided by 8
> +.*:121: Error: offset overflows expected range
> +.*:123: Error: offset is negative
> +.*:123: Error: offset overflows expected range
> +.*:125: Error: offset should be divided by 8
> +.*:126: Error: offset overflows expected range
> +.*: Error: open SEH entry at end of file \(missing .seh_endproc\)
> diff --git a/gas/testsuite/gas/pe/seh-aarch64-error.s b/gas/testsuite/gas/pe/seh-aarch64-error.s
> new file mode 100644
> index 00000000000..dc4118b7390
> --- /dev/null
> +++ b/gas/testsuite/gas/pe/seh-aarch64-error.s
> @@ -0,0 +1,128 @@
> +	.text
> +	.seh_endprologue
> +	.seh_stackalloc 16
> +	.seh_save_reg x19, 0
> +	.seh_save_reg_x x19, 16
> +	.seh_save_regp x19, 32
> +	.seh_save_regp_x x19, 48
> +	.seh_save_lrpair x19, 64
> +	.seh_save_fregp d8, 80
> +	.seh_save_fregp_x d8, 96
> +	.seh_save_freg d8, 112
> +	.seh_save_freg_x d8, 128
> +	.seh_save_fplr 144
> +	.seh_save_fplr_x 160
> +	.seh_save_r19r20_x 176
> +	.seh_add_fp 192
> +	.seh_nop
> +	.seh_pac_sign_lr
> +	.seh_set_fp
> +	.seh_save_next
> +	.seh_endproc
> +
> +	.seh_proc
> +	.seh_proc foo
> +	.seh_endproc
> +
> +	.seh_proc foo
> +
> +	.seh_stackalloc -16
> +	.seh_stackalloc 268435455
> +	.seh_stackalloc 268435456
> +
> +	.seh_save_reg x18, 0
> +	.seh_save_reg x31, 0
> +	.seh_save_reg d19, 0
> +	.seh_save_reg x19, -8
> +	.seh_save_reg x19, 504
> +	.seh_save_reg x19, 511
> +	.seh_save_reg x19, 512
> +
> +	.seh_save_reg_x x18, 16
> +	.seh_save_reg_x x31, 16
> +	.seh_save_reg_x d19, 16
> +	.seh_save_reg_x x19, -8
> +	.seh_save_reg_x x19, 256
> +	.seh_save_reg_x x19, 263
> +	.seh_save_reg_x x19, 264
> +
> +	.seh_save_regp x18, 32
> +	.seh_save_regp x31, 32
> +	.seh_save_regp d19, 32
> +	.seh_save_regp x30, 32
> +	.seh_save_regp x19, -8
> +	.seh_save_regp x19, 504
> +	.seh_save_regp x19, 511
> +	.seh_save_regp x19, 512
> +
> +	.seh_save_regp_x x18, 48
> +	.seh_save_regp_x x31, 48
> +	.seh_save_regp_x d19, 48
> +	.seh_save_regp_x x30, 48
> +	.seh_save_regp_x x19, -8
> +	.seh_save_regp_x x19, 512
> +	.seh_save_regp_x x19, 519
> +	.seh_save_regp_x x19, 520
> +
> +	.seh_save_lrpair x18, 64
> +	.seh_save_lrpair x31, 64
> +	.seh_save_lrpair d19, 64
> +	.seh_save_lrpair x20, 64
> +	.seh_save_lrpair x19, -8
> +	.seh_save_lrpair x19, 504
> +	.seh_save_lrpair x19, 511
> +	.seh_save_lrpair x19, 512
> +
> +	.seh_save_fregp d7, 80
> +	.seh_save_fregp d16, 80
> +	.seh_save_fregp x8, 80
> +	.seh_save_fregp d8, -8
> +	.seh_save_fregp d8, 504
> +	.seh_save_fregp d8, 511
> +	.seh_save_fregp d8, 512
> +
> +	.seh_save_fregp_x d7, 96
> +	.seh_save_fregp_x d16, 96
> +	.seh_save_fregp_x x8, 96
> +	.seh_save_fregp_x d8, -8
> +	.seh_save_fregp_x d8, 512
> +	.seh_save_fregp_x d8, 519
> +	.seh_save_fregp_x d8, 520
> +
> +	.seh_save_freg d7, 112
> +	.seh_save_freg d16, 112
> +	.seh_save_freg x8, 112
> +	.seh_save_freg d8, -8
> +	.seh_save_freg d8, 504
> +	.seh_save_freg d8, 511
> +	.seh_save_freg d8, 512
> +
> +	.seh_save_freg_x d7, 128
> +	.seh_save_freg_x d16, 128
> +	.seh_save_freg_x x8, 128
> +	.seh_save_freg_x d8, -8
> +	.seh_save_freg_x d8, 256
> +	.seh_save_freg_x d8, 263
> +	.seh_save_freg_x d8, 264
> +
> +	.seh_save_fplr -8
> +	.seh_save_fplr 504
> +	.seh_save_fplr 511
> +	.seh_save_fplr 512
> +
> +	.seh_save_fplr_x -8
> +	.seh_save_fplr_x 512
> +	.seh_save_fplr_x 519
> +	.seh_save_fplr_x 520
> +
> +	.seh_save_r19r20_x -8
> +	.seh_save_r19r20_x 248
> +	.seh_save_r19r20_x 255
> +	.seh_save_r19r20_x 256
> +
> +	.seh_add_fp -8
> +	.seh_add_fp 2040
> +	.seh_add_fp 2047
> +	.seh_add_fp 2048
> +
> +	.seh_endprologue
> diff --git a/gas/testsuite/gas/pe/seh-aarch64-large-func.d b/gas/testsuite/gas/pe/seh-aarch64-large-func.d
> new file mode 100644
> index 00000000000..61338de5145
> --- /dev/null
> +++ b/gas/testsuite/gas/pe/seh-aarch64-large-func.d
> @@ -0,0 +1,53 @@
> +#objdump: -s -j .xdata
> +#name: PEP aarch64 SEH large function
> +
> +.*:     file format pe-aarch64-little
> +
> +Contents of section .xdata:
> +
> +# .xdata SEH record
> +# 0x0813ffff  code-words: 1
> +#             epilogue-count: 0
> +#             single-epilogue-in-header: 0
> +#             exception-data: 1
> +#             version: 0
> +#             function-size: 1048572
> +# 0x01         .seh_stackalloc 16
> +# 0xe4        end
> +# 0xe3        nop
> +# 0xe3        nop
> +# 0x00000000  seh-handler
> +# 0x00000000  fragment-offset
> +# 0x0000003c  seh-handle-data-address
> +# 0x0813ffff  code-words: 1
> +#             epilogue-count: 0
> +#             single-epilogue-in-header: 0
> +#             exception-data: 1
> +#             version: 0
> +#             function-size: 1048572
> +# 0x01        .seh_stackalloc 16
> +# 0xe4        end
> +# 0xe3        nop
> +# 0xe3        nop
> +# 0x00000000  seh-handler
> +# 0x000ffffc  fragment-offset
> +# 0x0000003c  seh-handle-data-address
> +# 0x087002ca  code-words: 1
> +#             epilogue-count: 0
> +#             single-epilogue-in-header: 0
> +#             exception-data: 1
> +#             version: 0
> +#             function-size: 2856
> +# 0xe5        end_c
> +# 0x01         .seh_stackalloc 16
> +# 0xe4        end
> +# 0xe3        nop
> +# 0x00000000  seh-handler
> +# 0x001ffff8  fragment-offset
> +# 0x0000003c  seh-handle-data-address
> +# 0x00000001  long 1 (seh_handlerdata)
> +
> + 0000 ffff1308 01e4e3e3 00000000 00000000  .*
> + 0010 3c000000 ffff1308 01e4e3e3 00000000  .*
> + 0020 fcff0f00 3c000000 ca027008 e501e4e3  .*
> + 0030 00000000 f8ff1f00 3c000000 01000000  .*
> \ No newline at end of file
> diff --git a/gas/testsuite/gas/pe/seh-aarch64-large-func.s b/gas/testsuite/gas/pe/seh-aarch64-large-func.s
> new file mode 100644
> index 00000000000..4e7d4772b65
> --- /dev/null
> +++ b/gas/testsuite/gas/pe/seh-aarch64-large-func.s
> @@ -0,0 +1,13 @@
> +	.text
> +	.seh_proc	foo
> +foo:
> +	.seh_stackalloc 16
> +	.seh_endprologue
> +	.rept 2100000 / 4
> +	nop
> +	.endr
> +	.seh_handler _ZN9exception6handleEPvS0_S0_S0_, @except
> +	.seh_handlerdata
> +	.long 1
> +	.seh_code
> +	.seh_endproc
> diff --git a/gas/testsuite/gas/pe/seh-aarch64.d b/gas/testsuite/gas/pe/seh-aarch64.d
> new file mode 100644
> index 00000000000..218366ab6b0
> --- /dev/null
> +++ b/gas/testsuite/gas/pe/seh-aarch64.d
> @@ -0,0 +1,66 @@
> +#objdump: -s -j .xdata
> +#name: PEP aarch64 SEH
> +
> +.*:     file format pe-aarch64-little
> +
> +Contents of section .xdata:
> +
> +# .xdata SEH record
> +# 0x98700000  code-words: 19
> +#             epilogue-count: 1
> +#             single-epilogue-in-header: 1
> +#             exception-data: 1
> +#             version: 0
> +#             function-size: 0
> +# 0xe6        .seh_save_next
> +# 0xe1        .seh_save_fp
> +# 0xfc        .seh_pac_sign_lr
> +# 0xe3        .seh_nop
> +# 0xe218      .seh_add_fp 192
> +# 0x36        .seh_save_r19r20_x 176
> +# 0x93        .seh_save_fplr_x 160
> +# 0x52        .seh_save_fplr 144
> +# 0xdeef      .seh_save_freg_x d15, 128
> +# 0xde2f      .seh_save_freg_x d9, 128
> +# 0xde0f      .seh_save_freg_x d8, 128
> +# 0xddce      .seh_save_freg d15, 112
> +# 0xdc4e      .seh_save_freg d9, 112
> +# 0xdc0e      .seh_save_freg d8, 112
> +# 0xdbcb      .seh_save_fregp_x d15, 96
> +# 0xda4b      .seh_save_fregp_x d9, 96
> +# 0xda0b      .seh_save_fregp_x d8, 96
> +# 0xd9ca      .seh_save_fregp d15, 80
> +# 0xd84a      .seh_save_fregp d9, 80
> +# 0xd80a      .seh_save_fregp d8, 80
> +# 0xd748      .seh_save_lrpair x29, 64
> +# 0xd648      .seh_save_lrpair x21, 64
> +# 0xd608      .seh_save_lrpair x19, 64
> +# 0xce85      .seh_save_regp_x x29, 48
> +# 0xcc45      .seh_save_regp_x x20, 48
> +# 0xcc05      .seh_save_regp_x x19, 48
> +# 0xca84      .seh_save_regp x29, 32
> +# 0xc844      .seh_save_regp x20, 32
> +# 0xc804      .seh_save_regp x19, 32
> +# 0xd561      .seh_save_reg_x x30, 16
> +# 0xd421      .seh_save_reg_x x20, 16
> +# 0xd401      .seh_save_reg_x x19, 16
> +# 0xd2c0      .seh_save_reg x30, 0
> +# 0xd040      .seh_save_reg x20, 0
> +# 0xd000      .seh_save_reg x19, 0
> +# 0xe0ffffff  .seh_stackalloc 268435440
> +# 0xe0000800  .seh_stackalloc 32768
> +# 0xc020      .seh_stackalloc 512
> +# 0x01        .seh_stackalloc 16
> +# 0xe4        nop
> +# 0xe4        nop
> +# 0x00000000  seh-handler
> +# 0x00000000  fragment-offset
> +# 0x0000005c  seh-handle-data-address
> +# 0x00000001  long 1 (seh_handlerdata)
> +
> + 0000 00007098 e6e1fce3 e2183693 52deefde  .*
> + 0010 2fde0fdd cedc4edc 0edbcbda 4bda0bd9  .*
> + 0020 cad84ad8 0ad748d6 48d608ce 85cc45cc  .*
> + 0030 05ca84c8 44c804d5 61d421d4 01d2c0d0  .*
> + 0040 40d000e0 ffffffe0 000800c0 2001e4e4  .*
> + 0050 00000000 00000000 5c000000 01000000  .*
> \ No newline at end of file
> diff --git a/gas/testsuite/gas/pe/seh-aarch64.s b/gas/testsuite/gas/pe/seh-aarch64.s
> new file mode 100644
> index 00000000000..5868a7f57dc
> --- /dev/null
> +++ b/gas/testsuite/gas/pe/seh-aarch64.s
> @@ -0,0 +1,49 @@
> +	.text
> +	.seh_proc	foo
> +	.seh_stackalloc 16
> +	.seh_stackalloc 512
> +	.seh_stackalloc 32768
> +	.seh_stackalloc 268435440
> +	.seh_save_reg x19, 0
> +	.seh_save_reg x20, 0
> +	.seh_save_reg x30, 0
> +	.seh_save_reg_x x19, 16
> +	.seh_save_reg_x x20, 16
> +	.seh_save_reg_x x30, 16
> +	.seh_save_regp x19, 32
> +	.seh_save_regp x20, 32
> +	.seh_save_regp x29, 32
> +	.seh_save_regp_x x19, 48
> +	.seh_save_regp_x x20, 48
> +	.seh_save_regp_x x29, 48
> +	.seh_save_lrpair x19, 64
> +	.seh_save_lrpair x21, 64
> +	.seh_save_lrpair x29, 64
> +	.seh_save_fregp d8, 80
> +	.seh_save_fregp d9, 80
> +	.seh_save_fregp d15, 80
> +	.seh_save_fregp_x d8, 96
> +	.seh_save_fregp_x d9, 96
> +	.seh_save_fregp_x d15, 96
> +	.seh_save_freg d8, 112
> +	.seh_save_freg d9, 112
> +	.seh_save_freg d15, 112
> +	.seh_save_freg_x d8, 128
> +	.seh_save_freg_x d9, 128
> +	.seh_save_freg_x d15, 128
> +	.seh_save_fplr 144
> +	.seh_save_fplr_x 160
> +	.seh_save_r19r20_x 176
> +	.seh_add_fp 192
> +	.seh_nop
> +	.seh_pac_sign_lr
> +	.seh_set_fp
> +	.seh_save_next
> +	.seh_endprologue
> +	.seh_handler _ZN9exception6handleEPvS0_S0_S0_, @except
> +	.seh_handlerdata
> +	.long 1
> +	.seh_code
> +	.seh_startepilogue
> +	.seh_endepilogue
> +	.seh_endproc
> diff --git a/gas/write.c b/gas/write.c
> index 9514c3df42e..b1a0d00a275 100644
> --- a/gas/write.c
> +++ b/gas/write.c
> @@ -1839,7 +1839,7 @@ set_symtab (void)
>  #endif
>  #endif
>  
> -static void
> +void
>  subsegs_finish_section (asection *s)
>  {
>    struct frchain *frchainP;
> diff --git a/gas/write.h b/gas/write.h
> index bc5260a2efd..69072cd57e2 100644
> --- a/gas/write.h
> +++ b/gas/write.h
> @@ -191,5 +191,6 @@ extern void as_bad_subtract (fixS *);
>  struct segment_info_struct;
>  extern fragS *get_frag_for_address (fragS *, const struct segment_info_struct *,
>  				    addressT);
> +extern void subsegs_finish_section (asection *);
>  
>  #endif /* __write_h__ */


From penny.technologyuserdatabase1@gmail.com  Tue Jun 16 18:16:03 2026
From: penny.technologyuserdatabase1@gmail.com (penny.technologyuserdatabase1@gmail.com)
Date: Tue, 16 Jun 2026 13:16:03 -0500
Subject: ASEE - Approved Mailing Database
Message-ID: <0e2101dcfdbc$5061add0$f1250970$@gmail.com>

Hi,

 

The American Society for Engineering Education Annual Conference 2026
Contact Mailing List is now available.

 

Data benefits - Email marketing campaigns | Direct mail marketing | Brand
promotion | Reach targeted prospects via email and phone | Lead generation
and business development | and more!

 

Please reply with one of the options below:

 

1 - Yes, send me the full details, pricing, and data format.

2 - Please remove me from this mailing list.

 

Looking forward to helping you grow your business.

 

Regards,

Penny Albritton

ASEE - Business Executive

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From ndesaulniers@google.com  Tue Jun 16 21:36:43 2026
From: ndesaulniers@google.com (Nick Desaulniers)
Date: Tue, 16 Jun 2026 14:36:43 -0700
Subject: CFP: Toolchains Track at Linux Plumbers Conf '26
Message-ID: <CAKwvOdkaE7nHQbMRKBHmY6jE326bx=czi8yeL2qypsOj3Pq+Og@mail.gmail.com>

(bcc (to avoid cross posting) the following lists:
- llvm@lists.linux.dev
- linux-kernel@vger.kernel.org
- rust-for-linux@vger.kernel.org
- gcc@gcc.gnu.org
- libc-alpha@sourceware.org
- gdb-patches@sourceware.org
- poke-devel@gnu.org,
- binutils@sourceware.org
- a few people explicitly as a polite suggestion/nudge
)

My colleague Jose Marchesi and I would like to announce that the Call
For Papers (CFP) is now open for the Toolchains Track at Linux
Plumbers Conference 2026.

This year, Plumbers will take place in Prague, Czechia from Monday
October 5th to Wednesday October 7th.  Please see
https://lpc.events/event/20/ for more info
about the event.

The aim of the Toolchains track is to fix particular toolchain issues
which are of the interest of the kernel and, ideally, find solutions
in situ, making the best use of the opportunity of live discussion
with kernel developers and maintainers. In particular, this is not
about presenting research nor abstract/miscellaneous toolchain work.

The track will be composed of activities, of variable length depending
on the topic being discussed. Each activity is intended to cover a
particular topic or issue involving both the Linux kernel and one or
more of its associated toolchains and development tools. This includes
compiling, linking, assemblers, debuggers and debugging formats, ABI
analysis tools, object manipulation, applied machine learning, etc.
Few slides shall be necessary, and most of the time shall be devoted to
actual discussion, brainstorming and seeking agreement.

To submit a proposal, please visit the below.  Click "Submit new
abstract" then make sure to select "Toolchains Track" under the
"Track" dropdown.

https://lpc.events/event/20/abstracts/

Submissions close: 24 July 2026 - Speakers notified: from 31 July 2026

We look forward to submissions, and hope to see you there!

-- 
Thanks,
~Nick Desaulniers

From amodra@gmail.com  Wed Jun 17 01:09:09 2026
From: amodra@gmail.com (Alan Modra)
Date: Wed, 17 Jun 2026 10:39:09 +0930
Subject: [PATCH] ld/testsuite: add support for remote testing in ld-cdtest
In-Reply-To: <CAJ307Eh2qzm1uc+yJoPSEt3LbYBM0bfwQo2fyTxVJS2H5jmP4Q@mail.gmail.com>
References: <20260529135252.2094804-1-chigot@adacore.com>
 <CAJ307Eh2qzm1uc+yJoPSEt3LbYBM0bfwQo2fyTxVJS2H5jmP4Q@mail.gmail.com>
Message-ID: <ajHztSbdug8aSbFp@squeak.grove.modra.org>

On Tue, Jun 16, 2026 at 04:12:06PM +0200, Cl?ment Chigot wrote:
> There is a minor mistake here, it should be "set failed 1". Otherwise,
> we get a duplicate FAIL.
> @Alan Modra  still ok for master ?

I was hoping someone who is more expert in the testsuite would review
this.  When I apply your patch locally, I see the following so I think
you have a little more work to do.

aarch64-linux-gnu  +FAIL: cdtest
aarch64-linux-gnu  +FAIL: cdtest with -Ur
alpha-linux-gnu  +FAIL: cdtest
alpha-linux-gnu  +FAIL: cdtest with -Ur
arm-linux-gnueabi  +FAIL: cdtest
arm-linux-gnueabi  +FAIL: cdtest with -Ur
hppa-linux-gnu  +FAIL: cdtest
hppa-linux-gnu  +FAIL: cdtest with -Ur
ia64-linux-gnu  +FAIL: cdtest
ia64-linux-gnu  +FAIL: cdtest with -Ur
m68k-linux-gnu  +FAIL: cdtest
m68k-linux-gnu  +FAIL: cdtest with -Ur
microblaze-linux-gnu  +FAIL: cdtest
microblaze-linux-gnu  +FAIL: cdtest with -Ur
mips64-linux-gnuabi64  +FAIL: cdtest
mips64-linux-gnuabi64  +FAIL: cdtest with -Ur
mips-linux-gnu  +FAIL: cdtest
mips-linux-gnu  +FAIL: cdtest with -Ur
powerpc64le-linux-gnu  +FAIL: cdtest
powerpc64le-linux-gnu  +FAIL: cdtest with -Ur
powerpc64-linux-gnu  +FAIL: cdtest
powerpc64-linux-gnu  +FAIL: cdtest with -Ur
powerpc-linux-gnu  +FAIL: cdtest
powerpc-linux-gnu  +FAIL: cdtest with -Ur
riscv64-linux-gnu  +FAIL: cdtest
riscv64-linux-gnu  +FAIL: cdtest with -Ur
s390-linux-gnu  +FAIL: cdtest
s390-linux-gnu  +FAIL: cdtest with -Ur
s390x-linux-gnu  +FAIL: cdtest
s390x-linux-gnu  +FAIL: cdtest with -Ur
sh4-linux-gnu  +FAIL: cdtest
sh4-linux-gnu  +FAIL: cdtest with -Ur
sparc64-linux-gnu  +FAIL: cdtest
sparc64-linux-gnu  +FAIL: cdtest with -Ur
sparc64-linux-gnu  -FAIL: Build pr29655
tilepro-linux-gnu  +FAIL: cdtest
tilepro-linux-gnu  +FAIL: cdtest with -Ur
x86_64-w64-mingw32  +ERROR: tmpdir/cdtest does not exist in unix_load.
x86_64-w64-mingw32  +ERROR: tmpdir/cdtest does not exist in unix_load.

-- 
Alan Modra

From amodra@gmail.com  Wed Jun 17 01:27:26 2026
From: amodra@gmail.com (Alan Modra)
Date: Wed, 17 Jun 2026 10:57:26 +0930
Subject: [PATCH] ld/testsuite: add support for remote testing in ld-cdtest
In-Reply-To: <ajHztSbdug8aSbFp@squeak.grove.modra.org>
References: <20260529135252.2094804-1-chigot@adacore.com>
 <CAJ307Eh2qzm1uc+yJoPSEt3LbYBM0bfwQo2fyTxVJS2H5jmP4Q@mail.gmail.com>
 <ajHztSbdug8aSbFp@squeak.grove.modra.org>
Message-ID: <ajH3_gntvteiUKnO@squeak.grove.modra.org>

Typical log file shows:
Running: tmpdir/cdtest
Setting LD_LIBRARY_PATH to :
Execution timeout is: 300
spawn [open ...]
tmpdir/cdtest: 1: ELF@?4H@4: not found
tmpdir/cdtest: 2: Syntax error: word unexpected (expecting ")")
tmpdir/cdtest: 1: ELF@?4H@4: not found
tmpdir/cdtest: 2: Syntax error: word unexpected (expecting ")")

FAIL: cdtest

-- 
Alan Modra

From jiawei@iscas.ac.cn  Wed Jun 17 05:01:21 2026
From: jiawei@iscas.ac.cn (Jiawei)
Date: Wed, 17 Jun 2026 13:01:21 +0800
Subject: [PATCH v6 1/2] RISC-V: Add SpacemiT vendor extension xsmtvdot
In-Reply-To: <0ca5423e-3712-4f84-abaf-fb24586d6b4b@suse.com>
References: <b9da157e-9a4d-4988-8478-487cad3850d9@iscas.ac.cn>
 <20260615081901.1991388-1-zhuangqiubin@linux.spacemit.com>
 <0ca5423e-3712-4f84-abaf-fb24586d6b4b@suse.com>
Message-ID: <5ad76b80-43c1-4d25-ac7f-cf487ff56c08@iscas.ac.cn>


? 2026/6/15 16:25, Jan Beulich ??:
> On 15.06.2026 10:19, Mark Zhuang wrote:
>> This patch series has received a Reviewed-by from Jiawei. Could you
>> please take a look and commit it when you have time? I'm happy to make
>> any further changes if needed.
> Hmm, no, not really. I'm not a RISC-V maintainer (adding them to Cc), and
> for arch-specific new code it should imo really be them to take care.
>
> I'm sorry, Jan

Thanks Jan.

I agree this should be handled by the RISC-V side.

I have reviewed the series and it looks good to me. I can also help
with testing and committing it once there is approval from a RISC-V
maintainer.

Best regards,

Jiawei


From chigot@adacore.com  Wed Jun 17 07:05:44 2026
From: chigot@adacore.com (=?UTF-8?Q?Cl=C3=A9ment_Chigot?=)
Date: Wed, 17 Jun 2026 09:05:44 +0200
Subject: [PATCH] ld/testsuite: add support for remote testing in ld-cdtest
In-Reply-To: <ajH3_gntvteiUKnO@squeak.grove.modra.org>
References: <20260529135252.2094804-1-chigot@adacore.com>
 <CAJ307Eh2qzm1uc+yJoPSEt3LbYBM0bfwQo2fyTxVJS2H5jmP4Q@mail.gmail.com>
 <ajHztSbdug8aSbFp@squeak.grove.modra.org>
 <ajH3_gntvteiUKnO@squeak.grove.modra.org>
Message-ID: <CAJ307Ej+u3vDMj+kvaRGf8P=te411=5txT96OayZBcxXr_ogPg@mail.gmail.com>

On Wed, Jun 17, 2026 at 3:27?AM Alan Modra <amodra@gmail.com> wrote:
>
> Typical log file shows:
> Running: tmpdir/cdtest
> Setting LD_LIBRARY_PATH to :
> Execution timeout is: 300
> spawn [open ...]
> tmpdir/cdtest: 1:  ELF       @ ?4H@  4: not found
> tmpdir/cdtest: 2: Syntax error: word unexpected (expecting ")")
> tmpdir/cdtest: 1:  ELF       @ ?4H@  4: not found
> tmpdir/cdtest: 2: Syntax error: word unexpected (expecting ")")
>
> FAIL: cdtest

Hum indeed. I don't see those errors during our internal testing
(using remote obviously) nor when I've tried with master on my laptop
(x86_64-linux-gnu but it seems ok on our side too).
I'll investigate.

Thanks
Cl?ment

> Alan Modra

From evgeny.karpov@arm.com  Wed Jun 17 08:39:46 2026
From: evgeny.karpov@arm.com (Evgeny Karpov)
Date: Wed, 17 Jun 2026 10:39:46 +0200
Subject: [PATCH v9 0/1] Implement Structured Exception Handling (SEH) on
 AArch64
Message-ID: <20260617083947.8097-1-evgeny.karpov@arm.com>

Hello,

Thank you for reviewing v8!
v9 contains minor stylistic changes.

Changes in v9:
- Align backslashes only with tabs.
- Replace links with text that can help find proper resources.
- Replace binary literals with hex.
- Correct whitespace.

Changes in v8 2026-06-15:
- Refactor and simplify some conditions.
- Move .xdata record writing to a separate
  function (seh_aarch64_emit_xdata_record).
- Add documentation link to obj-coff-seh-aarch64.h.
- Add a minor change to the patch description.
- Use only prologue/epilogue.
- Add SEH tests.
- Use unsigned char instead of unsigned for aarch64_unwind_info.
- Rename offset/reg_offset to offset_addend/reg_addend.
- Remove shift direction from the names.
- Correct typos and comments locations.
- Add more comments and extend some of them.
- Reorder aarch64_unwind_code_data declarations.
- Remove AARCH64_UNOP_* and use code inside the declaration.
- Remove members that are NULL or 0.
- Rename unwind_code_pack_info to info.
- Rename aarch64_element to element and move 4 lines to the end of the function.
- Add validations for offset and reg.
- Drop the condition for code_bits.
- Inline some constants to the conditions.
- Check the register name for SEH directives.
- Modify style by changing line wrapping.
- Optimize some calculations.
- Remove some comments to avoid confusion.
- Add clarification for missing implementation.
- Move seh_aarch64_write_data under OBJ_COFF scope.
- Support .seh_code to simplify porting from x86_64.
https://sourceware.org/pipermail/binutils/2026-June/149639.html

Changes in v7 2026-03-19:
- Rename sort_x64_pdata to sort_pdata.
- Move obj_coff_seh_do_final implementation to a separate function.
- Merge patch 3/4 with 4/4.
https://sourceware.org/pipermail/binutils/2026-March/148657.html

Changes in v6 2026-03-11:
- Revert changes in frag_offset_ignore_align_p.
- Relax the code segment to be able to calculate the function sizes.
- Add seh_function_size that implements the calculation of the function size
  and replace frag_offset_ignore_align_p call with this implementation.
https://sourceware.org/pipermail/binutils/2026-March/148488.html

Changes in v5 2026-02-24:
- In many places int, uint32_t and int32_t have been replaced to unsigned.
- Refactor and move SEH aarch64 implementation to separate files.
- Replace uintptr_t with bfd_vma.
- Update comments.
- Add dedicated initializers.
- Move some variables inside loops.
- Fix the definition for packing some unwinding codes.
- Add description to seh commands.
- Rename prolog_instruction_count to prolog_insn_count.
- Relocate variable initilization closer to place of use.
- Add unwind_ prefix to unwind type enumerator.
https://sourceware.org/pipermail/binutils/2026-February/148332.html

Changes in v3(v4) 2025-08-14:
- Make the AArch64 implementation fully static.
- Fix ARM64_MAX_UNWIND_CODES and introduce AARCH64_MAX_UNWIND_CODES_SIZE.
- Add validation for the epilogue_scope array.
- Add an upper bound for the register number.
- Exclude changes in md_do_align.
- Refactor the AArch64 SEH implementation to emit .pdata/.xdata records at
  the end of assembly.
- Declare md_finish for AArch64 to trigger obj_coff_generate_pdata.
- Support different fragment ordering in frag_offset_ignore_align_p
- Change signed to unsigned.
- Replace Arm64 / arm64 with AArch64 / aarch64.
- Add references to the official documentation to clarify
  implementation.
- Add static and aarch64_ prefix.
- Rebase onto the current master.
- Fix comments.
- Correct code style and naming.
https://sourceware.org/pipermail/binutils/2025-August/143401.html

Changes in v2 2025-05-09:
- Add guards for different architectures
- Fix code style issues and typos
- Move Arm64-specific code to pdata/xdata functions
- Prefer unsigned int over uint32_t in some places
- Revert memory release to the original implementation
- Refactor long function fragmentation
- Fix the function size calculation issue related to code alignment
https://sourceware.org/pipermail/binutils/2025-May/140961.html

v1 2025-04-09:
This patch series supports the GCC patch series that implements SEH
support for the aarch64-w64-mingw32 target.
https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669003.html
The patch series has been tested by applying internal tests and passing
all Boost library tests that involve exception handling.
https://sourceware.org/pipermail/binutils/2025-April/140495.html

Regards,
Evgeny

Evgeny Karpov (1):
  aarch64: Implement Structured Exception Handling (SEH) on AArch64

 gas/config/obj-coff-seh-aarch64.c             | 971 ++++++++++++++++++
 gas/config/obj-coff-seh-aarch64.h             | 251 +++++
 gas/config/obj-coff-seh-shared.c              |   8 +-
 gas/config/obj-coff.c                         |   4 +
 gas/config/tc-aarch64.c                       |  10 +
 gas/config/tc-aarch64.h                       |   6 +
 gas/testsuite/gas/pe/pe.exp                   |   3 +
 gas/testsuite/gas/pe/seh-aarch64-error.l      | 110 ++
 gas/testsuite/gas/pe/seh-aarch64-error.s      | 128 +++
 gas/testsuite/gas/pe/seh-aarch64-large-func.d |  53 +
 gas/testsuite/gas/pe/seh-aarch64-large-func.s |  13 +
 gas/testsuite/gas/pe/seh-aarch64.d            |  66 ++
 gas/testsuite/gas/pe/seh-aarch64.s            |  49 +
 gas/write.c                                   |   2 +-
 gas/write.h                                   |   1 +
 15 files changed, 1673 insertions(+), 2 deletions(-)
 create mode 100644 gas/config/obj-coff-seh-aarch64.c
 create mode 100644 gas/config/obj-coff-seh-aarch64.h
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64-error.l
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64-error.s
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64-large-func.d
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64-large-func.s
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64.d
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64.s


From evgeny.karpov@arm.com  Wed Jun 17 08:39:47 2026
From: evgeny.karpov@arm.com (Evgeny Karpov)
Date: Wed, 17 Jun 2026 10:39:47 +0200
Subject: [PATCH v9 1/1] aarch64: Implement Structured Exception Handling (SEH)
 on AArch64
In-Reply-To: <20260617083947.8097-1-evgeny.karpov@arm.com>
References: <20260617083947.8097-1-evgeny.karpov@arm.com>
Message-ID: <20260617083947.8097-2-evgeny.karpov@arm.com>

The patch reuses shared helpers for SEH and implements SEH on AArch64.
The implementation is based on
(https://learn.microsoft.com/en-us/cpp/build/arm64-exception-handling?view=msvc-170)
and pdata/xdata SEH records are emitted from md_finish.

When .pdata/.xdata is emitted, the function size is required.
Function sizes are calculated as late as possible, and the code segment needs
to be relaxed to be able to calculate the function sizes.

Initially, obj_coff_generate_pdata was called in write_object_file.
Before the change, obj_coff_generate_pdata was used only to validate
syntax, which was sufficient for that purpose. However, that location
seems incorrect, as it is too late to emit .pdata/.xdata records
in the AArch64 case.

md_finish has been declared for AArch64 and extended with
seh_aarch64_write_data to emit .pdata/.xdata records after all
assembly has been completed.

Signed-off-by: Evgeny Karpov <evgeny@kmaps.co>

gas/ChangeLog:
	* gas/config/obj-coff-seh-shared.c (defined): Update.
	(struct seh_seg_list): Use seh_context_t.
	* gas/config/obj-coff.c (defined): Update.
	* gas/config/tc-aarch64.c (defined): Add OBJ_COFF guard.
	(aarch64_md_finish): Add.
	* gas/config/tc-aarch64.h (defined): Add OBJ_COFF guard.
	(md_finish): Add.
	(aarch64_md_finish): Add.
	(seh_aarch64_write_data): Add.
	* testsuite/gas/pe/pe.exp: Add SEH tests.
	* write.c: Update.
	* write.h (subsegs_finish_section): Update.
	* config/obj-coff-seh-aarch64.c: New file.
	* config/obj-coff-seh-aarch64.h: New file.
	* testsuite/gas/pe/seh-aarch64-error.l: New test.
	* testsuite/gas/pe/seh-aarch64-error.s: New test.
	* testsuite/gas/pe/seh-aarch64-large-func.d: New test.
	* testsuite/gas/pe/seh-aarch64-large-func.s: New test.
	* testsuite/gas/pe/seh-aarch64.d: New test.
	* testsuite/gas/pe/seh-aarch64.s: New test.
---
 gas/config/obj-coff-seh-aarch64.c             | 971 ++++++++++++++++++
 gas/config/obj-coff-seh-aarch64.h             | 251 +++++
 gas/config/obj-coff-seh-shared.c              |   8 +-
 gas/config/obj-coff.c                         |   4 +
 gas/config/tc-aarch64.c                       |  10 +
 gas/config/tc-aarch64.h                       |   6 +
 gas/testsuite/gas/pe/pe.exp                   |   3 +
 gas/testsuite/gas/pe/seh-aarch64-error.l      | 110 ++
 gas/testsuite/gas/pe/seh-aarch64-error.s      | 128 +++
 gas/testsuite/gas/pe/seh-aarch64-large-func.d |  53 +
 gas/testsuite/gas/pe/seh-aarch64-large-func.s |  13 +
 gas/testsuite/gas/pe/seh-aarch64.d            |  66 ++
 gas/testsuite/gas/pe/seh-aarch64.s            |  49 +
 gas/write.c                                   |   2 +-
 gas/write.h                                   |   1 +
 15 files changed, 1673 insertions(+), 2 deletions(-)
 create mode 100644 gas/config/obj-coff-seh-aarch64.c
 create mode 100644 gas/config/obj-coff-seh-aarch64.h
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64-error.l
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64-error.s
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64-large-func.d
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64-large-func.s
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64.d
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64.s

diff --git a/gas/config/obj-coff-seh-aarch64.c b/gas/config/obj-coff-seh-aarch64.c
new file mode 100644
index 00000000000..ec030ab8b70
--- /dev/null
+++ b/gas/config/obj-coff-seh-aarch64.c
@@ -0,0 +1,971 @@
+/* SEH .pdata/.xdata COFF object file format on AArch64
+   Copyright (C) 2026 Free Software Foundation, Inc.
+
+   This file is part of GAS.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#include "obj-coff-seh-aarch64.h"
+
+static struct seh_aarch64_context *seh_ctx_root = NULL;
+static bool in_seh_proc = false;
+
+struct aarch64_unwind_info {
+  const char *directive;
+  char reg_type;
+  unsigned char offset_bits;
+  unsigned char reg_bits;
+  unsigned char reg_max;
+  unsigned char code_bits;
+  unsigned char code;
+  unsigned char offset_shift;
+  unsigned char offset_addend;
+  unsigned char reg_shift;
+  unsigned char reg_addend;
+  unsigned char size;
+};
+
+/* Unwind codes for AArch64 are described based on
+   "Microsoft ARM64 exception handling, unwind codes documentation"
+   and calculated in seh_aarch64_add_unwind_element function.
+   aarch64_unwind_code_data is indexed by the seh_aarch64_unwind_types enum.  */
+
+static const struct aarch64_unwind_info
+aarch64_unwind_code_data[] = {
+  {
+    .size = 1,
+    .code_bits = 3, .code = 0x0,
+    .offset_bits = 5, .offset_shift = 4
+  },
+  {
+    .size = 2,
+    .code_bits = 5, .code = 0x18,
+    .offset_bits = 11, .offset_shift = 4
+  },
+  {
+    .size = 4,
+    .code_bits = 8, .code = 0xe0,
+    .offset_bits = 24, .offset_shift = 4
+  },
+  {
+    .directive = ".seh_save_reg",
+    .size = 2,
+    .code_bits = 6, .code = 0x34,
+    .offset_bits = 6, .offset_shift = 3,
+    .reg_bits = 4, .reg_addend = 19, .reg_type = 'x'
+  },
+  {
+    .directive = ".seh_save_reg_x",
+    .size = 2,
+    .code_bits = 7, .code = 0x6a,
+    .offset_bits = 5, .offset_shift = 3, .offset_addend = 1,
+    .reg_bits = 4, .reg_addend = 19, .reg_type = 'x'
+  },
+  {
+    .directive = ".seh_save_regp",
+    .size = 2,
+    .code_bits = 6, .code = 0x32,
+    .offset_bits = 6, .offset_shift = 3,
+    .reg_bits = 4, .reg_addend = 19, .reg_type = 'x', .reg_max = 29
+  },
+  {
+    .directive = ".seh_save_regp_x",
+    .size = 2,
+    .code_bits = 6, .code = 0x33,
+    .offset_bits = 6, .offset_shift = 3, .offset_addend = 1,
+    .reg_bits = 4, .reg_addend = 19, .reg_type = 'x', .reg_max = 29
+  },
+  {
+    .directive = ".seh_save_fregp",
+    .size = 2,
+    .code_bits = 7, .code = 0x6c,
+    .offset_bits = 6, .offset_shift = 3,
+    .reg_bits = 3, .reg_addend = 8, .reg_type = 'd'
+  },
+  {
+    .directive = ".seh_save_fregp_x",
+    .size = 2,
+    .code_bits = 7, .code = 0x6d,
+    .offset_bits = 6, .offset_shift = 3, .offset_addend = 1,
+    .reg_bits = 3, .reg_addend = 8, .reg_type = 'd'
+  },
+  {
+    .directive = ".seh_save_freg",
+    .size = 2,
+    .code_bits = 7, .code = 0x6e,
+    .offset_bits = 6, .offset_shift = 3,
+    .reg_bits = 3, .reg_addend = 8, .reg_type = 'd'
+  },
+  {
+    .directive = ".seh_save_freg_x",
+    .size = 2,
+    .code_bits = 8, .code = 0xde,
+    .offset_bits = 5, .offset_shift = 3, .offset_addend = 1,
+    .reg_bits = 3, .reg_addend = 8, .reg_type = 'd'
+  },
+  {
+    .directive = ".seh_save_lrpair",
+    .size = 2,
+    .code_bits = 7, .code = 0x6b,
+    .offset_bits = 6, .offset_shift = 3,
+    .reg_bits = 3, .reg_shift = 1, .reg_addend = 19, .reg_type = 'x'
+  },
+  {
+    .directive = ".seh_save_fplr",
+    .size = 1,
+    .code_bits = 2, .code = 0x1,
+    .offset_bits = 6, .offset_shift = 3
+  },
+  {
+    .directive = ".seh_save_fplr_x",
+    .size = 1,
+    .code_bits = 2, .code = 0x2,
+    .offset_bits = 6, .offset_shift = 3, .offset_addend = 1
+  },
+  {
+    .directive = ".seh_save_r19r20_x",
+    .size = 1,
+    .code_bits = 3, .code = 0x1,
+    .offset_bits = 5, .offset_shift = 3
+  },
+  {
+    .directive = ".seh_add_fp",
+    .size = 2,
+    .code_bits = 8, .code = 0xe2,
+    .offset_bits = 8, .offset_shift = 3
+  },
+  {
+    .directive = ".seh_set_fp",
+    .size = 1,
+    .code_bits = 8, .code = 0xe1
+  },
+  {
+    .directive = ".seh_save_next",
+    .size = 1,
+    .code_bits = 8, .code = 0xe6
+  },
+  {
+    .directive = ".seh_nop",
+    .size = 1,
+    .code_bits = 8, .code = 0xe3
+  },
+  {
+    .directive = ".seh_pac_sign_lr",
+    .size = 1,
+    .code_bits = 8, .code = 0xfc
+  },
+  {
+    .size = 1,
+    .code_bits = 8, .code = 0xe4
+  },
+};
+
+/* Set for current context the default handler.  */
+static void
+obj_coff_seh_handler (const int what ATTRIBUTE_UNUSED)
+{
+  char *symbol_name;
+  char name_end;
+
+  if (!verify_context (".seh_handler"))
+    return;
+
+  if (*input_line_pointer == 0 || *input_line_pointer == '\n')
+    as_bad (_(".seh_handler requires a handler"));
+
+  SKIP_WHITESPACE ();
+
+  if (*input_line_pointer == '@')
+    {
+      name_end = get_symbol_name (&symbol_name);
+
+      seh_ctx_cur->handler.X_op = O_constant;
+      seh_ctx_cur->handler.X_add_number = 0;
+
+      if (strcasecmp (symbol_name, "@1") == 0)
+	seh_ctx_cur->handler.X_add_number = 1;
+      else if (strcasecmp (symbol_name, "@0")
+	       && strcasecmp (symbol_name, "@null"))
+	as_bad (_("unknown constant value '%s' for handler"), symbol_name);
+
+      (void) restore_line_pointer (name_end);
+    }
+  else
+    expression (&seh_ctx_cur->handler);
+
+  seh_ctx_cur->handler_data.X_op = O_constant;
+  seh_ctx_cur->handler_data.X_add_number = 0;
+  seh_ctx_cur->xdata_header.x = 1;
+
+  while (skip_whitespace_and_comma (0))
+    {
+      name_end = get_symbol_name (&symbol_name);
+      (void) restore_line_pointer (name_end);
+    }
+}
+
+/* Switch to subsection for handler data for exception region.  */
+static void
+obj_coff_seh_handlerdata (const int what ATTRIBUTE_UNUSED)
+{
+  demand_empty_rest_of_line ();
+
+  switch_xdata (seh_ctx_cur->subsection + 1, seh_ctx_cur->code_seg);
+  seh_ctx_cur->handler_data_xdata_addr = symbol_temp_new_now();
+}
+
+/* Switch back to the code section.  */
+static void
+obj_coff_seh_code (int ignored ATTRIBUTE_UNUSED)
+{
+  subseg_set (seh_ctx_cur->code_seg, 0);
+}
+
+/* Obtain available unwind element.  */
+static void
+seh_aarch64_add_unwind_element (const seh_aarch64_unwind_types unwind_type,
+				unsigned offset, unsigned reg)
+{
+  const struct aarch64_unwind_info *info
+    = aarch64_unwind_code_data + unwind_type;
+  unsigned value_offset_bits = 0;
+
+  if ((seh_ctx_cur->unwind_codes_byte_count
+      + info->size) > AARCH64_MAX_UNWIND_CODES_SIZE)
+    as_bad (_("no unwind element available."));
+
+  unsigned value = 0;
+
+  if (info->offset_bits)
+    {
+      const unsigned divided_by = 1u << info->offset_shift;
+      if (offset & (divided_by - 1))
+	as_bad (_("offset should be divided by %u"), divided_by);
+      offset = (offset >> info->offset_shift) - info->offset_addend;
+      if (offset >= (1u << info->offset_bits))
+	as_bad (_("offset overflows expected range"));
+      value |= offset << value_offset_bits;
+      value_offset_bits += info->offset_bits;
+    }
+
+  if (info->reg_bits)
+    {
+      const unsigned regn_divided_by = 1u << info->reg_shift;
+      reg -= info->reg_addend;
+      if (reg & (regn_divided_by - 1))
+	as_bad (_("unexpected register number"));
+      reg >>= info->reg_shift;
+      if (reg >= (1u << info->reg_bits))
+	as_bad (_("unexpected register number"));
+      value |= reg << value_offset_bits;
+      value_offset_bits += info->reg_bits;
+    }
+
+  const unsigned code = info->code;
+  gas_assert (code < (1u << info->code_bits));
+  value |= code << value_offset_bits;
+
+  seh_aarch64_unwind_code *element;
+  element = seh_ctx_cur->unwind_codes + seh_ctx_cur->unwind_codes_count++;
+  element->type = unwind_type;
+  element->value = value;
+
+  seh_ctx_cur->unwind_codes_byte_count += info->size;
+}
+
+/* Mark begin of new context.  */
+static void
+obj_coff_seh_proc (const int what ATTRIBUTE_UNUSED)
+{
+  char *symbol_name;
+  char name_end;
+
+  if (in_seh_proc)
+    as_bad (_("previous SEH entry not closed (missing .seh_endproc)"));
+
+  if (*input_line_pointer == 0 || *input_line_pointer == '\n')
+    as_bad (_(".seh_proc requires function label name"));
+
+
+  if (!seh_ctx_root)
+  {
+    seh_ctx_root = XCNEW (seh_context);
+    seh_ctx_cur = seh_ctx_root;
+  }
+  else
+  {
+    seh_ctx_cur->next = XCNEW (seh_context);
+    seh_ctx_cur = seh_ctx_cur->next;
+  }
+
+  seh_ctx_cur->next = NULL;
+  seh_ctx_cur->code_seg = now_seg;
+
+  /* The current implementation always use a pair of .pdata and .xdata
+     records.  */
+  const bool use_xdata = true;
+
+  if (use_xdata)
+    {
+      x_segcur = seh_hash_find_or_make (seh_ctx_cur->code_seg, ".xdata");
+      seh_ctx_cur->subsection = x_segcur->subseg;
+      x_segcur->subseg += 2;
+
+      /* Initialize an empty .xdata record.  */
+      seh_ctx_cur->unwind_codes_count = 0;
+      seh_ctx_cur->unwind_codes_byte_count = 0;
+      seh_ctx_cur->epilogue_scopes_count = 0;
+      seh_ctx_cur->epilogue_scopes_capacity = 0;
+      seh_ctx_cur->epilogue_scopes = NULL;
+      seh_ctx_cur->xdata_header.x = 0;
+    }
+
+  SKIP_WHITESPACE ();
+
+  name_end = get_symbol_name (&symbol_name);
+  seh_ctx_cur->func_name = xstrdup (symbol_name);
+  (void) restore_line_pointer (name_end);
+
+  demand_empty_rest_of_line ();
+
+  seh_ctx_cur->start_addr = symbol_temp_new_now ();
+  in_seh_proc = true;
+}
+
+/* Mark end of prologue for current context.  */
+static void
+obj_coff_seh_endprologue (const int what ATTRIBUTE_UNUSED)
+{
+  if (!verify_context (".seh_endprologue")
+      || !seh_validate_seg (".seh_endprologue"))
+    return;
+  demand_empty_rest_of_line ();
+
+  if (seh_ctx_cur->endprologue_addr != NULL)
+    as_warn (_("duplicate .seh_endprologue in .seh_proc block"));
+  else
+    seh_ctx_cur->endprologue_addr = symbol_temp_new_now ();
+
+  /* Unwind codes need to be reversed.  */
+  for (unsigned i = 0, n = seh_ctx_cur->unwind_codes_count; i < n / 2; ++i)
+    {
+      seh_aarch64_unwind_code *unwind_codes = seh_ctx_cur->unwind_codes;
+      const seh_aarch64_unwind_code temp = unwind_codes[i];
+      unwind_codes[i] = unwind_codes[n-i-1];
+      unwind_codes[n-i-1] = temp;
+    }
+
+   seh_aarch64_add_unwind_element (unwind_end, 0, 0);
+}
+
+/* Mark end of current context.  */
+static void
+obj_coff_seh_endproc (const int what ATTRIBUTE_UNUSED)
+{
+  demand_empty_rest_of_line ();
+  if (!in_seh_proc)
+    {
+      as_bad (_(".seh_endproc used without .seh_proc"));
+      return;
+    }
+
+  seh_validate_seg (".seh_endproc");
+
+  seh_ctx_cur->end_addr = symbol_temp_new_now ();
+  in_seh_proc = false;
+}
+
+static void
+obj_coff_seh_startepilogue (const int what ATTRIBUTE_UNUSED)
+{
+  if (!verify_context (".seh_startepilogue")
+      || !seh_validate_seg (".seh_startepilogue"))
+    return;
+  demand_empty_rest_of_line ();
+
+  if (seh_ctx_cur->epilogue_scopes_count >= AARCH64_MAX_EPILOGUE_SCOPES)
+    as_bad (_("no epilogue scopes available."));
+
+  symbolS *epilogue_start_addr = symbol_temp_new_now ();
+  expressionS exp;
+  exp.X_op = O_subtract;
+  exp.X_add_symbol = epilogue_start_addr;
+  exp.X_op_symbol = seh_ctx_cur->start_addr;
+  exp.X_add_number = 0;
+
+  if (!resolve_expression (&exp) || exp.X_op != O_constant
+      || exp.X_add_number < 0)
+    as_bad (_(".seh_startepilogue offset expression for %s "
+	    "does not evaluate to a non-negative constant"),
+	    S_GET_NAME (epilogue_start_addr));
+
+  if (seh_ctx_cur->epilogue_scopes_count
+      >= seh_ctx_cur->epilogue_scopes_capacity)
+    {
+      const unsigned initial_capacity = 32;
+      if (seh_ctx_cur->epilogue_scopes_capacity)
+	seh_ctx_cur->epilogue_scopes_capacity *= 2;
+      else
+	seh_ctx_cur->epilogue_scopes_capacity = initial_capacity;
+
+      seh_ctx_cur->epilogue_scopes
+	= XRESIZEVEC (seh_aarch64_epilogue_scope, seh_ctx_cur->epilogue_scopes,
+		     seh_ctx_cur->epilogue_scopes_capacity);
+    }
+
+  seh_aarch64_epilogue_scope *epilogue_scope = seh_ctx_cur->epilogue_scopes
+    + seh_ctx_cur->epilogue_scopes_count;
+  epilogue_scope->epilogue_start_offset = exp.X_add_number / 4;
+  epilogue_scope->reserved = 0;
+  epilogue_scope->epilogue_start_index = 0;
+  seh_ctx_cur->epilogue_scopes_count++;
+}
+
+static void
+obj_coff_seh_endepilogue (const int what ATTRIBUTE_UNUSED)
+{
+  if (!verify_context (".seh_endepilogue")
+      || !seh_validate_seg (".seh_endepilogue"))
+    return;
+
+  demand_empty_rest_of_line ();
+
+  expressionS exp;
+  symbolS *epilogue_end_addr = symbol_temp_new_now ();
+  exp.X_op = O_subtract;
+  exp.X_add_symbol = epilogue_end_addr;
+  exp.X_op_symbol = seh_ctx_cur->start_addr;
+  exp.X_add_number = 0;
+
+  if (!resolve_expression (&exp) || exp.X_op != O_constant
+      || exp.X_add_number < 0)
+    as_bad (_(".seh_endepilogue offset expression for %s "
+	    "does not evaluate to a non-negative constant"),
+	    S_GET_NAME (epilogue_end_addr));
+
+   seh_aarch64_epilogue_scope *epilogue_scope = seh_ctx_cur->epilogue_scopes
+     + seh_ctx_cur->epilogue_scopes_count - 1;
+
+   epilogue_scope->epilogue_end_offset = exp.X_add_number;
+
+  /* End code.  */
+  seh_aarch64_add_unwind_element (unwind_end, 0, 0);
+}
+
+/* End-of-file hook.  */
+static void
+free_seh_ctx (struct seh_aarch64_context *seh_ctx)
+{
+  free (seh_ctx->func_name);
+  const seh_aarch64_func_fragment *fragment = seh_ctx->func_fragment.next;
+  while (fragment)
+    {
+      const seh_aarch64_func_fragment *next = fragment->next;
+      XDELETE (fragment);
+      fragment = next;
+    }
+  XDELETEVEC (seh_ctx->epilogue_scopes);
+  free (seh_ctx);
+}
+
+static void
+obj_coff_seh_save_reg (const int type)
+{
+  gas_assert (type >= 0 && type <= unwind_last_type);
+
+  const struct aarch64_unwind_info *info
+    = aarch64_unwind_code_data + type;
+
+  SKIP_WHITESPACE ();
+
+  char *symbol_name = NULL;
+  unsigned reg = -1;
+
+  if (info->reg_bits)
+    {
+      char name_end = get_symbol_name (&symbol_name);
+      if (info->reg_type != *symbol_name)
+	as_bad ("unexpected register name");
+
+      reg = atoi (symbol_name + 1);
+      (void) restore_line_pointer (name_end);
+
+      if (!skip_whitespace_and_comma (1))
+	return;
+
+      const unsigned reg_max = info->reg_max ? info->reg_max: 30;
+      if (reg > reg_max)
+	as_bad (_("unexpected register number"));
+    }
+
+  offsetT off = -1;
+  if (info->offset_bits)
+    {
+      off = get_absolute_expression ();
+
+      if (off < 0)
+	as_bad (_("offset is negative"));
+    }
+
+  demand_empty_rest_of_line ();
+
+  if (!in_seh_proc)
+  {
+    as_bad (_("SEH entry has not been found (missing .seh_proc)"));
+    return;
+  }
+
+  if (!info->directive || !seh_validate_seg (info->directive))
+    return;
+
+  seh_aarch64_add_unwind_element (type, off, reg);
+}
+
+/* Add a stack-allocation token to current context.  */
+static void
+obj_coff_seh_stackalloc (const int what ATTRIBUTE_UNUSED)
+{
+  const offsetT off = get_absolute_expression ();
+  demand_empty_rest_of_line ();
+
+  if (!in_seh_proc)
+    {
+      as_bad (_("SEH entry has not been found (missing .seh_proc)"));
+      return;
+    }
+
+  if (off < 0x200)
+    seh_aarch64_add_unwind_element (unwind_alloc_s, off, 0);
+  else if (off < 0x8000)
+    seh_aarch64_add_unwind_element (unwind_alloc_m, off, 0);
+  else if (off < 0x10000000)
+    seh_aarch64_add_unwind_element (unwind_alloc_l, off, 0);
+  else
+    as_bad (_(".seh_stackalloc offset is out of range"));
+}
+
+/* Data writing routines.  */
+static void
+seh_aarch64_emit_epilogue_scopes (const seh_context *seh_ctx,
+				  const uint64_t fragment_offset,
+				  const unsigned prologue_size,
+				  const unsigned first_fragment_scope,
+				  const unsigned last_fragment_scope,
+				  const bool has_phantom_prologue)
+{
+  unsigned start_index_offset = 0;
+  const seh_aarch64_epilogue_scope *scopes = seh_ctx->epilogue_scopes;
+  if (first_fragment_scope < seh_ctx->epilogue_scopes_count)
+    start_index_offset = scopes[first_fragment_scope].epilogue_start_index
+			 - prologue_size;
+  if (has_phantom_prologue)
+    {
+      if (start_index_offset == 0)
+	as_bad (_("start index offset for the epilogue cannot be 0 when "
+		"phantom prologue is used"));
+      --start_index_offset;
+    }
+
+  for (unsigned i = first_fragment_scope; i < last_fragment_scope; ++i)
+    {
+      seh_aarch64_epilogue_scope scope = seh_ctx->epilogue_scopes[i];
+      scope.epilogue_start_offset_reduced = (scope.epilogue_start_offset
+					    - fragment_offset) >> 2;
+      scope.epilogue_start_index -= start_index_offset;
+      uint32_t scope_code;
+      memcpy (&scope_code, &scope, sizeof (scope_code));
+      md_number_to_chars (frag_more (4), scope_code, 4);
+    }
+}
+
+static void
+seh_aarch64_emit_unwind_codes (const seh_context *seh_ctx,
+			       const unsigned prologue_size,
+			       const unsigned first_epilogue_index,
+			       const unsigned last_epilogue_index,
+			       const bool has_phantom_prologue)
+{
+  unsigned total_byte_count = 0;
+
+  if (has_phantom_prologue)
+    {
+      ++total_byte_count;
+      const unsigned endc_code = 0xe5;
+      md_number_to_chars (frag_more (1), endc_code, 1);
+    }
+
+  unsigned unwind_bytes_offset = 0;
+  for (unsigned i = 0; i < seh_ctx->unwind_codes_count; ++i)
+    {
+      const seh_aarch64_unwind_code *code = seh_ctx->unwind_codes + i;
+      const unsigned byte_count
+	= aarch64_unwind_code_data[code->type].size;
+      unwind_bytes_offset += byte_count;
+
+      if (unwind_bytes_offset > last_epilogue_index)
+	break;
+
+      if (unwind_bytes_offset > prologue_size
+	  && unwind_bytes_offset <= first_epilogue_index)
+	continue;
+
+      /*  emit unwind code bytes in big endian.  */
+      number_to_chars_bigendian (frag_more (byte_count), code->value,
+				 byte_count);
+      total_byte_count += byte_count;
+    }
+
+    /* Handle word alignment.  */
+    const unsigned required_padding = (-total_byte_count) % 4;
+    if (required_padding)
+      {
+	/* Use the nop unwind code for alignment.  */
+	const uint32_t nop_chain = 0xe3e3e3e3;
+
+	md_number_to_chars (frag_more (required_padding), nop_chain,
+			    required_padding);
+      }
+}
+
+static void
+seh_aarch64_emit_xdata_record (struct seh_aarch64_context *seh_ctx,
+			       const uintptr_t frag_size,
+			       const uintptr_t fragment_offset,
+			       const unsigned header_size,
+			       const unsigned prologue_size,
+			       const unsigned prologue_insn_count,
+			       const bool has_phantom_prologue,
+			       const unsigned first_fragment_scope,
+			       const unsigned last_fragment_scope,
+			       const unsigned first_epilogue_index,
+			       const unsigned last_epilogue_index)
+{
+  const seh_aarch64_xdata_header *header = &seh_ctx->xdata_header;
+  md_number_to_chars (frag_more (header_size), seh_ctx->xdata_header_value,
+		      header_size);
+
+  if (header->ext_epilogue_count && !header->e)
+    {
+      seh_aarch64_emit_epilogue_scopes (seh_ctx,
+					fragment_offset, prologue_size,
+					first_fragment_scope,
+					last_fragment_scope,
+					has_phantom_prologue);
+      if (has_phantom_prologue)
+	{
+	  const uint32_t epilogue_start_index_encoded = 1 << 22;
+	  const uint32_t epilogue_start_offset_encoded
+	    = (frag_size - prologue_insn_count * 4) >> 2;
+	  md_number_to_chars (frag_more (4),
+			      epilogue_start_index_encoded
+			      | epilogue_start_offset_encoded, 4);
+	}
+    }
+
+  if (header->ext_code_words)
+    seh_aarch64_emit_unwind_codes (seh_ctx, prologue_size, first_epilogue_index,
+				   last_epilogue_index, has_phantom_prologue);
+
+  if (header->x == 1)
+    {
+      if (seh_ctx->handler.X_op == O_symbol)
+	seh_ctx->handler.X_op = O_symbol_rva;
+
+      emit_expr (&seh_ctx->handler, 4);
+
+      /* Emit the fragment offset.  */
+      md_number_to_chars (frag_more (4), fragment_offset, 4);
+
+      /* Use the same SEH handler data for all fragments.
+	 The SEH handler data is emitted after the last fragment.  */
+      expressionS exp;
+      memset (&exp, 0, sizeof (expressionS));
+      exp.X_op = O_symbol_rva;
+      exp.X_add_symbol = seh_ctx->handler_data_xdata_addr;
+      emit_expr (&exp, 4);
+    }
+}
+
+static bool
+seh_function_size (const struct seh_aarch64_context *seh_ctx,
+		  uintptr_t *size)
+{
+  fragS *start_frag, *end_frag;
+  addressT start_offset, end_offset;
+  start_frag = symbol_get_frag_and_value (seh_ctx->start_addr, &start_offset);
+  end_frag = symbol_get_frag_and_value (seh_ctx->end_addr, &end_offset);
+
+  intptr_t func_size = end_frag->fr_address + end_offset
+		       - start_frag->fr_address - start_offset;
+  if (func_size < 0)
+    return false;
+
+  *size = func_size;
+  return true;
+}
+
+/* Write out the xdata information for one function.  */
+static void
+seh_aarch64_write_function_xdata (struct seh_aarch64_context *seh_ctx)
+{
+  if (!seh_ctx->unwind_codes_byte_count)
+    return;
+
+  const segT save_seg = now_seg;
+  const subsegT save_subseg = now_subseg;
+
+  switch_xdata (seh_ctx->subsection, seh_ctx->code_seg);
+
+  /* Set 4-byte alignment.  */
+  frag_align (2, 0, 0);
+
+  uintptr_t func_size = 0;
+  if (!seh_function_size (seh_ctx, &func_size))
+    {
+      as_bad (_("the function size for %s has not been evaluated"),
+	      seh_ctx->func_name);
+      return;
+    }
+
+  /* The large functions should be split into fragments smaller than 1MB with
+     4 bytes alignment, based on
+     "Microsoft ARM64 exception handling, large functions documentation".  */
+  const unsigned max_frag_size = (1 << 20) - 4;
+  const bool is_fragmented_function = func_size > max_frag_size;
+
+  unsigned prologue_insn_count = 0;
+  for (unsigned i = 0; i < seh_ctx->unwind_codes_count; ++i)
+    {
+      if (seh_ctx->unwind_codes[i].type == unwind_end)
+	{
+	  prologue_insn_count = i + 1;
+	  break;
+	}
+    }
+
+  unsigned prologue_size = seh_ctx->unwind_codes_byte_count;
+
+  seh_aarch64_func_fragment *fragment;
+  fragment = &seh_ctx->func_fragment;
+  uintptr_t fragment_offset = 0;
+  unsigned first_fragment_scope = 0;
+  unsigned last_fragment_scope = 0;
+
+  /* Large functions (>= 1MB) will be split into multiple fragments.
+     However, it is expected the most of the functions will have only one
+     fragment. This loop iterates fragments and emit them.  */
+  while (true)
+    {
+      fragment->xdata_addr = symbol_temp_new_now ();
+      fragment->offset = fragment_offset;
+      fragment->next = NULL;
+
+      /* Calculate current fragment size.  */
+      uintptr_t frag_size = func_size - fragment_offset;
+      if (frag_size > max_frag_size)
+	frag_size = max_frag_size;
+
+      const bool is_last_frag = (fragment_offset + frag_size) == func_size;
+
+      /* If it is a fragmented function, the epilogue range should be calculated
+	 and will be emitted for the current fragment, otherwise all epilogues
+	 will be emitted.  */
+      if (!is_fragmented_function)
+	last_fragment_scope = seh_ctx->epilogue_scopes_count;
+      else
+	{
+	  first_fragment_scope = last_fragment_scope;
+	  for (unsigned i = first_fragment_scope;
+	       i < seh_ctx->epilogue_scopes_count; ++i)
+	    {
+	      const seh_aarch64_epilogue_scope *scope
+		= seh_ctx->epilogue_scopes;
+	      scope += i;
+	      if (scope->epilogue_start_offset >= (fragment_offset + frag_size))
+		break;
+
+	      if (scope->epilogue_end_offset >= (fragment_offset + frag_size))
+		{
+		  frag_size = scope->epilogue_start_offset - fragment_offset;
+		  break;
+		}
+
+	      if (scope->epilogue_start_offset >= fragment_offset)
+		last_fragment_scope = i + 1;
+	    }
+	}
+
+      seh_aarch64_xdata_header *header = &seh_ctx->xdata_header;
+      const seh_aarch64_epilogue_scope *scopes = seh_ctx->epilogue_scopes;
+
+      /* Initialize the .xdata record.  */
+      const uint32_t func_length_encoded = frag_size >> 2;
+      header->func_length = func_length_encoded;
+      header->vers = 0;
+      header->e = 0;
+      header->code_words = 0;
+      header->epilogue_count = 0;
+
+      header->ext_code_words = 0;
+      header->ext_epilogue_count = last_fragment_scope
+				   - first_fragment_scope;
+      header->reserved = 0;
+
+      /* Calculate epilogue indexes for the current fragment.  */
+      unsigned first_epilogue_index = 0;
+      unsigned last_epilogue_index = 0;
+      if (!header->ext_epilogue_count)
+	{
+	  first_epilogue_index = prologue_size;
+	  last_epilogue_index = prologue_size;
+	}
+      else
+	{
+	  const seh_aarch64_epilogue_scope *scope;
+	  scope = scopes + first_fragment_scope;
+	  first_epilogue_index = scope->epilogue_start_index;
+	  last_epilogue_index = seh_ctx->unwind_codes_byte_count;
+	}
+
+      /* Calculate how many unwind bytes will be emitted in .xdata record.  */
+      unsigned unwind_bytes = prologue_size;
+
+      /* Check if current fragment has a phantom prologue. If yes, then
+	 the unwinding size should be adjusted.  */
+      const bool has_phantom_prologue = is_fragmented_function && is_last_frag;
+      if (has_phantom_prologue && unwind_bytes)
+	{
+	  /* One more epilogue scope and unwind code are emitted with phantom
+	     prologue.  */
+	  unwind_bytes += 1;
+	  ++header->ext_epilogue_count;
+	}
+
+      /* Calculate the number of code words with 4-byte alignment.  */
+      header->ext_code_words = (unwind_bytes + 3) / 4;
+
+      /* Check if short or extended header for a .xdata record should be
+	 used.  */
+      unsigned header_size = 8;
+      if ((header->ext_code_words != 0 || header->ext_epilogue_count != 0)
+	  && header->ext_code_words < 32
+	  && header->ext_epilogue_count < 32)
+	{
+	  header_size = 4;
+	  header->code_words = header->ext_code_words;
+	  header->epilogue_count = header->ext_epilogue_count;
+	  if (header->epilogue_count == 1)
+	    {
+	      header->e = 1;
+	      if (has_phantom_prologue)
+		header->ext_epilogue_count = 0;
+	      else
+		{
+		  const seh_aarch64_epilogue_scope *scope;
+		  scope = scopes + first_fragment_scope;
+		  header->ext_epilogue_count = scope->epilogue_start_index;
+		}
+	    }
+	}
+
+      /* Emit a .xdata record for the current fragment.  */
+      seh_aarch64_emit_xdata_record(seh_ctx, frag_size, fragment_offset,
+				    header_size,
+				    prologue_size, prologue_insn_count,
+				    has_phantom_prologue,
+				    first_fragment_scope, last_fragment_scope,
+				    first_epilogue_index, last_epilogue_index);
+
+      fragment_offset += frag_size;
+      /* Exit the loop if it is the latest fragment.  */
+      if (is_last_frag)
+	break;
+
+      /* Allocate a new fragment that will be used also for emitting a .pdata
+	 record.  */
+      fragment->next = XCNEW (seh_aarch64_func_fragment);
+      fragment = fragment->next;
+    }
+
+  subseg_set (save_seg, save_subseg);
+}
+
+/* Write out pdata for one function.  */
+static void
+seh_aarch64_write_function_pdata (const seh_context *seh_ctx)
+{
+  expressionS exp;
+  const segT save_seg = now_seg;
+  const subsegT save_subseg = now_subseg;
+  memset (&exp, 0, sizeof (expressionS));
+  switch_pdata (seh_ctx->code_seg);
+
+  if (seh_ctx->unwind_codes_byte_count)
+    {
+      const seh_aarch64_func_fragment *fragment = &seh_ctx->func_fragment;
+      while (fragment)
+	{
+	  exp.X_op = O_symbol_rva;
+	  exp.X_add_number = fragment->offset;
+	  exp.X_add_symbol = seh_ctx->start_addr;
+	  emit_expr (&exp, 4);
+
+	  exp.X_op = O_symbol_rva;
+	  /* TODO: Implementing packed unwind data.  */
+	  exp.X_add_number = 0;
+	  exp.X_add_symbol = fragment->xdata_addr;
+	  emit_expr (&exp, 4);
+	  fragment = fragment->next;
+	}
+    }
+
+  subseg_set (save_seg, save_subseg);
+}
+
+void
+seh_aarch64_write_data (void)
+{
+  if (in_seh_proc)
+  {
+    as_bad (_("open SEH entry at end of file (missing .seh_endproc)"));
+    return;
+  }
+
+  if (!seh_ctx_root)
+    return;
+
+  struct seh_aarch64_context *seh_ctx = seh_ctx_root;
+  seh_ctx_root = NULL;
+
+  /* Relax the segment to be able to calculate the function sizes.  */
+  subsegs_finish_section (seh_ctx->code_seg);
+  const segment_info_type *seginfo = seg_info (seh_ctx->code_seg);
+  relax_segment (seginfo->frchainP->frch_root, seh_ctx->code_seg, 0);
+
+  while (seh_ctx)
+  {
+    seh_aarch64_write_function_xdata (seh_ctx);
+    seh_aarch64_write_function_pdata (seh_ctx);
+    struct seh_aarch64_context *next = seh_ctx->next;
+    free_seh_ctx (seh_ctx);
+    seh_ctx = next;
+  }
+}
+
+void
+obj_coff_seh_do_final (void)
+{
+}
diff --git a/gas/config/obj-coff-seh-aarch64.h b/gas/config/obj-coff-seh-aarch64.h
new file mode 100644
index 00000000000..99828721a72
--- /dev/null
+++ b/gas/config/obj-coff-seh-aarch64.h
@@ -0,0 +1,251 @@
+/* SEH .pdata/.xdata COFF object file format on AArch64
+   Copyright (C) 2026 Free Software Foundation, Inc.
+
+   This file is part of GAS.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+/* SEH COFF AArch64 implementation partially intersects with the x64
+   version, however it has a different extension to the unwind codes.
+   It emits SEH data to pdata and xdata sections.  In some cases SEH
+   data could be emitted to a packed record in the pdata section
+   without the need for data in the xdata section.  However, the packed
+   pdata record is not implemented yet.
+
+   The current implementation does not include:
+   - Packed .pdata record.
+   - Support for AdvSIMD and SVE.
+   - Epilogue start index different than 0.  */
+
+#ifndef OBJ_COFF_SEH_AARCH64_H
+#define OBJ_COFF_SEH_AARCH64_H
+
+/* Unwind codes for AArch64 are based on
+   "Microsoft ARM64 exception handling, unwind codes documentation".  */
+
+typedef enum seh_aarch64_unwind_types
+{
+  unwind_alloc_s,
+  unwind_alloc_m,
+  unwind_alloc_l,
+  unwind_save_reg,
+  unwind_save_reg_x,
+  unwind_save_regp,
+  unwind_save_regp_x,
+  unwind_save_fregp,
+  unwind_save_fregp_x,
+  unwind_save_freg,
+  unwind_save_freg_x,
+  unwind_save_lrpair,
+  unwind_save_fplr,
+  unwind_save_fplr_x,
+  unwind_save_r19r20_x,
+  unwind_add_fp,
+  unwind_set_fp,
+  unwind_save_next,
+  unwind_nop,
+  unwind_pac_sign_lr,
+  unwind_end,
+  unwind_end_c,
+  unwind_last_type = unwind_end_c
+} seh_aarch64_unwind_types;
+
+#define SEH_CMDS							\
+  /* Start a function that contains SEH.  */				\
+  {"seh_proc", obj_coff_seh_proc, 0},					\
+									\
+  /* End a function that contains SEH.  */				\
+  {"seh_endproc", obj_coff_seh_endproc, 0},				\
+									\
+  /* End a SEH prologue with unwinding codes.  */			\
+  {"seh_endprologue", obj_coff_seh_endprologue, 0},			\
+									\
+  /* Allocate stack.  */						\
+  {"seh_stackalloc", obj_coff_seh_stackalloc, 0},			\
+									\
+  /* Set a SEH handler.  */						\
+  {"seh_handler", obj_coff_seh_handler, 0},				\
+									\
+  /* Set a SEH handler data.  */					\
+  {"seh_handlerdata", obj_coff_seh_handlerdata, 0},			\
+									\
+  /* Switch back to the code section.  */				\
+  {"seh_code", obj_coff_seh_code, 0},					\
+									\
+  /* Start a SEH epilogue.  */						\
+  {"seh_startepilogue", obj_coff_seh_startepilogue, 0},			\
+									\
+  /* End a SEH epilogue.  */						\
+  {"seh_endepilogue", obj_coff_seh_endepilogue, 0},			\
+									\
+  /* Save an 'x' register.  */						\
+  {"seh_save_reg", obj_coff_seh_save_reg, unwind_save_reg},		\
+									\
+  /* Save an 'x' register with a pre-indexed offset.  */		\
+  {"seh_save_reg_x", obj_coff_seh_save_reg, unwind_save_reg_x},		\
+									\
+  /* Save an 'x' register pair.  */					\
+  {"seh_save_regp", obj_coff_seh_save_reg, unwind_save_regp},		\
+									\
+  /* Save an 'x' register pair with a pre-indexed offset.  */		\
+  {"seh_save_regp_x", obj_coff_seh_save_reg, unwind_save_regp_x},	\
+									\
+  /* Save an 'x' register and lr.  */					\
+  {"seh_save_lrpair", obj_coff_seh_save_reg, unwind_save_lrpair},	\
+									\
+  /* Save a 'd' register pair.  */					\
+  {"seh_save_fregp", obj_coff_seh_save_reg, unwind_save_fregp},		\
+									\
+  /* Save a 'd' register pair with a pre-indexed offset.  */		\
+  {"seh_save_fregp_x", obj_coff_seh_save_reg, unwind_save_fregp_x},	\
+									\
+  /* Save a 'd' register.  */						\
+  {"seh_save_freg", obj_coff_seh_save_reg, unwind_save_freg},		\
+									\
+  /* Save a 'd' register with a pre-indexed offset.  */			\
+  {"seh_save_freg_x", obj_coff_seh_save_reg, unwind_save_freg_x},	\
+									\
+  /* Save fp and lr registers.  */					\
+  {"seh_save_fplr", obj_coff_seh_save_reg, unwind_save_fplr},		\
+									\
+  /* Save fp and lr registers with a pre-indexed offset.  */		\
+  {"seh_save_fplr_x", obj_coff_seh_save_reg, unwind_save_fplr_x},	\
+									\
+  /* Save x19 and x20 registers with a pre-indexed offset.  */		\
+  {"seh_save_r19r20_x", obj_coff_seh_save_reg, unwind_save_r19r20_x},	\
+									\
+  /* Set fp by sp + offset.  */						\
+  {"seh_add_fp", obj_coff_seh_save_reg, unwind_add_fp},			\
+									\
+  /* Unwind operation is not required.  */				\
+  {"seh_nop", obj_coff_seh_save_reg, unwind_nop},			\
+									\
+  /* Sign the return address in lr with pacibsp.  */			\
+  {"seh_pac_sign_lr", obj_coff_seh_save_reg, unwind_pac_sign_lr},	\
+									\
+  /* Set fp by sp.  */							\
+  {"seh_set_fp", obj_coff_seh_save_reg, unwind_set_fp},			\
+									\
+  /* Save next register pair.  */					\
+  {"seh_save_next", obj_coff_seh_save_reg, unwind_save_next},
+
+/* AArch64 exceptions handling and unwinding structures are based on
+   "Microsoft ARM64 exception handling, pdata records documentation".  */
+
+typedef struct seh_aarch64_unwind_code
+{
+  unsigned value;
+  seh_aarch64_unwind_types type;
+} seh_aarch64_unwind_code;
+
+typedef struct seh_aarch64_packed_unwind_data
+{
+  uint32_t flag : 2;
+  uint32_t func_length : 11;
+  uint32_t frame_size : 9;
+  uint32_t cr : 2;
+  uint32_t h : 1;
+  uint32_t regI : 4;
+  uint32_t regF : 3;
+} seh_aarch64_packed_unwind_data;
+
+typedef struct seh_aarch64_except_info
+{
+  uint32_t flag : 2;
+  uint32_t except_info_rva : 30;
+} seh_aarch64_except_info;
+
+typedef union seh_aarch64_unwind_info
+{
+  seh_aarch64_except_info except_info;
+  seh_aarch64_packed_unwind_data packed_unwind_data;
+} seh_aarch64_unwind_info;
+
+typedef struct seh_aarch64_xdata_header
+{
+  uint32_t func_length : 18;
+  uint32_t vers : 2;
+  uint32_t x : 1;
+  uint32_t e : 1;
+  uint32_t epilogue_count : 5;
+  uint32_t code_words : 5;
+  uint32_t ext_epilogue_count : 16;
+  uint32_t ext_code_words : 8;
+  uint32_t reserved : 8;
+} seh_aarch64_xdata_header;
+
+typedef struct seh_aarch64_epilogue_scope
+{
+  uint32_t epilogue_start_offset_reduced : 18;
+  uint32_t reserved : 4;
+  uint32_t epilogue_start_index : 10;
+  bfd_vma epilogue_start_offset;
+  bfd_vma epilogue_end_offset;
+} seh_aarch64_epilogue_scope;
+
+typedef struct seh_aarch64_func_fragment
+{
+  bfd_vma offset;
+  symbolS *xdata_addr;
+  struct seh_aarch64_func_fragment *next;
+} seh_aarch64_func_fragment;
+
+/* AARCH64_MAX_UNWIND_CODES is limited by
+   seh_aarch64_xdata_header::ext_code_words.  */
+#define AARCH64_MAX_UNWIND_CODES (255 * 4)
+#define AARCH64_MAX_UNWIND_CODES_SIZE (255 * 4)
+/* AARCH64_MAX_EPILOGUE_SCOPES is limited by
+   seh_aarch64_xdata_header::ext_epilogue_count.  */
+#define AARCH64_MAX_EPILOGUE_SCOPES 65535
+
+typedef struct seh_aarch64_context
+{
+  struct seh_aarch64_context *next;
+
+  /* Initial code-segment.  */
+  segT code_seg;
+  /* Function name.  */
+  char *func_name;
+  /* BeginAddress.  */
+  symbolS *start_addr;
+  /* EndAddress.  */
+  symbolS *end_addr;
+  /* PrologueEnd.  */
+  symbolS *endprologue_addr;
+
+  symbolS *handler_data_xdata_addr;
+  /* ExceptionHandler.  */
+  expressionS handler;
+  /* ExceptionHandlerData.  */
+  expressionS handler_data;
+
+  subsegT subsection;
+
+  union {
+    seh_aarch64_xdata_header xdata_header;
+    valueT xdata_header_value;
+  };
+  unsigned unwind_codes_count;
+  unsigned unwind_codes_byte_count;
+  seh_aarch64_unwind_code unwind_codes[AARCH64_MAX_UNWIND_CODES];
+  unsigned epilogue_scopes_count;
+  unsigned epilogue_scopes_capacity;
+  seh_aarch64_epilogue_scope *epilogue_scopes;
+  /* The function fragments.  */
+  seh_aarch64_func_fragment func_fragment;
+} seh_context;
+
+#endif /* OBJ_COFF_SEH_AARCH64_H.  */
diff --git a/gas/config/obj-coff-seh-shared.c b/gas/config/obj-coff-seh-shared.c
index 717a7d345ef..b99a6bb67ee 100644
--- a/gas/config/obj-coff-seh-shared.c
+++ b/gas/config/obj-coff-seh-shared.c
@@ -19,7 +19,13 @@
    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
    02110-1301, USA.  */
 
+#if defined (COFFAARCH64)
+#include "obj-coff-seh-aarch64.h"
+typedef struct seh_aarch64_context seh_context_t;
+#else
 #include "obj-coff-seh.h"
+typedef struct seh_context seh_context_t;
+#endif
 
 /* Private segment collection list.  */
 struct seh_seg_list {
@@ -28,7 +34,7 @@ struct seh_seg_list {
   char *seg_name;
 };
 
-static struct seh_context *seh_ctx_cur = NULL;
+static seh_context_t *seh_ctx_cur = NULL;
 
 static htab_t seh_hash;
 
diff --git a/gas/config/obj-coff.c b/gas/config/obj-coff.c
index 7732c0af911..b08295019d8 100644
--- a/gas/config/obj-coff.c
+++ b/gas/config/obj-coff.c
@@ -55,7 +55,11 @@ static const char weak_altprefix[] = ".weak.";
 #endif /* TE_PE */
 
 #include "obj-coff-seh-shared.c"
+#if defined (COFFAARCH64)
+#include "obj-coff-seh-aarch64.c"
+#else
 #include "obj-coff-seh.c"
+#endif
 
 typedef struct
   {
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index fb58bcca9b1..c672f284a48 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10459,6 +10459,16 @@ aarch64_cleanup (void)
     }
 }
 
+#if defined (OBJ_COFF)
+/* Called after all assembly has been done.  */
+
+void
+aarch64_md_finish (void)
+{
+  seh_aarch64_write_data();
+}
+#endif /* OBJ_COFF.  */
+
 #ifdef OBJ_ELF
 /* Remove any excess mapping symbols generated for alignment frags in
    SEC.  We may have created a mapping symbol before a zero byte
diff --git a/gas/config/tc-aarch64.h b/gas/config/tc-aarch64.h
index d1fb4c9058b..6446ac8efb8 100644
--- a/gas/config/tc-aarch64.h
+++ b/gas/config/tc-aarch64.h
@@ -82,6 +82,12 @@ struct aarch64_fix
 
 #define tc_frob_section(S) aarch64_frob_section (S)
 
+#if defined (OBJ_COFF)
+#define md_finish aarch64_md_finish
+extern void aarch64_md_finish (void);
+extern void seh_aarch64_write_data (void);
+#endif
+
 /* The key used to sign a function's return address.  */
 enum pointer_auth_key {
   AARCH64_PAUTH_KEY_A,
diff --git a/gas/testsuite/gas/pe/pe.exp b/gas/testsuite/gas/pe/pe.exp
index e25de3cfa9d..cc7701587ac 100644
--- a/gas/testsuite/gas/pe/pe.exp
+++ b/gas/testsuite/gas/pe/pe.exp
@@ -63,6 +63,9 @@ if ([istarget "x86_64-*-mingw*"]) then {
 # This test is only for AArch64
 if {[istarget "aarch64-*-pe*"] || [istarget "aarch64-*-mingw*"]} {
 	run_dump_test "pe-aarch64"
+	run_dump_test "seh-aarch64"
+	run_dump_test "seh-aarch64-large-func"
+	run_list_test "seh-aarch64-error" ""
 }
 
 # Big obj
diff --git a/gas/testsuite/gas/pe/seh-aarch64-error.l b/gas/testsuite/gas/pe/seh-aarch64-error.l
new file mode 100644
index 00000000000..2d7f2c055f6
--- /dev/null
+++ b/gas/testsuite/gas/pe/seh-aarch64-error.l
@@ -0,0 +1,110 @@
+.*: Assembler messages:
+.*:2: Error: .seh_endprologue used outside of .seh_proc block
+.*:3: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:4: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:5: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:6: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:7: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:8: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:9: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:10: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:11: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:12: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:13: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:14: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:15: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:16: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:17: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:18: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:19: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:20: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:21: Error: .seh_endproc used without .seh_proc
+.*:23: Error: .seh_proc requires function label name
+.*:24: Error: previous SEH entry not closed \(missing .seh_endproc\)
+.*:29: Error: offset overflows expected range
+.*:30: Error: offset should be divided by 16
+.*:31: Error: .seh_stackalloc offset is out of range
+.*:33: Error: unexpected register number
+.*:34: Error: unexpected register number
+.*:35: Error: unexpected register name
+.*:36: Error: offset is negative
+.*:36: Error: offset overflows expected range
+.*:38: Error: offset should be divided by 8
+.*:39: Error: offset overflows expected range
+.*:41: Error: unexpected register number
+.*:42: Error: unexpected register number
+.*:43: Error: unexpected register name
+.*:44: Error: offset is negative
+.*:44: Error: offset overflows expected range
+.*:46: Error: offset should be divided by 8
+.*:47: Error: offset overflows expected range
+.*:49: Error: unexpected register number
+.*:50: Error: unexpected register number
+.*:51: Error: unexpected register name
+.*:52: Error: unexpected register number
+.*:53: Error: offset is negative
+.*:53: Error: offset overflows expected range
+.*:55: Error: offset should be divided by 8
+.*:56: Error: offset overflows expected range
+.*:58: Error: unexpected register number
+.*:59: Error: unexpected register number
+.*:60: Error: unexpected register name
+.*:61: Error: unexpected register number
+.*:62: Error: offset is negative
+.*:62: Error: offset overflows expected range
+.*:64: Error: offset should be divided by 8
+.*:65: Error: offset overflows expected range
+.*:67: Error: unexpected register number
+.*:67: Error: unexpected register number
+.*:68: Error: unexpected register number
+.*:69: Error: unexpected register name
+.*:70: Error: unexpected register number
+.*:71: Error: offset is negative
+.*:71: Error: offset overflows expected range
+.*:73: Error: offset should be divided by 8
+.*:74: Error: offset overflows expected range
+.*:76: Error: unexpected register number
+.*:77: Error: unexpected register number
+.*:78: Error: unexpected register name
+.*:79: Error: offset is negative
+.*:79: Error: offset overflows expected range
+.*:81: Error: offset should be divided by 8
+.*:82: Error: offset overflows expected range
+.*:84: Error: unexpected register number
+.*:85: Error: unexpected register number
+.*:86: Error: unexpected register name
+.*:87: Error: offset is negative
+.*:87: Error: offset overflows expected range
+.*:89: Error: offset should be divided by 8
+.*:90: Error: offset overflows expected range
+.*:92: Error: unexpected register number
+.*:93: Error: unexpected register number
+.*:94: Error: unexpected register name
+.*:95: Error: offset is negative
+.*:95: Error: offset overflows expected range
+.*:97: Error: offset should be divided by 8
+.*:98: Error: offset overflows expected range
+.*:100: Error: unexpected register number
+.*:101: Error: unexpected register number
+.*:102: Error: unexpected register name
+.*:103: Error: offset is negative
+.*:103: Error: offset overflows expected range
+.*:105: Error: offset should be divided by 8
+.*:106: Error: offset overflows expected range
+.*:108: Error: offset is negative
+.*:108: Error: offset overflows expected range
+.*:110: Error: offset should be divided by 8
+.*:111: Error: offset overflows expected range
+.*:113: Error: offset is negative
+.*:113: Error: offset overflows expected range
+.*:115: Error: offset should be divided by 8
+.*:116: Error: offset overflows expected range
+.*:118: Error: offset is negative
+.*:118: Error: offset overflows expected range
+.*:120: Error: offset should be divided by 8
+.*:121: Error: offset overflows expected range
+.*:123: Error: offset is negative
+.*:123: Error: offset overflows expected range
+.*:125: Error: offset should be divided by 8
+.*:126: Error: offset overflows expected range
+.*: Error: open SEH entry at end of file \(missing .seh_endproc\)
diff --git a/gas/testsuite/gas/pe/seh-aarch64-error.s b/gas/testsuite/gas/pe/seh-aarch64-error.s
new file mode 100644
index 00000000000..dc4118b7390
--- /dev/null
+++ b/gas/testsuite/gas/pe/seh-aarch64-error.s
@@ -0,0 +1,128 @@
+	.text
+	.seh_endprologue
+	.seh_stackalloc 16
+	.seh_save_reg x19, 0
+	.seh_save_reg_x x19, 16
+	.seh_save_regp x19, 32
+	.seh_save_regp_x x19, 48
+	.seh_save_lrpair x19, 64
+	.seh_save_fregp d8, 80
+	.seh_save_fregp_x d8, 96
+	.seh_save_freg d8, 112
+	.seh_save_freg_x d8, 128
+	.seh_save_fplr 144
+	.seh_save_fplr_x 160
+	.seh_save_r19r20_x 176
+	.seh_add_fp 192
+	.seh_nop
+	.seh_pac_sign_lr
+	.seh_set_fp
+	.seh_save_next
+	.seh_endproc
+
+	.seh_proc
+	.seh_proc foo
+	.seh_endproc
+
+	.seh_proc foo
+
+	.seh_stackalloc -16
+	.seh_stackalloc 268435455
+	.seh_stackalloc 268435456
+
+	.seh_save_reg x18, 0
+	.seh_save_reg x31, 0
+	.seh_save_reg d19, 0
+	.seh_save_reg x19, -8
+	.seh_save_reg x19, 504
+	.seh_save_reg x19, 511
+	.seh_save_reg x19, 512
+
+	.seh_save_reg_x x18, 16
+	.seh_save_reg_x x31, 16
+	.seh_save_reg_x d19, 16
+	.seh_save_reg_x x19, -8
+	.seh_save_reg_x x19, 256
+	.seh_save_reg_x x19, 263
+	.seh_save_reg_x x19, 264
+
+	.seh_save_regp x18, 32
+	.seh_save_regp x31, 32
+	.seh_save_regp d19, 32
+	.seh_save_regp x30, 32
+	.seh_save_regp x19, -8
+	.seh_save_regp x19, 504
+	.seh_save_regp x19, 511
+	.seh_save_regp x19, 512
+
+	.seh_save_regp_x x18, 48
+	.seh_save_regp_x x31, 48
+	.seh_save_regp_x d19, 48
+	.seh_save_regp_x x30, 48
+	.seh_save_regp_x x19, -8
+	.seh_save_regp_x x19, 512
+	.seh_save_regp_x x19, 519
+	.seh_save_regp_x x19, 520
+
+	.seh_save_lrpair x18, 64
+	.seh_save_lrpair x31, 64
+	.seh_save_lrpair d19, 64
+	.seh_save_lrpair x20, 64
+	.seh_save_lrpair x19, -8
+	.seh_save_lrpair x19, 504
+	.seh_save_lrpair x19, 511
+	.seh_save_lrpair x19, 512
+
+	.seh_save_fregp d7, 80
+	.seh_save_fregp d16, 80
+	.seh_save_fregp x8, 80
+	.seh_save_fregp d8, -8
+	.seh_save_fregp d8, 504
+	.seh_save_fregp d8, 511
+	.seh_save_fregp d8, 512
+
+	.seh_save_fregp_x d7, 96
+	.seh_save_fregp_x d16, 96
+	.seh_save_fregp_x x8, 96
+	.seh_save_fregp_x d8, -8
+	.seh_save_fregp_x d8, 512
+	.seh_save_fregp_x d8, 519
+	.seh_save_fregp_x d8, 520
+
+	.seh_save_freg d7, 112
+	.seh_save_freg d16, 112
+	.seh_save_freg x8, 112
+	.seh_save_freg d8, -8
+	.seh_save_freg d8, 504
+	.seh_save_freg d8, 511
+	.seh_save_freg d8, 512
+
+	.seh_save_freg_x d7, 128
+	.seh_save_freg_x d16, 128
+	.seh_save_freg_x x8, 128
+	.seh_save_freg_x d8, -8
+	.seh_save_freg_x d8, 256
+	.seh_save_freg_x d8, 263
+	.seh_save_freg_x d8, 264
+
+	.seh_save_fplr -8
+	.seh_save_fplr 504
+	.seh_save_fplr 511
+	.seh_save_fplr 512
+
+	.seh_save_fplr_x -8
+	.seh_save_fplr_x 512
+	.seh_save_fplr_x 519
+	.seh_save_fplr_x 520
+
+	.seh_save_r19r20_x -8
+	.seh_save_r19r20_x 248
+	.seh_save_r19r20_x 255
+	.seh_save_r19r20_x 256
+
+	.seh_add_fp -8
+	.seh_add_fp 2040
+	.seh_add_fp 2047
+	.seh_add_fp 2048
+
+	.seh_endprologue
diff --git a/gas/testsuite/gas/pe/seh-aarch64-large-func.d b/gas/testsuite/gas/pe/seh-aarch64-large-func.d
new file mode 100644
index 00000000000..61338de5145
--- /dev/null
+++ b/gas/testsuite/gas/pe/seh-aarch64-large-func.d
@@ -0,0 +1,53 @@
+#objdump: -s -j .xdata
+#name: PEP aarch64 SEH large function
+
+.*:     file format pe-aarch64-little
+
+Contents of section .xdata:
+
+# .xdata SEH record
+# 0x0813ffff  code-words: 1
+#             epilogue-count: 0
+#             single-epilogue-in-header: 0
+#             exception-data: 1
+#             version: 0
+#             function-size: 1048572
+# 0x01         .seh_stackalloc 16
+# 0xe4        end
+# 0xe3        nop
+# 0xe3        nop
+# 0x00000000  seh-handler
+# 0x00000000  fragment-offset
+# 0x0000003c  seh-handle-data-address
+# 0x0813ffff  code-words: 1
+#             epilogue-count: 0
+#             single-epilogue-in-header: 0
+#             exception-data: 1
+#             version: 0
+#             function-size: 1048572
+# 0x01        .seh_stackalloc 16
+# 0xe4        end
+# 0xe3        nop
+# 0xe3        nop
+# 0x00000000  seh-handler
+# 0x000ffffc  fragment-offset
+# 0x0000003c  seh-handle-data-address
+# 0x087002ca  code-words: 1
+#             epilogue-count: 0
+#             single-epilogue-in-header: 0
+#             exception-data: 1
+#             version: 0
+#             function-size: 2856
+# 0xe5        end_c
+# 0x01         .seh_stackalloc 16
+# 0xe4        end
+# 0xe3        nop
+# 0x00000000  seh-handler
+# 0x001ffff8  fragment-offset
+# 0x0000003c  seh-handle-data-address
+# 0x00000001  long 1 (seh_handlerdata)
+
+ 0000 ffff1308 01e4e3e3 00000000 00000000  .*
+ 0010 3c000000 ffff1308 01e4e3e3 00000000  .*
+ 0020 fcff0f00 3c000000 ca027008 e501e4e3  .*
+ 0030 00000000 f8ff1f00 3c000000 01000000  .*
\ No newline at end of file
diff --git a/gas/testsuite/gas/pe/seh-aarch64-large-func.s b/gas/testsuite/gas/pe/seh-aarch64-large-func.s
new file mode 100644
index 00000000000..4e7d4772b65
--- /dev/null
+++ b/gas/testsuite/gas/pe/seh-aarch64-large-func.s
@@ -0,0 +1,13 @@
+	.text
+	.seh_proc	foo
+foo:
+	.seh_stackalloc 16
+	.seh_endprologue
+	.rept 2100000 / 4
+	nop
+	.endr
+	.seh_handler _ZN9exception6handleEPvS0_S0_S0_, @except
+	.seh_handlerdata
+	.long 1
+	.seh_code
+	.seh_endproc
diff --git a/gas/testsuite/gas/pe/seh-aarch64.d b/gas/testsuite/gas/pe/seh-aarch64.d
new file mode 100644
index 00000000000..218366ab6b0
--- /dev/null
+++ b/gas/testsuite/gas/pe/seh-aarch64.d
@@ -0,0 +1,66 @@
+#objdump: -s -j .xdata
+#name: PEP aarch64 SEH
+
+.*:     file format pe-aarch64-little
+
+Contents of section .xdata:
+
+# .xdata SEH record
+# 0x98700000  code-words: 19
+#             epilogue-count: 1
+#             single-epilogue-in-header: 1
+#             exception-data: 1
+#             version: 0
+#             function-size: 0
+# 0xe6        .seh_save_next
+# 0xe1        .seh_save_fp
+# 0xfc        .seh_pac_sign_lr
+# 0xe3        .seh_nop
+# 0xe218      .seh_add_fp 192
+# 0x36        .seh_save_r19r20_x 176
+# 0x93        .seh_save_fplr_x 160
+# 0x52        .seh_save_fplr 144
+# 0xdeef      .seh_save_freg_x d15, 128
+# 0xde2f      .seh_save_freg_x d9, 128
+# 0xde0f      .seh_save_freg_x d8, 128
+# 0xddce      .seh_save_freg d15, 112
+# 0xdc4e      .seh_save_freg d9, 112
+# 0xdc0e      .seh_save_freg d8, 112
+# 0xdbcb      .seh_save_fregp_x d15, 96
+# 0xda4b      .seh_save_fregp_x d9, 96
+# 0xda0b      .seh_save_fregp_x d8, 96
+# 0xd9ca      .seh_save_fregp d15, 80
+# 0xd84a      .seh_save_fregp d9, 80
+# 0xd80a      .seh_save_fregp d8, 80
+# 0xd748      .seh_save_lrpair x29, 64
+# 0xd648      .seh_save_lrpair x21, 64
+# 0xd608      .seh_save_lrpair x19, 64
+# 0xce85      .seh_save_regp_x x29, 48
+# 0xcc45      .seh_save_regp_x x20, 48
+# 0xcc05      .seh_save_regp_x x19, 48
+# 0xca84      .seh_save_regp x29, 32
+# 0xc844      .seh_save_regp x20, 32
+# 0xc804      .seh_save_regp x19, 32
+# 0xd561      .seh_save_reg_x x30, 16
+# 0xd421      .seh_save_reg_x x20, 16
+# 0xd401      .seh_save_reg_x x19, 16
+# 0xd2c0      .seh_save_reg x30, 0
+# 0xd040      .seh_save_reg x20, 0
+# 0xd000      .seh_save_reg x19, 0
+# 0xe0ffffff  .seh_stackalloc 268435440
+# 0xe0000800  .seh_stackalloc 32768
+# 0xc020      .seh_stackalloc 512
+# 0x01        .seh_stackalloc 16
+# 0xe4        nop
+# 0xe4        nop
+# 0x00000000  seh-handler
+# 0x00000000  fragment-offset
+# 0x0000005c  seh-handle-data-address
+# 0x00000001  long 1 (seh_handlerdata)
+
+ 0000 00007098 e6e1fce3 e2183693 52deefde  .*
+ 0010 2fde0fdd cedc4edc 0edbcbda 4bda0bd9  .*
+ 0020 cad84ad8 0ad748d6 48d608ce 85cc45cc  .*
+ 0030 05ca84c8 44c804d5 61d421d4 01d2c0d0  .*
+ 0040 40d000e0 ffffffe0 000800c0 2001e4e4  .*
+ 0050 00000000 00000000 5c000000 01000000  .*
\ No newline at end of file
diff --git a/gas/testsuite/gas/pe/seh-aarch64.s b/gas/testsuite/gas/pe/seh-aarch64.s
new file mode 100644
index 00000000000..5868a7f57dc
--- /dev/null
+++ b/gas/testsuite/gas/pe/seh-aarch64.s
@@ -0,0 +1,49 @@
+	.text
+	.seh_proc	foo
+	.seh_stackalloc 16
+	.seh_stackalloc 512
+	.seh_stackalloc 32768
+	.seh_stackalloc 268435440
+	.seh_save_reg x19, 0
+	.seh_save_reg x20, 0
+	.seh_save_reg x30, 0
+	.seh_save_reg_x x19, 16
+	.seh_save_reg_x x20, 16
+	.seh_save_reg_x x30, 16
+	.seh_save_regp x19, 32
+	.seh_save_regp x20, 32
+	.seh_save_regp x29, 32
+	.seh_save_regp_x x19, 48
+	.seh_save_regp_x x20, 48
+	.seh_save_regp_x x29, 48
+	.seh_save_lrpair x19, 64
+	.seh_save_lrpair x21, 64
+	.seh_save_lrpair x29, 64
+	.seh_save_fregp d8, 80
+	.seh_save_fregp d9, 80
+	.seh_save_fregp d15, 80
+	.seh_save_fregp_x d8, 96
+	.seh_save_fregp_x d9, 96
+	.seh_save_fregp_x d15, 96
+	.seh_save_freg d8, 112
+	.seh_save_freg d9, 112
+	.seh_save_freg d15, 112
+	.seh_save_freg_x d8, 128
+	.seh_save_freg_x d9, 128
+	.seh_save_freg_x d15, 128
+	.seh_save_fplr 144
+	.seh_save_fplr_x 160
+	.seh_save_r19r20_x 176
+	.seh_add_fp 192
+	.seh_nop
+	.seh_pac_sign_lr
+	.seh_set_fp
+	.seh_save_next
+	.seh_endprologue
+	.seh_handler _ZN9exception6handleEPvS0_S0_S0_, @except
+	.seh_handlerdata
+	.long 1
+	.seh_code
+	.seh_startepilogue
+	.seh_endepilogue
+	.seh_endproc
diff --git a/gas/write.c b/gas/write.c
index 9514c3df42e..b1a0d00a275 100644
--- a/gas/write.c
+++ b/gas/write.c
@@ -1839,7 +1839,7 @@ set_symtab (void)
 #endif
 #endif
 
-static void
+void
 subsegs_finish_section (asection *s)
 {
   struct frchain *frchainP;
diff --git a/gas/write.h b/gas/write.h
index bc5260a2efd..69072cd57e2 100644
--- a/gas/write.h
+++ b/gas/write.h
@@ -191,5 +191,6 @@ extern void as_bad_subtract (fixS *);
 struct segment_info_struct;
 extern fragS *get_frag_for_address (fragS *, const struct segment_info_struct *,
 				    addressT);
+extern void subsegs_finish_section (asection *);
 
 #endif /* __write_h__ */

From amodra@gmail.com  Wed Jun 17 13:51:07 2026
From: amodra@gmail.com (Alan Modra)
Date: Wed, 17 Jun 2026 23:21:07 +0930
Subject: [PATCH] ld/testsuite: add support for remote testing in ld-cdtest
In-Reply-To: <CAJ307Ej+u3vDMj+kvaRGf8P=te411=5txT96OayZBcxXr_ogPg@mail.gmail.com>
References: <20260529135252.2094804-1-chigot@adacore.com>
 <CAJ307Eh2qzm1uc+yJoPSEt3LbYBM0bfwQo2fyTxVJS2H5jmP4Q@mail.gmail.com>
 <ajHztSbdug8aSbFp@squeak.grove.modra.org>
 <ajH3_gntvteiUKnO@squeak.grove.modra.org>
 <CAJ307Ej+u3vDMj+kvaRGf8P=te411=5txT96OayZBcxXr_ogPg@mail.gmail.com>
Message-ID: <ajKmS_DmAhoG944I@squeak.grove.modra.org>

On Wed, Jun 17, 2026 at 09:05:44AM +0200, Cl?ment Chigot wrote:
> On Wed, Jun 17, 2026 at 3:27?AM Alan Modra <amodra@gmail.com> wrote:
> >
> > Typical log file shows:
> > Running: tmpdir/cdtest
> > Setting LD_LIBRARY_PATH to :
> > Execution timeout is: 300
> > spawn [open ...]
> > tmpdir/cdtest: 1:  ELF       @ ?4H@  4: not found
> > tmpdir/cdtest: 2: Syntax error: word unexpected (expecting ")")
> > tmpdir/cdtest: 1:  ELF       @ ?4H@  4: not found
> > tmpdir/cdtest: 2: Syntax error: word unexpected (expecting ")")
> >
> > FAIL: cdtest
> 
> Hum indeed. I don't see those errors during our internal testing
> (using remote obviously) nor when I've tried with master on my laptop
> (x86_64-linux-gnu but it seems ok on our side too).
> I'll investigate.

I was testing without any remote.

> Thanks
> Cl?ment
> 
> > Alan Modra

-- 
Alan Modra

From robot@translationproject.org  Wed Jun 17 20:52:13 2026
From: robot@translationproject.org (Translation Project Robot)
Date: Wed, 17 Jun 2026 22:52:13 +0200
Subject: New German PO file for 'ld' (version 2.45.90)
Message-ID: <E1wZxF7-000pTN-38@duik.vrijschrift.org>

Hello, gentle maintainer.

This is a message from the Translation Project robot.

A revised PO file for textual domain 'ld' has been submitted
by the German team of translators.  The file is available at:

    https://translationproject.org/latest/ld/de.po

(We can arrange things so that in the future such files are automatically
e-mailed to you when they arrive.  Ask at the address below if you want this.)

All other PO files for your package are available in:

    https://translationproject.org/latest/ld/

Please consider including all of these in your next release, whether
official or a pretest.

Whenever you have a new distribution with a new version number ready,
containing a newer POT file, please send the URL of that distribution
tarball to the address below.  The tarball may be just a pretest or a
snapshot, it does not even have to compile.  It is just used by the
translators when they need some extra translation context.

The following HTML page has been updated:

    https://translationproject.org/domain/ld.html

If any question arises, please contact the translation coordinator.

Thank you for all your work,

                                The Translation Project robot, in the
                                name of your translation coordinator.
                                <coordinator@translationproject.org>


From amodra@gmail.com  Wed Jun 17 23:54:04 2026
From: amodra@gmail.com (Alan Modra)
Date: Thu, 18 Jun 2026 09:24:04 +0930
Subject: mep disassembler buffer overflow
Message-ID: <ajMznI_E0S-ZgZIc@squeak.grove.modra.org>

mep_examine_vliw64_insns uses a buffer of size 4 to read 8 bytes.
Fix that, and tidy other places obscuring the code by using a macro to
size buffers.

cpu/
	* mep.opc (mep_print_vliw_insns): Delete commented out insnbuf.
	(mep_examine_vliw32_insns): Don't use CGEN_MAX_INSN_SIZE in
	buf size.  Set buflength using sizeof.  Delete comment.
	(mep_examine_vliw64_insns): Likewise.
	(mep_examine_ivc2_insns): Likewise.
opcodes/
	* mep-dis.c: Regenerate.

diff --git a/cpu/mep.opc b/cpu/mep.opc
index 33dd63b4b9d..032906cadf6 100644
--- a/cpu/mep.opc
+++ b/cpu/mep.opc
@@ -937,7 +937,6 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
 {
   int i;
   int status = 0;
-  /* char insnbuf[CGEN_MAX_INSN_SIZE]; */
   bfd_byte insnbuf[64];
 
   /* If corelength > 0 then there is a core insn present. It
@@ -1100,7 +1099,7 @@ mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
   int corebuflength;
   int cop1buflength;
   int cop2buflength;
-  bfd_byte buf[CGEN_MAX_INSN_SIZE];
+  bfd_byte buf[4];
   char indicator16[1];
   char indicatorcop32[2];
 
@@ -1109,7 +1108,7 @@ mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
   cop2buflength = 0;
 
   /* Read in 32 bits.  */
-  buflength = 4; /* VLIW insn spans 4 bytes.  */
+  buflength = sizeof (buf);
   status = (*info->read_memory_func) (pc, buf, buflength, info);
 
   if (status != 0)
@@ -1175,7 +1174,7 @@ mep_examine_vliw64_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
   int corebuflength;
   int cop1buflength;
   int cop2buflength;
-  bfd_byte buf[CGEN_MAX_INSN_SIZE];
+  bfd_byte buf[8];
   char indicator16[1];
   char indicator64[4];
 
@@ -1184,7 +1183,7 @@ mep_examine_vliw64_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
   cop2buflength = 0;
 
   /* Read in 64 bits.  */
-  buflength = 8; /* VLIW insn spans 8 bytes.  */
+  buflength = sizeof (buf);
   status = (*info->read_memory_func) (pc, buf, buflength, info);
 
   if (status != 0)
@@ -1341,7 +1340,7 @@ mep_examine_ivc2_insns (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_
   int e;
 
   /* Read in 64 bits.  */
-  buflength = 8; /* VLIW insn spans 8 bytes.  */
+  buflength = sizeof (buf);
   status = (*info->read_memory_func) (pc, buf, buflength, info);
 
   if (status != 0)
diff --git a/opcodes/mep-dis.c b/opcodes/mep-dis.c
index b18454d6156..864511aeca9 100644
--- a/opcodes/mep-dis.c
+++ b/opcodes/mep-dis.c
@@ -132,7 +132,6 @@ mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info,
 {
   int i;
   int status = 0;
-  /* char insnbuf[CGEN_MAX_INSN_SIZE]; */
   bfd_byte insnbuf[64];
 
   /* If corelength > 0 then there is a core insn present. It
@@ -295,7 +294,7 @@ mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
   int corebuflength;
   int cop1buflength;
   int cop2buflength;
-  bfd_byte buf[CGEN_MAX_INSN_SIZE];
+  bfd_byte buf[4];
   char indicator16[1];
   char indicatorcop32[2];
 
@@ -304,7 +303,7 @@ mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
   cop2buflength = 0;
 
   /* Read in 32 bits.  */
-  buflength = 4; /* VLIW insn spans 4 bytes.  */
+  buflength = sizeof (buf);
   status = (*info->read_memory_func) (pc, buf, buflength, info);
 
   if (status != 0)
@@ -370,7 +369,7 @@ mep_examine_vliw64_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
   int corebuflength;
   int cop1buflength;
   int cop2buflength;
-  bfd_byte buf[CGEN_MAX_INSN_SIZE];
+  bfd_byte buf[8];
   char indicator16[1];
   char indicator64[4];
 
@@ -379,7 +378,7 @@ mep_examine_vliw64_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
   cop2buflength = 0;
 
   /* Read in 64 bits.  */
-  buflength = 8; /* VLIW insn spans 8 bytes.  */
+  buflength = sizeof (buf);
   status = (*info->read_memory_func) (pc, buf, buflength, info);
 
   if (status != 0)
@@ -536,7 +535,7 @@ mep_examine_ivc2_insns (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_
   int e;
 
   /* Read in 64 bits.  */
-  buflength = 8; /* VLIW insn spans 8 bytes.  */
+  buflength = sizeof (buf);
   status = (*info->read_memory_func) (pc, buf, buflength, info);
 
   if (status != 0)

-- 
Alan Modra

From amodra@gmail.com  Wed Jun 17 23:54:28 2026
From: amodra@gmail.com (Alan Modra)
Date: Thu, 18 Jun 2026 09:24:28 +0930
Subject: move _bfd_mul_overflow from libbfd.h to bfd.h
Message-ID: <ajMztGlTpwdV1R3a@squeak.grove.modra.org>

Replace gas_mul_overflow with _bfd_mul_overflow, and don't include
libbfd.h outside of bfd/.

bfd/
	* libbfd-in.h (_bfd_mul_overflow, _bfd_constant_p): Move to..
	* bfd-in.h: ..here.  Include inttypes.h earlier.
	* libbfd.h: Regenerate.
	* bfd-in2.h: Regenerate.
gas/
	* as.h (gas_mul_overflow): Don't define.
	* read.c (do_repeat, s_space): Replace gas_mul_overflow with
	_bfd_mul_overflow.
	* symbols.c (notes_calloc): Likewise.
ld/
	* emultempl/nto.em: Don't include libbfd.h.
	* ldlang.c: Likewise.
	* pdb.c: Likewise.
opcodes/
	* kvx-opc.c: Don't include libbfd.h.

diff --git a/bfd/bfd-in.h b/bfd/bfd-in.h
index 3d15132b956..5cac762fb4f 100644
--- a/bfd/bfd-in.h
+++ b/bfd/bfd-in.h
@@ -41,6 +41,7 @@ extern "C" {
 #include <stdarg.h>
 #include <string.h>
 #include <sys/stat.h>
+#include <inttypes.h>
 
 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 #ifndef SABER
@@ -70,12 +71,24 @@ extern "C" {
 /* The word size of the default bfd target.  */
 #define BFD_DEFAULT_TARGET_SIZE @bfd_default_target_size@
 
-#include <inttypes.h>
-
 #if BFD_ARCH_SIZE >= 64
 #define BFD64
 #endif
 
+#if GCC_VERSION >= 7000
+#define _bfd_mul_overflow(a, b, res) __builtin_mul_overflow (a, b, res)
+#else
+/* Assumes unsigned values.  Careful!  Args evaluated multiple times.  */
+#define _bfd_mul_overflow(a, b, res) \
+  ((*res) = (a), (*res) *= (b), (b) != 0 && (*res) / (b) != (a))
+#endif
+
+#ifdef __GNUC__
+#define _bfd_constant_p(v) __builtin_constant_p (v)
+#else
+#define _bfd_constant_p(v) 0
+#endif
+
 /* Silence "applying zero offset to null pointer" UBSAN warnings.  */
 #define PTR_ADD(P,A) ((A) != 0 ? (P) + (A) : (P))
 /* Also prevent non-zero offsets from being applied to a null pointer.  */
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index c019a5accd4..e49d67316f3 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -48,6 +48,7 @@ extern "C" {
 #include <stdarg.h>
 #include <string.h>
 #include <sys/stat.h>
+#include <inttypes.h>
 
 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
 #ifndef SABER
@@ -77,12 +78,24 @@ extern "C" {
 /* The word size of the default bfd target.  */
 #define BFD_DEFAULT_TARGET_SIZE @bfd_default_target_size@
 
-#include <inttypes.h>
-
 #if BFD_ARCH_SIZE >= 64
 #define BFD64
 #endif
 
+#if GCC_VERSION >= 7000
+#define _bfd_mul_overflow(a, b, res) __builtin_mul_overflow (a, b, res)
+#else
+/* Assumes unsigned values.  Careful!  Args evaluated multiple times.  */
+#define _bfd_mul_overflow(a, b, res) \
+  ((*res) = (a), (*res) *= (b), (b) != 0 && (*res) / (b) != (a))
+#endif
+
+#ifdef __GNUC__
+#define _bfd_constant_p(v) __builtin_constant_p (v)
+#else
+#define _bfd_constant_p(v) 0
+#endif
+
 /* Silence "applying zero offset to null pointer" UBSAN warnings.  */
 #define PTR_ADD(P,A) ((A) != 0 ? (P) + (A) : (P))
 /* Also prevent non-zero offsets from being applied to a null pointer.  */
diff --git a/bfd/libbfd-in.h b/bfd/libbfd-in.h
index 7b4c93228a7..e7ec6bfa9a0 100644
--- a/bfd/libbfd-in.h
+++ b/bfd/libbfd-in.h
@@ -840,20 +840,6 @@ extern uintptr_t _bfd_pagesize_m1 ATTRIBUTE_HIDDEN;
 extern uintptr_t _bfd_minimum_mmap_size ATTRIBUTE_HIDDEN;
 #endif
 
-#if GCC_VERSION >= 7000
-#define _bfd_mul_overflow(a, b, res) __builtin_mul_overflow (a, b, res)
-#else
-/* Assumes unsigned values.  Careful!  Args evaluated multiple times.  */
-#define _bfd_mul_overflow(a, b, res) \
-  ((*res) = (a), (*res) *= (b), (b) != 0 && (*res) / (b) != (a))
-#endif
-
-#ifdef __GNUC__
-#define _bfd_constant_p(v) __builtin_constant_p (v)
-#else
-#define _bfd_constant_p(v) 0
-#endif
-
 static inline void *
 _bfd_alloc_and_read (bfd *abfd, bfd_size_type asize, bfd_size_type rsize)
 {
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index 3d19b597b71..27bc0875cf6 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -846,20 +846,6 @@ extern uintptr_t _bfd_pagesize_m1 ATTRIBUTE_HIDDEN;
 extern uintptr_t _bfd_minimum_mmap_size ATTRIBUTE_HIDDEN;
 #endif
 
-#if GCC_VERSION >= 7000
-#define _bfd_mul_overflow(a, b, res) __builtin_mul_overflow (a, b, res)
-#else
-/* Assumes unsigned values.  Careful!  Args evaluated multiple times.  */
-#define _bfd_mul_overflow(a, b, res) \
-  ((*res) = (a), (*res) *= (b), (b) != 0 && (*res) / (b) != (a))
-#endif
-
-#ifdef __GNUC__
-#define _bfd_constant_p(v) __builtin_constant_p (v)
-#else
-#define _bfd_constant_p(v) 0
-#endif
-
 static inline void *
 _bfd_alloc_and_read (bfd *abfd, bfd_size_type asize, bfd_size_type rsize)
 {
diff --git a/gas/as.h b/gas/as.h
index f0fbf38adee..94bc816be1e 100644
--- a/gas/as.h
+++ b/gas/as.h
@@ -119,14 +119,6 @@ void *mempcpy(void *, const void *, size_t);
 
 #define xfree free
 
-#if GCC_VERSION >= 7000
-#define gas_mul_overflow(a, b, res) __builtin_mul_overflow (a, b, res)
-#else
-/* Assumes unsigned values.  Careful!  Args evaluated multiple times.  */
-#define gas_mul_overflow(a, b, res) \
-  ((*res) = (a), (*res) *= (b), (b) != 0 && (*res) / (b) != (a))
-#endif
-
 #include "asintl.h"
 
 #define BAD_CASE(val)							    \
diff --git a/gas/read.c b/gas/read.c
index 5b6a3c115a0..56bd222acf0 100644
--- a/gas/read.c
+++ b/gas/read.c
@@ -3222,7 +3222,7 @@ do_repeat (size_t count, const char *start, const char *end,
   sb_terminate (&one);
 
   limit = (size_t) LONG_MAX < 0xffffffff ? (size_t) LONG_MAX : 0xffffffff;
-  if (gas_mul_overflow (count, one.len, &total) || total > limit)
+  if (_bfd_mul_overflow (count, one.len, &total) || total > limit)
     {
       as_bad_where (file, line,
 		    _("excessive count %zu for %s - ignored"), count, start);
@@ -3580,7 +3580,7 @@ s_space (int mult)
 	    }
 	  if ((unsigned int) mult <= 1)
 	    total = repeat;
-	  else if (gas_mul_overflow (repeat, mult, &total)
+	  else if (_bfd_mul_overflow (repeat, mult, &total)
 		   || (offsetT) total < 0)
 	    {
 	      as_warn (_(".space repeat count overflow, ignored"));
diff --git a/gas/symbols.c b/gas/symbols.c
index 3fc0a97927c..02df923d128 100644
--- a/gas/symbols.c
+++ b/gas/symbols.c
@@ -259,7 +259,7 @@ notes_calloc (size_t n, size_t size)
 {
   size_t amt;
   void *ret;
-  if (gas_mul_overflow (n, size, &amt))
+  if (_bfd_mul_overflow (n, size, &amt))
     {
       obstack_alloc_failed_handler ();
       abort ();
diff --git a/ld/emultempl/nto.em b/ld/emultempl/nto.em
index 7af2bef0e21..e5b47a9a94f 100644
--- a/ld/emultempl/nto.em
+++ b/ld/emultempl/nto.em
@@ -29,7 +29,6 @@ cat >>e${EMULATION_NAME}.c <<EOF
 #include "elf/internal.h"
 #include "elf/common.h"
 #include "elf-bfd.h"
-#include "../bfd/libbfd.h"
 
 bool nto_lazy_stack = false;
 struct nto_stack_note
diff --git a/ld/ldlang.c b/ld/ldlang.c
index 48dd33a49bb..b04ba113aaa 100644
--- a/ld/ldlang.c
+++ b/ld/ldlang.c
@@ -21,7 +21,6 @@
 #include "sysdep.h"
 #include <limits.h>
 #include "bfd.h"
-#include "libbfd.h"
 #include "libiberty.h"
 #include "filenames.h"
 #include "safe-ctype.h"
diff --git a/ld/pdb.c b/ld/pdb.c
index c0ac50b323d..673d041ce2e 100644
--- a/ld/pdb.c
+++ b/ld/pdb.c
@@ -23,7 +23,6 @@
 #include "ld.h"
 #include "ldmain.h"
 #include "ldmisc.h"
-#include "libbfd.h"
 #include "libiberty.h"
 #include "coff/i386.h"
 #include "coff/external.h"
diff --git a/opcodes/kvx-opc.c b/opcodes/kvx-opc.c
index e6504924094..bd74b90670f 100644
--- a/opcodes/kvx-opc.c
+++ b/opcodes/kvx-opc.c
@@ -22,7 +22,6 @@
 #include <stddef.h>
 #include <stdio.h>
 #include "bfd.h"
-#include "libbfd.h"
 #include <elf/kvx.h>
 #include <opcode/kvx.h>
 

-- 
Alan Modra

From amodra@gmail.com  Wed Jun 17 23:55:26 2026
From: amodra@gmail.com (Alan Modra)
Date: Thu, 18 Jun 2026 09:25:26 +0930
Subject: buffer_read_memory hardening
Message-ID: <ajMz7izBu9fnpXhi@squeak.grove.modra.org>

What drew my attention here was wondering if division of the buffer
length or the requested length by octets_per_byte could result in
trucation and thus an incomplete check for possible buffer overflow.
Rather than convincing myself that this couldn't happen, I decided to
rewrite the checks in a way that avoids the possibility of truncation,
and avoids any addition overflows too.

	* dis-buf.c (buffer_read_memory): Rewrite buffer overflow
	sanity checks.

diff --git a/opcodes/dis-buf.c b/opcodes/dis-buf.c
index 83fce0a2fc3..504d0b37b98 100644
--- a/opcodes/dis-buf.c
+++ b/opcodes/dis-buf.c
@@ -32,18 +32,19 @@ buffer_read_memory (bfd_vma memaddr,
 		    struct disassemble_info *info)
 {
   unsigned int opb = info->octets_per_byte;
-  size_t end_addr_offset = length / opb;
-  size_t max_addr_offset = info->buffer_length / opb;
-  size_t octets = (memaddr - info->buffer_vma) * opb;
+  size_t addr_off, to_stop;
 
   if (memaddr < info->buffer_vma
-      || memaddr - info->buffer_vma > max_addr_offset
-      || memaddr - info->buffer_vma + end_addr_offset > max_addr_offset
-      || (info->stop_vma && (memaddr >= info->stop_vma
-			     || memaddr + end_addr_offset > info->stop_vma)))
+      || _bfd_mul_overflow (memaddr - info->buffer_vma, opb, &addr_off)
+      || addr_off > info->buffer_length
+      || length > info->buffer_length - addr_off
+      || (info->stop_vma
+	  && (memaddr >= info->stop_vma
+	      || _bfd_mul_overflow (info->stop_vma - memaddr, opb, &to_stop)
+	      || length > to_stop)))
     /* Out of bounds.  Use EIO because GDB uses it.  */
     return EIO;
-  memcpy (myaddr, info->buffer + octets, length);
+  memcpy (myaddr, info->buffer + addr_off, length);
 
   return 0;
 }

-- 
Alan Modra

From amodra@gmail.com  Wed Jun 17 23:56:20 2026
From: amodra@gmail.com (Alan Modra)
Date: Thu, 18 Jun 2026 09:26:20 +0930
Subject: elflink.c: remove unnecessary casts
Message-ID: <ajM0JFFTrcuYy6JA@squeak.grove.modra.org>

I noticed when going through elflink.c looking for places where memory
allocation function return values weren't checked, that many places
still have the now unnecessary casts from K&R days.  This patch
removes them, and tidies some places that don't need to use a variable
to pass the size.

diff --git a/bfd/elflink.c b/bfd/elflink.c
index 290fc5f2031..0af9837a28c 100644
--- a/bfd/elflink.c
+++ b/bfd/elflink.c
@@ -856,7 +856,6 @@ bfd_elf_link_record_local_dynamic_symbol (struct bfd_link_info *info,
 					  bfd *input_bfd,
 					  long input_indx)
 {
-  size_t amt;
   struct elf_link_local_dynamic_entry *entry;
   struct elf_link_hash_table *eht;
   struct elf_strtab_hash *dynstr;
@@ -873,8 +872,7 @@ bfd_elf_link_record_local_dynamic_symbol (struct bfd_link_info *info,
     if (entry->input_bfd == input_bfd && entry->input_indx == input_indx)
       return 1;
 
-  amt = sizeof (*entry);
-  entry = (struct elf_link_local_dynamic_entry *) bfd_alloc (input_bfd, amt);
+  entry = bfd_alloc (input_bfd, sizeof (*entry));
   if (entry == NULL)
     return 0;
 
@@ -959,7 +957,7 @@ static bool
 elf_link_renumber_hash_table_dynsyms (struct elf_link_hash_entry *h,
 				      void *data)
 {
-  size_t *count = (size_t *) data;
+  size_t *count = data;
 
   if (h->forced_local)
     return true;
@@ -978,7 +976,7 @@ static bool
 elf_link_renumber_local_hash_table_dynsyms (struct elf_link_hash_entry *h,
 					    void *data)
 {
-  size_t *count = (size_t *) data;
+  size_t *count = data;
 
   if (!h->forced_local)
     return true;
@@ -2019,7 +2017,7 @@ _bfd_elf_add_default_symbol (bfd *abfd,
   dynamic = (abfd->flags & DYNAMIC) != 0;
 
   shortlen = p - name;
-  shortname = (char *) bfd_hash_allocate (&info->hash->table, shortlen + 1);
+  shortname = bfd_hash_allocate (&info->hash->table, shortlen + 1);
   if (shortname == NULL)
     return false;
   memcpy (shortname, name, shortlen);
@@ -2183,7 +2181,7 @@ _bfd_elf_add_default_symbol (bfd *abfd,
 
  nondefault:
   len = strlen (name);
-  shortname = (char *) bfd_hash_allocate (&info->hash->table, len);
+  shortname = bfd_hash_allocate (&info->hash->table, len);
   if (shortname == NULL)
     return false;
   memcpy (shortname, name, shortlen);
@@ -2283,7 +2281,7 @@ _bfd_elf_add_default_symbol (bfd *abfd,
 static bool
 _bfd_elf_export_symbol (struct elf_link_hash_entry *h, void *data)
 {
-  struct elf_info_failed *eif = (struct elf_info_failed *) data;
+  struct elf_info_failed *eif = data;
 
   /* Ignore indirect symbols.  These are added by the versioning code.  */
   if (h->root.type == bfd_link_hash_indirect)
@@ -2323,7 +2321,6 @@ elf_link_add_glibc_verneed (struct elf_find_verdep_info *rinfo,
 {
   Elf_Internal_Verneed *t;
   Elf_Internal_Vernaux *a;
-  size_t amt;
   int minor_version = -1;
   bool added = false;
   bool glibc = false;
@@ -2397,8 +2394,7 @@ elf_link_add_glibc_verneed (struct elf_find_verdep_info *rinfo,
 	goto update_auto_version_and_return;
     }
 
-  amt = sizeof *a;
-  a = (Elf_Internal_Vernaux *) bfd_zalloc (rinfo->info->output_bfd, amt);
+  a = bfd_zalloc (rinfo->info->output_bfd, sizeof (*a));
   if (a == NULL)
     {
       rinfo->failed = true;
@@ -2474,10 +2470,9 @@ static bool
 _bfd_elf_link_find_version_dependencies (struct elf_link_hash_entry *h,
 					 void *data)
 {
-  struct elf_find_verdep_info *rinfo = (struct elf_find_verdep_info *) data;
+  struct elf_find_verdep_info *rinfo = data;
   Elf_Internal_Verneed *t;
   Elf_Internal_Vernaux *a;
-  size_t amt;
 
   /* We only care about symbols defined in shared objects with version
      information.  */
@@ -2508,8 +2503,7 @@ _bfd_elf_link_find_version_dependencies (struct elf_link_hash_entry *h,
 
   if (t == NULL)
     {
-      amt = sizeof *t;
-      t = (Elf_Internal_Verneed *) bfd_zalloc (rinfo->info->output_bfd, amt);
+      t = bfd_zalloc (rinfo->info->output_bfd, sizeof (*t));
       if (t == NULL)
 	{
 	  rinfo->failed = true;
@@ -2521,8 +2515,7 @@ _bfd_elf_link_find_version_dependencies (struct elf_link_hash_entry *h,
       elf_tdata (rinfo->info->output_bfd)->verref = t;
     }
 
-  amt = sizeof *a;
-  a = (Elf_Internal_Vernaux *) bfd_zalloc (rinfo->info->output_bfd, amt);
+  a = bfd_zalloc (rinfo->info->output_bfd, sizeof (*a));
   if (a == NULL)
     {
       rinfo->failed = true;
@@ -2570,7 +2563,7 @@ _bfd_elf_link_hide_versioned_symbol (struct bfd_link_info *info,
 	  struct bfd_elf_version_expr *d;
 
 	  len = version_p - h->root.root.string;
-	  alc = (char *) bfd_malloc (len);
+	  alc = bfd_malloc (len);
 	  if (alc == NULL)
 	    return false;
 	  memcpy (alc, h->root.root.string, len - 1);
@@ -2664,16 +2657,13 @@ _bfd_elf_link_hide_sym_by_version (struct bfd_link_info *info,
 static bool
 _bfd_elf_link_assign_sym_version (struct elf_link_hash_entry *h, void *data)
 {
-  struct elf_info_failed *sinfo;
-  struct bfd_link_info *info;
+  struct elf_info_failed *sinfo = data;
+  struct bfd_link_info *info = sinfo->info;
   elf_backend_data *obed;
   struct elf_info_failed eif;
   const char *p;
   bool hide;
 
-  sinfo = (struct elf_info_failed *) data;
-  info = sinfo->info;
-
   /* Fix the symbol flags.  */
   eif.failed = false;
   eif.info = info;
@@ -2733,8 +2723,7 @@ _bfd_elf_link_assign_sym_version (struct elf_link_hash_entry *h, void *data)
 	  if (h->dynindx == -1)
 	    return true;
 
-	  t = (struct bfd_elf_version_tree *) bfd_zalloc (info->output_bfd,
-							  sizeof *t);
+	  t = bfd_zalloc (info->output_bfd, sizeof (*t));
 	  if (t == NULL)
 	    {
 	      sinfo->failed = true;
@@ -2931,7 +2920,7 @@ _bfd_elf_link_info_read_relocs (bfd *abfd,
       size = (bfd_size_type) o->reloc_count * sizeof (Elf_Internal_Rela);
       if (keep_memory && info)
 	info->cache_size += size;
-      internal_relocs = alloc2 = (Elf_Internal_Rela *) bfd_malloc (size);
+      internal_relocs = alloc2 = bfd_malloc (size);
       if (internal_relocs == NULL)
 	return NULL;
     }
@@ -3279,7 +3268,7 @@ _bfd_elf_fix_symbol_flags (struct elf_link_hash_entry *h,
 static bool
 _bfd_elf_adjust_dynamic_symbol (struct elf_link_hash_entry *h, void *data)
 {
-  struct elf_info_failed *eif = (struct elf_info_failed *) data;
+  struct elf_info_failed *eif = data;
   struct elf_link_hash_table *htab;
   elf_backend_data *obed;
 
@@ -3474,7 +3463,7 @@ _bfd_elf_link_sec_merge_syms (struct elf_link_hash_entry *h, void *data)
       && ((sec = h->root.u.def.section)->flags & SEC_MERGE)
       && sec->sec_info_type == SEC_INFO_TYPE_MERGE)
     {
-      bfd *output_bfd = (bfd *) data;
+      bfd *output_bfd = data;
 
       h->root.u.def.value =
 	_bfd_merged_section_offset (output_bfd,
@@ -3824,7 +3813,7 @@ _bfd_elf_add_dynamic_entry (struct bfd_link_info *info,
   BFD_ASSERT (s != NULL);
 
   newsize = s->size + obed->s->sizeof_dyn;
-  newcontents = (bfd_byte *) bfd_realloc (s->contents, newsize);
+  newcontents = bfd_realloc (s->contents, newsize);
   if (newcontents == NULL)
     return false;
 
@@ -4076,7 +4065,7 @@ elf_sort_symbol (const void *arg1, const void *arg2)
 static bool
 elf_adjust_dynstr_offsets (struct elf_link_hash_entry *h, void *data)
 {
-  struct elf_strtab_hash *dynstr = (struct elf_strtab_hash *) data;
+  struct elf_strtab_hash *dynstr = data;
 
   if (h->dynindx != -1)
     h->dynstr_index = _bfd_elf_strtab_offset (dynstr, h->dynstr_index);
@@ -4374,9 +4363,7 @@ elf_link_first_hash_newfunc (struct bfd_hash_entry *entry,
   /* Allocate the structure if it has not already been allocated by a
      subclass.  */
   if (ret == NULL)
-    ret = (struct elf_link_first_hash_entry *)
-	bfd_hash_allocate (table,
-			   sizeof (struct elf_link_first_hash_entry));
+    ret = bfd_hash_allocate (table, sizeof (struct elf_link_first_hash_entry));
   if (ret == NULL)
     return NULL;
 
@@ -4468,8 +4455,7 @@ elf_link_add_object_symbols (bfd *abfd, struct bfd_link_info *info)
 	  && htab->first_hash == NULL)
 	{
 	  /* Initialize first_hash for an IR input.  */
-	  htab->first_hash = (struct bfd_hash_table *)
-	    bfd_malloc (sizeof (struct bfd_hash_table));
+	  htab->first_hash = bfd_malloc (sizeof (struct bfd_hash_table));
 	  if (htab->first_hash == NULL
 	      || !bfd_hash_table_init
 		   (htab->first_hash, elf_link_first_hash_newfunc,
@@ -4549,7 +4535,7 @@ elf_link_add_object_symbols (bfd *abfd, struct bfd_link_info *info)
 	    }
 
 	  sz = s->size;
-	  msg = (char *) bfd_alloc (abfd, sz + 1);
+	  msg = bfd_alloc (abfd, sz + 1);
 	  if (msg == NULL)
 	    goto error_return;
 
@@ -4667,14 +4653,14 @@ elf_link_add_object_symbols (bfd *abfd, struct bfd_link_info *info)
 		  struct bfd_link_needed_list *n, **pn;
 		  char *fnm, *anm;
 		  unsigned int tagv = dyn.d_un.d_val;
-		  size_t amt = sizeof (struct bfd_link_needed_list);
+		  size_t amt;
 
-		  n = (struct bfd_link_needed_list *) bfd_alloc (abfd, amt);
+		  n = bfd_alloc (abfd, sizeof (*n));
 		  fnm = bfd_elf_string_from_elf_section (abfd, shlink, tagv);
 		  if (n == NULL || fnm == NULL)
 		    goto error_free_dyn;
 		  amt = strlen (fnm) + 1;
-		  anm = (char *) bfd_alloc (abfd, amt);
+		  anm = bfd_alloc (abfd, amt);
 		  if (anm == NULL)
 		    goto error_free_dyn;
 		  memcpy (anm, fnm, amt);
@@ -4690,14 +4676,14 @@ elf_link_add_object_symbols (bfd *abfd, struct bfd_link_info *info)
 		  struct bfd_link_needed_list *n, **pn;
 		  char *fnm, *anm;
 		  unsigned int tagv = dyn.d_un.d_val;
-		  size_t amt = sizeof (struct bfd_link_needed_list);
+		  size_t amt;
 
-		  n = (struct bfd_link_needed_list *) bfd_alloc (abfd, amt);
+		  n = bfd_alloc (abfd, sizeof (*n));
 		  fnm = bfd_elf_string_from_elf_section (abfd, shlink, tagv);
 		  if (n == NULL || fnm == NULL)
 		    goto error_free_dyn;
 		  amt = strlen (fnm) + 1;
-		  anm = (char *) bfd_alloc (abfd, amt);
+		  anm = bfd_alloc (abfd, amt);
 		  if (anm == NULL)
 		    goto error_free_dyn;
 		  memcpy (anm, fnm, amt);
@@ -4716,14 +4702,14 @@ elf_link_add_object_symbols (bfd *abfd, struct bfd_link_info *info)
 		  struct bfd_link_needed_list *n, **pn;
 		  char *fnm, *anm;
 		  unsigned int tagv = dyn.d_un.d_val;
-		  size_t amt = sizeof (struct bfd_link_needed_list);
+		  size_t amt;
 
-		  n = (struct bfd_link_needed_list *) bfd_alloc (abfd, amt);
+		  n = bfd_alloc (abfd, sizeof (*n));
 		  fnm = bfd_elf_string_from_elf_section (abfd, shlink, tagv);
 		  if (n == NULL || fnm == NULL)
 		    goto error_free_dyn;
 		  amt = strlen (fnm) + 1;
-		  anm = (char *) bfd_alloc (abfd, amt);
+		  anm = bfd_alloc (abfd, amt);
 		  if (anm == NULL)
 		    goto error_free_dyn;
 		  memcpy (anm, fnm, amt);
@@ -4887,8 +4873,7 @@ elf_link_add_object_symbols (bfd *abfd, struct bfd_link_info *info)
 
 	  if (bfd_seek (abfd, versymhdr->sh_offset, SEEK_SET) != 0)
 	    goto error_free_sym;
-	  extversym = (Elf_External_Versym *)
-	    _bfd_malloc_and_read (abfd, amt, amt);
+	  extversym = _bfd_malloc_and_read (abfd, amt, amt);
 	  if (extversym == NULL)
 	    goto error_free_sym;
 	  extversym_end = extversym + amt / sizeof (*extversym);
@@ -5303,7 +5288,7 @@ elf_link_add_object_symbols (bfd *abfd, struct bfd_link_info *info)
 		  && isym->st_shndx != SHN_UNDEF)
 		++newlen;
 
-	      newname = (char *) bfd_hash_allocate (&htab->root.table, newlen);
+	      newname = bfd_hash_allocate (&htab->root.table, newlen);
 	      if (newname == NULL)
 		goto error_free_vers;
 	      memcpy (newname, name, namelen);
@@ -5683,10 +5668,8 @@ elf_link_add_object_symbols (bfd *abfd, struct bfd_link_info *info)
 		     aliases can be checked.  */
 		  if (!nondeflt_vers)
 		    {
-		      size_t amt = ((isymend - isym + 1)
-				    * sizeof (struct elf_link_hash_entry *));
-		      nondeflt_vers
-			= (struct elf_link_hash_entry **) bfd_malloc (amt);
+		      nondeflt_vers = bfd_malloc ((isymend - isym + 1)
+						  * sizeof (*nondeflt_vers));
 		      if (!nondeflt_vers)
 			goto error_free_vers;
 		    }
@@ -5937,7 +5920,7 @@ elf_link_add_object_symbols (bfd *abfd, struct bfd_link_info *info)
 	    continue;
 
 	  amt = p - h->root.root.string;
-	  shortname = (char *) bfd_malloc (amt + 1);
+	  shortname = bfd_malloc (amt + 1);
 	  if (!shortname)
 	    goto error_free_vers;
 	  memcpy (shortname, h->root.root.string, amt);
@@ -5989,13 +5972,12 @@ elf_link_add_object_symbols (bfd *abfd, struct bfd_link_info *info)
       struct elf_link_hash_entry **hppend;
       struct elf_link_hash_entry **sorted_sym_hash;
       struct elf_link_hash_entry *h;
-      size_t sym_count, amt;
+      size_t sym_count;
 
       /* Since we have to search the whole symbol list for each weak
 	 defined symbol, search time for N weak defined symbols will be
 	 O(N^2). Binary search will cut it down to O(NlogN).  */
-      amt = extsymcount * sizeof (*sorted_sym_hash);
-      sorted_sym_hash = bfd_malloc (amt);
+      sorted_sym_hash = bfd_malloc (extsymcount * sizeof (*sorted_sym_hash));
       if (sorted_sym_hash == NULL)
 	goto error_return;
       sym_hash = sorted_sym_hash;
@@ -6166,7 +6148,7 @@ elf_link_add_object_symbols (bfd *abfd, struct bfd_link_info *info)
       /* Add this bfd to the loaded list.  */
       struct elf_link_loaded_list *n;
 
-      n = (struct elf_link_loaded_list *) bfd_alloc (abfd, sizeof (*n));
+      n = bfd_alloc (abfd, sizeof (*n));
       if (n == NULL)
 	goto error_return;
       n->abfd = abfd;
@@ -6224,7 +6206,7 @@ _bfd_elf_archive_symbol_lookup (bfd *abfd,
 
   /* First check with only one `@'.  */
   len = strlen (name);
-  copy = (char *) bfd_alloc (abfd, len);
+  copy = bfd_alloc (abfd, len);
   if (copy == NULL)
     return (struct bfd_link_hash_entry *) -1;
 
@@ -6265,7 +6247,6 @@ elf_link_add_archive_symbols (bfd *abfd, struct bfd_link_info *info)
   unsigned char *included = NULL;
   carsym *symdefs;
   bool loop;
-  size_t amt;
   elf_backend_data *bed;
   struct bfd_link_hash_entry * (*archive_symbol_lookup)
     (bfd *, struct bfd_link_info *, const char *);
@@ -6288,8 +6269,7 @@ elf_link_add_archive_symbols (bfd *abfd, struct bfd_link_info *info)
   c = bfd_ardata (abfd)->symdef_count;
   if (c == 0)
     return true;
-  amt = c * sizeof (*included);
-  included = (unsigned char *) bfd_zmalloc (amt);
+  included = bfd_zmalloc (c * sizeof (*included));
   if (included == NULL)
     return false;
 
@@ -6485,7 +6465,7 @@ struct hash_codes_info
 static bool
 elf_collect_hash_codes (struct elf_link_hash_entry *h, void *data)
 {
-  struct hash_codes_info *inf = (struct hash_codes_info *) data;
+  struct hash_codes_info *inf = data;
   const char *name;
   unsigned long ha;
   char *alc = NULL;
@@ -6500,7 +6480,7 @@ elf_collect_hash_codes (struct elf_link_hash_entry *h, void *data)
       const char *p = strchr (name, ELF_VER_CHR);
       if (p != NULL)
 	{
-	  alc = (char *) bfd_malloc (p - name + 1);
+	  alc = bfd_malloc (p - name + 1);
 	  if (alc == NULL)
 	    {
 	      inf->error = true;
@@ -6555,7 +6535,7 @@ struct collect_gnu_hash_codes
 static bool
 elf_collect_gnu_hash_codes (struct elf_link_hash_entry *h, void *data)
 {
-  struct collect_gnu_hash_codes *s = (struct collect_gnu_hash_codes *) data;
+  struct collect_gnu_hash_codes *s = data;
   const char *name;
   unsigned long ha;
   char *alc = NULL;
@@ -6574,7 +6554,7 @@ elf_collect_gnu_hash_codes (struct elf_link_hash_entry *h, void *data)
       const char *p = strchr (name, ELF_VER_CHR);
       if (p != NULL)
 	{
-	  alc = (char *) bfd_malloc (p - name + 1);
+	  alc = bfd_malloc (p - name + 1);
 	  if (alc == NULL)
 	    {
 	      s->error = true;
@@ -6609,7 +6589,7 @@ elf_collect_gnu_hash_codes (struct elf_link_hash_entry *h, void *data)
 static bool
 elf_gnu_hash_process_symidx (struct elf_link_hash_entry *h, void *data)
 {
-  struct collect_gnu_hash_codes *s = (struct collect_gnu_hash_codes *) data;
+  struct collect_gnu_hash_codes *s = data;
   unsigned long int bucket;
   unsigned long int val;
 
@@ -6712,7 +6692,6 @@ compute_bucket_count (struct bfd_link_info *info ATTRIBUTE_UNUSED,
       size_t dynsymcount = elf_hash_table (info)->dynsymcount;
       elf_backend_data *obed = get_elf_backend_data (dynobj);
       unsigned long int *counts;
-      bfd_size_type amt;
       unsigned int no_improvement_count = 0;
 
       /* Possible optimization parameters: if we have NSYMS symbols we say
@@ -6732,9 +6711,7 @@ compute_bucket_count (struct bfd_link_info *info ATTRIBUTE_UNUSED,
 
       /* Create array where we count the collisions in.  We must use bfd_malloc
 	 since the size could be large.  */
-      amt = maxsize;
-      amt *= sizeof (unsigned long int);
-      counts = (unsigned long int *) bfd_malloc (amt);
+      counts = bfd_malloc (maxsize * sizeof (*counts));
       if (counts == NULL)
 	return 0;
 
@@ -6921,9 +6898,8 @@ elf_gc_sweep_symbol (struct elf_link_hash_entry *h, void *data)
 	  || h->root.type == bfd_link_hash_undefined
 	  || h->root.type == bfd_link_hash_undefweak))
     {
-      struct elf_gc_sweep_symbol_info *inf;
+      struct elf_gc_sweep_symbol_info *inf = data;
 
-      inf = (struct elf_gc_sweep_symbol_info *) data;
       (*inf->hide_symbol) (inf->info, h, true);
       h->def_regular = 0;
       h->ref_regular = 0;
@@ -7026,7 +7002,7 @@ bfd_elf_size_dynamic_sections (struct bfd_link_info *info,
 	      verlen = strlen (verstr);
 	      newlen = namelen + verlen + 3;
 
-	      newname = (char *) bfd_malloc (newlen);
+	      newname = bfd_malloc (newlen);
 	      if (newname == NULL)
 		return false;
 	      newname[0] = leading_char;
@@ -7935,7 +7911,7 @@ bfd_elf_size_dynsym_hash_dynstr (struct bfd_link_info *info)
       if ((s->flags & SEC_EXCLUDE) == 0)
 	{
 	  s->size = dynsymcount * sizeof (Elf_External_Versym);
-	  s->contents = (unsigned char *) bfd_zalloc (info->output_bfd, s->size);
+	  s->contents = bfd_zalloc (info->output_bfd, s->size);
 	  if (s->contents == NULL)
 	    return false;
 	  s->alloced = 1;
@@ -7972,7 +7948,6 @@ bfd_elf_size_dynsym_hash_dynstr (struct bfd_link_info *info)
 	{
 	  unsigned long int *hashcodes;
 	  struct hash_codes_info hashinf;
-	  bfd_size_type amt;
 	  unsigned long int nsyms;
 	  size_t bucketcount;
 	  size_t hash_entry_size;
@@ -7980,8 +7955,7 @@ bfd_elf_size_dynsym_hash_dynstr (struct bfd_link_info *info)
 	  /* Compute the hash values for all exported symbols.  At the same
 	     time store the values in an array so that we could use them for
 	     optimizations.  */
-	  amt = dynsymcount * sizeof (unsigned long int);
-	  hashcodes = (unsigned long int *) bfd_malloc (amt);
+	  hashcodes = bfd_malloc (dynsymcount * sizeof (*hashcodes));
 	  if (hashcodes == NULL)
 	    return false;
 	  hashinf.hashcodes = hashcodes;
@@ -8034,8 +8008,8 @@ bfd_elf_size_dynsym_hash_dynstr (struct bfd_link_info *info)
 	  /* Compute the hash values for all exported symbols.  At the same
 	     time store the values in an array so that we could use them for
 	     optimizations.  */
-	  amt = dynsymcount * 2 * sizeof (unsigned long int);
-	  cinfo.hashcodes = (long unsigned int *) bfd_malloc (amt);
+	  amt = dynsymcount * 2 * sizeof (*cinfo.hashcodes);
+	  cinfo.hashcodes = bfd_malloc (amt);
 	  if (cinfo.hashcodes == NULL)
 	    return false;
 
@@ -8119,7 +8093,7 @@ bfd_elf_size_dynsym_hash_dynstr (struct bfd_link_info *info)
 	      maskwords = 1 << (maskbitslog2 - cinfo.shift1);
 	      amt = bucketcount * sizeof (unsigned long int) * 2;
 	      amt += maskwords * sizeof (bfd_vma);
-	      cinfo.bitmask = (bfd_vma *) bfd_malloc (amt);
+	      cinfo.bitmask = bfd_malloc (amt);
 	      if (cinfo.bitmask == NULL)
 		{
 		  free (cinfo.hashcodes);
@@ -8237,8 +8211,7 @@ _bfd_elf_link_hash_newfunc (struct bfd_hash_entry *entry,
      subclass.  */
   if (entry == NULL)
     {
-      entry = (struct bfd_hash_entry *)
-	bfd_hash_allocate (table, sizeof (struct elf_link_hash_entry));
+      entry = bfd_hash_allocate (table, sizeof (struct elf_link_hash_entry));
       if (entry == NULL)
 	return entry;
     }
@@ -8433,9 +8406,8 @@ struct bfd_link_hash_table *
 _bfd_elf_link_hash_table_create (bfd *obfd)
 {
   struct elf_link_hash_table *ret;
-  size_t amt = sizeof (struct elf_link_hash_table);
 
-  ret = (struct elf_link_hash_table *) bfd_zmalloc (amt);
+  ret = bfd_zmalloc (sizeof (*ret));
   if (ret == NULL)
     return NULL;
 
@@ -8598,14 +8570,12 @@ bfd_elf_get_bfd_needed_list (bfd *abfd,
 	  const char *string;
 	  struct bfd_link_needed_list *l;
 	  unsigned int tagv = dyn.d_un.d_val;
-	  size_t amt;
 
 	  string = bfd_elf_string_from_elf_section (abfd, shlink, tagv);
 	  if (string == NULL)
 	    goto error_return;
 
-	  amt = sizeof *l;
-	  l = (struct bfd_link_needed_list *) bfd_alloc (abfd, amt);
+	  l = bfd_alloc (abfd, sizeof (*l));
 	  if (l == NULL)
 	    goto error_return;
 
@@ -8670,8 +8640,8 @@ elf_sort_elf_symbol (const void *arg1, const void *arg2)
 static int
 elf_sym_name_compare (const void *arg1, const void *arg2)
 {
-  const struct elf_symbol *s1 = (const struct elf_symbol *) arg1;
-  const struct elf_symbol *s2 = (const struct elf_symbol *) arg2;
+  const struct elf_symbol *s1 = arg1;
+  const struct elf_symbol *s2 = arg2;
   int ret = strcmp (s1->name, s2->name);
   if (ret != 0)
     return ret;
@@ -8686,10 +8656,9 @@ elf_create_symbuf (size_t symcount, Elf_Internal_Sym *isymbuf)
   Elf_Internal_Sym **ind, **indbufend, **indbuf;
   struct elf_symbuf_symbol *ssym;
   struct elf_symbuf_head *ssymbuf, *ssymhead;
-  size_t i, shndx_count, total_size, amt;
+  size_t i, shndx_count, total_size;
 
-  amt = symcount * sizeof (*indbuf);
-  indbuf = (Elf_Internal_Sym **) bfd_malloc (amt);
+  indbuf = bfd_malloc (symcount * sizeof (*indbuf));
   if (indbuf == NULL)
     return NULL;
 
@@ -8709,7 +8678,7 @@ elf_create_symbuf (size_t symcount, Elf_Internal_Sym *isymbuf)
 
   total_size = ((shndx_count + 1) * sizeof (*ssymbuf)
 		+ (indbufend - indbuf) * sizeof (*ssym));
-  ssymbuf = (struct elf_symbuf_head *) bfd_malloc (total_size);
+  ssymbuf = bfd_malloc (total_size);
   if (ssymbuf == NULL)
     {
       free (indbuf);
@@ -8892,10 +8861,8 @@ bfd_elf_match_symbols_in_sections (asection *sec1, asection *sec2,
       if (count1 == 0 || count2 == 0 || count1 != count2)
 	goto done;
 
-      symtable1
-	= (struct elf_symbol *) bfd_malloc (count1 * sizeof (*symtable1));
-      symtable2
-	= (struct elf_symbol *) bfd_malloc (count2 * sizeof (*symtable2));
+      symtable1 = bfd_malloc (count1 * sizeof (*symtable1));
+      symtable2 = bfd_malloc (count2 * sizeof (*symtable2));
       if (symtable1 == NULL || symtable2 == NULL)
 	goto done;
 
@@ -8946,10 +8913,8 @@ bfd_elf_match_symbols_in_sections (asection *sec1, asection *sec2,
       goto done;
     }
 
-  symtable1 = (struct elf_symbol *)
-      bfd_malloc (symcount1 * sizeof (struct elf_symbol));
-  symtable2 = (struct elf_symbol *)
-      bfd_malloc (symcount2 * sizeof (struct elf_symbol));
+  symtable1 = bfd_malloc (symcount1 * sizeof (struct elf_symbol));
+  symtable2 = bfd_malloc (symcount2 * sizeof (struct elf_symbol));
   if (symtable1 == NULL || symtable2 == NULL)
     goto done;
 
@@ -9094,8 +9059,7 @@ local_hash_newfunc (struct bfd_hash_entry *entry,
      subclass.  */
   if (entry == NULL)
     {
-      entry = bfd_hash_allocate (table,
-				 sizeof (struct local_hash_entry));
+      entry = bfd_hash_allocate (table, sizeof (struct local_hash_entry));
       if (entry == NULL)
         return entry;
     }
@@ -9995,8 +9959,8 @@ struct elf_link_sort_rela
 static int
 elf_link_sort_cmp1 (const void *A, const void *B)
 {
-  const struct elf_link_sort_rela *a = (const struct elf_link_sort_rela *) A;
-  const struct elf_link_sort_rela *b = (const struct elf_link_sort_rela *) B;
+  const struct elf_link_sort_rela *a = A;
+  const struct elf_link_sort_rela *b = B;
   int relativea, relativeb;
 
   relativea = a->type == reloc_class_relative;
@@ -10020,8 +9984,8 @@ elf_link_sort_cmp1 (const void *A, const void *B)
 static int
 elf_link_sort_cmp2 (const void *A, const void *B)
 {
-  const struct elf_link_sort_rela *a = (const struct elf_link_sort_rela *) A;
-  const struct elf_link_sort_rela *b = (const struct elf_link_sort_rela *) B;
+  const struct elf_link_sort_rela *a = A;
+  const struct elf_link_sort_rela *b = B;
 
   if (a->type < b->type)
     return -1;
@@ -10225,7 +10189,7 @@ elf_link_sort_relocs (bfd *obfd, struct bfd_link_info *info, asection **psec)
   count = dynamic_relocs->size / ext_size;
   if (count == 0)
     return 0;
-  sort = (bfd_byte *) bfd_zmalloc (sort_elt * count);
+  sort = bfd_zmalloc (sort_elt * count);
 
   if (sort == NULL)
     {
@@ -10458,9 +10422,7 @@ elf_link_output_symstrtab (void *finf,
       strtabsize += strtabsize;
       hash_table->strtabsize = strtabsize;
       strtabsize *= sizeof (*hash_table->strtab);
-      hash_table->strtab
-	= (struct elf_sym_strtab *) bfd_realloc (hash_table->strtab,
-						 strtabsize);
+      hash_table->strtab = bfd_realloc (hash_table->strtab, strtabsize);
       if (hash_table->strtab == NULL)
 	return 0;
     }
@@ -10495,7 +10457,7 @@ elf_link_swap_symbols_out (struct elf_final_link_info *flinfo)
   bed = get_elf_backend_data (flinfo->output_bfd);
 
   amt = bed->s->sizeof_sym * flinfo->output_bfd->symcount;
-  symbuf = (bfd_byte *) bfd_malloc (amt);
+  symbuf = bfd_malloc (amt);
   if (symbuf == NULL)
     return false;
 
@@ -10503,7 +10465,7 @@ elf_link_swap_symbols_out (struct elf_final_link_info *flinfo)
     {
       amt = sizeof (Elf_External_Sym_Shndx);
       amt *= bfd_get_symcount (flinfo->output_bfd);
-      flinfo->symshndxbuf = (Elf_External_Sym_Shndx *) bfd_zmalloc (amt);
+      flinfo->symshndxbuf = bfd_zmalloc (amt);
       if (flinfo->symshndxbuf == NULL)
 	{
 	  free (symbuf);
@@ -10667,9 +10629,8 @@ elf_link_check_versioned_symbol (struct bfd_link_info *info,
       /* Read in any version definitions.  */
       versymhdr = &elf_tdata (input)->dynversym_hdr;
       if (bfd_seek (input, versymhdr->sh_offset, SEEK_SET) != 0
-	  || (extversym = (Elf_External_Versym *)
-	      _bfd_malloc_and_read (input, versymhdr->sh_size,
-				    versymhdr->sh_size)) == NULL)
+	  || (extversym = _bfd_malloc_and_read (input, versymhdr->sh_size,
+						versymhdr->sh_size)) == NULL)
 	{
 	  free (isymbuf);
 	  return false;
@@ -10756,7 +10717,7 @@ static bool
 elf_link_output_extsym (struct bfd_hash_entry *bh, void *data)
 {
   struct elf_link_hash_entry *h = (struct elf_link_hash_entry *) bh;
-  struct elf_outext_info *eoinfo = (struct elf_outext_info *) data;
+  struct elf_outext_info *eoinfo = data;
   struct elf_final_link_info *flinfo = eoinfo->flinfo;
   bool strip;
   Elf_Internal_Sym sym;
@@ -12439,8 +12400,8 @@ elf_reloc_link_order (bfd *output_bfd,
       const char *sym_name;
       bfd_size_type octets;
 
-      size = (bfd_size_type) bfd_get_reloc_size (howto);
-      buf = (bfd_byte *) bfd_zmalloc (size);
+      size = bfd_get_reloc_size (howto);
+      buf = bfd_zmalloc (size);
       if (buf == NULL && size != 0)
 	return false;
       rstat = _bfd_relocate_contents (howto, output_bfd, addend, buf);
@@ -12998,8 +12959,7 @@ _bfd_elf_final_link (bfd *obfd, struct bfd_link_info *info)
 	  unsigned char *contents = esdo->this_hdr.contents;
 	  if (contents != NULL)
 	    abort ();
-	  contents
-	    = (unsigned char *) bfd_malloc (esdo->this_hdr.sh_size);
+	  contents = bfd_malloc (esdo->this_hdr.sh_size);
 	  if (contents == NULL)
 	    goto error_return;
 	  esdo->this_hdr.contents = contents;
@@ -13024,8 +12984,7 @@ _bfd_elf_final_link (bfd *obfd, struct bfd_link_info *info)
   if (max_sym_count < 20)
     max_sym_count = 20;
   htab->strtabsize = max_sym_count;
-  amt = max_sym_count * sizeof (struct elf_sym_strtab);
-  htab->strtab = (struct elf_sym_strtab *) bfd_malloc (amt);
+  htab->strtab = bfd_malloc (max_sym_count * sizeof (*htab->strtab));
   if (htab->strtab == NULL)
     goto error_return;
   /* The real buffer will be allocated in elf_link_swap_symbols_out.  */
@@ -13102,7 +13061,7 @@ _bfd_elf_final_link (bfd *obfd, struct bfd_link_info *info)
      files.  */
   if (max_contents_size != 0)
     {
-      flinfo.contents = (bfd_byte *) bfd_malloc (max_contents_size);
+      flinfo.contents = bfd_malloc (max_contents_size);
       if (flinfo.contents == NULL)
 	goto error_return;
     }
@@ -13117,7 +13076,7 @@ _bfd_elf_final_link (bfd *obfd, struct bfd_link_info *info)
   if (max_internal_reloc_count != 0)
     {
       amt = max_internal_reloc_count * sizeof (Elf_Internal_Rela);
-      flinfo.internal_relocs = (Elf_Internal_Rela *) bfd_malloc (amt);
+      flinfo.internal_relocs = bfd_malloc (amt);
       if (flinfo.internal_relocs == NULL)
 	goto error_return;
     }
@@ -13125,22 +13084,22 @@ _bfd_elf_final_link (bfd *obfd, struct bfd_link_info *info)
   if (max_sym_count != 0)
     {
       amt = max_sym_count * obed->s->sizeof_sym;
-      flinfo.external_syms = (bfd_byte *) bfd_malloc (amt);
+      flinfo.external_syms = bfd_malloc (amt);
       if (flinfo.external_syms == NULL)
 	goto error_return;
 
       amt = max_sym_count * sizeof (Elf_Internal_Sym);
-      flinfo.internal_syms = (Elf_Internal_Sym *) bfd_malloc (amt);
+      flinfo.internal_syms = bfd_malloc (amt);
       if (flinfo.internal_syms == NULL)
 	goto error_return;
 
       amt = max_sym_count * sizeof (long);
-      flinfo.indices = (long int *) bfd_malloc (amt);
+      flinfo.indices = bfd_malloc (amt);
       if (flinfo.indices == NULL)
 	goto error_return;
 
       amt = max_sym_count * sizeof (asection *);
-      flinfo.sections = (asection **) bfd_malloc (amt);
+      flinfo.sections = bfd_malloc (amt);
       if (flinfo.sections == NULL)
 	goto error_return;
     }
@@ -13148,7 +13107,7 @@ _bfd_elf_final_link (bfd *obfd, struct bfd_link_info *info)
   if (max_sym_shndx_count != 0)
     {
       amt = max_sym_shndx_count * sizeof (Elf_External_Sym_Shndx);
-      flinfo.locsym_shndx = (Elf_External_Sym_Shndx *) bfd_malloc (amt);
+      flinfo.locsym_shndx = bfd_malloc (amt);
       if (flinfo.locsym_shndx == NULL)
 	goto error_return;
     }
@@ -14540,7 +14499,7 @@ elf_gc_smash_unused_vtentry_relocs (struct elf_link_hash_entry *h,
   Elf_Internal_Rela *relstart, *relend, *rel;
   elf_backend_data *bed;
   unsigned int log_file_align;
-  struct link_info_ok *info = (struct link_info_ok *) ptr;
+  struct link_info_ok *info = ptr;
 
   /* Take care of both those symbols that do not describe vtables as
      well as those that are not loaded.  */
@@ -14590,7 +14549,7 @@ elf_gc_smash_unused_vtentry_relocs (struct elf_link_hash_entry *h,
 bool
 bfd_elf_gc_mark_dynamic_ref_symbol (struct elf_link_hash_entry *h, void *inf)
 {
-  struct bfd_link_info *info = (struct bfd_link_info *) inf;
+  struct bfd_link_info *info = inf;
   struct bfd_elf_dynamic_list *d = info->dynamic_list;
 
   if ((h->root.type == bfd_link_hash_defined
@@ -14844,8 +14803,7 @@ bfd_elf_gc_record_vtinherit (bfd *abfd,
  win:
   if (!child->u2.vtable)
     {
-      child->u2.vtable = ((struct elf_link_virtual_table_entry *)
-			  bfd_zalloc (abfd, sizeof (*child->u2.vtable)));
+      child->u2.vtable = bfd_zalloc (abfd, sizeof (*child->u2.vtable));
       if (!child->u2.vtable)
 	return false;
     }
@@ -14885,8 +14843,7 @@ bfd_elf_gc_record_vtentry (bfd *abfd, asection *sec,
 
   if (!h->u2.vtable)
     {
-      h->u2.vtable = ((struct elf_link_virtual_table_entry *)
-		      bfd_zalloc (abfd, sizeof (*h->u2.vtable)));
+      h->u2.vtable = bfd_zalloc (abfd, sizeof (*h->u2.vtable));
       if (!h->u2.vtable)
 	return false;
     }
@@ -14919,7 +14876,7 @@ bfd_elf_gc_record_vtentry (bfd *abfd, asection *sec,
 
       if (ptr)
 	{
-	  ptr = (bool *) bfd_realloc (ptr - 1, bytes);
+	  ptr = bfd_realloc (ptr - 1, bytes);
 
 	  if (ptr != NULL)
 	    {
@@ -14931,7 +14888,7 @@ bfd_elf_gc_record_vtentry (bfd *abfd, asection *sec,
 	    }
 	}
       else
-	ptr = (bool *) bfd_zmalloc (bytes);
+	ptr = bfd_zmalloc (bytes);
 
       if (ptr == NULL)
 	return false;
@@ -15049,7 +15006,7 @@ struct alloc_got_off_arg {
 static bool
 elf_gc_allocate_got_offsets (struct elf_link_hash_entry *h, void *arg)
 {
-  struct alloc_got_off_arg *gofarg = (struct alloc_got_off_arg *) arg;
+  struct alloc_got_off_arg *gofarg = arg;
   bfd *obfd = gofarg->info->output_bfd;
   elf_backend_data *obed = get_elf_backend_data (obfd);
 
@@ -15146,7 +15103,7 @@ _bfd_elf_gc_common_final_link (bfd *obfd, struct bfd_link_info *info)
 bool
 bfd_elf_reloc_symbol_deleted_p (bfd_vma offset, void *cookie)
 {
-  struct elf_reloc_cookie *rcookie = (struct elf_reloc_cookie *) cookie;
+  struct elf_reloc_cookie *rcookie = cookie;
 
   if (elf_bad_symtab (rcookie->abfd))
     rcookie->rel = rcookie->rels;
@@ -15757,7 +15714,7 @@ _bfd_elf_maybe_set_textrel (struct elf_link_hash_entry *h, void *inf)
   sec = _bfd_elf_readonly_dynrelocs (h);
   if (sec != NULL)
     {
-      struct bfd_link_info *info = (struct bfd_link_info *) inf;
+      struct bfd_link_info *info = inf;
 
       info->flags |= DF_TEXTREL;
       /* xgettext:c-format */

-- 
Alan Modra

From amodra@gmail.com  Thu Jun 18 05:18:51 2026
From: amodra@gmail.com (Alan Modra)
Date: Thu, 18 Jun 2026 14:48:51 +0930
Subject: PR 29655 test: xfail more targets
Message-ID: <ajN_uxj8OQ2QlW-x@squeak.grove.modra.org>

Apparently some libraries (Qt5 is called out in PR 29655) want to know
if one of their functions has been overridden, and do so by comparing
the address of the function with the address of a local hidden alias.
This is a bug in every such library that tries that trick, because if
the main program is non-PIC and calls the function in question then
the globally visible address of the function is set to the PLT call
stub code for that function in the main executable.  This will happen
even when there is no real overriding of the function.

On the other hand if the main executable is PIC then there should be
no need to define function addresses on PLT call stub code, but some
linker target support still does so.  This is a minor bug in the
linker as it results in more work in ld.so and sligntly slower
startup.  However, I don't think it is an important issue if target
maintainers can't fix the problem.

	* testsuite/ld-elf/shared.exp (pr29655): xfail more targets.

diff --git a/ld/testsuite/ld-elf/shared.exp b/ld/testsuite/ld-elf/shared.exp
index a4437162e3a..f69a0d402bd 100644
--- a/ld/testsuite/ld-elf/shared.exp
+++ b/ld/testsuite/ld-elf/shared.exp
@@ -1879,7 +1879,7 @@ run_cc_link_tests [list \
 # of a function defined in a DSO results in the function address (from GOT)
 # and not the "canonical PLT" address from the PDE.
 # PR ld/34151
-setup_xfail sparc*-*-*
+setup_xfail sparc*-*-* m68k-*-* riscv*-*-* s390-*-* sh*-*-* tile*-*-*
 run_cc_link_tests [list \
     [list \
 	"Build pr29655" \

-- 
Alan Modra

From amodra@gmail.com  Thu Jun 18 05:59:45 2026
From: amodra@gmail.com (Alan Modra)
Date: Thu, 18 Jun 2026 15:29:45 +0930
Subject: buffer overflow in fetch_indexed_addr
Message-ID: <ajOJUf3EcSGggKdi@squeak.grove.modra.org>

oss-fuzz found another case where sanity checks weren't good enough.

	* dwarf.c (fetch_indexed_addr): Avoid integer overflow when
	sanity checking field offset
	(fetch_indexed_offset): Similarly.  Don't bother with "too small"
	warning, which will be covered by field offset check.  Warn
	about base and index rather than possibly overflowed calculation.

diff --git a/binutils/dwarf.c b/binutils/dwarf.c
index 4720dd717fa..f915495f6b3 100644
--- a/binutils/dwarf.c
+++ b/binutils/dwarf.c
@@ -744,7 +744,8 @@ fetch_indexed_addr (uint64_t offset, uint32_t num_bytes)
       return 0;
     }
 
-  if (offset + num_bytes > section->size)
+  if (offset > section->size
+      || num_bytes > section->size - offset)
     {
       warn (_("Offset into section %s too big: %#" PRIx64 "\n"),
 	    section->name, offset);
@@ -769,7 +770,7 @@ fetch_indexed_offset (uint64_t                         idx,
 		      uint64_t                         base_address,
 		      uint64_t                         offset_size)
 {
-  uint64_t offset_of_offset = base_address + idx * offset_size;
+  uint64_t offset_of_offset;
   struct dwarf_section *section = &debug_displays [sec_enum].section;
 
   if (section->start == NULL)
@@ -778,17 +779,13 @@ fetch_indexed_offset (uint64_t                         idx,
       return -1;
     }
 
-  if (section->size < 4)
-    {
-      warn (_("Section %s is too small to contain an value indexed from another section!\n"),
-	    section->name);
-      return -1;
-    }
-
-  if (offset_of_offset + offset_size >= section->size)
+  if (_bfd_mul_overflow (idx, offset_size, &offset_of_offset)
+      || (offset_of_offset += base_address) < base_address
+      || offset_of_offset > section->size
+      || offset_size > section->size - offset_of_offset)
     {
-      warn (_("Offset of %#" PRIx64 " is too big for section %s\n"),
-	    offset_of_offset, section->name);
+      warn (_("Base %#" PRIx64 " with index %#" PRIx64 " is too big for section %s\n"),
+	    base_address, idx, section->name);
       return -1;
     }
 

-- 
Alan Modra

From mengqinggang@loongson.cn  Thu Jun 18 06:29:10 2026
From: mengqinggang@loongson.cn (mengqinggang)
Date: Thu, 18 Jun 2026 14:29:10 +0800
Subject: [PATCH v1] LoongArch: Fix linker relaxation alignment
Message-ID: <20260618062910.972814-1-mengqinggang@loongson.cn>

When linking multiple objects, relaxation can cause alignment issues.
Input section's output_offset is updated in relaxation without considering
section alignment. Update section output_offset by align_opwer.
---
 bfd/elfnn-loongarch.c                         | 24 +++----------------
 ld/testsuite/ld-loongarch-elf/relax-align-1.d | 13 ++++++++++
 .../ld-loongarch-elf/relax-align-1a.s         |  5 ++++
 .../ld-loongarch-elf/relax-align-1b.s         |  3 +++
 ld/testsuite/ld-loongarch-elf/relax.exp       |  4 ++++
 5 files changed, 28 insertions(+), 21 deletions(-)
 create mode 100644 ld/testsuite/ld-loongarch-elf/relax-align-1.d
 create mode 100644 ld/testsuite/ld-loongarch-elf/relax-align-1a.s
 create mode 100644 ld/testsuite/ld-loongarch-elf/relax-align-1b.s

diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c
index 9d9c68664bb..b7af2041238 100644
--- a/bfd/elfnn-loongarch.c
+++ b/bfd/elfnn-loongarch.c
@@ -5725,11 +5725,6 @@ loongarch_relax_pcala_addi (bfd *abfd, asection *sec, asection *sym_sec,
   uint32_t add = bfd_get (32, abfd, contents + rel_lo->r_offset);
   uint32_t rd = LARCH_GET_RD (pca);
 
-  /* This section's output_offset need to subtract the bytes of instructions
-     relaxed by the previous sections, so it needs to be updated beforehand.
-     size_input_section already took care of updating it after relaxation,
-     so we additionally update once here.  */
-  sec->output_offset = sec->output_section->size;
   bfd_vma pc = sec_addr (sec)
 	       + loongarch_calc_relaxed_addr (info, rel_hi->r_offset);
   if (sym_sec == sec)
@@ -5790,11 +5785,6 @@ loongarch_relax_call36 (bfd *abfd, asection *sec, asection *sym_sec,
   uint32_t jirl = bfd_get (32, abfd, contents + rel->r_offset + 4);
   uint32_t rd = LARCH_GET_RD (jirl);
 
-  /* This section's output_offset need to subtract the bytes of instructions
-     relaxed by the previous sections, so it needs to be updated beforehand.
-     size_input_section already took care of updating it after relaxation,
-     so we additionally update once here.  */
-  sec->output_offset = sec->output_section->size;
   bfd_vma pc = sec_addr (sec)
 	       + loongarch_calc_relaxed_addr (info, rel->r_offset);
   if (sym_sec == sec)
@@ -5851,11 +5841,6 @@ loongarch_relax_pcala_ld (bfd *abfd, asection *sec,
 			  bool *again ATTRIBUTE_UNUSED,
 			  bfd_vma max_alignment)
 {
-  /* This section's output_offset need to subtract the bytes of instructions
-     relaxed by the previous sections, so it needs to be updated beforehand.
-     size_input_section already took care of updating it after relaxation,
-     so we additionally update once here.  */
-  sec->output_offset = sec->output_section->size;
   bfd_vma pc = sec_addr (sec)
 	       + loongarch_calc_relaxed_addr (info, rel_hi->r_offset);
   if (sym_sec == sec)
@@ -6008,11 +5993,6 @@ loongarch_relax_tls_ld_gd_desc (bfd *abfd, asection *sec, asection *sym_sec,
   uint32_t add = bfd_get (32, abfd, contents + rel_lo->r_offset);
   uint32_t rd = LARCH_GET_RD (pca);
 
-  /* This section's output_offset need to subtract the bytes of instructions
-     relaxed by the previous sections, so it needs to be updated beforehand.
-     size_input_section already took care of updating it after relaxation,
-     so we additionally update once here.  */
-  sec->output_offset = sec->output_section->size;
   bfd_vma pc = sec_addr (sec)
 	       + loongarch_calc_relaxed_addr (info, rel_hi->r_offset);
   if (sym_sec == sec)
@@ -6187,7 +6167,9 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec,
      so we additionally update once here.  */
 
   /* update before tls trans and relax, or may cause same pcadd_hi20 address.  */
-  sec->output_offset = sec->output_section->size;
+
+  sec->output_offset = align_power (sec->output_section->size,
+				    sec->alignment_power);
 
   for (unsigned int i = 0; i < sec->reloc_count; i++)
     {
diff --git a/ld/testsuite/ld-loongarch-elf/relax-align-1.d b/ld/testsuite/ld-loongarch-elf/relax-align-1.d
new file mode 100644
index 00000000000..30b7c4cb293
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/relax-align-1.d
@@ -0,0 +1,13 @@
+#source: relax-align-1a.s
+#source: relax-align-1b.s
+#ld: -e0
+#objdump: -d
+
+#...
+.*[0|8]:	54000400 	bl          	4.*<f>
+#...
+.*[0|8]:	02c001ac 	addi.d      	\$t0, \$t1, 0
+#...
+.*0:	02c005ac 	addi.d      	\$t0, \$t1, 1
+#...
+.*0:	02c005ac 	addi.d      	\$t0, \$t1, 1
diff --git a/ld/testsuite/ld-loongarch-elf/relax-align-1a.s b/ld/testsuite/ld-loongarch-elf/relax-align-1a.s
new file mode 100644
index 00000000000..2b7f3ecb6be
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/relax-align-1a.s
@@ -0,0 +1,5 @@
+.text
+  call f
+f:
+  .align 3
+  addi.d $t0, $t1, 0
diff --git a/ld/testsuite/ld-loongarch-elf/relax-align-1b.s b/ld/testsuite/ld-loongarch-elf/relax-align-1b.s
new file mode 100644
index 00000000000..2ed480a6c1b
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/relax-align-1b.s
@@ -0,0 +1,3 @@
+addi.d $t0, $t1, 1
+.align 4
+addi.d $t0, $t1, 1
diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp
index 7c32a65244c..31787a93967 100644
--- a/ld/testsuite/ld-loongarch-elf/relax.exp
+++ b/ld/testsuite/ld-loongarch-elf/relax.exp
@@ -46,6 +46,10 @@ proc run_partial_linking_align_test {} {
   }
 }
 
+if [istarget loongarch*-*-*] {
+  run_dump_test "relax-align-1"
+}
+
 if [istarget loongarch64-*-*] {
   if [isbuild loongarch64-*-*] {
     run_dump_test "relax-align-ignore-start"
-- 
2.34.1


From mengqinggang@loongson.cn  Thu Jun 18 07:01:55 2026
From: mengqinggang@loongson.cn (mengqinggang)
Date: Thu, 18 Jun 2026 15:01:55 +0800
Subject: [PATCH v2] LoongArch: Fix relaxation alignment with ld -r (PR 33236)
Message-ID: <20260618070155.1339292-1-mengqinggang@loongson.cn>

LoongArch has the same issue as RISC-V for PR 33236 [1].

Section alignment can't be adjusted for objects generated by ld -r.
If previous sections are relaxed, the subsequent section maybe misaligned.

To fix this, add an align section and an align relocation before each
section when ld -r. And change the section alignment to 4 to disable
the default section start address calculation.

ld.lld has fixed this issue in the following two patches [2] [3].

[1] https://sourceware.org/bugzilla/show_bug.cgi?id=33236
[2] https://github.com/llvm/llvm-project/pull/151639
[3] https://github.com/llvm/llvm-project/pull/198147
---

v1 -> v2:
- Remove changes in ldlang.c.
- Stop ldlang.c:size_input_section padding by changing
  the input section alignment_power.

 bfd/elfnn-loongarch.c                         | 150 +++++++++++++++
 bfd/elfxx-loongarch.h                         |  10 +
 ld/emultempl/loongarchelf.em                  | 182 ++++++++++++++++++
 .../ld-loongarch-elf/relax-align-ld-r.d       |   9 +
 .../ld-loongarch-elf/relax-align-ld-r.s       |  12 ++
 ld/testsuite/ld-loongarch-elf/relax.exp       |   1 +
 6 files changed, 364 insertions(+)
 create mode 100644 ld/testsuite/ld-loongarch-elf/relax-align-ld-r.d
 create mode 100644 ld/testsuite/ld-loongarch-elf/relax-align-ld-r.s

diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c
index b7af2041238..ba9406c6c40 100644
--- a/bfd/elfnn-loongarch.c
+++ b/bfd/elfnn-loongarch.c
@@ -7054,6 +7054,156 @@ elf_loongarch64_hash_symbol (struct elf_link_hash_entry *h)
   return _bfd_elf_hash_symbol (h);
 }
 
+/* Write nops to align section.  */
+
+static bool
+loongarch_build_align_nops (asection *section, asection *align_section)
+{
+  if (section->output_section == NULL
+      || align_section->output_section == NULL)
+    {
+      _bfd_error_handler (_("Could not assign to an output section."));
+      return false;
+    }
+
+  bfd_byte *loc = align_section->contents;
+  for (bfd_size_type i = 0; i < (align_section->size / 4); i++)
+    {
+      bfd_putl32 (LARCH_NOP, loc);
+      loc += 4;
+    }
+
+  return true;
+}
+
+/* Emit an align relocation and a related undefined symbol.  */
+
+static bool
+loongarch_add_align_relocs (asection *align_sec, bfd* align_bfd)
+{
+  elf_backend_data *bed = get_elf_backend_data (align_bfd);
+
+  if (elf_section_data (align_sec)->relocs == NULL)
+    {
+      align_sec->reloc_count = 1;
+      align_sec->flags |= SEC_RELOC;
+
+      Elf_Internal_Rela *rela = (Elf_Internal_Rela *)
+	bfd_malloc (sizeof (Elf_Internal_Rela));
+      if (rela == NULL)
+	return false;
+
+      rela->r_offset = 0;
+      rela->r_addend = align_sec->size;
+      rela->r_info = ELFNN_R_INFO (0, R_LARCH_ALIGN);
+      elf_section_data (align_sec)->relocs = rela;
+
+      Elf_Internal_Shdr *rela_hdr = (Elf_Internal_Shdr *)
+	bfd_zalloc (align_bfd, sizeof (Elf_Internal_Shdr));
+      if (rela_hdr == NULL)
+       return false;
+
+      rela_hdr->sh_size = sizeof (Elf_Internal_Rela);
+      rela_hdr->sh_entsize = sizeof (Elf_Internal_Rela);
+      rela_hdr->sh_type = SHT_RELA;
+      rela_hdr->sh_addralign = (bfd_vma) 1 << bed->s->log_file_align;
+      elf_section_data (align_sec)->rela.hdr = rela_hdr;
+    }
+
+  /* Used in loongarch_elf_relax_section for align relocations.  */
+  Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (align_bfd);
+  if (symtab_hdr->contents == NULL)
+    {
+      Elf_Internal_Sym *sym = (Elf_Internal_Sym *)
+	bfd_zmalloc (sizeof (Elf_Internal_Sym));
+      if (sym == NULL)
+	return false;
+
+      /* Match if (r_symndx < symtab_hdr->sh_info) branch in
+	 loongarch_elf_relocate_section to avoid find link failed.  */
+      symtab_hdr->sh_info = 1;
+      symtab_hdr->contents = (unsigned char *) sym;
+    }
+
+  return true;
+}
+
+/* Section name for aligns is the associated section name plus this
+   string.  */
+#define ALIGN_SUFFIX ".align"
+
+/* Determine and set the size of the align section for a final link.  */
+
+bool
+elfNN_loongarch_size_aligns (bfd *output_bfd,
+			     bfd *align_bfd,
+			     struct bfd_link_info *info,
+			     asection * (*add_align_section)
+					  (const char *, asection *),
+			     void (*layout_sections_again) (void))
+{
+  bool need_laying_out = false;
+  for (bfd *input_bfd = info->input_bfds; input_bfd != NULL;
+       input_bfd = input_bfd->link.next)
+    {
+      asection *sec;
+      asection *align_sec;
+
+      if (!is_loongarch_elf (input_bfd)
+	  || (input_bfd->flags & BFD_LINKER_CREATED) != 0)
+	continue;
+
+      for (sec = input_bfd->sections; sec != NULL; sec = sec->next)
+	{
+	  /* If this section is not a code section, do nothing.  */
+	  if ((sec->flags & SEC_CODE) == 0)
+	    continue;
+
+	  /* If this section is a link-once section that will be
+	     discarded, then don't create any stubs.  */
+	  if (sec->output_section == NULL
+	      || sec->output_section->owner != output_bfd)
+	    continue;
+
+	  if (sec->alignment_power > 2)
+	    {
+	      char *s_name;
+	      size_t namelen;
+	      bfd_size_type len;
+	      namelen = strlen (sec->name);
+	      len = namelen + sizeof (ALIGN_SUFFIX);
+	      s_name = bfd_alloc (align_bfd, len);
+	      if (s_name == NULL)
+		return false;
+	      memcpy (s_name, sec->name, namelen);
+	      memcpy (s_name + namelen, ALIGN_SUFFIX, sizeof (ALIGN_SUFFIX));
+
+	      align_sec = add_align_section (s_name, sec);
+
+	      if (align_sec == NULL)
+		return false;
+
+	      if (! loongarch_build_align_nops (sec, align_sec))
+		return false;
+
+	      if (! loongarch_add_align_relocs (align_sec, align_bfd))
+		return false;
+
+	      /* Change the section alignment to 4 to disable the default
+		 behavior of "dot += alignment_needed" in ldlang.c. */
+	      bfd_set_section_alignment (sec, 2);
+
+	      need_laying_out = true;
+	    }
+	}
+    }
+
+  if (need_laying_out)
+    layout_sections_again ();
+
+  return true;
+}
+
 #define TARGET_LITTLE_SYM loongarch_elfNN_vec
 #define TARGET_LITTLE_NAME "elfNN-loongarch"
 #define ELF_ARCH bfd_arch_loongarch
diff --git a/bfd/elfxx-loongarch.h b/bfd/elfxx-loongarch.h
index 400b7377ccd..b295b7a9070 100644
--- a/bfd/elfxx-loongarch.h
+++ b/bfd/elfxx-loongarch.h
@@ -45,6 +45,16 @@ bfd_elf64_loongarch_set_data_segment_info (struct bfd_link_info *, int *);
 bfd_byte *
 loongarch_write_unsigned_leb128 (bfd_byte *, size_t, bfd_vma) ATTRIBUTE_HIDDEN;
 
+extern bool elf64_loongarch_size_aligns
+  (bfd *, bfd *, struct bfd_link_info *,
+   struct bfd_section * (*) (const char *, struct bfd_section *),
+   void (*) (void));
+
+extern bool elf32_loongarch_size_aligns
+  (bfd *, bfd *, struct bfd_link_info *,
+   struct bfd_section * (*) (const char *, struct bfd_section *),
+   void (*) (void));
+
 /* TRUE if this is a PLT reference to a local IFUNC.  */
 #define PLT_LOCAL_IFUNC_P(INFO, H) \
   ((H)->dynindx == -1 \
diff --git a/ld/emultempl/loongarchelf.em b/ld/emultempl/loongarchelf.em
index 713331d30fc..4240ee70a23 100644
--- a/ld/emultempl/loongarchelf.em
+++ b/ld/emultempl/loongarchelf.em
@@ -41,6 +41,10 @@ PARSE_AND_LIST_ARGS_CASES=${PARSE_AND_LIST_ARGS_CASES}'
 '
 
 fragment <<EOF
+
+/* Fake input file for align.  */
+static lang_input_statement_type *align_file;
+
 static void
 larch_elf_before_allocation (void)
 {
@@ -61,6 +65,136 @@ larch_elf_before_allocation (void)
   link_info.relax_pass = 3;
 }
 
+/* Traverse the linker tree to insert the align section
+   before input section.  */
+
+static bool
+hook_in_align (lang_statement_list_type add,
+	       asection *input_section,
+	       lang_statement_union_type **lp)
+{
+  bool ret;
+  lang_statement_union_type *l;
+
+  for (; (l = *lp) != NULL; lp = &l->header.next)
+    {
+      switch (l->header.type)
+	{
+	case lang_constructors_statement_enum:
+	  ret = hook_in_align (add, input_section, &constructor_list.head);
+	  if (ret)
+	    return ret;
+	  break;
+
+	case lang_output_section_statement_enum:
+	  ret = hook_in_align (add, input_section,
+			       &l->output_section_statement.children.head);
+	  if (ret)
+	    return ret;
+	  break;
+
+	case lang_wild_statement_enum:
+	  ret = hook_in_align (add, input_section,
+			       &l->wild_statement.children.head);
+	  if (ret)
+	    return ret;
+	  break;
+
+	case lang_group_statement_enum:
+	  ret = hook_in_align (add, input_section,
+			       &l->group_statement.children.head);
+	  if (ret)
+	    return ret;
+	  break;
+
+	case lang_input_section_enum:
+	  if (l->input_section.section == input_section)
+	    {
+	      /* We've found our section.  Insert the align immediately
+		 before its associated input section.  */
+	      //*(add.tail) = l->header.next;
+	      //l->header.next = add.head;
+	      *lp = add.head;
+	      add.head->header.next = l;
+	      return true;
+	    }
+	  break;
+
+	case lang_data_statement_enum:
+	case lang_reloc_statement_enum:
+	case lang_object_symbols_statement_enum:
+	case lang_output_statement_enum:
+	case lang_target_statement_enum:
+	case lang_input_statement_enum:
+	case lang_assignment_statement_enum:
+	case lang_padding_statement_enum:
+	case lang_address_statement_enum:
+	case lang_fill_statement_enum:
+	  break;
+
+	default:
+	  FAIL ();
+	  break;
+	}
+    }
+
+  return false;
+}
+
+/* Create a new align section, and arrange for it to be linked
+   immediately before INPUT_SECTION.  */
+
+static asection *
+elf${ELFSIZE}_loongarch_add_align_section (const char *align_sec_name,
+					   asection *input_section)
+{
+  flagword flags;
+  asection *align_sec;
+  asection *output_section;
+  lang_statement_list_type add_child;
+  lang_output_section_statement_type *os;
+
+  flags = (SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
+	   | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY | SEC_KEEP);
+  align_sec = bfd_make_section_anyway_with_flags (align_file->the_bfd,
+						  align_sec_name, flags);
+  if (align_sec == NULL)
+    goto err_ret;
+
+  align_sec->veneer = 1;
+  bfd_set_section_alignment (align_sec, 2);
+
+  output_section = input_section->output_section;
+  os = lang_output_section_get (output_section);
+
+  lang_list_init (&add_child);
+  lang_add_section (&add_child, align_sec, NULL, NULL, os);
+
+  if (add_child.head == NULL)
+    goto err_ret;
+
+  align_sec->size = (1 << input_section->alignment_power) - 4;
+  align_sec->contents = bfd_alloc (align_file->the_bfd, align_sec->size);
+  if (align_sec->contents == NULL && align_sec->size != 0)
+    goto err_ret;
+  align_sec->alloced = 1;
+
+  if (hook_in_align (add_child, input_section, &os->children.head))
+    return align_sec;
+
+ err_ret:
+  einfo (_("%X%P: can not make align section: %E\n"));
+  return NULL;
+}
+
+static void
+gldloongarch_layout_sections_again (void)
+{
+  /* If we have changed sizes of the align sections, then we need
+     to recalculate all the section offsets.  */
+  ldelf_map_segments (true);
+}
+
 static void
 gld${EMULATION_NAME}_after_allocation (void)
 {
@@ -78,6 +212,21 @@ gld${EMULATION_NAME}_after_allocation (void)
 	}
     }
 
+  /* If generating a relocatable output file, we have to add align
+     at the start of sections.  */
+  if (align_file != NULL && bfd_link_relocatable (&link_info))
+    {
+      if (! elf${ELFSIZE}_loongarch_size_aligns (link_info.output_bfd,
+			align_file->the_bfd,
+			&link_info,
+			&elf${ELFSIZE}_loongarch_add_align_section,
+			&gldloongarch_layout_sections_again))
+	{
+	  einfo (_("%X%P: can not size align section: %E\n"));
+	  return;
+	}
+    }
+
   /* The program header size of executable file may increase.  */
   if (bfd_get_flavour (link_info.output_bfd) == bfd_target_elf_flavour
       && !bfd_link_relocatable (&link_info))
@@ -101,7 +250,40 @@ gld${EMULATION_NAME}_after_allocation (void)
   ldelf_map_segments (need_layout);
 }
 
+/* This is called before the input files are opened.  We create a new
+   fake input file to hold the align sections.  */
+
+static void
+loongarch_elf_create_output_section_statements (void)
+{
+  if (! bfd_link_relocatable (&link_info))
+    return;
+
+  align_file = lang_add_input_file ("linker aligns",
+				    lang_input_file_is_fake_enum,
+				    NULL);
+  align_file->the_bfd = bfd_create ("linker aligns",
+				    link_info.output_bfd);
+  if (align_file->the_bfd == NULL
+      || ! bfd_set_arch_mach (align_file->the_bfd,
+			      bfd_get_arch (link_info.output_bfd),
+			      bfd_get_mach (link_info.output_bfd)))
+    {
+      fatal (_("%P: can not create BFD: %E\n"));
+      return;
+    }
+
+  align_file->the_bfd->flags |= BFD_LINKER_CREATED;
+
+  Elf_Internal_Ehdr *ehdr = elf_elfheader (align_file->the_bfd);
+  elf_backend_data *bed = get_elf_backend_data (link_info.output_bfd);
+  ehdr->e_ident[EI_CLASS] = bed->s->elfclass;
+
+  ldlang_add_file (align_file);
+}
+
 EOF
 
 LDEMUL_BEFORE_ALLOCATION=larch_elf_before_allocation
 LDEMUL_AFTER_ALLOCATION=gld${EMULATION_NAME}_after_allocation
+LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS=loongarch_elf_create_output_section_statements
diff --git a/ld/testsuite/ld-loongarch-elf/relax-align-ld-r.d b/ld/testsuite/ld-loongarch-elf/relax-align-ld-r.d
new file mode 100644
index 00000000000..a2d19734a59
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/relax-align-ld-r.d
@@ -0,0 +1,9 @@
+#as:
+#ld: -r
+#objdump: -Dr
+
+#...
+.*R_LARCH_ALIGN.*
+#...
+.*R_LARCH_ALIGN.*
+#...
diff --git a/ld/testsuite/ld-loongarch-elf/relax-align-ld-r.s b/ld/testsuite/ld-loongarch-elf/relax-align-ld-r.s
new file mode 100644
index 00000000000..19555a7148e
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/relax-align-ld-r.s
@@ -0,0 +1,12 @@
+# Add an align section before text section when ld -r.
+# There will be two R_LARCH_ALIGN relocations after ld -r.
+.text
+  addi.d $a0, $a0, 1
+  call36 func
+  .align 3
+func:
+  addi.d $a0, $a0, 1
+
+# Only add a align section for code section.
+.data
+  .4byte 0x1234
diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp
index 31787a93967..bb8429ab515 100644
--- a/ld/testsuite/ld-loongarch-elf/relax.exp
+++ b/ld/testsuite/ld-loongarch-elf/relax.exp
@@ -48,6 +48,7 @@ proc run_partial_linking_align_test {} {
 
 if [istarget loongarch*-*-*] {
   run_dump_test "relax-align-1"
+  run_dump_test "relax-align-ld-r"
 }
 
 if [istarget loongarch64-*-*] {
-- 
2.34.1


From chigot@adacore.com  Thu Jun 18 07:58:56 2026
From: chigot@adacore.com (=?UTF-8?q?Cl=C3=A9ment=20Chigot?=)
Date: Thu, 18 Jun 2026 09:58:56 +0200
Subject: [PATCH v2] ld/testsuite: add support for remote testing in ld-cdtest
Message-ID: <20260618075856.2258643-1-chigot@adacore.com>

This converts the existing to code to use "remote_load" allowing
execution on both native and remote targets.

The "diff" between the output and the expected result has been
transformed to the usual regexp_diff. The previous could have been
transformed into `remote_exec build diff` but tends to be fickled with
new lines.
---
 ld/testsuite/ld-cdtest/cdtest-nrv.dat | 26 ++++----
 ld/testsuite/ld-cdtest/cdtest.dat     | 30 ++++-----
 ld/testsuite/ld-cdtest/cdtest.exp     | 95 +++++++++++++--------------
 3 files changed, 73 insertions(+), 78 deletions(-)

diff --git a/ld/testsuite/ld-cdtest/cdtest-nrv.dat b/ld/testsuite/ld-cdtest/cdtest-nrv.dat
index d3f871ff108..76fcbaa03d4 100644
--- a/ld/testsuite/ld-cdtest/cdtest-nrv.dat
+++ b/ld/testsuite/ld-cdtest/cdtest-nrv.dat
@@ -1,13 +1,13 @@
-Constructing Foo(1) "static_foo"
-Constructing Foo(2) "static_foo"
-Constructing Foo(3) "automatic_foo"
-Constructing Foo(4) "default-foo"
-Constructing Foo(5) "other_foo1"
-Constructing Foo(6) "other_foo2"
-Copying Foo(5) "other_foo1" to Foo(6)
-Destructing Foo(6) "other_foo1" (remaining foos: 5)
-Destructing Foo(5) "other_foo1" (remaining foos: 4)
-Destructing Foo(4) "default-foo" (remaining foos: 3)
-Destructing Foo(3) "automatic_foo" (remaining foos: 2)
-Destructing Foo(2) "static_foo" (remaining foos: 1)
-Destructing Foo(1) "static_foo" (remaining foos: 0)
+Constructing Foo\(1\) "static_foo"
+Constructing Foo\(2\) "static_foo"
+Constructing Foo\(3\) "automatic_foo"
+Constructing Foo\(4\) "default-foo"
+Constructing Foo\(5\) "other_foo1"
+Constructing Foo\(6\) "other_foo2"
+Copying Foo\(5\) "other_foo1" to Foo\(6\)
+Destructing Foo\(6\) "other_foo1" \(remaining foos: 5\)
+Destructing Foo\(5\) "other_foo1" \(remaining foos: 4\)
+Destructing Foo\(4\) "default-foo" \(remaining foos: 3\)
+Destructing Foo\(3\) "automatic_foo" \(remaining foos: 2\)
+Destructing Foo\(2\) "static_foo" \(remaining foos: 1\)
+Destructing Foo\(1\) "static_foo" \(remaining foos: 0\)
diff --git a/ld/testsuite/ld-cdtest/cdtest.dat b/ld/testsuite/ld-cdtest/cdtest.dat
index 39be0dbc2c7..c0bdffb3c26 100644
--- a/ld/testsuite/ld-cdtest/cdtest.dat
+++ b/ld/testsuite/ld-cdtest/cdtest.dat
@@ -1,15 +1,15 @@
-Constructing Foo(1) "static_foo"
-Constructing Foo(2) "static_foo"
-Constructing Foo(3) "automatic_foo"
-Constructing Foo(4) "default-foo"
-Initializing Foo(5) "default-foo" with Foo(4)
-Destructing Foo(4) "default-foo" (remaining foos: 4)
-Constructing Foo(5) "other_foo1"
-Constructing Foo(6) "other_foo2"
-Copying Foo(5) "other_foo1" to Foo(6)
-Destructing Foo(6) "other_foo1" (remaining foos: 5)
-Destructing Foo(5) "other_foo1" (remaining foos: 4)
-Destructing Foo(5) "default-foo" (remaining foos: 3)
-Destructing Foo(3) "automatic_foo" (remaining foos: 2)
-Destructing Foo(2) "static_foo" (remaining foos: 1)
-Destructing Foo(1) "static_foo" (remaining foos: 0)
+Constructing Foo\(1\) "static_foo"
+Constructing Foo\(2\) "static_foo"
+Constructing Foo\(3\) "automatic_foo"
+Constructing Foo\(4\) "default-foo"
+Initializing Foo\(5\) "default-foo" with Foo\(4\)
+Destructing Foo\(4\) "default-foo" \(remaining foos: 4\)
+Constructing Foo\(5\) "other_foo1"
+Constructing Foo\(6\) "other_foo2"
+Copying Foo\(5\) "other_foo1" to Foo\(6\)
+Destructing Foo\(6\) "other_foo1" \(remaining foos: 5\)
+Destructing Foo\(5\) "other_foo1" \(remaining foos: 4\)
+Destructing Foo\(5\) "default-foo" \(remaining foos: 3\)
+Destructing Foo\(3\) "automatic_foo" \(remaining foos: 2\)
+Destructing Foo\(2\) "static_foo" \(remaining foos: 1\)
+Destructing Foo\(1\) "static_foo" \(remaining foos: 0\)
diff --git a/ld/testsuite/ld-cdtest/cdtest.exp b/ld/testsuite/ld-cdtest/cdtest.exp
index 89fdd581abb..81547af3c9e 100644
--- a/ld/testsuite/ld-cdtest/cdtest.exp
+++ b/ld/testsuite/ld-cdtest/cdtest.exp
@@ -28,11 +28,7 @@ set test1 "cdtest"
 set test2 "cdtest with -Ur"
 
 # This test requires running the executable generated by ld.
-if ![isnative] {
-    return
-}
-
-if { [which $CXX_FOR_TARGET] == 0 } {
+if { [which $CXX_FOR_TARGET] == 0 || ![check_execution_available] } {
     untested $test1
     untested $test2
     return
@@ -51,44 +47,39 @@ set expected_output "$srcdir/$subdir/cdtest.dat"
 if ![ld_link $CC_FOR_TARGET tmpdir/cdtest "$CFLAGS_FOR_TARGET tmpdir/cdtest-foo.o tmpdir/cdtest-bar.o tmpdir/cdtest-main.o"] {
     fail $test1
 } else {
-    send_log   "tmpdir/cdtest >tmpdir/cdtest.out\n"
-    verbose    "tmpdir/cdtest >tmpdir/cdtest.out"
-    catch "exec tmpdir/cdtest >tmpdir/cdtest.out" exec_output
+    set failed 0
 
-    if ![string match "" $exec_output] then {
+    send_log "Running: tmpdir/cdtest\n"
+    verbose "Running: tmpdir/cdtest"
+    set state [remote_load target tmpdir/cdtest]
+    set status [lindex $state 0]
+    set exec_output [lindex $state 1]
+
+    if { $status != "pass"  } {
 	send_log "$exec_output\n"
 	verbose "$exec_output" 1
-
-	fail $test1
+	set failed 1
     } else {
-	send_log   "diff tmpdir/cdtest.out $expected_output\n"
-	verbose    "diff tmpdir/cdtest.out $expected_output"
-	catch "exec diff tmpdir/cdtest.out $expected_output" exec_output
-	set exec_output [prune_warnings $exec_output]
-
-	if ![string match "" $exec_output] then {
-	    send_log "$exec_output\n"
-	    verbose  "$exec_output" 1
+	set output_filename "tmpdir/cdtest.out"
+	set_file_contents $output_filename $exec_output
 
+	send_log [file_contents $output_filename]
+	verbose [file_contents $output_filename] 2
+	if [regexp_diff $output_filename $expected_output] {
 	    send_log "Checking against Named Return Value optimization\n"
 	    verbose  "Checking against Named Return Value optimization" 1
 
 	    set expected_output "$srcdir/$subdir/cdtest-nrv.dat"
-
-	    send_log   "diff tmpdir/cdtest.out $expected_output\n"
-	    verbose    "diff tmpdir/cdtest.out $expected_output"
-	    catch "exec diff tmpdir/cdtest.out $expected_output" exec_output
-	    set exec_output [prune_warnings $exec_output]
+	    if [regexp_diff $output_filename $expected_output] {
+		set failed 1
+	    }
 	}
+    }
 
-	if [string match "" $exec_output] then {
-	    pass $test1
-	} else {
-	    send_log "$exec_output\n"
-	    verbose  "$exec_output" 1
-
-	    fail $test1
-	}
+    if { $failed != 0 } {
+	fail $test1
+    } else {
+	pass $test1
     }
 }
 
@@ -103,29 +94,33 @@ if ![ld_relocate $ld tmpdir/cdtest.o {-Ur tmpdir/cdtest-foo.o tmpdir/cdtest-bar.
     if ![ld_link $CC_FOR_TARGET tmpdir/cdtest "$CFLAGS_FOR_TARGET tmpdir/cdtest.o"] {
 	fail $test2
     } else {
-	send_log   "tmpdir/cdtest >tmpdir/cdtest.out\n"
-	verbose    "tmpdir/cdtest >tmpdir/cdtest.out"
-	catch "exec tmpdir/cdtest >tmpdir/cdtest.out" exec_output
+	set failed 0
+
+	send_log "Running: tmpdir/cdtest\n"
+	verbose "Running: tmpdir/cdtest"
+	set state [remote_load target tmpdir/cdtest]
+	set status [lindex $state 0]
+	set exec_output [lindex $state 1]
 
-	if ![string match "" $exec_output] then {
+	if { $status != "pass" } {
 	    send_log "$exec_output\n"
-	    verbose  "$exec_output" 1
+	    verbose "$exec_output" 1
+	    set failed 1
+	} else {
+	    set output_filename "tmpdir/cdtest.out"
+	    set_file_contents $output_filename $exec_output
 
+	    send_log [file_contents $output_filename]
+	    verbose [file_contents $output_filename] 2
+	    if [regexp_diff $output_filename $expected_output] {
+		set failed 1
+	    }
+	}
+
+	if { $failed != 0 } {
 	    fail $test2
 	} else {
-	    send_log   "diff tmpdir/cdtest.out $expected_output\n"
-	    verbose    "diff tmpdir/cdtest.out $expected_output"
-	    catch "exec diff tmpdir/cdtest.out $expected_output" exec_output
-	    set exec_output [prune_warnings $exec_output]
-
-	    if [string match "" $exec_output] then {
-		pass $test2
-	    } else {
-		send_log "$exec_output\n"
-		verbose  "$exec_output" 1
-
-		fail $test2
-	    }
+	    pass $test2
 	}
     }
 }
-- 
2.43.0


From chigot@adacore.com  Thu Jun 18 08:01:54 2026
From: chigot@adacore.com (=?UTF-8?Q?Cl=C3=A9ment_Chigot?=)
Date: Thu, 18 Jun 2026 10:01:54 +0200
Subject: [PATCH] ld/testsuite: add support for remote testing in ld-cdtest
In-Reply-To: <ajKmS_DmAhoG944I@squeak.grove.modra.org>
References: <20260529135252.2094804-1-chigot@adacore.com>
 <CAJ307Eh2qzm1uc+yJoPSEt3LbYBM0bfwQo2fyTxVJS2H5jmP4Q@mail.gmail.com>
 <ajHztSbdug8aSbFp@squeak.grove.modra.org>
 <ajH3_gntvteiUKnO@squeak.grove.modra.org>
 <CAJ307Ej+u3vDMj+kvaRGf8P=te411=5txT96OayZBcxXr_ogPg@mail.gmail.com>
 <ajKmS_DmAhoG944I@squeak.grove.modra.org>
Message-ID: <CAJ307EiDKPi0KaQGHymk8ZExCgsKAHfQGJUd_uanf_nYt61k6g@mail.gmail.com>

On Wed, Jun 17, 2026 at 3:51?PM Alan Modra <amodra@gmail.com> wrote:
>
> On Wed, Jun 17, 2026 at 09:05:44AM +0200, Cl?ment Chigot wrote:
> > On Wed, Jun 17, 2026 at 3:27?AM Alan Modra <amodra@gmail.com> wrote:
> > >
> > > Typical log file shows:
> > > Running: tmpdir/cdtest
> > > Setting LD_LIBRARY_PATH to :
> > > Execution timeout is: 300
> > > spawn [open ...]
> > > tmpdir/cdtest: 1:  ELF       @ ?4H@  4: not found
> > > tmpdir/cdtest: 2: Syntax error: word unexpected (expecting ")")
> > > tmpdir/cdtest: 1:  ELF       @ ?4H@  4: not found
> > > tmpdir/cdtest: 2: Syntax error: word unexpected (expecting ")")
> > >
> > > FAIL: cdtest
> >
> > Hum indeed. I don't see those errors during our internal testing
> > (using remote obviously) nor when I've tried with master on my laptop
> > (x86_64-linux-gnu but it seems ok on our side too).
> > I'll investigate.
>
> I was testing without any remote.

Yeah that's the issue. Those tests still need to be skipped when
execution (remotely or locally) is unavailable.
I've sent v2 and cc @macro@redhat.com, you did something similar afterall.

Cl?ment

> > Thanks
> > Cl?ment
> >
> > > Alan Modra
>
> --
> Alan Modra

From chigot@adacore.com  Thu Jun 18 08:04:43 2026
From: chigot@adacore.com (=?UTF-8?Q?Cl=C3=A9ment_Chigot?=)
Date: Thu, 18 Jun 2026 10:04:43 +0200
Subject: [PATCH v2] ld/testsuite: add support for remote testing in
 ld-cdtest
In-Reply-To: <20260618075856.2258643-1-chigot@adacore.com>
References: <20260618075856.2258643-1-chigot@adacore.com>
Message-ID: <CAJ307EghSg-BPajFHCG-3HqA5VF0FwoEoE92CMfNW5WWMqu4ug@mail.gmail.com>

On Thu, Jun 18, 2026 at 9:58?AM Cl?ment Chigot <chigot@adacore.com> wrote:
>
> This converts the existing to code to use "remote_load" allowing
> execution on both native and remote targets.
>
> The "diff" between the output and the expected result has been
> transformed to the usual regexp_diff. The previous could have been
> transformed into `remote_exec build diff` but tends to be fickled with
> new lines.

Arf got Maciej's Redhat email rejected. Trying with macro@orcam.me.uk.

> ---
>  ld/testsuite/ld-cdtest/cdtest-nrv.dat | 26 ++++----
>  ld/testsuite/ld-cdtest/cdtest.dat     | 30 ++++-----
>  ld/testsuite/ld-cdtest/cdtest.exp     | 95 +++++++++++++--------------
>  3 files changed, 73 insertions(+), 78 deletions(-)
>
> diff --git a/ld/testsuite/ld-cdtest/cdtest-nrv.dat b/ld/testsuite/ld-cdtest/cdtest-nrv.dat
> index d3f871ff108..76fcbaa03d4 100644
> --- a/ld/testsuite/ld-cdtest/cdtest-nrv.dat
> +++ b/ld/testsuite/ld-cdtest/cdtest-nrv.dat
> @@ -1,13 +1,13 @@
> -Constructing Foo(1) "static_foo"
> -Constructing Foo(2) "static_foo"
> -Constructing Foo(3) "automatic_foo"
> -Constructing Foo(4) "default-foo"
> -Constructing Foo(5) "other_foo1"
> -Constructing Foo(6) "other_foo2"
> -Copying Foo(5) "other_foo1" to Foo(6)
> -Destructing Foo(6) "other_foo1" (remaining foos: 5)
> -Destructing Foo(5) "other_foo1" (remaining foos: 4)
> -Destructing Foo(4) "default-foo" (remaining foos: 3)
> -Destructing Foo(3) "automatic_foo" (remaining foos: 2)
> -Destructing Foo(2) "static_foo" (remaining foos: 1)
> -Destructing Foo(1) "static_foo" (remaining foos: 0)
> +Constructing Foo\(1\) "static_foo"
> +Constructing Foo\(2\) "static_foo"
> +Constructing Foo\(3\) "automatic_foo"
> +Constructing Foo\(4\) "default-foo"
> +Constructing Foo\(5\) "other_foo1"
> +Constructing Foo\(6\) "other_foo2"
> +Copying Foo\(5\) "other_foo1" to Foo\(6\)
> +Destructing Foo\(6\) "other_foo1" \(remaining foos: 5\)
> +Destructing Foo\(5\) "other_foo1" \(remaining foos: 4\)
> +Destructing Foo\(4\) "default-foo" \(remaining foos: 3\)
> +Destructing Foo\(3\) "automatic_foo" \(remaining foos: 2\)
> +Destructing Foo\(2\) "static_foo" \(remaining foos: 1\)
> +Destructing Foo\(1\) "static_foo" \(remaining foos: 0\)
> diff --git a/ld/testsuite/ld-cdtest/cdtest.dat b/ld/testsuite/ld-cdtest/cdtest.dat
> index 39be0dbc2c7..c0bdffb3c26 100644
> --- a/ld/testsuite/ld-cdtest/cdtest.dat
> +++ b/ld/testsuite/ld-cdtest/cdtest.dat
> @@ -1,15 +1,15 @@
> -Constructing Foo(1) "static_foo"
> -Constructing Foo(2) "static_foo"
> -Constructing Foo(3) "automatic_foo"
> -Constructing Foo(4) "default-foo"
> -Initializing Foo(5) "default-foo" with Foo(4)
> -Destructing Foo(4) "default-foo" (remaining foos: 4)
> -Constructing Foo(5) "other_foo1"
> -Constructing Foo(6) "other_foo2"
> -Copying Foo(5) "other_foo1" to Foo(6)
> -Destructing Foo(6) "other_foo1" (remaining foos: 5)
> -Destructing Foo(5) "other_foo1" (remaining foos: 4)
> -Destructing Foo(5) "default-foo" (remaining foos: 3)
> -Destructing Foo(3) "automatic_foo" (remaining foos: 2)
> -Destructing Foo(2) "static_foo" (remaining foos: 1)
> -Destructing Foo(1) "static_foo" (remaining foos: 0)
> +Constructing Foo\(1\) "static_foo"
> +Constructing Foo\(2\) "static_foo"
> +Constructing Foo\(3\) "automatic_foo"
> +Constructing Foo\(4\) "default-foo"
> +Initializing Foo\(5\) "default-foo" with Foo\(4\)
> +Destructing Foo\(4\) "default-foo" \(remaining foos: 4\)
> +Constructing Foo\(5\) "other_foo1"
> +Constructing Foo\(6\) "other_foo2"
> +Copying Foo\(5\) "other_foo1" to Foo\(6\)
> +Destructing Foo\(6\) "other_foo1" \(remaining foos: 5\)
> +Destructing Foo\(5\) "other_foo1" \(remaining foos: 4\)
> +Destructing Foo\(5\) "default-foo" \(remaining foos: 3\)
> +Destructing Foo\(3\) "automatic_foo" \(remaining foos: 2\)
> +Destructing Foo\(2\) "static_foo" \(remaining foos: 1\)
> +Destructing Foo\(1\) "static_foo" \(remaining foos: 0\)
> diff --git a/ld/testsuite/ld-cdtest/cdtest.exp b/ld/testsuite/ld-cdtest/cdtest.exp
> index 89fdd581abb..81547af3c9e 100644
> --- a/ld/testsuite/ld-cdtest/cdtest.exp
> +++ b/ld/testsuite/ld-cdtest/cdtest.exp
> @@ -28,11 +28,7 @@ set test1 "cdtest"
>  set test2 "cdtest with -Ur"
>
>  # This test requires running the executable generated by ld.
> -if ![isnative] {
> -    return
> -}
> -
> -if { [which $CXX_FOR_TARGET] == 0 } {
> +if { [which $CXX_FOR_TARGET] == 0 || ![check_execution_available] } {
>      untested $test1
>      untested $test2
>      return
> @@ -51,44 +47,39 @@ set expected_output "$srcdir/$subdir/cdtest.dat"
>  if ![ld_link $CC_FOR_TARGET tmpdir/cdtest "$CFLAGS_FOR_TARGET tmpdir/cdtest-foo.o tmpdir/cdtest-bar.o tmpdir/cdtest-main.o"] {
>      fail $test1
>  } else {
> -    send_log   "tmpdir/cdtest >tmpdir/cdtest.out\n"
> -    verbose    "tmpdir/cdtest >tmpdir/cdtest.out"
> -    catch "exec tmpdir/cdtest >tmpdir/cdtest.out" exec_output
> +    set failed 0
>
> -    if ![string match "" $exec_output] then {
> +    send_log "Running: tmpdir/cdtest\n"
> +    verbose "Running: tmpdir/cdtest"
> +    set state [remote_load target tmpdir/cdtest]
> +    set status [lindex $state 0]
> +    set exec_output [lindex $state 1]
> +
> +    if { $status != "pass"  } {
>         send_log "$exec_output\n"
>         verbose "$exec_output" 1
> -
> -       fail $test1
> +       set failed 1
>      } else {
> -       send_log   "diff tmpdir/cdtest.out $expected_output\n"
> -       verbose    "diff tmpdir/cdtest.out $expected_output"
> -       catch "exec diff tmpdir/cdtest.out $expected_output" exec_output
> -       set exec_output [prune_warnings $exec_output]
> -
> -       if ![string match "" $exec_output] then {
> -           send_log "$exec_output\n"
> -           verbose  "$exec_output" 1
> +       set output_filename "tmpdir/cdtest.out"
> +       set_file_contents $output_filename $exec_output
>
> +       send_log [file_contents $output_filename]
> +       verbose [file_contents $output_filename] 2
> +       if [regexp_diff $output_filename $expected_output] {
>             send_log "Checking against Named Return Value optimization\n"
>             verbose  "Checking against Named Return Value optimization" 1
>
>             set expected_output "$srcdir/$subdir/cdtest-nrv.dat"
> -
> -           send_log   "diff tmpdir/cdtest.out $expected_output\n"
> -           verbose    "diff tmpdir/cdtest.out $expected_output"
> -           catch "exec diff tmpdir/cdtest.out $expected_output" exec_output
> -           set exec_output [prune_warnings $exec_output]
> +           if [regexp_diff $output_filename $expected_output] {
> +               set failed 1
> +           }
>         }
> +    }
>
> -       if [string match "" $exec_output] then {
> -           pass $test1
> -       } else {
> -           send_log "$exec_output\n"
> -           verbose  "$exec_output" 1
> -
> -           fail $test1
> -       }
> +    if { $failed != 0 } {
> +       fail $test1
> +    } else {
> +       pass $test1
>      }
>  }
>
> @@ -103,29 +94,33 @@ if ![ld_relocate $ld tmpdir/cdtest.o {-Ur tmpdir/cdtest-foo.o tmpdir/cdtest-bar.
>      if ![ld_link $CC_FOR_TARGET tmpdir/cdtest "$CFLAGS_FOR_TARGET tmpdir/cdtest.o"] {
>         fail $test2
>      } else {
> -       send_log   "tmpdir/cdtest >tmpdir/cdtest.out\n"
> -       verbose    "tmpdir/cdtest >tmpdir/cdtest.out"
> -       catch "exec tmpdir/cdtest >tmpdir/cdtest.out" exec_output
> +       set failed 0
> +
> +       send_log "Running: tmpdir/cdtest\n"
> +       verbose "Running: tmpdir/cdtest"
> +       set state [remote_load target tmpdir/cdtest]
> +       set status [lindex $state 0]
> +       set exec_output [lindex $state 1]
>
> -       if ![string match "" $exec_output] then {
> +       if { $status != "pass" } {
>             send_log "$exec_output\n"
> -           verbose  "$exec_output" 1
> +           verbose "$exec_output" 1
> +           set failed 1
> +       } else {
> +           set output_filename "tmpdir/cdtest.out"
> +           set_file_contents $output_filename $exec_output
>
> +           send_log [file_contents $output_filename]
> +           verbose [file_contents $output_filename] 2
> +           if [regexp_diff $output_filename $expected_output] {
> +               set failed 1
> +           }
> +       }
> +
> +       if { $failed != 0 } {
>             fail $test2
>         } else {
> -           send_log   "diff tmpdir/cdtest.out $expected_output\n"
> -           verbose    "diff tmpdir/cdtest.out $expected_output"
> -           catch "exec diff tmpdir/cdtest.out $expected_output" exec_output
> -           set exec_output [prune_warnings $exec_output]
> -
> -           if [string match "" $exec_output] then {
> -               pass $test2
> -           } else {
> -               send_log "$exec_output\n"
> -               verbose  "$exec_output" 1
> -
> -               fail $test2
> -           }
> +           pass $test2
>         }
>      }
>  }
> --
> 2.43.0
>

On Thu, Jun 18, 2026 at 9:58?AM Cl?ment Chigot <chigot@adacore.com> wrote:
>
> This converts the existing to code to use "remote_load" allowing
> execution on both native and remote targets.
>
> The "diff" between the output and the expected result has been
> transformed to the usual regexp_diff. The previous could have been
> transformed into `remote_exec build diff` but tends to be fickled with
> new lines.
> ---
>  ld/testsuite/ld-cdtest/cdtest-nrv.dat | 26 ++++----
>  ld/testsuite/ld-cdtest/cdtest.dat     | 30 ++++-----
>  ld/testsuite/ld-cdtest/cdtest.exp     | 95 +++++++++++++--------------
>  3 files changed, 73 insertions(+), 78 deletions(-)
>
> diff --git a/ld/testsuite/ld-cdtest/cdtest-nrv.dat b/ld/testsuite/ld-cdtest/cdtest-nrv.dat
> index d3f871ff108..76fcbaa03d4 100644
> --- a/ld/testsuite/ld-cdtest/cdtest-nrv.dat
> +++ b/ld/testsuite/ld-cdtest/cdtest-nrv.dat
> @@ -1,13 +1,13 @@
> -Constructing Foo(1) "static_foo"
> -Constructing Foo(2) "static_foo"
> -Constructing Foo(3) "automatic_foo"
> -Constructing Foo(4) "default-foo"
> -Constructing Foo(5) "other_foo1"
> -Constructing Foo(6) "other_foo2"
> -Copying Foo(5) "other_foo1" to Foo(6)
> -Destructing Foo(6) "other_foo1" (remaining foos: 5)
> -Destructing Foo(5) "other_foo1" (remaining foos: 4)
> -Destructing Foo(4) "default-foo" (remaining foos: 3)
> -Destructing Foo(3) "automatic_foo" (remaining foos: 2)
> -Destructing Foo(2) "static_foo" (remaining foos: 1)
> -Destructing Foo(1) "static_foo" (remaining foos: 0)
> +Constructing Foo\(1\) "static_foo"
> +Constructing Foo\(2\) "static_foo"
> +Constructing Foo\(3\) "automatic_foo"
> +Constructing Foo\(4\) "default-foo"
> +Constructing Foo\(5\) "other_foo1"
> +Constructing Foo\(6\) "other_foo2"
> +Copying Foo\(5\) "other_foo1" to Foo\(6\)
> +Destructing Foo\(6\) "other_foo1" \(remaining foos: 5\)
> +Destructing Foo\(5\) "other_foo1" \(remaining foos: 4\)
> +Destructing Foo\(4\) "default-foo" \(remaining foos: 3\)
> +Destructing Foo\(3\) "automatic_foo" \(remaining foos: 2\)
> +Destructing Foo\(2\) "static_foo" \(remaining foos: 1\)
> +Destructing Foo\(1\) "static_foo" \(remaining foos: 0\)
> diff --git a/ld/testsuite/ld-cdtest/cdtest.dat b/ld/testsuite/ld-cdtest/cdtest.dat
> index 39be0dbc2c7..c0bdffb3c26 100644
> --- a/ld/testsuite/ld-cdtest/cdtest.dat
> +++ b/ld/testsuite/ld-cdtest/cdtest.dat
> @@ -1,15 +1,15 @@
> -Constructing Foo(1) "static_foo"
> -Constructing Foo(2) "static_foo"
> -Constructing Foo(3) "automatic_foo"
> -Constructing Foo(4) "default-foo"
> -Initializing Foo(5) "default-foo" with Foo(4)
> -Destructing Foo(4) "default-foo" (remaining foos: 4)
> -Constructing Foo(5) "other_foo1"
> -Constructing Foo(6) "other_foo2"
> -Copying Foo(5) "other_foo1" to Foo(6)
> -Destructing Foo(6) "other_foo1" (remaining foos: 5)
> -Destructing Foo(5) "other_foo1" (remaining foos: 4)
> -Destructing Foo(5) "default-foo" (remaining foos: 3)
> -Destructing Foo(3) "automatic_foo" (remaining foos: 2)
> -Destructing Foo(2) "static_foo" (remaining foos: 1)
> -Destructing Foo(1) "static_foo" (remaining foos: 0)
> +Constructing Foo\(1\) "static_foo"
> +Constructing Foo\(2\) "static_foo"
> +Constructing Foo\(3\) "automatic_foo"
> +Constructing Foo\(4\) "default-foo"
> +Initializing Foo\(5\) "default-foo" with Foo\(4\)
> +Destructing Foo\(4\) "default-foo" \(remaining foos: 4\)
> +Constructing Foo\(5\) "other_foo1"
> +Constructing Foo\(6\) "other_foo2"
> +Copying Foo\(5\) "other_foo1" to Foo\(6\)
> +Destructing Foo\(6\) "other_foo1" \(remaining foos: 5\)
> +Destructing Foo\(5\) "other_foo1" \(remaining foos: 4\)
> +Destructing Foo\(5\) "default-foo" \(remaining foos: 3\)
> +Destructing Foo\(3\) "automatic_foo" \(remaining foos: 2\)
> +Destructing Foo\(2\) "static_foo" \(remaining foos: 1\)
> +Destructing Foo\(1\) "static_foo" \(remaining foos: 0\)
> diff --git a/ld/testsuite/ld-cdtest/cdtest.exp b/ld/testsuite/ld-cdtest/cdtest.exp
> index 89fdd581abb..81547af3c9e 100644
> --- a/ld/testsuite/ld-cdtest/cdtest.exp
> +++ b/ld/testsuite/ld-cdtest/cdtest.exp
> @@ -28,11 +28,7 @@ set test1 "cdtest"
>  set test2 "cdtest with -Ur"
>
>  # This test requires running the executable generated by ld.
> -if ![isnative] {
> -    return
> -}
> -
> -if { [which $CXX_FOR_TARGET] == 0 } {
> +if { [which $CXX_FOR_TARGET] == 0 || ![check_execution_available] } {
>      untested $test1
>      untested $test2
>      return
> @@ -51,44 +47,39 @@ set expected_output "$srcdir/$subdir/cdtest.dat"
>  if ![ld_link $CC_FOR_TARGET tmpdir/cdtest "$CFLAGS_FOR_TARGET tmpdir/cdtest-foo.o tmpdir/cdtest-bar.o tmpdir/cdtest-main.o"] {
>      fail $test1
>  } else {
> -    send_log   "tmpdir/cdtest >tmpdir/cdtest.out\n"
> -    verbose    "tmpdir/cdtest >tmpdir/cdtest.out"
> -    catch "exec tmpdir/cdtest >tmpdir/cdtest.out" exec_output
> +    set failed 0
>
> -    if ![string match "" $exec_output] then {
> +    send_log "Running: tmpdir/cdtest\n"
> +    verbose "Running: tmpdir/cdtest"
> +    set state [remote_load target tmpdir/cdtest]
> +    set status [lindex $state 0]
> +    set exec_output [lindex $state 1]
> +
> +    if { $status != "pass"  } {
>         send_log "$exec_output\n"
>         verbose "$exec_output" 1
> -
> -       fail $test1
> +       set failed 1
>      } else {
> -       send_log   "diff tmpdir/cdtest.out $expected_output\n"
> -       verbose    "diff tmpdir/cdtest.out $expected_output"
> -       catch "exec diff tmpdir/cdtest.out $expected_output" exec_output
> -       set exec_output [prune_warnings $exec_output]
> -
> -       if ![string match "" $exec_output] then {
> -           send_log "$exec_output\n"
> -           verbose  "$exec_output" 1
> +       set output_filename "tmpdir/cdtest.out"
> +       set_file_contents $output_filename $exec_output
>
> +       send_log [file_contents $output_filename]
> +       verbose [file_contents $output_filename] 2
> +       if [regexp_diff $output_filename $expected_output] {
>             send_log "Checking against Named Return Value optimization\n"
>             verbose  "Checking against Named Return Value optimization" 1
>
>             set expected_output "$srcdir/$subdir/cdtest-nrv.dat"
> -
> -           send_log   "diff tmpdir/cdtest.out $expected_output\n"
> -           verbose    "diff tmpdir/cdtest.out $expected_output"
> -           catch "exec diff tmpdir/cdtest.out $expected_output" exec_output
> -           set exec_output [prune_warnings $exec_output]
> +           if [regexp_diff $output_filename $expected_output] {
> +               set failed 1
> +           }
>         }
> +    }
>
> -       if [string match "" $exec_output] then {
> -           pass $test1
> -       } else {
> -           send_log "$exec_output\n"
> -           verbose  "$exec_output" 1
> -
> -           fail $test1
> -       }
> +    if { $failed != 0 } {
> +       fail $test1
> +    } else {
> +       pass $test1
>      }
>  }
>
> @@ -103,29 +94,33 @@ if ![ld_relocate $ld tmpdir/cdtest.o {-Ur tmpdir/cdtest-foo.o tmpdir/cdtest-bar.
>      if ![ld_link $CC_FOR_TARGET tmpdir/cdtest "$CFLAGS_FOR_TARGET tmpdir/cdtest.o"] {
>         fail $test2
>      } else {
> -       send_log   "tmpdir/cdtest >tmpdir/cdtest.out\n"
> -       verbose    "tmpdir/cdtest >tmpdir/cdtest.out"
> -       catch "exec tmpdir/cdtest >tmpdir/cdtest.out" exec_output
> +       set failed 0
> +
> +       send_log "Running: tmpdir/cdtest\n"
> +       verbose "Running: tmpdir/cdtest"
> +       set state [remote_load target tmpdir/cdtest]
> +       set status [lindex $state 0]
> +       set exec_output [lindex $state 1]
>
> -       if ![string match "" $exec_output] then {
> +       if { $status != "pass" } {
>             send_log "$exec_output\n"
> -           verbose  "$exec_output" 1
> +           verbose "$exec_output" 1
> +           set failed 1
> +       } else {
> +           set output_filename "tmpdir/cdtest.out"
> +           set_file_contents $output_filename $exec_output
>
> +           send_log [file_contents $output_filename]
> +           verbose [file_contents $output_filename] 2
> +           if [regexp_diff $output_filename $expected_output] {
> +               set failed 1
> +           }
> +       }
> +
> +       if { $failed != 0 } {
>             fail $test2
>         } else {
> -           send_log   "diff tmpdir/cdtest.out $expected_output\n"
> -           verbose    "diff tmpdir/cdtest.out $expected_output"
> -           catch "exec diff tmpdir/cdtest.out $expected_output" exec_output
> -           set exec_output [prune_warnings $exec_output]
> -
> -           if [string match "" $exec_output] then {
> -               pass $test2
> -           } else {
> -               send_log "$exec_output\n"
> -               verbose  "$exec_output" 1
> -
> -               fail $test2
> -           }
> +           pass $test2
>         }
>      }
>  }
> --
> 2.43.0
>

From amodra@gmail.com  Thu Jun 18 09:26:30 2026
From: amodra@gmail.com (Alan Modra)
Date: Thu, 18 Jun 2026 18:56:30 +0930
Subject: [PATCH] ld/testsuite: add support for remote testing in ld-cdtest
In-Reply-To: <CAJ307EiDKPi0KaQGHymk8ZExCgsKAHfQGJUd_uanf_nYt61k6g@mail.gmail.com>
References: <20260529135252.2094804-1-chigot@adacore.com>
 <CAJ307Eh2qzm1uc+yJoPSEt3LbYBM0bfwQo2fyTxVJS2H5jmP4Q@mail.gmail.com>
 <ajHztSbdug8aSbFp@squeak.grove.modra.org>
 <ajH3_gntvteiUKnO@squeak.grove.modra.org>
 <CAJ307Ej+u3vDMj+kvaRGf8P=te411=5txT96OayZBcxXr_ogPg@mail.gmail.com>
 <ajKmS_DmAhoG944I@squeak.grove.modra.org>
 <CAJ307EiDKPi0KaQGHymk8ZExCgsKAHfQGJUd_uanf_nYt61k6g@mail.gmail.com>
Message-ID: <ajO5xsYcVVQ68kef@squeak.grove.modra.org>

On Thu, Jun 18, 2026 at 10:01:54AM +0200, Cl?ment Chigot wrote:
> On Wed, Jun 17, 2026 at 3:51?PM Alan Modra <amodra@gmail.com> wrote:
> > I was testing without any remote.
> 
> Yeah that's the issue. Those tests still need to be skipped when
> execution (remotely or locally) is unavailable.
> I've sent v2 and cc @macro@redhat.com, you did something similar afterall.

This version doesn't regress for me.

-- 
Alan Modra

From abhay@linux.ibm.com  Thu Jun 18 10:15:29 2026
From: abhay@linux.ibm.com (Abhay Kandpal)
Date: Thu, 18 Jun 2026 15:45:29 +0530
Subject: =?UTF-8?Q?Re=3A_Nominations_for_Anthropic=E2=80=99s_Claude_for_Open?=
 =?UTF-8?Q?_Source_program?=
In-Reply-To: <CAGWvnykaUiiAPY8sMFAGu83ObWzChqp1Jk8BDwjy7tFedkd0Bg@mail.gmail.com>
References: <CAGWvnykaUiiAPY8sMFAGu83ObWzChqp1Jk8BDwjy7tFedkd0Bg@mail.gmail.com>
Message-ID: <7d909c5c-e452-4574-b4af-11a3275b7d11@linux.ibm.com>

Hi David,

I would like to be considered for the Claude for Open Source program.

Binutils &I am an active contributor to the GNU Toolchain ecosystem, 
working primarily on PowerPC support acrossGDB. I would use Claude for 
bug triage, code exploration, patch review, and investigating 
interactions across toolchain components. I believe it would help 
improve productivity and accelerate analysis and resolution of issues 
affecting the GNU Toolchain.

Thank you for considering my nomination.

Regards,
Abhay Kandpal


On 13/06/26 00:54, David Edelsohn wrote:
> Developers, Anthropic is generously offering 6 months of Claude Max 
> 20x to Free and Open Source Software projects to support the FOSS 
> ecosystem. These tools can be incredibly helpful with reviewing 
> upstream code, evaluating the conformance of
> 
> Developers,
>
> Anthropic is generously offering 6 months of Claude Max 20x to Free 
> and Open
> Source Software projects to support the FOSS ecosystem. These tools can be
> incredibly helpful with reviewing upstream code, evaluating the 
> conformance of
> a particular interface to a standard, or just for your own learning and
> exploring the implementation of the project or subsystem.
>
> If you are an established, active contributor to the GNU Toolchain and are
> interested in having access to Claude Max 20x under Anthropic?s Claude 
> for Open
> Source program, please respond to this email thread with a short 
> description of
> how you would utilize the access and the potential impact on the GNU 
> Toolchain.
> The program's slots are limited and Carlos O'Donell and I plan to 
> review the
> proposals. Please keep in mind that these are individual grants from 
> Anthropic
> to you personally. If you are approved you?ll get an email from 
> Anthropic with
> further instructions.
>
> While the current GNU Project policy is not to accept LLM-generated 
> content in
> the projects, that still leaves other uses like bug triage, patch 
> review, and
> research as ways to use these tools.
>
> Cheers, David
>
> P.S. This is not an endorsement of Anthropic, Claude or LLMs. We dislike
> having to say it, but please don?t use this thread as a platform to 
> express
> your personal opinions about the companies or about AI?s impact on the 
> world.
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From hjl.tools@gmail.com  Thu Jun 18 12:05:37 2026
From: hjl.tools@gmail.com (H.J. Lu)
Date: Thu, 18 Jun 2026 20:05:37 +0800
Subject: [PATCH] ld: Use 0x10000 as absolute symbol value in PR ld/25754 tests
Message-ID: <CAMe9rOomM1cKXNZLU0A60xe8cc45zHgZdiKqZOtH2ephQUhwEQ@mail.gmail.com>

PR ld/25754 tests verify that relocations against absolute symbol are
properly handled, using 42 as the absolute symbol value.  But GCC 17
treats 42 as the impossible symbol address, which is the absolute symbol
value and optimize out the symbol address check:

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125869

Use 0x10000, instead of 42, as absolute symbol value to work with GCC 17.

PR ld/34298
* testsuite/ld-elf/pr25754-1a.c (main): Check against 0x10000
instead of 42.
* testsuite/ld-elf/pr25754-1b.s (bar): Replace 42 with 0x10000.

-- 
H.J.
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From jbeulich@suse.com  Thu Jun 18 12:19:46 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Thu, 18 Jun 2026 14:19:46 +0200
Subject: [PATCH] ld: Use 0x10000 as absolute symbol value in PR ld/25754
 tests
In-Reply-To: <CAMe9rOomM1cKXNZLU0A60xe8cc45zHgZdiKqZOtH2ephQUhwEQ@mail.gmail.com>
References: <CAMe9rOomM1cKXNZLU0A60xe8cc45zHgZdiKqZOtH2ephQUhwEQ@mail.gmail.com>
Message-ID: <2e5a4f17-31a2-41f7-9d51-86e9e753a356@suse.com>

On 18.06.2026 14:05, H.J. Lu wrote:
> PR ld/25754 tests verify that relocations against absolute symbol are
> properly handled, using 42 as the absolute symbol value.  But GCC 17
> treats 42 as the impossible symbol address, which is the absolute symbol
> value and optimize out the symbol address check:
> 
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125869
> 
> Use 0x10000, instead of 42, as absolute symbol value to work with GCC 17.
> 
> PR ld/34298
> * testsuite/ld-elf/pr25754-1a.c (main): Check against 0x10000
> instead of 42.
> * testsuite/ld-elf/pr25754-1b.s (bar): Replace 42 with 0x10000.

The binutils bugzilla entry says it's a gcc bug. The gcc bugzilla entry
says it's a flawed testcase in binutils. Which one is it? Depending on
that the description here needs updating. Furthermore you name just 42
here, when in the gcc bugzilla entry you said values up to 0x800 are a
problem.

Jan

From penny.technologyuserdatabase1@gmail.com  Thu Jun 18 19:05:55 2026
From: penny.technologyuserdatabase1@gmail.com (penny.technologyuserdatabase1@gmail.com)
Date: Thu, 18 Jun 2026 14:05:55 -0500
Subject: ASEE - Approved Mailing Database
In-Reply-To: <0e2101dcfdbc$5061add0$f1250970$@gmail.com>
References: <0e2101dcfdbc$5061add0$f1250970$@gmail.com>
Message-ID: <031301dcff55$9e55abf0$db0103d0$@gmail.com>

 
 
Hi,
 
Hope you're well and safe. Just wanted to check if there are any updates for
me regarding list purchase?
 
I look forward to your response.
 
Thanks!
Penny
 
From: penny.technologyuserdatabase1@gmail.com
<penny.technologyuserdatabase1@gmail.com> 
Sent: 16 June 2026 01:16 PM
To: binutils@sourceware.org
Subject: ASEE - Approved Mailing Database
Importance: High
 
Hi,
 
The American Society for Engineering Education Annual Conference 2026
Contact Mailing List is now available.
 
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promotion | Reach targeted prospects via email and phone | Lead generation
and business development | and more!
 
Please reply with one of the options below:
 
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2 - Please remove me from this mailing list.
 
Looking forward to helping you grow your business.
 
Regards,
Penny Albritton
ASEE - Business Executive
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From sivan.shani@arm.com  Thu Jun 18 19:55:04 2026
From: sivan.shani@arm.com (Sivan Shani)
Date: Thu, 18 Jun 2026 19:55:04 +0000
Subject: [PATCH v4] gas: arm: Support CPU-specific extensions with -mcpu
Message-ID: <20260618195504.620749-1-sivan.shani@arm.com>

Previously, +ext/+noext feature modifiers were only available with
-march. Extend the same mechanism to -mcpu so that CPU-specific
extensions can be enabled and disabled with -mcpu=<cpu>+ext and
-mcpu=<cpu>+noext, matching GCC behaviour.

Add a per-CPU extension table (arm_ext_table) and a new ext_table
field to struct arm_cpu_option_table, reusing the existing
arm_parse_extension () infrastructure used by -march. Move the
ARM_EXT/ARM_ADD/ARM_REMOVE helpers, the ALL_FP/ALL_SIMD/ALL_FP_MVE_FP
masks and the CDE_EXTENSIONS list so they can be shared by both
-mcpu and -march extension tables.

Update ARM CPU feature definitions to match GCC CPU baselines. The
default feature set for each -mcpu remains unchanged; only support for
+ext/+noext modifiers is added.

Add tests covering supported CPU extension modifiers and the resulting
build attributes for each CPU.

gas/
    * config/tc-arm.c (struct arm_cpu_option_table): Add ext_table
    field.
    (ARM_EXT, ARM_ADD, ARM_REMOVE, ALL_FP, ALL_SIMD,
    ALL_FP_MVE_FP, CDE_EXTENSIONS): Move earlier.
    (cortex_*_ext_table, ...): New.
    (arm_cpus): Populate ext_table and update CPU feature baselines
    to match GCC.
    (arm_parse_cpu): Pass opt->ext_table to arm_parse_extension.

gas/testsuite/
    * gas/arm/feat-*.s: New test sources.
    * gas/arm/mcpu-*.d: New tests.
    * gas/arm/attr-cpu-directive.d: Update.

###
This version address the review comments from:
Message-ID: <2846ac09-3590-409d-8ecf-cc385c8929e8@arm.com>
https://inbox.sourceware.org/binutils/2846ac09-3590-409d-8ecf-cc385c8929e8@arm.com/
###

---
 gas/config/tc-arm.c                           | 699 ++++++++++++++----
 gas/testsuite/gas/arm/attr-cpu-directive.d    |   2 +
 gas/testsuite/gas/arm/feat-bf16.s             |   5 +
 gas/testsuite/gas/arm/feat-crc.s              |   4 +
 gas/testsuite/gas/arm/feat-dotprod.s          |   4 +
 gas/testsuite/gas/arm/feat-dsp.s              |   4 +
 gas/testsuite/gas/arm/feat-fp-vfpv3.s         |   4 +
 gas/testsuite/gas/arm/feat-fp-vfpv5.s         |   4 +
 gas/testsuite/gas/arm/feat-fp.dp.s            |   4 +
 gas/testsuite/gas/arm/feat-fp.s               |   4 +
 gas/testsuite/gas/arm/feat-fp16.s             |   4 +
 gas/testsuite/gas/arm/feat-i8mm.s             |   4 +
 gas/testsuite/gas/arm/feat-idiv.s             |   3 +
 gas/testsuite/gas/arm/feat-mp.s               |   4 +
 gas/testsuite/gas/arm/feat-mve.fp.s           |   5 +
 gas/testsuite/gas/arm/feat-neon-fp16.s        |   4 +
 gas/testsuite/gas/arm/feat-pacbti.s           |   4 +
 gas/testsuite/gas/arm/feat-sec.s              |   4 +
 gas/testsuite/gas/arm/feat-simd.s             |   5 +
 gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s   |   4 +
 gas/testsuite/gas/arm/mcpu-cortex-a12-attrs.d |  17 +
 .../gas/arm/mcpu-cortex-a12-feat-simd.d       |  19 +
 gas/testsuite/gas/arm/mcpu-cortex-a15-attrs.d |  17 +
 .../gas/arm/mcpu-cortex-a15-feat-simd.d       |  19 +
 gas/testsuite/gas/arm/mcpu-cortex-a17-attrs.d |  17 +
 .../gas/arm/mcpu-cortex-a17-feat-simd.d       |  19 +
 gas/testsuite/gas/arm/mcpu-cortex-a32-attrs.d |  16 +
 .../gas/arm/mcpu-cortex-a32-attrs1.d          |  18 +
 .../gas/arm/mcpu-cortex-a32-feat-crc.d        |  18 +
 .../gas/arm/mcpu-cortex-a32-feat-simd.d       |  18 +
 gas/testsuite/gas/arm/mcpu-cortex-a35-attrs.d |  16 +
 .../gas/arm/mcpu-cortex-a35-attrs1.d          |  18 +
 .../gas/arm/mcpu-cortex-a35-feat-crc.d        |  18 +
 .../gas/arm/mcpu-cortex-a35-feat-simd.d       |  18 +
 gas/testsuite/gas/arm/mcpu-cortex-a5-attrs.d  |  16 +
 .../gas/arm/mcpu-cortex-a5-feat-mp.d          |  18 +
 .../gas/arm/mcpu-cortex-a5-feat-neon-fp16.d   |  18 +
 .../gas/arm/mcpu-cortex-a5-feat-sec.d         |  18 +
 gas/testsuite/gas/arm/mcpu-cortex-a53-attrs.d |  16 +
 .../gas/arm/mcpu-cortex-a53-attrs1.d          |  18 +
 .../gas/arm/mcpu-cortex-a53-feat-crc.d        |  18 +
 .../gas/arm/mcpu-cortex-a53-feat-simd.d       |  18 +
 gas/testsuite/gas/arm/mcpu-cortex-a55-attrs.d |  17 +
 .../gas/arm/mcpu-cortex-a55-attrs1.d          |  18 +
 .../gas/arm/mcpu-cortex-a55-feat-dotprod.d    |  18 +
 .../gas/arm/mcpu-cortex-a55-feat-fp16.d       |  18 +
 gas/testsuite/gas/arm/mcpu-cortex-a57-attrs.d |  18 +
 .../gas/arm/mcpu-cortex-a57-feat-crc.d        |  18 +
 .../gas/arm/mcpu-cortex-a57-feat-simd.d       |  18 +
 gas/testsuite/gas/arm/mcpu-cortex-a7-attrs.d  |  17 +
 .../gas/arm/mcpu-cortex-a7-feat-simd.d        |  19 +
 .../gas/arm/mcpu-cortex-a710-attrs.d          |  18 +
 .../gas/arm/mcpu-cortex-a710-feat-bf16.d      |  18 +
 .../gas/arm/mcpu-cortex-a710-feat-fp16.d      |  18 +
 .../gas/arm/mcpu-cortex-a710-feat-i8mm.d      |  18 +
 gas/testsuite/gas/arm/mcpu-cortex-a72-attrs.d |  18 +
 .../gas/arm/mcpu-cortex-a72-feat-crc.d        |  18 +
 .../gas/arm/mcpu-cortex-a72-feat-simd.d       |  18 +
 gas/testsuite/gas/arm/mcpu-cortex-a73-attrs.d |  18 +
 .../gas/arm/mcpu-cortex-a73-feat-crc.d        |  18 +
 .../gas/arm/mcpu-cortex-a73-feat-simd.d       |  18 +
 gas/testsuite/gas/arm/mcpu-cortex-a75-attrs.d |  18 +
 .../gas/arm/mcpu-cortex-a75-feat-dotprod.d    |  18 +
 .../gas/arm/mcpu-cortex-a75-feat-fp16.d       |  18 +
 gas/testsuite/gas/arm/mcpu-cortex-a76-attrs.d |  18 +
 .../gas/arm/mcpu-cortex-a76-feat-dotprod.d    |  18 +
 .../gas/arm/mcpu-cortex-a76-feat-fp16.d       |  18 +
 .../gas/arm/mcpu-cortex-a76ae-attrs.d         |  18 +
 .../gas/arm/mcpu-cortex-a76ae-feat-dotprod.d  |  18 +
 .../gas/arm/mcpu-cortex-a76ae-feat-fp16.d     |  18 +
 gas/testsuite/gas/arm/mcpu-cortex-a77-attrs.d |  18 +
 .../gas/arm/mcpu-cortex-a77-feat-dotprod.d    |  18 +
 .../gas/arm/mcpu-cortex-a77-feat-fp16.d       |  18 +
 gas/testsuite/gas/arm/mcpu-cortex-a78-attrs.d |  18 +
 .../gas/arm/mcpu-cortex-a78-feat-dotprod.d    |  18 +
 .../gas/arm/mcpu-cortex-a78-feat-fp16.d       |  18 +
 .../gas/arm/mcpu-cortex-a78ae-attrs.d         |  18 +
 .../gas/arm/mcpu-cortex-a78ae-feat-dotprod.d  |  18 +
 .../gas/arm/mcpu-cortex-a78ae-feat-fp16.d     |  18 +
 .../gas/arm/mcpu-cortex-a78c-attrs.d          |  18 +
 .../gas/arm/mcpu-cortex-a78c-feat-dotprod.d   |  18 +
 .../gas/arm/mcpu-cortex-a78c-feat-fp16.d      |  18 +
 gas/testsuite/gas/arm/mcpu-cortex-a8-attrs.d  |  15 +
 .../gas/arm/mcpu-cortex-a8-feat-simd.d        |  17 +
 gas/testsuite/gas/arm/mcpu-cortex-a9-attrs.d  |  16 +
 .../gas/arm/mcpu-cortex-a9-feat-mp.d          |  18 +
 .../gas/arm/mcpu-cortex-a9-feat-neon-fp16.d   |  18 +
 .../gas/arm/mcpu-cortex-a9-feat-sec.d         |  18 +
 gas/testsuite/gas/arm/mcpu-cortex-m33-attrs.d |  13 +
 .../gas/arm/mcpu-cortex-m33-feat-dsp.d        |  15 +
 .../gas/arm/mcpu-cortex-m33-feat-fp-vfpv5.d   |  15 +
 .../gas/arm/mcpu-cortex-m35p-attrs.d          |  13 +
 .../gas/arm/mcpu-cortex-m35p-feat-dsp.d       |  15 +
 .../gas/arm/mcpu-cortex-m35p-feat-fp-vfpv5.d  |  15 +
 gas/testsuite/gas/arm/mcpu-cortex-m4-attrs.d  |  13 +
 .../gas/arm/mcpu-cortex-m4-feat-fp-vfpv3.d    |  15 +
 gas/testsuite/gas/arm/mcpu-cortex-m52-attrs.d |  14 +
 .../gas/arm/mcpu-cortex-m52-attrs1.d          |  16 +
 .../gas/arm/mcpu-cortex-m52-feat-fp-dp.d      |  16 +
 .../gas/arm/mcpu-cortex-m52-feat-mve-fp.d     |  16 +
 .../gas/arm/mcpu-cortex-m52-feat-pacbti.d     |  16 +
 gas/testsuite/gas/arm/mcpu-cortex-m55-attrs.d |  14 +
 .../gas/arm/mcpu-cortex-m55-attrs1.d          |  16 +
 .../gas/arm/mcpu-cortex-m55-feat-fp-dp.d      |  16 +
 .../gas/arm/mcpu-cortex-m55-feat-mve-fp.d     |  16 +
 gas/testsuite/gas/arm/mcpu-cortex-m7-attrs.d  |  13 +
 .../gas/arm/mcpu-cortex-m7-feat-fp-dp.d       |  14 +
 gas/testsuite/gas/arm/mcpu-cortex-m85-attrs.d |  14 +
 .../gas/arm/mcpu-cortex-m85-feat-fp-dp.d      |  16 +
 .../gas/arm/mcpu-cortex-m85-feat-mve-fp.d     |  16 +
 .../gas/arm/mcpu-cortex-m85-feat-pacbti.d     |  16 +
 .../gas/arm/mcpu-cortex-r4f-feat-fp-vfpv3.d   |  15 +
 gas/testsuite/gas/arm/mcpu-cortex-r5-attrs.d  |  15 +
 .../gas/arm/mcpu-cortex-r5-feat-fp-vfpv3.d    |  16 +
 .../gas/arm/mcpu-cortex-r5-feat-idiv.d        |  16 +
 gas/testsuite/gas/arm/mcpu-cortex-r52-attrs.d |  17 +
 .../gas/arm/mcpu-cortex-r52-feat-crc.d        |  18 +
 .../gas/arm/mcpu-cortex-r52-feat-simd.d       |  18 +
 .../gas/arm/mcpu-cortex-r52plus-attrs.d       |  17 +
 .../gas/arm/mcpu-cortex-r52plus-feat-crc.d    |  18 +
 .../gas/arm/mcpu-cortex-r52plus-feat-simd.d   |  18 +
 gas/testsuite/gas/arm/mcpu-cortex-r7-attrs.d  |  15 +
 .../gas/arm/mcpu-cortex-r7-feat-idiv.d        |  17 +
 .../arm/mcpu-cortex-r7-feat-vfpv3-d16-fp16.d  |  17 +
 gas/testsuite/gas/arm/mcpu-cortex-r8-attrs.d  |  15 +
 .../gas/arm/mcpu-cortex-r8-feat-idiv.d        |  17 +
 .../arm/mcpu-cortex-r8-feat-vfpv3-d16-fp16.d  |  17 +
 gas/testsuite/gas/arm/mcpu-cortex-x1-attrs.d  |  18 +
 .../gas/arm/mcpu-cortex-x1-feat-dotprod.d     |  18 +
 .../gas/arm/mcpu-cortex-x1-feat-fp16.d        |  18 +
 gas/testsuite/gas/arm/mcpu-cortex-x1c-attrs.d |  18 +
 .../gas/arm/mcpu-cortex-x1c-feat-dotprod.d    |  18 +
 .../gas/arm/mcpu-cortex-x1c-feat-fp16.d       |  18 +
 gas/testsuite/gas/arm/mcpu-exynos-m1-attrs.d  |  18 +
 .../gas/arm/mcpu-exynos-m1-feat-crc.d         |  18 +
 .../gas/arm/mcpu-exynos-m1-feat-simd.d        |  18 +
 .../gas/arm/mcpu-marvell-pj4-feat-fp-vfpv3.d  |  17 +
 .../gas/arm/mcpu-marvell-pj4-feat-mp.d        |  17 +
 .../gas/arm/mcpu-marvell-pj4-feat-sec.d       |  17 +
 .../gas/arm/mcpu-neoverse-n1-attrs.d          |  18 +
 .../gas/arm/mcpu-neoverse-n1-feat-dotprod.d   |  18 +
 .../gas/arm/mcpu-neoverse-n1-feat-fp16.d      |  18 +
 .../gas/arm/mcpu-neoverse-n2-attrs.d          |  18 +
 .../gas/arm/mcpu-neoverse-n2-feat-bf16.d      |  18 +
 .../gas/arm/mcpu-neoverse-n2-feat-fp16.d      |  18 +
 .../gas/arm/mcpu-neoverse-n2-feat-i8mm.d      |  18 +
 .../gas/arm/mcpu-neoverse-v1-attrs.d          |  18 +
 .../gas/arm/mcpu-neoverse-v1-feat-bf16.d      |  18 +
 .../gas/arm/mcpu-neoverse-v1-feat-fp16.d      |  18 +
 .../gas/arm/mcpu-neoverse-v1-feat-i8mm.d      |  18 +
 gas/testsuite/gas/arm/mcpu-xgene1-feat-simd.d |  18 +
 151 files changed, 2867 insertions(+), 155 deletions(-)
 create mode 100644 gas/testsuite/gas/arm/feat-bf16.s
 create mode 100644 gas/testsuite/gas/arm/feat-crc.s
 create mode 100644 gas/testsuite/gas/arm/feat-dotprod.s
 create mode 100644 gas/testsuite/gas/arm/feat-dsp.s
 create mode 100644 gas/testsuite/gas/arm/feat-fp-vfpv3.s
 create mode 100644 gas/testsuite/gas/arm/feat-fp-vfpv5.s
 create mode 100644 gas/testsuite/gas/arm/feat-fp.dp.s
 create mode 100644 gas/testsuite/gas/arm/feat-fp.s
 create mode 100644 gas/testsuite/gas/arm/feat-fp16.s
 create mode 100644 gas/testsuite/gas/arm/feat-i8mm.s
 create mode 100644 gas/testsuite/gas/arm/feat-idiv.s
 create mode 100644 gas/testsuite/gas/arm/feat-mp.s
 create mode 100644 gas/testsuite/gas/arm/feat-mve.fp.s
 create mode 100644 gas/testsuite/gas/arm/feat-neon-fp16.s
 create mode 100644 gas/testsuite/gas/arm/feat-pacbti.s
 create mode 100644 gas/testsuite/gas/arm/feat-sec.s
 create mode 100644 gas/testsuite/gas/arm/feat-simd.s
 create mode 100644 gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a12-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a12-feat-simd.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a15-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a15-feat-simd.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a17-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a17-feat-simd.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a32-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a32-attrs1.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a32-feat-crc.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a32-feat-simd.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a35-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a35-attrs1.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a35-feat-crc.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a35-feat-simd.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a5-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a5-feat-mp.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a5-feat-neon-fp16.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a5-feat-sec.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a53-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a53-attrs1.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a53-feat-crc.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a53-feat-simd.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a55-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a55-attrs1.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a55-feat-dotprod.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a55-feat-fp16.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a57-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a57-feat-crc.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a57-feat-simd.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a7-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a7-feat-simd.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a710-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a710-feat-bf16.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a710-feat-fp16.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a710-feat-i8mm.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a72-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a72-feat-crc.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a72-feat-simd.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a73-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a73-feat-crc.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a73-feat-simd.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a75-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a75-feat-dotprod.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a75-feat-fp16.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a76-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a76-feat-dotprod.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a76-feat-fp16.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a76ae-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a76ae-feat-dotprod.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a76ae-feat-fp16.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a77-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a77-feat-dotprod.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a77-feat-fp16.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a78-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a78-feat-dotprod.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a78-feat-fp16.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a78ae-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a78ae-feat-dotprod.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a78ae-feat-fp16.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a78c-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a78c-feat-dotprod.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a78c-feat-fp16.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a8-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a8-feat-simd.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a9-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a9-feat-mp.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a9-feat-neon-fp16.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a9-feat-sec.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m33-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m33-feat-dsp.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m33-feat-fp-vfpv5.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m35p-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m35p-feat-dsp.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m35p-feat-fp-vfpv5.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m4-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m4-feat-fp-vfpv3.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m52-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m52-attrs1.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m52-feat-fp-dp.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m52-feat-mve-fp.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m52-feat-pacbti.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m55-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m55-attrs1.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m55-feat-fp-dp.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m55-feat-mve-fp.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m7-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m7-feat-fp-dp.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m85-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m85-feat-fp-dp.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m85-feat-mve-fp.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m85-feat-pacbti.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r4f-feat-fp-vfpv3.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r5-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r5-feat-fp-vfpv3.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r5-feat-idiv.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r52-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r52-feat-crc.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r52-feat-simd.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r52plus-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r52plus-feat-crc.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r52plus-feat-simd.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r7-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r7-feat-idiv.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r7-feat-vfpv3-d16-fp16.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r8-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r8-feat-idiv.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r8-feat-vfpv3-d16-fp16.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-x1-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-x1-feat-dotprod.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-x1-feat-fp16.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-x1c-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-x1c-feat-dotprod.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-x1c-feat-fp16.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-exynos-m1-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-exynos-m1-feat-crc.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-exynos-m1-feat-simd.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-marvell-pj4-feat-fp-vfpv3.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-marvell-pj4-feat-mp.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-marvell-pj4-feat-sec.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-neoverse-n1-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-neoverse-n1-feat-dotprod.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-neoverse-n1-feat-fp16.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-neoverse-n2-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-neoverse-n2-feat-bf16.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-neoverse-n2-feat-fp16.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-neoverse-n2-feat-i8mm.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-neoverse-v1-attrs.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-neoverse-v1-feat-bf16.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-neoverse-v1-feat-fp16.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-neoverse-v1-feat-i8mm.d
 create mode 100644 gas/testsuite/gas/arm/mcpu-xgene1-feat-simd.d

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index 3ff29542411..ba599ef1fda 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -30495,6 +30495,14 @@ const struct arm_legacy_option_table arm_legacy_opts[] =
   {NULL, NULL, ARM_ARCH_NONE, NULL}
 };
 
+struct arm_ext_table
+{
+  const char *		  name;
+  size_t		  name_len;
+  const arm_feature_set	  merge;
+  const arm_feature_set	  clear;
+};
+
 struct arm_cpu_option_table
 {
   const char *           name;
@@ -30507,11 +30515,339 @@ struct arm_cpu_option_table
   /* The canonical name of the CPU, or NULL to use NAME converted to upper
      case.  */
   const char *           canonical_name;
+  const struct arm_ext_table *	ext_table;
+};
+
+/* Used to add support for +E and +noE extension.  */
+#define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
+/* Used to add support for a +E extension.  */
+#define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
+/* Used to add support for a +noE extension.  */
+#define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
+
+#define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
+			    ~0 & ~FPU_ENDIAN_PURE)
+#define ALL_FP_MVE_FP ARM_FEATURE (0, (ARM_EXT2_FP16_INST		   \
+					| ARM_EXT2_FP16_FML		   \
+					| ARM_EXT2_MVE_FP),		   \
+				   ~0 & ~FPU_ENDIAN_PURE)
+#define ALL_SIMD ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA       \
+				     | FPU_NEON_EXT_ARMV8 | FPU_NEON_EXT_RDMA \
+				     | FPU_NEON_EXT_DOTPROD)
+
+#define CDE_EXTENSIONS \
+  ARM_ADD ("cdecp0", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE0)), \
+  ARM_ADD ("cdecp1", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE1)), \
+  ARM_ADD ("cdecp2", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE2)), \
+  ARM_ADD ("cdecp3", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE3)), \
+  ARM_ADD ("cdecp4", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE4)), \
+  ARM_ADD ("cdecp5", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE5)), \
+  ARM_ADD ("cdecp6", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE6)), \
+  ARM_ADD ("cdecp7", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE7))
+
+/* -mcpu extensions.  */
+static const struct arm_ext_table cortex_a5_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  ARM_REMOVE ("simd", ALL_SIMD),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a7_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  ARM_REMOVE ("simd", ALL_SIMD),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a8_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a9_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  ARM_REMOVE ("simd", ALL_SIMD),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a12_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a15_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a17_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_r5_ext_table[] =
+{
+  ARM_REMOVE ("fp",    ALL_FP),
+  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
+					   | FPU_VFP_EXT_ARMV8)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_r7_ext_table[] =
+{
+  ARM_REMOVE ("fp",    ALL_FP),
+  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
+					   | FPU_VFP_EXT_ARMV8)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_r8_ext_table[] =
+{
+  ARM_REMOVE ("fp",    ALL_FP),
+  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
+					   | FPU_VFP_EXT_ARMV8)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m4_ext_table[] =
+{
+  ARM_REMOVE ("fp",    ALL_FP),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m7_ext_table[] =
+{
+  ARM_REMOVE ("fp",    ALL_FP),
+  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
+					   | FPU_VFP_EXT_ARMV8)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a32_ext_table[] =
+{
+  ARM_REMOVE ("fp",     ALL_FP),
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a35_ext_table[] =
+{
+  ARM_REMOVE ("fp",     ALL_FP),
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a53_ext_table[] =
+{
+  ARM_REMOVE ("fp",     ALL_FP),
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a57_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a72_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a73_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table exynos_m1_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_r52_ext_table[] =
+{
+  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_D32 | FPU_VFP_EXT_ARMV8
+					   | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA
+					   | FPU_NEON_EXT_ARMV8 | FPU_NEON_EXT_RDMA
+					   | FPU_NEON_EXT_DOTPROD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_r52plus_ext_table[] =
+{
+  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_D32 | FPU_VFP_EXT_ARMV8
+					   | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA
+					   | FPU_NEON_EXT_ARMV8 | FPU_NEON_EXT_RDMA
+					   | FPU_NEON_EXT_DOTPROD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m33_ext_table[] =
+{
+  ARM_REMOVE ("fp",  ALL_FP),
+  ARM_REMOVE ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m35p_ext_table[] =
+{
+  ARM_REMOVE ("fp",  ALL_FP),
+  ARM_REMOVE ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m52_ext_table[] =
+{
+  ARM_REMOVE ("pacbti", ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI)),
+  ARM_REMOVE ("mve.fp", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP)),
+  ARM_REMOVE ("mve",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+  ARM_REMOVE ("fp",     ALL_FP_MVE_FP),
+  ARM_REMOVE ("dsp",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+  CDE_EXTENSIONS,
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m55_ext_table[] =
+{
+  ARM_REMOVE ("mve.fp", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP)),
+  ARM_REMOVE ("mve",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+  ARM_REMOVE ("fp",     ALL_FP_MVE_FP),
+  ARM_REMOVE ("dsp",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+  CDE_EXTENSIONS,
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_m85_ext_table[] =
+{
+  ARM_REMOVE ("pacbti", ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI)),
+  ARM_REMOVE ("mve.fp", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP)),
+  ARM_REMOVE ("mve",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+  ARM_REMOVE ("fp",     ALL_FP_MVE_FP),
+  ARM_REMOVE ("dsp",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a55_ext_table[] =
+{
+  ARM_REMOVE ("fp", ALL_FP),
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a75_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a76_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a76ae_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a77_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a78_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a78ae_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a78c_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_x1_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_x1c_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table neoverse_n1_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table neoverse_v1_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table cortex_a710_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
+};
+
+static const struct arm_ext_table neoverse_n2_ext_table[] =
+{
+  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
+					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
 };
 
 /* This list should, at a minimum, contain all the cpu names
    recognized by GCC.  */
-#define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
+#define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN, NULL }
+#define ARM_CPU_OPT2(N, CN, V, E, DF, ext) \
+  { N, sizeof (N) - 1, V, E, DF, CN, ext##_ext_table }
 
 static const struct arm_cpu_option_table arm_cpus[] =
 {
@@ -30764,113 +31100,171 @@ static const struct arm_cpu_option_table arm_cpus[] =
   ARM_CPU_OPT ("arm1176jzf-s",	  NULL,		       ARM_ARCH_V6KZ,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_VFP_V2),
-  ARM_CPU_OPT ("cortex-a5",	  "Cortex-A5",	       ARM_ARCH_V7A,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
-	       FPU_ARCH_SOFTVFP),
-  ARM_CPU_OPT ("cortex-a7",	  "Cortex-A7",	       ARM_ARCH_V7VE,
-	       ARM_ARCH_NONE,
-	       FPU_ARCH_NEON_VFP_V4),
-  ARM_CPU_OPT ("cortex-a8",	  "Cortex-A8",	       ARM_ARCH_V7A,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
-	       ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
-  ARM_CPU_OPT ("cortex-a9",	  "Cortex-A9",	       ARM_ARCH_V7A,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
-	       ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
-  ARM_CPU_OPT ("cortex-a12",	  "Cortex-A12",	       ARM_ARCH_V7VE,
-	       ARM_ARCH_NONE,
-	       FPU_ARCH_NEON_VFP_V4),
-  ARM_CPU_OPT ("cortex-a15",	  "Cortex-A15",	       ARM_ARCH_V7VE,
-	       ARM_ARCH_NONE,
-	       FPU_ARCH_NEON_VFP_V4),
-  ARM_CPU_OPT ("cortex-a17",	  "Cortex-A17",	       ARM_ARCH_V7VE,
-	       ARM_ARCH_NONE,
-	       FPU_ARCH_NEON_VFP_V4),
-  ARM_CPU_OPT ("cortex-a32",	  "Cortex-A32",	       ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a35",	  "Cortex-A35",	       ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a53",	  "Cortex-A53",	       ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a55",    "Cortex-A55",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
-  ARM_CPU_OPT ("cortex-a57",	  "Cortex-A57",	       ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a72",	  "Cortex-A72",	       ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	      FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a73",	  "Cortex-A73",	       ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	      FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a75",    "Cortex-A75",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
-  ARM_CPU_OPT ("cortex-a76",    "Cortex-A76",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
-  ARM_CPU_OPT ("cortex-a76ae",    "Cortex-A76AE",      ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
-  ARM_CPU_OPT ("cortex-a77",    "Cortex-A77",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
-  ARM_CPU_OPT ("cortex-a78",   "Cortex-A78",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
-	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a78ae",   "Cortex-A78AE",	   ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
-	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a78c",   "Cortex-A78C",	   ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
-	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-a710",   "Cortex-A710",	   ARM_ARCH_V9A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
-				    | ARM_EXT2_BF16
-				    | ARM_EXT2_I8MM),
-	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("ares",    "Ares",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
+  ARM_CPU_OPT2 ("cortex-a5",	  "Cortex-A5",	       ARM_ARCH_V7A,
+		ARM_FEATURE ((ARM_EXT_MP | ARM_EXT_SEC),
+			     ARM_EXT2_FP16_INST,
+			     (FPU_VFP_V4 | FPU_NEON_EXT_V1
+			      | FPU_NEON_EXT_FMA)),
+		FPU_ARCH_NEON_VFP_V4,
+		cortex_a5),
+  ARM_CPU_OPT2 ("cortex-a7",	  "Cortex-A7",	       ARM_ARCH_V7VE,
+		ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1
+				    | FPU_NEON_EXT_FMA),
+		FPU_ARCH_NEON_VFP_V4,
+		cortex_a7),
+  ARM_CPU_OPT2 ("cortex-a8",	  "Cortex-A8",	       ARM_ARCH_V7A,
+		ARM_FEATURE_LOW (ARM_EXT_SEC, FPU_VFP_V3 | FPU_NEON_EXT_V1),
+		ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1),
+		cortex_a8),
+  ARM_CPU_OPT2 ("cortex-a9",	  "Cortex-A9",	       ARM_ARCH_V7A,
+		ARM_FEATURE ((ARM_EXT_MP | ARM_EXT_SEC),
+			     ARM_EXT2_FP16_INST,
+			     (FPU_VFP_V4 | FPU_NEON_EXT_V1
+			      | FPU_NEON_EXT_FMA)),
+		FPU_ARCH_NEON_VFP_V4,
+		cortex_a9),
+  ARM_CPU_OPT2 ("cortex-a12",	  "Cortex-A12",	       ARM_ARCH_V7VE,
+		ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1
+				    | FPU_NEON_EXT_FMA),
+		FPU_ARCH_NEON_VFP_V4,
+		cortex_a12),
+  ARM_CPU_OPT2 ("cortex-a15",	  "Cortex-A15",	       ARM_ARCH_V7VE,
+		ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1
+				    | FPU_NEON_EXT_FMA),
+		FPU_ARCH_NEON_VFP_V4,
+		cortex_a15),
+  ARM_CPU_OPT2 ("cortex-a17",	  "Cortex-A17",	       ARM_ARCH_V7VE,
+		ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1
+				    | FPU_NEON_EXT_FMA),
+		FPU_ARCH_NEON_VFP_V4,
+		cortex_a17),
+  ARM_CPU_OPT2 ("cortex-a32",	  "Cortex-A32",	       ARM_ARCH_V8A,
+		ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+		FPU_ARCH_NEON_VFP_ARMV8,
+		cortex_a32),
+  ARM_CPU_OPT2 ("cortex-a35",	  "Cortex-A35",	       ARM_ARCH_V8A,
+		ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+		FPU_ARCH_NEON_VFP_ARMV8,
+		cortex_a35),
+  ARM_CPU_OPT2 ("cortex-a53",	  "Cortex-A53",	       ARM_ARCH_V8A,
+		ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+		FPU_ARCH_NEON_VFP_ARMV8,
+		cortex_a53),
+  ARM_CPU_OPT2 ("cortex-a55",    "Cortex-A55",	       ARM_ARCH_V8_2A,
+		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+		cortex_a55),
+  ARM_CPU_OPT2 ("cortex-a57",	  "Cortex-A57",	       ARM_ARCH_V8A,
+		ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+		FPU_ARCH_NEON_VFP_ARMV8,
+		cortex_a57),
+  ARM_CPU_OPT2 ("cortex-a72",	  "Cortex-A72",	       ARM_ARCH_V8A,
+		ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+		FPU_ARCH_NEON_VFP_ARMV8,
+		cortex_a72),
+  ARM_CPU_OPT2 ("cortex-a73",	  "Cortex-A73",	       ARM_ARCH_V8A,
+		ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+		FPU_ARCH_NEON_VFP_ARMV8,
+		cortex_a73),
+  ARM_CPU_OPT2 ("cortex-a75",    "Cortex-A75",	       ARM_ARCH_V8_2A,
+		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+		cortex_a75),
+  ARM_CPU_OPT2 ("cortex-a76",    "Cortex-A76",	       ARM_ARCH_V8_2A,
+		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+		FPU_ARCH_VFP_V5_SP_D16,
+		cortex_a76),
+  ARM_CPU_OPT2 ("cortex-a76ae",    "Cortex-A76AE",      ARM_ARCH_V8_2A,
+		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+		FPU_ARCH_VFP_V5_SP_D16,
+		cortex_a76ae),
+  ARM_CPU_OPT2 ("cortex-a77",    "Cortex-A77",	       ARM_ARCH_V8_2A,
+		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+		FPU_ARCH_VFP_V5_SP_D16,
+		cortex_a77),
+  ARM_CPU_OPT2 ("cortex-a78",   "Cortex-A78",	       ARM_ARCH_V8_2A,
+		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+		FPU_ARCH_VFP_V5_SP_D16,
+		cortex_a78),
+  ARM_CPU_OPT2 ("cortex-a78ae",   "Cortex-A78AE",	   ARM_ARCH_V8_2A,
+		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+		FPU_ARCH_VFP_V5_SP_D16,
+		cortex_a78ae),
+  ARM_CPU_OPT2 ("cortex-a78c",   "Cortex-A78C",	   ARM_ARCH_V8_2A,
+		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+		FPU_ARCH_VFP_V5_SP_D16,
+		cortex_a78c),
   ARM_CPU_OPT ("cortex-r4",	  "Cortex-R4",	       ARM_ARCH_V7R,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_SOFTVFP),
   ARM_CPU_OPT ("cortex-r4f",	  "Cortex-R4F",	       ARM_ARCH_V7R,
-	       ARM_ARCH_NONE,
-	       FPU_ARCH_VFP_V3D16),
-  ARM_CPU_OPT ("cortex-r5",	  "Cortex-R5",	       ARM_ARCH_V7R,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
-	       FPU_ARCH_SOFTVFP),
-  ARM_CPU_OPT ("cortex-r7",	  "Cortex-R7",	       ARM_ARCH_V7R,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
-	       FPU_ARCH_VFP_V3D16),
-  ARM_CPU_OPT ("cortex-r8",	  "Cortex-R8",	       ARM_ARCH_V7R,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
+	       FPU_ARCH_VFP_V3D16,
 	       FPU_ARCH_VFP_V3D16),
-  ARM_CPU_OPT ("cortex-r52",	  "Cortex-R52",	       ARM_ARCH_V8R,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	      FPU_ARCH_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-r52plus",	  "Cortex-R52+",	       ARM_ARCH_V8R,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	      FPU_ARCH_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-m35p",	  "Cortex-M35P",       ARM_ARCH_V8M_MAIN,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
-	       FPU_ARCH_SOFTVFP),
-  ARM_CPU_OPT ("cortex-m33",	  "Cortex-M33",	       ARM_ARCH_V8M_MAIN,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
-	       FPU_ARCH_SOFTVFP),
+  ARM_CPU_OPT2 ("cortex-r5",	  "Cortex-R5",	       ARM_ARCH_V7R,
+		ARM_FEATURE (ARM_EXT_ADIV, 0, FPU_VFP_V3),
+		FPU_ARCH_VFP_V3,
+		cortex_r5),
+  ARM_CPU_OPT2 ("cortex-r7",	  "Cortex-R7",	       ARM_ARCH_V7R,
+		ARM_FEATURE (ARM_EXT_ADIV, 0, FPU_VFP_V3D16 | FPU_VFP_EXT_FP16),
+		FPU_ARCH_VFP_V3D16_FP16,
+		cortex_r7),
+  ARM_CPU_OPT2 ("cortex-r8",	  "Cortex-R8",	       ARM_ARCH_V7R,
+		ARM_FEATURE (ARM_EXT_ADIV, 0, FPU_VFP_V3D16 | FPU_VFP_EXT_FP16),
+		FPU_ARCH_VFP_V3D16_FP16,
+		cortex_r8),
+  ARM_CPU_OPT2 ("cortex-r52",	  "Cortex-R52",	       ARM_ARCH_V8R,
+		ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+		FPU_ARCH_NEON_VFP_ARMV8,
+		cortex_r52),
+  ARM_CPU_OPT2 ("cortex-r52plus",	  "Cortex-R52+",	ARM_ARCH_V8R,
+		ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+		FPU_ARCH_NEON_VFP_ARMV8,
+		cortex_r52plus),
+  ARM_CPU_OPT2 ("cortex-m85",	 "Cortex-M85",	       ARM_ARCH_V8_1M_MAIN,
+		ARM_FEATURE_ALL(ARM_AEXT_V8M_MAIN_DSP,
+				(ARM_EXT2_FP16_INST | ARM_EXT2_MVE
+				 | ARM_EXT2_MVE_FP),
+				ARM_EXT3_PACBTI,
+				(FPU_VFP_V5D16 | FPU_VFP_EXT_FP16
+				 | FPU_VFP_EXT_FMA)),
+		FPU_ARCH_SOFTVFP,
+		cortex_m85),
+  ARM_CPU_OPT2 ("cortex-m55",	 "Cortex-M55",	       ARM_ARCH_V8_1M_MAIN,
+		ARM_FEATURE_ALL(ARM_AEXT_V8M_MAIN_DSP,
+				(ARM_EXT2_FP16_INST | ARM_EXT2_MVE
+				 | ARM_EXT2_MVE_FP),
+				0,
+				(FPU_VFP_V5D16 | FPU_VFP_EXT_FP16
+				 | FPU_VFP_EXT_FMA)),
+		FPU_ARCH_SOFTVFP,
+		cortex_m55),
+  ARM_CPU_OPT2 ("cortex-m52",	 "Cortex-M52",	       ARM_ARCH_V8_1M_MAIN,
+		ARM_FEATURE_ALL (ARM_AEXT_V8M_MAIN_DSP,
+				 (ARM_EXT2_FP16_INST | ARM_EXT2_MVE
+				  | ARM_EXT2_MVE_FP),
+				 ARM_EXT3_PACBTI,
+				 (FPU_VFP_V5D16 | FPU_VFP_EXT_FP16
+				  | FPU_VFP_EXT_FMA)),
+		FPU_ARCH_SOFTVFP,
+		cortex_m52),
+  ARM_CPU_OPT2 ("cortex-m35p",	  "Cortex-M35P",       ARM_ARCH_V8M_MAIN,
+		ARM_FEATURE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP, FPU_VFP_V4D16),
+		FPU_ARCH_VFP_V3D16,
+		cortex_m35p),
+  ARM_CPU_OPT2 ("cortex-m33",	  "Cortex-M33",	       ARM_ARCH_V8M_MAIN,
+		ARM_FEATURE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP, FPU_VFP_V4D16),
+		FPU_ARCH_VFP_V3D16, cortex_m33),
   ARM_CPU_OPT ("cortex-m23",	  "Cortex-M23",	       ARM_ARCH_V8M_BASE,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_SOFTVFP),
-  ARM_CPU_OPT ("cortex-m7",	  "Cortex-M7",	       ARM_ARCH_V7EM,
-	       ARM_ARCH_NONE,
-	       FPU_ARCH_SOFTVFP),
-  ARM_CPU_OPT ("cortex-m4",	  "Cortex-M4",	       ARM_ARCH_V7EM,
-	       ARM_ARCH_NONE,
-	       FPU_ARCH_SOFTVFP),
+  ARM_CPU_OPT2 ("cortex-m7",	  "Cortex-M7",	       ARM_ARCH_V7EM,
+		ARM_FEATURE_COPROC (FPU_VFP_V5D16),
+		FPU_ARCH_VFP_V5D16,
+		cortex_m7),
+  ARM_CPU_OPT2 ("cortex-m4",	  "Cortex-M4",	       ARM_ARCH_V7EM,
+		ARM_FEATURE_COPROC (FPU_VFP_V4_SP_D16),
+		FPU_ARCH_VFP_V4_SP_D16,
+		cortex_m4),
   ARM_CPU_OPT ("cortex-m3",	  "Cortex-M3",	       ARM_ARCH_V7M,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_SOFTVFP),
@@ -30883,28 +31277,50 @@ static const struct arm_cpu_option_table arm_cpus[] =
   ARM_CPU_OPT ("cortex-m0plus",	  "Cortex-M0+",	       ARM_ARCH_V6SM,
 	       ARM_ARCH_NONE,
 	       FPU_ARCH_SOFTVFP),
-  ARM_CPU_OPT ("cortex-x1",   "Cortex-X1",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
-	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("cortex-x1c",   "Cortex-X1C",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
-	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("exynos-m1",	  "Samsung Exynos M1", ARM_ARCH_V8A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
-  ARM_CPU_OPT ("neoverse-n1",    "Neoverse N1",	       ARM_ARCH_V8_2A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
-  ARM_CPU_OPT ("neoverse-n2",	 "Neoverse N2",	       ARM_ARCH_V8_5A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
-				    | ARM_EXT2_BF16
-				    | ARM_EXT2_I8MM),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4),
-  ARM_CPU_OPT ("neoverse-v1", "Neoverse V1", ARM_ARCH_V8_4A,
-	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
-				    | ARM_EXT2_BF16
-				    | ARM_EXT2_I8MM),
-	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4),
+  ARM_CPU_OPT2 ("cortex-x1",   "Cortex-X1",	       ARM_ARCH_V8_2A,
+		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+		FPU_ARCH_VFP_V5_SP_D16,
+		cortex_x1),
+  ARM_CPU_OPT2 ("cortex-x1c",   "Cortex-X1C",	       ARM_ARCH_V8_2A,
+		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+		FPU_ARCH_VFP_V5_SP_D16,
+		cortex_x1c),
+  ARM_CPU_OPT2 ("exynos-m1",	  "Samsung Exynos M1", ARM_ARCH_V8A,
+		ARM_FEATURE (0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
+		FPU_ARCH_NEON_VFP_ARMV8,
+		exynos_m1),
+  ARM_CPU_OPT2 ("neoverse-n1",	 "Neoverse N1",	       ARM_ARCH_V8_2A,
+		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+		FPU_ARCH_VFP_V5_SP_D16,
+		neoverse_n1),
+  ARM_CPU_OPT2 ("ares",    "Ares",	       ARM_ARCH_V8_2A,
+		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+		FPU_ARCH_VFP_V5_SP_D16,
+		neoverse_n1),
+  ARM_CPU_OPT2 ("neoverse-n2",	 "Neoverse N2",	       ARM_ARCH_V9A,
+		ARM_FEATURE(0,
+			    (ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML
+			     | ARM_EXT2_BF16 | ARM_EXT2_I8MM),
+			    (FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8
+			     | FPU_NEON_EXT_DOTPROD | FPU_NEON_EXT_RDMA)),
+		FPU_ARCH_VFP_V5_SP_D16,
+		neoverse_n2),
+  ARM_CPU_OPT2 ("cortex-a710",	 "Cortex-A710",	   ARM_ARCH_V9A,
+		ARM_FEATURE(0,
+			    (ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML
+			     | ARM_EXT2_BF16 | ARM_EXT2_I8MM),
+			    (FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8
+			     | FPU_NEON_EXT_DOTPROD | FPU_NEON_EXT_RDMA)),
+		FPU_ARCH_VFP_V5_SP_D16,
+		cortex_a710),
+  ARM_CPU_OPT2 ("neoverse-v1",	 "Neoverse V1",	       ARM_ARCH_V8_4A,
+		ARM_FEATURE(0,
+			    (ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML
+			     | ARM_EXT2_BF16 | ARM_EXT2_I8MM),
+			    (FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8
+			     | FPU_NEON_EXT_DOTPROD)),
+		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
+		neoverse_v1),
   /* ??? XSCALE is really an architecture.  */
   ARM_CPU_OPT ("xscale",	  NULL,		       ARM_ARCH_XSCALE,
 	       ARM_ARCH_NONE,
@@ -30928,31 +31344,24 @@ static const struct arm_cpu_option_table arm_cpus[] =
 
   /* Marvell processors.  */
   ARM_CPU_OPT ("marvell-pj4",	  NULL,		       ARM_ARCH_V7A,
-	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
-	       FPU_ARCH_VFP_V3D16),
+	       ARM_FEATURE (ARM_EXT_MP | ARM_EXT_SEC, 0, FPU_VFP_V3),
+	       FPU_ARCH_VFP_V3),
   ARM_CPU_OPT ("marvell-whitney", NULL,		       ARM_ARCH_V7A,
 	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
 	       FPU_ARCH_NEON_VFP_V4),
 
   /* APM X-Gene family.  */
   ARM_CPU_OPT ("xgene1",	  "APM X-Gene 1",      ARM_ARCH_V8A,
-	       ARM_ARCH_NONE,
+	       ARM_FEATURE (0, 0, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
 	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
   ARM_CPU_OPT ("xgene2",	  "APM X-Gene 2",      ARM_ARCH_V8A,
 	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
 	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
 
-  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
+  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL, NULL }
 };
 #undef ARM_CPU_OPT
-
-struct arm_ext_table
-{
-  const char *		  name;
-  size_t		  name_len;
-  const arm_feature_set	  merge;
-  const arm_feature_set	  clear;
-};
+#undef ARM_CPU_OPT2
 
 struct arm_arch_option_table
 {
@@ -30963,16 +31372,6 @@ struct arm_arch_option_table
   const struct arm_ext_table *	ext_table;
 };
 
-/* Used to add support for +E and +noE extension.  */
-#define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
-/* Used to add support for a +E extension.  */
-#define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
-/* Used to add support for a +noE extension.  */
-#define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
-
-#define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
-			    ~0 & ~FPU_ENDIAN_PURE)
-
 static const struct arm_ext_table armv5te_ext_table[] =
 {
   ARM_EXT ("fp", FPU_ARCH_VFP_V2, ALL_FP),
@@ -31169,16 +31568,6 @@ static const struct arm_ext_table armv9a_ext_table[] =
 #define armv94a_ext_table armv93a_ext_table
 #define armv95a_ext_table armv94a_ext_table
 
-#define CDE_EXTENSIONS \
-  ARM_ADD ("cdecp0", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE0)), \
-  ARM_ADD ("cdecp1", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE1)), \
-  ARM_ADD ("cdecp2", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE2)), \
-  ARM_ADD ("cdecp3", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE3)), \
-  ARM_ADD ("cdecp4", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE4)), \
-  ARM_ADD ("cdecp5", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE5)), \
-  ARM_ADD ("cdecp6", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE6)), \
-  ARM_ADD ("cdecp7", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE7))
-
 static const struct arm_ext_table armv8m_main_ext_table[] =
 {
   ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP),
@@ -31755,7 +32144,7 @@ arm_parse_cpu (const char *str)
 	  }
 
 	if (ext != NULL)
-	  return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, NULL);
+	  return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, opt->ext_table);
 
 	return true;
       }
diff --git a/gas/testsuite/gas/arm/attr-cpu-directive.d b/gas/testsuite/gas/arm/attr-cpu-directive.d
index a2ab435fc0a..62a07adb4de 100644
--- a/gas/testsuite/gas/arm/attr-cpu-directive.d
+++ b/gas/testsuite/gas/arm/attr-cpu-directive.d
@@ -12,4 +12,6 @@ File Attributes
   Tag_CPU_arch_profile: Application
   Tag_ARM_ISA_use: Yes
   Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3
+  Tag_Advanced_SIMD_arch: NEONv1
   Tag_Virtualization_use: TrustZone
diff --git a/gas/testsuite/gas/arm/feat-bf16.s b/gas/testsuite/gas/arm/feat-bf16.s
new file mode 100644
index 00000000000..46fc48ba567
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-bf16.s
@@ -0,0 +1,5 @@
+.syntax unified
+.thumb
+
+@ feat FP16
+vdot.bf16 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/feat-crc.s b/gas/testsuite/gas/arm/feat-crc.s
new file mode 100644
index 00000000000..671ac14ebcb
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-crc.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat CRC
+crc32w  r0, r0, r1
diff --git a/gas/testsuite/gas/arm/feat-dotprod.s b/gas/testsuite/gas/arm/feat-dotprod.s
new file mode 100644
index 00000000000..775c3ba4c02
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-dotprod.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat DOTPROD
+vudot.u8 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/feat-dsp.s b/gas/testsuite/gas/arm/feat-dsp.s
new file mode 100644
index 00000000000..2f54c7327d1
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-dsp.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat DSP
+smlad   r0, r1, r2, r3
diff --git a/gas/testsuite/gas/arm/feat-fp-vfpv3.s b/gas/testsuite/gas/arm/feat-fp-vfpv3.s
new file mode 100644
index 00000000000..4435db35690
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-fp-vfpv3.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat FP (VFP-v3)
+vmla.f32 s0, s1, s2
diff --git a/gas/testsuite/gas/arm/feat-fp-vfpv5.s b/gas/testsuite/gas/arm/feat-fp-vfpv5.s
new file mode 100644
index 00000000000..13a2e7aca9e
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-fp-vfpv5.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat FP (VFP-v5)
+vfma.f32 s0, s1, s2
diff --git a/gas/testsuite/gas/arm/feat-fp.dp.s b/gas/testsuite/gas/arm/feat-fp.dp.s
new file mode 100644
index 00000000000..34b68cd8603
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-fp.dp.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat FP.DP
+vadd.f64 d0, d1, d2
diff --git a/gas/testsuite/gas/arm/feat-fp.s b/gas/testsuite/gas/arm/feat-fp.s
new file mode 100644
index 00000000000..5cf49af0e9f
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-fp.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat FP
+vadd.f32 s0, s1, s2
diff --git a/gas/testsuite/gas/arm/feat-fp16.s b/gas/testsuite/gas/arm/feat-fp16.s
new file mode 100644
index 00000000000..6780678e8ca
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-fp16.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat FP16
+vadd.f16 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/feat-i8mm.s b/gas/testsuite/gas/arm/feat-i8mm.s
new file mode 100644
index 00000000000..bb3818726a8
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-i8mm.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat I8MM
+vusmmla.s8  q6, q7, q8
diff --git a/gas/testsuite/gas/arm/feat-idiv.s b/gas/testsuite/gas/arm/feat-idiv.s
new file mode 100644
index 00000000000..8b289fa817d
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-idiv.s
@@ -0,0 +1,3 @@
+.syntax unified
+
+sdiv r0, r1, r2
diff --git a/gas/testsuite/gas/arm/feat-mp.s b/gas/testsuite/gas/arm/feat-mp.s
new file mode 100644
index 00000000000..db365d7f282
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-mp.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat MP
+ldrex r0, [r1]
diff --git a/gas/testsuite/gas/arm/feat-mve.fp.s b/gas/testsuite/gas/arm/feat-mve.fp.s
new file mode 100644
index 00000000000..81c23300dc3
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-mve.fp.s
@@ -0,0 +1,5 @@
+.syntax unified
+.thumb
+
+@ MVE.FP
+vmul.f32 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/feat-neon-fp16.s b/gas/testsuite/gas/arm/feat-neon-fp16.s
new file mode 100644
index 00000000000..55ab08553bf
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-neon-fp16.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat NEON-FP16
+vadd.f16 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/feat-pacbti.s b/gas/testsuite/gas/arm/feat-pacbti.s
new file mode 100644
index 00000000000..2399f0ca230
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-pacbti.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ PACBTI
+pac     r12, lr, sp
diff --git a/gas/testsuite/gas/arm/feat-sec.s b/gas/testsuite/gas/arm/feat-sec.s
new file mode 100644
index 00000000000..bdb516a30f4
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-sec.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat SEC
+smc     #0
diff --git a/gas/testsuite/gas/arm/feat-simd.s b/gas/testsuite/gas/arm/feat-simd.s
new file mode 100644
index 00000000000..871f5490902
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-simd.s
@@ -0,0 +1,5 @@
+.syntax unified
+.text
+
+@ feat SIMD
+vadd.i32 q0, q1, q2
diff --git a/gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s b/gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s
new file mode 100644
index 00000000000..41ccd2d9414
--- /dev/null
+++ b/gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s
@@ -0,0 +1,4 @@
+.syntax unified
+
+@ feat VFP3-D16-FP16
+vcvtt.f16.f32 s0, s1
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a12-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a12-attrs.d
new file mode 100644
index 00000000000..953175f6eba
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a12-attrs.d
@@ -0,0 +1,17 @@
+#name: Cortex-A12 Attributes
+#as: -mcpu=cortex-a12+nofp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A12"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_MPextension_use: Allowed
+  Tag_DIV_use: Allowed in v7-A with integer division extension
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a12-feat-simd.d b/gas/testsuite/gas/arm/mcpu-cortex-a12-feat-simd.d
new file mode 100644
index 00000000000..e8d96c21f04
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a12-feat-simd.d
@@ -0,0 +1,19 @@
+#name: Cortex-A12 feat-simd
+#as: -mcpu=cortex-a12
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A12"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv4
+  Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
+  Tag_MPextension_use: Allowed
+  Tag_DIV_use: Allowed in v7-A with integer division extension
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a15-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a15-attrs.d
new file mode 100644
index 00000000000..c780f280b0c
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a15-attrs.d
@@ -0,0 +1,17 @@
+#name: Cortex-A15 Attributes
+#as: -mcpu=cortex-a15+nofp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A15"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_MPextension_use: Allowed
+  Tag_DIV_use: Allowed in v7-A with integer division extension
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a15-feat-simd.d b/gas/testsuite/gas/arm/mcpu-cortex-a15-feat-simd.d
new file mode 100644
index 00000000000..796f8d3fb04
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a15-feat-simd.d
@@ -0,0 +1,19 @@
+#name: Cortex-A15 feat-simd
+#as: -mcpu=cortex-a15
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A15"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv4
+  Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
+  Tag_MPextension_use: Allowed
+  Tag_DIV_use: Allowed in v7-A with integer division extension
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a17-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a17-attrs.d
new file mode 100644
index 00000000000..c8b56ff58c2
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a17-attrs.d
@@ -0,0 +1,17 @@
+#name: Cortex-A17 Attributes
+#as: -mcpu=cortex-a17+nofp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A17"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_MPextension_use: Allowed
+  Tag_DIV_use: Allowed in v7-A with integer division extension
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a17-feat-simd.d b/gas/testsuite/gas/arm/mcpu-cortex-a17-feat-simd.d
new file mode 100644
index 00000000000..37e3444d237
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a17-feat-simd.d
@@ -0,0 +1,19 @@
+#name: Cortex-A17 feat-simd
+#as: -mcpu=cortex-a17
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A17"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv4
+  Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
+  Tag_MPextension_use: Allowed
+  Tag_DIV_use: Allowed in v7-A with integer division extension
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a32-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a32-attrs.d
new file mode 100644
index 00000000000..6979aff8835
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a32-attrs.d
@@ -0,0 +1,16 @@
+#name: Cortex-A32 Attributes
+#as: -mcpu=cortex-a32+nofp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A32"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a32-attrs1.d b/gas/testsuite/gas/arm/mcpu-cortex-a32-attrs1.d
new file mode 100644
index 00000000000..98dc43bde01
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a32-attrs1.d
@@ -0,0 +1,18 @@
+#name: Cortex-A32 Attributes 1
+#as: -mcpu=cortex-a32+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A32"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a32-feat-crc.d b/gas/testsuite/gas/arm/mcpu-cortex-a32-feat-crc.d
new file mode 100644
index 00000000000..dfa191bd52c
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a32-feat-crc.d
@@ -0,0 +1,18 @@
+#name: Cortex-A32 feat-crc
+#as: -mcpu=cortex-a32
+#source: feat-crc.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A32"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a32-feat-simd.d b/gas/testsuite/gas/arm/mcpu-cortex-a32-feat-simd.d
new file mode 100644
index 00000000000..20b6a34a8fb
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a32-feat-simd.d
@@ -0,0 +1,18 @@
+#name: Cortex-A32 feat-simd
+#as: -mcpu=cortex-a32
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A32"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a35-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a35-attrs.d
new file mode 100644
index 00000000000..5743016e2e3
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a35-attrs.d
@@ -0,0 +1,16 @@
+#name: Cortex-A35 Attributes
+#as: -mcpu=cortex-a35+nofp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A35"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a35-attrs1.d b/gas/testsuite/gas/arm/mcpu-cortex-a35-attrs1.d
new file mode 100644
index 00000000000..97160cf2f8a
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a35-attrs1.d
@@ -0,0 +1,18 @@
+#name: Cortex-A35 Attributes 1
+#as: -mcpu=cortex-a35+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A35"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a35-feat-crc.d b/gas/testsuite/gas/arm/mcpu-cortex-a35-feat-crc.d
new file mode 100644
index 00000000000..eb61f3b0f36
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a35-feat-crc.d
@@ -0,0 +1,18 @@
+#name: Cortex-A35 feat-crc
+#as: -mcpu=cortex-a35
+#source: feat-crc.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A35"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a35-feat-simd.d b/gas/testsuite/gas/arm/mcpu-cortex-a35-feat-simd.d
new file mode 100644
index 00000000000..3c92517c90f
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a35-feat-simd.d
@@ -0,0 +1,18 @@
+#name: Cortex-A35 feat-simd
+#as: -mcpu=cortex-a35
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A35"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a5-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a5-attrs.d
new file mode 100644
index 00000000000..d1ab26e87aa
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a5-attrs.d
@@ -0,0 +1,16 @@
+#name: Cortex-A5 Attributes
+#as: -mcpu=cortex-a5+nofp+nosimd
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A5"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a5-feat-mp.d b/gas/testsuite/gas/arm/mcpu-cortex-a5-feat-mp.d
new file mode 100644
index 00000000000..3b34ffb508b
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a5-feat-mp.d
@@ -0,0 +1,18 @@
+#name: Cortex-A5 feat-mp
+#as: -mcpu=cortex-a5
+#source: feat-mp.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A5"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv4
+  Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a5-feat-neon-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-a5-feat-neon-fp16.d
new file mode 100644
index 00000000000..36571e2aed3
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a5-feat-neon-fp16.d
@@ -0,0 +1,18 @@
+#name: Cortex-A5 feat-neon-fp16
+#as: -mcpu=cortex-a5
+#source: feat-neon-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A5"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv4
+  Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a5-feat-sec.d b/gas/testsuite/gas/arm/mcpu-cortex-a5-feat-sec.d
new file mode 100644
index 00000000000..dad84126dec
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a5-feat-sec.d
@@ -0,0 +1,18 @@
+#name: Cortex-A5 feat-sec
+#as: -mcpu=cortex-a5
+#source: feat-sec.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A5"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv4
+  Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a53-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a53-attrs.d
new file mode 100644
index 00000000000..754eca0570e
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a53-attrs.d
@@ -0,0 +1,16 @@
+#name: Cortex-A53 Attributes
+#as: -mcpu=cortex-a53+nofp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A53"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a53-attrs1.d b/gas/testsuite/gas/arm/mcpu-cortex-a53-attrs1.d
new file mode 100644
index 00000000000..ad52b9278fb
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a53-attrs1.d
@@ -0,0 +1,18 @@
+#name: Cortex-A53 Attributes 1
+#as: -mcpu=cortex-a53+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A53"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a53-feat-crc.d b/gas/testsuite/gas/arm/mcpu-cortex-a53-feat-crc.d
new file mode 100644
index 00000000000..70a688c1116
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a53-feat-crc.d
@@ -0,0 +1,18 @@
+#name: Cortex-A53 feat-crc
+#as: -mcpu=cortex-a53
+#source: feat-crc.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A53"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a53-feat-simd.d b/gas/testsuite/gas/arm/mcpu-cortex-a53-feat-simd.d
new file mode 100644
index 00000000000..0c423b767bf
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a53-feat-simd.d
@@ -0,0 +1,18 @@
+#name: Cortex-A53 feat-simd
+#as: -mcpu=cortex-a53
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A53"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a55-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a55-attrs.d
new file mode 100644
index 00000000000..247e146fc23
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a55-attrs.d
@@ -0,0 +1,17 @@
+#name: Cortex-A55 Attributes
+#as: -mcpu=cortex-a55+nofp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A55"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a55-attrs1.d b/gas/testsuite/gas/arm/mcpu-cortex-a55-attrs1.d
new file mode 100644
index 00000000000..595a677bc73
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a55-attrs1.d
@@ -0,0 +1,18 @@
+#name: Cortex-A55 Attributes 1
+#as: -mcpu=cortex-a55+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A55"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a55-feat-dotprod.d b/gas/testsuite/gas/arm/mcpu-cortex-a55-feat-dotprod.d
new file mode 100644
index 00000000000..bd95929778c
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a55-feat-dotprod.d
@@ -0,0 +1,18 @@
+#name: Cortex-A55 feat-dotprod
+#as: -mcpu=cortex-a55
+#source: feat-dotprod.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A55"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a55-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-a55-feat-fp16.d
new file mode 100644
index 00000000000..79ec5bc418f
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a55-feat-fp16.d
@@ -0,0 +1,18 @@
+#name: Cortex-A55 feat-fp16
+#as: -mcpu=cortex-a55
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A55"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a57-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a57-attrs.d
new file mode 100644
index 00000000000..0d7e1200e7d
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a57-attrs.d
@@ -0,0 +1,18 @@
+#name: Cortex-A57 Attributes
+#as: -mcpu=cortex-a57+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A57"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a57-feat-crc.d b/gas/testsuite/gas/arm/mcpu-cortex-a57-feat-crc.d
new file mode 100644
index 00000000000..49be31c5c15
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a57-feat-crc.d
@@ -0,0 +1,18 @@
+#name: Cortex-A57 feat-crc
+#as: -mcpu=cortex-a57
+#source: feat-crc.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A57"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a57-feat-simd.d b/gas/testsuite/gas/arm/mcpu-cortex-a57-feat-simd.d
new file mode 100644
index 00000000000..48fc50eaf60
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a57-feat-simd.d
@@ -0,0 +1,18 @@
+#name: Cortex-A57 feat-simd
+#as: -mcpu=cortex-a57
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A57"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a7-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a7-attrs.d
new file mode 100644
index 00000000000..20f0d4b02c8
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a7-attrs.d
@@ -0,0 +1,17 @@
+#name: Cortex-A7 Attributes
+#as: -mcpu=cortex-a7+nofp+nosimd
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A7"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_MPextension_use: Allowed
+  Tag_DIV_use: Allowed in v7-A with integer division extension
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a7-feat-simd.d b/gas/testsuite/gas/arm/mcpu-cortex-a7-feat-simd.d
new file mode 100644
index 00000000000..b0c59f22900
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a7-feat-simd.d
@@ -0,0 +1,19 @@
+#name: Cortex-A7 feat-simd
+#as: -mcpu=cortex-a7
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A7"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv4
+  Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
+  Tag_MPextension_use: Allowed
+  Tag_DIV_use: Allowed in v7-A with integer division extension
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a710-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a710-attrs.d
new file mode 100644
index 00000000000..dac147dfb51
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a710-attrs.d
@@ -0,0 +1,18 @@
+#name: Cortex-A710 Attributes
+#as: -mcpu=cortex-a710+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A710"
+  Tag_CPU_arch: v9
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a710-feat-bf16.d b/gas/testsuite/gas/arm/mcpu-cortex-a710-feat-bf16.d
new file mode 100644
index 00000000000..b53d648d5ad
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a710-feat-bf16.d
@@ -0,0 +1,18 @@
+#name: Cortex-A710 feat-bf16
+#as: -mcpu=cortex-a710
+#source: feat-bf16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A710"
+  Tag_CPU_arch: v9
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a710-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-a710-feat-fp16.d
new file mode 100644
index 00000000000..b2a2c376c64
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a710-feat-fp16.d
@@ -0,0 +1,18 @@
+#name: Cortex-A710 feat-fp16
+#as: -mcpu=cortex-a710
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A710"
+  Tag_CPU_arch: v9
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a710-feat-i8mm.d b/gas/testsuite/gas/arm/mcpu-cortex-a710-feat-i8mm.d
new file mode 100644
index 00000000000..c682f38d31c
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a710-feat-i8mm.d
@@ -0,0 +1,18 @@
+#name: Cortex-A710 feat-i8mm
+#as: -mcpu=cortex-a710
+#source: feat-i8mm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A710"
+  Tag_CPU_arch: v9
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a72-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a72-attrs.d
new file mode 100644
index 00000000000..6c16d2ae6d6
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a72-attrs.d
@@ -0,0 +1,18 @@
+#name: Cortex-A72 Attributes
+#as: -mcpu=cortex-a72+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A72"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a72-feat-crc.d b/gas/testsuite/gas/arm/mcpu-cortex-a72-feat-crc.d
new file mode 100644
index 00000000000..8f3b7002250
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a72-feat-crc.d
@@ -0,0 +1,18 @@
+#name: Cortex-A72 feat-crc
+#as: -mcpu=cortex-a72
+#source: feat-crc.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A72"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a72-feat-simd.d b/gas/testsuite/gas/arm/mcpu-cortex-a72-feat-simd.d
new file mode 100644
index 00000000000..3cad2ec1b5e
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a72-feat-simd.d
@@ -0,0 +1,18 @@
+#name: Cortex-A72 feat-simd
+#as: -mcpu=cortex-a72
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A72"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a73-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a73-attrs.d
new file mode 100644
index 00000000000..07df89b796a
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a73-attrs.d
@@ -0,0 +1,18 @@
+#name: Cortex-A73 Attributes
+#as: -mcpu=cortex-a73+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A73"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a73-feat-crc.d b/gas/testsuite/gas/arm/mcpu-cortex-a73-feat-crc.d
new file mode 100644
index 00000000000..ca750aaf6fd
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a73-feat-crc.d
@@ -0,0 +1,18 @@
+#name: Cortex-A73 feat-crc
+#as: -mcpu=cortex-a73
+#source: feat-crc.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A73"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a73-feat-simd.d b/gas/testsuite/gas/arm/mcpu-cortex-a73-feat-simd.d
new file mode 100644
index 00000000000..7475b25de40
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a73-feat-simd.d
@@ -0,0 +1,18 @@
+#name: Cortex-A73 feat-simd
+#as: -mcpu=cortex-a73
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A73"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a75-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a75-attrs.d
new file mode 100644
index 00000000000..cc88ad25c11
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a75-attrs.d
@@ -0,0 +1,18 @@
+#name: Cortex-A75 Attributes
+#as: -mcpu=cortex-a75+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A75"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a75-feat-dotprod.d b/gas/testsuite/gas/arm/mcpu-cortex-a75-feat-dotprod.d
new file mode 100644
index 00000000000..83ee9088ad0
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a75-feat-dotprod.d
@@ -0,0 +1,18 @@
+#name: Cortex-A75 feat-dotprod
+#as: -mcpu=cortex-a75
+#source: feat-dotprod.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A75"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a75-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-a75-feat-fp16.d
new file mode 100644
index 00000000000..c996200a244
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a75-feat-fp16.d
@@ -0,0 +1,18 @@
+#name: Cortex-A75 feat-fp16
+#as: -mcpu=cortex-a75
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A75"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a76-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a76-attrs.d
new file mode 100644
index 00000000000..088939c0559
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a76-attrs.d
@@ -0,0 +1,18 @@
+#name: Cortex-A76 Attributes
+#as: -mcpu=cortex-a76+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A76"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a76-feat-dotprod.d b/gas/testsuite/gas/arm/mcpu-cortex-a76-feat-dotprod.d
new file mode 100644
index 00000000000..720ea69608f
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a76-feat-dotprod.d
@@ -0,0 +1,18 @@
+#name: Cortex-A76 feat-dotprod
+#as: -mcpu=cortex-a76
+#source: feat-dotprod.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A76"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a76-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-a76-feat-fp16.d
new file mode 100644
index 00000000000..c9632960f64
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a76-feat-fp16.d
@@ -0,0 +1,18 @@
+#name: Cortex-A76 feat-fp16
+#as: -mcpu=cortex-a76
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A76"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a76ae-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a76ae-attrs.d
new file mode 100644
index 00000000000..ed050b3e2da
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a76ae-attrs.d
@@ -0,0 +1,18 @@
+#name: Cortex-A76AE Attributes
+#as: -mcpu=cortex-a76ae+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A76AE"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a76ae-feat-dotprod.d b/gas/testsuite/gas/arm/mcpu-cortex-a76ae-feat-dotprod.d
new file mode 100644
index 00000000000..449e70ccf5e
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a76ae-feat-dotprod.d
@@ -0,0 +1,18 @@
+#name: Cortex-A76AE feat-dotprod
+#as: -mcpu=cortex-a76ae
+#source: feat-dotprod.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A76AE"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a76ae-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-a76ae-feat-fp16.d
new file mode 100644
index 00000000000..43af92dd16a
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a76ae-feat-fp16.d
@@ -0,0 +1,18 @@
+#name: Cortex-A76AE feat-fp16
+#as: -mcpu=cortex-a76ae
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A76AE"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a77-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a77-attrs.d
new file mode 100644
index 00000000000..e014c789449
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a77-attrs.d
@@ -0,0 +1,18 @@
+#name: Cortex-A77 Attributes
+#as: -mcpu=cortex-a77+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A77"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a77-feat-dotprod.d b/gas/testsuite/gas/arm/mcpu-cortex-a77-feat-dotprod.d
new file mode 100644
index 00000000000..7cccf0feec1
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a77-feat-dotprod.d
@@ -0,0 +1,18 @@
+#name: Cortex-A77 feat-dotprod
+#as: -mcpu=cortex-a77
+#source: feat-dotprod.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A77"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a77-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-a77-feat-fp16.d
new file mode 100644
index 00000000000..97fe61e0f09
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a77-feat-fp16.d
@@ -0,0 +1,18 @@
+#name: Cortex-A77 feat-fp16
+#as: -mcpu=cortex-a77
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A77"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a78-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a78-attrs.d
new file mode 100644
index 00000000000..73c5e070aaf
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a78-attrs.d
@@ -0,0 +1,18 @@
+#name: Cortex-A78 Attributes
+#as: -mcpu=cortex-a78+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A78"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a78-feat-dotprod.d b/gas/testsuite/gas/arm/mcpu-cortex-a78-feat-dotprod.d
new file mode 100644
index 00000000000..eeb2260163b
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a78-feat-dotprod.d
@@ -0,0 +1,18 @@
+#name: Cortex-A78 feat-dotprod
+#as: -mcpu=cortex-a78
+#source: feat-dotprod.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A78"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a78-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-a78-feat-fp16.d
new file mode 100644
index 00000000000..88936f78c3f
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a78-feat-fp16.d
@@ -0,0 +1,18 @@
+#name: Cortex-A78 feat-fp16
+#as: -mcpu=cortex-a78
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A78"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a78ae-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a78ae-attrs.d
new file mode 100644
index 00000000000..944c21f2530
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a78ae-attrs.d
@@ -0,0 +1,18 @@
+#name: Cortex-A78AE Attributes
+#as: -mcpu=cortex-a78ae+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A78AE"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a78ae-feat-dotprod.d b/gas/testsuite/gas/arm/mcpu-cortex-a78ae-feat-dotprod.d
new file mode 100644
index 00000000000..8d24972514d
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a78ae-feat-dotprod.d
@@ -0,0 +1,18 @@
+#name: Cortex-A78AE feat-dotprod
+#as: -mcpu=cortex-a78ae
+#source: feat-dotprod.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A78AE"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a78ae-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-a78ae-feat-fp16.d
new file mode 100644
index 00000000000..07d142b24fe
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a78ae-feat-fp16.d
@@ -0,0 +1,18 @@
+#name: Cortex-A78AE feat-fp16
+#as: -mcpu=cortex-a78ae
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A78AE"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a78c-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a78c-attrs.d
new file mode 100644
index 00000000000..bd0a9d8a455
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a78c-attrs.d
@@ -0,0 +1,18 @@
+#name: Cortex-A78C Attributes
+#as: -mcpu=cortex-a78c+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A78C"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a78c-feat-dotprod.d b/gas/testsuite/gas/arm/mcpu-cortex-a78c-feat-dotprod.d
new file mode 100644
index 00000000000..67027068b23
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a78c-feat-dotprod.d
@@ -0,0 +1,18 @@
+#name: Cortex-A78C feat-dotprod
+#as: -mcpu=cortex-a78c
+#source: feat-dotprod.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A78C"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a78c-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-a78c-feat-fp16.d
new file mode 100644
index 00000000000..f45fc34dc2a
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a78c-feat-fp16.d
@@ -0,0 +1,18 @@
+#name: Cortex-A78C feat-fp16
+#as: -mcpu=cortex-a78c
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A78C"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a8-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a8-attrs.d
new file mode 100644
index 00000000000..5b1696f3f0a
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a8-attrs.d
@@ -0,0 +1,15 @@
+#name: Cortex-A8 Attributes
+#as: -mcpu=cortex-a8+nofp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A8"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_Virtualization_use: TrustZone
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a8-feat-simd.d b/gas/testsuite/gas/arm/mcpu-cortex-a8-feat-simd.d
new file mode 100644
index 00000000000..e8de97b31da
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a8-feat-simd.d
@@ -0,0 +1,17 @@
+#name: Cortex-A8 feat-simd
+#as: -mcpu=cortex-a8
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A8"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3
+  Tag_Advanced_SIMD_arch: NEONv1
+  Tag_Virtualization_use: TrustZone
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a9-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a9-attrs.d
new file mode 100644
index 00000000000..4d1ebaa9dab
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a9-attrs.d
@@ -0,0 +1,16 @@
+#name: Cortex-A9 Attributes
+#as: -mcpu=cortex-a9+nofp+nosimd
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A9"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a9-feat-mp.d b/gas/testsuite/gas/arm/mcpu-cortex-a9-feat-mp.d
new file mode 100644
index 00000000000..96ecaaf32b7
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a9-feat-mp.d
@@ -0,0 +1,18 @@
+#name: Cortex-A9 feat-mp
+#as: -mcpu=cortex-a9
+#source: feat-mp.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A9"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv4
+  Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a9-feat-neon-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-a9-feat-neon-fp16.d
new file mode 100644
index 00000000000..83ecc83db6f
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a9-feat-neon-fp16.d
@@ -0,0 +1,18 @@
+#name: Cortex-A9 feat-neon-fp16
+#as: -mcpu=cortex-a9
+#source: feat-neon-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A9"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv4
+  Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a9-feat-sec.d b/gas/testsuite/gas/arm/mcpu-cortex-a9-feat-sec.d
new file mode 100644
index 00000000000..73386c2bb82
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-a9-feat-sec.d
@@ -0,0 +1,18 @@
+#name: Cortex-A9 feat-sec
+#as: -mcpu=cortex-a9
+#source: feat-sec.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-A9"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv4
+  Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m33-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-m33-attrs.d
new file mode 100644
index 00000000000..d2195500a43
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-m33-attrs.d
@@ -0,0 +1,13 @@
+#name: Cortex-M33 Attributes
+#as: -mcpu=cortex-m33+nofp+nodsp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-M33"
+  Tag_CPU_arch: v8-M.mainline
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Yes
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m33-feat-dsp.d b/gas/testsuite/gas/arm/mcpu-cortex-m33-feat-dsp.d
new file mode 100644
index 00000000000..521846cdcc2
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-m33-feat-dsp.d
@@ -0,0 +1,15 @@
+#name: Cortex-M33 feat-dsp
+#as: -mcpu=cortex-m33
+#source: feat-dsp.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-M33"
+  Tag_CPU_arch: v8-M.mainline
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Yes
+  Tag_FP_arch: VFPv4-D16
+  Tag_DSP_extension: Allowed
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m33-feat-fp-vfpv5.d b/gas/testsuite/gas/arm/mcpu-cortex-m33-feat-fp-vfpv5.d
new file mode 100644
index 00000000000..6624dbac797
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-m33-feat-fp-vfpv5.d
@@ -0,0 +1,15 @@
+#name: Cortex-M33 feat-fp-vfpv5
+#as: -mcpu=cortex-m33
+#source: feat-fp-vfpv5.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-M33"
+  Tag_CPU_arch: v8-M.mainline
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Yes
+  Tag_FP_arch: VFPv4-D16
+  Tag_DSP_extension: Allowed
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m35p-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-m35p-attrs.d
new file mode 100644
index 00000000000..e8bb5884eac
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-m35p-attrs.d
@@ -0,0 +1,13 @@
+#name: Cortex-M35P Attributes
+#as: -mcpu=cortex-m35p+nofp+nodsp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-M35P"
+  Tag_CPU_arch: v8-M.mainline
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Yes
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m35p-feat-dsp.d b/gas/testsuite/gas/arm/mcpu-cortex-m35p-feat-dsp.d
new file mode 100644
index 00000000000..12b6b6dfbfa
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-m35p-feat-dsp.d
@@ -0,0 +1,15 @@
+#name: Cortex-M35P feat-dsp
+#as: -mcpu=cortex-m35p
+#source: feat-dsp.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-M35P"
+  Tag_CPU_arch: v8-M.mainline
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Yes
+  Tag_FP_arch: VFPv4-D16
+  Tag_DSP_extension: Allowed
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m35p-feat-fp-vfpv5.d b/gas/testsuite/gas/arm/mcpu-cortex-m35p-feat-fp-vfpv5.d
new file mode 100644
index 00000000000..918942ba693
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-m35p-feat-fp-vfpv5.d
@@ -0,0 +1,15 @@
+#name: Cortex-M35P feat-fp-vfpv5
+#as: -mcpu=cortex-m35p
+#source: feat-fp-vfpv5.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-M35P"
+  Tag_CPU_arch: v8-M.mainline
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Yes
+  Tag_FP_arch: VFPv4-D16
+  Tag_DSP_extension: Allowed
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m4-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-m4-attrs.d
new file mode 100644
index 00000000000..e27944539d7
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-m4-attrs.d
@@ -0,0 +1,13 @@
+#name: Cortex-M4 Attributes
+#as: -mcpu=cortex-m4+nofp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-M4"
+  Tag_CPU_arch: v7E-M
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Thumb-2
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m4-feat-fp-vfpv3.d b/gas/testsuite/gas/arm/mcpu-cortex-m4-feat-fp-vfpv3.d
new file mode 100644
index 00000000000..c66e37244bc
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-m4-feat-fp-vfpv3.d
@@ -0,0 +1,15 @@
+#name: Cortex-M4 feat-fp-vfpv3
+#as: -mcpu=cortex-m4
+#source: feat-fp-vfpv3.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-M4"
+  Tag_CPU_arch: v7E-M
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv4-D16
+  Tag_ABI_HardFP_use: SP only
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m52-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-m52-attrs.d
new file mode 100644
index 00000000000..3e32853c951
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-m52-attrs.d
@@ -0,0 +1,14 @@
+#name: Cortex-M52 Attributes
+#as: -mcpu=cortex-m52+nopacbti+nomve.fp+nomve+nofp+nodsp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-M52"
+  Tag_CPU_arch: v8.1-M.mainline
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Yes
+  Tag_DSP_extension: Allowed
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m52-attrs1.d b/gas/testsuite/gas/arm/mcpu-cortex-m52-attrs1.d
new file mode 100644
index 00000000000..d378a5d4e01
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-m52-attrs1.d
@@ -0,0 +1,16 @@
+#name: Cortex-M52 Attributes 1
+#as: -mcpu=cortex-m52+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-M52"
+  Tag_CPU_arch: v8.1-M.mainline
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Yes
+  Tag_FP_arch: FPv5/FP-D16 for ARMv8
+  Tag_DSP_extension: Allowed
+  Tag_MVE_arch: MVE Integer and FP
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m52-feat-fp-dp.d b/gas/testsuite/gas/arm/mcpu-cortex-m52-feat-fp-dp.d
new file mode 100644
index 00000000000..fe47c58bd0d
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-m52-feat-fp-dp.d
@@ -0,0 +1,16 @@
+#name: Cortex-M52 feat-fp.dp
+#as: -mcpu=cortex-m52
+#source: feat-fp.dp.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-M52"
+  Tag_CPU_arch: v8.1-M.mainline
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Yes
+  Tag_FP_arch: FPv5/FP-D16 for ARMv8
+  Tag_DSP_extension: Allowed
+  Tag_MVE_arch: MVE Integer and FP
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m52-feat-mve-fp.d b/gas/testsuite/gas/arm/mcpu-cortex-m52-feat-mve-fp.d
new file mode 100644
index 00000000000..e87ce8184fe
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-m52-feat-mve-fp.d
@@ -0,0 +1,16 @@
+#name: Cortex-M52 feat-mve.fp
+#as: -mcpu=cortex-m52
+#source: feat-mve.fp.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-M52"
+  Tag_CPU_arch: v8.1-M.mainline
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Yes
+  Tag_FP_arch: FPv5/FP-D16 for ARMv8
+  Tag_DSP_extension: Allowed
+  Tag_MVE_arch: MVE Integer and FP
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m52-feat-pacbti.d b/gas/testsuite/gas/arm/mcpu-cortex-m52-feat-pacbti.d
new file mode 100644
index 00000000000..e04aae72a08
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-m52-feat-pacbti.d
@@ -0,0 +1,16 @@
+#name: Cortex-M52 feat-pacbti
+#as: -mcpu=cortex-m52
+#source: feat-pacbti.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-M52"
+  Tag_CPU_arch: v8.1-M.mainline
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Yes
+  Tag_FP_arch: FPv5/FP-D16 for ARMv8
+  Tag_DSP_extension: Allowed
+  Tag_MVE_arch: MVE Integer and FP
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m55-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-m55-attrs.d
new file mode 100644
index 00000000000..b873ecdb2f5
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-m55-attrs.d
@@ -0,0 +1,14 @@
+#name: Cortex-M55 Attributes
+#as: -mcpu=cortex-m55+nomve.fp+nomve+nofp+nodsp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-M55"
+  Tag_CPU_arch: v8.1-M.mainline
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Yes
+  Tag_DSP_extension: Allowed
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m55-attrs1.d b/gas/testsuite/gas/arm/mcpu-cortex-m55-attrs1.d
new file mode 100644
index 00000000000..a5b181fc067
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-m55-attrs1.d
@@ -0,0 +1,16 @@
+#name: Cortex-M55 Attributes 1
+#as: -mcpu=cortex-m55+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-M55"
+  Tag_CPU_arch: v8.1-M.mainline
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Yes
+  Tag_FP_arch: FPv5/FP-D16 for ARMv8
+  Tag_DSP_extension: Allowed
+  Tag_MVE_arch: MVE Integer and FP
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m55-feat-fp-dp.d b/gas/testsuite/gas/arm/mcpu-cortex-m55-feat-fp-dp.d
new file mode 100644
index 00000000000..29e7bc9f8b6
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-m55-feat-fp-dp.d
@@ -0,0 +1,16 @@
+#name: Cortex-M55 feat-fp.dp
+#as: -mcpu=cortex-m55
+#source: feat-fp.dp.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-M55"
+  Tag_CPU_arch: v8.1-M.mainline
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Yes
+  Tag_FP_arch: FPv5/FP-D16 for ARMv8
+  Tag_DSP_extension: Allowed
+  Tag_MVE_arch: MVE Integer and FP
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m55-feat-mve-fp.d b/gas/testsuite/gas/arm/mcpu-cortex-m55-feat-mve-fp.d
new file mode 100644
index 00000000000..9ec48163df6
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-m55-feat-mve-fp.d
@@ -0,0 +1,16 @@
+#name: Cortex-M55 feat-mve.fp
+#as: -mcpu=cortex-m55
+#source: feat-mve.fp.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-M55"
+  Tag_CPU_arch: v8.1-M.mainline
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Yes
+  Tag_FP_arch: FPv5/FP-D16 for ARMv8
+  Tag_DSP_extension: Allowed
+  Tag_MVE_arch: MVE Integer and FP
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m7-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-m7-attrs.d
new file mode 100644
index 00000000000..ad3faf91c1e
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-m7-attrs.d
@@ -0,0 +1,13 @@
+#name: Cortex-M7 Attributes
+#as: -mcpu=cortex-m7+nofp+nofp.dp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-M7"
+  Tag_CPU_arch: v7E-M
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Thumb-2
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m7-feat-fp-dp.d b/gas/testsuite/gas/arm/mcpu-cortex-m7-feat-fp-dp.d
new file mode 100644
index 00000000000..46045a1a3a5
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-m7-feat-fp-dp.d
@@ -0,0 +1,14 @@
+#name: Cortex-M7 feat-fp.dp
+#as: -mcpu=cortex-m7
+#source: feat-fp.dp.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-M7"
+  Tag_CPU_arch: v7E-M
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FPv5/FP-D16 for ARMv8
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m85-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-m85-attrs.d
new file mode 100644
index 00000000000..558cacd4ba8
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-m85-attrs.d
@@ -0,0 +1,14 @@
+#name: Cortex-M85 Attributes
+#as: -mcpu=cortex-m85+nopacbti+nomve.fp+nomve+nofp+nodsp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-M85"
+  Tag_CPU_arch: v8.1-M.mainline
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Yes
+  Tag_DSP_extension: Allowed
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m85-feat-fp-dp.d b/gas/testsuite/gas/arm/mcpu-cortex-m85-feat-fp-dp.d
new file mode 100644
index 00000000000..711bea59a91
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-m85-feat-fp-dp.d
@@ -0,0 +1,16 @@
+#name: Cortex-M85 feat-fp.dp
+#as: -mcpu=cortex-m85
+#source: feat-fp.dp.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-M85"
+  Tag_CPU_arch: v8.1-M.mainline
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Yes
+  Tag_FP_arch: FPv5/FP-D16 for ARMv8
+  Tag_DSP_extension: Allowed
+  Tag_MVE_arch: MVE Integer and FP
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m85-feat-mve-fp.d b/gas/testsuite/gas/arm/mcpu-cortex-m85-feat-mve-fp.d
new file mode 100644
index 00000000000..6533fc66e4e
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-m85-feat-mve-fp.d
@@ -0,0 +1,16 @@
+#name: Cortex-M85 feat-mve.fp
+#as: -mcpu=cortex-m85
+#source: feat-mve.fp.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-M85"
+  Tag_CPU_arch: v8.1-M.mainline
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Yes
+  Tag_FP_arch: FPv5/FP-D16 for ARMv8
+  Tag_DSP_extension: Allowed
+  Tag_MVE_arch: MVE Integer and FP
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m85-feat-pacbti.d b/gas/testsuite/gas/arm/mcpu-cortex-m85-feat-pacbti.d
new file mode 100644
index 00000000000..dc615de9327
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-m85-feat-pacbti.d
@@ -0,0 +1,16 @@
+#name: Cortex-M85 feat-pacbti
+#as: -mcpu=cortex-m85
+#source: feat-pacbti.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-M85"
+  Tag_CPU_arch: v8.1-M.mainline
+  Tag_CPU_arch_profile: Microcontroller
+  Tag_THUMB_ISA_use: Yes
+  Tag_FP_arch: FPv5/FP-D16 for ARMv8
+  Tag_DSP_extension: Allowed
+  Tag_MVE_arch: MVE Integer and FP
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r4f-feat-fp-vfpv3.d b/gas/testsuite/gas/arm/mcpu-cortex-r4f-feat-fp-vfpv3.d
new file mode 100644
index 00000000000..a6361398eb9
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-r4f-feat-fp-vfpv3.d
@@ -0,0 +1,15 @@
+#name: Cortex R4F feat-fp-vfpv3
+#as: -mcpu=cortex-r4f
+#source: feat-fp-vfpv3.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-R4F"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Realtime
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3-D16
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r5-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-r5-attrs.d
new file mode 100644
index 00000000000..802ee1cb00a
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-r5-attrs.d
@@ -0,0 +1,15 @@
+#name: Cortex-R5 Attributes
+#as: -mcpu=cortex-r5+nofp+nofp.dp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-R5"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Realtime
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_DIV_use: Allowed in v7-A with integer division extension
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r5-feat-fp-vfpv3.d b/gas/testsuite/gas/arm/mcpu-cortex-r5-feat-fp-vfpv3.d
new file mode 100644
index 00000000000..4ee716dfe6a
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-r5-feat-fp-vfpv3.d
@@ -0,0 +1,16 @@
+#name: Cortex-R5 feat-fp-vfpv3
+#as: -mcpu=cortex-r5
+#source: feat-fp-vfpv3.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-R5"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Realtime
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3
+  Tag_DIV_use: Allowed in v7-A with integer division extension
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r5-feat-idiv.d b/gas/testsuite/gas/arm/mcpu-cortex-r5-feat-idiv.d
new file mode 100644
index 00000000000..71b2d2ee073
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-r5-feat-idiv.d
@@ -0,0 +1,16 @@
+#name: Cortex-R5 feat-idiv
+#as: -mcpu=cortex-r5
+#source: feat-idiv.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-R5"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Realtime
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3
+  Tag_DIV_use: Allowed in v7-A with integer division extension
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r52-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-r52-attrs.d
new file mode 100644
index 00000000000..33422be2cce
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-r52-attrs.d
@@ -0,0 +1,17 @@
+#name: Cortex-R52 Attributes
+#as: -mcpu=cortex-r52+nofp.dp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-R52"
+  Tag_CPU_arch: v8-R
+  Tag_CPU_arch_profile: Realtime
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FPv5/FP-D16 for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r52-feat-crc.d b/gas/testsuite/gas/arm/mcpu-cortex-r52-feat-crc.d
new file mode 100644
index 00000000000..71055cce2a2
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-r52-feat-crc.d
@@ -0,0 +1,18 @@
+#name: Cortex-R52 feat-crc
+#as: -mcpu=cortex-r52
+#source: feat-crc.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-R52"
+  Tag_CPU_arch: v8-R
+  Tag_CPU_arch_profile: Realtime
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r52-feat-simd.d b/gas/testsuite/gas/arm/mcpu-cortex-r52-feat-simd.d
new file mode 100644
index 00000000000..148400ef1d9
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-r52-feat-simd.d
@@ -0,0 +1,18 @@
+#name: Cortex-R52 feat-simd
+#as: -mcpu=cortex-r52
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-R52"
+  Tag_CPU_arch: v8-R
+  Tag_CPU_arch_profile: Realtime
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r52plus-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-r52plus-attrs.d
new file mode 100644
index 00000000000..e2eb9c35fe7
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-r52plus-attrs.d
@@ -0,0 +1,17 @@
+#name: Cortex-R52plus Attributes
+#as: -mcpu=cortex-r52plus+nofp.dp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-R52\+"
+  Tag_CPU_arch: v8-R
+  Tag_CPU_arch_profile: Realtime
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FPv5/FP-D16 for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r52plus-feat-crc.d b/gas/testsuite/gas/arm/mcpu-cortex-r52plus-feat-crc.d
new file mode 100644
index 00000000000..2666aaf1588
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-r52plus-feat-crc.d
@@ -0,0 +1,18 @@
+#name: Cortex-R52plus feat-crc
+#as: -mcpu=cortex-r52plus
+#source: feat-crc.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-R52\+"
+  Tag_CPU_arch: v8-R
+  Tag_CPU_arch_profile: Realtime
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r52plus-feat-simd.d b/gas/testsuite/gas/arm/mcpu-cortex-r52plus-feat-simd.d
new file mode 100644
index 00000000000..1af6862ca1c
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-r52plus-feat-simd.d
@@ -0,0 +1,18 @@
+#name: Cortex-R52plus feat-simd
+#as: -mcpu=cortex-r52plus
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-R52\+"
+  Tag_CPU_arch: v8-R
+  Tag_CPU_arch_profile: Realtime
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r7-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-r7-attrs.d
new file mode 100644
index 00000000000..b8fa7c90c1b
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-r7-attrs.d
@@ -0,0 +1,15 @@
+#name: Cortex-R7 Attributes
+#as: -mcpu=cortex-r7+nofp+nofp.dp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-R7"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Realtime
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_DIV_use: Allowed in v7-A with integer division extension
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r7-feat-idiv.d b/gas/testsuite/gas/arm/mcpu-cortex-r7-feat-idiv.d
new file mode 100644
index 00000000000..ac04305c3a3
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-r7-feat-idiv.d
@@ -0,0 +1,17 @@
+#name: Cortex-R7 feat-idiv
+#as: -mcpu=cortex-r7
+#source: feat-idiv.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-R7"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Realtime
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3-D16
+  Tag_FP_HP_extension: Allowed
+  Tag_DIV_use: Allowed in v7-A with integer division extension
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r7-feat-vfpv3-d16-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-r7-feat-vfpv3-d16-fp16.d
new file mode 100644
index 00000000000..9361607a70c
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-r7-feat-vfpv3-d16-fp16.d
@@ -0,0 +1,17 @@
+#name: Cortex-R7 feat-vfpv3-d16-fp16
+#as: -mcpu=cortex-r7
+#source: feat-vfpv3-d16-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-R7"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Realtime
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3-D16
+  Tag_FP_HP_extension: Allowed
+  Tag_DIV_use: Allowed in v7-A with integer division extension
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r8-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-r8-attrs.d
new file mode 100644
index 00000000000..2bd0bf4378d
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-r8-attrs.d
@@ -0,0 +1,15 @@
+#name: Cortex-R8 Attributes
+#as: -mcpu=cortex-r8+nofp+nofp.dp
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-R8"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Realtime
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_DIV_use: Allowed in v7-A with integer division extension
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r8-feat-idiv.d b/gas/testsuite/gas/arm/mcpu-cortex-r8-feat-idiv.d
new file mode 100644
index 00000000000..df3f2b561ef
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-r8-feat-idiv.d
@@ -0,0 +1,17 @@
+#name: Cortex-R8 feat-idiv
+#as: -mcpu=cortex-r8
+#source: feat-idiv.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-R8"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Realtime
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3-D16
+  Tag_FP_HP_extension: Allowed
+  Tag_DIV_use: Allowed in v7-A with integer division extension
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r8-feat-vfpv3-d16-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-r8-feat-vfpv3-d16-fp16.d
new file mode 100644
index 00000000000..09a254d76ca
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-r8-feat-vfpv3-d16-fp16.d
@@ -0,0 +1,17 @@
+#name: Cortex-R8 feat-vfpv3-d16-fp16
+#as: -mcpu=cortex-r8
+#source: feat-vfpv3-d16-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-R8"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Realtime
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3-D16
+  Tag_FP_HP_extension: Allowed
+  Tag_DIV_use: Allowed in v7-A with integer division extension
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-x1-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-x1-attrs.d
new file mode 100644
index 00000000000..960aed9ac94
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-x1-attrs.d
@@ -0,0 +1,18 @@
+#name: Cortex-X1 Attributes
+#as: -mcpu=cortex-x1+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-X1"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-x1-feat-dotprod.d b/gas/testsuite/gas/arm/mcpu-cortex-x1-feat-dotprod.d
new file mode 100644
index 00000000000..e49e914757d
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-x1-feat-dotprod.d
@@ -0,0 +1,18 @@
+#name: Cortex-X1 feat-dotprod
+#as: -mcpu=cortex-x1
+#source: feat-dotprod.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-X1"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-x1-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-x1-feat-fp16.d
new file mode 100644
index 00000000000..3bdf1c2557b
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-x1-feat-fp16.d
@@ -0,0 +1,18 @@
+#name: Cortex-X1 feat-fp16
+#as: -mcpu=cortex-x1
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-X1"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-x1c-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-x1c-attrs.d
new file mode 100644
index 00000000000..1e9d8e147eb
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-x1c-attrs.d
@@ -0,0 +1,18 @@
+#name: Cortex-X1C Attributes
+#as: -mcpu=cortex-x1c+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-X1C"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-x1c-feat-dotprod.d b/gas/testsuite/gas/arm/mcpu-cortex-x1c-feat-dotprod.d
new file mode 100644
index 00000000000..186b4068b0a
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-x1c-feat-dotprod.d
@@ -0,0 +1,18 @@
+#name: Cortex-X1C feat-dotprod
+#as: -mcpu=cortex-x1c
+#source: feat-dotprod.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-X1C"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-cortex-x1c-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-x1c-feat-fp16.d
new file mode 100644
index 00000000000..23c70c14a23
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-cortex-x1c-feat-fp16.d
@@ -0,0 +1,18 @@
+#name: Cortex-X1C feat-fp16
+#as: -mcpu=cortex-x1c
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Cortex-X1C"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-exynos-m1-attrs.d b/gas/testsuite/gas/arm/mcpu-exynos-m1-attrs.d
new file mode 100644
index 00000000000..f898b63bef3
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-exynos-m1-attrs.d
@@ -0,0 +1,18 @@
+#name: Exynos-M1 Attributes
+#as: -mcpu=exynos-m1+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Samsung Exynos M1"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-exynos-m1-feat-crc.d b/gas/testsuite/gas/arm/mcpu-exynos-m1-feat-crc.d
new file mode 100644
index 00000000000..ca932b7330a
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-exynos-m1-feat-crc.d
@@ -0,0 +1,18 @@
+#name: Exynos-M1 feat-crc
+#as: -mcpu=exynos-m1
+#source: feat-crc.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Samsung Exynos M1"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-exynos-m1-feat-simd.d b/gas/testsuite/gas/arm/mcpu-exynos-m1-feat-simd.d
new file mode 100644
index 00000000000..0e2976aa4f9
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-exynos-m1-feat-simd.d
@@ -0,0 +1,18 @@
+#name: Exynos-M1 feat-simd
+#as: -mcpu=exynos-m1
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Samsung Exynos M1"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-marvell-pj4-feat-fp-vfpv3.d b/gas/testsuite/gas/arm/mcpu-marvell-pj4-feat-fp-vfpv3.d
new file mode 100644
index 00000000000..2f0e17e4338
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-marvell-pj4-feat-fp-vfpv3.d
@@ -0,0 +1,17 @@
+#name: Marvell-PJ4 feat-fp-vfpv3
+#as: -mcpu=marvell-pj4
+#source: feat-fp-vfpv3.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "MARVELL-PJ4"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone
diff --git a/gas/testsuite/gas/arm/mcpu-marvell-pj4-feat-mp.d b/gas/testsuite/gas/arm/mcpu-marvell-pj4-feat-mp.d
new file mode 100644
index 00000000000..67bbd6c916d
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-marvell-pj4-feat-mp.d
@@ -0,0 +1,17 @@
+#name: Marvell-PJ4 feat-mp
+#as: -mcpu=marvell-pj4
+#source: feat-mp.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "MARVELL-PJ4"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone
diff --git a/gas/testsuite/gas/arm/mcpu-marvell-pj4-feat-sec.d b/gas/testsuite/gas/arm/mcpu-marvell-pj4-feat-sec.d
new file mode 100644
index 00000000000..aa41494cf7d
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-marvell-pj4-feat-sec.d
@@ -0,0 +1,17 @@
+#name: Marvell-PJ4 feat-sec
+#as: -mcpu=marvell-pj4
+#source: feat-sec.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "MARVELL-PJ4"
+  Tag_CPU_arch: v7
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: VFPv3
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone
diff --git a/gas/testsuite/gas/arm/mcpu-neoverse-n1-attrs.d b/gas/testsuite/gas/arm/mcpu-neoverse-n1-attrs.d
new file mode 100644
index 00000000000..c850ee0b139
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-neoverse-n1-attrs.d
@@ -0,0 +1,18 @@
+#name: Neoverse-N1 Attributes
+#as: -mcpu=neoverse-n1+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Neoverse N1"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-neoverse-n1-feat-dotprod.d b/gas/testsuite/gas/arm/mcpu-neoverse-n1-feat-dotprod.d
new file mode 100644
index 00000000000..b35d1ee4c44
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-neoverse-n1-feat-dotprod.d
@@ -0,0 +1,18 @@
+#name: Neoverse-N1 feat-dotprod
+#as: -mcpu=neoverse-n1
+#source: feat-dotprod.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Neoverse N1"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-neoverse-n1-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-neoverse-n1-feat-fp16.d
new file mode 100644
index 00000000000..36a02e8dc24
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-neoverse-n1-feat-fp16.d
@@ -0,0 +1,18 @@
+#name: Neoverse-N1 feat-fp16
+#as: -mcpu=neoverse-n1
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Neoverse N1"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-neoverse-n2-attrs.d b/gas/testsuite/gas/arm/mcpu-neoverse-n2-attrs.d
new file mode 100644
index 00000000000..9a4360e35b1
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-neoverse-n2-attrs.d
@@ -0,0 +1,18 @@
+#name: Neoverse-N2 Attributes
+#as: -mcpu=neoverse-n2+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Neoverse N2"
+  Tag_CPU_arch: v9
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-neoverse-n2-feat-bf16.d b/gas/testsuite/gas/arm/mcpu-neoverse-n2-feat-bf16.d
new file mode 100644
index 00000000000..955130e1102
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-neoverse-n2-feat-bf16.d
@@ -0,0 +1,18 @@
+#name: Neoverse-N2 feat-bf16
+#as: -mcpu=neoverse-n2
+#source: feat-bf16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Neoverse N2"
+  Tag_CPU_arch: v9
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-neoverse-n2-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-neoverse-n2-feat-fp16.d
new file mode 100644
index 00000000000..72e15f84577
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-neoverse-n2-feat-fp16.d
@@ -0,0 +1,18 @@
+#name: Neoverse-N2 feat-fp16
+#as: -mcpu=neoverse-n2
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Neoverse N2"
+  Tag_CPU_arch: v9
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-neoverse-n2-feat-i8mm.d b/gas/testsuite/gas/arm/mcpu-neoverse-n2-feat-i8mm.d
new file mode 100644
index 00000000000..380e4ce850d
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-neoverse-n2-feat-i8mm.d
@@ -0,0 +1,18 @@
+#name: Neoverse-N2 feat-i8mm
+#as: -mcpu=neoverse-n2
+#source: feat-i8mm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Neoverse N2"
+  Tag_CPU_arch: v9
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-neoverse-v1-attrs.d b/gas/testsuite/gas/arm/mcpu-neoverse-v1-attrs.d
new file mode 100644
index 00000000000..9478192edfe
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-neoverse-v1-attrs.d
@@ -0,0 +1,18 @@
+#name: Neoverse-V1 Attributes
+#as: -mcpu=neoverse-v1+crypto
+#source: nop-asm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Neoverse V1"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-neoverse-v1-feat-bf16.d b/gas/testsuite/gas/arm/mcpu-neoverse-v1-feat-bf16.d
new file mode 100644
index 00000000000..48efeeabba7
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-neoverse-v1-feat-bf16.d
@@ -0,0 +1,18 @@
+#name: Neoverse-V1 feat-bf16
+#as: -mcpu=neoverse-v1
+#source: feat-bf16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Neoverse V1"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-neoverse-v1-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-neoverse-v1-feat-fp16.d
new file mode 100644
index 00000000000..59040dc0660
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-neoverse-v1-feat-fp16.d
@@ -0,0 +1,18 @@
+#name: Neoverse-V1 feat-fp16
+#as: -mcpu=neoverse-v1
+#source: feat-fp16.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Neoverse V1"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-neoverse-v1-feat-i8mm.d b/gas/testsuite/gas/arm/mcpu-neoverse-v1-feat-i8mm.d
new file mode 100644
index 00000000000..be46641d570
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-neoverse-v1-feat-i8mm.d
@@ -0,0 +1,18 @@
+#name: Neoverse-V1 feat-i8mm
+#as: -mcpu=neoverse-v1
+#source: feat-i8mm.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "Neoverse V1"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
diff --git a/gas/testsuite/gas/arm/mcpu-xgene1-feat-simd.d b/gas/testsuite/gas/arm/mcpu-xgene1-feat-simd.d
new file mode 100644
index 00000000000..e8ef6a837a2
--- /dev/null
+++ b/gas/testsuite/gas/arm/mcpu-xgene1-feat-simd.d
@@ -0,0 +1,18 @@
+#name: XGene1 feat-simd
+#as: -mcpu=xgene1
+#source: feat-simd.s
+#readelf: -A
+# This test is only valid on EABI based ports.
+# target: *-*-*eabi*
+
+Attribute Section: aeabi
+File Attributes
+  Tag_CPU_name: "APM X-Gene 1"
+  Tag_CPU_arch: v8
+  Tag_CPU_arch_profile: Application
+  Tag_ARM_ISA_use: Yes
+  Tag_THUMB_ISA_use: Thumb-2
+  Tag_FP_arch: FP for ARMv8
+  Tag_Advanced_SIMD_arch: NEON for ARMv8
+  Tag_MPextension_use: Allowed
+  Tag_Virtualization_use: TrustZone and Virtualization Extensions
-- 
2.43.0


From amodra@gmail.com  Thu Jun 18 21:59:00 2026
From: amodra@gmail.com (Alan Modra)
Date: Fri, 19 Jun 2026 07:29:00 +0930
Subject: [PATCH] ld: Use 0x10000 as absolute symbol value in PR ld/25754
 tests
In-Reply-To: <CAMe9rOomM1cKXNZLU0A60xe8cc45zHgZdiKqZOtH2ephQUhwEQ@mail.gmail.com>
References: <CAMe9rOomM1cKXNZLU0A60xe8cc45zHgZdiKqZOtH2ephQUhwEQ@mail.gmail.com>
Message-ID: <ajRqJH6RCk_XjjnD@squeak.grove.modra.org>

On Thu, Jun 18, 2026 at 08:05:37PM +0800, H.J. Lu wrote:
> PR ld/25754 tests verify that relocations against absolute symbol are
> properly handled, using 42 as the absolute symbol value.  But GCC 17
> treats 42 as the impossible symbol address, which is the absolute symbol
> value and optimize out the symbol address check:
> 
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=125869
> 
> Use 0x10000, instead of 42, as absolute symbol value to work with GCC 17.
> 
> PR ld/34298
> * testsuite/ld-elf/pr25754-1a.c (main): Check against 0x10000
> instead of 42.
> * testsuite/ld-elf/pr25754-1b.s (bar): Replace 42 with 0x10000.

OK.

-- 
Alan Modra

From robot@translationproject.org  Fri Jun 19 07:42:21 2026
From: robot@translationproject.org (Translation Project Robot)
Date: Fri, 19 Jun 2026 09:42:21 +0200
Subject: New Malay PO file for 'bfd' (version 2.45.90)
Message-ID: <E1waTrp-00158Q-0N@duik.vrijschrift.org>

Hello, gentle maintainer.

This is a message from the Translation Project robot.

A revised PO file for textual domain 'bfd' has been submitted
by the Malay team of translators.  The file is available at:

    https://translationproject.org/latest/bfd/ms.po

(We can arrange things so that in the future such files are automatically
e-mailed to you when they arrive.  Ask at the address below if you want this.)

All other PO files for your package are available in:

    https://translationproject.org/latest/bfd/

Please consider including all of these in your next release, whether
official or a pretest.

Whenever you have a new distribution with a new version number ready,
containing a newer POT file, please send the URL of that distribution
tarball to the address below.  The tarball may be just a pretest or a
snapshot, it does not even have to compile.  It is just used by the
translators when they need some extra translation context.

The following HTML page has been updated:

    https://translationproject.org/domain/bfd.html

If any question arises, please contact the translation coordinator.

Thank you for all your work,

                                The Translation Project robot, in the
                                name of your translation coordinator.
                                <coordinator@translationproject.org>


From jbeulich@suse.com  Fri Jun 19 08:15:41 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 19 Jun 2026 10:15:41 +0200
Subject: [PATCH 0/3] gas: escapes in strings
Message-ID: <120092a3-6629-493c-ab22-c9692d212c19@suse.com>

While dealing with [1] I noticed further anomalies.

1: ignore ONLY_STANDARD_ESCAPES in scrubber
2: don't recognize '8' and '9' as octal escape chars in strings
3: scrubber handling of string continuation across lines

Jan

[1] https://sourceware.org/pipermail/binutils/2026-June/149558.html

From jbeulich@suse.com  Fri Jun 19 08:17:37 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 19 Jun 2026 10:17:37 +0200
Subject: [PATCH 1/3] gas: ignore ONLY_STANDARD_ESCAPES in scrubber
In-Reply-To: <120092a3-6629-493c-ab22-c9692d212c19@suse.com>
References: <120092a3-6629-493c-ab22-c9692d212c19@suse.com>
Message-ID: <4a9d68ab-c87c-4cb0-8ef1-e2969a5fdde1@suse.com>

The handling there is broken in several ways:
- It gets in the way of macro parameter names starting with one of the not
  special cased values.
- For perhaps a small set of targets (SINGLE_QUOTE_STRINGS, M68k MRI
  mode): While the "quotechar" static variable allows for string quotation
  by other than '"', the case labels circumventing the warning only (and
  potentially wrongly) cover '"'.

read.c:next_char_of_string() having similar checking in place, drop the
special casing (as as_warn() invocation) from here.

While adjusting macros/macros.exp XFAIL-ary for an affected testcase,
correct the referenced manifest symbol at the same time.

--- a/gas/app.c
+++ b/gas/app.c
@@ -712,35 +712,7 @@ do_scrub_chars (size_t (*get) (char *, s
 	      PUT (quotechar);
 	      continue;
 
-	      /* These two are used inside macros.  */
-	    case '@':
-	    case '+':
-	      break;
-
-	    case '"':
-	    case '\\':
-	    case 'b':
-	    case 'f':
-	    case 'n':
-	    case 'r':
-	    case 't':
-	    case 'v':
-	    case 'x':
-	    case 'X':
-	    case '0':
-	    case '1':
-	    case '2':
-	    case '3':
-	    case '4':
-	    case '5':
-	    case '6':
-	    case '7':
-	      break;
-
 	    default:
-#ifdef ONLY_STANDARD_ESCAPES
-	      as_warn (_("unknown escape '\\%c' in string; ignored"), ch);
-#endif
 	      break;
 	    }
 	  PUT (ch);
--- a/gas/testsuite/gas/macros/macros.exp
+++ b/gas/testsuite/gas/macros/macros.exp
@@ -53,13 +53,9 @@ switch -glob $target_triplet {
 }
 
 if { ![istarget hppa*-*-*] || [istarget *-*-linux*] } {
-    # FIXME: Due to macro mishandling of ONLY_STANDARD_ESCAPES.
-    setup_xfail "avr-*" "cris-*" "crisv32-*" "msp430-*"
-
-    # These fail due to NO_STRING_ESCAPES
+    # These fail due to !TC_STRING_ESCAPES
     setup_xfail "powerpc*-*-aix*" "powerpc*-*-beos*" "powerpc*-*-macos*"
     setup_xfail "rs6000-*-*"
-    setup_xfail "z80-*-*"
 
     # FIXME: Due to difference in what "consecutive octets" means.
     setup_xfail "*c4x*-*-*" "*c54x*-*"


From jbeulich@suse.com  Fri Jun 19 08:17:57 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 19 Jun 2026 10:17:57 +0200
Subject: [PATCH 2/3] gas: don't recognize '8' and '9' as octal escape chars in
 strings
In-Reply-To: <120092a3-6629-493c-ab22-c9692d212c19@suse.com>
References: <120092a3-6629-493c-ab22-c9692d212c19@suse.com>
Message-ID: <53e012cb-de27-4b69-8fed-f4d3571ae87a@suse.com>

It's not clear why these were covered; it has been like this from the very
beginning of (available) source history. Yet more oddly, an old ia64
testcase actually uses such malformed escape sequences (which are being
adjusted).

--- a/gas/read.c
+++ b/gas/read.c
@@ -6206,14 +6206,12 @@ next_char_of_string (void)
 	case '5':
 	case '6':
 	case '7':
-	case '8':
-	case '9':
 	  {
 	    unsigned number;
 	    int i;
 
 	    for (i = 0, number = 0;
-		 ISDIGIT (c) && i < 3;
+		 i < 3 && c >= '0' && c <= '7';
 		 c = *input_line_pointer++, i++)
 	      {
 		number = number * 8 + c - '0';
--- a/gas/testsuite/gas/ia64/alias.s
+++ b/gas/testsuite/gas/ia64/alias.s
@@ -1,11 +1,11 @@
 	.section .foo,"aw","progbits"
 	.secalias .foo,"1234"
 	.secalias .foo,"1234"
-	.alias foo, "\"\80\84\""
-	.alias foo, "\"\80\84\""
+	.alias foo, "\"\100\104\""
+	.alias foo, "\"\100\104\""
 foo:
-	stringz "\"\80\84\""
+	stringz "\"\x40\x44\""
 	.secalias .foo,"1234"
 	.secalias .foo,"1234"
-	.alias foo, "\"\80\84\""
-	.alias foo, "\"\80\84\""
+	.alias foo, "\"\x40\x44\""
+	.alias foo, "\"\x40\x44\""


From jbeulich@suse.com  Fri Jun 19 08:18:18 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 19 Jun 2026 10:18:18 +0200
Subject: [PATCH 3/3] gas: scrubber handling of string continuation across lines
In-Reply-To: <120092a3-6629-493c-ab22-c9692d212c19@suse.com>
References: <120092a3-6629-493c-ab22-c9692d212c19@suse.com>
Message-ID: <f68023f3-27d0-4cb6-8cda-09accefca691@suse.com>

Apparently forever (according to [available] history) two backslashes have
been emitted when, afaict, only one was meant.
---
RFC: Of course the behavior here (with or without this change) has an
     unwanted effect: With

	.macro m n:req
	.print "n: >>>\n<<<"
	.print ">>>\
<<<"
	.endm

     the 2nd .print use also references the "n" macro parameter. Problem
     being that at the scrubbing stage different forms of quoted entities
     (directive vs macro arguments) cannot be distinguished. Question
     therefore is whether such string continuation handling is useful in
     the first place.

--- a/gas/app.c
+++ b/gas/app.c
@@ -699,12 +699,12 @@ do_scrub_chars (size_t (*get) (char *, s
 	  ch = GET ();
 	  switch (ch)
 	    {
-	      /* Handle strings broken across lines, by turning '\n' into
-		 '\\' and 'n'.  */
+	      /* Handle strings broken across lines, by turning '\\' followed
+		 by '\n' into '\\' (already emitted when state moved to 6) and
+		 'n'.  */
 	    case '\n':
-	      UNGET ('n');
 	      add_newlines++;
-	      PUT ('\\');
+	      PUT ('n');
 	      continue;
 
 	    case EOF:


From jbeulich@suse.com  Fri Jun 19 11:45:25 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 19 Jun 2026 13:45:25 +0200
Subject: [PATCH v3 00/13] RISC-V: assorted fixes and (hopefully) improvements
Message-ID: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>

There may not be many dependencies among the patches, but the issues
were all noticed more or less together (i.e. while addressing one,
the next one popped up). I've not made an attempt at sorting the V vs
Z?inx issue, as per Andrew's request.

Quite a few further points are made in remarks in individual patches.
Input there is very welcome.

Jiawei kindly reviewed v1 and v2, and I meanwhile committed a few more
patches from there, which I assumed were pretty sure to be reasonably
uncontroversial. For the others I'd prefer RISC-V maintainer approval,
yet I'm not going to wait indefinitely.

There aren't many changes in v3. See individual changes for what
changed, if anything.

01: RISC-V: add dedicated vector arithmetic .insn forms
02: RISC-V: EEW64 checking
03: bfd/RISC-V: Zvfbfwma implies Zvfbfmin
04: RISC-V: Zv{b,k}* imply Zve32x
05: RISC-V: drop FCVT.Q.L{,U} forms with rounding mode operand
06: RISC-V: make FP rounding mode an optional argument
07: RISC-V: check operands for Zdinx in RV32
08: RISC-V: check operands for Zqinx
09: RISC-V/gas: .attribute vs .insn
10: RISC-V/gas: warn about non-boolean unaligned-access attribute
11: RISC-V/gas: warn about non-power-of-2 stack-align attribute
12: RISC-V/bfd: warn about non-boolean unaligned-access attribute
13: RISC-V/bfd: warn about non-power-of-2 stack-align attribute

I'd also like to point out that [1] continues to be pending. I'm
far from insisting that that patch be taken, but something needs
doing about the issue.

Jan

[1] https://sourceware.org/pipermail/binutils/2023-March/126601.html

From jbeulich@suse.com  Fri Jun 19 11:47:10 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 19 Jun 2026 13:47:10 +0200
Subject: [PATCH v3 01/13] RISC-V: add dedicated vector arithmetic .insn forms
In-Reply-To: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
Message-ID: <81e3d6d0-39d3-42e3-a8cd-d6b11b8449a4@suse.com>

As .insn documentation states, using the available .insn forms can be a
little challenging. For OP_V and OP_VE, help the situation by providing a
few more dedicated forms.
---
No form is provided for OPCFG: Such insns may better use "r" forms, or
whatever is best suited there.

For OPIVI permitting both signed (Vi) and unsigned (Vj) immediates might
be nice, but won't work with the present parsing (needs delaying
as_bad()).

To help encoding V*UNARY* insns, forms with immediates in the respective
positions may be helpful. Thoughts? (Some of the testcase additions are
commented upon accordingly.)
---
v3: Add O7 as first operand.

--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1631,6 +1631,7 @@ validate_riscv_insn (const struct riscv_
 	  switch (*++oparg)
 	    {
 	    case '7': USE_BITS (OP_MASK_FUNCT7, OP_SH_FUNCT7); break;
+	    case '6': USE_BITS (OP_MASK_FUNCT6, OP_SH_FUNCT6); break;
 	    case '3': USE_BITS (OP_MASK_FUNCT3, OP_SH_FUNCT3); break;
 	    case '2': USE_BITS (OP_MASK_FUNCT2, OP_SH_FUNCT2); break;
 	    default:
@@ -3763,6 +3764,10 @@ riscv_ip (char *str, struct riscv_cl_ins
 		  INSERT_OPERAND (FUNCT7, *ip, imm_expr->X_add_number);
 		  break;
 
+		case 6:
+		  INSERT_OPERAND (FUNCT6, *ip, imm_expr->X_add_number);
+		  break;
+
 		case 3:
 		  INSERT_OPERAND (FUNCT3, *ip, imm_expr->X_add_number);
 		  break;
--- a/gas/testsuite/gas/riscv/insn.d
+++ b/gas/testsuite/gas/riscv/insn.d
@@ -70,6 +70,20 @@ Disassembly of section .text:
 [^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
 [^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
 [^:]+:[ 	]+022180d7[ 	]+vadd\.vv[ 	]+v1,v2,v3
+[^:]+:[ 	]+2c2081d7[ 	]+vxor\.vv[ 	]+v3,v2,v1,v0\.t
+[^:]+:[ 	]+182091d7[ 	]+vfmax\.vv[ 	]+v3,v2,v1,v0\.t
+[^:]+:[ 	]+fc1111d7[ 	]+vfwnmsac\.vv[ 	]+v3,v2,v1,v0\.t
+[^:]+:[ 	]+422010d7[ 	]+vfmv\.f\.s[ 	]+ft1,v2
+[^:]+:[ 	]+7a20a1d7[ 	]+vmnor\.mm[ 	]+v3,v2,v1
+[^:]+:[ 	]+422020d7[ 	]+vmv\.x\.s[ 	]+ra,v2
+[^:]+:[ 	]+8220a1f7[ 	]+vsm3me\.vv[ 	]+v3,v2,v1
+[^:]+:[ 	]+2c20b1d7[ 	]+vxor\.vi[ 	]+v3,v2,1,v0\.t
+[^:]+:[ 	]+2c20c1d7[ 	]+vxor\.vx[ 	]+v3,v2,ra,v0\.t
+[^:]+:[ 	]+1820d1d7[ 	]+vfmax\.vf[ 	]+v3,v2,ft1,v0\.t
+[^:]+:[ 	]+fc1151d7[ 	]+vfwnmsac\.vf[ 	]+v3,ft2,v1,v0\.t
+[^:]+:[ 	]+420150d7[ 	]+vfmv\.s\.f[ 	]+v1,ft2
+[^:]+:[ 	]+bc1161d7[ 	]+vnmsac\.vx[ 	]+v3,sp,v1,v0\.t
+[^:]+:[ 	]+420160d7[ 	]+vmv\.s\.x[ 	]+v1,sp
 [^:]+:[ 	]+0001[ 	]+nop
 [^:]+:[ 	]+00000013[ 	]+nop
 [^:]+:[ 	]+001f 0000 0000[ 	].*
--- a/gas/testsuite/gas/riscv/insn.s
+++ b/gas/testsuite/gas/riscv/insn.s
@@ -56,6 +56,24 @@ target:
 
 	.insn r  OP_V, 0, 1, x1, x3, x2
 
+	.option push
+	.option arch, +v,+zvksh			# the latter only for disassembly
+	.insn ivv OP_V, 0x0b, v3, v2, v1, v0.t
+	.insn fvv OP_V, 0x06, v3, v2, v1, v0.t
+	.insn fvv OP_V, 0x3f, v3, v1, v2, v0.t
+	.insn fvv OP_V, 0x10, f1, v2, v0	# last operand is opcode
+	.insn mvv OP_V, 0x1e, v3, v2, v1
+	.insn mvv OP_V, 0x10, x1, v2, v0	# last operand is opcode
+	.insn mvv OP_VE, 0x20, v3, v2, v1
+	.insn ivi OP_V, 0x0b, v3, v2, 1, v0.t
+	.insn ivx OP_V, 0x0b, v3, v2, x1, v0.t
+	.insn fvf OP_V, 0x06, v3, v2, f1, v0.t
+	.insn fvf OP_V, 0x3f, v3, v1, f2, v0.t
+	.insn fvf OP_V, 0x10, v1, v0, f2	# middle operand is opcode
+	.insn mvx OP_V, 0x2f, v3, v1, x2, v0.t
+	.insn mvx OP_V, 0x10, v1, v0, x2	# middle operand is opcode
+	.option pop
+
 	.insn 0x0001
 	.insn 0x00000013
 	.insn 0x0000001f
--- a/gas/testsuite/gas/riscv/insn-dwarf.d
+++ b/gas/testsuite/gas/riscv/insn-dwarf.d
@@ -60,28 +60,42 @@ insn.s +53 +0x9a.*
 insn.s +54 +0x9e.*
 insn.s +55 +0xa2.*
 insn.s +57 +0xa6.*
-insn.s +59 +0xaa.*
-insn.s +60 +0xac.*
-insn.s +61 +0xb0.*
-insn.s +62 +0xb6.*
-insn.s +63 +0xbe.*
-insn.s +64 +0xc8.*
-insn.s +65 +0xd4.*
-insn.s +66 +0xea.*
-insn.s +67 +0xec.*
-insn.s +68 +0xf0.*
-insn.s +69 +0xf6.*
-insn.s +70 +0xfe.*
-insn.s +71 +0x108.*
-insn.s +72 +0x114.*
-insn.s +74 +0x12a.*
-insn.s +75 +0x134.*
-insn.s +76 +0x13e.*
-insn.s +77 +0x154.*
-insn.s +78 +0x16a.*
-insn.s +79 +0x180.*
-insn.s +80 +0x196.*
-insn.s +81 +0x1ac.*
-insn.s +83 +0x1c2.*
-insn.s +- +0x1c6
+insn.s +61 +0xaa.*
+insn.s +62 +0xae.*
+insn.s +63 +0xb2.*
+insn.s +64 +0xb6.*
+insn.s +65 +0xba.*
+insn.s +66 +0xbe.*
+insn.s +67 +0xc2.*
+insn.s +68 +0xc6.*
+insn.s +69 +0xca.*
+insn.s +70 +0xce.*
+insn.s +71 +0xd2.*
+insn.s +72 +0xd6.*
+insn.s +73 +0xda.*
+insn.s +74 +0xde.*
+insn.s +77 +0xe2.*
+insn.s +78 +0xe4.*
+insn.s +79 +0xe8.*
+insn.s +80 +0xee.*
+insn.s +81 +0xf6.*
+insn.s +82 +0x100.*
+insn.s +83 +0x10c.*
+insn.s +84 +0x122.*
+insn.s +85 +0x124.*
+insn.s +86 +0x128.*
+insn.s +87 +0x12e.*
+insn.s +88 +0x136.*
+insn.s +89 +0x140.*
+insn.s +90 +0x14c.*
+insn.s +92 +0x162.*
+insn.s +93 +0x16c.*
+insn.s +94 +0x176.*
+insn.s +95 +0x18c.*
+insn.s +96 +0x1a2.*
+insn.s +97 +0x1b8.*
+insn.s +98 +0x1ce.*
+insn.s +99 +0x1e4.*
+insn.s +101 +0x1fa.*
+insn.s +- +0x1fe
 #pass
--- a/gas/testsuite/gas/riscv/insn-na.d
+++ b/gas/testsuite/gas/riscv/insn-na.d
@@ -59,6 +59,20 @@ Disassembly of section .text:
 [^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
 [^:]+:[ 	]+00c58533[ 	]+add[ 	]+a0,a1,a2
 [^:]+:[ 	]+022180d7[ 	]+vadd\.vv[ 	]+v1,v2,v3
+[^:]+:[ 	]+2c2081d7[ 	]+vxor\.vv[ 	]+v3,v2,v1,v0\.t
+[^:]+:[ 	]+182091d7[ 	]+vfmax\.vv[ 	]+v3,v2,v1,v0\.t
+[^:]+:[ 	]+fc1111d7[ 	]+vfwnmsac\.vv[ 	]+v3,v2,v1,v0\.t
+[^:]+:[ 	]+422010d7[ 	]+vfmv\.f\.s[ 	]+ft1,v2
+[^:]+:[ 	]+7a20a1d7[ 	]+vmnor\.mm[ 	]+v3,v2,v1
+[^:]+:[ 	]+422020d7[ 	]+vmv\.x\.s[ 	]+ra,v2
+[^:]+:[ 	]+8220a1f7[ 	]+vsm3me\.vv[ 	]+v3,v2,v1
+[^:]+:[ 	]+2c20b1d7[ 	]+vxor\.vi[ 	]+v3,v2,1,v0\.t
+[^:]+:[ 	]+2c20c1d7[ 	]+vxor\.vx[ 	]+v3,v2,ra,v0\.t
+[^:]+:[ 	]+1820d1d7[ 	]+vfmax\.vf[ 	]+v3,v2,ft1,v0\.t
+[^:]+:[ 	]+fc1151d7[ 	]+vfwnmsac\.vf[ 	]+v3,ft2,v1,v0\.t
+[^:]+:[ 	]+420150d7[ 	]+vfmv\.s\.f[ 	]+v1,ft2
+[^:]+:[ 	]+bc1161d7[ 	]+vnmsac\.vx[ 	]+v3,sp,v1,v0\.t
+[^:]+:[ 	]+420160d7[ 	]+vmv\.s\.x[ 	]+v1,sp
 [^:]+:[ 	]+0001[ 	]+c\.addi[ 	]+zero,0
 [^:]+:[ 	]+00000013[ 	]+addi[ 	]+zero,zero,0
 [^:]+:[ 	]+001f 0000 0000[ 	].*
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -351,6 +351,9 @@ static inline unsigned int riscv_insn_le
 
 /* RVV fields.  */
 
+#define OP_MASK_FUNCT6		0x3fU
+#define OP_SH_FUNCT6		26
+
 #define OP_MASK_VD		0x1f
 #define OP_SH_VD		7
 #define OP_MASK_VS1		0x1f
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -3660,6 +3660,17 @@ const struct riscv_opcode riscv_insn_typ
 {"j",       0, INSN_CLASS_I,       "O7,d,a",            0, 0, NULL, 0 },
 {"j",       0, INSN_CLASS_F,       "O7,D,a",            0, 0, NULL, 0 },
 
+{"ivv",     0, INSN_CLASS_V,       "O7,F6,Vd,Vt,VsVm", 0x0000, 0x7000, NULL, 0 },
+{"fvv",     0, INSN_CLASS_ZVEF,    "O7,F6,Vd,Vt,VsVm", 0x1000, 0x7000, NULL, 0 },
+{"fvv",     0, INSN_CLASS_ZVEF,    "O7,F6,D,Vt,VsVm",  0x1000, 0x7000, NULL, 0 },
+{"mvv",     0, INSN_CLASS_V,       "O7,F6,Vd,Vt,VsVm", 0x2000, 0x7000, NULL, 0 },
+{"mvv",     0, INSN_CLASS_V,       "O7,F6,d,Vt,VsVm",  0x2000, 0x7000, NULL, 0 },
+{"ivi",     0, INSN_CLASS_V,       "O7,F6,Vd,Vt,ViVm", 0x3000, 0x7000, NULL, 0 },
+{"ivx",     0, INSN_CLASS_V,       "O7,F6,Vd,Vt,sVm",  0x4000, 0x7000, NULL, 0 },
+{"fvf",     0, INSN_CLASS_ZVEF,    "O7,F6,Vd,Vt,SVm",  0x5000, 0x7000, NULL, 0 },
+{"mvx",     0, INSN_CLASS_V,       "O7,F6,Vd,Vt,sVm",  0x6000, 0x7000, NULL, 0 },
+{"mvx",     0, INSN_CLASS_V,       "O7,F6,d,Vt,sVm",   0x6000, 0x7000, NULL, 0 },
+
 {"cr",      0, INSN_CLASS_ZCA,       "O2,CF4,d,CV",       0, 0, NULL, 0 },
 {"cr",      0, INSN_CLASS_ZCF, "O2,CF4,D,CV",       0, 0, NULL, 0 },
 {"cr",      0, INSN_CLASS_ZCF, "O2,CF4,d,CT",       0, 0, NULL, 0 },


From jbeulich@suse.com  Fri Jun 19 11:47:41 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 19 Jun 2026 13:47:41 +0200
Subject: [PATCH v3 02/13] RISC-V: EEW64 checking
In-Reply-To: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
Message-ID: <1a57710b-44d4-4852-91b1-01665b8f383c@suse.com>

Like the assembler, the disassembler should also use the INSN_V_EEW64
flag. Respectively marked insns shouldn't be disassembled normally when
Zve64x isn't enabled.

While there also drop the redundant Zve32x check from gas: All affected
insns are INSN_CLASS_V, which means Zve32x was already checked to be
enabled (both V and Zve64x imply Zve32x).
---
Question is why a flag was used in the first place: The property could be
expressed by a new INSN_CLASS_ZVE64X, couldn't it?

--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -2964,10 +2964,9 @@ riscv_ip (char *str, struct riscv_cl_ins
 		      insn_with_csr = false;
 		    }
 
-		  /* The (segmant) load and store with EEW 64 cannot be used
+		  /* The (segment) load and store with EEW 64 cannot be used
 		     when zve32x is enabled.  */
-		  if (ip->insn_mo->pinfo & INSN_V_EEW64
-		      && riscv_subset_supports (&riscv_rps_as, "zve32x")
+		  if ((ip->insn_mo->pinfo & INSN_V_EEW64)
 		      && !riscv_subset_supports (&riscv_rps_as, "zve64x"))
 		    {
 		      error.msg = _("illegal opcode for zve32x");
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -1018,10 +1018,16 @@ riscv_disassemble_insn (bfd_vma memaddr,
 	      && (op->xlen_requirement != pd->xlen))
 	    continue;
 	  /* Is this instruction supported by the current architecture?  */
-	  if (!pd->all_ext
-	      && !riscv_multi_subset_supports (&pd->riscv_rps_dis,
-					       op->insn_class))
-	    continue;
+	  if (!pd->all_ext)
+	    {
+	      if (!riscv_multi_subset_supports (&pd->riscv_rps_dis,
+						op->insn_class))
+		continue;
+
+ 	      if ((op->pinfo & INSN_V_EEW64)
+		  && !riscv_subset_supports (&pd->riscv_rps_dis, "zve64x"))
+		continue;
+	    }
 
 	  /* It's a match.  */
 	  (*info->fprintf_styled_func) (info->stream, dis_style_mnemonic,
--- /dev/null
+++ b/gas/testsuite/gas/riscv/eew64.d
@@ -0,0 +1,13 @@
+#as: -march=rv32i
+#objdump: -d
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <eew32>:
+[ 	]+0:[ 	]+020ff007[ 	]+\.insn[ 	]+4, ?0x020ff007
+
+0+004 <eew64>:
+[ 	]+4:[ 	]+020ff007[ 	]+vle64\.v[ 	]+v0,\(t6\)
+#pass
--- /dev/null
+++ b/gas/testsuite/gas/riscv/eew64.s
@@ -0,0 +1,12 @@
+	.option arch, rv32i
+	.option arch, +zve32x
+
+eew32:
+	# vle64.v v0, (x31)
+	.insn 4, 0x020ff007
+
+	.option arch, rv32i
+	.option arch, +zve64x
+
+eew64:
+	vle64.v	v0, (x31)


From jbeulich@suse.com  Fri Jun 19 11:48:10 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 19 Jun 2026 13:48:10 +0200
Subject: [PATCH v3 03/13] bfd/RISC-V: Zvfbfwma implies Zvfbfmin
In-Reply-To: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
Message-ID: <7be489de-fb0b-4062-9e40-1238e7a00fc1@suse.com>

This is pretty clear from the spec.
---
While the spec is also explicit there: I would have expected Zvfbfmin (not
Zvfbfwma) to be what implies Zfbfmin. Is there an explanation for this?

--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1232,7 +1232,7 @@ static const struct riscv_implicit_subse
   {"v", "+zve64d,+zvl128b", check_implicit_always},
   {"zvfh", "+zvfhmin,+zfhmin", check_implicit_always},
   {"zvfhmin", "+zve32f", check_implicit_always},
-  {"zvfbfwma", "+zve32f,+zfbfmin", check_implicit_always},
+  {"zvfbfwma", "+zfbfmin,+zvfbfmin", check_implicit_always},
   {"zvfbfmin", "+zve32f", check_implicit_always},
   {"zve64d", "+d,+zve64f", check_implicit_always},
   {"zve64f", "+zve32f,+zve64x,+zvl64b", check_implicit_always},
--- a/gas/testsuite/gas/riscv/imply.d
+++ b/gas/testsuite/gas/riscv/imply.d
@@ -27,7 +27,7 @@ SYMBOL TABLE:
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvl32b1p0
-[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfbfwma1p0_zvl32b1p0
+[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0


From jbeulich@suse.com  Fri Jun 19 11:48:56 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 19 Jun 2026 13:48:56 +0200
Subject: [PATCH v3 04/13] bfd/RISC-V: Zv{b,k}* imply Zve32x
In-Reply-To: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
Message-ID: <0450f2b8-fa5b-4921-b330-d9fe2e2c54b2@suse.com>

The specification is quite explicit about this.
---
Is the placement of "zve32x" after "zvbb" / "zvbc" actually correct? While
riscv_compare_subsets() indeed does a mere strcasecmp() past "zv", it
seems unlikely to be mere chance that Zve* come ahead of all other Zv* in
riscv_supported_std_z_ext[].
---
v3: New.

--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1306,6 +1306,15 @@ static const struct riscv_implicit_subse
   {"zvksc", "+zvks,+zvbc", check_implicit_always},
   {"zvks", "+zvksed,+zvksh,+zvkb,+zvkt", check_implicit_always},
 
+  {"zvbc", "+zve32x", check_implicit_always},
+  {"zvkb", "+zve32x", check_implicit_always},
+  {"zvkg", "+zve32x", check_implicit_always},
+  {"zvkned", "+zve32x", check_implicit_always},
+  {"zvknha", "+zve32x", check_implicit_always},
+  {"zvknhb", "+zve32x", check_implicit_always},
+  {"zvksed", "+zve32x", check_implicit_always},
+  {"zvksh", "+zve32x", check_implicit_always},
+
   {"sdtrig", "+zicsr", check_implicit_always},
 
   {"smaia", "+ssaia", check_implicit_always},
--- a/gas/testsuite/gas/riscv/imply.d
+++ b/gas/testsuite/gas/riscv/imply.d
@@ -87,13 +87,13 @@ SYMBOL TABLE:
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0
-[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvbb1p0_zvkb1p0
-[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0
-[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvbc1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0
-[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0
-[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0
-[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvbc1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0
-[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0
+[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvbb1p0_zve32x1p0_zvkb1p0
+[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zve32x1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0
+[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvbc1p0_zve32x1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0
+[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zve32x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0
+[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zve32x1p0_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0
+[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvbc1p0_zve32x1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0
+[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zve32x1p0_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_sdtrig1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_smaia1p0_ssaia1p0
 [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_smcdeleg1p0_ssccfg1p0_sscsrind1p0


From jbeulich@suse.com  Fri Jun 19 11:49:25 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 19 Jun 2026 13:49:25 +0200
Subject: [PATCH v3 05/13] RISC-V: drop FCVT.Q.L{,U} forms with rounding mode
 operand
In-Reply-To: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
Message-ID: <50d06f39-9de9-476e-a0ed-e211ee777950@suse.com>

Like FCVT.D.W{,U} and FCVT.Q.W{,U} these also are unaffected by rounding
mode, and hence allowing for a respective operand is bogus. (Otherwise
MASK_RM should also be used in the match field for the respectively other
forms.)

--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1165,9 +1165,7 @@ const struct riscv_opcode riscv_opcodes[
 {"fcvt.lu.q", 64, INSN_CLASS_Q_INX,   "d,S",       MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 },
 {"fcvt.lu.q", 64, INSN_CLASS_Q_INX,   "d,S,m",     MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 },
 {"fcvt.q.l",  64, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
-{"fcvt.q.l",  64, INSN_CLASS_Q_INX,   "D,s,m",     MATCH_FCVT_Q_L, MASK_FCVT_Q_L, match_opcode, 0 },
 {"fcvt.q.lu", 64, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 },
-{"fcvt.q.lu", 64, INSN_CLASS_Q_INX,   "D,s,m",     MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU, match_opcode, 0 },
 
 /* Compressed instructions.  */
 {"c.unimp",    0, INSN_CLASS_ZCA,   "",          0, 0xffffU,  match_opcode, 0 },


From jbeulich@suse.com  Fri Jun 19 11:50:13 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 19 Jun 2026 13:50:13 +0200
Subject: [PATCH v3 06/13] RISC-V: make FP rounding mode an optional operand
In-Reply-To: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
Message-ID: <4fe30051-625f-448d-82b3-a232e9b0308a@suse.com>

Model this after Vm (and somewhat after its VM counterpart): It's similarly
always last, and we can hence similarly reduce the number of entries in the
opcode table. The exception being FCVTMOD.W.D, where M needs using.

--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1612,6 +1612,7 @@ validate_riscv_insn (const struct riscv_
 	case 't': USE_BITS (OP_MASK_RS2, OP_SH_RS2); break;
 	case 'R': /* RS3, floating point.  */
 	case 'r': USE_BITS (OP_MASK_RS3, OP_SH_RS3); break;
+	case 'M':
 	case 'm': USE_BITS (OP_MASK_RM, OP_SH_RM); break;
 	case 'E': USE_BITS (OP_MASK_CSR, OP_SH_CSR); break;
 	case 'P': USE_BITS (OP_MASK_PRED, OP_SH_PRED); break;
@@ -3505,7 +3506,17 @@ riscv_ip (char *str, struct riscv_cl_ins
 		}
 	      continue;
 
-	    case 'm': /* Rounding mode.  */
+	    case 'm': /* Optional rounding mode.  */
+	      if (*asarg == '\0')
+		{
+		  INSERT_OPERAND (RM, *ip, OP_MASK_RM);
+		  continue;
+		}
+	      if (*asarg != ',')
+		break;
+	      ++asarg;
+	      /* Fall through. */
+	    case 'M': /* Rounding mode.  */
 	      if (arg_lookup (&asarg, riscv_rm,
 			      ARRAY_SIZE (riscv_rm), &regno))
 		{
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -536,6 +536,11 @@ print_insn_args (const char *oparg, insn
 	  break;
 
 	case 'm':
+	  if (EXTRACT_OPERAND (RM, l) == OP_MASK_RM)
+	    break;
+	  print (info->stream, dis_style_text, ",");
+	  /* Fall through. */
+	case 'M':
 	  arg_print (info, EXTRACT_OPERAND (RM, l),
 		     riscv_rm, ARRAY_SIZE (riscv_rm));
 	  break;
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -915,61 +915,40 @@ const struct riscv_opcode riscv_opcodes[
 {"fsgnj.h",    0, INSN_CLASS_ZFH_INX,   "D,S,T",     MATCH_FSGNJ_H, MASK_FSGNJ_H, match_opcode, 0 },
 {"fsgnjn.h",   0, INSN_CLASS_ZFH_INX,   "D,S,T",     MATCH_FSGNJN_H, MASK_FSGNJN_H, match_opcode, 0 },
 {"fsgnjx.h",   0, INSN_CLASS_ZFH_INX,   "D,S,T",     MATCH_FSGNJX_H, MASK_FSGNJX_H, match_opcode, 0 },
-{"fadd.h",     0, INSN_CLASS_ZFH_INX,   "D,S,T",     MATCH_FADD_H|MASK_RM, MASK_FADD_H|MASK_RM, match_opcode, 0 },
-{"fadd.h",     0, INSN_CLASS_ZFH_INX,   "D,S,T,m",   MATCH_FADD_H, MASK_FADD_H, match_opcode, 0 },
-{"fsub.h",     0, INSN_CLASS_ZFH_INX,   "D,S,T",     MATCH_FSUB_H|MASK_RM, MASK_FSUB_H|MASK_RM, match_opcode, 0 },
-{"fsub.h",     0, INSN_CLASS_ZFH_INX,   "D,S,T,m",   MATCH_FSUB_H, MASK_FSUB_H, match_opcode, 0 },
-{"fmul.h",     0, INSN_CLASS_ZFH_INX,   "D,S,T",     MATCH_FMUL_H|MASK_RM, MASK_FMUL_H|MASK_RM, match_opcode, 0 },
-{"fmul.h",     0, INSN_CLASS_ZFH_INX,   "D,S,T,m",   MATCH_FMUL_H, MASK_FMUL_H, match_opcode, 0 },
-{"fdiv.h",     0, INSN_CLASS_ZFH_INX,   "D,S,T",     MATCH_FDIV_H|MASK_RM, MASK_FDIV_H|MASK_RM, match_opcode, 0 },
-{"fdiv.h",     0, INSN_CLASS_ZFH_INX,   "D,S,T,m",   MATCH_FDIV_H, MASK_FDIV_H, match_opcode, 0 },
-{"fsqrt.h",    0, INSN_CLASS_ZFH_INX,   "D,S",       MATCH_FSQRT_H|MASK_RM, MASK_FSQRT_H|MASK_RM, match_opcode, 0 },
-{"fsqrt.h",    0, INSN_CLASS_ZFH_INX,   "D,S,m",     MATCH_FSQRT_H, MASK_FSQRT_H, match_opcode, 0 },
+{"fadd.h",     0, INSN_CLASS_ZFH_INX,  "D,S,Tm",    MATCH_FADD_H, MASK_FADD_H, match_opcode, 0 },
+{"fsub.h",     0, INSN_CLASS_ZFH_INX,  "D,S,Tm",    MATCH_FSUB_H, MASK_FSUB_H, match_opcode, 0 },
+{"fmul.h",     0, INSN_CLASS_ZFH_INX,  "D,S,Tm",    MATCH_FMUL_H, MASK_FMUL_H, match_opcode, 0 },
+{"fdiv.h",     0, INSN_CLASS_ZFH_INX,  "D,S,Tm",    MATCH_FDIV_H, MASK_FDIV_H, match_opcode, 0 },
+{"fsqrt.h",    0, INSN_CLASS_ZFH_INX,  "D,Sm",      MATCH_FSQRT_H, MASK_FSQRT_H, match_opcode, 0 },
 {"fmin.h",     0, INSN_CLASS_ZFH_INX,   "D,S,T",     MATCH_FMIN_H, MASK_FMIN_H, match_opcode, 0 },
 {"fmax.h",     0, INSN_CLASS_ZFH_INX,   "D,S,T",     MATCH_FMAX_H, MASK_FMAX_H, match_opcode, 0 },
-{"fmadd.h",    0, INSN_CLASS_ZFH_INX,   "D,S,T,R",   MATCH_FMADD_H|MASK_RM, MASK_FMADD_H|MASK_RM, match_opcode, 0 },
-{"fmadd.h",    0, INSN_CLASS_ZFH_INX,   "D,S,T,R,m", MATCH_FMADD_H, MASK_FMADD_H, match_opcode, 0 },
-{"fnmadd.h",   0, INSN_CLASS_ZFH_INX,   "D,S,T,R",   MATCH_FNMADD_H|MASK_RM, MASK_FNMADD_H|MASK_RM, match_opcode, 0 },
-{"fnmadd.h",   0, INSN_CLASS_ZFH_INX,   "D,S,T,R,m", MATCH_FNMADD_H, MASK_FNMADD_H, match_opcode, 0 },
-{"fmsub.h",    0, INSN_CLASS_ZFH_INX,   "D,S,T,R",   MATCH_FMSUB_H|MASK_RM, MASK_FMSUB_H|MASK_RM, match_opcode, 0 },
-{"fmsub.h",    0, INSN_CLASS_ZFH_INX,   "D,S,T,R,m", MATCH_FMSUB_H, MASK_FMSUB_H, match_opcode, 0 },
-{"fnmsub.h",   0, INSN_CLASS_ZFH_INX,   "D,S,T,R",   MATCH_FNMSUB_H|MASK_RM, MASK_FNMSUB_H|MASK_RM, match_opcode, 0 },
-{"fnmsub.h",   0, INSN_CLASS_ZFH_INX,   "D,S,T,R,m", MATCH_FNMSUB_H, MASK_FNMSUB_H, match_opcode, 0 },
-{"fcvt.w.h",   0, INSN_CLASS_ZFH_INX,   "d,S",       MATCH_FCVT_W_H|MASK_RM, MASK_FCVT_W_H|MASK_RM, match_opcode, 0 },
-{"fcvt.w.h",   0, INSN_CLASS_ZFH_INX,   "d,S,m",     MATCH_FCVT_W_H, MASK_FCVT_W_H, match_opcode, 0 },
-{"fcvt.wu.h",  0, INSN_CLASS_ZFH_INX,   "d,S",       MATCH_FCVT_WU_H|MASK_RM, MASK_FCVT_WU_H|MASK_RM, match_opcode, 0 },
-{"fcvt.wu.h",  0, INSN_CLASS_ZFH_INX,   "d,S,m",     MATCH_FCVT_WU_H, MASK_FCVT_WU_H, match_opcode, 0 },
-{"fcvt.h.w",   0, INSN_CLASS_ZFH_INX,   "D,s",       MATCH_FCVT_H_W|MASK_RM, MASK_FCVT_H_W|MASK_RM, match_opcode, 0 },
-{"fcvt.h.w",   0, INSN_CLASS_ZFH_INX,   "D,s,m",     MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 },
-{"fcvt.h.wu",  0, INSN_CLASS_ZFH_INX,   "D,s",       MATCH_FCVT_H_WU|MASK_RM, MASK_FCVT_H_WU|MASK_RM, match_opcode, 0 },
-{"fcvt.h.wu",  0, INSN_CLASS_ZFH_INX,   "D,s,m",     MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 },
+{"fmadd.h",    0, INSN_CLASS_ZFH_INX,  "D,S,T,Rm",  MATCH_FMADD_H, MASK_FMADD_H, match_opcode, 0 },
+{"fnmadd.h",   0, INSN_CLASS_ZFH_INX,  "D,S,T,Rm",  MATCH_FNMADD_H, MASK_FNMADD_H, match_opcode, 0 },
+{"fmsub.h",    0, INSN_CLASS_ZFH_INX,  "D,S,T,Rm",  MATCH_FMSUB_H, MASK_FMSUB_H, match_opcode, 0 },
+{"fnmsub.h",   0, INSN_CLASS_ZFH_INX,  "D,S,T,Rm",  MATCH_FNMSUB_H, MASK_FNMSUB_H, match_opcode, 0 },
+{"fcvt.w.h",   0, INSN_CLASS_ZFH_INX,  "d,Sm",      MATCH_FCVT_W_H, MASK_FCVT_W_H, match_opcode, 0 },
+{"fcvt.wu.h",  0, INSN_CLASS_ZFH_INX,  "d,Sm",      MATCH_FCVT_WU_H, MASK_FCVT_WU_H, match_opcode, 0 },
+{"fcvt.h.w",   0, INSN_CLASS_ZFH_INX,  "D,sm",      MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 },
+{"fcvt.h.wu",  0, INSN_CLASS_ZFH_INX,  "D,sm",      MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 },
 {"fcvt.s.h",   0, INSN_CLASS_ZFHMIN_INX, "D,S",     MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 },
 {"fcvt.d.h",   0, INSN_CLASS_ZFHMIN_AND_D_INX,     "D,S",       MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, 0 },
 {"fcvt.q.h",   0, INSN_CLASS_ZFHMIN_AND_Q_INX,     "D,S",       MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 },
-{"fcvt.h.s",   0, INSN_CLASS_ZFHMIN_INX, "D,S",     MATCH_FCVT_H_S|MASK_RM, MASK_FCVT_H_S|MASK_RM, match_opcode, 0 },
-{"fcvt.h.s",   0, INSN_CLASS_ZFHMIN_INX, "D,S,m",   MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 },
-{"fcvt.h.d",   0, INSN_CLASS_ZFHMIN_AND_D_INX,     "D,S",       MATCH_FCVT_H_D|MASK_RM, MASK_FCVT_H_D|MASK_RM, match_opcode, 0 },
-{"fcvt.h.d",   0, INSN_CLASS_ZFHMIN_AND_D_INX,     "D,S,m",     MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, 0 },
-{"fcvt.h.q",   0, INSN_CLASS_ZFHMIN_AND_Q_INX,     "D,S",       MATCH_FCVT_H_Q|MASK_RM, MASK_FCVT_H_Q|MASK_RM, match_opcode, 0 },
-{"fcvt.h.q",   0, INSN_CLASS_ZFHMIN_AND_Q_INX,     "D,S,m",     MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 },
+{"fcvt.h.s",   0, INSN_CLASS_ZFHMIN_INX, "D,Sm",    MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 },
+{"fcvt.h.d",   0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,Sm", MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, 0 },
+{"fcvt.h.q",   0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,Sm", MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 },
 {"fclass.h",   0, INSN_CLASS_ZFH_INX,   "d,S",       MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 },
 {"feq.h",      0, INSN_CLASS_ZFH_INX,   "d,S,T",     MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 },
 {"flt.h",      0, INSN_CLASS_ZFH_INX,   "d,S,T",     MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
 {"fle.h",      0, INSN_CLASS_ZFH_INX,   "d,S,T",     MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
 {"fgt.h",      0, INSN_CLASS_ZFH_INX,   "d,T,S",     MATCH_FLT_H, MASK_FLT_H, match_opcode, INSN_ALIAS },
 {"fge.h",      0, INSN_CLASS_ZFH_INX,   "d,T,S",     MATCH_FLE_H, MASK_FLE_H, match_opcode, INSN_ALIAS },
-{"fcvt.l.h",  64, INSN_CLASS_ZFH_INX,   "d,S",       MATCH_FCVT_L_H|MASK_RM, MASK_FCVT_L_H|MASK_RM, match_opcode, 0 },
-{"fcvt.l.h",  64, INSN_CLASS_ZFH_INX,   "d,S,m",     MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, 0 },
-{"fcvt.lu.h", 64, INSN_CLASS_ZFH_INX,   "d,S",       MATCH_FCVT_LU_H|MASK_RM, MASK_FCVT_LU_H|MASK_RM, match_opcode, 0 },
-{"fcvt.lu.h", 64, INSN_CLASS_ZFH_INX,   "d,S,m",     MATCH_FCVT_LU_H, MASK_FCVT_LU_H, match_opcode, 0 },
-{"fcvt.h.l",  64, INSN_CLASS_ZFH_INX,   "D,s",       MATCH_FCVT_H_L|MASK_RM, MASK_FCVT_H_L|MASK_RM, match_opcode, 0 },
-{"fcvt.h.l",  64, INSN_CLASS_ZFH_INX,   "D,s,m",     MATCH_FCVT_H_L, MASK_FCVT_H_L, match_opcode, 0 },
-{"fcvt.h.lu", 64, INSN_CLASS_ZFH_INX,   "D,s",       MATCH_FCVT_H_LU|MASK_RM, MASK_FCVT_H_LU|MASK_RM, match_opcode, 0 },
-{"fcvt.h.lu", 64, INSN_CLASS_ZFH_INX,   "D,s,m",     MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 },
+{"fcvt.l.h",  64, INSN_CLASS_ZFH_INX,  "d,Sm",      MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, 0 },
+{"fcvt.lu.h", 64, INSN_CLASS_ZFH_INX,  "d,Sm",      MATCH_FCVT_LU_H, MASK_FCVT_LU_H, match_opcode, 0 },
+{"fcvt.h.l",  64, INSN_CLASS_ZFH_INX,  "D,sm",      MATCH_FCVT_H_L, MASK_FCVT_H_L, match_opcode, 0 },
+{"fcvt.h.lu", 64, INSN_CLASS_ZFH_INX,  "D,sm",      MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 },
 
 /* Zfbfmin instructions.  */
-{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S",   MATCH_FCVT_BF16_S|MASK_RM, MASK_FCVT_BF16_S|MASK_RM, match_opcode, 0 },
-{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,S,m", MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S, match_opcode, 0 },
+{"fcvt.bf16.s", 0, INSN_CLASS_ZFBFMIN, "D,Sm",  MATCH_FCVT_BF16_S, MASK_FCVT_BF16_S, match_opcode, 0 },
 {"fcvt.s.bf16", 0, INSN_CLASS_ZFBFMIN, "D,S",   MATCH_FCVT_S_BF16, MASK_FCVT_S_BF16|MASK_RM, match_opcode, 0 },
 
 /* Single-precision floating-point instruction subset.  */
@@ -1007,48 +986,31 @@ const struct riscv_opcode riscv_opcodes[
 {"fsgnj.s",    0, INSN_CLASS_F_INX,   "D,S,T",     MATCH_FSGNJ_S, MASK_FSGNJ_S, match_opcode, 0 },
 {"fsgnjn.s",   0, INSN_CLASS_F_INX,   "D,S,T",     MATCH_FSGNJN_S, MASK_FSGNJN_S, match_opcode, 0 },
 {"fsgnjx.s",   0, INSN_CLASS_F_INX,   "D,S,T",     MATCH_FSGNJX_S, MASK_FSGNJX_S, match_opcode, 0 },
-{"fadd.s",     0, INSN_CLASS_F_INX,   "D,S,T",     MATCH_FADD_S|MASK_RM, MASK_FADD_S|MASK_RM, match_opcode, 0 },
-{"fadd.s",     0, INSN_CLASS_F_INX,   "D,S,T,m",   MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 },
-{"fsub.s",     0, INSN_CLASS_F_INX,   "D,S,T",     MATCH_FSUB_S|MASK_RM, MASK_FSUB_S|MASK_RM, match_opcode, 0 },
-{"fsub.s",     0, INSN_CLASS_F_INX,   "D,S,T,m",   MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 },
-{"fmul.s",     0, INSN_CLASS_F_INX,   "D,S,T",     MATCH_FMUL_S|MASK_RM, MASK_FMUL_S|MASK_RM, match_opcode, 0 },
-{"fmul.s",     0, INSN_CLASS_F_INX,   "D,S,T,m",   MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 },
-{"fdiv.s",     0, INSN_CLASS_F_INX,   "D,S,T",     MATCH_FDIV_S|MASK_RM, MASK_FDIV_S|MASK_RM, match_opcode, 0 },
-{"fdiv.s",     0, INSN_CLASS_F_INX,   "D,S,T,m",   MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 },
-{"fsqrt.s",    0, INSN_CLASS_F_INX,   "D,S",       MATCH_FSQRT_S|MASK_RM, MASK_FSQRT_S|MASK_RM, match_opcode, 0 },
-{"fsqrt.s",    0, INSN_CLASS_F_INX,   "D,S,m",     MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 },
+{"fadd.s",     0, INSN_CLASS_F_INX,   "D,S,Tm",    MATCH_FADD_S, MASK_FADD_S, match_opcode, 0 },
+{"fsub.s",     0, INSN_CLASS_F_INX,   "D,S,Tm",    MATCH_FSUB_S, MASK_FSUB_S, match_opcode, 0 },
+{"fmul.s",     0, INSN_CLASS_F_INX,   "D,S,Tm",    MATCH_FMUL_S, MASK_FMUL_S, match_opcode, 0 },
+{"fdiv.s",     0, INSN_CLASS_F_INX,   "D,S,Tm",    MATCH_FDIV_S, MASK_FDIV_S, match_opcode, 0 },
+{"fsqrt.s",    0, INSN_CLASS_F_INX,   "D,Sm",      MATCH_FSQRT_S, MASK_FSQRT_S, match_opcode, 0 },
 {"fmin.s",     0, INSN_CLASS_F_INX,   "D,S,T",     MATCH_FMIN_S, MASK_FMIN_S, match_opcode, 0 },
 {"fmax.s",     0, INSN_CLASS_F_INX,   "D,S,T",     MATCH_FMAX_S, MASK_FMAX_S, match_opcode, 0 },
-{"fmadd.s",    0, INSN_CLASS_F_INX,   "D,S,T,R",   MATCH_FMADD_S|MASK_RM, MASK_FMADD_S|MASK_RM, match_opcode, 0 },
-{"fmadd.s",    0, INSN_CLASS_F_INX,   "D,S,T,R,m", MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 },
-{"fnmadd.s",   0, INSN_CLASS_F_INX,   "D,S,T,R",   MATCH_FNMADD_S|MASK_RM, MASK_FNMADD_S|MASK_RM, match_opcode, 0 },
-{"fnmadd.s",   0, INSN_CLASS_F_INX,   "D,S,T,R,m", MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 },
-{"fmsub.s",    0, INSN_CLASS_F_INX,   "D,S,T,R",   MATCH_FMSUB_S|MASK_RM, MASK_FMSUB_S|MASK_RM, match_opcode, 0 },
-{"fmsub.s",    0, INSN_CLASS_F_INX,   "D,S,T,R,m", MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 },
-{"fnmsub.s",   0, INSN_CLASS_F_INX,   "D,S,T,R",   MATCH_FNMSUB_S|MASK_RM, MASK_FNMSUB_S|MASK_RM, match_opcode, 0 },
-{"fnmsub.s",   0, INSN_CLASS_F_INX,   "D,S,T,R,m", MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 },
-{"fcvt.w.s",   0, INSN_CLASS_F_INX,   "d,S",       MATCH_FCVT_W_S|MASK_RM, MASK_FCVT_W_S|MASK_RM, match_opcode, 0 },
-{"fcvt.w.s",   0, INSN_CLASS_F_INX,   "d,S,m",     MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 },
-{"fcvt.wu.s",  0, INSN_CLASS_F_INX,   "d,S",       MATCH_FCVT_WU_S|MASK_RM, MASK_FCVT_WU_S|MASK_RM, match_opcode, 0 },
-{"fcvt.wu.s",  0, INSN_CLASS_F_INX,   "d,S,m",     MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 },
-{"fcvt.s.w",   0, INSN_CLASS_F_INX,   "D,s",       MATCH_FCVT_S_W|MASK_RM, MASK_FCVT_S_W|MASK_RM, match_opcode, 0 },
-{"fcvt.s.w",   0, INSN_CLASS_F_INX,   "D,s,m",     MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 },
-{"fcvt.s.wu",  0, INSN_CLASS_F_INX,   "D,s",       MATCH_FCVT_S_WU|MASK_RM, MASK_FCVT_S_WU|MASK_RM, match_opcode, 0 },
-{"fcvt.s.wu",  0, INSN_CLASS_F_INX,   "D,s,m",     MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 },
+{"fmadd.s",    0, INSN_CLASS_F_INX,   "D,S,T,Rm",  MATCH_FMADD_S, MASK_FMADD_S, match_opcode, 0 },
+{"fnmadd.s",   0, INSN_CLASS_F_INX,   "D,S,T,Rm",  MATCH_FNMADD_S, MASK_FNMADD_S, match_opcode, 0 },
+{"fmsub.s",    0, INSN_CLASS_F_INX,   "D,S,T,Rm",  MATCH_FMSUB_S, MASK_FMSUB_S, match_opcode, 0 },
+{"fnmsub.s",   0, INSN_CLASS_F_INX,   "D,S,T,Rm",  MATCH_FNMSUB_S, MASK_FNMSUB_S, match_opcode, 0 },
+{"fcvt.w.s",   0, INSN_CLASS_F_INX,   "d,Sm",      MATCH_FCVT_W_S, MASK_FCVT_W_S, match_opcode, 0 },
+{"fcvt.wu.s",  0, INSN_CLASS_F_INX,   "d,Sm",      MATCH_FCVT_WU_S, MASK_FCVT_WU_S, match_opcode, 0 },
+{"fcvt.s.w",   0, INSN_CLASS_F_INX,   "D,sm",      MATCH_FCVT_S_W, MASK_FCVT_S_W, match_opcode, 0 },
+{"fcvt.s.wu",  0, INSN_CLASS_F_INX,   "D,sm",      MATCH_FCVT_S_WU, MASK_FCVT_S_WU, match_opcode, 0 },
 {"fclass.s",   0, INSN_CLASS_F_INX,   "d,S",       MATCH_FCLASS_S, MASK_FCLASS_S, match_opcode, 0 },
 {"feq.s",      0, INSN_CLASS_F_INX,   "d,S,T",     MATCH_FEQ_S, MASK_FEQ_S, match_opcode, 0 },
 {"flt.s",      0, INSN_CLASS_F_INX,   "d,S,T",     MATCH_FLT_S, MASK_FLT_S, match_opcode, 0 },
 {"fle.s",      0, INSN_CLASS_F_INX,   "d,S,T",     MATCH_FLE_S, MASK_FLE_S, match_opcode, 0 },
 {"fgt.s",      0, INSN_CLASS_F_INX,   "d,T,S",     MATCH_FLT_S, MASK_FLT_S, match_opcode, INSN_ALIAS },
 {"fge.s",      0, INSN_CLASS_F_INX,   "d,T,S",     MATCH_FLE_S, MASK_FLE_S, match_opcode, INSN_ALIAS },
-{"fcvt.l.s",  64, INSN_CLASS_F_INX,   "d,S",       MATCH_FCVT_L_S|MASK_RM, MASK_FCVT_L_S|MASK_RM, match_opcode, 0 },
-{"fcvt.l.s",  64, INSN_CLASS_F_INX,   "d,S,m",     MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 },
-{"fcvt.lu.s", 64, INSN_CLASS_F_INX,   "d,S",       MATCH_FCVT_LU_S|MASK_RM, MASK_FCVT_LU_S|MASK_RM, match_opcode, 0 },
-{"fcvt.lu.s", 64, INSN_CLASS_F_INX,   "d,S,m",     MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 },
-{"fcvt.s.l",  64, INSN_CLASS_F_INX,   "D,s",       MATCH_FCVT_S_L|MASK_RM, MASK_FCVT_S_L|MASK_RM, match_opcode, 0 },
-{"fcvt.s.l",  64, INSN_CLASS_F_INX,   "D,s,m",     MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 },
-{"fcvt.s.lu", 64, INSN_CLASS_F_INX,   "D,s",       MATCH_FCVT_S_LU|MASK_RM, MASK_FCVT_S_LU|MASK_RM, match_opcode, 0 },
-{"fcvt.s.lu", 64, INSN_CLASS_F_INX,   "D,s,m",     MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 },
+{"fcvt.l.s",  64, INSN_CLASS_F_INX,   "d,Sm",      MATCH_FCVT_L_S, MASK_FCVT_L_S, match_opcode, 0 },
+{"fcvt.lu.s", 64, INSN_CLASS_F_INX,   "d,Sm",      MATCH_FCVT_LU_S, MASK_FCVT_LU_S, match_opcode, 0 },
+{"fcvt.s.l",  64, INSN_CLASS_F_INX,   "D,sm",      MATCH_FCVT_S_L, MASK_FCVT_S_L, match_opcode, 0 },
+{"fcvt.s.lu", 64, INSN_CLASS_F_INX,   "D,sm",      MATCH_FCVT_S_LU, MASK_FCVT_S_LU, match_opcode, 0 },
 
 /* Double-precision floating-point instruction subset.  */
 {"fld",        0, INSN_CLASS_ZCD, "D,Cn(Cc)",  MATCH_C_FLDSP, MASK_C_FLDSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
@@ -1065,35 +1027,23 @@ const struct riscv_opcode riscv_opcodes[
 {"fsgnj.d",    0, INSN_CLASS_D_INX,   "D,S,T",     MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 },
 {"fsgnjn.d",   0, INSN_CLASS_D_INX,   "D,S,T",     MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 },
 {"fsgnjx.d",   0, INSN_CLASS_D_INX,   "D,S,T",     MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 },
-{"fadd.d",     0, INSN_CLASS_D_INX,   "D,S,T",     MATCH_FADD_D|MASK_RM, MASK_FADD_D|MASK_RM, match_opcode, 0 },
-{"fadd.d",     0, INSN_CLASS_D_INX,   "D,S,T,m",   MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 },
-{"fsub.d",     0, INSN_CLASS_D_INX,   "D,S,T",     MATCH_FSUB_D|MASK_RM, MASK_FSUB_D|MASK_RM, match_opcode, 0 },
-{"fsub.d",     0, INSN_CLASS_D_INX,   "D,S,T,m",   MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 },
-{"fmul.d",     0, INSN_CLASS_D_INX,   "D,S,T",     MATCH_FMUL_D|MASK_RM, MASK_FMUL_D|MASK_RM, match_opcode, 0 },
-{"fmul.d",     0, INSN_CLASS_D_INX,   "D,S,T,m",   MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 },
-{"fdiv.d",     0, INSN_CLASS_D_INX,   "D,S,T",     MATCH_FDIV_D|MASK_RM, MASK_FDIV_D|MASK_RM, match_opcode, 0 },
-{"fdiv.d",     0, INSN_CLASS_D_INX,   "D,S,T,m",   MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 },
-{"fsqrt.d",    0, INSN_CLASS_D_INX,   "D,S",       MATCH_FSQRT_D|MASK_RM, MASK_FSQRT_D|MASK_RM, match_opcode, 0 },
-{"fsqrt.d",    0, INSN_CLASS_D_INX,   "D,S,m",     MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 },
+{"fadd.d",     0, INSN_CLASS_D_INX,   "D,S,Tm",    MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 },
+{"fsub.d",     0, INSN_CLASS_D_INX,   "D,S,Tm",    MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 },
+{"fmul.d",     0, INSN_CLASS_D_INX,   "D,S,Tm",    MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 },
+{"fdiv.d",     0, INSN_CLASS_D_INX,   "D,S,Tm",    MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 },
+{"fsqrt.d",    0, INSN_CLASS_D_INX,   "D,Sm",      MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 },
 {"fmin.d",     0, INSN_CLASS_D_INX,   "D,S,T",     MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 },
 {"fmax.d",     0, INSN_CLASS_D_INX,   "D,S,T",     MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 },
-{"fmadd.d",    0, INSN_CLASS_D_INX,   "D,S,T,R",   MATCH_FMADD_D|MASK_RM, MASK_FMADD_D|MASK_RM, match_opcode, 0 },
-{"fmadd.d",    0, INSN_CLASS_D_INX,   "D,S,T,R,m", MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 },
-{"fnmadd.d",   0, INSN_CLASS_D_INX,   "D,S,T,R",   MATCH_FNMADD_D|MASK_RM, MASK_FNMADD_D|MASK_RM, match_opcode, 0 },
-{"fnmadd.d",   0, INSN_CLASS_D_INX,   "D,S,T,R,m", MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 },
-{"fmsub.d",    0, INSN_CLASS_D_INX,   "D,S,T,R",   MATCH_FMSUB_D|MASK_RM, MASK_FMSUB_D|MASK_RM, match_opcode, 0 },
-{"fmsub.d",    0, INSN_CLASS_D_INX,   "D,S,T,R,m", MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 },
-{"fnmsub.d",   0, INSN_CLASS_D_INX,   "D,S,T,R",   MATCH_FNMSUB_D|MASK_RM, MASK_FNMSUB_D|MASK_RM, match_opcode, 0 },
-{"fnmsub.d",   0, INSN_CLASS_D_INX,   "D,S,T,R,m", MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 },
-{"fcvt.w.d",   0, INSN_CLASS_D_INX,   "d,S",       MATCH_FCVT_W_D|MASK_RM, MASK_FCVT_W_D|MASK_RM, match_opcode, 0 },
-{"fcvt.w.d",   0, INSN_CLASS_D_INX,   "d,S,m",     MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 },
-{"fcvt.wu.d",  0, INSN_CLASS_D_INX,   "d,S",       MATCH_FCVT_WU_D|MASK_RM, MASK_FCVT_WU_D|MASK_RM, match_opcode, 0 },
-{"fcvt.wu.d",  0, INSN_CLASS_D_INX,   "d,S,m",     MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 },
+{"fmadd.d",    0, INSN_CLASS_D_INX,   "D,S,T,Rm",  MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 },
+{"fnmadd.d",   0, INSN_CLASS_D_INX,   "D,S,T,Rm",  MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 },
+{"fmsub.d",    0, INSN_CLASS_D_INX,   "D,S,T,Rm",  MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 },
+{"fnmsub.d",   0, INSN_CLASS_D_INX,   "D,S,T,Rm",  MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 },
+{"fcvt.w.d",   0, INSN_CLASS_D_INX,   "d,Sm",      MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 },
+{"fcvt.wu.d",  0, INSN_CLASS_D_INX,   "d,Sm",      MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 },
 {"fcvt.d.w",   0, INSN_CLASS_D_INX,   "D,s",       MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 },
 {"fcvt.d.wu",  0, INSN_CLASS_D_INX,   "D,s",       MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 },
 {"fcvt.d.s",   0, INSN_CLASS_D_INX,   "D,S",       MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 },
-{"fcvt.s.d",   0, INSN_CLASS_D_INX,   "D,S",       MATCH_FCVT_S_D|MASK_RM, MASK_FCVT_S_D|MASK_RM, match_opcode, 0 },
-{"fcvt.s.d",   0, INSN_CLASS_D_INX,   "D,S,m",     MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 },
+{"fcvt.s.d",   0, INSN_CLASS_D_INX,   "D,Sm",      MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 },
 {"fclass.d",   0, INSN_CLASS_D_INX,   "d,S",       MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 },
 {"feq.d",      0, INSN_CLASS_D_INX,   "d,S,T",     MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 },
 {"flt.d",      0, INSN_CLASS_D_INX,   "d,S,T",     MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
@@ -1102,14 +1052,10 @@ const struct riscv_opcode riscv_opcodes[
 {"fge.d",      0, INSN_CLASS_D_INX,   "d,T,S",     MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_ALIAS },
 {"fmv.x.d",   64, INSN_CLASS_D,   "d,S",       MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 },
 {"fmv.d.x",   64, INSN_CLASS_D,   "D,s",       MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 },
-{"fcvt.l.d",  64, INSN_CLASS_D_INX,   "d,S",       MATCH_FCVT_L_D|MASK_RM, MASK_FCVT_L_D|MASK_RM, match_opcode, 0 },
-{"fcvt.l.d",  64, INSN_CLASS_D_INX,   "d,S,m",     MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 },
-{"fcvt.lu.d", 64, INSN_CLASS_D_INX,   "d,S",       MATCH_FCVT_LU_D|MASK_RM, MASK_FCVT_LU_D|MASK_RM, match_opcode, 0 },
-{"fcvt.lu.d", 64, INSN_CLASS_D_INX,   "d,S,m",     MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 },
-{"fcvt.d.l",  64, INSN_CLASS_D_INX,   "D,s",       MATCH_FCVT_D_L|MASK_RM, MASK_FCVT_D_L|MASK_RM, match_opcode, 0 },
-{"fcvt.d.l",  64, INSN_CLASS_D_INX,   "D,s,m",     MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 },
-{"fcvt.d.lu", 64, INSN_CLASS_D_INX,   "D,s",       MATCH_FCVT_D_LU|MASK_RM, MASK_FCVT_D_LU|MASK_RM, match_opcode, 0 },
-{"fcvt.d.lu", 64, INSN_CLASS_D_INX,   "D,s,m",     MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 },
+{"fcvt.l.d",  64, INSN_CLASS_D_INX,   "d,Sm",      MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 },
+{"fcvt.lu.d", 64, INSN_CLASS_D_INX,   "d,Sm",      MATCH_FCVT_LU_D, MASK_FCVT_LU_D, match_opcode, 0 },
+{"fcvt.d.l",  64, INSN_CLASS_D_INX,   "D,sm",      MATCH_FCVT_D_L, MASK_FCVT_D_L, match_opcode, 0 },
+{"fcvt.d.lu", 64, INSN_CLASS_D_INX,   "D,sm",      MATCH_FCVT_D_LU, MASK_FCVT_D_LU, match_opcode, 0 },
 
 /* Quad-precision floating-point instruction subset.  */
 {"flq",        0, INSN_CLASS_Q,   "D,o(s)",    MATCH_FLQ, MASK_FLQ, match_opcode, INSN_DREF|INSN_16_BYTE },
@@ -1122,48 +1068,33 @@ const struct riscv_opcode riscv_opcodes[
 {"fsgnj.q",    0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 },
 {"fsgnjn.q",   0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 },
 {"fsgnjx.q",   0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 },
-{"fadd.q",     0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FADD_Q|MASK_RM, MASK_FADD_Q|MASK_RM, match_opcode, 0 },
-{"fadd.q",     0, INSN_CLASS_Q_INX,   "D,S,T,m",   MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 },
-{"fsub.q",     0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FSUB_Q|MASK_RM, MASK_FSUB_Q|MASK_RM, match_opcode, 0 },
-{"fsub.q",     0, INSN_CLASS_Q_INX,   "D,S,T,m",   MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 },
-{"fmul.q",     0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FMUL_Q|MASK_RM, MASK_FMUL_Q|MASK_RM, match_opcode, 0 },
-{"fmul.q",     0, INSN_CLASS_Q_INX,   "D,S,T,m",   MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 },
-{"fdiv.q",     0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FDIV_Q|MASK_RM, MASK_FDIV_Q|MASK_RM, match_opcode, 0 },
-{"fdiv.q",     0, INSN_CLASS_Q_INX,   "D,S,T,m",   MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 },
-{"fsqrt.q",    0, INSN_CLASS_Q_INX,   "D,S",       MATCH_FSQRT_Q|MASK_RM, MASK_FSQRT_Q|MASK_RM, match_opcode, 0 },
-{"fsqrt.q",    0, INSN_CLASS_Q_INX,   "D,S,m",     MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 },
+{"fadd.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 },
+{"fsub.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 },
+{"fmul.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 },
+{"fdiv.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 },
+{"fsqrt.q",    0, INSN_CLASS_Q_INX,   "D,Sm",      MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 },
 {"fmin.q",     0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 },
 {"fmax.q",     0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 },
-{"fmadd.q",    0, INSN_CLASS_Q_INX,   "D,S,T,R",   MATCH_FMADD_Q|MASK_RM, MASK_FMADD_Q|MASK_RM, match_opcode, 0 },
-{"fmadd.q",    0, INSN_CLASS_Q_INX,   "D,S,T,R,m", MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 },
-{"fnmadd.q",   0, INSN_CLASS_Q_INX,   "D,S,T,R",   MATCH_FNMADD_Q|MASK_RM, MASK_FNMADD_Q|MASK_RM, match_opcode, 0 },
-{"fnmadd.q",   0, INSN_CLASS_Q_INX,   "D,S,T,R,m", MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 },
-{"fmsub.q",    0, INSN_CLASS_Q_INX,   "D,S,T,R",   MATCH_FMSUB_Q|MASK_RM, MASK_FMSUB_Q|MASK_RM, match_opcode, 0 },
-{"fmsub.q",    0, INSN_CLASS_Q_INX,   "D,S,T,R,m", MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 },
-{"fnmsub.q",   0, INSN_CLASS_Q_INX,   "D,S,T,R",   MATCH_FNMSUB_Q|MASK_RM, MASK_FNMSUB_Q|MASK_RM, match_opcode, 0 },
-{"fnmsub.q",   0, INSN_CLASS_Q_INX,   "D,S,T,R,m", MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 },
-{"fcvt.w.q",   0, INSN_CLASS_Q_INX,   "d,S",       MATCH_FCVT_W_Q|MASK_RM, MASK_FCVT_W_Q|MASK_RM, match_opcode, 0 },
-{"fcvt.w.q",   0, INSN_CLASS_Q_INX,   "d,S,m",     MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 },
-{"fcvt.wu.q",  0, INSN_CLASS_Q_INX,   "d,S",       MATCH_FCVT_WU_Q|MASK_RM, MASK_FCVT_WU_Q|MASK_RM, match_opcode, 0 },
-{"fcvt.wu.q",  0, INSN_CLASS_Q_INX,   "d,S,m",     MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 },
+{"fmadd.q",    0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 },
+{"fnmadd.q",   0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 },
+{"fmsub.q",    0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 },
+{"fnmsub.q",   0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 },
+{"fcvt.w.q",   0, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 },
+{"fcvt.wu.q",  0, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 },
 {"fcvt.q.w",   0, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 },
 {"fcvt.q.wu",  0, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 },
 {"fcvt.q.s",   0, INSN_CLASS_Q_INX,   "D,S",       MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 },
 {"fcvt.q.d",   0, INSN_CLASS_Q_INX,   "D,S",       MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 },
-{"fcvt.s.q",   0, INSN_CLASS_Q_INX,   "D,S",       MATCH_FCVT_S_Q|MASK_RM, MASK_FCVT_S_Q|MASK_RM, match_opcode, 0 },
-{"fcvt.s.q",   0, INSN_CLASS_Q_INX,   "D,S,m",     MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 },
-{"fcvt.d.q",   0, INSN_CLASS_Q_INX,   "D,S",       MATCH_FCVT_D_Q|MASK_RM, MASK_FCVT_D_Q|MASK_RM, match_opcode, 0 },
-{"fcvt.d.q",   0, INSN_CLASS_Q_INX,   "D,S,m",     MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 },
+{"fcvt.s.q",   0, INSN_CLASS_Q_INX,   "D,Sm",      MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 },
+{"fcvt.d.q",   0, INSN_CLASS_Q_INX,   "D,Sm",      MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 },
 {"fclass.q",   0, INSN_CLASS_Q_INX,   "d,S",       MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 },
 {"feq.q",      0, INSN_CLASS_Q_INX,   "d,S,T",     MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 },
 {"flt.q",      0, INSN_CLASS_Q_INX,   "d,S,T",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
 {"fle.q",      0, INSN_CLASS_Q_INX,   "d,S,T",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
 {"fgt.q",      0, INSN_CLASS_Q_INX,   "d,T,S",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_ALIAS },
 {"fge.q",      0, INSN_CLASS_Q_INX,   "d,T,S",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_ALIAS },
-{"fcvt.l.q",  64, INSN_CLASS_Q_INX,   "d,S",       MATCH_FCVT_L_Q|MASK_RM, MASK_FCVT_L_Q|MASK_RM, match_opcode, 0 },
-{"fcvt.l.q",  64, INSN_CLASS_Q_INX,   "d,S,m",     MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 },
-{"fcvt.lu.q", 64, INSN_CLASS_Q_INX,   "d,S",       MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 },
-{"fcvt.lu.q", 64, INSN_CLASS_Q_INX,   "d,S,m",     MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 },
+{"fcvt.l.q",  64, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 },
+{"fcvt.lu.q", 64, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 },
 {"fcvt.q.l",  64, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
 {"fcvt.q.lu", 64, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 },
 
@@ -1306,23 +1237,15 @@ const struct riscv_opcode riscv_opcodes[
 {"fmaxm.q",     0, INSN_CLASS_Q_AND_ZFA,   "D,S,T", MATCH_FMAXM_Q, MASK_FMAXM_Q, match_opcode, 0 },
 {"fminm.h",     0, INSN_CLASS_ZFH_AND_ZFA, "D,S,T", MATCH_FMINM_H, MASK_FMINM_H, match_opcode, 0 },
 {"fmaxm.h",     0, INSN_CLASS_ZFH_AND_ZFA, "D,S,T", MATCH_FMAXM_H, MASK_FMAXM_H, match_opcode, 0 },
-{"fround.s",    0, INSN_CLASS_ZFA,         "D,S",   MATCH_FROUND_S|MASK_RM, MASK_FROUND_S|MASK_RM, match_opcode, 0 },
-{"fround.s",    0, INSN_CLASS_ZFA,         "D,S,m", MATCH_FROUND_S, MASK_FROUND_S, match_opcode, 0 },
-{"froundnx.s",  0, INSN_CLASS_ZFA,         "D,S",   MATCH_FROUNDNX_S|MASK_RM, MASK_FROUNDNX_S|MASK_RM, match_opcode, 0 },
-{"froundnx.s",  0, INSN_CLASS_ZFA,         "D,S,m", MATCH_FROUNDNX_S, MASK_FROUNDNX_S, match_opcode, 0 },
-{"fround.d",    0, INSN_CLASS_D_AND_ZFA,   "D,S",   MATCH_FROUND_D|MASK_RM, MASK_FROUND_D|MASK_RM, match_opcode, 0 },
-{"fround.d",    0, INSN_CLASS_D_AND_ZFA,   "D,S,m", MATCH_FROUND_D, MASK_FROUND_D, match_opcode, 0 },
-{"froundnx.d",  0, INSN_CLASS_D_AND_ZFA,   "D,S",   MATCH_FROUNDNX_D|MASK_RM, MASK_FROUNDNX_D|MASK_RM, match_opcode, 0 },
-{"froundnx.d",  0, INSN_CLASS_D_AND_ZFA,   "D,S,m", MATCH_FROUNDNX_D, MASK_FROUNDNX_D, match_opcode, 0 },
-{"fround.q",    0, INSN_CLASS_Q_AND_ZFA,   "D,S",   MATCH_FROUND_Q|MASK_RM, MASK_FROUND_Q|MASK_RM, match_opcode, 0 },
-{"fround.q",    0, INSN_CLASS_Q_AND_ZFA,   "D,S,m", MATCH_FROUND_Q, MASK_FROUND_Q, match_opcode, 0 },
-{"froundnx.q",  0, INSN_CLASS_Q_AND_ZFA,   "D,S",   MATCH_FROUNDNX_Q|MASK_RM, MASK_FROUNDNX_Q|MASK_RM, match_opcode, 0 },
-{"froundnx.q",  0, INSN_CLASS_Q_AND_ZFA,   "D,S,m", MATCH_FROUNDNX_Q, MASK_FROUNDNX_Q, match_opcode, 0 },
-{"fround.h",    0, INSN_CLASS_ZFH_AND_ZFA, "D,S",   MATCH_FROUND_H|MASK_RM, MASK_FROUND_H|MASK_RM, match_opcode, 0 },
-{"fround.h",    0, INSN_CLASS_ZFH_AND_ZFA, "D,S,m", MATCH_FROUND_H, MASK_FROUND_H, match_opcode, 0 },
-{"froundnx.h",  0, INSN_CLASS_ZFH_AND_ZFA, "D,S",   MATCH_FROUNDNX_H|MASK_RM, MASK_FROUNDNX_H|MASK_RM, match_opcode, 0 },
-{"froundnx.h",  0, INSN_CLASS_ZFH_AND_ZFA, "D,S,m", MATCH_FROUNDNX_H, MASK_FROUNDNX_H, match_opcode, 0 },
-{"fcvtmod.w.d", 0, INSN_CLASS_D_AND_ZFA,   "d,S,m", MATCH_FCVTMOD_W_D, MASK_FCVTMOD_W_D, match_opcode, 0 },
+{"fround.s",    0, INSN_CLASS_ZFA,         "D,Sm",  MATCH_FROUND_S, MASK_FROUND_S, match_opcode, 0 },
+{"froundnx.s",  0, INSN_CLASS_ZFA,         "D,Sm",  MATCH_FROUNDNX_S, MASK_FROUNDNX_S, match_opcode, 0 },
+{"fround.d",    0, INSN_CLASS_D_AND_ZFA,   "D,Sm",  MATCH_FROUND_D, MASK_FROUND_D, match_opcode, 0 },
+{"froundnx.d",  0, INSN_CLASS_D_AND_ZFA,   "D,Sm",  MATCH_FROUNDNX_D, MASK_FROUNDNX_D, match_opcode, 0 },
+{"fround.q",    0, INSN_CLASS_Q_AND_ZFA,   "D,Sm",  MATCH_FROUND_Q, MASK_FROUND_Q, match_opcode, 0 },
+{"froundnx.q",  0, INSN_CLASS_Q_AND_ZFA,   "D,Sm",  MATCH_FROUNDNX_Q, MASK_FROUNDNX_Q, match_opcode, 0 },
+{"fround.h",    0, INSN_CLASS_ZFH_AND_ZFA, "D,Sm",  MATCH_FROUND_H, MASK_FROUND_H, match_opcode, 0 },
+{"froundnx.h",  0, INSN_CLASS_ZFH_AND_ZFA, "D,Sm",  MATCH_FROUNDNX_H, MASK_FROUNDNX_H, match_opcode, 0 },
+{"fcvtmod.w.d", 0, INSN_CLASS_D_AND_ZFA,   "d,S,M", MATCH_FCVTMOD_W_D, MASK_FCVTMOD_W_D, match_opcode, 0 },
 {"fmvh.x.d",   32, INSN_CLASS_D_AND_ZFA,   "d,S",   MATCH_FMVH_X_D, MASK_FMVH_X_D, match_opcode, 0 },
 {"fmvp.d.x",   32, INSN_CLASS_D_AND_ZFA,   "D,s,t", MATCH_FMVP_D_X, MASK_FMVP_D_X, match_opcode, 0 },
 {"fmvh.x.q",   64, INSN_CLASS_Q_AND_ZFA,   "d,S",   MATCH_FMVH_X_Q, MASK_FMVH_X_Q, match_opcode, 0 },


From jbeulich@suse.com  Fri Jun 19 11:50:45 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 19 Jun 2026 13:50:45 +0200
Subject: [PATCH v3 07/13] RISC-V: check operands for Zdinx in RV32
In-Reply-To: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
Message-ID: <c827b159-f08e-4f0f-88dd-302b96a25a82@suse.com>

Like for Zilsd, register pair operands are required to be encoded with the
low bit clear. Since match functions don't have XLEN available, introduce
respective flags, to be used explicitly in assembler and disassembler.
---
No similar checking is easily possible for scalar vector insns, as element
width there isn't encoded in the insn. (Plus V and Zdinx can't be enabled
together right now anyway.)

We could further use RV32_EVEN_CHECK for Zilsd as well, then allowing to
eliminate one or two match functions. (Hence RV32_EVEN_CHECK()'s scope is
pretty wide.)

--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -2928,6 +2928,12 @@ riscv_ip (char *str, struct riscv_cl_ins
       *imm_reloc = BFD_RELOC_UNUSED;
       p = percent_op_null;
 
+#define RV32_EVEN_CHECK(form, rclass, regno)     \
+  (!(ip->insn_mo->pinfo & INSN_RV32_EVEN_##form) \
+   || xlen != 32                                 \
+   || (rclass) != RCLASS_GPR                     \
+   || !((regno) & 1))
+
       for (oparg = insn->args;; ++oparg)
 	{
 	  opargStart = oparg;
@@ -2935,6 +2941,8 @@ riscv_ip (char *str, struct riscv_cl_ins
 	    ++asarg;
 	  switch (*oparg)
 	    {
+	      enum reg_class rclass;
+
 	    case '\0': /* End of args.  */
 	      if (insn->match_func && !insn->match_func (insn, ip->insn_opcode))
 		break;
@@ -3574,32 +3582,40 @@ riscv_ip (char *str, struct riscv_cl_ins
 	    case 'T': /* Floating point RS2.  */
 	    case 'U': /* Floating point RS1 and RS2.  */
 	    case 'R': /* Floating point RS3.  */
-	      if (reg_lookup (&asarg,
-			      (riscv_subset_supports (&riscv_rps_as, "zfinx")
-			      ? RCLASS_GPR : RCLASS_FPR), &regno))
+	      rclass = riscv_subset_supports (&riscv_rps_as, "zfinx")
+		       ? RCLASS_GPR : RCLASS_FPR;
+	      if (reg_lookup (&asarg, rclass, &regno))
 		{
 		  char c = *oparg;
 		  if (is_whitespace (*asarg))
 		    ++asarg;
+
 		  switch (c)
 		    {
 		    case 'D':
+		      if (!RV32_EVEN_CHECK (D, rclass, regno))
+			break;
 		      INSERT_OPERAND (RD, *ip, regno);
-		      break;
+		      continue;
 		    case 'S':
+		      if (!RV32_EVEN_CHECK (S, rclass, regno))
+			break;
 		      INSERT_OPERAND (RS1, *ip, regno);
-		      break;
+		      continue;
 		    case 'U':
 		      INSERT_OPERAND (RS1, *ip, regno);
 		      /* Fall through.  */
 		    case 'T':
+		      if (!RV32_EVEN_CHECK (T, rclass, regno))
+			break;
 		      INSERT_OPERAND (RS2, *ip, regno);
-		      break;
+		      continue;
 		    case 'R':
+		      if (!RV32_EVEN_CHECK (R, rclass, regno))
+			break;
 		      INSERT_OPERAND (RS3, *ip, regno);
-		      break;
+		      continue;
 		    }
-		  continue;
 		}
 	      break;
 
@@ -4295,6 +4311,8 @@ riscv_ip (char *str, struct riscv_cl_ins
       insn_with_csr = false;
     }
 
+#undef RV32_EVEN_CHECK
+
  out:
   /* Restore the character we might have clobbered above.  */
   if (save_c)
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zdinx-rv32.d
@@ -0,0 +1,52 @@
+#as: -march=rv32i_zdinx
+#objdump: -dwr
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+02e67553[ 	]+fadd\.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+02e60553[ 	]+fadd\.d[ 	]+a0,a2,a4,rne
+[ 	]+[0-9a-f]+:[ 	]+0ae67553[ 	]+fsub\.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+0ae60553[ 	]+fsub\.d[ 	]+a0,a2,a4,rne
+[ 	]+[0-9a-f]+:[ 	]+12e67553[ 	]+fmul\.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+12e60553[ 	]+fmul\.d[ 	]+a0,a2,a4,rne
+[ 	]+[0-9a-f]+:[ 	]+1ae67553[ 	]+fdiv\.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+1ae60553[ 	]+fdiv\.d[ 	]+a0,a2,a4,rne
+[ 	]+[0-9a-f]+:[ 	]+5a067553[ 	]+fsqrt\.d[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+5a060553[ 	]+fsqrt\.d[ 	]+a0,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+2ae60553[ 	]+fmin\.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+2ae61553[ 	]+fmax\.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+82e67543[ 	]+fmadd\.d[ 	]+a0,a2,a4,a6
+[ 	]+[0-9a-f]+:[ 	]+82e60543[ 	]+fmadd\.d[ 	]+a0,a2,a4,a6,rne
+[ 	]+[0-9a-f]+:[ 	]+82e6754f[ 	]+fnmadd\.d[ 	]+a0,a2,a4,a6
+[ 	]+[0-9a-f]+:[ 	]+82e6054f[ 	]+fnmadd\.d[ 	]+a0,a2,a4,a6,rne
+[ 	]+[0-9a-f]+:[ 	]+82e67547[ 	]+fmsub\.d[ 	]+a0,a2,a4,a6
+[ 	]+[0-9a-f]+:[ 	]+82e60547[ 	]+fmsub\.d[ 	]+a0,a2,a4,a6,rne
+[ 	]+[0-9a-f]+:[ 	]+82e6754b[ 	]+fnmsub\.d[ 	]+a0,a2,a4,a6
+[ 	]+[0-9a-f]+:[ 	]+82e6054b[ 	]+fnmsub\.d[ 	]+a0,a2,a4,a6,rne
+[ 	]+[0-9a-f]+:[ 	]+c20675d3[ 	]+fcvt\.w\.d[ 	]+a1,a2
+[ 	]+[0-9a-f]+:[ 	]+c20605d3[ 	]+fcvt\.w\.d[ 	]+a1,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+c21675d3[ 	]+fcvt\.wu\.d[ 	]+a1,a2
+[ 	]+[0-9a-f]+:[ 	]+c21605d3[ 	]+fcvt\.wu\.d[ 	]+a1,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+d2058553[ 	]+fcvt\.d\.w[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+d2158553[ 	]+fcvt\.d\.wu[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+42058553[ 	]+fcvt\.d\.s[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+401675d3[ 	]+fcvt\.s\.d[ 	]+a1,a2
+[ 	]+[0-9a-f]+:[ 	]+401605d3[ 	]+fcvt\.s\.d[ 	]+a1,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+42258553[ 	]+fcvt\.d\.h[ 	]+a0,a1
+[ 	]+[0-9a-f]+:[ 	]+441675d3[ 	]+fcvt\.h\.d[ 	]+a1,a2
+[ 	]+[0-9a-f]+:[ 	]+441605d3[ 	]+fcvt\.h\.d[ 	]+a1,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+22e60553[ 	]+fsgnj\.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+22e61553[ 	]+fsgnjn\.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+22e62553[ 	]+fsgnjx\.d[ 	]+a0,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+a2e625d3[ 	]+feq\.d[ 	]+a1,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+a2e615d3[ 	]+flt\.d[ 	]+a1,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+a2e605d3[ 	]+fle\.d[ 	]+a1,a2,a4
+[ 	]+[0-9a-f]+:[ 	]+a2c715d3[ 	]+flt\.d[ 	]+a1,a4,a2
+[ 	]+[0-9a-f]+:[ 	]+a2c705d3[ 	]+fle\.d[ 	]+a1,a4,a2
+[ 	]+[0-9a-f]+:[ 	]+22c60553[ 	]+fmv\.d[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+22c61553[ 	]+fneg\.d[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+22c62553[ 	]+fabs\.d[ 	]+a0,a2
+[ 	]+[0-9a-f]+:[ 	]+e20615d3[ 	]+fclass\.d[ 	]+a1,a2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zdinx-rv32.s
@@ -0,0 +1,52 @@
+target:
+	fadd.d		a0, a2, a4
+	fadd.d		a0, a2, a4, rne
+	fsub.d		a0, a2, a4
+	fsub.d		a0, a2, a4, rne
+	fmul.d		a0, a2, a4
+	fmul.d		a0, a2, a4, rne
+	fdiv.d		a0, a2, a4
+	fdiv.d		a0, a2, a4, rne
+	fsqrt.d		a0, a2
+	fsqrt.d		a0, a2, rne
+	fmin.d		a0, a2, a4
+	fmax.d		a0, a2, a4
+	fmadd.d		a0, a2, a4, a6
+	fmadd.d		a0, a2, a4, a6, rne
+	fnmadd.d	a0, a2, a4, a6
+	fnmadd.d	a0, a2, a4, a6, rne
+	fmsub.d		a0, a2, a4, a6
+	fmsub.d		a0, a2, a4, a6, rne
+	fnmsub.d	a0, a2, a4, a6
+	fnmsub.d	a0, a2, a4, a6, rne
+
+	fcvt.w.d	a1, a2
+	fcvt.w.d	a1, a2, rne
+	fcvt.wu.d	a1, a2
+	fcvt.wu.d	a1, a2, rne
+	fcvt.d.w	a0, a1
+	fcvt.d.wu	a0, a1
+
+	fcvt.d.s	a0, a1
+	fcvt.s.d	a1, a2
+	fcvt.s.d	a1, a2, rne
+
+	.option push
+	.option arch, +zhinxmin
+	fcvt.d.h	a0, a1
+	fcvt.h.d	a1, a2
+	fcvt.h.d	a1, a2, rne
+	.option pop
+
+	fsgnj.d		a0, a2, a4
+	fsgnjn.d	a0, a2, a4
+	fsgnjx.d	a0, a2, a4
+	feq.d		a1, a2, a4
+	flt.d		a1, a2, a4
+	fle.d		a1, a2, a4
+	fgt.d		a1, a2, a4
+	fge.d		a1, a2, a4
+	fmv.d		a0, a2
+	fneg.d		a0, a2
+	fabs.d		a0, a2
+	fclass.d	a1, a2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zdinx-rv32-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_zdinx
+#source: zdinx.s
+#error_output: zdinx-rv32-fail.l
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zdinx-rv32-fail.l
@@ -0,0 +1,47 @@
+.*: Assembler messages:
+.*: Error: illegal operands `fadd\.d .*'
+.*: Error: illegal operands `fadd\.d .*'
+.*: Error: illegal operands `fsub\.d .*'
+.*: Error: illegal operands `fsub\.d .*'
+.*: Error: illegal operands `fmul\.d .*'
+.*: Error: illegal operands `fmul\.d .*'
+.*: Error: illegal operands `fdiv\.d .*'
+.*: Error: illegal operands `fdiv\.d .*'
+.*: Error: illegal operands `fsqrt\.d .*'
+.*: Error: illegal operands `fsqrt\.d .*'
+.*: Error: illegal operands `fmin\.d .*'
+.*: Error: illegal operands `fmax\.d .*'
+.*: Error: illegal operands `fmadd\.d .*'
+.*: Error: illegal operands `fmadd\.d .*'
+.*: Error: illegal operands `fnmadd\.d .*'
+.*: Error: illegal operands `fnmadd\.d .*'
+.*: Error: illegal operands `fmsub\.d .*'
+.*: Error: illegal operands `fmsub\.d .*'
+.*: Error: illegal operands `fnmsub\.d .*'
+.*: Error: illegal operands `fnmsub\.d .*'
+.*: Error: illegal operands `fcvt\.w\.d .*'
+.*: Error: illegal operands `fcvt\.w\.d .*'
+.*: Error: illegal operands `fcvt\.wu\.d .*'
+.*: Error: illegal operands `fcvt\.wu\.d .*'
+.*: Error: unrecognized opcode `fcvt\.l\.d .*'
+.*: Error: unrecognized opcode `fcvt\.l\.d .*'
+.*: Error: unrecognized opcode `fcvt\.lu\.d .*'
+.*: Error: unrecognized opcode `fcvt\.lu\.d .*'
+.*: Error: unrecognized opcode `fcvt\.d\.l .*'
+.*: Error: unrecognized opcode `fcvt\.d\.l .*'
+.*: Error: unrecognized opcode `fcvt\.d\.lu .*'
+.*: Error: unrecognized opcode `fcvt\.d\.lu .*'
+.*: Error: illegal operands `fcvt\.s\.d .*'
+.*: Error: illegal operands `fcvt\.s\.d .*'
+.*: Error: illegal operands `fsgnj\.d .*'
+.*: Error: illegal operands `fsgnjn\.d .*'
+.*: Error: illegal operands `fsgnjx\.d .*'
+.*: Error: illegal operands `feq\.d .*'
+.*: Error: illegal operands `flt\.d .*'
+.*: Error: illegal operands `fle\.d .*'
+.*: Error: illegal operands `fgt\.d .*'
+.*: Error: illegal operands `fge\.d .*'
+.*: Error: illegal operands `fmv\.d .*'
+.*: Error: illegal operands `fneg\.d .*'
+.*: Error: illegal operands `fabs\.d .*'
+.*: Error: illegal operands `fclass\.d .*'
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -679,6 +679,18 @@ struct riscv_opcode
 #define INSN_8_BYTE		0x00000040
 #define INSN_16_BYTE		0x00000050
 
+/* Operands required to be an even-numbered register (pair) in RV32.  */
+#define INSN_RV32_EVEN_D	0x00000100
+#define INSN_RV32_EVEN_S	0x00000200
+#define INSN_RV32_EVEN_T	0x00000400 /* Also covering U.  */
+#define INSN_RV32_EVEN_R	0x00000800
+/* Shorthands for combinations of the above.  */
+#define INSN_RV32_EVEN_DS	(INSN_RV32_EVEN_D   | INSN_RV32_EVEN_S)
+#define INSN_RV32_EVEN_DST	(INSN_RV32_EVEN_DS  | INSN_RV32_EVEN_T)
+#define INSN_RV32_EVEN_DSTR	(INSN_RV32_EVEN_DST | INSN_RV32_EVEN_R)
+#define INSN_RV32_EVEN_DU	(INSN_RV32_EVEN_D   | INSN_RV32_EVEN_T)
+#define INSN_RV32_EVEN_ST	(INSN_RV32_EVEN_S   | INSN_RV32_EVEN_T)
+
 /* Instruction is actually a macro.  It should be ignored by the
    disassembler, and requires special treatment by the assembler.  */
 #define INSN_MACRO		0xffffffff
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -1032,6 +1032,23 @@ riscv_disassemble_insn (bfd_vma memaddr,
  	      if ((op->pinfo & INSN_V_EEW64)
 		  && !riscv_subset_supports (&pd->riscv_rps_dis, "zve64x"))
 		continue;
+
+	      if (pd->xlen == 32
+		  && riscv_subset_supports (&pd->riscv_rps_dis, "zdinx"))
+		{
+		  if ((op->pinfo & INSN_RV32_EVEN_D)
+		      && (word & (1u << OP_SH_RD)))
+		    continue;
+		  if ((op->pinfo & INSN_RV32_EVEN_S)
+		      && (word & (1u << OP_SH_RS1)))
+		    continue;
+		  if ((op->pinfo & INSN_RV32_EVEN_T)
+		      && (word & (1u << OP_SH_RS2)))
+		    continue;
+		  if ((op->pinfo & INSN_RV32_EVEN_R)
+		      && (word & (1u << OP_SH_RS3)))
+		    continue;
+		}
 	    }
 
 	  /* It's a match.  */
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -931,10 +931,10 @@ const struct riscv_opcode riscv_opcodes[
 {"fcvt.h.w",   0, INSN_CLASS_ZFH_INX,  "D,sm",      MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 },
 {"fcvt.h.wu",  0, INSN_CLASS_ZFH_INX,  "D,sm",      MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 },
 {"fcvt.s.h",   0, INSN_CLASS_ZFHMIN_INX, "D,S",     MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 },
-{"fcvt.d.h",   0, INSN_CLASS_ZFHMIN_AND_D_INX,     "D,S",       MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, 0 },
-{"fcvt.q.h",   0, INSN_CLASS_ZFHMIN_AND_Q_INX,     "D,S",       MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 },
+{"fcvt.d.h",   0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,S", MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, INSN_RV32_EVEN_D },
+{"fcvt.q.h",   0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 },
 {"fcvt.h.s",   0, INSN_CLASS_ZFHMIN_INX, "D,Sm",    MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 },
-{"fcvt.h.d",   0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,Sm", MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, 0 },
+{"fcvt.h.d",   0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,Sm", MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, INSN_RV32_EVEN_S },
 {"fcvt.h.q",   0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,Sm", MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 },
 {"fclass.h",   0, INSN_CLASS_ZFH_INX,   "d,S",       MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 },
 {"feq.h",      0, INSN_CLASS_ZFH_INX,   "d,S,T",     MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 },
@@ -1021,35 +1021,35 @@ const struct riscv_opcode riscv_opcodes[
 {"fsd",        0, INSN_CLASS_ZCD, "CD,Cl(Cs)", MATCH_C_FSD, MASK_C_FSD, match_opcode, INSN_ALIAS|INSN_DREF|INSN_8_BYTE },
 {"fsd",        0, INSN_CLASS_D,   "T,q(s)",    MATCH_FSD, MASK_FSD, match_opcode, INSN_DREF|INSN_8_BYTE },
 {"fsd",        0, INSN_CLASS_D,   "T,A,s",     0, (int) M_Sx_FSx, match_rs1_nonzero, INSN_MACRO },
-{"fmv.d",      0, INSN_CLASS_D_INX,   "D,U",       MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS },
-{"fneg.d",     0, INSN_CLASS_D_INX,   "D,U",       MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS },
-{"fabs.d",     0, INSN_CLASS_D_INX,   "D,U",       MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS },
-{"fsgnj.d",    0, INSN_CLASS_D_INX,   "D,S,T",     MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, 0 },
-{"fsgnjn.d",   0, INSN_CLASS_D_INX,   "D,S,T",     MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, 0 },
-{"fsgnjx.d",   0, INSN_CLASS_D_INX,   "D,S,T",     MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, 0 },
-{"fadd.d",     0, INSN_CLASS_D_INX,   "D,S,Tm",    MATCH_FADD_D, MASK_FADD_D, match_opcode, 0 },
-{"fsub.d",     0, INSN_CLASS_D_INX,   "D,S,Tm",    MATCH_FSUB_D, MASK_FSUB_D, match_opcode, 0 },
-{"fmul.d",     0, INSN_CLASS_D_INX,   "D,S,Tm",    MATCH_FMUL_D, MASK_FMUL_D, match_opcode, 0 },
-{"fdiv.d",     0, INSN_CLASS_D_INX,   "D,S,Tm",    MATCH_FDIV_D, MASK_FDIV_D, match_opcode, 0 },
-{"fsqrt.d",    0, INSN_CLASS_D_INX,   "D,Sm",      MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, 0 },
-{"fmin.d",     0, INSN_CLASS_D_INX,   "D,S,T",     MATCH_FMIN_D, MASK_FMIN_D, match_opcode, 0 },
-{"fmax.d",     0, INSN_CLASS_D_INX,   "D,S,T",     MATCH_FMAX_D, MASK_FMAX_D, match_opcode, 0 },
-{"fmadd.d",    0, INSN_CLASS_D_INX,   "D,S,T,Rm",  MATCH_FMADD_D, MASK_FMADD_D, match_opcode, 0 },
-{"fnmadd.d",   0, INSN_CLASS_D_INX,   "D,S,T,Rm",  MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, 0 },
-{"fmsub.d",    0, INSN_CLASS_D_INX,   "D,S,T,Rm",  MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, 0 },
-{"fnmsub.d",   0, INSN_CLASS_D_INX,   "D,S,T,Rm",  MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, 0 },
-{"fcvt.w.d",   0, INSN_CLASS_D_INX,   "d,Sm",      MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, 0 },
-{"fcvt.wu.d",  0, INSN_CLASS_D_INX,   "d,Sm",      MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, 0 },
-{"fcvt.d.w",   0, INSN_CLASS_D_INX,   "D,s",       MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, 0 },
-{"fcvt.d.wu",  0, INSN_CLASS_D_INX,   "D,s",       MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, 0 },
-{"fcvt.d.s",   0, INSN_CLASS_D_INX,   "D,S",       MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, 0 },
-{"fcvt.s.d",   0, INSN_CLASS_D_INX,   "D,Sm",      MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, 0 },
-{"fclass.d",   0, INSN_CLASS_D_INX,   "d,S",       MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, 0 },
-{"feq.d",      0, INSN_CLASS_D_INX,   "d,S,T",     MATCH_FEQ_D, MASK_FEQ_D, match_opcode, 0 },
-{"flt.d",      0, INSN_CLASS_D_INX,   "d,S,T",     MATCH_FLT_D, MASK_FLT_D, match_opcode, 0 },
-{"fle.d",      0, INSN_CLASS_D_INX,   "d,S,T",     MATCH_FLE_D, MASK_FLE_D, match_opcode, 0 },
-{"fgt.d",      0, INSN_CLASS_D_INX,   "d,T,S",     MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_ALIAS },
-{"fge.d",      0, INSN_CLASS_D_INX,   "d,T,S",     MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_ALIAS },
+{"fmv.d",      0, INSN_CLASS_D_INX,   "D,U",       MATCH_FSGNJ_D, MASK_FSGNJ_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_RV32_EVEN_DU },
+{"fneg.d",     0, INSN_CLASS_D_INX,   "D,U",       MATCH_FSGNJN_D, MASK_FSGNJN_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_RV32_EVEN_DU },
+{"fabs.d",     0, INSN_CLASS_D_INX,   "D,U",       MATCH_FSGNJX_D, MASK_FSGNJX_D, match_rs1_eq_rs2, INSN_ALIAS|INSN_RV32_EVEN_DU },
+{"fsgnj.d",    0, INSN_CLASS_D_INX,   "D,S,T",     MATCH_FSGNJ_D, MASK_FSGNJ_D, match_opcode, INSN_RV32_EVEN_DST },
+{"fsgnjn.d",   0, INSN_CLASS_D_INX,   "D,S,T",     MATCH_FSGNJN_D, MASK_FSGNJN_D, match_opcode, INSN_RV32_EVEN_DST },
+{"fsgnjx.d",   0, INSN_CLASS_D_INX,   "D,S,T",     MATCH_FSGNJX_D, MASK_FSGNJX_D, match_opcode, INSN_RV32_EVEN_DST },
+{"fadd.d",     0, INSN_CLASS_D_INX,   "D,S,Tm",    MATCH_FADD_D, MASK_FADD_D, match_opcode, INSN_RV32_EVEN_DST },
+{"fsub.d",     0, INSN_CLASS_D_INX,   "D,S,Tm",    MATCH_FSUB_D, MASK_FSUB_D, match_opcode, INSN_RV32_EVEN_DST },
+{"fmul.d",     0, INSN_CLASS_D_INX,   "D,S,Tm",    MATCH_FMUL_D, MASK_FMUL_D, match_opcode, INSN_RV32_EVEN_DST },
+{"fdiv.d",     0, INSN_CLASS_D_INX,   "D,S,Tm",    MATCH_FDIV_D, MASK_FDIV_D, match_opcode, INSN_RV32_EVEN_DST },
+{"fsqrt.d",    0, INSN_CLASS_D_INX,   "D,Sm",      MATCH_FSQRT_D, MASK_FSQRT_D, match_opcode, INSN_RV32_EVEN_DS },
+{"fmin.d",     0, INSN_CLASS_D_INX,   "D,S,T",     MATCH_FMIN_D, MASK_FMIN_D, match_opcode, INSN_RV32_EVEN_DST },
+{"fmax.d",     0, INSN_CLASS_D_INX,   "D,S,T",     MATCH_FMAX_D, MASK_FMAX_D, match_opcode, INSN_RV32_EVEN_DST },
+{"fmadd.d",    0, INSN_CLASS_D_INX,   "D,S,T,Rm",  MATCH_FMADD_D, MASK_FMADD_D, match_opcode, INSN_RV32_EVEN_DSTR },
+{"fnmadd.d",   0, INSN_CLASS_D_INX,   "D,S,T,Rm",  MATCH_FNMADD_D, MASK_FNMADD_D, match_opcode, INSN_RV32_EVEN_DSTR },
+{"fmsub.d",    0, INSN_CLASS_D_INX,   "D,S,T,Rm",  MATCH_FMSUB_D, MASK_FMSUB_D, match_opcode, INSN_RV32_EVEN_DSTR },
+{"fnmsub.d",   0, INSN_CLASS_D_INX,   "D,S,T,Rm",  MATCH_FNMSUB_D, MASK_FNMSUB_D, match_opcode, INSN_RV32_EVEN_DSTR },
+{"fcvt.w.d",   0, INSN_CLASS_D_INX,   "d,Sm",      MATCH_FCVT_W_D, MASK_FCVT_W_D, match_opcode, INSN_RV32_EVEN_S },
+{"fcvt.wu.d",  0, INSN_CLASS_D_INX,   "d,Sm",      MATCH_FCVT_WU_D, MASK_FCVT_WU_D, match_opcode, INSN_RV32_EVEN_S },
+{"fcvt.d.w",   0, INSN_CLASS_D_INX,   "D,s",       MATCH_FCVT_D_W, MASK_FCVT_D_W|MASK_RM, match_opcode, INSN_RV32_EVEN_D },
+{"fcvt.d.wu",  0, INSN_CLASS_D_INX,   "D,s",       MATCH_FCVT_D_WU, MASK_FCVT_D_WU|MASK_RM, match_opcode, INSN_RV32_EVEN_D },
+{"fcvt.d.s",   0, INSN_CLASS_D_INX,   "D,S",       MATCH_FCVT_D_S, MASK_FCVT_D_S|MASK_RM, match_opcode, INSN_RV32_EVEN_D },
+{"fcvt.s.d",   0, INSN_CLASS_D_INX,   "D,Sm",      MATCH_FCVT_S_D, MASK_FCVT_S_D, match_opcode, INSN_RV32_EVEN_S },
+{"fclass.d",   0, INSN_CLASS_D_INX,   "d,S",       MATCH_FCLASS_D, MASK_FCLASS_D, match_opcode, INSN_RV32_EVEN_S },
+{"feq.d",      0, INSN_CLASS_D_INX,   "d,S,T",     MATCH_FEQ_D, MASK_FEQ_D, match_opcode, INSN_RV32_EVEN_ST },
+{"flt.d",      0, INSN_CLASS_D_INX,   "d,S,T",     MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_RV32_EVEN_ST },
+{"fle.d",      0, INSN_CLASS_D_INX,   "d,S,T",     MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_RV32_EVEN_ST },
+{"fgt.d",      0, INSN_CLASS_D_INX,   "d,T,S",     MATCH_FLT_D, MASK_FLT_D, match_opcode, INSN_ALIAS|INSN_RV32_EVEN_ST },
+{"fge.d",      0, INSN_CLASS_D_INX,   "d,T,S",     MATCH_FLE_D, MASK_FLE_D, match_opcode, INSN_ALIAS|INSN_RV32_EVEN_ST },
 {"fmv.x.d",   64, INSN_CLASS_D,   "d,S",       MATCH_FMV_X_D, MASK_FMV_X_D, match_opcode, 0 },
 {"fmv.d.x",   64, INSN_CLASS_D,   "D,s",       MATCH_FMV_D_X, MASK_FMV_D_X, match_opcode, 0 },
 {"fcvt.l.d",  64, INSN_CLASS_D_INX,   "d,Sm",      MATCH_FCVT_L_D, MASK_FCVT_L_D, match_opcode, 0 },


From jbeulich@suse.com  Fri Jun 19 11:51:10 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 19 Jun 2026 13:51:10 +0200
Subject: [PATCH v3 08/13] RISC-V: check operands for Zqinx
In-Reply-To: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
Message-ID: <1aecd2c8-d5f5-4f36-a8ae-36ae4ea83978@suse.com>

By analogy to Zdinx on RV32, register pair operands are presumably (there
not being any formal spec afaict) required to be encoded with the low bit
clear in RV64; in RV32 the low two bits need to be clear. Since match
functions don't have XLEN available, introduce respective flags, to be
used explicitly in assembler and disassembler.
---
Does Zqinx actually make much sense in RV32? Function argument passing,
for example, ends up odd: a0..a3 aren't suitable to hold an argument.
Hence only a single argument can be passed in registers (a2..a5).

No similar checking is easily possible for scalar vector insns, as element
width there isn't encoded in the insn. (Plus V and Zqinx can't be enabled
together right now anyway.)
---
v3: Fix typo in comment.
v2: New.

--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -2934,6 +2934,12 @@ riscv_ip (char *str, struct riscv_cl_ins
    || (rclass) != RCLASS_GPR                     \
    || !((regno) & 1))
 
+#define RV64_EVEN_CHECK(form, rclass, regno)     \
+  (!(ip->insn_mo->pinfo & INSN_RV64_EVEN_##form) \
+   || xlen > 64                                  \
+   || (rclass) != RCLASS_GPR                     \
+   || !((regno) & (xlen == 32 ? 3 : 1)))
+
       for (oparg = insn->args;; ++oparg)
 	{
 	  opargStart = oparg;
@@ -3593,12 +3599,14 @@ riscv_ip (char *str, struct riscv_cl_ins
 		  switch (c)
 		    {
 		    case 'D':
-		      if (!RV32_EVEN_CHECK (D, rclass, regno))
+		      if (!RV32_EVEN_CHECK (D, rclass, regno)
+			  || !RV64_EVEN_CHECK (D, rclass, regno))
 			break;
 		      INSERT_OPERAND (RD, *ip, regno);
 		      continue;
 		    case 'S':
-		      if (!RV32_EVEN_CHECK (S, rclass, regno))
+		      if (!RV32_EVEN_CHECK (S, rclass, regno)
+			  || !RV64_EVEN_CHECK (S, rclass, regno))
 			break;
 		      INSERT_OPERAND (RS1, *ip, regno);
 		      continue;
@@ -3606,12 +3614,14 @@ riscv_ip (char *str, struct riscv_cl_ins
 		      INSERT_OPERAND (RS1, *ip, regno);
 		      /* Fall through.  */
 		    case 'T':
-		      if (!RV32_EVEN_CHECK (T, rclass, regno))
+		      if (!RV32_EVEN_CHECK (T, rclass, regno)
+			  || !RV64_EVEN_CHECK (T, rclass, regno))
 			break;
 		      INSERT_OPERAND (RS2, *ip, regno);
 		      continue;
 		    case 'R':
-		      if (!RV32_EVEN_CHECK (R, rclass, regno))
+		      if (!RV32_EVEN_CHECK (R, rclass, regno)
+			  || !RV64_EVEN_CHECK (R, rclass, regno))
 			break;
 		      INSERT_OPERAND (RS3, *ip, regno);
 		      continue;
@@ -4312,6 +4322,7 @@ riscv_ip (char *str, struct riscv_cl_ins
     }
 
 #undef RV32_EVEN_CHECK
+#undef RV64_EVEN_CHECK
 
  out:
   /* Restore the character we might have clobbered above.  */
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-rv32.d
@@ -0,0 +1,52 @@
+#as: -march=rv32i_zqinx
+#objdump: -dwr
+
+.*:[ 	]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+078a7453[ 	]+fadd\.q[ 	]+s0,s4,s8
+[ 	]+[0-9a-f]+:[ 	]+078a0453[ 	]+fadd\.q[ 	]+s0,s4,s8,rne
+[ 	]+[0-9a-f]+:[ 	]+0f8a7453[ 	]+fsub\.q[ 	]+s0,s4,s8
+[ 	]+[0-9a-f]+:[ 	]+0f8a0453[ 	]+fsub\.q[ 	]+s0,s4,s8,rne
+[ 	]+[0-9a-f]+:[ 	]+178a7453[ 	]+fmul\.q[ 	]+s0,s4,s8
+[ 	]+[0-9a-f]+:[ 	]+178a0453[ 	]+fmul\.q[ 	]+s0,s4,s8,rne
+[ 	]+[0-9a-f]+:[ 	]+1f8a7453[ 	]+fdiv\.q[ 	]+s0,s4,s8
+[ 	]+[0-9a-f]+:[ 	]+1f8a0453[ 	]+fdiv\.q[ 	]+s0,s4,s8,rne
+[ 	]+[0-9a-f]+:[ 	]+5e0a7453[ 	]+fsqrt\.q[ 	]+s0,s4
+[ 	]+[0-9a-f]+:[ 	]+5e0a0453[ 	]+fsqrt\.q[ 	]+s0,s4,rne
+[ 	]+[0-9a-f]+:[ 	]+2f8a0453[ 	]+fmin\.q[ 	]+s0,s4,s8
+[ 	]+[0-9a-f]+:[ 	]+2f8a1453[ 	]+fmax\.q[ 	]+s0,s4,s8
+[ 	]+[0-9a-f]+:[ 	]+678a7443[ 	]+fmadd\.q[ 	]+s0,s4,s8,a2
+[ 	]+[0-9a-f]+:[ 	]+678a0443[ 	]+fmadd\.q[ 	]+s0,s4,s8,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+678a744f[ 	]+fnmadd\.q[ 	]+s0,s4,s8,a2
+[ 	]+[0-9a-f]+:[ 	]+678a044f[ 	]+fnmadd\.q[ 	]+s0,s4,s8,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+678a7447[ 	]+fmsub\.q[ 	]+s0,s4,s8,a2
+[ 	]+[0-9a-f]+:[ 	]+678a0447[ 	]+fmsub\.q[ 	]+s0,s4,s8,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+678a744b[ 	]+fnmsub\.q[ 	]+s0,s4,s8,a2
+[ 	]+[0-9a-f]+:[ 	]+678a044b[ 	]+fnmsub\.q[ 	]+s0,s4,s8,a2,rne
+[ 	]+[0-9a-f]+:[ 	]+c60a75d3[ 	]+fcvt\.w\.q[ 	]+a1,s4
+[ 	]+[0-9a-f]+:[ 	]+c60a05d3[ 	]+fcvt\.w\.q[ 	]+a1,s4,rne
+[ 	]+[0-9a-f]+:[ 	]+c61a75d3[ 	]+fcvt\.wu\.q[ 	]+a1,s4
+[ 	]+[0-9a-f]+:[ 	]+c61a05d3[ 	]+fcvt\.wu\.q[ 	]+a1,s4,rne
+[ 	]+[0-9a-f]+:[ 	]+d6058453[ 	]+fcvt\.q\.w[ 	]+s0,a1
+[ 	]+[0-9a-f]+:[ 	]+d6158453[ 	]+fcvt\.q\.wu[ 	]+s0,a1
+[ 	]+[0-9a-f]+:[ 	]+46058453[ 	]+fcvt\.q\.s[ 	]+s0,a1
+[ 	]+[0-9a-f]+:[ 	]+403a75d3[ 	]+fcvt\.s\.q[ 	]+a1,s4
+[ 	]+[0-9a-f]+:[ 	]+403a05d3[ 	]+fcvt\.s\.q[ 	]+a1,s4,rne
+[ 	]+[0-9a-f]+:[ 	]+46150453[ 	]+fcvt\.q\.d[ 	]+s0,a0
+[ 	]+[0-9a-f]+:[ 	]+423a7553[ 	]+fcvt\.d\.q[ 	]+a0,s4
+[ 	]+[0-9a-f]+:[ 	]+423a0553[ 	]+fcvt\.d\.q[ 	]+a0,s4,rne
+[ 	]+[0-9a-f]+:[ 	]+46258453[ 	]+fcvt\.q\.h[ 	]+s0,a1
+[ 	]+[0-9a-f]+:[ 	]+443a75d3[ 	]+fcvt\.h\.q[ 	]+a1,s4
+[ 	]+[0-9a-f]+:[ 	]+443a05d3[ 	]+fcvt\.h\.q[ 	]+a1,s4,rne
+[ 	]+[0-9a-f]+:[ 	]+278a0453[ 	]+fsgnj\.q[ 	]+s0,s4,s8
+[ 	]+[0-9a-f]+:[ 	]+278a1453[ 	]+fsgnjn\.q[ 	]+s0,s4,s8
+[ 	]+[0-9a-f]+:[ 	]+278a2453[ 	]+fsgnjx\.q[ 	]+s0,s4,s8
+[ 	]+[0-9a-f]+:[ 	]+a78a25d3[ 	]+feq\.q[ 	]+a1,s4,s8
+[ 	]+[0-9a-f]+:[ 	]+a78a15d3[ 	]+flt\.q[ 	]+a1,s4,s8
+[ 	]+[0-9a-f]+:[ 	]+a78a05d3[ 	]+fle\.q[ 	]+a1,s4,s8
+[ 	]+[0-9a-f]+:[ 	]+a74c15d3[ 	]+flt\.q[ 	]+a1,s8,s4
+[ 	]+[0-9a-f]+:[ 	]+a74c05d3[ 	]+fle\.q[ 	]+a1,s8,s4
+[ 	]+[0-9a-f]+:[ 	]+274a0453[ 	]+fmv\.q[ 	]+s0,s4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-rv32.s
@@ -0,0 +1,54 @@
+target:
+	fadd.q		s0, s4, s8
+	fadd.q		s0, s4, s8, rne
+	fsub.q		s0, s4, s8
+	fsub.q		s0, s4, s8, rne
+	fmul.q		s0, s4, s8
+	fmul.q		s0, s4, s8, rne
+	fdiv.q		s0, s4, s8
+	fdiv.q		s0, s4, s8, rne
+	fsqrt.q		s0, s4
+	fsqrt.q		s0, s4, rne
+	fmin.q		s0, s4, s8
+	fmax.q		s0, s4, s8
+	fmadd.q		s0, s4, s8, a2
+	fmadd.q		s0, s4, s8, a2, rne
+	fnmadd.q	s0, s4, s8, a2
+	fnmadd.q	s0, s4, s8, a2, rne
+	fmsub.q		s0, s4, s8, a2
+	fmsub.q		s0, s4, s8, a2, rne
+	fnmsub.q	s0, s4, s8, a2
+	fnmsub.q	s0, s4, s8, a2, rne
+
+	fcvt.w.q	a1, s4
+	fcvt.w.q	a1, s4, rne
+	fcvt.wu.q	a1, s4
+	fcvt.wu.q	a1, s4, rne
+	fcvt.q.w	s0, a1
+	fcvt.q.wu	s0, a1
+
+	fcvt.q.s	s0, a1
+	fcvt.s.q	a1, s4
+	fcvt.s.q	a1, s4, rne
+
+	fcvt.q.d	s0, a0
+	fcvt.d.q	a0, s4
+	fcvt.d.q	a0, s4, rne
+
+	.option push
+	.option arch, +zhinxmin
+	fcvt.q.h	s0, a1
+	fcvt.h.q	a1, s4
+	fcvt.h.q	a1, s4, rne
+	.option pop
+
+	fsgnj.q		s0, s4, s8
+	fsgnjn.q	s0, s4, s8
+	fsgnjx.q	s0, s4, s8
+	feq.q		a1, s4, s8
+	flt.q		a1, s4, s8
+	fle.q		a1, s4, s8
+	fgt.q		a1, s4, s8
+	fge.q		a1, s4, s8
+
+	fmv.q		s0, s4
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-rv32-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv32i_zqinx
+#source: zqinx.s
+#error_output: zqinx-rv32-fail.l
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-rv32-fail.l
@@ -0,0 +1,42 @@
+.*: Assembler messages:
+.*: Error: illegal operands `fadd\.q .*'
+.*: Error: illegal operands `fadd\.q .*'
+.*: Error: illegal operands `fsub\.q .*'
+.*: Error: illegal operands `fsub\.q .*'
+.*: Error: illegal operands `fmul\.q .*'
+.*: Error: illegal operands `fmul\.q .*'
+.*: Error: illegal operands `fdiv\.q .*'
+.*: Error: illegal operands `fdiv\.q .*'
+.*: Error: illegal operands `fsqrt\.q .*'
+.*: Error: illegal operands `fsqrt\.q .*'
+.*: Error: illegal operands `fmin\.q .*'
+.*: Error: illegal operands `fmax\.q .*'
+.*: Error: illegal operands `fmadd\.q .*'
+.*: Error: illegal operands `fmadd\.q .*'
+.*: Error: illegal operands `fnmadd\.q .*'
+.*: Error: illegal operands `fnmadd\.q .*'
+.*: Error: illegal operands `fmsub\.q .*'
+.*: Error: illegal operands `fmsub\.q .*'
+.*: Error: illegal operands `fnmsub\.q .*'
+.*: Error: illegal operands `fnmsub\.q .*'
+.*: Error: unrecognized opcode `fcvt\.l\.q .*'
+.*: Error: unrecognized opcode `fcvt\.l\.q .*'
+.*: Error: unrecognized opcode `fcvt\.lu\.q .*'
+.*: Error: unrecognized opcode `fcvt\.lu\.q .*'
+.*: Error: illegal operands `fcvt\.q\.w .*'
+.*: Error: illegal operands `fcvt\.q\.wu .*'
+.*: Error: unrecognized opcode `fcvt\.q\.l .*'
+.*: Error: unrecognized opcode `fcvt\.q\.lu .*'
+.*: Error: illegal operands `fcvt\.q\.s .*'
+.*: Error: illegal operands `fcvt\.q\.d .*'
+.*: Error: illegal operands `fsgnj\.q .*'
+.*: Error: illegal operands `fsgnjn\.q .*'
+.*: Error: illegal operands `fsgnjx\.q .*'
+.*: Error: illegal operands `feq\.q .*'
+.*: Error: illegal operands `flt\.q .*'
+.*: Error: illegal operands `fle\.q .*'
+.*: Error: illegal operands `fgt\.q .*'
+.*: Error: illegal operands `fge\.q .*'
+.*: Error: illegal operands `fmv\.q .*'
+.*: Error: illegal operands `fneg\.q .*'
+.*: Error: illegal operands `fabs\.q .*'
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-rv64-fail.d
@@ -0,0 +1,2 @@
+#as: -march=rv64i_zqinx
+#error_output: zqinx-rv64-fail.l
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-rv64-fail.l
@@ -0,0 +1,62 @@
+.*: Assembler messages:
+.*: Error: illegal operands `fadd\.q .*'
+.*: Error: illegal operands `fadd\.q .*'
+.*: Error: illegal operands `fadd\.q .*'
+.*: Error: illegal operands `fsub\.q .*'
+.*: Error: illegal operands `fsub\.q .*'
+.*: Error: illegal operands `fsub\.q .*'
+.*: Error: illegal operands `fmul\.q .*'
+.*: Error: illegal operands `fmul\.q .*'
+.*: Error: illegal operands `fmul\.q .*'
+.*: Error: illegal operands `fdiv\.q .*'
+.*: Error: illegal operands `fdiv\.q .*'
+.*: Error: illegal operands `fdiv\.q .*'
+.*: Error: illegal operands `fsqrt\.q .*'
+.*: Error: illegal operands `fsqrt\.q .*'
+.*: Error: illegal operands `fmin\.q .*'
+.*: Error: illegal operands `fmin\.q .*'
+.*: Error: illegal operands `fmin\.q .*'
+.*: Error: illegal operands `fmax\.q .*'
+.*: Error: illegal operands `fmax\.q .*'
+.*: Error: illegal operands `fmax\.q .*'
+.*: Error: illegal operands `fmadd\.q .*'
+.*: Error: illegal operands `fmadd\.q .*'
+.*: Error: illegal operands `fmadd\.q .*'
+.*: Error: illegal operands `fmadd\.q .*'
+.*: Error: illegal operands `fnmadd\.q .*'
+.*: Error: illegal operands `fnmadd\.q .*'
+.*: Error: illegal operands `fnmadd\.q .*'
+.*: Error: illegal operands `fnmadd\.q .*'
+.*: Error: illegal operands `fmsub\.q .*'
+.*: Error: illegal operands `fmsub\.q .*'
+.*: Error: illegal operands `fmsub\.q .*'
+.*: Error: illegal operands `fmsub\.q .*'
+.*: Error: illegal operands `fnmsub\.q .*'
+.*: Error: illegal operands `fnmsub\.q .*'
+.*: Error: illegal operands `fnmsub\.q .*'
+.*: Error: illegal operands `fnmsub\.q .*'
+.*: Error: illegal operands `fcvt\.w\.q .*'
+.*: Error: illegal operands `fcvt\.wu\.q .*'
+.*: Error: illegal operands `fcvt\.q\.w .*'
+.*: Error: illegal operands `fcvt\.q\.wu .*'
+.*: Error: illegal operands `fcvt\.q\.s .*'
+.*: Error: illegal operands `fcvt\.s\.q .*'
+.*: Error: illegal operands `fcvt\.q\.d .*'
+.*: Error: illegal operands `fcvt\.d\.q .*'
+.*: Error: illegal operands `fcvt\.q\.h .*'
+.*: Error: illegal operands `fcvt\.h\.q .*'
+.*: Error: illegal operands `fsgnj\.q .*'
+.*: Error: illegal operands `fsgnjn\.q .*'
+.*: Error: illegal operands `fsgnjx\.q .*'
+.*: Error: illegal operands `feq\.q .*'
+.*: Error: illegal operands `flt\.q .*'
+.*: Error: illegal operands `fle\.q .*'
+.*: Error: illegal operands `fgt\.q .*'
+.*: Error: illegal operands `fge\.q .*'
+.*: Error: illegal operands `fmv\.q .*'
+.*: Error: illegal operands `fmv\.q .*'
+.*: Error: illegal operands `fneg\.q .*'
+.*: Error: illegal operands `fneg\.q .*'
+.*: Error: illegal operands `fabs\.q .*'
+.*: Error: illegal operands `fabs\.q .*'
+.*: Error: illegal operands `fclass\.q .*'
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zqinx-rv64-fail.s
@@ -0,0 +1,70 @@
+target:
+	fadd.q		s1, s4, s8
+	fadd.q		s0, s5, s8
+	fadd.q		s0, s4, s9
+	fsub.q		s1, s4, s8
+	fsub.q		s0, s5, s8
+	fsub.q		s0, s4, s9
+	fmul.q		s1, s4, s8
+	fmul.q		s0, s5, s8
+	fmul.q		s0, s4, s9
+	fdiv.q		s1, s4, s8
+	fdiv.q		s0, s5, s8
+	fdiv.q		s0, s4, s9
+	fsqrt.q		s1, s4
+	fsqrt.q		s0, s5
+	fmin.q		s1, s4, s8
+	fmin.q		s0, s5, s8
+	fmin.q		s0, s4, s9
+	fmax.q		s1, s4, s8
+	fmax.q		s0, s5, s8
+	fmax.q		s0, s4, s9
+	fmadd.q		s1, s4, s8, a2
+	fmadd.q		s0, s5, s8, a2
+	fmadd.q		s0, s4, s9, a2
+	fmadd.q		s0, s4, s8, a3
+	fnmadd.q	s1, s4, s8, a2
+	fnmadd.q	s0, s5, s8, a2
+	fnmadd.q	s0, s4, s9, a2
+	fnmadd.q	s0, s4, s8, a3
+	fmsub.q		s1, s4, s8, a2
+	fmsub.q		s0, s5, s8, a2
+	fmsub.q		s0, s4, s9, a2
+	fmsub.q		s0, s4, s8, a3
+	fnmsub.q	s1, s4, s8, a2
+	fnmsub.q	s0, s5, s8, a2
+	fnmsub.q	s0, s4, s9, a2
+	fnmsub.q	s0, s4, s8, a3
+
+	fcvt.w.q	a0, s5
+	fcvt.wu.q	a0, s5
+	fcvt.q.w	s1, a0
+	fcvt.q.wu	s1, a0
+
+	fcvt.q.s	s1, a0
+	fcvt.s.q	a0, s5
+
+	fcvt.q.d	s1, a0
+	fcvt.d.q	a0, s5
+
+	.option push
+	.option arch, +zhinxmin
+	fcvt.q.h	s1, a0
+	fcvt.h.q	a0, s5
+	.option pop
+
+	fsgnj.q		s1, s4, s8
+	fsgnjn.q	s0, s5, s8
+	fsgnjx.q	s0, s4, s9
+	feq.q		a0, s5, s8
+	flt.q		a0, s4, s9
+	fle.q		a0, s5, s8
+	fgt.q		a0, s4, s9
+	fge.q		a0, s5, s8
+	fmv.q		s1, s4
+	fmv.q		s0, s5
+	fneg.q		s1, s4
+	fneg.q		s0, s5
+	fabs.q		s1, s4
+	fabs.q		s0, s5
+	fclass.q	a0, s5
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -691,6 +691,19 @@ struct riscv_opcode
 #define INSN_RV32_EVEN_DU	(INSN_RV32_EVEN_D   | INSN_RV32_EVEN_T)
 #define INSN_RV32_EVEN_ST	(INSN_RV32_EVEN_S   | INSN_RV32_EVEN_T)
 
+/* Operands required to be an even-numbered register (pair) in RV64, and one
+   divisible by 4 on RV32.  */
+#define INSN_RV64_EVEN_D	0x00001000
+#define INSN_RV64_EVEN_S	0x00002000
+#define INSN_RV64_EVEN_T	0x00004000 /* Also covering U.  */
+#define INSN_RV64_EVEN_R	0x00008000
+/* Shorthands for combinations of the above.  */
+#define INSN_RV64_EVEN_DS	(INSN_RV64_EVEN_D   | INSN_RV64_EVEN_S)
+#define INSN_RV64_EVEN_DST	(INSN_RV64_EVEN_DS  | INSN_RV64_EVEN_T)
+#define INSN_RV64_EVEN_DSTR	(INSN_RV64_EVEN_DST | INSN_RV64_EVEN_R)
+#define INSN_RV64_EVEN_DU	(INSN_RV64_EVEN_D   | INSN_RV64_EVEN_T)
+#define INSN_RV64_EVEN_ST	(INSN_RV64_EVEN_S   | INSN_RV64_EVEN_T)
+
 /* Instruction is actually a macro.  It should be ignored by the
    disassembler, and requires special treatment by the assembler.  */
 #define INSN_MACRO		0xffffffff
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -1049,6 +1049,25 @@ riscv_disassemble_insn (bfd_vma memaddr,
 		      && (word & (1u << OP_SH_RS3)))
 		    continue;
 		}
+
+	      if (pd->xlen <= 64
+		  && riscv_subset_supports (&pd->riscv_rps_dis, "zqinx"))
+		{
+		  unsigned int mask = pd->xlen == 32 ? 3 : 1;
+
+		  if ((op->pinfo & INSN_RV64_EVEN_D)
+		      && (word & (mask << OP_SH_RD)))
+		    continue;
+		  if ((op->pinfo & INSN_RV64_EVEN_S)
+		      && (word & (mask << OP_SH_RS1)))
+		    continue;
+		  if ((op->pinfo & INSN_RV64_EVEN_T)
+		      && (word & (mask << OP_SH_RS2)))
+		    continue;
+		  if ((op->pinfo & INSN_RV64_EVEN_R)
+		      && (word & (mask << OP_SH_RS3)))
+		    continue;
+		}
 	    }
 
 	  /* It's a match.  */
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -932,10 +932,10 @@ const struct riscv_opcode riscv_opcodes[
 {"fcvt.h.wu",  0, INSN_CLASS_ZFH_INX,  "D,sm",      MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 },
 {"fcvt.s.h",   0, INSN_CLASS_ZFHMIN_INX, "D,S",     MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 },
 {"fcvt.d.h",   0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,S", MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, INSN_RV32_EVEN_D },
-{"fcvt.q.h",   0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 },
+{"fcvt.q.h",   0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,S", MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, INSN_RV64_EVEN_D },
 {"fcvt.h.s",   0, INSN_CLASS_ZFHMIN_INX, "D,Sm",    MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 },
 {"fcvt.h.d",   0, INSN_CLASS_ZFHMIN_AND_D_INX, "D,Sm", MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, INSN_RV32_EVEN_S },
-{"fcvt.h.q",   0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,Sm", MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 },
+{"fcvt.h.q",   0, INSN_CLASS_ZFHMIN_AND_Q_INX, "D,Sm", MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, INSN_RV64_EVEN_S },
 {"fclass.h",   0, INSN_CLASS_ZFH_INX,   "d,S",       MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 },
 {"feq.h",      0, INSN_CLASS_ZFH_INX,   "d,S,T",     MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 },
 {"flt.h",      0, INSN_CLASS_ZFH_INX,   "d,S,T",     MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
@@ -1062,41 +1062,41 @@ const struct riscv_opcode riscv_opcodes[
 {"flq",        0, INSN_CLASS_Q,   "D,A,s",     0, (int) M_FLx, match_rs1_nonzero, INSN_MACRO },
 {"fsq",        0, INSN_CLASS_Q,   "T,q(s)",    MATCH_FSQ, MASK_FSQ, match_opcode, INSN_DREF|INSN_16_BYTE },
 {"fsq",        0, INSN_CLASS_Q,   "T,A,s",     0, (int) M_Sx_FSx, match_rs1_nonzero, INSN_MACRO },
-{"fmv.q",      0, INSN_CLASS_Q_INX,   "D,U",       MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS },
-{"fneg.q",     0, INSN_CLASS_Q_INX,   "D,U",       MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS },
-{"fabs.q",     0, INSN_CLASS_Q_INX,   "D,U",       MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS },
-{"fsgnj.q",    0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, 0 },
-{"fsgnjn.q",   0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, 0 },
-{"fsgnjx.q",   0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, 0 },
-{"fadd.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FADD_Q, MASK_FADD_Q, match_opcode, 0 },
-{"fsub.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, 0 },
-{"fmul.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, 0 },
-{"fdiv.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, 0 },
-{"fsqrt.q",    0, INSN_CLASS_Q_INX,   "D,Sm",      MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, 0 },
-{"fmin.q",     0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, 0 },
-{"fmax.q",     0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, 0 },
-{"fmadd.q",    0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, 0 },
-{"fnmadd.q",   0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, 0 },
-{"fmsub.q",    0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, 0 },
-{"fnmsub.q",   0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, 0 },
-{"fcvt.w.q",   0, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, 0 },
-{"fcvt.wu.q",  0, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, 0 },
-{"fcvt.q.w",   0, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, 0 },
-{"fcvt.q.wu",  0, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, 0 },
-{"fcvt.q.s",   0, INSN_CLASS_Q_INX,   "D,S",       MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, 0 },
-{"fcvt.q.d",   0, INSN_CLASS_Q_INX,   "D,S",       MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, 0 },
-{"fcvt.s.q",   0, INSN_CLASS_Q_INX,   "D,Sm",      MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, 0 },
-{"fcvt.d.q",   0, INSN_CLASS_Q_INX,   "D,Sm",      MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, 0 },
-{"fclass.q",   0, INSN_CLASS_Q_INX,   "d,S",       MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, 0 },
-{"feq.q",      0, INSN_CLASS_Q_INX,   "d,S,T",     MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, 0 },
-{"flt.q",      0, INSN_CLASS_Q_INX,   "d,S,T",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, 0 },
-{"fle.q",      0, INSN_CLASS_Q_INX,   "d,S,T",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, 0 },
-{"fgt.q",      0, INSN_CLASS_Q_INX,   "d,T,S",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_ALIAS },
-{"fge.q",      0, INSN_CLASS_Q_INX,   "d,T,S",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_ALIAS },
-{"fcvt.l.q",  64, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, 0 },
-{"fcvt.lu.q", 64, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, 0 },
-{"fcvt.q.l",  64, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
-{"fcvt.q.lu", 64, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 },
+{"fmv.q",      0, INSN_CLASS_Q_INX,   "D,U",       MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_RV64_EVEN_DU },
+{"fneg.q",     0, INSN_CLASS_Q_INX,   "D,U",       MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_RV64_EVEN_DU },
+{"fabs.q",     0, INSN_CLASS_Q_INX,   "D,U",       MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_rs1_eq_rs2, INSN_ALIAS|INSN_RV64_EVEN_DU },
+{"fsgnj.q",    0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FSGNJ_Q, MASK_FSGNJ_Q, match_opcode, INSN_RV64_EVEN_DST },
+{"fsgnjn.q",   0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FSGNJN_Q, MASK_FSGNJN_Q, match_opcode, INSN_RV64_EVEN_DST },
+{"fsgnjx.q",   0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FSGNJX_Q, MASK_FSGNJX_Q, match_opcode, INSN_RV64_EVEN_DST },
+{"fadd.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FADD_Q, MASK_FADD_Q, match_opcode, INSN_RV64_EVEN_DST },
+{"fsub.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FSUB_Q, MASK_FSUB_Q, match_opcode, INSN_RV64_EVEN_DST },
+{"fmul.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FMUL_Q, MASK_FMUL_Q, match_opcode, INSN_RV64_EVEN_DST },
+{"fdiv.q",     0, INSN_CLASS_Q_INX,   "D,S,Tm",    MATCH_FDIV_Q, MASK_FDIV_Q, match_opcode, INSN_RV64_EVEN_DST },
+{"fsqrt.q",    0, INSN_CLASS_Q_INX,   "D,Sm",      MATCH_FSQRT_Q, MASK_FSQRT_Q, match_opcode, INSN_RV64_EVEN_DS },
+{"fmin.q",     0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FMIN_Q, MASK_FMIN_Q, match_opcode, INSN_RV64_EVEN_DST },
+{"fmax.q",     0, INSN_CLASS_Q_INX,   "D,S,T",     MATCH_FMAX_Q, MASK_FMAX_Q, match_opcode, INSN_RV64_EVEN_DST },
+{"fmadd.q",    0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FMADD_Q, MASK_FMADD_Q, match_opcode, INSN_RV64_EVEN_DSTR },
+{"fnmadd.q",   0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FNMADD_Q, MASK_FNMADD_Q, match_opcode, INSN_RV64_EVEN_DSTR },
+{"fmsub.q",    0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FMSUB_Q, MASK_FMSUB_Q, match_opcode, INSN_RV64_EVEN_DSTR },
+{"fnmsub.q",   0, INSN_CLASS_Q_INX,   "D,S,T,Rm",  MATCH_FNMSUB_Q, MASK_FNMSUB_Q, match_opcode, INSN_RV64_EVEN_DSTR },
+{"fcvt.w.q",   0, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_W_Q, MASK_FCVT_W_Q, match_opcode, INSN_RV64_EVEN_S },
+{"fcvt.wu.q",  0, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q, match_opcode, INSN_RV64_EVEN_S },
+{"fcvt.q.w",   0, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_W, MASK_FCVT_Q_W|MASK_RM, match_opcode, INSN_RV64_EVEN_D },
+{"fcvt.q.wu",  0, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU|MASK_RM, match_opcode, INSN_RV64_EVEN_D },
+{"fcvt.q.s",   0, INSN_CLASS_Q_INX,   "D,S",       MATCH_FCVT_Q_S, MASK_FCVT_Q_S|MASK_RM, match_opcode, INSN_RV64_EVEN_D },
+{"fcvt.q.d",   0, INSN_CLASS_Q_INX,   "D,S",       MATCH_FCVT_Q_D, MASK_FCVT_Q_D|MASK_RM, match_opcode, INSN_RV64_EVEN_D|INSN_RV32_EVEN_S },
+{"fcvt.s.q",   0, INSN_CLASS_Q_INX,   "D,Sm",      MATCH_FCVT_S_Q, MASK_FCVT_S_Q, match_opcode, INSN_RV64_EVEN_S },
+{"fcvt.d.q",   0, INSN_CLASS_Q_INX,   "D,Sm",      MATCH_FCVT_D_Q, MASK_FCVT_D_Q, match_opcode, INSN_RV32_EVEN_D|INSN_RV64_EVEN_S },
+{"fclass.q",   0, INSN_CLASS_Q_INX,   "d,S",       MATCH_FCLASS_Q, MASK_FCLASS_Q, match_opcode, INSN_RV64_EVEN_S },
+{"feq.q",      0, INSN_CLASS_Q_INX,   "d,S,T",     MATCH_FEQ_Q, MASK_FEQ_Q, match_opcode, INSN_RV64_EVEN_ST },
+{"flt.q",      0, INSN_CLASS_Q_INX,   "d,S,T",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_RV64_EVEN_ST },
+{"fle.q",      0, INSN_CLASS_Q_INX,   "d,S,T",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_RV64_EVEN_ST },
+{"fgt.q",      0, INSN_CLASS_Q_INX,   "d,T,S",     MATCH_FLT_Q, MASK_FLT_Q, match_opcode, INSN_ALIAS|INSN_RV64_EVEN_ST },
+{"fge.q",      0, INSN_CLASS_Q_INX,   "d,T,S",     MATCH_FLE_Q, MASK_FLE_Q, match_opcode, INSN_ALIAS|INSN_RV64_EVEN_ST },
+{"fcvt.l.q",  64, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_L_Q, MASK_FCVT_L_Q, match_opcode, INSN_RV64_EVEN_S },
+{"fcvt.lu.q", 64, INSN_CLASS_Q_INX,   "d,Sm",      MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q, match_opcode, INSN_RV64_EVEN_S },
+{"fcvt.q.l",  64, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_L, MASK_FCVT_Q_L|MASK_RM, match_opcode, INSN_RV64_EVEN_D },
+{"fcvt.q.lu", 64, INSN_CLASS_Q_INX,   "D,s",       MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU|MASK_RM, match_opcode, INSN_RV64_EVEN_D },
 
 /* Compressed instructions.  */
 {"c.unimp",    0, INSN_CLASS_ZCA,   "",          0, 0xffffU,  match_opcode, 0 },


From jbeulich@suse.com  Fri Jun 19 11:51:36 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 19 Jun 2026 13:51:36 +0200
Subject: [PATCH v3 09/13] RISC-V/gas: .attribute vs .insn
In-Reply-To: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
Message-ID: <e834db1a-ee9e-4d7f-ac10-592e56559b33@suse.com>

"... before any instruction", as the diagnostic from s_riscv_attribute()
says, presumably ought to include also insns resulting from .insn. Make a
small helper function.

Reviewed-by: Jiawei <jiawei@iscas.ac.cn>
---
RFC: I can't quite figure why this constraint exists, so there may also be
     the option of relaxing things (up to fully dropping start_assemble).
---
v2: Style correction.

--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -4415,6 +4415,18 @@ riscv_ip_hardcode (char *str,
   return NULL;
 }
 
+/* The architecture and privileged elf attributes should be set before
+   assembling.  */
+static bool
+start_assembly (void)
+{
+  start_assemble = true;
+
+  riscv_set_abi_by_arch ();
+
+  return riscv_set_default_priv_spec (NULL);
+}
+
 void
 md_assemble (char *str)
 {
@@ -4422,16 +4434,8 @@ md_assemble (char *str)
   expressionS imm_expr;
   bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
 
-  /* The architecture and privileged elf attributes should be set
-     before assembling.  */
-  if (!start_assemble)
-    {
-      start_assemble = true;
-
-      riscv_set_abi_by_arch ();
-      if (!riscv_set_default_priv_spec (NULL))
-       return;
-    }
+  if (!start_assemble && !start_assembly())
+    return;
 
   riscv_mapping_state (MAP_INSN, 0, false/* fr_align_code */);
 
@@ -5640,6 +5644,9 @@ s_riscv_insn (int x ATTRIBUTE_UNUSED)
   bfd_reloc_code_real_type imm_reloc = BFD_RELOC_UNUSED;
   char save_c;
 
+  if (!start_assemble && !start_assembly())
+    return;
+
   while (!is_end_of_stmt (*input_line_pointer))
     ++input_line_pointer;
 


From jbeulich@suse.com  Fri Jun 19 11:51:59 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 19 Jun 2026 13:51:59 +0200
Subject: [PATCH v3 10/13] RISC-V/gas: warn about non-boolean unaligned-access
 attribute
In-Reply-To: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
Message-ID: <d26d357f-dbcb-4aa1-a193-2dd61bb9f40a@suse.com>

The attribute being a boolean one, values should be solely 0 or 1.

Reviewed-by: Jiawei <jiawei@iscas.ac.cn>
---
Shouldn't settings accumulate, much like what riscv_merge_attributes()
does?
---
v2: New.

--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -5870,14 +5870,13 @@ s_riscv_attribute (int ignored ATTRIBUTE
 {
   obj_attr_tag_t tag = obj_attr_process_attribute (OBJ_ATTR_PROC);
   unsigned old_xlen;
-  obj_attribute *attr;
+  const obj_attribute *attr = elf_known_obj_attributes_proc (stdoutput);
 
   explicit_attr = true;
   switch (tag)
     {
     case Tag_RISCV_arch:
       old_xlen = xlen;
-      attr = elf_known_obj_attributes_proc (stdoutput);
       if (!start_assemble)
 	riscv_set_arch (attr[Tag_RISCV_arch].s);
       else
@@ -5903,6 +5902,11 @@ s_riscv_attribute (int ignored ATTRIBUTE
 		   "any instructions"));
       break;
 
+    case Tag_RISCV_unaligned_access:
+      if (attr[Tag_RISCV_unaligned_access].i > 1)
+	as_warn (_("`unaligned_access' attribute with non-boolean value"));
+      break;
+
     default:
       break;
     }
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-warn.d
@@ -0,0 +1,7 @@
+#as: -march-attr
+#readelf: -A
+#warning_output: attribute-warn.l
+
+Attribute Section: riscv
+File Attributes
+  Tag_RISCV_arch: [a-zA-Z0-9_\"].*
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-warn.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*:2: Warning: `unaligned_access' attribute with non-boolean value
--- /dev/null
+++ b/gas/testsuite/gas/riscv/attribute-warn.s
@@ -0,0 +1,3 @@
+	.attribute unaligned_access, 1
+	.attribute unaligned_access, 0x1234
+	.attribute unaligned_access, 0


From jbeulich@suse.com  Fri Jun 19 11:52:18 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 19 Jun 2026 13:52:18 +0200
Subject: [PATCH v3 11/13] RISC-V/gas: warn about non-power-of-2 stack-align
 attribute
In-Reply-To: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
Message-ID: <70bdd397-4326-4c00-841b-7e4a57c82919@suse.com>

Only power-of-2 values are sensible for alignment.

Reviewed-by: Jiawei <jiawei@iscas.ac.cn>
---
Should we reject changing an already set non-zero value, like
riscv_merge_attributes() does?

Should we permit 0 as an explicit indication of "attribute not set"?
---
v2: New.

--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -5902,6 +5902,13 @@ s_riscv_attribute (int ignored ATTRIBUTE
 		   "any instructions"));
       break;
 
+    case Tag_RISCV_stack_align:
+      if (!attr[Tag_RISCV_stack_align].i
+	  || (attr[Tag_RISCV_stack_align].i &
+	      (attr[Tag_RISCV_stack_align].i - 1)))
+	as_warn (_("`stack_align' attribute with non-power-of-2 value"));
+      break;
+
     case Tag_RISCV_unaligned_access:
       if (attr[Tag_RISCV_unaligned_access].i > 1)
 	as_warn (_("`unaligned_access' attribute with non-boolean value"));
--- a/gas/testsuite/gas/riscv/attribute-warn.d
+++ b/gas/testsuite/gas/riscv/attribute-warn.d
@@ -4,4 +4,5 @@
 
 Attribute Section: riscv
 File Attributes
+  Tag_RISCV_stack_align: 65536-bytes
   Tag_RISCV_arch: [a-zA-Z0-9_\"].*
--- a/gas/testsuite/gas/riscv/attribute-warn.l
+++ b/gas/testsuite/gas/riscv/attribute-warn.l
@@ -1,2 +1,4 @@
 .*: Assembler messages:
 .*:2: Warning: `unaligned_access' attribute with non-boolean value
+.*:5: Warning: `stack_align' attribute with non-power-of-2 value
+.*:6: Warning: `stack_align' attribute with non-power-of-2 value
--- a/gas/testsuite/gas/riscv/attribute-warn.s
+++ b/gas/testsuite/gas/riscv/attribute-warn.s
@@ -1,3 +1,7 @@
 	.attribute unaligned_access, 1
 	.attribute unaligned_access, 0x1234
 	.attribute unaligned_access, 0
+
+	.attribute stack_align, 0
+	.attribute stack_align, 0x4444
+	.attribute stack_align, 0x10000


From jbeulich@suse.com  Fri Jun 19 11:52:40 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 19 Jun 2026 13:52:40 +0200
Subject: [PATCH v3 12/13] RISC-V/bfd: warn about non-boolean unaligned-access
 attribute
In-Reply-To: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
Message-ID: <3ecb6e90-f46f-46de-ba79-f4188e25e58f@suse.com>

The attribute being a boolean one, incoming values should be solely 0 or
1. Convert other non-zero values to 1.
---
v3: New.

--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -3777,6 +3777,23 @@ riscv_merge_attributes (bfd *ibfd, struc
 	 initialized.  */
       out_attr[0].i = 1;
 
+      for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
+	{
+	  switch (i)
+	    {
+	    case Tag_RISCV_unaligned_access:
+	      if (out_attr[i].i <= 1)
+		break;
+
+	      _bfd_error_handler
+		(_("warning: %pB uses non-boolean `unaligned access' attribute; "
+		   "converting to boolean"),
+		 ibfd);
+	      out_attr[i].i = 1;
+	      break;
+	    }
+	}
+
       return true;
     }
 
@@ -3865,7 +3882,12 @@ riscv_merge_attributes (bfd *ibfd, struc
 	break;
 
       case Tag_RISCV_unaligned_access:
-	out_attr[i].i |= in_attr[i].i;
+	if (in_attr[i].i > 1)
+	  _bfd_error_handler
+	    (_("warning: %pB uses non-boolean `unaligned access' attribute; "
+	       "converting to boolean"),
+	     ibfd);
+	out_attr[i].i |= !!in_attr[i].i;
 	break;
 
       case Tag_RISCV_stack_align:


From jbeulich@suse.com  Fri Jun 19 11:53:18 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 19 Jun 2026 13:53:18 +0200
Subject: [PATCH v3 13/13] RISC-V/bfd: warn about non-power-of-2 stack-align
 attribute
In-Reply-To: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
Message-ID: <2fcf62ca-0e51-48fc-a9cf-7a48a40dc82e@suse.com>

Only power-of-2 values are sensible for alignment. Reject other values.

While there also drop a redundant part of a related conditional.
---
v3: New.

--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -3791,6 +3791,17 @@ riscv_merge_attributes (bfd *ibfd, struc
 		 ibfd);
 	      out_attr[i].i = 1;
 	      break;
+
+	    case Tag_RISCV_stack_align:
+	      if (!(out_attr[i].i & (out_attr[i].i - 1)))
+		break;
+
+	      _bfd_error_handler
+		(_("warning: %pB uses non-power-of-2 `stack align' attribute; "
+		   "ignoring"),
+		 ibfd);
+	      out_attr[i].i = 0;
+	      break;
 	    }
 	}
 
@@ -3891,10 +3902,14 @@ riscv_merge_attributes (bfd *ibfd, struc
 	break;
 
       case Tag_RISCV_stack_align:
-	if (out_attr[i].i == 0)
+	if ((in_attr[i].i & (in_attr[i].i - 1)) != 0)
+	  _bfd_error_handler
+	    (_("warning: %pB uses non-power-of-2 `stack align' attribute; "
+	       "ignoring"),
+	     ibfd);
+	else if (out_attr[i].i == 0)
 	  out_attr[i].i = in_attr[i].i;
 	else if (in_attr[i].i != 0
-		 && out_attr[i].i != 0
 		 && out_attr[i].i != in_attr[i].i)
 	  {
 	    _bfd_error_handler


From jbeulich@suse.com  Fri Jun 19 13:01:41 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 19 Jun 2026 15:01:41 +0200
Subject: [PATCH v2] elf: Set text-segment address to the maximum page size
In-Reply-To: <CAMe9rOo5sxQ6x0jdD9JPXunmDt3rywckofJjPKgwXwUqsU-=GQ@mail.gmail.com>
References: <CAMe9rOo5sxQ6x0jdD9JPXunmDt3rywckofJjPKgwXwUqsU-=GQ@mail.gmail.com>
Message-ID: <eed00d94-f8eb-421e-973b-a9e35e00e68e@suse.com>

On 28.05.2026 09:16, H.J. Lu wrote:
> On Thu, May 28, 2026 at 11:08?AM H.J. Lu <hjl.tools@gmail.com> wrote:
>>
>> When generating Position Dependent Executable for ELF with the maximum
>> page size set on command-line, if text-segment address is lower than the
>> maximum page size, set text-segment address to the maximum page size.
>>
>> PR ld/34184
>> * ldexp.c (fold_binary): Set text-segment address to the maximum
>> page size for ELF PDE output with -z max-page-size=SIZE.
>> * testsuite/ld-elf/elf.exp: Add ld/34184 test.
>> * testsuite/ld-elf/pr34184.c: New file.
> 
> Here is the v2 patch to add tests for PIE, static PDE and static PIE.

Why is this special to text-segment? Doesn't something like this need
doing either for all segments, or for whatever is the first segment?

Jan

From jon.turney@dronecode.org.uk  Fri Jun 19 13:43:39 2026
From: jon.turney@dronecode.org.uk (Jon Turney)
Date: Fri, 19 Jun 2026 14:43:39 +0100
Subject: [PATCH] objdump: Fix private header ('-p') import table output for
 pe-aarch64
Message-ID: <20260619134339.73604-1-jon.turney@dronecode.org.uk>

The private header ('-p') import table output for pe-aarch64 (and
probably all other 64-bit arches apart from x86_64) is truncated after the
first import.

The distinction between the conditional branches here should be between
PE32 (32-bit) and PE32+ (somewhat confusingly, the 64-bit version of the
PE format).

PE file format specification [1] states under "Import Lookup Table":

"An import lookup table is an array of 32-bit numbers for PE32 or an
array of 64-bit numbers for PE32+."

[1] https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#import-lookup-table

2026-06-19  Jon Turney  <jon.turney@dronecode.org.uk>

	* peXXigen.c (pe_print_idata): Fix conditional.
---
 bfd/peXXigen.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/bfd/peXXigen.c b/bfd/peXXigen.c
index bdb23dcbcab..c946557f3a0 100644
--- a/bfd/peXXigen.c
+++ b/bfd/peXXigen.c
@@ -1462,7 +1462,7 @@ pe_print_idata (bfd * abfd, void * vfile)
 	    }
 
 	  /* Print HintName vector entries.  */
-#ifdef COFF_WITH_pex64
+#if defined COFF_WITH_pep || defined COFF_WITH_pex64 || defined COFF_WITH_peAArch64 || defined COFF_WITH_peLoongArch64 || defined COFF_WITH_peRiscV64
 	  for (j = 0; idx + j + 8 <= datasize; j += 8)
 	    {
 	      bfd_size_type amt;
-- 
2.51.0


From Richard.Earnshaw@arm.com  Fri Jun 19 15:38:48 2026
From: Richard.Earnshaw@arm.com (Richard Earnshaw (foss))
Date: Fri, 19 Jun 2026 16:38:48 +0100
Subject: [PATCH v4] gas: arm: Support CPU-specific extensions with -mcpu
In-Reply-To: <20260618195504.620749-1-sivan.shani@arm.com>
References: <20260618195504.620749-1-sivan.shani@arm.com>
Message-ID: <72792b9e-ec6f-49aa-bbaa-fbcc0d13d990@arm.com>

On 18/06/2026 20:55, Sivan Shani wrote:
> Previously, +ext/+noext feature modifiers were only available with
> -march. Extend the same mechanism to -mcpu so that CPU-specific
> extensions can be enabled and disabled with -mcpu=<cpu>+ext and
> -mcpu=<cpu>+noext, matching GCC behaviour.
> 
> Add a per-CPU extension table (arm_ext_table) and a new ext_table
> field to struct arm_cpu_option_table, reusing the existing
> arm_parse_extension () infrastructure used by -march. Move the
> ARM_EXT/ARM_ADD/ARM_REMOVE helpers, the ALL_FP/ALL_SIMD/ALL_FP_MVE_FP
> masks and the CDE_EXTENSIONS list so they can be shared by both
> -mcpu and -march extension tables.
> 
> Update ARM CPU feature definitions to match GCC CPU baselines. The
> default feature set for each -mcpu remains unchanged; only support for
> +ext/+noext modifiers is added.
> 
> Add tests covering supported CPU extension modifiers and the resulting
> build attributes for each CPU.
> 
> gas/
>     * config/tc-arm.c (struct arm_cpu_option_table): Add ext_table
>     field.
>     (ARM_EXT, ARM_ADD, ARM_REMOVE, ALL_FP, ALL_SIMD,
>     ALL_FP_MVE_FP, CDE_EXTENSIONS): Move earlier.
>     (cortex_*_ext_table, ...): New.
>     (arm_cpus): Populate ext_table and update CPU feature baselines
>     to match GCC.
>     (arm_parse_cpu): Pass opt->ext_table to arm_parse_extension.
> 
> gas/testsuite/
>     * gas/arm/feat-*.s: New test sources.
>     * gas/arm/mcpu-*.d: New tests.
>     * gas/arm/attr-cpu-directive.d: Update.

Thanks,

Pushed.

R.> 
> ###
> This version address the review comments from:
> Message-ID: <2846ac09-3590-409d-8ecf-cc385c8929e8@arm.com>
> https://inbox.sourceware.org/binutils/2846ac09-3590-409d-8ecf-cc385c8929e8@arm.com/
> ###
> 
> ---
>  gas/config/tc-arm.c                           | 699 ++++++++++++++----
>  gas/testsuite/gas/arm/attr-cpu-directive.d    |   2 +
>  gas/testsuite/gas/arm/feat-bf16.s             |   5 +
>  gas/testsuite/gas/arm/feat-crc.s              |   4 +
>  gas/testsuite/gas/arm/feat-dotprod.s          |   4 +
>  gas/testsuite/gas/arm/feat-dsp.s              |   4 +
>  gas/testsuite/gas/arm/feat-fp-vfpv3.s         |   4 +
>  gas/testsuite/gas/arm/feat-fp-vfpv5.s         |   4 +
>  gas/testsuite/gas/arm/feat-fp.dp.s            |   4 +
>  gas/testsuite/gas/arm/feat-fp.s               |   4 +
>  gas/testsuite/gas/arm/feat-fp16.s             |   4 +
>  gas/testsuite/gas/arm/feat-i8mm.s             |   4 +
>  gas/testsuite/gas/arm/feat-idiv.s             |   3 +
>  gas/testsuite/gas/arm/feat-mp.s               |   4 +
>  gas/testsuite/gas/arm/feat-mve.fp.s           |   5 +
>  gas/testsuite/gas/arm/feat-neon-fp16.s        |   4 +
>  gas/testsuite/gas/arm/feat-pacbti.s           |   4 +
>  gas/testsuite/gas/arm/feat-sec.s              |   4 +
>  gas/testsuite/gas/arm/feat-simd.s             |   5 +
>  gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s   |   4 +
>  gas/testsuite/gas/arm/mcpu-cortex-a12-attrs.d |  17 +
>  .../gas/arm/mcpu-cortex-a12-feat-simd.d       |  19 +
>  gas/testsuite/gas/arm/mcpu-cortex-a15-attrs.d |  17 +
>  .../gas/arm/mcpu-cortex-a15-feat-simd.d       |  19 +
>  gas/testsuite/gas/arm/mcpu-cortex-a17-attrs.d |  17 +
>  .../gas/arm/mcpu-cortex-a17-feat-simd.d       |  19 +
>  gas/testsuite/gas/arm/mcpu-cortex-a32-attrs.d |  16 +
>  .../gas/arm/mcpu-cortex-a32-attrs1.d          |  18 +
>  .../gas/arm/mcpu-cortex-a32-feat-crc.d        |  18 +
>  .../gas/arm/mcpu-cortex-a32-feat-simd.d       |  18 +
>  gas/testsuite/gas/arm/mcpu-cortex-a35-attrs.d |  16 +
>  .../gas/arm/mcpu-cortex-a35-attrs1.d          |  18 +
>  .../gas/arm/mcpu-cortex-a35-feat-crc.d        |  18 +
>  .../gas/arm/mcpu-cortex-a35-feat-simd.d       |  18 +
>  gas/testsuite/gas/arm/mcpu-cortex-a5-attrs.d  |  16 +
>  .../gas/arm/mcpu-cortex-a5-feat-mp.d          |  18 +
>  .../gas/arm/mcpu-cortex-a5-feat-neon-fp16.d   |  18 +
>  .../gas/arm/mcpu-cortex-a5-feat-sec.d         |  18 +
>  gas/testsuite/gas/arm/mcpu-cortex-a53-attrs.d |  16 +
>  .../gas/arm/mcpu-cortex-a53-attrs1.d          |  18 +
>  .../gas/arm/mcpu-cortex-a53-feat-crc.d        |  18 +
>  .../gas/arm/mcpu-cortex-a53-feat-simd.d       |  18 +
>  gas/testsuite/gas/arm/mcpu-cortex-a55-attrs.d |  17 +
>  .../gas/arm/mcpu-cortex-a55-attrs1.d          |  18 +
>  .../gas/arm/mcpu-cortex-a55-feat-dotprod.d    |  18 +
>  .../gas/arm/mcpu-cortex-a55-feat-fp16.d       |  18 +
>  gas/testsuite/gas/arm/mcpu-cortex-a57-attrs.d |  18 +
>  .../gas/arm/mcpu-cortex-a57-feat-crc.d        |  18 +
>  .../gas/arm/mcpu-cortex-a57-feat-simd.d       |  18 +
>  gas/testsuite/gas/arm/mcpu-cortex-a7-attrs.d  |  17 +
>  .../gas/arm/mcpu-cortex-a7-feat-simd.d        |  19 +
>  .../gas/arm/mcpu-cortex-a710-attrs.d          |  18 +
>  .../gas/arm/mcpu-cortex-a710-feat-bf16.d      |  18 +
>  .../gas/arm/mcpu-cortex-a710-feat-fp16.d      |  18 +
>  .../gas/arm/mcpu-cortex-a710-feat-i8mm.d      |  18 +
>  gas/testsuite/gas/arm/mcpu-cortex-a72-attrs.d |  18 +
>  .../gas/arm/mcpu-cortex-a72-feat-crc.d        |  18 +
>  .../gas/arm/mcpu-cortex-a72-feat-simd.d       |  18 +
>  gas/testsuite/gas/arm/mcpu-cortex-a73-attrs.d |  18 +
>  .../gas/arm/mcpu-cortex-a73-feat-crc.d        |  18 +
>  .../gas/arm/mcpu-cortex-a73-feat-simd.d       |  18 +
>  gas/testsuite/gas/arm/mcpu-cortex-a75-attrs.d |  18 +
>  .../gas/arm/mcpu-cortex-a75-feat-dotprod.d    |  18 +
>  .../gas/arm/mcpu-cortex-a75-feat-fp16.d       |  18 +
>  gas/testsuite/gas/arm/mcpu-cortex-a76-attrs.d |  18 +
>  .../gas/arm/mcpu-cortex-a76-feat-dotprod.d    |  18 +
>  .../gas/arm/mcpu-cortex-a76-feat-fp16.d       |  18 +
>  .../gas/arm/mcpu-cortex-a76ae-attrs.d         |  18 +
>  .../gas/arm/mcpu-cortex-a76ae-feat-dotprod.d  |  18 +
>  .../gas/arm/mcpu-cortex-a76ae-feat-fp16.d     |  18 +
>  gas/testsuite/gas/arm/mcpu-cortex-a77-attrs.d |  18 +
>  .../gas/arm/mcpu-cortex-a77-feat-dotprod.d    |  18 +
>  .../gas/arm/mcpu-cortex-a77-feat-fp16.d       |  18 +
>  gas/testsuite/gas/arm/mcpu-cortex-a78-attrs.d |  18 +
>  .../gas/arm/mcpu-cortex-a78-feat-dotprod.d    |  18 +
>  .../gas/arm/mcpu-cortex-a78-feat-fp16.d       |  18 +
>  .../gas/arm/mcpu-cortex-a78ae-attrs.d         |  18 +
>  .../gas/arm/mcpu-cortex-a78ae-feat-dotprod.d  |  18 +
>  .../gas/arm/mcpu-cortex-a78ae-feat-fp16.d     |  18 +
>  .../gas/arm/mcpu-cortex-a78c-attrs.d          |  18 +
>  .../gas/arm/mcpu-cortex-a78c-feat-dotprod.d   |  18 +
>  .../gas/arm/mcpu-cortex-a78c-feat-fp16.d      |  18 +
>  gas/testsuite/gas/arm/mcpu-cortex-a8-attrs.d  |  15 +
>  .../gas/arm/mcpu-cortex-a8-feat-simd.d        |  17 +
>  gas/testsuite/gas/arm/mcpu-cortex-a9-attrs.d  |  16 +
>  .../gas/arm/mcpu-cortex-a9-feat-mp.d          |  18 +
>  .../gas/arm/mcpu-cortex-a9-feat-neon-fp16.d   |  18 +
>  .../gas/arm/mcpu-cortex-a9-feat-sec.d         |  18 +
>  gas/testsuite/gas/arm/mcpu-cortex-m33-attrs.d |  13 +
>  .../gas/arm/mcpu-cortex-m33-feat-dsp.d        |  15 +
>  .../gas/arm/mcpu-cortex-m33-feat-fp-vfpv5.d   |  15 +
>  .../gas/arm/mcpu-cortex-m35p-attrs.d          |  13 +
>  .../gas/arm/mcpu-cortex-m35p-feat-dsp.d       |  15 +
>  .../gas/arm/mcpu-cortex-m35p-feat-fp-vfpv5.d  |  15 +
>  gas/testsuite/gas/arm/mcpu-cortex-m4-attrs.d  |  13 +
>  .../gas/arm/mcpu-cortex-m4-feat-fp-vfpv3.d    |  15 +
>  gas/testsuite/gas/arm/mcpu-cortex-m52-attrs.d |  14 +
>  .../gas/arm/mcpu-cortex-m52-attrs1.d          |  16 +
>  .../gas/arm/mcpu-cortex-m52-feat-fp-dp.d      |  16 +
>  .../gas/arm/mcpu-cortex-m52-feat-mve-fp.d     |  16 +
>  .../gas/arm/mcpu-cortex-m52-feat-pacbti.d     |  16 +
>  gas/testsuite/gas/arm/mcpu-cortex-m55-attrs.d |  14 +
>  .../gas/arm/mcpu-cortex-m55-attrs1.d          |  16 +
>  .../gas/arm/mcpu-cortex-m55-feat-fp-dp.d      |  16 +
>  .../gas/arm/mcpu-cortex-m55-feat-mve-fp.d     |  16 +
>  gas/testsuite/gas/arm/mcpu-cortex-m7-attrs.d  |  13 +
>  .../gas/arm/mcpu-cortex-m7-feat-fp-dp.d       |  14 +
>  gas/testsuite/gas/arm/mcpu-cortex-m85-attrs.d |  14 +
>  .../gas/arm/mcpu-cortex-m85-feat-fp-dp.d      |  16 +
>  .../gas/arm/mcpu-cortex-m85-feat-mve-fp.d     |  16 +
>  .../gas/arm/mcpu-cortex-m85-feat-pacbti.d     |  16 +
>  .../gas/arm/mcpu-cortex-r4f-feat-fp-vfpv3.d   |  15 +
>  gas/testsuite/gas/arm/mcpu-cortex-r5-attrs.d  |  15 +
>  .../gas/arm/mcpu-cortex-r5-feat-fp-vfpv3.d    |  16 +
>  .../gas/arm/mcpu-cortex-r5-feat-idiv.d        |  16 +
>  gas/testsuite/gas/arm/mcpu-cortex-r52-attrs.d |  17 +
>  .../gas/arm/mcpu-cortex-r52-feat-crc.d        |  18 +
>  .../gas/arm/mcpu-cortex-r52-feat-simd.d       |  18 +
>  .../gas/arm/mcpu-cortex-r52plus-attrs.d       |  17 +
>  .../gas/arm/mcpu-cortex-r52plus-feat-crc.d    |  18 +
>  .../gas/arm/mcpu-cortex-r52plus-feat-simd.d   |  18 +
>  gas/testsuite/gas/arm/mcpu-cortex-r7-attrs.d  |  15 +
>  .../gas/arm/mcpu-cortex-r7-feat-idiv.d        |  17 +
>  .../arm/mcpu-cortex-r7-feat-vfpv3-d16-fp16.d  |  17 +
>  gas/testsuite/gas/arm/mcpu-cortex-r8-attrs.d  |  15 +
>  .../gas/arm/mcpu-cortex-r8-feat-idiv.d        |  17 +
>  .../arm/mcpu-cortex-r8-feat-vfpv3-d16-fp16.d  |  17 +
>  gas/testsuite/gas/arm/mcpu-cortex-x1-attrs.d  |  18 +
>  .../gas/arm/mcpu-cortex-x1-feat-dotprod.d     |  18 +
>  .../gas/arm/mcpu-cortex-x1-feat-fp16.d        |  18 +
>  gas/testsuite/gas/arm/mcpu-cortex-x1c-attrs.d |  18 +
>  .../gas/arm/mcpu-cortex-x1c-feat-dotprod.d    |  18 +
>  .../gas/arm/mcpu-cortex-x1c-feat-fp16.d       |  18 +
>  gas/testsuite/gas/arm/mcpu-exynos-m1-attrs.d  |  18 +
>  .../gas/arm/mcpu-exynos-m1-feat-crc.d         |  18 +
>  .../gas/arm/mcpu-exynos-m1-feat-simd.d        |  18 +
>  .../gas/arm/mcpu-marvell-pj4-feat-fp-vfpv3.d  |  17 +
>  .../gas/arm/mcpu-marvell-pj4-feat-mp.d        |  17 +
>  .../gas/arm/mcpu-marvell-pj4-feat-sec.d       |  17 +
>  .../gas/arm/mcpu-neoverse-n1-attrs.d          |  18 +
>  .../gas/arm/mcpu-neoverse-n1-feat-dotprod.d   |  18 +
>  .../gas/arm/mcpu-neoverse-n1-feat-fp16.d      |  18 +
>  .../gas/arm/mcpu-neoverse-n2-attrs.d          |  18 +
>  .../gas/arm/mcpu-neoverse-n2-feat-bf16.d      |  18 +
>  .../gas/arm/mcpu-neoverse-n2-feat-fp16.d      |  18 +
>  .../gas/arm/mcpu-neoverse-n2-feat-i8mm.d      |  18 +
>  .../gas/arm/mcpu-neoverse-v1-attrs.d          |  18 +
>  .../gas/arm/mcpu-neoverse-v1-feat-bf16.d      |  18 +
>  .../gas/arm/mcpu-neoverse-v1-feat-fp16.d      |  18 +
>  .../gas/arm/mcpu-neoverse-v1-feat-i8mm.d      |  18 +
>  gas/testsuite/gas/arm/mcpu-xgene1-feat-simd.d |  18 +
>  151 files changed, 2867 insertions(+), 155 deletions(-)
>  create mode 100644 gas/testsuite/gas/arm/feat-bf16.s
>  create mode 100644 gas/testsuite/gas/arm/feat-crc.s
>  create mode 100644 gas/testsuite/gas/arm/feat-dotprod.s
>  create mode 100644 gas/testsuite/gas/arm/feat-dsp.s
>  create mode 100644 gas/testsuite/gas/arm/feat-fp-vfpv3.s
>  create mode 100644 gas/testsuite/gas/arm/feat-fp-vfpv5.s
>  create mode 100644 gas/testsuite/gas/arm/feat-fp.dp.s
>  create mode 100644 gas/testsuite/gas/arm/feat-fp.s
>  create mode 100644 gas/testsuite/gas/arm/feat-fp16.s
>  create mode 100644 gas/testsuite/gas/arm/feat-i8mm.s
>  create mode 100644 gas/testsuite/gas/arm/feat-idiv.s
>  create mode 100644 gas/testsuite/gas/arm/feat-mp.s
>  create mode 100644 gas/testsuite/gas/arm/feat-mve.fp.s
>  create mode 100644 gas/testsuite/gas/arm/feat-neon-fp16.s
>  create mode 100644 gas/testsuite/gas/arm/feat-pacbti.s
>  create mode 100644 gas/testsuite/gas/arm/feat-sec.s
>  create mode 100644 gas/testsuite/gas/arm/feat-simd.s
>  create mode 100644 gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a12-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a12-feat-simd.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a15-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a15-feat-simd.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a17-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a17-feat-simd.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a32-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a32-attrs1.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a32-feat-crc.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a32-feat-simd.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a35-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a35-attrs1.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a35-feat-crc.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a35-feat-simd.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a5-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a5-feat-mp.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a5-feat-neon-fp16.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a5-feat-sec.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a53-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a53-attrs1.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a53-feat-crc.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a53-feat-simd.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a55-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a55-attrs1.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a55-feat-dotprod.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a55-feat-fp16.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a57-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a57-feat-crc.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a57-feat-simd.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a7-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a7-feat-simd.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a710-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a710-feat-bf16.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a710-feat-fp16.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a710-feat-i8mm.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a72-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a72-feat-crc.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a72-feat-simd.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a73-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a73-feat-crc.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a73-feat-simd.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a75-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a75-feat-dotprod.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a75-feat-fp16.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a76-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a76-feat-dotprod.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a76-feat-fp16.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a76ae-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a76ae-feat-dotprod.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a76ae-feat-fp16.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a77-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a77-feat-dotprod.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a77-feat-fp16.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a78-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a78-feat-dotprod.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a78-feat-fp16.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a78ae-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a78ae-feat-dotprod.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a78ae-feat-fp16.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a78c-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a78c-feat-dotprod.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a78c-feat-fp16.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a8-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a8-feat-simd.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a9-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a9-feat-mp.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a9-feat-neon-fp16.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-a9-feat-sec.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m33-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m33-feat-dsp.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m33-feat-fp-vfpv5.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m35p-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m35p-feat-dsp.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m35p-feat-fp-vfpv5.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m4-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m4-feat-fp-vfpv3.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m52-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m52-attrs1.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m52-feat-fp-dp.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m52-feat-mve-fp.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m52-feat-pacbti.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m55-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m55-attrs1.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m55-feat-fp-dp.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m55-feat-mve-fp.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m7-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m7-feat-fp-dp.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m85-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m85-feat-fp-dp.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m85-feat-mve-fp.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-m85-feat-pacbti.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r4f-feat-fp-vfpv3.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r5-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r5-feat-fp-vfpv3.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r5-feat-idiv.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r52-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r52-feat-crc.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r52-feat-simd.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r52plus-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r52plus-feat-crc.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r52plus-feat-simd.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r7-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r7-feat-idiv.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r7-feat-vfpv3-d16-fp16.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r8-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r8-feat-idiv.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-r8-feat-vfpv3-d16-fp16.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-x1-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-x1-feat-dotprod.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-x1-feat-fp16.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-x1c-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-x1c-feat-dotprod.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-cortex-x1c-feat-fp16.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-exynos-m1-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-exynos-m1-feat-crc.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-exynos-m1-feat-simd.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-marvell-pj4-feat-fp-vfpv3.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-marvell-pj4-feat-mp.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-marvell-pj4-feat-sec.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-neoverse-n1-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-neoverse-n1-feat-dotprod.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-neoverse-n1-feat-fp16.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-neoverse-n2-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-neoverse-n2-feat-bf16.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-neoverse-n2-feat-fp16.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-neoverse-n2-feat-i8mm.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-neoverse-v1-attrs.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-neoverse-v1-feat-bf16.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-neoverse-v1-feat-fp16.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-neoverse-v1-feat-i8mm.d
>  create mode 100644 gas/testsuite/gas/arm/mcpu-xgene1-feat-simd.d
> 
> diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
> index 3ff29542411..ba599ef1fda 100644
> --- a/gas/config/tc-arm.c
> +++ b/gas/config/tc-arm.c
> @@ -30495,6 +30495,14 @@ const struct arm_legacy_option_table arm_legacy_opts[] =
>    {NULL, NULL, ARM_ARCH_NONE, NULL}
>  };
>  
> +struct arm_ext_table
> +{
> +  const char *		  name;
> +  size_t		  name_len;
> +  const arm_feature_set	  merge;
> +  const arm_feature_set	  clear;
> +};
> +
>  struct arm_cpu_option_table
>  {
>    const char *           name;
> @@ -30507,11 +30515,339 @@ struct arm_cpu_option_table
>    /* The canonical name of the CPU, or NULL to use NAME converted to upper
>       case.  */
>    const char *           canonical_name;
> +  const struct arm_ext_table *	ext_table;
> +};
> +
> +/* Used to add support for +E and +noE extension.  */
> +#define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
> +/* Used to add support for a +E extension.  */
> +#define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
> +/* Used to add support for a +noE extension.  */
> +#define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
> +
> +#define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
> +			    ~0 & ~FPU_ENDIAN_PURE)
> +#define ALL_FP_MVE_FP ARM_FEATURE (0, (ARM_EXT2_FP16_INST		   \
> +					| ARM_EXT2_FP16_FML		   \
> +					| ARM_EXT2_MVE_FP),		   \
> +				   ~0 & ~FPU_ENDIAN_PURE)
> +#define ALL_SIMD ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA       \
> +				     | FPU_NEON_EXT_ARMV8 | FPU_NEON_EXT_RDMA \
> +				     | FPU_NEON_EXT_DOTPROD)
> +
> +#define CDE_EXTENSIONS \
> +  ARM_ADD ("cdecp0", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE0)), \
> +  ARM_ADD ("cdecp1", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE1)), \
> +  ARM_ADD ("cdecp2", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE2)), \
> +  ARM_ADD ("cdecp3", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE3)), \
> +  ARM_ADD ("cdecp4", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE4)), \
> +  ARM_ADD ("cdecp5", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE5)), \
> +  ARM_ADD ("cdecp6", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE6)), \
> +  ARM_ADD ("cdecp7", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE7))
> +
> +/* -mcpu extensions.  */
> +static const struct arm_ext_table cortex_a5_ext_table[] =
> +{
> +  ARM_REMOVE ("fp", ALL_FP),
> +  ARM_REMOVE ("simd", ALL_SIMD),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a7_ext_table[] =
> +{
> +  ARM_REMOVE ("fp", ALL_FP),
> +  ARM_REMOVE ("simd", ALL_SIMD),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a8_ext_table[] =
> +{
> +  ARM_REMOVE ("fp", ALL_FP),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a9_ext_table[] =
> +{
> +  ARM_REMOVE ("fp", ALL_FP),
> +  ARM_REMOVE ("simd", ALL_SIMD),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a12_ext_table[] =
> +{
> +  ARM_REMOVE ("fp", ALL_FP),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a15_ext_table[] =
> +{
> +  ARM_REMOVE ("fp", ALL_FP),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a17_ext_table[] =
> +{
> +  ARM_REMOVE ("fp", ALL_FP),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_r5_ext_table[] =
> +{
> +  ARM_REMOVE ("fp",    ALL_FP),
> +  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
> +					   | FPU_VFP_EXT_ARMV8)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_r7_ext_table[] =
> +{
> +  ARM_REMOVE ("fp",    ALL_FP),
> +  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
> +					   | FPU_VFP_EXT_ARMV8)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_r8_ext_table[] =
> +{
> +  ARM_REMOVE ("fp",    ALL_FP),
> +  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
> +					   | FPU_VFP_EXT_ARMV8)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_m4_ext_table[] =
> +{
> +  ARM_REMOVE ("fp",    ALL_FP),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_m7_ext_table[] =
> +{
> +  ARM_REMOVE ("fp",    ALL_FP),
> +  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_V1 | FPU_VFP_EXT_V3
> +					   | FPU_VFP_EXT_ARMV8)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a32_ext_table[] =
> +{
> +  ARM_REMOVE ("fp",     ALL_FP),
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
> +					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a35_ext_table[] =
> +{
> +  ARM_REMOVE ("fp",     ALL_FP),
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
> +					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a53_ext_table[] =
> +{
> +  ARM_REMOVE ("fp",     ALL_FP),
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
> +					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a57_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
> +					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a72_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
> +					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a73_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
> +					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table exynos_m1_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
> +					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_r52_ext_table[] =
> +{
> +  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_D32 | FPU_VFP_EXT_ARMV8
> +					   | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA
> +					   | FPU_NEON_EXT_ARMV8 | FPU_NEON_EXT_RDMA
> +					   | FPU_NEON_EXT_DOTPROD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_r52plus_ext_table[] =
> +{
> +  ARM_REMOVE ("fp.dp", ARM_FEATURE_COPROC (FPU_VFP_EXT_D32 | FPU_VFP_EXT_ARMV8
> +					   | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA
> +					   | FPU_NEON_EXT_ARMV8 | FPU_NEON_EXT_RDMA
> +					   | FPU_NEON_EXT_DOTPROD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_m33_ext_table[] =
> +{
> +  ARM_REMOVE ("fp",  ALL_FP),
> +  ARM_REMOVE ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_m35p_ext_table[] =
> +{
> +  ARM_REMOVE ("fp",  ALL_FP),
> +  ARM_REMOVE ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_m52_ext_table[] =
> +{
> +  ARM_REMOVE ("pacbti", ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI)),
> +  ARM_REMOVE ("mve.fp", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP)),
> +  ARM_REMOVE ("mve",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
> +  ARM_REMOVE ("fp",     ALL_FP_MVE_FP),
> +  ARM_REMOVE ("dsp",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
> +  CDE_EXTENSIONS,
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_m55_ext_table[] =
> +{
> +  ARM_REMOVE ("mve.fp", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP)),
> +  ARM_REMOVE ("mve",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
> +  ARM_REMOVE ("fp",     ALL_FP_MVE_FP),
> +  ARM_REMOVE ("dsp",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
> +  CDE_EXTENSIONS,
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_m85_ext_table[] =
> +{
> +  ARM_REMOVE ("pacbti", ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI)),
> +  ARM_REMOVE ("mve.fp", ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP)),
> +  ARM_REMOVE ("mve",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
> +  ARM_REMOVE ("fp",     ALL_FP_MVE_FP),
> +  ARM_REMOVE ("dsp",    ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a55_ext_table[] =
> +{
> +  ARM_REMOVE ("fp", ALL_FP),
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
> +					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a75_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
> +					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a76_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
> +					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a76ae_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
> +					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a77_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
> +					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a78_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
> +					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a78ae_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
> +					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a78c_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
> +					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_x1_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
> +					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_x1c_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
> +					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table neoverse_n1_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
> +					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table neoverse_v1_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
> +					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table cortex_a710_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
> +					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
> +};
> +
> +static const struct arm_ext_table neoverse_n2_ext_table[] =
> +{
> +  ARM_ADD ("crypto", ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
> +					 | FPU_VFP_EXT_ARMV8 | FPU_VFP_EXT_ARMV8xD)),
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
>  };
>  
>  /* This list should, at a minimum, contain all the cpu names
>     recognized by GCC.  */
> -#define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
> +#define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN, NULL }
> +#define ARM_CPU_OPT2(N, CN, V, E, DF, ext) \
> +  { N, sizeof (N) - 1, V, E, DF, CN, ext##_ext_table }
>  
>  static const struct arm_cpu_option_table arm_cpus[] =
>  {
> @@ -30764,113 +31100,171 @@ static const struct arm_cpu_option_table arm_cpus[] =
>    ARM_CPU_OPT ("arm1176jzf-s",	  NULL,		       ARM_ARCH_V6KZ,
>  	       ARM_ARCH_NONE,
>  	       FPU_ARCH_VFP_V2),
> -  ARM_CPU_OPT ("cortex-a5",	  "Cortex-A5",	       ARM_ARCH_V7A,
> -	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
> -	       FPU_ARCH_SOFTVFP),
> -  ARM_CPU_OPT ("cortex-a7",	  "Cortex-A7",	       ARM_ARCH_V7VE,
> -	       ARM_ARCH_NONE,
> -	       FPU_ARCH_NEON_VFP_V4),
> -  ARM_CPU_OPT ("cortex-a8",	  "Cortex-A8",	       ARM_ARCH_V7A,
> -	       ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
> -	       ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
> -  ARM_CPU_OPT ("cortex-a9",	  "Cortex-A9",	       ARM_ARCH_V7A,
> -	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
> -	       ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
> -  ARM_CPU_OPT ("cortex-a12",	  "Cortex-A12",	       ARM_ARCH_V7VE,
> -	       ARM_ARCH_NONE,
> -	       FPU_ARCH_NEON_VFP_V4),
> -  ARM_CPU_OPT ("cortex-a15",	  "Cortex-A15",	       ARM_ARCH_V7VE,
> -	       ARM_ARCH_NONE,
> -	       FPU_ARCH_NEON_VFP_V4),
> -  ARM_CPU_OPT ("cortex-a17",	  "Cortex-A17",	       ARM_ARCH_V7VE,
> -	       ARM_ARCH_NONE,
> -	       FPU_ARCH_NEON_VFP_V4),
> -  ARM_CPU_OPT ("cortex-a32",	  "Cortex-A32",	       ARM_ARCH_V8A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("cortex-a35",	  "Cortex-A35",	       ARM_ARCH_V8A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("cortex-a53",	  "Cortex-A53",	       ARM_ARCH_V8A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("cortex-a55",    "Cortex-A55",	       ARM_ARCH_V8_2A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
> -  ARM_CPU_OPT ("cortex-a57",	  "Cortex-A57",	       ARM_ARCH_V8A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("cortex-a72",	  "Cortex-A72",	       ARM_ARCH_V8A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
> -	      FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("cortex-a73",	  "Cortex-A73",	       ARM_ARCH_V8A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
> -	      FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("cortex-a75",    "Cortex-A75",	       ARM_ARCH_V8_2A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
> -  ARM_CPU_OPT ("cortex-a76",    "Cortex-A76",	       ARM_ARCH_V8_2A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
> -  ARM_CPU_OPT ("cortex-a76ae",    "Cortex-A76AE",      ARM_ARCH_V8_2A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
> -  ARM_CPU_OPT ("cortex-a77",    "Cortex-A77",	       ARM_ARCH_V8_2A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
> -  ARM_CPU_OPT ("cortex-a78",   "Cortex-A78",	       ARM_ARCH_V8_2A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
> -	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("cortex-a78ae",   "Cortex-A78AE",	   ARM_ARCH_V8_2A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
> -	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("cortex-a78c",   "Cortex-A78C",	   ARM_ARCH_V8_2A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
> -	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("cortex-a710",   "Cortex-A710",	   ARM_ARCH_V9A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
> -				    | ARM_EXT2_BF16
> -				    | ARM_EXT2_I8MM),
> -	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("ares",    "Ares",	       ARM_ARCH_V8_2A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
> +  ARM_CPU_OPT2 ("cortex-a5",	  "Cortex-A5",	       ARM_ARCH_V7A,
> +		ARM_FEATURE ((ARM_EXT_MP | ARM_EXT_SEC),
> +			     ARM_EXT2_FP16_INST,
> +			     (FPU_VFP_V4 | FPU_NEON_EXT_V1
> +			      | FPU_NEON_EXT_FMA)),
> +		FPU_ARCH_NEON_VFP_V4,
> +		cortex_a5),
> +  ARM_CPU_OPT2 ("cortex-a7",	  "Cortex-A7",	       ARM_ARCH_V7VE,
> +		ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1
> +				    | FPU_NEON_EXT_FMA),
> +		FPU_ARCH_NEON_VFP_V4,
> +		cortex_a7),
> +  ARM_CPU_OPT2 ("cortex-a8",	  "Cortex-A8",	       ARM_ARCH_V7A,
> +		ARM_FEATURE_LOW (ARM_EXT_SEC, FPU_VFP_V3 | FPU_NEON_EXT_V1),
> +		ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1),
> +		cortex_a8),
> +  ARM_CPU_OPT2 ("cortex-a9",	  "Cortex-A9",	       ARM_ARCH_V7A,
> +		ARM_FEATURE ((ARM_EXT_MP | ARM_EXT_SEC),
> +			     ARM_EXT2_FP16_INST,
> +			     (FPU_VFP_V4 | FPU_NEON_EXT_V1
> +			      | FPU_NEON_EXT_FMA)),
> +		FPU_ARCH_NEON_VFP_V4,
> +		cortex_a9),
> +  ARM_CPU_OPT2 ("cortex-a12",	  "Cortex-A12",	       ARM_ARCH_V7VE,
> +		ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1
> +				    | FPU_NEON_EXT_FMA),
> +		FPU_ARCH_NEON_VFP_V4,
> +		cortex_a12),
> +  ARM_CPU_OPT2 ("cortex-a15",	  "Cortex-A15",	       ARM_ARCH_V7VE,
> +		ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1
> +				    | FPU_NEON_EXT_FMA),
> +		FPU_ARCH_NEON_VFP_V4,
> +		cortex_a15),
> +  ARM_CPU_OPT2 ("cortex-a17",	  "Cortex-A17",	       ARM_ARCH_V7VE,
> +		ARM_FEATURE_COPROC (FPU_VFP_V4 | FPU_NEON_EXT_V1
> +				    | FPU_NEON_EXT_FMA),
> +		FPU_ARCH_NEON_VFP_V4,
> +		cortex_a17),
> +  ARM_CPU_OPT2 ("cortex-a32",	  "Cortex-A32",	       ARM_ARCH_V8A,
> +		ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
> +		FPU_ARCH_NEON_VFP_ARMV8,
> +		cortex_a32),
> +  ARM_CPU_OPT2 ("cortex-a35",	  "Cortex-A35",	       ARM_ARCH_V8A,
> +		ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
> +		FPU_ARCH_NEON_VFP_ARMV8,
> +		cortex_a35),
> +  ARM_CPU_OPT2 ("cortex-a53",	  "Cortex-A53",	       ARM_ARCH_V8A,
> +		ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
> +		FPU_ARCH_NEON_VFP_ARMV8,
> +		cortex_a53),
> +  ARM_CPU_OPT2 ("cortex-a55",    "Cortex-A55",	       ARM_ARCH_V8_2A,
> +		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +		cortex_a55),
> +  ARM_CPU_OPT2 ("cortex-a57",	  "Cortex-A57",	       ARM_ARCH_V8A,
> +		ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
> +		FPU_ARCH_NEON_VFP_ARMV8,
> +		cortex_a57),
> +  ARM_CPU_OPT2 ("cortex-a72",	  "Cortex-A72",	       ARM_ARCH_V8A,
> +		ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
> +		FPU_ARCH_NEON_VFP_ARMV8,
> +		cortex_a72),
> +  ARM_CPU_OPT2 ("cortex-a73",	  "Cortex-A73",	       ARM_ARCH_V8A,
> +		ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
> +		FPU_ARCH_NEON_VFP_ARMV8,
> +		cortex_a73),
> +  ARM_CPU_OPT2 ("cortex-a75",    "Cortex-A75",	       ARM_ARCH_V8_2A,
> +		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +		cortex_a75),
> +  ARM_CPU_OPT2 ("cortex-a76",    "Cortex-A76",	       ARM_ARCH_V8_2A,
> +		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +		FPU_ARCH_VFP_V5_SP_D16,
> +		cortex_a76),
> +  ARM_CPU_OPT2 ("cortex-a76ae",    "Cortex-A76AE",      ARM_ARCH_V8_2A,
> +		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +		FPU_ARCH_VFP_V5_SP_D16,
> +		cortex_a76ae),
> +  ARM_CPU_OPT2 ("cortex-a77",    "Cortex-A77",	       ARM_ARCH_V8_2A,
> +		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +		FPU_ARCH_VFP_V5_SP_D16,
> +		cortex_a77),
> +  ARM_CPU_OPT2 ("cortex-a78",   "Cortex-A78",	       ARM_ARCH_V8_2A,
> +		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +		FPU_ARCH_VFP_V5_SP_D16,
> +		cortex_a78),
> +  ARM_CPU_OPT2 ("cortex-a78ae",   "Cortex-A78AE",	   ARM_ARCH_V8_2A,
> +		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +		FPU_ARCH_VFP_V5_SP_D16,
> +		cortex_a78ae),
> +  ARM_CPU_OPT2 ("cortex-a78c",   "Cortex-A78C",	   ARM_ARCH_V8_2A,
> +		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +		FPU_ARCH_VFP_V5_SP_D16,
> +		cortex_a78c),
>    ARM_CPU_OPT ("cortex-r4",	  "Cortex-R4",	       ARM_ARCH_V7R,
>  	       ARM_ARCH_NONE,
>  	       FPU_ARCH_SOFTVFP),
>    ARM_CPU_OPT ("cortex-r4f",	  "Cortex-R4F",	       ARM_ARCH_V7R,
> -	       ARM_ARCH_NONE,
> -	       FPU_ARCH_VFP_V3D16),
> -  ARM_CPU_OPT ("cortex-r5",	  "Cortex-R5",	       ARM_ARCH_V7R,
> -	       ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
> -	       FPU_ARCH_SOFTVFP),
> -  ARM_CPU_OPT ("cortex-r7",	  "Cortex-R7",	       ARM_ARCH_V7R,
> -	       ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
> -	       FPU_ARCH_VFP_V3D16),
> -  ARM_CPU_OPT ("cortex-r8",	  "Cortex-R8",	       ARM_ARCH_V7R,
> -	       ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
> +	       FPU_ARCH_VFP_V3D16,
>  	       FPU_ARCH_VFP_V3D16),
> -  ARM_CPU_OPT ("cortex-r52",	  "Cortex-R52",	       ARM_ARCH_V8R,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
> -	      FPU_ARCH_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("cortex-r52plus",	  "Cortex-R52+",	       ARM_ARCH_V8R,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
> -	      FPU_ARCH_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("cortex-m35p",	  "Cortex-M35P",       ARM_ARCH_V8M_MAIN,
> -	       ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
> -	       FPU_ARCH_SOFTVFP),
> -  ARM_CPU_OPT ("cortex-m33",	  "Cortex-M33",	       ARM_ARCH_V8M_MAIN,
> -	       ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
> -	       FPU_ARCH_SOFTVFP),
> +  ARM_CPU_OPT2 ("cortex-r5",	  "Cortex-R5",	       ARM_ARCH_V7R,
> +		ARM_FEATURE (ARM_EXT_ADIV, 0, FPU_VFP_V3),
> +		FPU_ARCH_VFP_V3,
> +		cortex_r5),
> +  ARM_CPU_OPT2 ("cortex-r7",	  "Cortex-R7",	       ARM_ARCH_V7R,
> +		ARM_FEATURE (ARM_EXT_ADIV, 0, FPU_VFP_V3D16 | FPU_VFP_EXT_FP16),
> +		FPU_ARCH_VFP_V3D16_FP16,
> +		cortex_r7),
> +  ARM_CPU_OPT2 ("cortex-r8",	  "Cortex-R8",	       ARM_ARCH_V7R,
> +		ARM_FEATURE (ARM_EXT_ADIV, 0, FPU_VFP_V3D16 | FPU_VFP_EXT_FP16),
> +		FPU_ARCH_VFP_V3D16_FP16,
> +		cortex_r8),
> +  ARM_CPU_OPT2 ("cortex-r52",	  "Cortex-R52",	       ARM_ARCH_V8R,
> +		ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
> +		FPU_ARCH_NEON_VFP_ARMV8,
> +		cortex_r52),
> +  ARM_CPU_OPT2 ("cortex-r52plus",	  "Cortex-R52+",	ARM_ARCH_V8R,
> +		ARM_FEATURE(0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
> +		FPU_ARCH_NEON_VFP_ARMV8,
> +		cortex_r52plus),
> +  ARM_CPU_OPT2 ("cortex-m85",	 "Cortex-M85",	       ARM_ARCH_V8_1M_MAIN,
> +		ARM_FEATURE_ALL(ARM_AEXT_V8M_MAIN_DSP,
> +				(ARM_EXT2_FP16_INST | ARM_EXT2_MVE
> +				 | ARM_EXT2_MVE_FP),
> +				ARM_EXT3_PACBTI,
> +				(FPU_VFP_V5D16 | FPU_VFP_EXT_FP16
> +				 | FPU_VFP_EXT_FMA)),
> +		FPU_ARCH_SOFTVFP,
> +		cortex_m85),
> +  ARM_CPU_OPT2 ("cortex-m55",	 "Cortex-M55",	       ARM_ARCH_V8_1M_MAIN,
> +		ARM_FEATURE_ALL(ARM_AEXT_V8M_MAIN_DSP,
> +				(ARM_EXT2_FP16_INST | ARM_EXT2_MVE
> +				 | ARM_EXT2_MVE_FP),
> +				0,
> +				(FPU_VFP_V5D16 | FPU_VFP_EXT_FP16
> +				 | FPU_VFP_EXT_FMA)),
> +		FPU_ARCH_SOFTVFP,
> +		cortex_m55),
> +  ARM_CPU_OPT2 ("cortex-m52",	 "Cortex-M52",	       ARM_ARCH_V8_1M_MAIN,
> +		ARM_FEATURE_ALL (ARM_AEXT_V8M_MAIN_DSP,
> +				 (ARM_EXT2_FP16_INST | ARM_EXT2_MVE
> +				  | ARM_EXT2_MVE_FP),
> +				 ARM_EXT3_PACBTI,
> +				 (FPU_VFP_V5D16 | FPU_VFP_EXT_FP16
> +				  | FPU_VFP_EXT_FMA)),
> +		FPU_ARCH_SOFTVFP,
> +		cortex_m52),
> +  ARM_CPU_OPT2 ("cortex-m35p",	  "Cortex-M35P",       ARM_ARCH_V8M_MAIN,
> +		ARM_FEATURE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP, FPU_VFP_V4D16),
> +		FPU_ARCH_VFP_V3D16,
> +		cortex_m35p),
> +  ARM_CPU_OPT2 ("cortex-m33",	  "Cortex-M33",	       ARM_ARCH_V8M_MAIN,
> +		ARM_FEATURE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP, FPU_VFP_V4D16),
> +		FPU_ARCH_VFP_V3D16, cortex_m33),
>    ARM_CPU_OPT ("cortex-m23",	  "Cortex-M23",	       ARM_ARCH_V8M_BASE,
>  	       ARM_ARCH_NONE,
>  	       FPU_ARCH_SOFTVFP),
> -  ARM_CPU_OPT ("cortex-m7",	  "Cortex-M7",	       ARM_ARCH_V7EM,
> -	       ARM_ARCH_NONE,
> -	       FPU_ARCH_SOFTVFP),
> -  ARM_CPU_OPT ("cortex-m4",	  "Cortex-M4",	       ARM_ARCH_V7EM,
> -	       ARM_ARCH_NONE,
> -	       FPU_ARCH_SOFTVFP),
> +  ARM_CPU_OPT2 ("cortex-m7",	  "Cortex-M7",	       ARM_ARCH_V7EM,
> +		ARM_FEATURE_COPROC (FPU_VFP_V5D16),
> +		FPU_ARCH_VFP_V5D16,
> +		cortex_m7),
> +  ARM_CPU_OPT2 ("cortex-m4",	  "Cortex-M4",	       ARM_ARCH_V7EM,
> +		ARM_FEATURE_COPROC (FPU_VFP_V4_SP_D16),
> +		FPU_ARCH_VFP_V4_SP_D16,
> +		cortex_m4),
>    ARM_CPU_OPT ("cortex-m3",	  "Cortex-M3",	       ARM_ARCH_V7M,
>  	       ARM_ARCH_NONE,
>  	       FPU_ARCH_SOFTVFP),
> @@ -30883,28 +31277,50 @@ static const struct arm_cpu_option_table arm_cpus[] =
>    ARM_CPU_OPT ("cortex-m0plus",	  "Cortex-M0+",	       ARM_ARCH_V6SM,
>  	       ARM_ARCH_NONE,
>  	       FPU_ARCH_SOFTVFP),
> -  ARM_CPU_OPT ("cortex-x1",   "Cortex-X1",	       ARM_ARCH_V8_2A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
> -	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("cortex-x1c",   "Cortex-X1C",	       ARM_ARCH_V8_2A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
> -	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("exynos-m1",	  "Samsung Exynos M1", ARM_ARCH_V8A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
> -  ARM_CPU_OPT ("neoverse-n1",    "Neoverse N1",	       ARM_ARCH_V8_2A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
> -  ARM_CPU_OPT ("neoverse-n2",	 "Neoverse N2",	       ARM_ARCH_V8_5A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
> -				    | ARM_EXT2_BF16
> -				    | ARM_EXT2_I8MM),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4),
> -  ARM_CPU_OPT ("neoverse-v1", "Neoverse V1", ARM_ARCH_V8_4A,
> -	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
> -				    | ARM_EXT2_BF16
> -				    | ARM_EXT2_I8MM),
> -	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4),
> +  ARM_CPU_OPT2 ("cortex-x1",   "Cortex-X1",	       ARM_ARCH_V8_2A,
> +		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +		FPU_ARCH_VFP_V5_SP_D16,
> +		cortex_x1),
> +  ARM_CPU_OPT2 ("cortex-x1c",   "Cortex-X1C",	       ARM_ARCH_V8_2A,
> +		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +		FPU_ARCH_VFP_V5_SP_D16,
> +		cortex_x1c),
> +  ARM_CPU_OPT2 ("exynos-m1",	  "Samsung Exynos M1", ARM_ARCH_V8A,
> +		ARM_FEATURE (0, ARM_EXT2_CRC, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
> +		FPU_ARCH_NEON_VFP_ARMV8,
> +		exynos_m1),
> +  ARM_CPU_OPT2 ("neoverse-n1",	 "Neoverse N1",	       ARM_ARCH_V8_2A,
> +		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +		FPU_ARCH_VFP_V5_SP_D16,
> +		neoverse_n1),
> +  ARM_CPU_OPT2 ("ares",    "Ares",	       ARM_ARCH_V8_2A,
> +		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +		FPU_ARCH_VFP_V5_SP_D16,
> +		neoverse_n1),
> +  ARM_CPU_OPT2 ("neoverse-n2",	 "Neoverse N2",	       ARM_ARCH_V9A,
> +		ARM_FEATURE(0,
> +			    (ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML
> +			     | ARM_EXT2_BF16 | ARM_EXT2_I8MM),
> +			    (FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8
> +			     | FPU_NEON_EXT_DOTPROD | FPU_NEON_EXT_RDMA)),
> +		FPU_ARCH_VFP_V5_SP_D16,
> +		neoverse_n2),
> +  ARM_CPU_OPT2 ("cortex-a710",	 "Cortex-A710",	   ARM_ARCH_V9A,
> +		ARM_FEATURE(0,
> +			    (ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML
> +			     | ARM_EXT2_BF16 | ARM_EXT2_I8MM),
> +			    (FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8
> +			     | FPU_NEON_EXT_DOTPROD | FPU_NEON_EXT_RDMA)),
> +		FPU_ARCH_VFP_V5_SP_D16,
> +		cortex_a710),
> +  ARM_CPU_OPT2 ("neoverse-v1",	 "Neoverse V1",	       ARM_ARCH_V8_4A,
> +		ARM_FEATURE(0,
> +			    (ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML
> +			     | ARM_EXT2_BF16 | ARM_EXT2_I8MM),
> +			    (FPU_NEON_ARMV8_1 | FPU_VFP_ARMV8
> +			     | FPU_NEON_EXT_DOTPROD)),
> +		FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML,
> +		neoverse_v1),
>    /* ??? XSCALE is really an architecture.  */
>    ARM_CPU_OPT ("xscale",	  NULL,		       ARM_ARCH_XSCALE,
>  	       ARM_ARCH_NONE,
> @@ -30928,31 +31344,24 @@ static const struct arm_cpu_option_table arm_cpus[] =
>  
>    /* Marvell processors.  */
>    ARM_CPU_OPT ("marvell-pj4",	  NULL,		       ARM_ARCH_V7A,
> -	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
> -	       FPU_ARCH_VFP_V3D16),
> +	       ARM_FEATURE (ARM_EXT_MP | ARM_EXT_SEC, 0, FPU_VFP_V3),
> +	       FPU_ARCH_VFP_V3),
>    ARM_CPU_OPT ("marvell-whitney", NULL,		       ARM_ARCH_V7A,
>  	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
>  	       FPU_ARCH_NEON_VFP_V4),
>  
>    /* APM X-Gene family.  */
>    ARM_CPU_OPT ("xgene1",	  "APM X-Gene 1",      ARM_ARCH_V8A,
> -	       ARM_ARCH_NONE,
> +	       ARM_FEATURE (0, 0, FPU_NEON_ARMV8 | FPU_VFP_ARMV8),
>  	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
>    ARM_CPU_OPT ("xgene2",	  "APM X-Gene 2",      ARM_ARCH_V8A,
>  	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
>  	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
>  
> -  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
> +  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL, NULL }
>  };
>  #undef ARM_CPU_OPT
> -
> -struct arm_ext_table
> -{
> -  const char *		  name;
> -  size_t		  name_len;
> -  const arm_feature_set	  merge;
> -  const arm_feature_set	  clear;
> -};
> +#undef ARM_CPU_OPT2
>  
>  struct arm_arch_option_table
>  {
> @@ -30963,16 +31372,6 @@ struct arm_arch_option_table
>    const struct arm_ext_table *	ext_table;
>  };
>  
> -/* Used to add support for +E and +noE extension.  */
> -#define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
> -/* Used to add support for a +E extension.  */
> -#define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
> -/* Used to add support for a +noE extension.  */
> -#define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
> -
> -#define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
> -			    ~0 & ~FPU_ENDIAN_PURE)
> -
>  static const struct arm_ext_table armv5te_ext_table[] =
>  {
>    ARM_EXT ("fp", FPU_ARCH_VFP_V2, ALL_FP),
> @@ -31169,16 +31568,6 @@ static const struct arm_ext_table armv9a_ext_table[] =
>  #define armv94a_ext_table armv93a_ext_table
>  #define armv95a_ext_table armv94a_ext_table
>  
> -#define CDE_EXTENSIONS \
> -  ARM_ADD ("cdecp0", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE0)), \
> -  ARM_ADD ("cdecp1", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE1)), \
> -  ARM_ADD ("cdecp2", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE2)), \
> -  ARM_ADD ("cdecp3", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE3)), \
> -  ARM_ADD ("cdecp4", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE4)), \
> -  ARM_ADD ("cdecp5", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE5)), \
> -  ARM_ADD ("cdecp6", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE6)), \
> -  ARM_ADD ("cdecp7", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE7))
> -
>  static const struct arm_ext_table armv8m_main_ext_table[] =
>  {
>    ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP),
> @@ -31755,7 +32144,7 @@ arm_parse_cpu (const char *str)
>  	  }
>  
>  	if (ext != NULL)
> -	  return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, NULL);
> +	  return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, opt->ext_table);
>  
>  	return true;
>        }
> diff --git a/gas/testsuite/gas/arm/attr-cpu-directive.d b/gas/testsuite/gas/arm/attr-cpu-directive.d
> index a2ab435fc0a..62a07adb4de 100644
> --- a/gas/testsuite/gas/arm/attr-cpu-directive.d
> +++ b/gas/testsuite/gas/arm/attr-cpu-directive.d
> @@ -12,4 +12,6 @@ File Attributes
>    Tag_CPU_arch_profile: Application
>    Tag_ARM_ISA_use: Yes
>    Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: VFPv3
> +  Tag_Advanced_SIMD_arch: NEONv1
>    Tag_Virtualization_use: TrustZone
> diff --git a/gas/testsuite/gas/arm/feat-bf16.s b/gas/testsuite/gas/arm/feat-bf16.s
> new file mode 100644
> index 00000000000..46fc48ba567
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-bf16.s
> @@ -0,0 +1,5 @@
> +.syntax unified
> +.thumb
> +
> +@ feat FP16
> +vdot.bf16 q0, q1, q2
> diff --git a/gas/testsuite/gas/arm/feat-crc.s b/gas/testsuite/gas/arm/feat-crc.s
> new file mode 100644
> index 00000000000..671ac14ebcb
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-crc.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ feat CRC
> +crc32w  r0, r0, r1
> diff --git a/gas/testsuite/gas/arm/feat-dotprod.s b/gas/testsuite/gas/arm/feat-dotprod.s
> new file mode 100644
> index 00000000000..775c3ba4c02
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-dotprod.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ feat DOTPROD
> +vudot.u8 q0, q1, q2
> diff --git a/gas/testsuite/gas/arm/feat-dsp.s b/gas/testsuite/gas/arm/feat-dsp.s
> new file mode 100644
> index 00000000000..2f54c7327d1
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-dsp.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ feat DSP
> +smlad   r0, r1, r2, r3
> diff --git a/gas/testsuite/gas/arm/feat-fp-vfpv3.s b/gas/testsuite/gas/arm/feat-fp-vfpv3.s
> new file mode 100644
> index 00000000000..4435db35690
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-fp-vfpv3.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ feat FP (VFP-v3)
> +vmla.f32 s0, s1, s2
> diff --git a/gas/testsuite/gas/arm/feat-fp-vfpv5.s b/gas/testsuite/gas/arm/feat-fp-vfpv5.s
> new file mode 100644
> index 00000000000..13a2e7aca9e
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-fp-vfpv5.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ feat FP (VFP-v5)
> +vfma.f32 s0, s1, s2
> diff --git a/gas/testsuite/gas/arm/feat-fp.dp.s b/gas/testsuite/gas/arm/feat-fp.dp.s
> new file mode 100644
> index 00000000000..34b68cd8603
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-fp.dp.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ feat FP.DP
> +vadd.f64 d0, d1, d2
> diff --git a/gas/testsuite/gas/arm/feat-fp.s b/gas/testsuite/gas/arm/feat-fp.s
> new file mode 100644
> index 00000000000..5cf49af0e9f
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-fp.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ feat FP
> +vadd.f32 s0, s1, s2
> diff --git a/gas/testsuite/gas/arm/feat-fp16.s b/gas/testsuite/gas/arm/feat-fp16.s
> new file mode 100644
> index 00000000000..6780678e8ca
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-fp16.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ feat FP16
> +vadd.f16 q0, q1, q2
> diff --git a/gas/testsuite/gas/arm/feat-i8mm.s b/gas/testsuite/gas/arm/feat-i8mm.s
> new file mode 100644
> index 00000000000..bb3818726a8
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-i8mm.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ feat I8MM
> +vusmmla.s8  q6, q7, q8
> diff --git a/gas/testsuite/gas/arm/feat-idiv.s b/gas/testsuite/gas/arm/feat-idiv.s
> new file mode 100644
> index 00000000000..8b289fa817d
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-idiv.s
> @@ -0,0 +1,3 @@
> +.syntax unified
> +
> +sdiv r0, r1, r2
> diff --git a/gas/testsuite/gas/arm/feat-mp.s b/gas/testsuite/gas/arm/feat-mp.s
> new file mode 100644
> index 00000000000..db365d7f282
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-mp.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ feat MP
> +ldrex r0, [r1]
> diff --git a/gas/testsuite/gas/arm/feat-mve.fp.s b/gas/testsuite/gas/arm/feat-mve.fp.s
> new file mode 100644
> index 00000000000..81c23300dc3
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-mve.fp.s
> @@ -0,0 +1,5 @@
> +.syntax unified
> +.thumb
> +
> +@ MVE.FP
> +vmul.f32 q0, q1, q2
> diff --git a/gas/testsuite/gas/arm/feat-neon-fp16.s b/gas/testsuite/gas/arm/feat-neon-fp16.s
> new file mode 100644
> index 00000000000..55ab08553bf
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-neon-fp16.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ feat NEON-FP16
> +vadd.f16 q0, q1, q2
> diff --git a/gas/testsuite/gas/arm/feat-pacbti.s b/gas/testsuite/gas/arm/feat-pacbti.s
> new file mode 100644
> index 00000000000..2399f0ca230
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-pacbti.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ PACBTI
> +pac     r12, lr, sp
> diff --git a/gas/testsuite/gas/arm/feat-sec.s b/gas/testsuite/gas/arm/feat-sec.s
> new file mode 100644
> index 00000000000..bdb516a30f4
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-sec.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ feat SEC
> +smc     #0
> diff --git a/gas/testsuite/gas/arm/feat-simd.s b/gas/testsuite/gas/arm/feat-simd.s
> new file mode 100644
> index 00000000000..871f5490902
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-simd.s
> @@ -0,0 +1,5 @@
> +.syntax unified
> +.text
> +
> +@ feat SIMD
> +vadd.i32 q0, q1, q2
> diff --git a/gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s b/gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s
> new file mode 100644
> index 00000000000..41ccd2d9414
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/feat-vfpv3-d16-fp16.s
> @@ -0,0 +1,4 @@
> +.syntax unified
> +
> +@ feat VFP3-D16-FP16
> +vcvtt.f16.f32 s0, s1
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a12-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a12-attrs.d
> new file mode 100644
> index 00000000000..953175f6eba
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a12-attrs.d
> @@ -0,0 +1,17 @@
> +#name: Cortex-A12 Attributes
> +#as: -mcpu=cortex-a12+nofp
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A12"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_MPextension_use: Allowed
> +  Tag_DIV_use: Allowed in v7-A with integer division extension
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a12-feat-simd.d b/gas/testsuite/gas/arm/mcpu-cortex-a12-feat-simd.d
> new file mode 100644
> index 00000000000..e8d96c21f04
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a12-feat-simd.d
> @@ -0,0 +1,19 @@
> +#name: Cortex-A12 feat-simd
> +#as: -mcpu=cortex-a12
> +#source: feat-simd.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A12"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: VFPv4
> +  Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
> +  Tag_MPextension_use: Allowed
> +  Tag_DIV_use: Allowed in v7-A with integer division extension
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a15-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a15-attrs.d
> new file mode 100644
> index 00000000000..c780f280b0c
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a15-attrs.d
> @@ -0,0 +1,17 @@
> +#name: Cortex-A15 Attributes
> +#as: -mcpu=cortex-a15+nofp
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A15"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_MPextension_use: Allowed
> +  Tag_DIV_use: Allowed in v7-A with integer division extension
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a15-feat-simd.d b/gas/testsuite/gas/arm/mcpu-cortex-a15-feat-simd.d
> new file mode 100644
> index 00000000000..796f8d3fb04
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a15-feat-simd.d
> @@ -0,0 +1,19 @@
> +#name: Cortex-A15 feat-simd
> +#as: -mcpu=cortex-a15
> +#source: feat-simd.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A15"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: VFPv4
> +  Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
> +  Tag_MPextension_use: Allowed
> +  Tag_DIV_use: Allowed in v7-A with integer division extension
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a17-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a17-attrs.d
> new file mode 100644
> index 00000000000..c8b56ff58c2
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a17-attrs.d
> @@ -0,0 +1,17 @@
> +#name: Cortex-A17 Attributes
> +#as: -mcpu=cortex-a17+nofp
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A17"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_MPextension_use: Allowed
> +  Tag_DIV_use: Allowed in v7-A with integer division extension
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a17-feat-simd.d b/gas/testsuite/gas/arm/mcpu-cortex-a17-feat-simd.d
> new file mode 100644
> index 00000000000..37e3444d237
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a17-feat-simd.d
> @@ -0,0 +1,19 @@
> +#name: Cortex-A17 feat-simd
> +#as: -mcpu=cortex-a17
> +#source: feat-simd.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A17"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: VFPv4
> +  Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
> +  Tag_MPextension_use: Allowed
> +  Tag_DIV_use: Allowed in v7-A with integer division extension
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a32-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a32-attrs.d
> new file mode 100644
> index 00000000000..6979aff8835
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a32-attrs.d
> @@ -0,0 +1,16 @@
> +#name: Cortex-A32 Attributes
> +#as: -mcpu=cortex-a32+nofp
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A32"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a32-attrs1.d b/gas/testsuite/gas/arm/mcpu-cortex-a32-attrs1.d
> new file mode 100644
> index 00000000000..98dc43bde01
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a32-attrs1.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A32 Attributes 1
> +#as: -mcpu=cortex-a32+crypto
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A32"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a32-feat-crc.d b/gas/testsuite/gas/arm/mcpu-cortex-a32-feat-crc.d
> new file mode 100644
> index 00000000000..dfa191bd52c
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a32-feat-crc.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A32 feat-crc
> +#as: -mcpu=cortex-a32
> +#source: feat-crc.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A32"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a32-feat-simd.d b/gas/testsuite/gas/arm/mcpu-cortex-a32-feat-simd.d
> new file mode 100644
> index 00000000000..20b6a34a8fb
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a32-feat-simd.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A32 feat-simd
> +#as: -mcpu=cortex-a32
> +#source: feat-simd.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A32"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a35-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a35-attrs.d
> new file mode 100644
> index 00000000000..5743016e2e3
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a35-attrs.d
> @@ -0,0 +1,16 @@
> +#name: Cortex-A35 Attributes
> +#as: -mcpu=cortex-a35+nofp
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A35"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a35-attrs1.d b/gas/testsuite/gas/arm/mcpu-cortex-a35-attrs1.d
> new file mode 100644
> index 00000000000..97160cf2f8a
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a35-attrs1.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A35 Attributes 1
> +#as: -mcpu=cortex-a35+crypto
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A35"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a35-feat-crc.d b/gas/testsuite/gas/arm/mcpu-cortex-a35-feat-crc.d
> new file mode 100644
> index 00000000000..eb61f3b0f36
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a35-feat-crc.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A35 feat-crc
> +#as: -mcpu=cortex-a35
> +#source: feat-crc.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A35"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a35-feat-simd.d b/gas/testsuite/gas/arm/mcpu-cortex-a35-feat-simd.d
> new file mode 100644
> index 00000000000..3c92517c90f
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a35-feat-simd.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A35 feat-simd
> +#as: -mcpu=cortex-a35
> +#source: feat-simd.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A35"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a5-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a5-attrs.d
> new file mode 100644
> index 00000000000..d1ab26e87aa
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a5-attrs.d
> @@ -0,0 +1,16 @@
> +#name: Cortex-A5 Attributes
> +#as: -mcpu=cortex-a5+nofp+nosimd
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A5"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a5-feat-mp.d b/gas/testsuite/gas/arm/mcpu-cortex-a5-feat-mp.d
> new file mode 100644
> index 00000000000..3b34ffb508b
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a5-feat-mp.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A5 feat-mp
> +#as: -mcpu=cortex-a5
> +#source: feat-mp.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A5"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: VFPv4
> +  Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a5-feat-neon-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-a5-feat-neon-fp16.d
> new file mode 100644
> index 00000000000..36571e2aed3
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a5-feat-neon-fp16.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A5 feat-neon-fp16
> +#as: -mcpu=cortex-a5
> +#source: feat-neon-fp16.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A5"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: VFPv4
> +  Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a5-feat-sec.d b/gas/testsuite/gas/arm/mcpu-cortex-a5-feat-sec.d
> new file mode 100644
> index 00000000000..dad84126dec
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a5-feat-sec.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A5 feat-sec
> +#as: -mcpu=cortex-a5
> +#source: feat-sec.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A5"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: VFPv4
> +  Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a53-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a53-attrs.d
> new file mode 100644
> index 00000000000..754eca0570e
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a53-attrs.d
> @@ -0,0 +1,16 @@
> +#name: Cortex-A53 Attributes
> +#as: -mcpu=cortex-a53+nofp
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A53"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a53-attrs1.d b/gas/testsuite/gas/arm/mcpu-cortex-a53-attrs1.d
> new file mode 100644
> index 00000000000..ad52b9278fb
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a53-attrs1.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A53 Attributes 1
> +#as: -mcpu=cortex-a53+crypto
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A53"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a53-feat-crc.d b/gas/testsuite/gas/arm/mcpu-cortex-a53-feat-crc.d
> new file mode 100644
> index 00000000000..70a688c1116
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a53-feat-crc.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A53 feat-crc
> +#as: -mcpu=cortex-a53
> +#source: feat-crc.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A53"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a53-feat-simd.d b/gas/testsuite/gas/arm/mcpu-cortex-a53-feat-simd.d
> new file mode 100644
> index 00000000000..0c423b767bf
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a53-feat-simd.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A53 feat-simd
> +#as: -mcpu=cortex-a53
> +#source: feat-simd.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A53"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a55-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a55-attrs.d
> new file mode 100644
> index 00000000000..247e146fc23
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a55-attrs.d
> @@ -0,0 +1,17 @@
> +#name: Cortex-A55 Attributes
> +#as: -mcpu=cortex-a55+nofp
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A55"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a55-attrs1.d b/gas/testsuite/gas/arm/mcpu-cortex-a55-attrs1.d
> new file mode 100644
> index 00000000000..595a677bc73
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a55-attrs1.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A55 Attributes 1
> +#as: -mcpu=cortex-a55+crypto
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A55"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a55-feat-dotprod.d b/gas/testsuite/gas/arm/mcpu-cortex-a55-feat-dotprod.d
> new file mode 100644
> index 00000000000..bd95929778c
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a55-feat-dotprod.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A55 feat-dotprod
> +#as: -mcpu=cortex-a55
> +#source: feat-dotprod.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A55"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a55-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-a55-feat-fp16.d
> new file mode 100644
> index 00000000000..79ec5bc418f
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a55-feat-fp16.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A55 feat-fp16
> +#as: -mcpu=cortex-a55
> +#source: feat-fp16.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A55"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a57-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a57-attrs.d
> new file mode 100644
> index 00000000000..0d7e1200e7d
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a57-attrs.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A57 Attributes
> +#as: -mcpu=cortex-a57+crypto
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A57"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a57-feat-crc.d b/gas/testsuite/gas/arm/mcpu-cortex-a57-feat-crc.d
> new file mode 100644
> index 00000000000..49be31c5c15
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a57-feat-crc.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A57 feat-crc
> +#as: -mcpu=cortex-a57
> +#source: feat-crc.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A57"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a57-feat-simd.d b/gas/testsuite/gas/arm/mcpu-cortex-a57-feat-simd.d
> new file mode 100644
> index 00000000000..48fc50eaf60
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a57-feat-simd.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A57 feat-simd
> +#as: -mcpu=cortex-a57
> +#source: feat-simd.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A57"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a7-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a7-attrs.d
> new file mode 100644
> index 00000000000..20f0d4b02c8
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a7-attrs.d
> @@ -0,0 +1,17 @@
> +#name: Cortex-A7 Attributes
> +#as: -mcpu=cortex-a7+nofp+nosimd
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A7"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_MPextension_use: Allowed
> +  Tag_DIV_use: Allowed in v7-A with integer division extension
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a7-feat-simd.d b/gas/testsuite/gas/arm/mcpu-cortex-a7-feat-simd.d
> new file mode 100644
> index 00000000000..b0c59f22900
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a7-feat-simd.d
> @@ -0,0 +1,19 @@
> +#name: Cortex-A7 feat-simd
> +#as: -mcpu=cortex-a7
> +#source: feat-simd.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A7"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: VFPv4
> +  Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
> +  Tag_MPextension_use: Allowed
> +  Tag_DIV_use: Allowed in v7-A with integer division extension
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a710-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a710-attrs.d
> new file mode 100644
> index 00000000000..dac147dfb51
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a710-attrs.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A710 Attributes
> +#as: -mcpu=cortex-a710+crypto
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A710"
> +  Tag_CPU_arch: v9
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a710-feat-bf16.d b/gas/testsuite/gas/arm/mcpu-cortex-a710-feat-bf16.d
> new file mode 100644
> index 00000000000..b53d648d5ad
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a710-feat-bf16.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A710 feat-bf16
> +#as: -mcpu=cortex-a710
> +#source: feat-bf16.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A710"
> +  Tag_CPU_arch: v9
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a710-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-a710-feat-fp16.d
> new file mode 100644
> index 00000000000..b2a2c376c64
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a710-feat-fp16.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A710 feat-fp16
> +#as: -mcpu=cortex-a710
> +#source: feat-fp16.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A710"
> +  Tag_CPU_arch: v9
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a710-feat-i8mm.d b/gas/testsuite/gas/arm/mcpu-cortex-a710-feat-i8mm.d
> new file mode 100644
> index 00000000000..c682f38d31c
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a710-feat-i8mm.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A710 feat-i8mm
> +#as: -mcpu=cortex-a710
> +#source: feat-i8mm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A710"
> +  Tag_CPU_arch: v9
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a72-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a72-attrs.d
> new file mode 100644
> index 00000000000..6c16d2ae6d6
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a72-attrs.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A72 Attributes
> +#as: -mcpu=cortex-a72+crypto
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A72"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a72-feat-crc.d b/gas/testsuite/gas/arm/mcpu-cortex-a72-feat-crc.d
> new file mode 100644
> index 00000000000..8f3b7002250
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a72-feat-crc.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A72 feat-crc
> +#as: -mcpu=cortex-a72
> +#source: feat-crc.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A72"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a72-feat-simd.d b/gas/testsuite/gas/arm/mcpu-cortex-a72-feat-simd.d
> new file mode 100644
> index 00000000000..3cad2ec1b5e
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a72-feat-simd.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A72 feat-simd
> +#as: -mcpu=cortex-a72
> +#source: feat-simd.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A72"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a73-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a73-attrs.d
> new file mode 100644
> index 00000000000..07df89b796a
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a73-attrs.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A73 Attributes
> +#as: -mcpu=cortex-a73+crypto
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A73"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a73-feat-crc.d b/gas/testsuite/gas/arm/mcpu-cortex-a73-feat-crc.d
> new file mode 100644
> index 00000000000..ca750aaf6fd
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a73-feat-crc.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A73 feat-crc
> +#as: -mcpu=cortex-a73
> +#source: feat-crc.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A73"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a73-feat-simd.d b/gas/testsuite/gas/arm/mcpu-cortex-a73-feat-simd.d
> new file mode 100644
> index 00000000000..7475b25de40
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a73-feat-simd.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A73 feat-simd
> +#as: -mcpu=cortex-a73
> +#source: feat-simd.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A73"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a75-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a75-attrs.d
> new file mode 100644
> index 00000000000..cc88ad25c11
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a75-attrs.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A75 Attributes
> +#as: -mcpu=cortex-a75+crypto
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A75"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a75-feat-dotprod.d b/gas/testsuite/gas/arm/mcpu-cortex-a75-feat-dotprod.d
> new file mode 100644
> index 00000000000..83ee9088ad0
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a75-feat-dotprod.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A75 feat-dotprod
> +#as: -mcpu=cortex-a75
> +#source: feat-dotprod.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A75"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a75-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-a75-feat-fp16.d
> new file mode 100644
> index 00000000000..c996200a244
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a75-feat-fp16.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A75 feat-fp16
> +#as: -mcpu=cortex-a75
> +#source: feat-fp16.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A75"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a76-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a76-attrs.d
> new file mode 100644
> index 00000000000..088939c0559
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a76-attrs.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A76 Attributes
> +#as: -mcpu=cortex-a76+crypto
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A76"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a76-feat-dotprod.d b/gas/testsuite/gas/arm/mcpu-cortex-a76-feat-dotprod.d
> new file mode 100644
> index 00000000000..720ea69608f
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a76-feat-dotprod.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A76 feat-dotprod
> +#as: -mcpu=cortex-a76
> +#source: feat-dotprod.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A76"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a76-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-a76-feat-fp16.d
> new file mode 100644
> index 00000000000..c9632960f64
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a76-feat-fp16.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A76 feat-fp16
> +#as: -mcpu=cortex-a76
> +#source: feat-fp16.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A76"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a76ae-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a76ae-attrs.d
> new file mode 100644
> index 00000000000..ed050b3e2da
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a76ae-attrs.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A76AE Attributes
> +#as: -mcpu=cortex-a76ae+crypto
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A76AE"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a76ae-feat-dotprod.d b/gas/testsuite/gas/arm/mcpu-cortex-a76ae-feat-dotprod.d
> new file mode 100644
> index 00000000000..449e70ccf5e
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a76ae-feat-dotprod.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A76AE feat-dotprod
> +#as: -mcpu=cortex-a76ae
> +#source: feat-dotprod.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A76AE"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a76ae-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-a76ae-feat-fp16.d
> new file mode 100644
> index 00000000000..43af92dd16a
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a76ae-feat-fp16.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A76AE feat-fp16
> +#as: -mcpu=cortex-a76ae
> +#source: feat-fp16.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A76AE"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a77-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a77-attrs.d
> new file mode 100644
> index 00000000000..e014c789449
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a77-attrs.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A77 Attributes
> +#as: -mcpu=cortex-a77+crypto
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A77"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a77-feat-dotprod.d b/gas/testsuite/gas/arm/mcpu-cortex-a77-feat-dotprod.d
> new file mode 100644
> index 00000000000..7cccf0feec1
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a77-feat-dotprod.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A77 feat-dotprod
> +#as: -mcpu=cortex-a77
> +#source: feat-dotprod.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A77"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a77-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-a77-feat-fp16.d
> new file mode 100644
> index 00000000000..97fe61e0f09
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a77-feat-fp16.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A77 feat-fp16
> +#as: -mcpu=cortex-a77
> +#source: feat-fp16.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A77"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a78-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a78-attrs.d
> new file mode 100644
> index 00000000000..73c5e070aaf
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a78-attrs.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A78 Attributes
> +#as: -mcpu=cortex-a78+crypto
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A78"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a78-feat-dotprod.d b/gas/testsuite/gas/arm/mcpu-cortex-a78-feat-dotprod.d
> new file mode 100644
> index 00000000000..eeb2260163b
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a78-feat-dotprod.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A78 feat-dotprod
> +#as: -mcpu=cortex-a78
> +#source: feat-dotprod.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A78"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a78-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-a78-feat-fp16.d
> new file mode 100644
> index 00000000000..88936f78c3f
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a78-feat-fp16.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A78 feat-fp16
> +#as: -mcpu=cortex-a78
> +#source: feat-fp16.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A78"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a78ae-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a78ae-attrs.d
> new file mode 100644
> index 00000000000..944c21f2530
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a78ae-attrs.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A78AE Attributes
> +#as: -mcpu=cortex-a78ae+crypto
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A78AE"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a78ae-feat-dotprod.d b/gas/testsuite/gas/arm/mcpu-cortex-a78ae-feat-dotprod.d
> new file mode 100644
> index 00000000000..8d24972514d
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a78ae-feat-dotprod.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A78AE feat-dotprod
> +#as: -mcpu=cortex-a78ae
> +#source: feat-dotprod.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A78AE"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a78ae-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-a78ae-feat-fp16.d
> new file mode 100644
> index 00000000000..07d142b24fe
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a78ae-feat-fp16.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A78AE feat-fp16
> +#as: -mcpu=cortex-a78ae
> +#source: feat-fp16.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A78AE"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a78c-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a78c-attrs.d
> new file mode 100644
> index 00000000000..bd0a9d8a455
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a78c-attrs.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A78C Attributes
> +#as: -mcpu=cortex-a78c+crypto
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A78C"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a78c-feat-dotprod.d b/gas/testsuite/gas/arm/mcpu-cortex-a78c-feat-dotprod.d
> new file mode 100644
> index 00000000000..67027068b23
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a78c-feat-dotprod.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A78C feat-dotprod
> +#as: -mcpu=cortex-a78c
> +#source: feat-dotprod.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A78C"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a78c-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-a78c-feat-fp16.d
> new file mode 100644
> index 00000000000..f45fc34dc2a
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a78c-feat-fp16.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A78C feat-fp16
> +#as: -mcpu=cortex-a78c
> +#source: feat-fp16.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A78C"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a8-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a8-attrs.d
> new file mode 100644
> index 00000000000..5b1696f3f0a
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a8-attrs.d
> @@ -0,0 +1,15 @@
> +#name: Cortex-A8 Attributes
> +#as: -mcpu=cortex-a8+nofp
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A8"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_Virtualization_use: TrustZone
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a8-feat-simd.d b/gas/testsuite/gas/arm/mcpu-cortex-a8-feat-simd.d
> new file mode 100644
> index 00000000000..e8de97b31da
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a8-feat-simd.d
> @@ -0,0 +1,17 @@
> +#name: Cortex-A8 feat-simd
> +#as: -mcpu=cortex-a8
> +#source: feat-simd.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A8"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: VFPv3
> +  Tag_Advanced_SIMD_arch: NEONv1
> +  Tag_Virtualization_use: TrustZone
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a9-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-a9-attrs.d
> new file mode 100644
> index 00000000000..4d1ebaa9dab
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a9-attrs.d
> @@ -0,0 +1,16 @@
> +#name: Cortex-A9 Attributes
> +#as: -mcpu=cortex-a9+nofp+nosimd
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A9"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a9-feat-mp.d b/gas/testsuite/gas/arm/mcpu-cortex-a9-feat-mp.d
> new file mode 100644
> index 00000000000..96ecaaf32b7
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a9-feat-mp.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A9 feat-mp
> +#as: -mcpu=cortex-a9
> +#source: feat-mp.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A9"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: VFPv4
> +  Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a9-feat-neon-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-a9-feat-neon-fp16.d
> new file mode 100644
> index 00000000000..83ecc83db6f
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a9-feat-neon-fp16.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A9 feat-neon-fp16
> +#as: -mcpu=cortex-a9
> +#source: feat-neon-fp16.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A9"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: VFPv4
> +  Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-a9-feat-sec.d b/gas/testsuite/gas/arm/mcpu-cortex-a9-feat-sec.d
> new file mode 100644
> index 00000000000..73386c2bb82
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-a9-feat-sec.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-A9 feat-sec
> +#as: -mcpu=cortex-a9
> +#source: feat-sec.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-A9"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: VFPv4
> +  Tag_Advanced_SIMD_arch: NEONv1 with Fused-MAC
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m33-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-m33-attrs.d
> new file mode 100644
> index 00000000000..d2195500a43
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-m33-attrs.d
> @@ -0,0 +1,13 @@
> +#name: Cortex-M33 Attributes
> +#as: -mcpu=cortex-m33+nofp+nodsp
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-M33"
> +  Tag_CPU_arch: v8-M.mainline
> +  Tag_CPU_arch_profile: Microcontroller
> +  Tag_THUMB_ISA_use: Yes
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m33-feat-dsp.d b/gas/testsuite/gas/arm/mcpu-cortex-m33-feat-dsp.d
> new file mode 100644
> index 00000000000..521846cdcc2
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-m33-feat-dsp.d
> @@ -0,0 +1,15 @@
> +#name: Cortex-M33 feat-dsp
> +#as: -mcpu=cortex-m33
> +#source: feat-dsp.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-M33"
> +  Tag_CPU_arch: v8-M.mainline
> +  Tag_CPU_arch_profile: Microcontroller
> +  Tag_THUMB_ISA_use: Yes
> +  Tag_FP_arch: VFPv4-D16
> +  Tag_DSP_extension: Allowed
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m33-feat-fp-vfpv5.d b/gas/testsuite/gas/arm/mcpu-cortex-m33-feat-fp-vfpv5.d
> new file mode 100644
> index 00000000000..6624dbac797
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-m33-feat-fp-vfpv5.d
> @@ -0,0 +1,15 @@
> +#name: Cortex-M33 feat-fp-vfpv5
> +#as: -mcpu=cortex-m33
> +#source: feat-fp-vfpv5.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-M33"
> +  Tag_CPU_arch: v8-M.mainline
> +  Tag_CPU_arch_profile: Microcontroller
> +  Tag_THUMB_ISA_use: Yes
> +  Tag_FP_arch: VFPv4-D16
> +  Tag_DSP_extension: Allowed
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m35p-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-m35p-attrs.d
> new file mode 100644
> index 00000000000..e8bb5884eac
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-m35p-attrs.d
> @@ -0,0 +1,13 @@
> +#name: Cortex-M35P Attributes
> +#as: -mcpu=cortex-m35p+nofp+nodsp
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-M35P"
> +  Tag_CPU_arch: v8-M.mainline
> +  Tag_CPU_arch_profile: Microcontroller
> +  Tag_THUMB_ISA_use: Yes
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m35p-feat-dsp.d b/gas/testsuite/gas/arm/mcpu-cortex-m35p-feat-dsp.d
> new file mode 100644
> index 00000000000..12b6b6dfbfa
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-m35p-feat-dsp.d
> @@ -0,0 +1,15 @@
> +#name: Cortex-M35P feat-dsp
> +#as: -mcpu=cortex-m35p
> +#source: feat-dsp.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-M35P"
> +  Tag_CPU_arch: v8-M.mainline
> +  Tag_CPU_arch_profile: Microcontroller
> +  Tag_THUMB_ISA_use: Yes
> +  Tag_FP_arch: VFPv4-D16
> +  Tag_DSP_extension: Allowed
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m35p-feat-fp-vfpv5.d b/gas/testsuite/gas/arm/mcpu-cortex-m35p-feat-fp-vfpv5.d
> new file mode 100644
> index 00000000000..918942ba693
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-m35p-feat-fp-vfpv5.d
> @@ -0,0 +1,15 @@
> +#name: Cortex-M35P feat-fp-vfpv5
> +#as: -mcpu=cortex-m35p
> +#source: feat-fp-vfpv5.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-M35P"
> +  Tag_CPU_arch: v8-M.mainline
> +  Tag_CPU_arch_profile: Microcontroller
> +  Tag_THUMB_ISA_use: Yes
> +  Tag_FP_arch: VFPv4-D16
> +  Tag_DSP_extension: Allowed
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m4-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-m4-attrs.d
> new file mode 100644
> index 00000000000..e27944539d7
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-m4-attrs.d
> @@ -0,0 +1,13 @@
> +#name: Cortex-M4 Attributes
> +#as: -mcpu=cortex-m4+nofp
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-M4"
> +  Tag_CPU_arch: v7E-M
> +  Tag_CPU_arch_profile: Microcontroller
> +  Tag_THUMB_ISA_use: Thumb-2
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m4-feat-fp-vfpv3.d b/gas/testsuite/gas/arm/mcpu-cortex-m4-feat-fp-vfpv3.d
> new file mode 100644
> index 00000000000..c66e37244bc
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-m4-feat-fp-vfpv3.d
> @@ -0,0 +1,15 @@
> +#name: Cortex-M4 feat-fp-vfpv3
> +#as: -mcpu=cortex-m4
> +#source: feat-fp-vfpv3.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-M4"
> +  Tag_CPU_arch: v7E-M
> +  Tag_CPU_arch_profile: Microcontroller
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: VFPv4-D16
> +  Tag_ABI_HardFP_use: SP only
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m52-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-m52-attrs.d
> new file mode 100644
> index 00000000000..3e32853c951
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-m52-attrs.d
> @@ -0,0 +1,14 @@
> +#name: Cortex-M52 Attributes
> +#as: -mcpu=cortex-m52+nopacbti+nomve.fp+nomve+nofp+nodsp
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-M52"
> +  Tag_CPU_arch: v8.1-M.mainline
> +  Tag_CPU_arch_profile: Microcontroller
> +  Tag_THUMB_ISA_use: Yes
> +  Tag_DSP_extension: Allowed
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m52-attrs1.d b/gas/testsuite/gas/arm/mcpu-cortex-m52-attrs1.d
> new file mode 100644
> index 00000000000..d378a5d4e01
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-m52-attrs1.d
> @@ -0,0 +1,16 @@
> +#name: Cortex-M52 Attributes 1
> +#as: -mcpu=cortex-m52+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-M52"
> +  Tag_CPU_arch: v8.1-M.mainline
> +  Tag_CPU_arch_profile: Microcontroller
> +  Tag_THUMB_ISA_use: Yes
> +  Tag_FP_arch: FPv5/FP-D16 for ARMv8
> +  Tag_DSP_extension: Allowed
> +  Tag_MVE_arch: MVE Integer and FP
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m52-feat-fp-dp.d b/gas/testsuite/gas/arm/mcpu-cortex-m52-feat-fp-dp.d
> new file mode 100644
> index 00000000000..fe47c58bd0d
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-m52-feat-fp-dp.d
> @@ -0,0 +1,16 @@
> +#name: Cortex-M52 feat-fp.dp
> +#as: -mcpu=cortex-m52
> +#source: feat-fp.dp.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-M52"
> +  Tag_CPU_arch: v8.1-M.mainline
> +  Tag_CPU_arch_profile: Microcontroller
> +  Tag_THUMB_ISA_use: Yes
> +  Tag_FP_arch: FPv5/FP-D16 for ARMv8
> +  Tag_DSP_extension: Allowed
> +  Tag_MVE_arch: MVE Integer and FP
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m52-feat-mve-fp.d b/gas/testsuite/gas/arm/mcpu-cortex-m52-feat-mve-fp.d
> new file mode 100644
> index 00000000000..e87ce8184fe
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-m52-feat-mve-fp.d
> @@ -0,0 +1,16 @@
> +#name: Cortex-M52 feat-mve.fp
> +#as: -mcpu=cortex-m52
> +#source: feat-mve.fp.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-M52"
> +  Tag_CPU_arch: v8.1-M.mainline
> +  Tag_CPU_arch_profile: Microcontroller
> +  Tag_THUMB_ISA_use: Yes
> +  Tag_FP_arch: FPv5/FP-D16 for ARMv8
> +  Tag_DSP_extension: Allowed
> +  Tag_MVE_arch: MVE Integer and FP
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m52-feat-pacbti.d b/gas/testsuite/gas/arm/mcpu-cortex-m52-feat-pacbti.d
> new file mode 100644
> index 00000000000..e04aae72a08
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-m52-feat-pacbti.d
> @@ -0,0 +1,16 @@
> +#name: Cortex-M52 feat-pacbti
> +#as: -mcpu=cortex-m52
> +#source: feat-pacbti.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-M52"
> +  Tag_CPU_arch: v8.1-M.mainline
> +  Tag_CPU_arch_profile: Microcontroller
> +  Tag_THUMB_ISA_use: Yes
> +  Tag_FP_arch: FPv5/FP-D16 for ARMv8
> +  Tag_DSP_extension: Allowed
> +  Tag_MVE_arch: MVE Integer and FP
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m55-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-m55-attrs.d
> new file mode 100644
> index 00000000000..b873ecdb2f5
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-m55-attrs.d
> @@ -0,0 +1,14 @@
> +#name: Cortex-M55 Attributes
> +#as: -mcpu=cortex-m55+nomve.fp+nomve+nofp+nodsp
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-M55"
> +  Tag_CPU_arch: v8.1-M.mainline
> +  Tag_CPU_arch_profile: Microcontroller
> +  Tag_THUMB_ISA_use: Yes
> +  Tag_DSP_extension: Allowed
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m55-attrs1.d b/gas/testsuite/gas/arm/mcpu-cortex-m55-attrs1.d
> new file mode 100644
> index 00000000000..a5b181fc067
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-m55-attrs1.d
> @@ -0,0 +1,16 @@
> +#name: Cortex-M55 Attributes 1
> +#as: -mcpu=cortex-m55+cdecp0+cdecp1+cdecp2+cdecp3+cdecp4+cdecp5+cdecp6+cdecp7
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-M55"
> +  Tag_CPU_arch: v8.1-M.mainline
> +  Tag_CPU_arch_profile: Microcontroller
> +  Tag_THUMB_ISA_use: Yes
> +  Tag_FP_arch: FPv5/FP-D16 for ARMv8
> +  Tag_DSP_extension: Allowed
> +  Tag_MVE_arch: MVE Integer and FP
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m55-feat-fp-dp.d b/gas/testsuite/gas/arm/mcpu-cortex-m55-feat-fp-dp.d
> new file mode 100644
> index 00000000000..29e7bc9f8b6
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-m55-feat-fp-dp.d
> @@ -0,0 +1,16 @@
> +#name: Cortex-M55 feat-fp.dp
> +#as: -mcpu=cortex-m55
> +#source: feat-fp.dp.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-M55"
> +  Tag_CPU_arch: v8.1-M.mainline
> +  Tag_CPU_arch_profile: Microcontroller
> +  Tag_THUMB_ISA_use: Yes
> +  Tag_FP_arch: FPv5/FP-D16 for ARMv8
> +  Tag_DSP_extension: Allowed
> +  Tag_MVE_arch: MVE Integer and FP
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m55-feat-mve-fp.d b/gas/testsuite/gas/arm/mcpu-cortex-m55-feat-mve-fp.d
> new file mode 100644
> index 00000000000..9ec48163df6
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-m55-feat-mve-fp.d
> @@ -0,0 +1,16 @@
> +#name: Cortex-M55 feat-mve.fp
> +#as: -mcpu=cortex-m55
> +#source: feat-mve.fp.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-M55"
> +  Tag_CPU_arch: v8.1-M.mainline
> +  Tag_CPU_arch_profile: Microcontroller
> +  Tag_THUMB_ISA_use: Yes
> +  Tag_FP_arch: FPv5/FP-D16 for ARMv8
> +  Tag_DSP_extension: Allowed
> +  Tag_MVE_arch: MVE Integer and FP
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m7-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-m7-attrs.d
> new file mode 100644
> index 00000000000..ad3faf91c1e
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-m7-attrs.d
> @@ -0,0 +1,13 @@
> +#name: Cortex-M7 Attributes
> +#as: -mcpu=cortex-m7+nofp+nofp.dp
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-M7"
> +  Tag_CPU_arch: v7E-M
> +  Tag_CPU_arch_profile: Microcontroller
> +  Tag_THUMB_ISA_use: Thumb-2
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m7-feat-fp-dp.d b/gas/testsuite/gas/arm/mcpu-cortex-m7-feat-fp-dp.d
> new file mode 100644
> index 00000000000..46045a1a3a5
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-m7-feat-fp-dp.d
> @@ -0,0 +1,14 @@
> +#name: Cortex-M7 feat-fp.dp
> +#as: -mcpu=cortex-m7
> +#source: feat-fp.dp.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-M7"
> +  Tag_CPU_arch: v7E-M
> +  Tag_CPU_arch_profile: Microcontroller
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FPv5/FP-D16 for ARMv8
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m85-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-m85-attrs.d
> new file mode 100644
> index 00000000000..558cacd4ba8
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-m85-attrs.d
> @@ -0,0 +1,14 @@
> +#name: Cortex-M85 Attributes
> +#as: -mcpu=cortex-m85+nopacbti+nomve.fp+nomve+nofp+nodsp
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-M85"
> +  Tag_CPU_arch: v8.1-M.mainline
> +  Tag_CPU_arch_profile: Microcontroller
> +  Tag_THUMB_ISA_use: Yes
> +  Tag_DSP_extension: Allowed
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m85-feat-fp-dp.d b/gas/testsuite/gas/arm/mcpu-cortex-m85-feat-fp-dp.d
> new file mode 100644
> index 00000000000..711bea59a91
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-m85-feat-fp-dp.d
> @@ -0,0 +1,16 @@
> +#name: Cortex-M85 feat-fp.dp
> +#as: -mcpu=cortex-m85
> +#source: feat-fp.dp.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-M85"
> +  Tag_CPU_arch: v8.1-M.mainline
> +  Tag_CPU_arch_profile: Microcontroller
> +  Tag_THUMB_ISA_use: Yes
> +  Tag_FP_arch: FPv5/FP-D16 for ARMv8
> +  Tag_DSP_extension: Allowed
> +  Tag_MVE_arch: MVE Integer and FP
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m85-feat-mve-fp.d b/gas/testsuite/gas/arm/mcpu-cortex-m85-feat-mve-fp.d
> new file mode 100644
> index 00000000000..6533fc66e4e
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-m85-feat-mve-fp.d
> @@ -0,0 +1,16 @@
> +#name: Cortex-M85 feat-mve.fp
> +#as: -mcpu=cortex-m85
> +#source: feat-mve.fp.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-M85"
> +  Tag_CPU_arch: v8.1-M.mainline
> +  Tag_CPU_arch_profile: Microcontroller
> +  Tag_THUMB_ISA_use: Yes
> +  Tag_FP_arch: FPv5/FP-D16 for ARMv8
> +  Tag_DSP_extension: Allowed
> +  Tag_MVE_arch: MVE Integer and FP
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-m85-feat-pacbti.d b/gas/testsuite/gas/arm/mcpu-cortex-m85-feat-pacbti.d
> new file mode 100644
> index 00000000000..dc615de9327
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-m85-feat-pacbti.d
> @@ -0,0 +1,16 @@
> +#name: Cortex-M85 feat-pacbti
> +#as: -mcpu=cortex-m85
> +#source: feat-pacbti.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-M85"
> +  Tag_CPU_arch: v8.1-M.mainline
> +  Tag_CPU_arch_profile: Microcontroller
> +  Tag_THUMB_ISA_use: Yes
> +  Tag_FP_arch: FPv5/FP-D16 for ARMv8
> +  Tag_DSP_extension: Allowed
> +  Tag_MVE_arch: MVE Integer and FP
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r4f-feat-fp-vfpv3.d b/gas/testsuite/gas/arm/mcpu-cortex-r4f-feat-fp-vfpv3.d
> new file mode 100644
> index 00000000000..a6361398eb9
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-r4f-feat-fp-vfpv3.d
> @@ -0,0 +1,15 @@
> +#name: Cortex R4F feat-fp-vfpv3
> +#as: -mcpu=cortex-r4f
> +#source: feat-fp-vfpv3.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-R4F"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Realtime
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: VFPv3-D16
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r5-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-r5-attrs.d
> new file mode 100644
> index 00000000000..802ee1cb00a
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-r5-attrs.d
> @@ -0,0 +1,15 @@
> +#name: Cortex-R5 Attributes
> +#as: -mcpu=cortex-r5+nofp+nofp.dp
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-R5"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Realtime
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_DIV_use: Allowed in v7-A with integer division extension
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r5-feat-fp-vfpv3.d b/gas/testsuite/gas/arm/mcpu-cortex-r5-feat-fp-vfpv3.d
> new file mode 100644
> index 00000000000..4ee716dfe6a
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-r5-feat-fp-vfpv3.d
> @@ -0,0 +1,16 @@
> +#name: Cortex-R5 feat-fp-vfpv3
> +#as: -mcpu=cortex-r5
> +#source: feat-fp-vfpv3.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-R5"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Realtime
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: VFPv3
> +  Tag_DIV_use: Allowed in v7-A with integer division extension
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r5-feat-idiv.d b/gas/testsuite/gas/arm/mcpu-cortex-r5-feat-idiv.d
> new file mode 100644
> index 00000000000..71b2d2ee073
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-r5-feat-idiv.d
> @@ -0,0 +1,16 @@
> +#name: Cortex-R5 feat-idiv
> +#as: -mcpu=cortex-r5
> +#source: feat-idiv.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-R5"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Realtime
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: VFPv3
> +  Tag_DIV_use: Allowed in v7-A with integer division extension
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r52-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-r52-attrs.d
> new file mode 100644
> index 00000000000..33422be2cce
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-r52-attrs.d
> @@ -0,0 +1,17 @@
> +#name: Cortex-R52 Attributes
> +#as: -mcpu=cortex-r52+nofp.dp
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-R52"
> +  Tag_CPU_arch: v8-R
> +  Tag_CPU_arch_profile: Realtime
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FPv5/FP-D16 for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r52-feat-crc.d b/gas/testsuite/gas/arm/mcpu-cortex-r52-feat-crc.d
> new file mode 100644
> index 00000000000..71055cce2a2
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-r52-feat-crc.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-R52 feat-crc
> +#as: -mcpu=cortex-r52
> +#source: feat-crc.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-R52"
> +  Tag_CPU_arch: v8-R
> +  Tag_CPU_arch_profile: Realtime
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r52-feat-simd.d b/gas/testsuite/gas/arm/mcpu-cortex-r52-feat-simd.d
> new file mode 100644
> index 00000000000..148400ef1d9
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-r52-feat-simd.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-R52 feat-simd
> +#as: -mcpu=cortex-r52
> +#source: feat-simd.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-R52"
> +  Tag_CPU_arch: v8-R
> +  Tag_CPU_arch_profile: Realtime
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r52plus-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-r52plus-attrs.d
> new file mode 100644
> index 00000000000..e2eb9c35fe7
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-r52plus-attrs.d
> @@ -0,0 +1,17 @@
> +#name: Cortex-R52plus Attributes
> +#as: -mcpu=cortex-r52plus+nofp.dp
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-R52\+"
> +  Tag_CPU_arch: v8-R
> +  Tag_CPU_arch_profile: Realtime
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FPv5/FP-D16 for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r52plus-feat-crc.d b/gas/testsuite/gas/arm/mcpu-cortex-r52plus-feat-crc.d
> new file mode 100644
> index 00000000000..2666aaf1588
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-r52plus-feat-crc.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-R52plus feat-crc
> +#as: -mcpu=cortex-r52plus
> +#source: feat-crc.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-R52\+"
> +  Tag_CPU_arch: v8-R
> +  Tag_CPU_arch_profile: Realtime
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r52plus-feat-simd.d b/gas/testsuite/gas/arm/mcpu-cortex-r52plus-feat-simd.d
> new file mode 100644
> index 00000000000..1af6862ca1c
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-r52plus-feat-simd.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-R52plus feat-simd
> +#as: -mcpu=cortex-r52plus
> +#source: feat-simd.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-R52\+"
> +  Tag_CPU_arch: v8-R
> +  Tag_CPU_arch_profile: Realtime
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r7-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-r7-attrs.d
> new file mode 100644
> index 00000000000..b8fa7c90c1b
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-r7-attrs.d
> @@ -0,0 +1,15 @@
> +#name: Cortex-R7 Attributes
> +#as: -mcpu=cortex-r7+nofp+nofp.dp
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-R7"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Realtime
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_DIV_use: Allowed in v7-A with integer division extension
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r7-feat-idiv.d b/gas/testsuite/gas/arm/mcpu-cortex-r7-feat-idiv.d
> new file mode 100644
> index 00000000000..ac04305c3a3
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-r7-feat-idiv.d
> @@ -0,0 +1,17 @@
> +#name: Cortex-R7 feat-idiv
> +#as: -mcpu=cortex-r7
> +#source: feat-idiv.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-R7"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Realtime
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: VFPv3-D16
> +  Tag_FP_HP_extension: Allowed
> +  Tag_DIV_use: Allowed in v7-A with integer division extension
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r7-feat-vfpv3-d16-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-r7-feat-vfpv3-d16-fp16.d
> new file mode 100644
> index 00000000000..9361607a70c
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-r7-feat-vfpv3-d16-fp16.d
> @@ -0,0 +1,17 @@
> +#name: Cortex-R7 feat-vfpv3-d16-fp16
> +#as: -mcpu=cortex-r7
> +#source: feat-vfpv3-d16-fp16.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-R7"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Realtime
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: VFPv3-D16
> +  Tag_FP_HP_extension: Allowed
> +  Tag_DIV_use: Allowed in v7-A with integer division extension
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r8-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-r8-attrs.d
> new file mode 100644
> index 00000000000..2bd0bf4378d
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-r8-attrs.d
> @@ -0,0 +1,15 @@
> +#name: Cortex-R8 Attributes
> +#as: -mcpu=cortex-r8+nofp+nofp.dp
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-R8"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Realtime
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_DIV_use: Allowed in v7-A with integer division extension
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r8-feat-idiv.d b/gas/testsuite/gas/arm/mcpu-cortex-r8-feat-idiv.d
> new file mode 100644
> index 00000000000..df3f2b561ef
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-r8-feat-idiv.d
> @@ -0,0 +1,17 @@
> +#name: Cortex-R8 feat-idiv
> +#as: -mcpu=cortex-r8
> +#source: feat-idiv.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-R8"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Realtime
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: VFPv3-D16
> +  Tag_FP_HP_extension: Allowed
> +  Tag_DIV_use: Allowed in v7-A with integer division extension
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-r8-feat-vfpv3-d16-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-r8-feat-vfpv3-d16-fp16.d
> new file mode 100644
> index 00000000000..09a254d76ca
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-r8-feat-vfpv3-d16-fp16.d
> @@ -0,0 +1,17 @@
> +#name: Cortex-R8 feat-vfpv3-d16-fp16
> +#as: -mcpu=cortex-r8
> +#source: feat-vfpv3-d16-fp16.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-R8"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Realtime
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: VFPv3-D16
> +  Tag_FP_HP_extension: Allowed
> +  Tag_DIV_use: Allowed in v7-A with integer division extension
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-x1-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-x1-attrs.d
> new file mode 100644
> index 00000000000..960aed9ac94
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-x1-attrs.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-X1 Attributes
> +#as: -mcpu=cortex-x1+crypto
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-X1"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-x1-feat-dotprod.d b/gas/testsuite/gas/arm/mcpu-cortex-x1-feat-dotprod.d
> new file mode 100644
> index 00000000000..e49e914757d
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-x1-feat-dotprod.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-X1 feat-dotprod
> +#as: -mcpu=cortex-x1
> +#source: feat-dotprod.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-X1"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-x1-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-x1-feat-fp16.d
> new file mode 100644
> index 00000000000..3bdf1c2557b
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-x1-feat-fp16.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-X1 feat-fp16
> +#as: -mcpu=cortex-x1
> +#source: feat-fp16.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-X1"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-x1c-attrs.d b/gas/testsuite/gas/arm/mcpu-cortex-x1c-attrs.d
> new file mode 100644
> index 00000000000..1e9d8e147eb
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-x1c-attrs.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-X1C Attributes
> +#as: -mcpu=cortex-x1c+crypto
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-X1C"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-x1c-feat-dotprod.d b/gas/testsuite/gas/arm/mcpu-cortex-x1c-feat-dotprod.d
> new file mode 100644
> index 00000000000..186b4068b0a
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-x1c-feat-dotprod.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-X1C feat-dotprod
> +#as: -mcpu=cortex-x1c
> +#source: feat-dotprod.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-X1C"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-cortex-x1c-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-cortex-x1c-feat-fp16.d
> new file mode 100644
> index 00000000000..23c70c14a23
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-cortex-x1c-feat-fp16.d
> @@ -0,0 +1,18 @@
> +#name: Cortex-X1C feat-fp16
> +#as: -mcpu=cortex-x1c
> +#source: feat-fp16.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Cortex-X1C"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-exynos-m1-attrs.d b/gas/testsuite/gas/arm/mcpu-exynos-m1-attrs.d
> new file mode 100644
> index 00000000000..f898b63bef3
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-exynos-m1-attrs.d
> @@ -0,0 +1,18 @@
> +#name: Exynos-M1 Attributes
> +#as: -mcpu=exynos-m1+crypto
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Samsung Exynos M1"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-exynos-m1-feat-crc.d b/gas/testsuite/gas/arm/mcpu-exynos-m1-feat-crc.d
> new file mode 100644
> index 00000000000..ca932b7330a
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-exynos-m1-feat-crc.d
> @@ -0,0 +1,18 @@
> +#name: Exynos-M1 feat-crc
> +#as: -mcpu=exynos-m1
> +#source: feat-crc.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Samsung Exynos M1"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-exynos-m1-feat-simd.d b/gas/testsuite/gas/arm/mcpu-exynos-m1-feat-simd.d
> new file mode 100644
> index 00000000000..0e2976aa4f9
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-exynos-m1-feat-simd.d
> @@ -0,0 +1,18 @@
> +#name: Exynos-M1 feat-simd
> +#as: -mcpu=exynos-m1
> +#source: feat-simd.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Samsung Exynos M1"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-marvell-pj4-feat-fp-vfpv3.d b/gas/testsuite/gas/arm/mcpu-marvell-pj4-feat-fp-vfpv3.d
> new file mode 100644
> index 00000000000..2f0e17e4338
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-marvell-pj4-feat-fp-vfpv3.d
> @@ -0,0 +1,17 @@
> +#name: Marvell-PJ4 feat-fp-vfpv3
> +#as: -mcpu=marvell-pj4
> +#source: feat-fp-vfpv3.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "MARVELL-PJ4"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: VFPv3
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone
> diff --git a/gas/testsuite/gas/arm/mcpu-marvell-pj4-feat-mp.d b/gas/testsuite/gas/arm/mcpu-marvell-pj4-feat-mp.d
> new file mode 100644
> index 00000000000..67bbd6c916d
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-marvell-pj4-feat-mp.d
> @@ -0,0 +1,17 @@
> +#name: Marvell-PJ4 feat-mp
> +#as: -mcpu=marvell-pj4
> +#source: feat-mp.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "MARVELL-PJ4"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: VFPv3
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone
> diff --git a/gas/testsuite/gas/arm/mcpu-marvell-pj4-feat-sec.d b/gas/testsuite/gas/arm/mcpu-marvell-pj4-feat-sec.d
> new file mode 100644
> index 00000000000..aa41494cf7d
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-marvell-pj4-feat-sec.d
> @@ -0,0 +1,17 @@
> +#name: Marvell-PJ4 feat-sec
> +#as: -mcpu=marvell-pj4
> +#source: feat-sec.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "MARVELL-PJ4"
> +  Tag_CPU_arch: v7
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: VFPv3
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone
> diff --git a/gas/testsuite/gas/arm/mcpu-neoverse-n1-attrs.d b/gas/testsuite/gas/arm/mcpu-neoverse-n1-attrs.d
> new file mode 100644
> index 00000000000..c850ee0b139
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-neoverse-n1-attrs.d
> @@ -0,0 +1,18 @@
> +#name: Neoverse-N1 Attributes
> +#as: -mcpu=neoverse-n1+crypto
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Neoverse N1"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-neoverse-n1-feat-dotprod.d b/gas/testsuite/gas/arm/mcpu-neoverse-n1-feat-dotprod.d
> new file mode 100644
> index 00000000000..b35d1ee4c44
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-neoverse-n1-feat-dotprod.d
> @@ -0,0 +1,18 @@
> +#name: Neoverse-N1 feat-dotprod
> +#as: -mcpu=neoverse-n1
> +#source: feat-dotprod.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Neoverse N1"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-neoverse-n1-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-neoverse-n1-feat-fp16.d
> new file mode 100644
> index 00000000000..36a02e8dc24
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-neoverse-n1-feat-fp16.d
> @@ -0,0 +1,18 @@
> +#name: Neoverse-N1 feat-fp16
> +#as: -mcpu=neoverse-n1
> +#source: feat-fp16.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Neoverse N1"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-neoverse-n2-attrs.d b/gas/testsuite/gas/arm/mcpu-neoverse-n2-attrs.d
> new file mode 100644
> index 00000000000..9a4360e35b1
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-neoverse-n2-attrs.d
> @@ -0,0 +1,18 @@
> +#name: Neoverse-N2 Attributes
> +#as: -mcpu=neoverse-n2+crypto
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Neoverse N2"
> +  Tag_CPU_arch: v9
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-neoverse-n2-feat-bf16.d b/gas/testsuite/gas/arm/mcpu-neoverse-n2-feat-bf16.d
> new file mode 100644
> index 00000000000..955130e1102
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-neoverse-n2-feat-bf16.d
> @@ -0,0 +1,18 @@
> +#name: Neoverse-N2 feat-bf16
> +#as: -mcpu=neoverse-n2
> +#source: feat-bf16.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Neoverse N2"
> +  Tag_CPU_arch: v9
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-neoverse-n2-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-neoverse-n2-feat-fp16.d
> new file mode 100644
> index 00000000000..72e15f84577
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-neoverse-n2-feat-fp16.d
> @@ -0,0 +1,18 @@
> +#name: Neoverse-N2 feat-fp16
> +#as: -mcpu=neoverse-n2
> +#source: feat-fp16.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Neoverse N2"
> +  Tag_CPU_arch: v9
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-neoverse-n2-feat-i8mm.d b/gas/testsuite/gas/arm/mcpu-neoverse-n2-feat-i8mm.d
> new file mode 100644
> index 00000000000..380e4ce850d
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-neoverse-n2-feat-i8mm.d
> @@ -0,0 +1,18 @@
> +#name: Neoverse-N2 feat-i8mm
> +#as: -mcpu=neoverse-n2
> +#source: feat-i8mm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Neoverse N2"
> +  Tag_CPU_arch: v9
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-neoverse-v1-attrs.d b/gas/testsuite/gas/arm/mcpu-neoverse-v1-attrs.d
> new file mode 100644
> index 00000000000..9478192edfe
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-neoverse-v1-attrs.d
> @@ -0,0 +1,18 @@
> +#name: Neoverse-V1 Attributes
> +#as: -mcpu=neoverse-v1+crypto
> +#source: nop-asm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Neoverse V1"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-neoverse-v1-feat-bf16.d b/gas/testsuite/gas/arm/mcpu-neoverse-v1-feat-bf16.d
> new file mode 100644
> index 00000000000..48efeeabba7
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-neoverse-v1-feat-bf16.d
> @@ -0,0 +1,18 @@
> +#name: Neoverse-V1 feat-bf16
> +#as: -mcpu=neoverse-v1
> +#source: feat-bf16.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Neoverse V1"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-neoverse-v1-feat-fp16.d b/gas/testsuite/gas/arm/mcpu-neoverse-v1-feat-fp16.d
> new file mode 100644
> index 00000000000..59040dc0660
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-neoverse-v1-feat-fp16.d
> @@ -0,0 +1,18 @@
> +#name: Neoverse-V1 feat-fp16
> +#as: -mcpu=neoverse-v1
> +#source: feat-fp16.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Neoverse V1"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-neoverse-v1-feat-i8mm.d b/gas/testsuite/gas/arm/mcpu-neoverse-v1-feat-i8mm.d
> new file mode 100644
> index 00000000000..be46641d570
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-neoverse-v1-feat-i8mm.d
> @@ -0,0 +1,18 @@
> +#name: Neoverse-V1 feat-i8mm
> +#as: -mcpu=neoverse-v1
> +#source: feat-i8mm.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "Neoverse V1"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8.1
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions
> diff --git a/gas/testsuite/gas/arm/mcpu-xgene1-feat-simd.d b/gas/testsuite/gas/arm/mcpu-xgene1-feat-simd.d
> new file mode 100644
> index 00000000000..e8ef6a837a2
> --- /dev/null
> +++ b/gas/testsuite/gas/arm/mcpu-xgene1-feat-simd.d
> @@ -0,0 +1,18 @@
> +#name: XGene1 feat-simd
> +#as: -mcpu=xgene1
> +#source: feat-simd.s
> +#readelf: -A
> +# This test is only valid on EABI based ports.
> +# target: *-*-*eabi*
> +
> +Attribute Section: aeabi
> +File Attributes
> +  Tag_CPU_name: "APM X-Gene 1"
> +  Tag_CPU_arch: v8
> +  Tag_CPU_arch_profile: Application
> +  Tag_ARM_ISA_use: Yes
> +  Tag_THUMB_ISA_use: Thumb-2
> +  Tag_FP_arch: FP for ARMv8
> +  Tag_Advanced_SIMD_arch: NEON for ARMv8
> +  Tag_MPextension_use: Allowed
> +  Tag_Virtualization_use: TrustZone and Virtualization Extensions


From hjl.tools@gmail.com  Sat Jun 20 00:58:50 2026
From: hjl.tools@gmail.com (H.J. Lu)
Date: Sat, 20 Jun 2026 08:58:50 +0800
Subject: [PATCH v3] elf: Set image base address to the maximum page size
In-Reply-To: <eed00d94-f8eb-421e-973b-a9e35e00e68e@suse.com>
References: <CAMe9rOo5sxQ6x0jdD9JPXunmDt3rywckofJjPKgwXwUqsU-=GQ@mail.gmail.com>
 <eed00d94-f8eb-421e-973b-a9e35e00e68e@suse.com>
Message-ID: <CAMe9rOpP7iERnrXuqB3zSOay7ULihiS3o3a-QyARzJeouR5P5Q@mail.gmail.com>

On Fri, Jun 19, 2026 at 9:01?PM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 28.05.2026 09:16, H.J. Lu wrote:
> > On Thu, May 28, 2026 at 11:08?AM H.J. Lu <hjl.tools@gmail.com> wrote:
> >>
> >> When generating Position Dependent Executable for ELF with the maximum
> >> page size set on command-line, if text-segment address is lower than the
> >> maximum page size, set text-segment address to the maximum page size.
> >>
> >> PR ld/34184
> >> * ldexp.c (fold_binary): Set text-segment address to the maximum
> >> page size for ELF PDE output with -z max-page-size=SIZE.
> >> * testsuite/ld-elf/elf.exp: Add ld/34184 test.
> >> * testsuite/ld-elf/pr34184.c: New file.
> >
> > Here is the v2 patch to add tests for PIE, static PDE and static PIE.
>
> Why is this special to text-segment? Doesn't something like this need
> doing either for all segments, or for whatever is the first segment?
>
> Jan

  -Ttext-segment ADDRESS      Set address of text segment

is kind of misleading.  --image-base is a better name:

?--image-base=ORG?
     When using ELF, same as ?-Ttext-segment?, with both options
     effectively setting the base address of the ELF executable.

     When using PE, use VALUE as the base address of your program or
     dll.  This is the lowest memory location that will be used when
     your program or dll is loaded.  To reduce the need to relocate and
     improve performance of your dlls, each should have a unique base
     address and not overlap any other dlls.  The default is 0x400000
     for executables, and 0x10000000 for dlls.

Here is the v3 patch to use image base address instead of text-segment
address.


-- 
H.J.
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From hjl.tools@gmail.com  Sat Jun 20 03:07:36 2026
From: hjl.tools@gmail.com (H.J. Lu)
Date: Sat, 20 Jun 2026 11:07:36 +0800
Subject: [RFC] Add GNU_PROPERTY_1_NEEDED_THP_ON_[READ_ONLY_SEGMENTS|MALLOC
Message-ID: <CAMe9rOowtMxrv5O2_5zdXu57wJ-41moD51S+W46tQf+vZEcPNQ@mail.gmail.com>

Transparent Huge Pages (THP) has been enabled in glibc to use THP on
THP eligible read-only segments and malloc to improve application
performance.  But there are some common issues & trade-offs of THP:

1. Latency Spikes: The background process (khugepaged) that consolidates
pages can cause temporary system freezes or high CPU usage.
2. Memory Waste: Using a 2MB page for only 4KB of data can lead to
internal fragmentation and higher memory consumption.
3. Database Incompatibility: Many databases (e.g., Oracle, MongoDB,
SAP ASE) recommend disabling THP because their non-contiguous access
patterns often trigger performance degradations.

THP shouldn't be always enabled on THP eligible read-only segments nor
in malloc blindly without the knowledge whether THP usage will improve
or hurt performance for the application.  To give application developers
per-application control over THP usage under madvise THP mode, add
the following bits to GNU_PROPERTY_1_NEEDED which indicates the properties
needed by object file for correctness or performance:

1. GNU_PROPERTY_1_NEEDED_THP_ON_READ_ONLY_SEGMENTS

 #define GNU_PROPERTY_1_NEEDED_THP_ON_READ_ONLY_SEGMENTS (1U << 1)

to opt-in THP usage on read-only segments in an application.  When this
bit is set on executable, run-time loader should call madvise with
MADV_HUGEPAGE on all Transparent Huge Pages (THP) eligible read-only
segments in executable and its loaded shared libraries after they are
mapped into memory under madvise THP mode.

2. GNU_PROPERTY_1_NEEDED_THP_ON_MALLOC

 #define GNU_PROPERTY_1_NEEDED_THP_ON_MALLOC (1U << 2)

to opt-in THP usage in malloc in an application.  When this bit is set on
executable, malloc should call madvise with MADV_HUGEPAGE if the
allocated size is greater than or equal to THP page size after calling
mmap to allocate memory under madvise THP mode.

Update GNU_PROPERTY_1_NEEDED description to clarify that it is for
correctness or performance.

Linker will set these bits in application if these bits are set in any
relocatable inputs.

Run-time and tool integration:

1. Add linker options to enable and disable THP:

-z thp=rosegment:
  Turn on the GNU_PROPERTY_1_NEEDED_THP_ON_READ_ONLY_SEGMENTS bit

-z thp=malloc:
  Turn on the GNU_PROPERTY_1_NEEDED_THP_ON_MALLOC bit

-z thp=all
  Turn on both bits

-z nothp=rosegment
  Turn off the GNU_PROPERTY_1_NEEDED_THP_ON_READ_ONLY_SEGMENTS bit

-z nothp=malloc
  Turn off the GNU_PROPERTY_1_NEEDED_THP_ON_MALLOC bit

-z nothp=all
  Turn off both bits

2. Add compiler options to generate these bits in the object output.

3. Add elfedit options to disable and enable these bits.

4. Update the C run-time to check these bits in the executable to enable
THP at run-time.

5. Add GNU_PROPERTY_1_NEEDED to crtn.o with 2 bits cleared so that
THP can be enabled by elfedit later.


-- 
H.J.

From aburgess@redhat.com  Sat Jun 20 12:54:57 2026
From: aburgess@redhat.com (Andrew Burgess)
Date: Sat, 20 Jun 2026 13:54:57 +0100
Subject: [PATCH] libiberty: sync with gcc commit df3510f80e7c02d9
In-Reply-To: <ff87d7cb74f9d3d3b81aeca0a979d3dcc1531567.1781002240.git.aburgess@redhat.com>
References: <ff87d7cb74f9d3d3b81aeca0a979d3dcc1531567.1781002240.git.aburgess@redhat.com>
Message-ID: <875x3dpe1q.fsf@redhat.com>

Andrew Burgess <aburgess@redhat.com> writes:

> Sync the libiberty/ directory with gcc commit
> df3510f80e7c02d9c19d7cb33759cd925880f53a.  This pulls in the following
> gcc commits and the associated updates to 'libiberty/ChangeLog':
>
>   * 06fb00cb66d libiberty: Fix typos in various files
>   * fbf903e5b9f Re-flow lines made longer than 80 characters by typo fixes
>   * cfb945957ee Regenerate some autoconf configure scripts after recent spelling fixes.
>   * bc4d9b6aeb3 libiberty: avoid exponential back reference issue in D demangler
>
> I have retained the changes that are in the following binutils-gdb
> commit, which are not in gcc:
>
>   commit 219822fd5db6305592b45677a3b38c02b523360e
>   Date:   Tue Apr 9 06:39:21 2024 -0700
>
>     mmap: Avoid the sanitizer configure check failure

I've gone ahead and checked this in.  If there are any problems then
just let me know.

Thanks,
Andrew


From xry111@xry111.site  Sun Jun 21 04:09:21 2026
From: xry111@xry111.site (Xi Ruoyao)
Date: Sun, 21 Jun 2026 12:09:21 +0800
Subject: [PATCH v2] LoongArch: Fix relaxation alignment with ld -r (PR
 33236)
In-Reply-To: <20260618070155.1339292-1-mengqinggang@loongson.cn>
References: <20260618070155.1339292-1-mengqinggang@loongson.cn>
Message-ID: <49c4da734915ec2bdf9af17e243330e035b66ad1.camel@xry111.site>

On Thu, 2026-06-18 at 15:01 +0800, mengqinggang wrote:
> +	case lang_input_section_enum:
> +	? if (l->input_section.section == input_section)
> +	??? {
> +	????? /* We've found our section.? Insert the align
> immediately
> +		 before its associated input section.? */
> +	????? //*(add.tail) = l->header.next;
> +	????? //l->header.next = add.head;

Again, remove them.  A patch shouldn't contain such a draft remnant
unless it's an RFC.  And IIRC binutils code base is still C89 where C++-
style comment is not allowed.

-- 
Xi Ruoyao <xry111@xry111.site>

From xry111@xry111.site  Sun Jun 21 04:40:13 2026
From: xry111@xry111.site (Xi Ruoyao)
Date: Sun, 21 Jun 2026 12:40:13 +0800
Subject: [PATCH v1] LoongArch: Fix linker relaxation alignment
In-Reply-To: <20260618062910.972814-1-mengqinggang@loongson.cn>
References: <20260618062910.972814-1-mengqinggang@loongson.cn>
Message-ID: <6f5dabdd8c73fd86d73c763f992b2add5485747d.camel@xry111.site>

On Thu, 2026-06-18 at 14:29 +0800, mengqinggang wrote:
> When linking multiple objects, relaxation can cause alignment issues.
> Input section's output_offset is updated in relaxation without considering
> section alignment. Update section output_offset by align_opwer.

I can confirm this fixes the insufficient alignment of
trampoline_code_table in libffi.

Reviewed-by: Xi Ruoyao <xry111@xry111.site>

> ---
> ?bfd/elfnn-loongarch.c???????????????????????? | 24 +++----------------
> ?ld/testsuite/ld-loongarch-elf/relax-align-1.d | 13 ++++++++++
> ?.../ld-loongarch-elf/relax-align-1a.s???????? |? 5 ++++
> ?.../ld-loongarch-elf/relax-align-1b.s???????? |? 3 +++
> ?ld/testsuite/ld-loongarch-elf/relax.exp?????? |? 4 ++++
> ?5 files changed, 28 insertions(+), 21 deletions(-)
> ?create mode 100644 ld/testsuite/ld-loongarch-elf/relax-align-1.d
> ?create mode 100644 ld/testsuite/ld-loongarch-elf/relax-align-1a.s
> ?create mode 100644 ld/testsuite/ld-loongarch-elf/relax-align-1b.s
> 
> diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c
> index 9d9c68664bb..b7af2041238 100644
> --- a/bfd/elfnn-loongarch.c
> +++ b/bfd/elfnn-loongarch.c
> @@ -5725,11 +5725,6 @@ loongarch_relax_pcala_addi (bfd *abfd, asection *sec, asection *sym_sec,
> ?? uint32_t add = bfd_get (32, abfd, contents + rel_lo->r_offset);
> ?? uint32_t rd = LARCH_GET_RD (pca);
> ?
> -? /* This section's output_offset need to subtract the bytes of instructions
> -???? relaxed by the previous sections, so it needs to be updated beforehand.
> -???? size_input_section already took care of updating it after relaxation,
> -???? so we additionally update once here.? */
> -? sec->output_offset = sec->output_section->size;
> ?? bfd_vma pc = sec_addr (sec)
> ?	?????? + loongarch_calc_relaxed_addr (info, rel_hi->r_offset);
> ?? if (sym_sec == sec)
> @@ -5790,11 +5785,6 @@ loongarch_relax_call36 (bfd *abfd, asection *sec, asection *sym_sec,
> ?? uint32_t jirl = bfd_get (32, abfd, contents + rel->r_offset + 4);
> ?? uint32_t rd = LARCH_GET_RD (jirl);
> ?
> -? /* This section's output_offset need to subtract the bytes of instructions
> -???? relaxed by the previous sections, so it needs to be updated beforehand.
> -???? size_input_section already took care of updating it after relaxation,
> -???? so we additionally update once here.? */
> -? sec->output_offset = sec->output_section->size;
> ?? bfd_vma pc = sec_addr (sec)
> ?	?????? + loongarch_calc_relaxed_addr (info, rel->r_offset);
> ?? if (sym_sec == sec)
> @@ -5851,11 +5841,6 @@ loongarch_relax_pcala_ld (bfd *abfd, asection *sec,
> ?			? bool *again ATTRIBUTE_UNUSED,
> ?			? bfd_vma max_alignment)
> ?{
> -? /* This section's output_offset need to subtract the bytes of instructions
> -???? relaxed by the previous sections, so it needs to be updated beforehand.
> -???? size_input_section already took care of updating it after relaxation,
> -???? so we additionally update once here.? */
> -? sec->output_offset = sec->output_section->size;
> ?? bfd_vma pc = sec_addr (sec)
> ?	?????? + loongarch_calc_relaxed_addr (info, rel_hi->r_offset);
> ?? if (sym_sec == sec)
> @@ -6008,11 +5993,6 @@ loongarch_relax_tls_ld_gd_desc (bfd *abfd, asection *sec, asection *sym_sec,
> ?? uint32_t add = bfd_get (32, abfd, contents + rel_lo->r_offset);
> ?? uint32_t rd = LARCH_GET_RD (pca);
> ?
> -? /* This section's output_offset need to subtract the bytes of instructions
> -???? relaxed by the previous sections, so it needs to be updated beforehand.
> -???? size_input_section already took care of updating it after relaxation,
> -???? so we additionally update once here.? */
> -? sec->output_offset = sec->output_section->size;
> ?? bfd_vma pc = sec_addr (sec)
> ?	?????? + loongarch_calc_relaxed_addr (info, rel_hi->r_offset);
> ?? if (sym_sec == sec)
> @@ -6187,7 +6167,9 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec,
> ????? so we additionally update once here.? */
> ?
> ?? /* update before tls trans and relax, or may cause same pcadd_hi20 address.? */
> -? sec->output_offset = sec->output_section->size;
> +
> +? sec->output_offset = align_power (sec->output_section->size,
> +				??? sec->alignment_power);
> ?
> ?? for (unsigned int i = 0; i < sec->reloc_count; i++)
> ???? {
> diff --git a/ld/testsuite/ld-loongarch-elf/relax-align-1.d b/ld/testsuite/ld-loongarch-elf/relax-align-1.d
> new file mode 100644
> index 00000000000..30b7c4cb293
> --- /dev/null
> +++ b/ld/testsuite/ld-loongarch-elf/relax-align-1.d
> @@ -0,0 +1,13 @@
> +#source: relax-align-1a.s
> +#source: relax-align-1b.s
> +#ld: -e0
> +#objdump: -d
> +
> +#...
> +.*[0|8]:	54000400?	bl??????????	4.*<f>
> +#...
> +.*[0|8]:	02c001ac?	addi.d??????	\$t0, \$t1, 0
> +#...
> +.*0:	02c005ac?	addi.d??????	\$t0, \$t1, 1
> +#...
> +.*0:	02c005ac?	addi.d??????	\$t0, \$t1, 1
> diff --git a/ld/testsuite/ld-loongarch-elf/relax-align-1a.s b/ld/testsuite/ld-loongarch-elf/relax-align-1a.s
> new file mode 100644
> index 00000000000..2b7f3ecb6be
> --- /dev/null
> +++ b/ld/testsuite/ld-loongarch-elf/relax-align-1a.s
> @@ -0,0 +1,5 @@
> +.text
> +? call f
> +f:
> +? .align 3
> +? addi.d $t0, $t1, 0
> diff --git a/ld/testsuite/ld-loongarch-elf/relax-align-1b.s b/ld/testsuite/ld-loongarch-elf/relax-align-1b.s
> new file mode 100644
> index 00000000000..2ed480a6c1b
> --- /dev/null
> +++ b/ld/testsuite/ld-loongarch-elf/relax-align-1b.s
> @@ -0,0 +1,3 @@
> +addi.d $t0, $t1, 1
> +.align 4
> +addi.d $t0, $t1, 1
> diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp
> index 7c32a65244c..31787a93967 100644
> --- a/ld/testsuite/ld-loongarch-elf/relax.exp
> +++ b/ld/testsuite/ld-loongarch-elf/relax.exp
> @@ -46,6 +46,10 @@ proc run_partial_linking_align_test {} {
> ?? }
> ?}
> ?
> +if [istarget loongarch*-*-*] {
> +? run_dump_test "relax-align-1"
> +}
> +
> ?if [istarget loongarch64-*-*] {
> ?? if [isbuild loongarch64-*-*] {
> ???? run_dump_test "relax-align-ignore-start"

-- 
Xi Ruoyao <xry111@xry111.site>

From avr@gjlay.de  Sun Jun 21 16:47:20 2026
From: avr@gjlay.de (Georg-Johann Lay)
Date: Sun, 21 Jun 2026 18:47:20 +0200
Subject: [patch, avr, applied] PR34307: Fix illegal opcode diagnostic
Message-ID: <28e3d238-7b0c-4cf7-bc49-cf172810efea@gjlay.de>

When there is an AVR instruction in include/opcode/avr.h that is not 
supported by a specific core, then gas will diagnose with the mnemonic 
of the next instruction:

     mul 1,2
     mulsu 1,1
     lat

$ avr-as x.sx
x.sx: Assembler messages:
x.sx:1: Error: illegal opcode or for mcu avr2
x.sx:2: Error: illegal opcode fmul for mcu avr2
x.sx:3: Error: illegal opcode movw for mcu avr2

The reason is that in gas/config/tc-avr.c::md_assemble() we have this loop:

    while ((opcode->isa & avr_mcu->isa) != opcode->isa)
      {
        opcode++;

        if (opcode->name && strcmp(op, opcode->name))
          {
            as_bad (_("illegal opcode %s for mcu %s"),
                    opcode->name, avr_mcu->name);
            return;
          }
      }

which in the as_bad case prints the next instruction's mnemonic due to 
the opcode++ above.

Applied as obvious.

Johann

--

     AVR: PR34307 - Fix diagnostic for unknown ISA opcode

     When there is an AVR instruction in include/opcode/avr.h that
     is not supported by a specific MCU, then gas will diagnose
     with the mnemonic of the next instruction:

         mul 1,2
         mulsu 1,1
         lat

     $ avr-as x.sx
     x.sx: Assembler messages:
     x.sx:1: Error: illegal opcode or for mcu avr2
     x.sx:2: Error: illegal opcode fmul for mcu avr2
     x.sx:3: Error: illegal opcode movw for mcu avr2

     The reason is that in gas/config/tc-avr.c::md_assemble() we have:

        while ((opcode->isa & avr_mcu->isa) != opcode->isa)
          {
            opcode++;

            if (opcode->name && strcmp(op, opcode->name))
              {
                as_bad (_("illegal opcode %s for mcu %s"),
                        opcode->name, avr_mcu->name);
                return;
              }
          }

     which in the as_bad case prints the next instruction's mnemonic
     due to the opcode++ above.

     gas/
             * config/tc-avr.c (md_assemble): Use right index to diagnose
             an opcode that are not supported by the MCU.
             * testsuite/gas/avr/pr34307-1.d: New test.
             * testsuite/gas/avr/pr34307-1.s: New test source.
             * testsuite/gas/avr/pr34307-2.d: New test.
             * testsuite/gas/avr/pr34307-2.s: New test source.
-------------- next part --------------
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From oleg.tolmatcev@gmail.com  Sun Jun 21 17:49:21 2026
From: oleg.tolmatcev@gmail.com (Oleg Tolmatcev)
Date: Sun, 21 Jun 2026 19:49:21 +0200
Subject: [PATCH] PE/COFF: auto-promote to bigobj target when section count
 overflows
Message-ID: <20260621174919.1150-3-oleg.tolmatcev@gmail.com>

Regular PE/COFF uses 16-bit section numbers in the symbol table,
limiting objects to at most 65535 sections.  When this limit is
exceeded, the assembler silently truncates section numbers, producing
corrupt objects that cause confusing linker errors like:

  undefined reference to `vtable for ...'

Fix this by automatically switching the xvec to the matching bigobj
target before any headers or symbols are finalized, so the object is
written out using the extended COFF format which supports 32-bit
section numbers.

bfd/
	* coffcode.h (coff_compute_section_file_positions): Auto-promote
	to bigobj target when section count exceeds 16-bit limit.

gas/
	* testsuite/gas/pe/big-obj-auto.d: New test.
	* testsuite/gas/pe/big-obj-auto.s: New test.
	* testsuite/gas/pe/pe.exp: Run big-obj-auto.

Signed-off-by: Oleg Tolmatcev <oleg.tolmatcev@gmail.com>
---
 bfd/coffcode.h                      | 14 ++++++++++++++
 gas/testsuite/gas/pe/big-obj-auto.d |  9 +++++++++
 gas/testsuite/gas/pe/big-obj-auto.s | 16 ++++++++++++++++
 gas/testsuite/gas/pe/pe.exp         |  1 +
 4 files changed, 40 insertions(+)
 create mode 100644 gas/testsuite/gas/pe/big-obj-auto.d
 create mode 100644 gas/testsuite/gas/pe/big-obj-auto.s

diff --git a/bfd/coffcode.h b/bfd/coffcode.h
index 7439fca676..5c9722a15e 100644
--- a/bfd/coffcode.h
+++ b/bfd/coffcode.h
@@ -360,6 +360,10 @@ CODE_FRAGMENT
 #include "coffswap.h"
 #endif
 
+#ifdef COFF_WITH_PE_BIGOBJ
+extern const bfd_target TARGET_SYM_BIG;
+#endif
+
 #define STRING_SIZE_SIZE 4
 
 #define DOT_DEBUG	".debug"
@@ -3154,6 +3158,16 @@ coff_compute_section_file_positions (bfd * abfd)
 
   if (target_index >= bfd_coff_max_nscns (abfd))
     {
+#ifdef COFF_WITH_PE_BIGOBJ
+      if (abfd->xvec != &TARGET_SYM_BIG)
+	{
+	  /* Regular PE/COFF uses 16-bit section numbers in symbols.
+	     Promote oversized objects to the matching bigobj target
+	     before any headers or symbols are finalized.  */
+	  abfd->xvec = &TARGET_SYM_BIG;
+	  return coff_compute_section_file_positions (abfd);
+	}
+#endif
       bfd_set_error (bfd_error_file_too_big);
       _bfd_error_handler
 	/* xgettext:c-format */
diff --git a/gas/testsuite/gas/pe/big-obj-auto.d b/gas/testsuite/gas/pe/big-obj-auto.d
new file mode 100644
index 0000000000..9538ed4c67
--- /dev/null
+++ b/gas/testsuite/gas/pe/big-obj-auto.d
@@ -0,0 +1,9 @@
+#objdump: -h
+#name: PE big obj auto-promotion
+
+.*: *file format pe-bigobj-.*
+
+Sections:
+#...
+5000. \.data\$a49999  .*
+                  CONTENTS, ALLOC, LOAD, DATA
diff --git a/gas/testsuite/gas/pe/big-obj-auto.s b/gas/testsuite/gas/pe/big-obj-auto.s
new file mode 100644
index 0000000000..dbf2585e81
--- /dev/null
+++ b/gas/testsuite/gas/pe/big-obj-auto.s
@@ -0,0 +1,16 @@
+	.file "big-obj-auto.s"
+
+	.irp n,0,1,2,3,4
+	.irp m,0,1,2,3,4,5,6,7,8,9
+	.irp c,0,1,2,3,4,5,6,7,8,9
+	.irp d,0,1,2,3,4,5,6,7,8,9
+	.irp u,0,1,2,3,4,5,6,7,8,9
+	.globl a\n\m\c\d\u
+	.section .data$a\n\m\c\d\u,"w"
+a\n\m\c\d\u :
+	.byte 1
+	.endr
+	.endr
+	.endr
+	.endr
+	.endr
diff --git a/gas/testsuite/gas/pe/pe.exp b/gas/testsuite/gas/pe/pe.exp
index e25de3cfa9..092ab4b335 100644
--- a/gas/testsuite/gas/pe/pe.exp
+++ b/gas/testsuite/gas/pe/pe.exp
@@ -70,4 +70,5 @@ if {[istarget "aarch64-*-pe*"] || [istarget "aarch64-*-mingw*"]} {
 
 if ([istarget "*-*-mingw*"]) then {
 	run_dump_test "big-obj"
+	run_dump_test "big-obj-auto"
 }
-- 
2.54.0.windows.1


From naveed@digiscrypt.com  Sun Jun 21 21:12:22 2026
From: naveed@digiscrypt.com (Naveed Khan)
Date: Mon, 22 Jun 2026 02:42:22 +0530
Subject: [PATCH] libsframe: validate FDE/FRE subsection bounds in sframe_decode
Message-ID: <178207634240.2958.13202347064770017350@digiscrypt.com>

sframe_decode only calls sframe_header_sanity_check_p, which verifies
that sfh_fdeoff <= sfh_freoff but never checks the header-supplied
offsets, lengths and counts against the size of the SFrame buffer.  On
the native-endian decode path -- the foreign-endian path is bounds
checked inside flip_sframe -- a crafted SFrame section therefore drives
two out-of-bounds heap reads:

  - sframe_fde_tbl_init reads sfh_num_fdes function descriptor entries
    starting at frame_buf + sfh_fdeoff, and

  - memcpy (dctx->sfd_fres, frame_buf + sfh_freoff, sfh_fre_len) copies
    sfh_fre_len bytes starting at frame_buf + sfh_freoff.

Both read past the end of the buffer.  The defect is reachable from
objdump --sframe and readelf on an object file carrying a crafted
.sframe section; for example a 28-byte section whose header claims
sfh_fre_len = 0x10000 makes objdump --sframe read 64KB past the
section contents.

Validate in sframe_decode that the FDE and FRE sub-sections described
by the header are fully contained in the buffer before they are read.
The checks use subtraction and division so the arithmetic cannot
overflow.

Signed-off-by: Naveed Khan <naveed@digiscrypt.com>
---
diff --git a/libsframe/sframe.c b/libsframe/sframe.c
index cd6bb302..24d07ae3 100644
--- a/libsframe/sframe.c
+++ b/libsframe/sframe.c
@@ -1480,6 +1480,25 @@ sframe_decode (const char *sf_buf, size_t sf_size, int *errp)
       goto decode_fail_free;
     }
   hdrsz = sframe_get_hdr_size (dhp);
+
+  /* Validate that the FDE and FRE sub-sections described by the SFrame
+     header lie entirely within the SFrame buffer.  The earlier call to
+     sframe_header_sanity_check_p has checked that sfh_fdeoff <= sfh_freoff.
+     The FDE sub-section holds sfh_num_fdes entries and precedes the FRE
+     sub-section, which is sfh_fre_len bytes long.  The arithmetic below uses
+     subtraction and division so that it cannot itself overflow.  */
+  size_t fde_size = sizeof (sframe_func_desc_entry_v2);
+  if (sfp->sfp_version == SFRAME_VERSION_3)
+    fde_size = sizeof (sframe_func_desc_idx_v3);
+  if (hdrsz > sf_size
+      || dhp->sfh_freoff > sf_size - hdrsz
+      || dhp->sfh_fre_len > sf_size - hdrsz - dhp->sfh_freoff
+      || dhp->sfh_num_fdes > (dhp->sfh_freoff - dhp->sfh_fdeoff) / fde_size)
+    {
+      sframe_ret_set_errno (errp, SFRAME_ERR_BUF_INVAL);
+      goto decode_fail_free;
+    }
+
   frame_buf += hdrsz;
 
   /* Handle the SFrame Function Descriptor Entry section.  */
-- 
2.52.0

From zhaofujin@nucleisys.com  Mon Jun 22 02:23:53 2026
From: zhaofujin@nucleisys.com (=?utf-8?B?QmlnbWFnaWM=?=)
Date: Mon, 22 Jun 2026 10:23:53 +0800
Subject: [PATCH 1/3] RISC-V: Add ZCMT table jump relaxation
Message-ID: <tencent_170D8B04403D2E57660C49C0@qq.com>

--- a/bfd/elfnn-riscv.c+++ b/bfd/elfnn-riscv.c
@@ -1893,11 +1893,18 @@ riscv_elf_late_size_sections (bfd *output_bfd, struct bfd_link_info *info)
&nbsp; &nbsp; &nbsp; &nbsp;if (s-&gt;output_section == NULL)
&nbsp; &nbsp; &nbsp; &nbsp; return false;


- &nbsp; &nbsp; &nbsp;if (!_bfd_generic_link_add_one_symbol (
- &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; info, output_bfd, RISCV_TABLE_JUMP_BASE_SYMBOL, BSF_GLOBAL, s,
- &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; (bfd_vma) 0, (const char *) NULL, true,
- &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; get_elf_backend_data (output_bfd)-&gt;collect, &amp;bh))
- &nbsp; &nbsp; &nbsp; return false;
+ &nbsp; &nbsp; &nbsp;/* Only create the symbol if it doesn't already exist (e.g. from
+ &nbsp; &nbsp; &nbsp; &nbsp;a linker script PROVIDE). &nbsp;*/
+ &nbsp; &nbsp; &nbsp;bh = bfd_link_hash_lookup (info-&gt;hash, RISCV_TABLE_JUMP_BASE_SYMBOL,
+ &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;false, false, false);
+ &nbsp; &nbsp; &nbsp;if (bh == NULL)
+ &nbsp; &nbsp; &nbsp; {
+ &nbsp; &nbsp; &nbsp; &nbsp; if (!_bfd_generic_link_add_one_symbol (
+ &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; info, output_bfd, RISCV_TABLE_JUMP_BASE_SYMBOL, BSF_GLOBAL, s,
+ &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; (bfd_vma) 0, (const char *) NULL, true,
+ &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; get_elf_backend_data (output_bfd)-&gt;collect, &amp;bh))
+ &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; return false;
+ &nbsp; &nbsp; &nbsp; }
&nbsp; &nbsp; &nbsp;}


This patch fixes an issue where the RISC-V linker would unconditionally create the __riscv_table_jump_base symbol during ZCMT relaxation, even if it was already defined in a linker script via PROVIDE.

Currently, riscv_elf_late_size_sections() always calls _bfd_generic_link_add_one_symbol() to create the __riscv_table_jump_base symbol. This overwrites any definition provided by a linker script, making it impossible for users to override this symbol with a custom address through PROVIDE.


The patch first looks up the symbol in the linker hash table using bfd_link_hash_lookup(). Only if the symbol is not found does it proceed to create it. This allows linker scripts to pre-define the symbol via PROVIDE, which will then be used by ZCMT relaxation.
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From peter0x44@disroot.org  Mon Jun 22 03:39:23 2026
From: peter0x44@disroot.org (Peter Damianov)
Date: Sun, 21 Jun 2026 23:39:23 -0400
Subject: [PATCH v2 0/3] PE-COFF weak external fixes
In-Reply-To: <20260530191522.57144-1-peter0x44@disroot.org>
References: <20260530191522.57144-1-peter0x44@disroot.org>
Message-ID: <20260622033926.220317-1-peter0x44@disroot.org>

This is v2 of the PE-COFF weak external fixes.  The series fixes two
weak external resolution bugs in the BFD linker and adds tests covering
the weak/strong interaction matrix.

Changes from v1:

  * Drop unnecessary casts from bfd_hash_allocate results.
  * Make the null-fallback handling in patch 2 more explicit: a COFF
    weak declaration uses the null symbol as its fallback, which appears
    in the hash table as a defined absolute symbol with value zero.  The
    updated code now treats that case as unresolved on both the old and
    incoming fallback sides.

Alan reported two test failures with Ubuntu's x86_64-w64-mingw32 cross
compiler.  I reproduced that as a testsuite setup issue rather than a
linker regression: that compiler is configured with --with-ld=/usr/bin/
x86_64-w64-mingw32-ld and ignores the testsuite's -B path, so the new
tests were being linked with the installed linker instead of the just
built one.

For my GitHub Actions coverage I worked around that by replacing the
disposable runner's hardwired MinGW ld/as entry points with symlinks to
the just-built tools before running the DejaGnu tests:

  https://github.com/Peter0x44/binutils-gdb/blob/30db88d4da5db6b3ddcfc745a8438ce8d1f600fe/.github/workflows/ld-pe-tests.yml#L126-L133

A successful run using that workaround is here:

  https://github.com/Peter0x44/binutils-gdb/actions/runs/27926498479/job/82629812736

Peter Damianov (3):
  PE-COFF: Fix weak external symbol resolution when strong undef is seen
    first
  PE-COFF: Prefer weak external with defined fallback over null fallback
  ld/testsuite: Add comprehensive PE COFF weak external tests

 bfd/cofflink.c                                | 137 ++++++++++++++++--
 ld/testsuite/ld-pe/pe-compile.exp             |  88 +++++++++++
 .../ld-pe/weak-ext-add1-weak-chained.c        |  13 ++
 ld/testsuite/ld-pe/weak-ext-add2.c            |   8 +
 ld/testsuite/ld-pe/weak-ext-dummy.c           |   5 +
 ld/testsuite/ld-pe/weak-ext-expected1.c       |   1 +
 .../ld-pe/weak-ext-expected3-add1-weak.c      |   9 ++
 ld/testsuite/ld-pe/weak-ext-expected3.c       |   1 +
 ld/testsuite/ld-pe/weak-ext-expected5.c       |   1 +
 ld/testsuite/ld-pe/weak-ext-main-weak-def.c   |  26 ++++
 ld/testsuite/ld-pe/weak-ext-main-weak.c       |  22 +++
 ld/testsuite/ld-pe/weak-ext-main.c            |  21 +++
 12 files changed, 319 insertions(+), 13 deletions(-)
 create mode 100644 ld/testsuite/ld-pe/weak-ext-add1-weak-chained.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-add2.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-dummy.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-expected1.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-expected3-add1-weak.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-expected3.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-expected5.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-main-weak-def.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-main-weak.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-main.c

-- 
2.54.0


From peter0x44@disroot.org  Mon Jun 22 03:39:24 2026
From: peter0x44@disroot.org (Peter Damianov)
Date: Sun, 21 Jun 2026 23:39:24 -0400
Subject: [PATCH v2 1/3] PE-COFF: Fix weak external symbol resolution when
 strong undef is seen first
In-Reply-To: <20260622033926.220317-1-peter0x44@disroot.org>
References: <20260530191522.57144-1-peter0x44@disroot.org>
 <20260622033926.220317-1-peter0x44@disroot.org>
Message-ID: <20260622033926.220317-2-peter0x44@disroot.org>

When linking PE-COFF objects, a weak external symbol (C_NT_WEAK with an
aux record specifying a fallback alias) may fail to resolve if a strong
undefined reference to the same symbol is encountered before the weak
definition.  This causes "undefined reference" errors for symbols like
operator new or personality routines that GCC emits as weak externals
with a fallback to a default implementation.

There are two problems:

1. In coff_link_add_symbols, when the generic linker resolves a weak
   undefined against an existing strong undefined (NOACT in the action
   table), the COFF-specific symbol_class and aux record were not stored
   because the existing hash entry already had non-null class/type from
   the first (strong) object file.

2. In _bfd_coff_generic_relocate_section, the weak alias fallback only
   triggered for bfd_link_hash_undefweak symbols.  When a strong undef
   is seen first, the hash type stays bfd_link_hash_undefined (the
   generic linker does not downgrade it), so the fallback was skipped.

Fix by extending the condition in coff_link_add_symbols to also update
symbol_class and aux when the incoming symbol is a PE weak external
with aux and the existing hash is still undefined.  Also extend the
relocation handler to resolve the weak alias fallback for
bfd_link_hash_undefined symbols that carry C_NT_WEAK class and have
an aux record.

bfd/
        * cofflink.c (coff_link_add_symbols): Also store symbol_class
        and aux record when a PE weak external with aux meets an
        existing undefined hash entry.
        (_bfd_coff_generic_relocate_section): Also resolve weak alias
        fallback for undefined symbols with C_NT_WEAK class and aux.
---
 bfd/cofflink.c | 55 ++++++++++++++++++++++++++++++++++++++------------
 1 file changed, 42 insertions(+), 13 deletions(-)

diff --git a/bfd/cofflink.c b/bfd/cofflink.c
index e5c8a987d69..eba0fad4c3f 100644
--- a/bfd/cofflink.c
+++ b/bfd/cofflink.c
@@ -477,13 +477,20 @@ coff_link_add_symbols (bfd *abfd,
 	      /* If we don't have any symbol information currently in
 		 the hash table, or if we are looking at a symbol
 		 definition, then update the symbol class and type in
-		 the hash table.  */
+		 the hash table.  Also update if the incoming symbol is
+		 a weak external with an aux record (PE COFF weak alias)
+		 and the existing symbol is still undefined, so the
+		 fallback alias information is preserved for the linker's
+		 relocation resolution.  */
 	      if (((*sym_hash)->symbol_class == C_NULL
 		   && (*sym_hash)->type == T_NULL)
 		  || sym.n_scnum != 0
 		  || (sym.n_value != 0
 		      && (*sym_hash)->root.type != bfd_link_hash_defined
-		      && (*sym_hash)->root.type != bfd_link_hash_defweak))
+		      && (*sym_hash)->root.type != bfd_link_hash_defweak)
+		  || (IS_WEAK_EXTERNAL (abfd, sym)
+		      && sym.n_numaux > 0
+		      && (*sym_hash)->root.type == bfd_link_hash_undefined))
 		{
 		  (*sym_hash)->symbol_class = sym.n_sclass;
 		  if (sym.n_type != T_NULL)
@@ -521,10 +528,9 @@ coff_link_add_symbols (bfd *abfd,
 		      union internal_auxent *iaux;
 
 		      (*sym_hash)->numaux = sym.n_numaux;
-		      alloc = ((union internal_auxent *)
-			       bfd_hash_allocate (&info->hash->table,
-						  (sym.n_numaux
-						   * sizeof (*alloc))));
+		      alloc = bfd_hash_allocate (&info->hash->table,
+						 (sym.n_numaux
+						  * sizeof (*alloc)));
 		      if (alloc == NULL)
 			goto error_return;
 		      for (i = 0, eaux = esym + symesz, iaux = alloc;
@@ -3065,14 +3071,24 @@ _bfd_coff_generic_relocate_section (bfd *output_bfd,
 		     + sec->output_offset);
 	    }
 
-	  else if (h->root.type == bfd_link_hash_undefweak)
+	  else if (h->root.type == bfd_link_hash_undefweak
+		   || (h->root.type == bfd_link_hash_undefined
+		       && h->symbol_class == C_NT_WEAK && h->numaux == 1))
 	    {
-	      if (h->symbol_class == C_NT_WEAK && h->numaux == 1)
+	      /* Weak undefined symbol: either GNU weak (no aux record) or
+		 PE COFF weak external (C_NT_WEAK with aux record).
+		 Also handles strong undefined symbols that carry PE weak
+		 external metadata (when strong undef is seen before weak def,
+		 the hash type stays bfd_link_hash_undefined but we preserve
+		 the weak external class and aux for later resolution).  */
+
+	      bool is_pe_weak = (h->symbol_class == C_NT_WEAK && h->numaux == 1);
+
+	      if (is_pe_weak)
 		{
-		  /* See _Microsoft Portable Executable and Common Object
+		  /* PE COFF weak external: resolve via fallback alias.
+		     See _Microsoft Portable Executable and Common Object
 		     File Format Specification_, section 5.5.3.
-		     Note that weak symbols without aux records are a GNU
-		     extension.
 		     FIXME: All weak externals are treated as having
 		     characteristic IMAGE_WEAK_EXTERN_SEARCH_NOLIBRARY (1).
 		     These behave as per SVR4 ABI:  A library member
@@ -3081,24 +3097,37 @@ _bfd_coff_generic_relocate_section (bfd *output_bfd,
 		     See also linker.c: generic_link_check_archive_element. */
 		  struct coff_link_hash_entry *h2 = NULL;
 		  unsigned long symndx2 = h->aux->x_sym.x_tagndx.u32;
+
 		  if (symndx2 < obj_raw_syment_count (h->auxbfd))
 		    h2 = obj_coff_sym_hashes (h->auxbfd)[symndx2];
 
 		  if (!h2 || h2->root.type == bfd_link_hash_undefined)
 		    {
+		      /* Fallback alias not found or still undefined.
+			 Resolve to NULL.  */
 		      sec = bfd_abs_section_ptr;
 		      val = 0;
 		    }
 		  else
 		    {
+		      /* Use fallback alias target.  */
 		      sec = h2->root.u.def.section;
 		      val = h2->root.u.def.value
 			+ sec->output_section->vma + sec->output_offset;
 		    }
 		}
 	      else
-		/* This is a GNU extension.  */
-		val = 0;
+		{
+		  /* GNU extension: ELF-style weak symbol in COFF without
+		     PE weak external aux record.  COFF has no native support
+		     for weak symbols (unlike ELF where they're part of the
+		     format).  PE COFF adds them via C_NT_WEAK storage class
+		     with an aux record pointing to a fallback symbol.  GNU ld
+		     extends this by allowing __attribute__((weak)) in COFF
+		     objects even without the PE aux structure, treating them
+		     like ELF weak symbols: resolve to NULL if not defined.  */
+		  val = 0;
+		}
 	    }
 
 	  else if (! bfd_link_relocatable (info))
-- 
2.54.0


From peter0x44@disroot.org  Mon Jun 22 03:39:25 2026
From: peter0x44@disroot.org (Peter Damianov)
Date: Sun, 21 Jun 2026 23:39:25 -0400
Subject: [PATCH v2 2/3] PE-COFF: Prefer weak external with defined fallback
 over null fallback
In-Reply-To: <20260622033926.220317-1-peter0x44@disroot.org>
References: <20260530191522.57144-1-peter0x44@disroot.org>
 <20260622033926.220317-1-peter0x44@disroot.org>
Message-ID: <20260622033926.220317-3-peter0x44@disroot.org>

When two PE COFF weak externals for the same symbol are linked (both
C_NT_WEAK with aux records), the generic linker takes no action on the
second one (NOACT: weak undef meets existing weak undef).  This means
the first file's fallback alias always wins regardless of whether it
points to a real definition or to NULL.

This causes a problem when a weak declaration (fallback = NULL,
i.e. "resolve to NULL if nothing provides it") is linked before a
weak definition (fallback = actual function body).  The symbol resolves
to address 0 at runtime, causing a crash when called.

Fix this by comparing the fallback targets when two weak externals
meet: if the incoming weak external's fallback resolves to a defined
symbol and the existing one does not (or points to NULL),
update the aux record to use the better fallback.

This matches the behavior of lld after:
  https://github.com/llvm/llvm-project/commit/7ca5698b4c3698d06065e0941df7f23d72913d23

bfd/
	* cofflink.c (coff_link_add_symbols): When two PE COFF weak
	externals meet, prefer the one whose fallback alias resolves
	to a defined symbol.
---
 bfd/cofflink.c | 82 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 82 insertions(+)

diff --git a/bfd/cofflink.c b/bfd/cofflink.c
index eba0fad4c3f..75b4c47eacf 100644
--- a/bfd/cofflink.c
+++ b/bfd/cofflink.c
@@ -542,6 +542,88 @@ coff_link_add_symbols (bfd *abfd,
 		      (*sym_hash)->aux = alloc;
 		    }
 		}
+
+	      /* When two PE COFF weak externals meet (both with aux
+		 records specifying fallback aliases), prefer the one
+		 whose fallback resolves to a defined symbol over one
+		 whose fallback is undefined or NULL.  This
+		 handles the case where a weak declaration (with a
+		 fallback of NULL) is seen before a weak
+		 definition (with a fallback of the actual function
+		 body).  */
+	      else if (IS_WEAK_EXTERNAL (abfd, sym)
+		       && sym.n_numaux > 0
+		       && (*sym_hash)->root.type == bfd_link_hash_undefweak
+		       && (*sym_hash)->symbol_class == C_NT_WEAK
+		       && (*sym_hash)->numaux == 1)
+		{
+		  /* Parse the incoming aux to get the fallback tagndx.  */
+		  union internal_auxent new_aux;
+		  unsigned long new_tagndx;
+		  unsigned long old_tagndx;
+		  struct coff_link_hash_entry *h2_new = NULL;
+		  struct coff_link_hash_entry *h2_old = NULL;
+		  bool new_is_real_fallback;
+		  bool old_is_unresolved_fallback;
+
+		  bfd_coff_swap_aux_in (abfd, esym + symesz, sym.n_type,
+					sym.n_sclass, 0, sym.n_numaux,
+					&new_aux);
+		  new_tagndx = new_aux.x_sym.x_tagndx.u32;
+
+		  if (new_tagndx < obj_raw_syment_count (abfd))
+		    h2_new = obj_coff_sym_hashes (abfd)[new_tagndx];
+
+		  old_tagndx = (*sym_hash)->aux->x_sym.x_tagndx.u32;
+		  if (old_tagndx
+		      < obj_raw_syment_count ((*sym_hash)->auxbfd))
+		    h2_old = obj_coff_sym_hashes
+		      ((*sym_hash)->auxbfd)[old_tagndx];
+
+		  /* Update if the new fallback is a real definition but
+		     the old one is not.  A weak declaration with no
+		     definition uses the COFF null symbol as its fallback.
+		     In the hash table that fallback looks like a defined
+		     absolute symbol with value zero, so treat that case as
+		     unresolved here.  */
+		  new_is_real_fallback
+		    = (h2_new != NULL
+		       && (h2_new->root.type == bfd_link_hash_defined
+			   || h2_new->root.type == bfd_link_hash_defweak)
+		       && !(bfd_is_abs_section (h2_new->root.u.def.section)
+			    && h2_new->root.u.def.value == 0));
+		  old_is_unresolved_fallback
+		    = (h2_old == NULL
+		       || h2_old->root.type == bfd_link_hash_undefined
+		       || h2_old->root.type == bfd_link_hash_undefweak
+		       || (h2_old->root.type == bfd_link_hash_defined
+			   && bfd_is_abs_section (h2_old->root.u.def.section)
+			   && h2_old->root.u.def.value == 0));
+
+		  if (new_is_real_fallback && old_is_unresolved_fallback)
+		    {
+		      union internal_auxent *alloc;
+		      unsigned int i;
+		      bfd_byte *eaux;
+		      union internal_auxent *iaux;
+
+		      (*sym_hash)->symbol_class = sym.n_sclass;
+		      (*sym_hash)->auxbfd = abfd;
+		      (*sym_hash)->numaux = sym.n_numaux;
+		      alloc = bfd_hash_allocate (&info->hash->table,
+						 (sym.n_numaux
+						  * sizeof (*alloc)));
+		      if (alloc == NULL)
+			goto error_return;
+		      for (i = 0, eaux = esym + symesz, iaux = alloc;
+			   i < sym.n_numaux;
+			   i++, eaux += symesz, iaux++)
+			bfd_coff_swap_aux_in (abfd, eaux, sym.n_type,
+					      sym.n_sclass, (int) i,
+					      sym.n_numaux, iaux);
+		      (*sym_hash)->aux = alloc;
+		    }
+		}
 	    }
 
 	  if (classification == COFF_SYMBOL_PE_SECTION
-- 
2.54.0


From peter0x44@disroot.org  Mon Jun 22 03:39:26 2026
From: peter0x44@disroot.org (Peter Damianov)
Date: Sun, 21 Jun 2026 23:39:26 -0400
Subject: [PATCH v2 3/3] ld/testsuite: Add comprehensive PE COFF weak external
 tests
In-Reply-To: <20260622033926.220317-1-peter0x44@disroot.org>
References: <20260530191522.57144-1-peter0x44@disroot.org>
 <20260622033926.220317-1-peter0x44@disroot.org>
Message-ID: <20260622033926.220317-4-peter0x44@disroot.org>

Add tests covering the full matrix of weak/strong symbol interactions
for PE COFF weak externals, based on testcases by Martin Storsjo.

ld/testsuite/

	* ld-pe/pe-compile.exp (weak_ext_test): New proc.  Compiles
	source files, links via gcc, and runs natively if possible.
	Add tests: normal, weak-undef, weak-defined, weak-decl-weak-def,
	weak-use, weak-override, weak-duplicate, weak-def-override,
	weak-def-use.
	* ld-pe/weak-ext-main.c: New file.
	* ld-pe/weak-ext-main-weak.c: New file.
	* ld-pe/weak-ext-main-weak-def.c: New file.
	* ld-pe/weak-ext-add2.c: New file.
	* ld-pe/weak-ext-add1-weak-chained.c: New file.
	* ld-pe/weak-ext-dummy.c: New file.
	* ld-pe/weak-ext-expected1.c: New file.
	* ld-pe/weak-ext-expected3.c: New file.
	* ld-pe/weak-ext-expected5.c: New file.
	* ld-pe/weak-ext-expected3-add1-weak.c: New file.
---
 ld/testsuite/ld-pe/pe-compile.exp             | 88 +++++++++++++++++++
 .../ld-pe/weak-ext-add1-weak-chained.c        | 13 +++
 ld/testsuite/ld-pe/weak-ext-add2.c            |  8 ++
 ld/testsuite/ld-pe/weak-ext-dummy.c           |  5 ++
 ld/testsuite/ld-pe/weak-ext-expected1.c       |  1 +
 .../ld-pe/weak-ext-expected3-add1-weak.c      |  9 ++
 ld/testsuite/ld-pe/weak-ext-expected3.c       |  1 +
 ld/testsuite/ld-pe/weak-ext-expected5.c       |  1 +
 ld/testsuite/ld-pe/weak-ext-main-weak-def.c   | 26 ++++++
 ld/testsuite/ld-pe/weak-ext-main-weak.c       | 22 +++++
 ld/testsuite/ld-pe/weak-ext-main.c            | 21 +++++
 11 files changed, 195 insertions(+)
 create mode 100644 ld/testsuite/ld-pe/weak-ext-add1-weak-chained.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-add2.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-dummy.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-expected1.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-expected3-add1-weak.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-expected3.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-expected5.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-main-weak-def.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-main-weak.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-main.c

diff --git a/ld/testsuite/ld-pe/pe-compile.exp b/ld/testsuite/ld-pe/pe-compile.exp
index 041a1cb9344..189b95ea315 100644
--- a/ld/testsuite/ld-pe/pe-compile.exp
+++ b/ld/testsuite/ld-pe/pe-compile.exp
@@ -138,3 +138,91 @@ set align_tests {
 }
 
 run_ld_link_tests $align_tests
+
+# Test PE COFF weak external symbol resolution.
+# These tests cover the full matrix of weak/strong interactions to verify
+# that the linker correctly resolves weak externals in PE COFF objects.
+# Based on testcases by Martin Storsjo.
+
+proc weak_ext_test { testname sources } {
+    global CC_FOR_TARGET
+    global srcdir
+    global subdir
+
+    set objfiles {}
+    foreach src $sources {
+	set fileroot [file rootname [file tail $src]]
+	set obj "tmpdir/$fileroot.o"
+	if ![ld_compile $CC_FOR_TARGET $srcdir/$subdir/$src $obj] {
+	    fail "$testname (compile $src)"
+	    return
+	}
+	lappend objfiles $obj
+    }
+
+    set output "tmpdir/weak-ext-test.exe"
+    if ![ld_link $CC_FOR_TARGET $output $objfiles] {
+	fail "$testname (link)"
+	return
+    }
+
+    if ![isnative] {
+	pass "$testname (link only)"
+	return
+    }
+
+    catch "exec $output" prog_output
+    if { $prog_output eq "" } {
+	pass $testname
+    } else {
+	verbose $prog_output
+	fail "$testname ($prog_output)"
+    }
+}
+
+# Strong undefined reference + strong definition: basic sanity check.
+weak_ext_test "weak external: normal (strong undef + strong def)" \
+    {weak-ext-main.c weak-ext-add2.c weak-ext-expected3.c weak-ext-dummy.c}
+
+# Weak declaration with no definition available: func remains NULL,
+# never called.
+weak_ext_test "weak external: weak undef (no def)" \
+    {weak-ext-main-weak.c weak-ext-expected1.c weak-ext-dummy.c}
+
+# Weak declaration resolved by a strong definition in another object.
+weak_ext_test "weak external: weak decl + strong def" \
+    {weak-ext-main-weak.c weak-ext-add2.c weak-ext-expected3.c weak-ext-dummy.c}
+
+# Two weak externals for the same symbol meet: the one whose fallback
+# alias points to an actual function body should win over the one whose
+# fallback is NULL.
+weak_ext_test "weak external: weak decl + weak def" \
+    {weak-ext-main-weak.c weak-ext-add1-weak-chained.c weak-ext-expected3.c}
+
+# Strong undefined reference is seen before the weak definition: the
+# linker must still store the weak external's aux record so the fallback
+# alias can be resolved later.
+weak_ext_test "weak external: strong undef + weak def" \
+    {weak-ext-main.c weak-ext-add1-weak-chained.c weak-ext-expected3.c}
+
+# Strong definition overrides a weak definition: both call sites (in
+# main and in dummy) should resolve to the strong def.
+weak_ext_test "weak external: strong override of weak" \
+    {weak-ext-main.c weak-ext-add1-weak-chained.c weak-ext-add2.c \
+     weak-ext-expected5.c}
+
+# Two identical weak definitions for the same symbol: no conflict,
+# the linker picks one (first wins) and discards the duplicate.
+weak_ext_test "weak external: duplicate weak defs" \
+    {weak-ext-main.c weak-ext-add1-weak-chained.c \
+     weak-ext-expected3-add1-weak.c}
+
+# Weak definition in main overridden by a strong definition elsewhere.
+weak_ext_test "weak external: weak def overridden by strong" \
+    {weak-ext-main-weak-def.c weak-ext-add2.c weak-ext-expected3.c \
+     weak-ext-dummy.c}
+
+# Weak definition in main used directly when no strong definition exists.
+weak_ext_test "weak external: weak def used (no strong)" \
+    {weak-ext-main-weak-def.c weak-ext-expected5.c weak-ext-dummy.c}
+
diff --git a/ld/testsuite/ld-pe/weak-ext-add1-weak-chained.c b/ld/testsuite/ld-pe/weak-ext-add1-weak-chained.c
new file mode 100644
index 00000000000..5b68b8435e2
--- /dev/null
+++ b/ld/testsuite/ld-pe/weak-ext-add1-weak-chained.c
@@ -0,0 +1,13 @@
+/* Weak definition of func (adds 1), plus dummy that calls func.  */
+extern int value;
+
+__attribute__((weak)) void func (void)
+{
+  value += 1;
+}
+
+void
+dummy (void)
+{
+  func ();
+}
diff --git a/ld/testsuite/ld-pe/weak-ext-add2.c b/ld/testsuite/ld-pe/weak-ext-add2.c
new file mode 100644
index 00000000000..691554d17e3
--- /dev/null
+++ b/ld/testsuite/ld-pe/weak-ext-add2.c
@@ -0,0 +1,8 @@
+/* Strong definition of func (adds 2).  */
+extern int value;
+
+void
+func (void)
+{
+  value += 2;
+}
diff --git a/ld/testsuite/ld-pe/weak-ext-dummy.c b/ld/testsuite/ld-pe/weak-ext-dummy.c
new file mode 100644
index 00000000000..1c97c3cf97f
--- /dev/null
+++ b/ld/testsuite/ld-pe/weak-ext-dummy.c
@@ -0,0 +1,5 @@
+/* Empty dummy function.  */
+void
+dummy (void)
+{
+}
diff --git a/ld/testsuite/ld-pe/weak-ext-expected1.c b/ld/testsuite/ld-pe/weak-ext-expected1.c
new file mode 100644
index 00000000000..5b4138b0bb1
--- /dev/null
+++ b/ld/testsuite/ld-pe/weak-ext-expected1.c
@@ -0,0 +1 @@
+int expected = 1;
diff --git a/ld/testsuite/ld-pe/weak-ext-expected3-add1-weak.c b/ld/testsuite/ld-pe/weak-ext-expected3-add1-weak.c
new file mode 100644
index 00000000000..585830bd304
--- /dev/null
+++ b/ld/testsuite/ld-pe/weak-ext-expected3-add1-weak.c
@@ -0,0 +1,9 @@
+/* Second weak definition of func (adds 1) plus expected value.  */
+extern int value;
+
+__attribute__((weak)) void func (void)
+{
+  value += 1;
+}
+
+int expected = 3;
diff --git a/ld/testsuite/ld-pe/weak-ext-expected3.c b/ld/testsuite/ld-pe/weak-ext-expected3.c
new file mode 100644
index 00000000000..3d67d70bcb0
--- /dev/null
+++ b/ld/testsuite/ld-pe/weak-ext-expected3.c
@@ -0,0 +1 @@
+int expected = 3;
diff --git a/ld/testsuite/ld-pe/weak-ext-expected5.c b/ld/testsuite/ld-pe/weak-ext-expected5.c
new file mode 100644
index 00000000000..fef6b322c03
--- /dev/null
+++ b/ld/testsuite/ld-pe/weak-ext-expected5.c
@@ -0,0 +1 @@
+int expected = 5;
diff --git a/ld/testsuite/ld-pe/weak-ext-main-weak-def.c b/ld/testsuite/ld-pe/weak-ext-main-weak-def.c
new file mode 100644
index 00000000000..05f81d189b4
--- /dev/null
+++ b/ld/testsuite/ld-pe/weak-ext-main-weak-def.c
@@ -0,0 +1,26 @@
+/* Weak definition of func in main (adds 4).  */
+#include <stdio.h>
+
+int value = 1;
+
+__attribute__((weak)) void func (void)
+{
+  value += 4;
+}
+
+void dummy (void);
+extern int expected;
+
+int
+main (void)
+{
+  if (func)
+    func ();
+  dummy ();
+  if (value != expected)
+    {
+      printf ("expected %d, got %d\n", expected, value);
+      return 1;
+    }
+  return 0;
+}
diff --git a/ld/testsuite/ld-pe/weak-ext-main-weak.c b/ld/testsuite/ld-pe/weak-ext-main-weak.c
new file mode 100644
index 00000000000..bc1501f62c0
--- /dev/null
+++ b/ld/testsuite/ld-pe/weak-ext-main-weak.c
@@ -0,0 +1,22 @@
+/* Weak declaration of func (no definition).  */
+#include <stdio.h>
+
+__attribute__((weak)) void func (void);
+void dummy (void);
+
+int value = 1;
+extern int expected;
+
+int
+main (void)
+{
+  if (func)
+    func ();
+  dummy ();
+  if (value != expected)
+    {
+      printf ("expected %d, got %d\n", expected, value);
+      return 1;
+    }
+  return 0;
+}
diff --git a/ld/testsuite/ld-pe/weak-ext-main.c b/ld/testsuite/ld-pe/weak-ext-main.c
new file mode 100644
index 00000000000..916bb246e5f
--- /dev/null
+++ b/ld/testsuite/ld-pe/weak-ext-main.c
@@ -0,0 +1,21 @@
+/* Strong undefined reference to func.  */
+#include <stdio.h>
+
+void func (void);
+void dummy (void);
+
+int value = 1;
+extern int expected;
+
+int
+main (void)
+{
+  func ();
+  dummy ();
+  if (value != expected)
+    {
+      printf ("expected %d, got %d\n", expected, value);
+      return 1;
+    }
+  return 0;
+}
-- 
2.54.0


From gnutoolsweekly@gmail.com  Mon Jun 22 05:21:01 2026
From: gnutoolsweekly@gmail.com (GNU Tools weekly)
Date: Sun, 21 Jun 2026 22:21:01 -0700
Subject: GNU Tools Weekly News Week 43 (June 21, 2026)
In-Reply-To: <CAHt=NyNonbJn-qYgZy4UR54x_0g39iMtzGreWj+mp5sM2wJyOg@mail.gmail.com>
References: <CAHt=NyPpC47e6400=ZxqwJ5W5B2ABmhUZk+SWsRKSTdxVu4SVA@mail.gmail.com>
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 <CAHt=NyPaAZhqc3WSi1_WMBr=uZmZL=Jc2jwgQibeR1n6xwqyKA@mail.gmail.com>
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 <CAHt=NyORRFiB8Jy1sK6rAfJJy+XiV0RTGHZaXJuM4Bd5SkRkEw@mail.gmail.com>
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 <CAHt=NyPC4okeNg3HX3DWM4eV5Q8SJ7tV2Vzj===QftzBhTOupQ@mail.gmail.com>
 <CAHt=NyOHu7=XXWBWLnvvFsg63cOVuVYPUz5c-fQw05wT2=rUBw@mail.gmail.com>
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Message-ID: <CAHt=NyPsTpkp+cZ=MyYAjprMHzo_RkbSPAkZnaB1Bp-2rytbPw@mail.gmail.com>

GNU Tools Weekly News Week 43 (June 21, 2026)

Release updates for GNU toolchain:
 * GCC 14 branch is frozen for GCC 14.4.0 release
  * https://inbox.sourceware.org/gcc/7qp3n3rq-3935-0qnn-s4s9-425230sso679@fhfr.qr/
 * GCC 14.4.0 RC1 is done
  * https://inbox.sourceware.org/gcc/864p303q-o5n8-s3q4-9901-24o31420p21s@fhfr.qr/

GNU toolchain conference reminders:
 * FOSSY 2026 toolchain track North America, Aug 6-9 (Vancouver, Canada)
 * GNU Tools Cauldron 2026, Fri-Sun, October 2-4 (Prague, Czechia)
  * https://gcc.gnu.org/wiki/cauldron2026
  * https://conf.gnu-tools-cauldron.org/prg26/cfp
 * Toolchains Track at LPC 2026, October 7th (Prague, Czechia)
  * https://inbox.sourceware.org/gcc/CAKwvOdkaE7nHQbMRKBHmY6jE326bx=czi8yeL2qypsOj3Pq+Og@mail.gmail.com/
  * https://lpc.events/event/20/abstracts/

General/big GNU toolchain news (including sourceware news):
 * Acceptance of GCC WebAssembly Backend
  * https://inbox.sourceware.org/gcc/CAGWvny=AE17wQU5mfz8UGWybVBSsb_ffqHcthS78g8zdzK6xSw@mail.gmail.com/
 * Joel Brobecker is stepping down as a gdb release manager
  * https://inbox.sourceware.org/gdb-patches/536dc95f-540f-4a1a-9ccc-73b34eb50819@simark.ca/T/


GCC easy issue to tackle of the week:
 * strlen(s) != 0 not folded into *s (when separate statements)
  * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92408
  * Reach out to Andrea Pinski <andrew.pinski@oss.qualcomm.com> for
mentoring on this issue.
 * Previous ones are listed on https://gcc.gnu.org/wiki/EasyIssuesOfTheWeek


GCC commits:
 * https://gcc.gnu.org/r17-1560 ... r17-1732  173 commits
 * Ada updates (Thanks Marc)
  * Bug fixes.
  * Diagnostics improvements.
  * Constructor Flare extension adjustments.
  * https://gcc.gnu.org/r17-1633-g881cb10e96d875 ...
https://gcc.gnu.org/r17-1653-g52f6d044261933
  * https://gcc.gnu.org/r17-1688-g343265c50f930c ...
https://gcc.gnu.org/r17-1701-g3b0af59dc9e67f
 * match.pd: Recognize integer spaceship operator patterns
  * https://gcc.gnu.org/r17-1582-g7659926b80deaf
 * c++, libcpp: Add -std=c++2[9d] and -std=gnu++2[9d] options
  * https://gcc.gnu.org/r17-1595-g0c5c6249a2e9a7
 * prange was improved and is in use
  * https://gcc.gnu.org/r17-1601-g8b45cd81fc3509 ...
https://gcc.gnu.org/r17-1604-gca582ee36820a3
 * Add vec_deconstruct costing kind
  * https://gcc.gnu.org/r17-1655-g7d351b07e5b85c
 * match: mask/sub sign-extension idiom not canonicalized to sign extension
  * https://gcc.gnu.org/r17-1680-gc05164c348242b
 * match: Optimize bit_ior/bit_and {bit_not} rshift to min/max
  * https://gcc.gnu.org/r17-1683-g43356828d897ad
 * PHIOPT (ifcvt): load commonization/factoring
  * https://gcc.gnu.org/r17-1703-g3c0fd2976ab4f4 ...
https://gcc.gnu.org/r17-1705-gcf64e6b0e07355
 * Match: Support unsigned scalar SAT_MUL form 13
  * https://gcc.gnu.org/r17-1730-g971f8d5b5fd5ce ...
https://gcc.gnu.org/r17-1732-ga05799c29c50d7

GCC discussion:
 *

GCC bugzilla stats
 *  128 new issues filed
 *  91 issues closed

binutils/gdb commits:
 *

gdb discussion:
 *

binutils discussion:
 *

glibc commits:
 * riscv: Add RVV memmove for both multiarch and non-multiarch builds
  * https://sourceware.org/cgit/glibc/commit/?id=60f7247847ba7244541fc783079c298416756399

glibc discussion:
 *

From jiawei@iscas.ac.cn  Mon Jun 22 07:45:58 2026
From: jiawei@iscas.ac.cn (Jiawei)
Date: Mon, 22 Jun 2026 15:45:58 +0800
Subject: [PATCH v3 01/13] RISC-V: add dedicated vector arithmetic .insn
 forms
In-Reply-To: <81e3d6d0-39d3-42e3-a8cd-d6b11b8449a4@suse.com>
References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
 <81e3d6d0-39d3-42e3-a8cd-d6b11b8449a4@suse.com>
Message-ID: <73deccbb-7066-43b1-84c4-de6d309a2845@iscas.ac.cn>

> As .insn documentation states, using the available .insn forms can be a
> little challenging. For OP_V and OP_VE, help the situation by providing a
> few more dedicated forms.
> ---
> No form is provided for OPCFG: Such insns may better use "r" forms, or
> whatever is best suited there.
>
> For OPIVI permitting both signed (Vi) and unsigned (Vj) immediates might
> be nice, but won't work with the present parsing (needs delaying
> as_bad()).
>
> To help encoding V*UNARY* insns, forms with immediates in the respective
> positions may be helpful. Thoughts? (Some of the testcase additions are
> commented upon accordingly.)
> ---
> v3: Add O7 as first operand.
>
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -3660,6 +3660,17 @@ const struct riscv_opcode riscv_insn_typ
>   {"j",       0, INSN_CLASS_I,       "O7,d,a",            0, 0, NULL, 0 },
>   {"j",       0, INSN_CLASS_F,       "O7,D,a",            0, 0, NULL, 0 },
>   
> +{"ivv",     0, INSN_CLASS_V,       "O7,F6,Vd,Vt,VsVm", 0x0000, 0x7000, NULL, 0 },
> +{"fvv",     0, INSN_CLASS_ZVEF,    "O7,F6,Vd,Vt,VsVm", 0x1000, 0x7000, NULL, 0 },
> +{"fvv",     0, INSN_CLASS_ZVEF,    "O7,F6,D,Vt,VsVm",  0x1000, 0x7000, NULL, 0 },
> +{"mvv",     0, INSN_CLASS_V,       "O7,F6,Vd,Vt,VsVm", 0x2000, 0x7000, NULL, 0 },
> +{"mvv",     0, INSN_CLASS_V,       "O7,F6,d,Vt,VsVm",  0x2000, 0x7000, NULL, 0 },
> +{"ivi",     0, INSN_CLASS_V,       "O7,F6,Vd,Vt,ViVm", 0x3000, 0x7000, NULL, 0 },
> +{"ivx",     0, INSN_CLASS_V,       "O7,F6,Vd,Vt,sVm",  0x4000, 0x7000, NULL, 0 },
> +{"fvf",     0, INSN_CLASS_ZVEF,    "O7,F6,Vd,Vt,SVm",  0x5000, 0x7000, NULL, 0 },
> +{"mvx",     0, INSN_CLASS_V,       "O7,F6,Vd,Vt,sVm",  0x6000, 0x7000, NULL, 0 },
> +{"mvx",     0, INSN_CLASS_V,       "O7,F6,d,Vt,sVm",   0x6000, 0x7000, NULL, 0 },
> +
>   {"cr",      0, INSN_CLASS_ZCA,       "O2,CF4,d,CV",       0, 0, NULL, 0 },
>   {"cr",      0, INSN_CLASS_ZCF, "O2,CF4,D,CV",       0, 0, NULL, 0 },
>   {"cr",      0, INSN_CLASS_ZCF, "O2,CF4,d,CT",       0, 0, NULL, 0 },

LGTM.

Adding O7 as the first operand looks reasonable to me. It lets the vector
.insn forms cover both OP_V and OP_VE, while F6 still selects the operation
within the selected funct3 class.

Regarding the open questions:

* Not adding a dedicated OPCFG form looks fine to me. These encodings seem
less common, and using the generic r form should be acceptable there.

* Allowing both signed and unsigned immediate operands for OPIVI would 
be nice,
but I agree that this probably needs parser-side changes to avoid diagnosing
too early. That seems better handled as a follow-up.

* Dedicated forms for V*UNARY* encodings could make those cases clearer,
especially where an operand position is effectively used as an opcode or
immediate field. But I do not think that needs to block the current OP_V /
OP_VE arithmetic forms.

Reviewed-by: Jiawei <jiawei@iscas.ac.cn>


From jbeulich@suse.com  Mon Jun 22 07:46:18 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Mon, 22 Jun 2026 09:46:18 +0200
Subject: [PATCH] PE/COFF: auto-promote to bigobj target when section count
 overflows
In-Reply-To: <20260621174919.1150-3-oleg.tolmatcev@gmail.com>
References: <20260621174919.1150-3-oleg.tolmatcev@gmail.com>
Message-ID: <5b3cf7f1-a1a9-46fe-a0ec-2267f5a0cf22@suse.com>

On 21.06.2026 19:49, Oleg Tolmatcev wrote:
> Regular PE/COFF uses 16-bit section numbers in the symbol table,
> limiting objects to at most 65535 sections.  When this limit is
> exceeded, the assembler silently truncates section numbers, producing
> corrupt objects that cause confusing linker errors like:
> 
>   undefined reference to `vtable for ...'
> 
> Fix this by automatically switching the xvec to the matching bigobj
> target before any headers or symbols are finalized, so the object is
> written out using the extended COFF format which supports 32-bit
> section numbers.

It has never really become clear to me why this wouldn't have been the
default behavior from the very beginning. Perhaps with a way to opt out
(rather than one to opt in).

> --- a/bfd/coffcode.h
> +++ b/bfd/coffcode.h
> @@ -360,6 +360,10 @@ CODE_FRAGMENT
>  #include "coffswap.h"
>  #endif
>  
> +#ifdef COFF_WITH_PE_BIGOBJ
> +extern const bfd_target TARGET_SYM_BIG;
> +#endif
> +
>  #define STRING_SIZE_SIZE 4
>  
>  #define DOT_DEBUG	".debug"
> @@ -3154,6 +3158,16 @@ coff_compute_section_file_positions (bfd * abfd)
>  
>    if (target_index >= bfd_coff_max_nscns (abfd))
>      {
> +#ifdef COFF_WITH_PE_BIGOBJ
> +      if (abfd->xvec != &TARGET_SYM_BIG)
> +	{
> +	  /* Regular PE/COFF uses 16-bit section numbers in symbols.
> +	     Promote oversized objects to the matching bigobj target
> +	     before any headers or symbols are finalized.  */
> +	  abfd->xvec = &TARGET_SYM_BIG;
> +	  return coff_compute_section_file_positions (abfd);
> +	}
> +#endif
>        bfd_set_error (bfd_error_file_too_big);
>        _bfd_error_handler
>  	/* xgettext:c-format */

In the description you mention silent generation of a corrupt output. Yet then
you place your addition next to the emission of an error. If this error path
wasn't taken in the case of interest, your new addition also would take any
effect. What am I missing?

> --- /dev/null
> +++ b/gas/testsuite/gas/pe/big-obj-auto.d
> @@ -0,0 +1,9 @@
> +#objdump: -h
> +#name: PE big obj auto-promotion
> +
> +.*: *file format pe-bigobj-.*
> +
> +Sections:
> +#...
> +5000. \.data\$a49999  .*

5000. still fits in 16 bits. How is this sufficient a test for the new behavior?
I expect you want ...

> --- /dev/null
> +++ b/gas/testsuite/gas/pe/big-obj-auto.s
> @@ -0,0 +1,16 @@
> +	.file "big-obj-auto.s"
> +
> +	.irp n,0,1,2,3,4

	.irp n,0,1,2,3,4,5,6,7

here.

> +	.irp m,0,1,2,3,4,5,6,7,8,9
> +	.irp c,0,1,2,3,4,5,6,7,8,9
> +	.irp d,0,1,2,3,4,5,6,7,8,9
> +	.irp u,0,1,2,3,4,5,6,7,8,9
> +	.globl a\n\m\c\d\u
> +	.section .data$a\n\m\c\d\u,"w"
> +a\n\m\c\d\u :
> +	.byte 1
> +	.endr
> +	.endr
> +	.endr
> +	.endr
> +	.endr
> --- a/gas/testsuite/gas/pe/pe.exp
> +++ b/gas/testsuite/gas/pe/pe.exp
> @@ -70,4 +70,5 @@ if {[istarget "aarch64-*-pe*"] || [istarget "aarch64-*-mingw*"]} {
>  
>  if ([istarget "*-*-mingw*"]) then {
>  	run_dump_test "big-obj"
> +	run_dump_test "big-obj-auto"
>  }

Why would the test want limiting to MinGW?

Jan

From chen.zhongyao@zte.com.cn  Mon Jun 22 07:08:12 2026
From: chen.zhongyao@zte.com.cn (chen.zhongyao@zte.com.cn)
Date: Mon, 22 Jun 2026 15:08:12 +0800 (CST)
Subject: =?UTF-8?B?UmU6IFtQQVRDSF0gUklTQy1WOiBTdXBwb3J0IFp2YWJkIGV4dGVuc2lvbiBpbnN0cnVjdGlvbnMu?=
In-Reply-To: <fa55bd86-ff4e-492c-9a68-8a2921802bde@oss.qualcomm.com>
References: 20260528100602.475331-1-jiawei@iscas.ac.cn,
 fa55bd86-ff4e-492c-9a68-8a2921802bde@oss.qualcomm.com
Message-ID: <202606220746.65M7kqRZ016533@mse-fl1.zte.com.cn>

> OK.  Thanks for taking care of this.

Just checking status, seems no change requests. 
but it hasn't landed in trunk yet. Can anyone help push it ?



Regards,
Zhongyao

From jiawei@iscas.ac.cn  Mon Jun 22 08:47:01 2026
From: jiawei@iscas.ac.cn (Jiawei)
Date: Mon, 22 Jun 2026 16:47:01 +0800
Subject: [PATCH v3 04/13] bfd/RISC-V: Zv{b,k}* imply Zve32x
In-Reply-To: <0450f2b8-fa5b-4921-b330-d9fe2e2c54b2@suse.com>
References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
 <0450f2b8-fa5b-4921-b330-d9fe2e2c54b2@suse.com>
Message-ID: <7c0e8605-9a7a-4120-90ba-10a8054691ff@iscas.ac.cn>

Hi Jan,

I checked this locally with current binutils using as-new/readelf.

For the ordering question, the canonical order does not seem to come 
from the
order in riscv_supported_std_z_ext[]. riscv_compare_subsets() compares Z
extensions by the character after 'z' and then by a case-insensitive suffix
comparison. For Zv* extensions, this means the current canonical order is
roughly:

zvbb, zvbc, zve32x, zvkb, zvkg, zvkn*, zvks*

The assembler/readelf tests confirm this. For example, both

-march=rv32i_zvbc_zve32x
-march=rv32i_zve32x_zvbc

are canonicalized with zvbc before zve32x, while zvkb/zvkg/zvkn*/zvks* are
placed after zve32x. So the ordering in the updated imply.d output looks
consistent with the current canonicalization rule.

However, while testing the implied-dependency change, I noticed another
possible issue. With the new implicit rows, an input such as

-march=rv32i_zvbc

is canonicalized as:

rv32i2p1_zvbc1p0_zve32x1p0

whereas explicitly specifying zve32x, for example

-march=rv32i_zvbc_zve32x

produces:

rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zvl32b1p0

So adding zve32x through the new Zv{b,k}* implication does not seem to 
trigger
the further dependencies normally implied by zve32x. This looks like it may
come from the implicit-subset processing order / single forward scan.

Therefore, I think the canonical placement of zve32x in the test is correct
for the current ordering rule, but we may need to clarify whether the 
implied
dependency should also pull in the full zve32x dependency closure.

BR,
Jiawei

On 2026/6/19 19:48, Jan Beulich wrote:
> The specification is quite explicit about this.
> ---
> Is the placement of "zve32x" after "zvbb" / "zvbc" actually correct? While
> riscv_compare_subsets() indeed does a mere strcasecmp() past "zv", it
> seems unlikely to be mere chance that Zve* come ahead of all other Zv* in
> riscv_supported_std_z_ext[].
> ---
> v3: New.
>
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1306,6 +1306,15 @@ static const struct riscv_implicit_subse
>     {"zvksc", "+zvks,+zvbc", check_implicit_always},
>     {"zvks", "+zvksed,+zvksh,+zvkb,+zvkt", check_implicit_always},
>   
> +  {"zvbc", "+zve32x", check_implicit_always},
> +  {"zvkb", "+zve32x", check_implicit_always},
> +  {"zvkg", "+zve32x", check_implicit_always},
> +  {"zvkned", "+zve32x", check_implicit_always},
> +  {"zvknha", "+zve32x", check_implicit_always},
> +  {"zvknhb", "+zve32x", check_implicit_always},
> +  {"zvksed", "+zve32x", check_implicit_always},
> +  {"zvksh", "+zve32x", check_implicit_always},
> +
>     {"sdtrig", "+zicsr", check_implicit_always},
>   
>     {"smaia", "+ssaia", check_implicit_always},
> --- a/gas/testsuite/gas/riscv/imply.d
> +++ b/gas/testsuite/gas/riscv/imply.d
> @@ -87,13 +87,13 @@ SYMBOL TABLE:
>   [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0
>   [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0
>   [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0
> -[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvbb1p0_zvkb1p0
> -[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0
> -[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvbc1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0
> -[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0
> -[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0
> -[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvbc1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0
> -[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0
> +[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvbb1p0_zve32x1p0_zvkb1p0
> +[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zve32x1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0
> +[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvbc1p0_zve32x1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0
> +[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zve32x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0
> +[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zve32x1p0_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0
> +[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zvbc1p0_zve32x1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0
> +[0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zve32x1p0_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0
>   [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_sdtrig1p0
>   [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_smaia1p0_ssaia1p0
>   [0-9a-f]+ l       .text	0+000 \$xrv32i2p1_zicsr2p0_smcdeleg1p0_ssccfg1p0_sscsrind1p0


From jiawei@iscas.ac.cn  Mon Jun 22 09:02:40 2026
From: jiawei@iscas.ac.cn (Jiawei)
Date: Mon, 22 Jun 2026 17:02:40 +0800
Subject: [PATCH v3 12/13] RISC-V/bfd: warn about non-boolean
 unaligned-access attribute
In-Reply-To: <3ecb6e90-f46f-46de-ba79-f4188e25e58f@suse.com>
References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
 <3ecb6e90-f46f-46de-ba79-f4188e25e58f@suse.com>
Message-ID: <3aad8208-9d61-4a78-a904-6faa6c2af959@iscas.ac.cn>

On 2026/6/19 19:52, Jan Beulich wrote:
> The attribute being a boolean one, incoming values should be solely 0 or
> 1. Convert other non-zero values to 1.
> ---
> v3: New.
>
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -3777,6 +3777,23 @@ riscv_merge_attributes (bfd *ibfd, struc
>   	 initialized.  */
>         out_attr[0].i = 1;
>   
> +      for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
> +	{
> +	  switch (i)
> +	    {
> +	    case Tag_RISCV_unaligned_access:
> +	      if (out_attr[i].i <= 1)
> +		break;
> +
> +	      _bfd_error_handler
> +		(_("warning: %pB uses non-boolean `unaligned access' attribute; "
> +		   "converting to boolean"),
> +		 ibfd);
> +	      out_attr[i].i = 1;
> +	      break;
> +	    }
> +	}
> +
>         return true;
>       }
>   
> @@ -3865,7 +3882,12 @@ riscv_merge_attributes (bfd *ibfd, struc
>   	break;
>   
>         case Tag_RISCV_unaligned_access:
> -	out_attr[i].i |= in_attr[i].i;
> +	if (in_attr[i].i > 1)
> +	  _bfd_error_handler
> +	    (_("warning: %pB uses non-boolean `unaligned access' attribute; "
> +	       "converting to boolean"),
> +	     ibfd);
> +	out_attr[i].i |= !!in_attr[i].i;
>   	break;
>   
>         case Tag_RISCV_stack_align:

LGTM.

Checking the copied attributes for the first input
object is necessary, since otherwise a non-boolean unaligned_access 
value from
the first object would be carried into the output unchanged.

One very small wording thought: the gas-side diagnostic uses
`unaligned_access', while this one uses `unaligned access'. Either is fine
with me, using the same spelling might make the diagnostics more
consistent, but this does not need to block the patch.

Reviewed-by: Jiawei jiawei@iscas.ac.cn


From nickc@redhat.com  Mon Jun 22 09:10:55 2026
From: nickc@redhat.com (Nick Clifton)
Date: Mon, 22 Jun 2026 10:10:55 +0100
Subject: Upcoming 2.47 branch and release dates
Message-ID: <87h5mvym74.fsf@redhat.com>

Hi Guys,

  The time for the 2.47 release is coming up fast.  My current plans
  are:

    Create the branch:   Sat 11 July
    Create the release:  Sat 25 July

  So now is the time to get any important fixes or features in...

  The dates are adjustable, if necessary, but I would prefer to stick to
  the timetable if I can.

Cheers
  Nick


From jbeulich@suse.com  Mon Jun 22 09:15:06 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Mon, 22 Jun 2026 11:15:06 +0200
Subject: [PATCH v3 12/13] RISC-V/bfd: warn about non-boolean
 unaligned-access attribute
In-Reply-To: <3aad8208-9d61-4a78-a904-6faa6c2af959@iscas.ac.cn>
References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
 <3ecb6e90-f46f-46de-ba79-f4188e25e58f@suse.com>
 <3aad8208-9d61-4a78-a904-6faa6c2af959@iscas.ac.cn>
Message-ID: <c2d97fc1-1dca-4e56-b14d-4a27e2e5a3a5@suse.com>

On 22.06.2026 11:02, Jiawei wrote:
> On 2026/6/19 19:52, Jan Beulich wrote:
>> The attribute being a boolean one, incoming values should be solely 0 or
>> 1. Convert other non-zero values to 1.
>> ---
>> v3: New.
>>
>> --- a/bfd/elfxx-riscv.c
>> +++ b/bfd/elfxx-riscv.c
>> @@ -3777,6 +3777,23 @@ riscv_merge_attributes (bfd *ibfd, struc
>>   	 initialized.  */
>>         out_attr[0].i = 1;
>>   
>> +      for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
>> +	{
>> +	  switch (i)
>> +	    {
>> +	    case Tag_RISCV_unaligned_access:
>> +	      if (out_attr[i].i <= 1)
>> +		break;
>> +
>> +	      _bfd_error_handler
>> +		(_("warning: %pB uses non-boolean `unaligned access' attribute; "
>> +		   "converting to boolean"),
>> +		 ibfd);
>> +	      out_attr[i].i = 1;
>> +	      break;
>> +	    }
>> +	}
>> +
>>         return true;
>>       }
>>   
>> @@ -3865,7 +3882,12 @@ riscv_merge_attributes (bfd *ibfd, struc
>>   	break;
>>   
>>         case Tag_RISCV_unaligned_access:
>> -	out_attr[i].i |= in_attr[i].i;
>> +	if (in_attr[i].i > 1)
>> +	  _bfd_error_handler
>> +	    (_("warning: %pB uses non-boolean `unaligned access' attribute; "
>> +	       "converting to boolean"),
>> +	     ibfd);
>> +	out_attr[i].i |= !!in_attr[i].i;
>>   	break;
>>   
>>         case Tag_RISCV_stack_align:
> 
> LGTM.
> 
> Checking the copied attributes for the first input
> object is necessary, since otherwise a non-boolean unaligned_access 
> value from
> the first object would be carried into the output unchanged.
> 
> One very small wording thought: the gas-side diagnostic uses
> `unaligned_access', while this one uses `unaligned access'. Either is fine
> with me, using the same spelling might make the diagnostics more
> consistent, but this does not need to block the patch.

Oh, thanks for noticing. I've added in the underscores, also for the subsequent
stack-align patch.

> Reviewed-by: Jiawei jiawei@iscas.ac.cn

Thanks.

Jan

From hjl.tools@gmail.com  Mon Jun 22 09:29:20 2026
From: hjl.tools@gmail.com (H.J. Lu)
Date: Mon, 22 Jun 2026 17:29:20 +0800
Subject: Upcoming 2.47 branch and release dates
In-Reply-To: <87h5mvym74.fsf@redhat.com>
References: <87h5mvym74.fsf@redhat.com>
Message-ID: <CAMe9rOpMuwTZDkKqWCx9J5d+SRO9ySUiTKjdY7G=04wOE2cGYA@mail.gmail.com>

On Mon, Jun 22, 2026 at 5:11?PM Nick Clifton <nickc@redhat.com> wrote:
>
> Hi Guys,
>
>   The time for the 2.47 release is coming up fast.  My current plans
>   are:
>
>     Create the branch:   Sat 11 July
>     Create the release:  Sat 25 July
>
>   So now is the time to get any important fixes or features in...

Hi Nick,

Can you review the fix

https://sourceware.org/pipermail/binutils/2026-June/149706.html

for

https://sourceware.org/bugzilla/show_bug.cgi?id=34184

Thanks.

>   The dates are adjustable, if necessary, but I would prefer to stick to
>   the timetable if I can.
>
> Cheers
>   Nick
>


-- 
H.J.

From jbeulich@suse.com  Mon Jun 22 09:31:19 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Mon, 22 Jun 2026 11:31:19 +0200
Subject: [PATCH v3 04/13] bfd/RISC-V: Zv{b,k}* imply Zve32x
In-Reply-To: <7c0e8605-9a7a-4120-90ba-10a8054691ff@iscas.ac.cn>
References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
 <0450f2b8-fa5b-4921-b330-d9fe2e2c54b2@suse.com>
 <7c0e8605-9a7a-4120-90ba-10a8054691ff@iscas.ac.cn>
Message-ID: <681dc57d-8356-4f29-8d99-5ade5175d07b@suse.com>

On 22.06.2026 10:47, Jiawei wrote:
> I checked this locally with current binutils using as-new/readelf.
> 
> For the ordering question, the canonical order does not seem to come 
> from the
> order in riscv_supported_std_z_ext[]. riscv_compare_subsets() compares Z
> extensions by the character after 'z' and then by a case-insensitive suffix
> comparison. For Zv* extensions, this means the current canonical order is
> roughly:
> 
> zvbb, zvbc, zve32x, zvkb, zvkg, zvkn*, zvks*
> 
> The assembler/readelf tests confirm this. For example, both
> 
> -march=rv32i_zvbc_zve32x
> -march=rv32i_zve32x_zvbc
> 
> are canonicalized with zvbc before zve32x, while zvkb/zvkg/zvkn*/zvks* are
> placed after zve32x. So the ordering in the updated imply.d output looks
> consistent with the current canonicalization rule.
> 
> However, while testing the implied-dependency change, I noticed another
> possible issue. With the new implicit rows, an input such as
> 
> -march=rv32i_zvbc
> 
> is canonicalized as:
> 
> rv32i2p1_zvbc1p0_zve32x1p0
> 
> whereas explicitly specifying zve32x, for example
> 
> -march=rv32i_zvbc_zve32x
> 
> produces:
> 
> rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zvl32b1p0
> 
> So adding zve32x through the new Zv{b,k}* implication does not seem to 
> trigger
> the further dependencies normally implied by zve32x. This looks like it may
> come from the implicit-subset processing order / single forward scan.

So this comment

/* Please added in order since this table is only run once time.  */

really is misleading. "in order" doesn't quite get it, as apparently only
forward references are permitted within the table. That then means that
the patch needs to move up the whole Zv{b,k} group as well.

Jan

From jiawei@iscas.ac.cn  Mon Jun 22 09:35:59 2026
From: jiawei@iscas.ac.cn (Jiawei)
Date: Mon, 22 Jun 2026 17:35:59 +0800
Subject: [PATCH v3 13/13] RISC-V/bfd: warn about non-power-of-2
 stack-align attribute
In-Reply-To: <2fcf62ca-0e51-48fc-a9cf-7a48a40dc82e@suse.com>
References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
 <2fcf62ca-0e51-48fc-a9cf-7a48a40dc82e@suse.com>
Message-ID: <585fe2dc-6c63-40c1-a0d6-5c658a825afd@iscas.ac.cn>

On 2026/6/19 19:53, Jan Beulich wrote:
> Only power-of-2 values are sensible for alignment. Reject other values.
>
> While there also drop a redundant part of a related conditional.
> ---
> v3: New.
>
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -3791,6 +3791,17 @@ riscv_merge_attributes (bfd *ibfd, struc
>   		 ibfd);
>   	      out_attr[i].i = 1;
>   	      break;
> +
> +	    case Tag_RISCV_stack_align:
> +	      if (!(out_attr[i].i & (out_attr[i].i - 1)))
> +		break;
> +
> +	      _bfd_error_handler
> +		(_("warning: %pB uses non-power-of-2 `stack align' attribute; "
> +		   "ignoring"), + ibfd); + out_attr[i].i = 0; + break; } } @@ -3891,10 +3902,14 @@ 
> riscv_merge_attributes (bfd *ibfd, struc break; case 
> Tag_RISCV_stack_align: - if (out_attr[i].i == 0) + if ((in_attr[i].i & 
> (in_attr[i].i - 1)) != 0) + _bfd_error_handler + (_("warning: %pB uses non-power-of-2 `stack align' attribute; "
> +	       "ignoring"),
> +	     ibfd);
> +	else if (out_attr[i].i == 0)
>   	  out_attr[i].i = in_attr[i].i;
>   	else if (in_attr[i].i != 0
> -		 && out_attr[i].i != 0
>   		 && out_attr[i].i != in_attr[i].i)
>   	  {
>   	    _bfd_error_handler

I tested the first-object path specifically. With the patch behavior
reproduced, an input object containing a non-power-of-2 stack_align value,

for example
.attribute stack_align, 0x4444

emits the warning, and the ld -r output omits Tag_RISCV_stack_align 
entirely.

The readelf shows this as Tag_RISCV_stack_align: 17476-bytes?
It does not emit an explicit 0-byte stack alignment attribute. So setting

out_attr[Tag_RISCV_stack_align].i = 0

appears to be sufficient to ignore the invalid value.

I also checked the merge cases. invalid + valid16 and valid16 + invalid both
emit the warning for the invalid object and keep the valid 16-byte stack
alignment in the output. An explicit input

.attribute stack_align, 0

is also omitted from the object, so zero behaves consistently as "unset" 
from
the BFD merge point of view.

The existing valid non-zero mismatch behavior is unchanged: linking 16-byte
and 32-byte stack alignment objects still errors as before.

Reviewed-by: Jiawei jiawei@iscas.ac.cn
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From abhay@linux.ibm.com  Mon Jun 22 10:14:08 2026
From: abhay@linux.ibm.com (Abhay Kandpal)
Date: Mon, 22 Jun 2026 05:14:08 -0500
Subject: [PATCH v1] PowerPC: Add NT_PPC_DMR core file support
Message-ID: <20260622101408.1384811-1-abhay@linux.ibm.com>

Add BFD and readelf support for the new NT_PPC_DMR note type, which
carries the contents of the Dense Math Registers (DMR) available on
a future PowerPC processor. The DMR register set consists of eight
1024-bit registers introduced by the Dense Math facility in a future
Power ISA revision.

GDB support for reading and writing DMR registers, both from live
processes and from core files, will be added as a follow-up patch.

bfd/
	* elf-bfd.h (elfcore_write_ppc_dmr): Declare.
	* elf.c (NOTE_PSEUDO_SECTION_PPC_DMR): Define.
	(elfcore_grok_ppc_dmr): New function.
	(elfcore_grok_note) <NT_PPC_DMR>: Handle it.
	(elfcore_write_ppc_dmr): New function.
	(elfcore_write_register_note): Handle .reg-ppc-dmr.

binutils/
	* readelf.c (get_note_type) <NT_PPC_DMR>: Handle it.

include/
	* elf/common.h (NT_PPC_DMR): New macro.
---
This patch is reg tested.

 bfd/elf-bfd.h        |  2 ++
 bfd/elf.c            | 20 ++++++++++++++++++++
 binutils/readelf.c   |  2 ++
 include/elf/common.h |  2 ++
 4 files changed, 26 insertions(+)

diff --git a/bfd/elf-bfd.h b/bfd/elf-bfd.h
index 88d35925987..0605d31107f 100644
--- a/bfd/elf-bfd.h
+++ b/bfd/elf-bfd.h
@@ -3100,6 +3100,8 @@ extern char *elfcore_write_ppc_tm_cppr
   (bfd *, char *, int *, const void *, int);
 extern char *elfcore_write_ppc_tm_cdscr
   (bfd *, char *, int *, const void *, int);
+extern char *elfcore_write_ppc_dmr
+  (bfd *, char *, int *, const void *, int);
 extern char *elfcore_write_s390_timer
   (bfd *, char *, int *, const void *, int);
 extern char *elfcore_write_s390_todcmp
diff --git a/bfd/elf.c b/bfd/elf.c
index c9a68404e9d..d0769d03644 100644
--- a/bfd/elf.c
+++ b/bfd/elf.c
@@ -80,6 +80,7 @@ SECTION
 #define NOTE_PSEUDO_SECTION_LOONGARCH_LASX	".reg-loongarch-lasx"
 #define NOTE_PSEUDO_SECTION_LOONGARCH_LBT	".reg-loongarch-lbt"
 #define NOTE_PSEUDO_SECTION_LOONGARCH_LSX	".reg-loongarch-lsx"
+#define NOTE_PSEUDO_SECTION_PPC_DMR		".reg-ppc-dmr"
 #define NOTE_PSEUDO_SECTION_PPC_DSCR		".reg-ppc-dscr"
 #define NOTE_PSEUDO_SECTION_PPC_EBB		".reg-ppc-ebb"
 #define NOTE_PSEUDO_SECTION_PPC_PMU		".reg-ppc-pmu"
@@ -10507,6 +10508,12 @@ elfcore_grok_ppc_vsx (bfd *abfd, Elf_Internal_Note *note)
   return elfcore_make_note_pseudosection (abfd, NOTE_PSEUDO_SECTION_PPC_VSX, note);
 }
 
+static bool
+elfcore_grok_ppc_dmr (bfd *abfd, Elf_Internal_Note *note)
+{
+  return elfcore_make_note_pseudosection (abfd, NOTE_PSEUDO_SECTION_PPC_DMR, note);
+}
+
 static bool
 elfcore_grok_ppc_tar (bfd *abfd, Elf_Internal_Note *note)
 {
@@ -11193,6 +11200,7 @@ elfcore_grok_note (bfd *abfd, Elf_Internal_Note *note)
 	case NT_LARCH_LASX:	return elfcore_grok_loongarch_lasx (abfd, note);
 	case NT_LARCH_LBT:	return elfcore_grok_loongarch_lbt (abfd, note);
 	case NT_LARCH_LSX:	return elfcore_grok_loongarch_lsx (abfd, note);
+	case NT_PPC_DMR:	return elfcore_grok_ppc_dmr (abfd, note);
 	case NT_PPC_DSCR:	return elfcore_grok_ppc_dscr (abfd, note);
 	case NT_PPC_EBB:	return elfcore_grok_ppc_ebb (abfd, note);
 	case NT_PPC_PMU:	return elfcore_grok_ppc_pmu (abfd, note);
@@ -12459,6 +12467,17 @@ elfcore_write_ppc_vsx (bfd *abfd,
 			     NOTE_NAME_LINUX, NT_PPC_VSX, ppc_vsx, size);
 }
 
+char *
+elfcore_write_ppc_dmr (bfd *abfd,
+		       char *buf,
+		       int *bufsiz,
+		       const void *ppc_dmr,
+		       int size)
+{
+  return elfcore_write_note (abfd, buf, bufsiz,
+			     NOTE_NAME_LINUX, NT_PPC_DMR, ppc_dmr, size);
+}
+
 char *
 elfcore_write_ppc_tar (bfd *abfd,
 		       char *buf,
@@ -13040,6 +13059,7 @@ elfcore_write_register_note (bfd *abfd,
       { NOTE_PSEUDO_SECTION_LOONGARCH_LASX,   elfcore_write_loongarch_lasx},
       { NOTE_PSEUDO_SECTION_LOONGARCH_LBT,    elfcore_write_loongarch_lbt},
       { NOTE_PSEUDO_SECTION_LOONGARCH_LSX,    elfcore_write_loongarch_lsx},
+      { NOTE_PSEUDO_SECTION_PPC_DMR,          elfcore_write_ppc_dmr},
       { NOTE_PSEUDO_SECTION_PPC_DSCR,         elfcore_write_ppc_dscr},
       { NOTE_PSEUDO_SECTION_PPC_EBB,          elfcore_write_ppc_ebb},
       { NOTE_PSEUDO_SECTION_PPC_PMU,          elfcore_write_ppc_pmu},
diff --git a/binutils/readelf.c b/binutils/readelf.c
index bf27f9eec23..aed0b058732 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -21847,6 +21847,8 @@ get_note_type (Filedata * filedata, unsigned e_type)
 	return _("NT_PPC_TM_CPPR (ppc checkpointed PPR register)");
       case NT_PPC_TM_CDSCR:
 	return _("NT_PPC_TM_CDSCR (ppc checkpointed DSCR register)");
+      case NT_PPC_DMR:
+	return _("NT_PPC_DMR (ppc Dense Math registers)");
       case NT_386_TLS:
 	return _("NT_386_TLS (x86 TLS information)");
       case NT_386_IOPERM:
diff --git a/include/elf/common.h b/include/elf/common.h
index 1ae68221a89..bd327194b7e 100644
--- a/include/elf/common.h
+++ b/include/elf/common.h
@@ -686,6 +686,8 @@
 					/*   note name must be "LINUX".  */
 #define NT_PPC_TM_CDSCR	0x10f		/* PowerPC TM checkpointed Data SCR */
 					/*   note name must be "LINUX".  */
+#define NT_PPC_DMR	0x113		/* PowerPC Dense Math Registers */
+					/*   note name must be "LINUX".  */
 #define NT_386_TLS	0x200		/* x86 TLS information */
 					/*   note name must be "LINUX".  */
 #define NT_386_IOPERM	0x201		/* x86 io permissions */
-- 
2.52.0


From SunilKumar.Dora@windriver.com  Mon Jun 22 11:06:00 2026
From: SunilKumar.Dora@windriver.com (Dora, Sunil Kumar)
Date: Mon, 22 Jun 2026 11:06:00 +0000
Subject: Does commit c2bf7de1 fix CVE-2026-3441 and CVE-2026-3442?
Message-ID: <DS0PR11MB7901E161B4E1B75EFA3655BBE0EF2@DS0PR11MB7901.namprd11.prod.outlook.com>

Hi,

I'm looking at commit c2bf7de1eb7<https://sourceware.org/git/?p=binutils-gdb.git;a=patch;h=c2bf7de1eb77a91d7a3c86d56408bf57de540faf> <https://sourceware.org/git/?p=binutils-gdb.git;a=patch;h=c2bf7de1eb77a91d7a3c86d56408bf57de540faf> ("xcofflink buffer overflows") for a downstream update and want to tag it correctly.

The diff fixes two out-of-bounds reads in xcoff_link_add_symbols: the x_scnlen index check and the r_symndx check. That looks like it matches Red Hat's CVE-2026-3441<https://nvd.nist.gov/vuln/detail/CVE-2026-3441> and CVE-2026-3442<https://nvd.nist.gov/vuln/detail/CVE-2026-3442> (bugs 2443826 and 2443828).

Can someone confirm this commit is the fix for those two CVEs? And do the two hunks map to one CVE each, or do both CVEs cover the whole change?

Also, is this planned for the binutils-2_46-branch / a 2.46.2 release ?
And would it be OK if I send a backport request for this commit to binutils-2_46-branch?

Thanks,
Sunil
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From jbeulich@suse.com  Mon Jun 22 11:18:41 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Mon, 22 Jun 2026 13:18:41 +0200
Subject: Does commit c2bf7de1 fix CVE-2026-3441 and CVE-2026-3442?
In-Reply-To: <DS0PR11MB7901E161B4E1B75EFA3655BBE0EF2@DS0PR11MB7901.namprd11.prod.outlook.com>
References: <DS0PR11MB7901E161B4E1B75EFA3655BBE0EF2@DS0PR11MB7901.namprd11.prod.outlook.com>
Message-ID: <498eed95-ec09-4b4f-a6e0-37ffd9c4d5f8@suse.com>

On 22.06.2026 13:06, Dora, Sunil Kumar via Binutils wrote:
> I'm looking at commit c2bf7de1eb7<https://sourceware.org/git/?p=binutils-gdb.git;a=patch;h=c2bf7de1eb77a91d7a3c86d56408bf57de540faf> <https://sourceware.org/git/?p=binutils-gdb.git;a=patch;h=c2bf7de1eb77a91d7a3c86d56408bf57de540faf> ("xcofflink buffer overflows") for a downstream update and want to tag it correctly.
> 
> The diff fixes two out-of-bounds reads in xcoff_link_add_symbols: the x_scnlen index check and the r_symndx check. That looks like it matches Red Hat's CVE-2026-3441<https://nvd.nist.gov/vuln/detail/CVE-2026-3441> and CVE-2026-3442<https://nvd.nist.gov/vuln/detail/CVE-2026-3442> (bugs 2443826 and 2443828).
> 
> Can someone confirm this commit is the fix for those two CVEs? And do the two hunks map to one CVE each, or do both CVEs cover the whole change?
> 
> Also, is this planned for the binutils-2_46-branch / a 2.46.2 release ?
> And would it be OK if I send a backport request for this commit to binutils-2_46-branch?

No and no. See in particular the first paragraph of [1]. But there had been
earlier discussions on this same underlying topic.

Jan

[1] https://sourceware.org/pipermail/binutils/2026-June/149585.html

From jremus@linux.ibm.com  Mon Jun 22 12:12:02 2026
From: jremus@linux.ibm.com (Jens Remus)
Date: Mon, 22 Jun 2026 14:12:02 +0200
Subject: [PATCH v2 0/1] s390: Deprecate s390 32-bit target "s390-*"
In-Reply-To: <20260423120006.3740571-1-jremus@linux.ibm.com>
References: <20260423120006.3740571-1-jremus@linux.ibm.com>
Message-ID: <120f8ebe-8052-45b2-80df-92bbeb148e34@linux.ibm.com>

On 4/23/2026 2:00 PM, Jens Remus wrote:
> Linux Kernel 6.19 removed s390 32-bit compatibility support. [1]
> Glibc 2.43 deprecated s390 32-bit [2] and will remove it with
> Glibc 2.44 [3].  GCC 16 will deprecate s390 32-bit (compiler option
> -m31) with the intent to remove it in a future release. [4]
> 
> This deprecates s390 32-bit (target "s390-*" and format "elf32-s390")
> in the upcoming Binutils and GDB release with the intent to remove it
> in a future release.

The Binutils 2.47 release is approaching, with the following planned
schedule:

  Create the branch:   Sat 11 July
  Create the release:  Sat 25 July

Andreas K., could you please approve for the Binutils s390 targets?
Andreas A. could then subsequently approve for the GDB s390 targets.

> 
> s390 32-bit deprecation/removal overview:
> - Linux Kernel 6.19 (February 2026) removed s390 32-bit compat
> - Glibc 2.43 (January 2026) deprecated s390 32-bit
> - GCC 16 (expected April 2026) will deprecate s390 32-bit
> - Glibc 2.44 (expected August 2026) will remove s390 32-bit
> - Binutils 2.47 (expected August 2026) would deprecate s390 32-bit
> - Binutils 2.48 (expected February 2027) would remove s390 32-bit
> - GCC 17 (expected April 2027) would remove s390 32-bit
> 
> Removal of s390 32-bit support in Binutils could also be deferred to
> Binutils 2.49 (expected August 2027) if that would be preferable, so
> that Binutils removes it after GCC.
> 
> Note that the error is actually not issued during a toplevel configure,
> as configure in bfd/ is actually deferred to make.  Should this be
> improved, for instance by replicating commit 91fb2a9d47c5 ("Add code to
> catch obsolete configurations ...") to configure.ac?
> 
> Changes in v2:
> - Add likewise gdb/NEWS entry, as the deprecation/removal in also
>   affects GDB.
> 
> Feedback is much appreciated!
> 
> [1]: Linux kernel 6.19 commit 8e0b986c59c6 ("s390: Remove compat support"),
>      https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=8e0b986c59c6
> [2]: Glibc 2.43 commit 638d437dbf9c ("Deprecate s390-linux-gnu (31bit)"),
>      https://sourceware.org/git/glibc.git?a=commitdiff;h=638d437dbf9c
> [3]: Glibc 2.44 patch series "[PATCH 0/5] Remove s390-linux-gnu (31bit)",
>      https://inbox.sourceware.org/libc-alpha/20260409085102.3475867-1-stli@linux.ibm.com/
> [4]: GCC 16 commit 5886bb453a6a ("s390: Deprecate -m31"),
>      https://gcc.gnu.org/git/gcc.git?h=5886bb453a6a
Thanks and regards,
Jens
-- 
Jens Remus
Linux on Z Development (D3303)
jremus@de.ibm.com / jremus@linux.ibm.com

IBM Deutschland Research & Development GmbH; Vorsitzender des Aufsichtsrats: Wolfgang Wendt; Gesch?ftsf?hrung: David Faller; Sitz der Gesellschaft: Ehningen; Registergericht: Amtsgericht Stuttgart, HRB 243294
IBM Data Privacy Statement: https://www.ibm.com/privacy/


From jremus@linux.ibm.com  Mon Jun 22 12:14:38 2026
From: jremus@linux.ibm.com (Jens Remus)
Date: Mon, 22 Jun 2026 14:14:38 +0200
Subject: [PATCH] s390: Add store CPU counter multiple instruction
In-Reply-To: <20260424084026.2959245-1-jremus@linux.ibm.com>
References: <20260424084026.2959245-1-jremus@linux.ibm.com>
Message-ID: <8fd02a7f-10c7-4db0-aeb8-bd70099cdd7b@linux.ibm.com>

On 4/24/2026 10:40 AM, Jens Remus wrote:
> IBM z13 introduced the "store CPU counter multiple" (stcctm) instruction
> with the Store-CPU-Counter-Multiple Facility, which is part of the
> CPU-Measurement Facilities (CPUMF) [1].
> 
> While at it add a comment to the s390 opcode table for the existing
> CPUMF instructions.

Gentle ping, due to approaching Binutils 2.47 release cutoff date.

> 
> [1]: The Load-Program-Parameter and the CPU-Measurement Facilities,
>      SA23-2260-08,
>      https://www.ibm.com/docs/en/module_1678991624569/pdf/SA23-2260-08.pdf
> 
> opcodes/
> 	* s390-opc.txt (stcctm): Add store CPU counter multiple
> 	instruction.  Add comment on CPUMF instructions.
> 
> gas/testsuite/
> 	* gas/s390/zarch-z13.d (stcctm): Add test for store CPU counter
> 	multiple instruction.
> 	* gas/s390/zarch-z13.s (stcctm): Likewise.
> 
> Signed-off-by: Jens Remus <jremus@linux.ibm.com>
> ---
>  gas/testsuite/gas/s390/zarch-z13.d | 2 ++
>  gas/testsuite/gas/s390/zarch-z13.s | 1 +
>  opcodes/s390-opc.txt               | 8 ++++++++
>  3 files changed, 11 insertions(+)
Thanks and regards,
Jens
-- 
Jens Remus
Linux on Z Development (D3303)
jremus@de.ibm.com / jremus@linux.ibm.com

IBM Deutschland Research & Development GmbH; Vorsitzender des Aufsichtsrats: Wolfgang Wendt; Gesch?ftsf?hrung: David Faller; Sitz der Gesellschaft: Ehningen; Registergericht: Amtsgericht Stuttgart, HRB 243294
IBM Data Privacy Statement: https://www.ibm.com/privacy/


From jiawei@iscas.ac.cn  Mon Jun 22 13:35:51 2026
From: jiawei@iscas.ac.cn (Jiawei)
Date: Mon, 22 Jun 2026 21:35:51 +0800
Subject: [PATCH v3 00/13] RISC-V: assorted fixes and (hopefully)
 improvements
In-Reply-To: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
References: <8243b692-4895-420c-b2d0-27ee3b714732@suse.com>
Message-ID: <d34ab0fc-ea35-4d64-a6de-26c2c30a5789@iscas.ac.cn>

On 2026/6/19 19:45, Jan Beulich wrote:
> [1]https://sourceware.org/pipermail/binutils/2023-March/126601.html

Hi Jan,

I did a more detailed local investigation of this old RFC.

I tested this on current trunk and also on a checkout close to the original
RFC date, around 2023-03-10. The exact numeric altmacro testcase from the
old RFC, using

m1 %v2-v1 17
m2b 81 243

already emits the expected bytes

a2 11

both on current trunk and on the 2023-03-10 checkout I tested. So that
testcase by itself does not demonstrate the issue for me.

However, the underlying problem still seems to exist. A symbolic variant:

.equ s1, 81
.equ s2, 243
m1 %s2-s1 17

fails without the patch with:

% operator needs absolute expression

GDB shows temp_ilp() parsing the string

s2-s1 17

and get_symbol_name() later seeing

s1 17

while input_from_string is true. Since RISC-V currently uses space as
FAKE_LABEL_CHAR, the generic expression parser can treat that space as part
of the symbol-name scan in this mode. That looks like the concrete root
cause.

Rebasing the RFC idea to use ".L0?" / '?' fixes this symbolic testcase. I
also kept the gas/app.c lex[] change from the RFC, so that 
FAKE_LABEL_CHAR is
accepted by the scrubber as part of generated/internal symbol names when
needed. In my tests this did not make ordinary unquoted '?' symbols 
accepted:
"user?symbol:" was still rejected, while quoted user symbols such as
"user?symbol" remained visible. So '?' looks like a reasonable replacement:
it is not a whitespace separator like the current space character, and I did
not see it introduce broad user-symbol parsing or hiding regressions in the
cases I tested.

I also think the gas/write.h comment update is still useful. The old RISC-V
choice of a space character shows that FAKE_LABEL_CHAR should not merely be
distinct from normal symbol characters; it also should not be a separator or
an operator-start character.

I rebuilt all-gas/all-binutils and ran:

make check-gas RUNTEST=... RUNTESTFLAGS="gas/all/gas.exp=altmacro"
# of expected passes? ? ? ? ? ? 112
# of expected failures? ? ? ? ? 8
# of unsupported tests? ? ? ? ? 2

make check-gas RUNTEST=... RUNTESTFLAGS="riscv.exp"
# of expected passes? ? ? ? ? ? 350

For the RISC-V tests I had to update the expected fake label spelling in
la-variants.d from ".L0 " to".L0?".

I would not revive the old patch exactly as-is, though. New objdump should
also hide old-style ".L0 " fake labels for old gas / new objdump
compatibility; otherwise objdump -dr can show labels such as:

0000000000000004 <.L0 >:

The reverse direction, new gas with old objdump, still exposes ".L0?", but I
do not think that can be fixed from the new sources.

One more thing I noticed is that even with patched gas and patched objdump,
objdump -dr can still print fake labels in relocation annotations, for 
example:

R_RISCV_PCREL_LO12_I .L0?

This path seems to bypass riscv_symbol_is_valid(). I think this should be
discussed as a separate objdump issue rather than hidden inside the
FAKE_LABEL_CHAR change, especially since these fake labels also help 
show the
PCREL HI/LO pairing.

Regarding the other points you raised, I agree that 
make_internal_label() using
the same FAKE_LABEL_NAME for all instances is not ideal. It makes relocation
output harder to associate with the specific generated label. But I think
renaming those internal labels to follow the fb_label_name() / 
dollar_label_name()
style is a separate cleanup from changing the fake-label character.

For LOCAL_LABEL_CHAR / DOLLAR_LABEL_CHAR handling in read_symbol_name() /
get_symbol_name(), I do not have a concrete failing case yet, so I would 
prefer
not to mix that into this change.

I also tested quoted symbols containing '?'. Quoted user symbols such as
"user?symbol" remained visible, and unquoted "user?symbol:" was still
rejected. Symbols like ".Luser?" are still subject to the existing generic
.L local-symbol filtering, but I did not see a new broad false-hiding or
symbol-lexing regression caused by using '?' as FAKE_LABEL_CHAR.

So my recommendation is:

  *

    use '?' rather than space for the RISC-V fake label character;

  *

    keep the gas/app.c lex[] handling from the RFC;

  *

    keep the gas/write.h constraint clarification;

  *

    add a stronger symbolic altmacro testcase, such as "%s2-s1 17";

  *

    add compatibility in the RISC-V objdump symbol-valid hook so new objdump
    hides both ".L0?" and old ".L0 ";

  *

    leave relocation annotation cleanup, make_internal_label() naming, and
    broader LOCAL_LABEL_CHAR / DOLLAR_LABEL_CHAR handling as separate
    follow-ups.

Please let me know if I misunderstood any part of the original issue or the
intended fake-label handling.

Best regards,
Jiawei
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From jeffrey.law@oss.qualcomm.com  Mon Jun 22 14:06:40 2026
From: jeffrey.law@oss.qualcomm.com (Jeffrey Law)
Date: Mon, 22 Jun 2026 08:06:40 -0600
Subject: [PATCH v6 1/2] RISC-V: Add SpacemiT vendor extension xsmtvdot
In-Reply-To: <20260615094528.2016824-1-zhuangqiubin@linux.spacemit.com>
References: <0ca5423e-3712-4f84-abaf-fb24586d6b4b@suse.com>
 <20260615094528.2016824-1-zhuangqiubin@linux.spacemit.com>
Message-ID: <d66fab74-12fb-4625-9fd1-b6c96f369e30@oss.qualcomm.com>



On 6/15/2026 3:45 AM, Mark Zhuang wrote:
> Hi Jan,
>
> Thanks for the clarification -- much appreciated.
>
> Just to be clear, I know you're not a RISC-V maintainer. I only reached out
> because the RISC-V maintainers have been less active lately, and I
> sincerely didn't mean to add to your workload.
>
> I fully agree this should go through them, and will wait for their
> availability to handle the patch.
Yea.? I was just looking and it appears that at least some RISC-V 
patches that have been approved haven't been integrated.? I'll try to 
burn through that set of patches, then we can evaluate what's still 
left.? But clearly things aren't working as smoothly as they should.

jeff

From alice.carlotti@arm.com  Mon Jun 22 14:06:01 2026
From: alice.carlotti@arm.com (Alice Carlotti)
Date: Mon, 22 Jun 2026 15:06:01 +0100
Subject: [PATCH v9 1/1] aarch64: Implement Structured Exception Handling
 (SEH) on AArch64
In-Reply-To: <20260617083947.8097-2-evgeny.karpov@arm.com>
References: <20260617083947.8097-1-evgeny.karpov@arm.com>
 <20260617083947.8097-2-evgeny.karpov@arm.com>
Message-ID: <cbb7cc0b-817d-38ad-51a0-43003c0524f3@e124511.cambridge.arm.com>

On Wed, Jun 17, 2026 at 10:39:47AM +0200, Evgeny Karpov wrote:
> The patch reuses shared helpers for SEH and implements SEH on AArch64.
> The implementation is based on
> (https://learn.microsoft.com/en-us/cpp/build/arm64-exception-handling?view=msvc-170)
> and pdata/xdata SEH records are emitted from md_finish.
> 
> When .pdata/.xdata is emitted, the function size is required.
> Function sizes are calculated as late as possible, and the code segment needs
> to be relaxed to be able to calculate the function sizes.
> 
> Initially, obj_coff_generate_pdata was called in write_object_file.
> Before the change, obj_coff_generate_pdata was used only to validate
> syntax, which was sufficient for that purpose. However, that location
> seems incorrect, as it is too late to emit .pdata/.xdata records
> in the AArch64 case.
> 
> md_finish has been declared for AArch64 and extended with
> seh_aarch64_write_data to emit .pdata/.xdata records after all
> assembly has been completed.
> 
> Signed-off-by: Evgeny Karpov <evgeny@kmaps.co>
> 

This looks better.  However, there are some points from my previous review that
still need fixing (or I need a clearer explanation of why they're actually not
wrong).  I've copied the previous comments to this thread:


On Thu, Jun 11, 2026 at 12:53:52PM +0200, Evgeny Karpov wrote:
> On Thu, 16 Apr 2026, Alice Carlotti wrote:
> > > +  addressT start_offset, end_offset;
> > > +  start_frag = symbol_get_frag_and_value (seh_ctx->start_addr, &start_offset);
> > > +  end_frag = symbol_get_frag_and_value (seh_ctx->end_addr, &end_offset);
> > > +
> > > +  intptr_t func_size = end_frag->fr_address + end_offset
> > > +		       - start_frag->fr_address - start_offset;
> > > +  if (func_size < 0)
> > 
> > Does this always hold when the function size "has not been evaluated"?
> 
> Yes, it makes sense to stop compilation when function size cannot be properly calculated.
> It means the assembler has an internal issue and should be fixed.

I think you missed my point - I'm asking whether "the function size has not
been evaluated" only happens when func_size < 0, or can it happen with
func_size >= 0 as well?

...
> > You're missing handling for too many epilogs or too many code words.
> 
> Unwind capacity is handled in seh_aarch64_add_unwind_element,
> and epilogue capacity is handled in obj_coff_seh_startepilogue,
> by AARCH64_MAX_UNWIND_CODES_SIZE and AARCH64_MAX_EPILOGUE_SCOPES.

I see - we currently apply the per-fragment limits on number of unwind codes
and epilogue scopes to the entire function, so we don't need to check those
limits when we later split the function into fragments.  But the downside is
that we bail out in some cases where we could have used fragments instead.

I'm ok with this limitation remaining in the current patch for now, as long as
it is explicitly called out in both:
- any lists of currently unsupported functionality, and
- a comment in this function explaining why we don't currently consider those
  limits during fragmentation (the comment above the "while (true)" would be a
  good place to mention this).

...
> > > +
> > > +/* SEH COFF AArch64 implementation partially intersects with the x64
> > > +   version, however it has a different extension to the unwind codes.
> > > +   It emits SEH data to pdata and xdata sections.  In some cases SEH
> > > +   data could be emitted to a packed record in the pdata section
> > > +   without the need for data in the xdata section.  However, the packed
> > > +   pdata record is not implemented yet.  */
> > 
> > Can we have a separate list of things that aren't yet supported (at least as a
> > separate paragraph).  As well as packed unwind data, I think this includes:
> > - Support for SVE/SME (at least, I think that's what the unimplemented unwind
> >   codes are used for);
> > - Reuse of identical unwind code sequences.
> 
> Ok, it makes sense.
> "Reuse of identical unwind code sequences" is not applicable for 
> aarch64-w64-mingw32.

Really?  I see no reason why it wouldn't be applicable, and the documentation
itself implicitly mentions reusing unwind codes:

    These assumptions are made in the exception handling description:

    - Prologs and epilogs tend to mirror each other. By taking advantage of
      this common trait, the size of the metadata needed to describe unwinding
      can be greatly reduced. Within the body of the function, it doesn't
      matter whether the prolog's operations are undone, or the epilog's
      operations are done in a forward manner. Both should produce identical
      results.

(https://learn.microsoft.com/en-us/cpp/build/arm64-exception-handling?view=msvc-170#assumptions)

> The description will be extended with text below.
> 
> /* The current implementation does not include:
>    - Packed pdata record.
>    - Support for AdvSIMD and SVE.
>    - Handling for pacibsp.  */
> 

...
> > > +
> > > +  subsegT subsection;
> > > +
> > > +  union {
> > > +    seh_aarch64_xdata_header xdata_header;
> > > +    valueT xdata_header_value;
> > > +  };
> > 
> > I think this type punning is incorrect for a big endian host, and there might
> > be other portability issues beyond this.  Type punning to a struct of two
> > uint32_t values is more likely to work, but that's still not guaranteed by the
> > C standard to be correct, so it might be best just to build uint32_t values
> > from the individual bitfields piece by piece.
> 
> The big endian host should be supported properly by md_number_to_chars that is used
> for emitting pdata/xdata records.

That only ensures that the conversion from valueT to bytes-on-disk is handled
correctly.  The issue is with the bit-field to valueT conversion - on a
big-endian host I think this would pack the bitfields in the wrong order. 

> Regards,
> Evgeny
> 







(On Wed, Jun 17, 2026 at 10:39:47AM +0200, Evgeny Karpov wrote:)
...
> +struct aarch64_unwind_info {
> +  const char *directive;
> +  char reg_type;
> +  unsigned char offset_bits;
> +  unsigned char reg_bits;
> +  unsigned char reg_max;
> +  unsigned char code_bits;
> +  unsigned char code;
> +  unsigned char offset_shift;
> +  unsigned char offset_addend;
> +  unsigned char reg_shift;
> +  unsigned char reg_addend;
> +  unsigned char size;
> +};
Could you reorder the fields in the struct definition as well, to match the
improved instantiation order?

...
> +/* Obtain available unwind element.  */
> +static void
> +seh_aarch64_add_unwind_element (const seh_aarch64_unwind_types unwind_type,
> +				unsigned offset, unsigned reg)
> +{
> +  const struct aarch64_unwind_info *info
> +    = aarch64_unwind_code_data + unwind_type;
> +  unsigned value_offset_bits = 0;
> +
> +  if ((seh_ctx_cur->unwind_codes_byte_count
> +      + info->size) > AARCH64_MAX_UNWIND_CODES_SIZE)
> +    as_bad (_("no unwind element available."));
> +
> +  unsigned value = 0;
> +
> +  if (info->offset_bits)
> +    {
> +      const unsigned divided_by = 1u << info->offset_shift;
offset_multiplier would be a better name

> +      if (offset & (divided_by - 1))
> +	as_bad (_("offset should be divided by %u"), divided_by);
"offset should be a multiple of %u"

> +      offset = (offset >> info->offset_shift) - info->offset_addend;
> +      if (offset >= (1u << info->offset_bits))
> +	as_bad (_("offset overflows expected range"));
> +      value |= offset << value_offset_bits;
> +      value_offset_bits += info->offset_bits;
> +    }
> +
> +  if (info->reg_bits)
> +    {
> +      const unsigned regn_divided_by = 1u << info->reg_shift;
similiarly reg_multiplier

> +      reg -= info->reg_addend;
> +      if (reg & (regn_divided_by - 1))
> +	as_bad (_("unexpected register number"));
> +      reg >>= info->reg_shift;
> +      if (reg >= (1u << info->reg_bits))
> +	as_bad (_("unexpected register number"));
> +      value |= reg << value_offset_bits;
> +      value_offset_bits += info->reg_bits;
> +    }


...
> +  if (info->reg_bits)
> +    {
> +      char name_end = get_symbol_name (&symbol_name);
> +      if (info->reg_type != *symbol_name)
> +	as_bad ("unexpected register name");
> +
> +      reg = atoi (symbol_name + 1);
> +      (void) restore_line_pointer (name_end);
> +
> +      if (!skip_whitespace_and_comma (1))
> +	return;
> +
> +      const unsigned reg_max = info->reg_max ? info->reg_max: 30;
> +      if (reg > reg_max)
> +	as_bad (_("unexpected register number"));
> +    }
This feels awkward, because the maximum isn't actually 30 in some cases.  I
think it would be clearer to have a reg_pair field (instead of the reg_max)
field, and replace this check with:


+      /* Most range checks are applied during encoding.  Check here that we
+	 don't reference registers higher than x30.  */
+      if (info->reg_type == 'x'
+	  && reg + (info->reg_pair ? 1 : 0) > 30)
+	as_bad (_("unexpected register number"));

Although now I look at it some more, I think we should put all of the range
checking in the same place (checking it during parsing might give better error
locations, but I haven't verified this).

...
> +/* Write out the xdata information for one function.  */
> +static void
> +seh_aarch64_write_function_xdata (struct seh_aarch64_context *seh_ctx)
> +{
> +  if (!seh_ctx->unwind_codes_byte_count)
> +    return;
> +
> +  const segT save_seg = now_seg;
> +  const subsegT save_subseg = now_subseg;
> +
> +  switch_xdata (seh_ctx->subsection, seh_ctx->code_seg);
> +
> +  /* Set 4-byte alignment.  */
> +  frag_align (2, 0, 0);
> +
> +  uintptr_t func_size = 0;
> +  if (!seh_function_size (seh_ctx, &func_size))
> +    {
> +      as_bad (_("the function size for %s has not been evaluated"),
> +	      seh_ctx->func_name);
> +      return;
> +    }
> +
> +  /* The large functions should be split into fragments smaller than 1MB with
> +     4 bytes alignment, based on
> +     "Microsoft ARM64 exception handling, large functions documentation".  */
> +  const unsigned max_frag_size = (1 << 20) - 4;
> +  const bool is_fragmented_function = func_size > max_frag_size;
> +
> +  unsigned prologue_insn_count = 0;
> +  for (unsigned i = 0; i < seh_ctx->unwind_codes_count; ++i)
> +    {
> +      if (seh_ctx->unwind_codes[i].type == unwind_end)
> +	{
> +	  prologue_insn_count = i + 1;
> +	  break;
> +	}
> +    }
> +
> +  unsigned prologue_size = seh_ctx->unwind_codes_byte_count;
> +
> +  seh_aarch64_func_fragment *fragment;
> +  fragment = &seh_ctx->func_fragment;
> +  uintptr_t fragment_offset = 0;
> +  unsigned first_fragment_scope = 0;
> +  unsigned last_fragment_scope = 0;
> +
> +  /* Large functions (>= 1MB) will be split into multiple fragments.
> +     However, it is expected the most of the functions will have only one
> +     fragment. This loop iterates fragments and emit them.  */
> +  while (true)
> +    {
> +      fragment->xdata_addr = symbol_temp_new_now ();
> +      fragment->offset = fragment_offset;
> +      fragment->next = NULL;
> +
> +      /* Calculate current fragment size.  */
> +      uintptr_t frag_size = func_size - fragment_offset;
> +      if (frag_size > max_frag_size)
> +	frag_size = max_frag_size;
> +
> +      const bool is_last_frag = (fragment_offset + frag_size) == func_size;
> +
> +      /* If it is a fragmented function, the epilogue range should be calculated
> +	 and will be emitted for the current fragment, otherwise all epilogues
> +	 will be emitted.  */
> +      if (!is_fragmented_function)
> +	last_fragment_scope = seh_ctx->epilogue_scopes_count;
> +      else
> +	{
> +	  first_fragment_scope = last_fragment_scope;
> +	  for (unsigned i = first_fragment_scope;
> +	       i < seh_ctx->epilogue_scopes_count; ++i)
> +	    {
> +	      const seh_aarch64_epilogue_scope *scope
> +		= seh_ctx->epilogue_scopes;
> +	      scope += i;
> +	      if (scope->epilogue_start_offset >= (fragment_offset + frag_size))
> +		break;
> +
> +	      if (scope->epilogue_end_offset >= (fragment_offset + frag_size))
> +		{
> +		  frag_size = scope->epilogue_start_offset - fragment_offset;
> +		  break;
> +		}
> +
> +	      if (scope->epilogue_start_offset >= fragment_offset)
> +		last_fragment_scope = i + 1;
> +	    }
> +	}
> +
> +      seh_aarch64_xdata_header *header = &seh_ctx->xdata_header;
> +      const seh_aarch64_epilogue_scope *scopes = seh_ctx->epilogue_scopes;
> +
> +      /* Initialize the .xdata record.  */
> +      const uint32_t func_length_encoded = frag_size >> 2;
> +      header->func_length = func_length_encoded;
> +      header->vers = 0;
> +      header->e = 0;
> +      header->code_words = 0;
> +      header->epilogue_count = 0;
> +
> +      header->ext_code_words = 0;
> +      header->ext_epilogue_count = last_fragment_scope
> +				   - first_fragment_scope;
> +      header->reserved = 0;
> +
> +      /* Calculate epilogue indexes for the current fragment.  */
> +      unsigned first_epilogue_index = 0;
> +      unsigned last_epilogue_index = 0;
> +      if (!header->ext_epilogue_count)
> +	{
> +	  first_epilogue_index = prologue_size;
> +	  last_epilogue_index = prologue_size;
> +	}
> +      else
> +	{
> +	  const seh_aarch64_epilogue_scope *scope;
> +	  scope = scopes + first_fragment_scope;
> +	  first_epilogue_index = scope->epilogue_start_index;
> +	  last_epilogue_index = seh_ctx->unwind_codes_byte_count;
> +	}
> +
> +      /* Calculate how many unwind bytes will be emitted in .xdata record.  */
> +      unsigned unwind_bytes = prologue_size;
> +
> +      /* Check if current fragment has a phantom prologue. If yes, then
> +	 the unwinding size should be adjusted.  */
> +      const bool has_phantom_prologue = is_fragmented_function && is_last_frag;
> +      if (has_phantom_prologue && unwind_bytes)
> +	{
> +	  /* One more epilogue scope and unwind code are emitted with phantom
> +	     prologue.  */
> +	  unwind_bytes += 1;
> +	  ++header->ext_epilogue_count;
> +	}
> +
> +      /* Calculate the number of code words with 4-byte alignment.  */
> +      header->ext_code_words = (unwind_bytes + 3) / 4;
> +
> +      /* Check if short or extended header for a .xdata record should be
> +	 used.  */
> +      unsigned header_size = 8;
> +      if ((header->ext_code_words != 0 || header->ext_epilogue_count != 0)
> +	  && header->ext_code_words < 32
> +	  && header->ext_epilogue_count < 32)
> +	{
> +	  header_size = 4;
> +	  header->code_words = header->ext_code_words;
> +	  header->epilogue_count = header->ext_epilogue_count;
> +	  if (header->epilogue_count == 1)
> +	    {
> +	      header->e = 1;
> +	      if (has_phantom_prologue)
> +		header->ext_epilogue_count = 0;
> +	      else
> +		{
> +		  const seh_aarch64_epilogue_scope *scope;
> +		  scope = scopes + first_fragment_scope;
> +		  header->ext_epilogue_count = scope->epilogue_start_index;
> +		}
> +	    }
> +	}
> +
> +      /* Emit a .xdata record for the current fragment.  */
> +      seh_aarch64_emit_xdata_record(seh_ctx, frag_size, fragment_offset,
> +				    header_size,
> +				    prologue_size, prologue_insn_count,
> +				    has_phantom_prologue,
> +				    first_fragment_scope, last_fragment_scope,
> +				    first_epilogue_index, last_epilogue_index);
> +
> +      fragment_offset += frag_size;
> +      /* Exit the loop if it is the latest fragment.  */
> +      if (is_last_frag)
> +	break;
> +
> +      /* Allocate a new fragment that will be used also for emitting a .pdata
> +	 record.  */
> +      fragment->next = XCNEW (seh_aarch64_func_fragment);
> +      fragment = fragment->next;
> +    }
> +
> +  subseg_set (save_seg, save_subseg);
> +}
> +
...
> diff --git a/gas/testsuite/gas/pe/seh-aarch64.d b/gas/testsuite/gas/pe/seh-aarch64.d
> new file mode 100644
> index 00000000000..218366ab6b0
> --- /dev/null
> +++ b/gas/testsuite/gas/pe/seh-aarch64.d
> @@ -0,0 +1,66 @@
> +#objdump: -s -j .xdata
> +#name: PEP aarch64 SEH
> +
> +.*:     file format pe-aarch64-little
> +
> +Contents of section .xdata:
> +
> +# .xdata SEH record
> +# 0x98700000  code-words: 19
> +#             epilogue-count: 1
> +#             single-epilogue-in-header: 1
> +#             exception-data: 1
> +#             version: 0
> +#             function-size: 0
> +# 0xe6        .seh_save_next
> +# 0xe1        .seh_save_fp
> +# 0xfc        .seh_pac_sign_lr
> +# 0xe3        .seh_nop
> +# 0xe218      .seh_add_fp 192
> +# 0x36        .seh_save_r19r20_x 176
> +# 0x93        .seh_save_fplr_x 160
> +# 0x52        .seh_save_fplr 144
> +# 0xdeef      .seh_save_freg_x d15, 128
> +# 0xde2f      .seh_save_freg_x d9, 128
> +# 0xde0f      .seh_save_freg_x d8, 128
> +# 0xddce      .seh_save_freg d15, 112
> +# 0xdc4e      .seh_save_freg d9, 112
> +# 0xdc0e      .seh_save_freg d8, 112
> +# 0xdbcb      .seh_save_fregp_x d15, 96
> +# 0xda4b      .seh_save_fregp_x d9, 96
> +# 0xda0b      .seh_save_fregp_x d8, 96
> +# 0xd9ca      .seh_save_fregp d15, 80
> +# 0xd84a      .seh_save_fregp d9, 80
> +# 0xd80a      .seh_save_fregp d8, 80
> +# 0xd748      .seh_save_lrpair x29, 64
> +# 0xd648      .seh_save_lrpair x21, 64
> +# 0xd608      .seh_save_lrpair x19, 64
> +# 0xce85      .seh_save_regp_x x29, 48
> +# 0xcc45      .seh_save_regp_x x20, 48
> +# 0xcc05      .seh_save_regp_x x19, 48
> +# 0xca84      .seh_save_regp x29, 32
> +# 0xc844      .seh_save_regp x20, 32
> +# 0xc804      .seh_save_regp x19, 32
> +# 0xd561      .seh_save_reg_x x30, 16
> +# 0xd421      .seh_save_reg_x x20, 16
> +# 0xd401      .seh_save_reg_x x19, 16
> +# 0xd2c0      .seh_save_reg x30, 0
> +# 0xd040      .seh_save_reg x20, 0
> +# 0xd000      .seh_save_reg x19, 0
> +# 0xe0ffffff  .seh_stackalloc 268435440
> +# 0xe0000800  .seh_stackalloc 32768
> +# 0xc020      .seh_stackalloc 512
> +# 0x01        .seh_stackalloc 16
> +# 0xe4        nop
> +# 0xe4        nop
> +# 0x00000000  seh-handler
> +# 0x00000000  fragment-offset
> +# 0x0000005c  seh-handle-data-address
> +# 0x00000001  long 1 (seh_handlerdata)
> +
> + 0000 00007098 e6e1fce3 e2183693 52deefde  .*
> + 0010 2fde0fdd cedc4edc 0edbcbda 4bda0bd9  .*
> + 0020 cad84ad8 0ad748d6 48d608ce 85cc45cc  .*
> + 0030 05ca84c8 44c804d5 61d421d4 01d2c0d0  .*
> + 0040 40d000e0 ffffffe0 000800c0 2001e4e4  .*
> + 0050 00000000 00000000 5c000000 01000000  .*
> \ No newline at end of file
> diff --git a/gas/testsuite/gas/pe/seh-aarch64.s b/gas/testsuite/gas/pe/seh-aarch64.s
> new file mode 100644
> index 00000000000..5868a7f57dc
> --- /dev/null
> +++ b/gas/testsuite/gas/pe/seh-aarch64.s
> @@ -0,0 +1,49 @@
> +	.text
> +	.seh_proc	foo
> +	.seh_stackalloc 16
> +	.seh_stackalloc 512
> +	.seh_stackalloc 32768
> +	.seh_stackalloc 268435440
> +	.seh_save_reg x19, 0
> +	.seh_save_reg x20, 0
> +	.seh_save_reg x30, 0
> +	.seh_save_reg_x x19, 16
> +	.seh_save_reg_x x20, 16
> +	.seh_save_reg_x x30, 16
> +	.seh_save_regp x19, 32
> +	.seh_save_regp x20, 32
> +	.seh_save_regp x29, 32
> +	.seh_save_regp_x x19, 48
> +	.seh_save_regp_x x20, 48
> +	.seh_save_regp_x x29, 48
> +	.seh_save_lrpair x19, 64
> +	.seh_save_lrpair x21, 64
> +	.seh_save_lrpair x29, 64
> +	.seh_save_fregp d8, 80
> +	.seh_save_fregp d9, 80
> +	.seh_save_fregp d15, 80
> +	.seh_save_fregp_x d8, 96
> +	.seh_save_fregp_x d9, 96
> +	.seh_save_fregp_x d15, 96
> +	.seh_save_freg d8, 112
> +	.seh_save_freg d9, 112
> +	.seh_save_freg d15, 112
> +	.seh_save_freg_x d8, 128
> +	.seh_save_freg_x d9, 128
> +	.seh_save_freg_x d15, 128
> +	.seh_save_fplr 144
> +	.seh_save_fplr_x 160
> +	.seh_save_r19r20_x 176
> +	.seh_add_fp 192
> +	.seh_nop
> +	.seh_pac_sign_lr
> +	.seh_set_fp
> +	.seh_save_next
> +	.seh_endprologue
> +	.seh_handler _ZN9exception6handleEPvS0_S0_S0_, @except
> +	.seh_handlerdata
> +	.long 1
> +	.seh_code
> +	.seh_startepilogue
> +	.seh_endepilogue
> +	.seh_endproc

Shouldn't seh directives be interleaved with the matching assembly
instructions?  We don't check the offsets of individual seh unwind codes, but
this test file looks like it would have a prologue that overlaps the epilogue
and extends beyond the end of the function (which is something that we should
probably check for).


Additionally, why is there a mismatch between .seh_set_fp near the end of the
prologue in the .s file, and .seh_save_fp near the start of the reversed
prologue in the .d file?


Thanks,
Alice

From jeffrey.law@oss.qualcomm.com  Mon Jun 22 14:22:19 2026
From: jeffrey.law@oss.qualcomm.com (Jeffrey Law)
Date: Mon, 22 Jun 2026 08:22:19 -0600
Subject: [PATCH] RISC-V: Support Zalasr extension.
In-Reply-To: <20260121162309.3466952-1-jiawei@iscas.ac.cn>
References: <20260121162309.3466952-1-jiawei@iscas.ac.cn>
Message-ID: <f713bf2b-25b0-44a2-b129-b4f656cba5df@oss.qualcomm.com>



On 1/21/2026 9:23 AM, Jiawei wrote:
> This patch supports Zalasr extension(load-acquire/store-release) instructions.
>
> https://github.com/riscv/riscv-zalasr
>
> bfd/ChangeLog:
>
>          * elfxx-riscv.c (riscv_multi_subset_supports): New ext.
>          (riscv_multi_subset_supports_ext): Ditto.
>
> gas/ChangeLog:
>
>          * NEWS: Support Zalasr extension.
>          * testsuite/gas/riscv/march-help.l: New ext.
>          * testsuite/gas/riscv/zalasr.d: New test.
>          * testsuite/gas/riscv/zalasr.s: New test.
>
> include/ChangeLog:
>
>          * opcode/riscv-opc.h (MATCH_LBA): New match opcode.
>          (MASK_LBA): New mask opcode.
>          (MATCH_LHA): New match opcode.
>          (MASK_LHA): New mask opcode.
>          (MATCH_LWA): New match opcode.
>          (MASK_LWA): New mask opcode.
>          (MATCH_LDA): New match opcode.
>          (MASK_LDA): New mask opcode.
>          (MATCH_SBR): New match opcode.
>          (MASK_SBR): New mask opcode.
>          (MATCH_SHR): New match opcode.
>          (MASK_SHR): New mask opcode.
>          (MATCH_SWR): New match opcode.
>          (MASK_SWR): New mask opcode.
>          (MATCH_SDR): New match opcode.
>          (MASK_SDR): New mask opcode.
>          (DECLARE_INSN): New insn declare.
>          * opcode/riscv.h (enum riscv_insn_class): New ext.
>
> opcodes/ChangeLog:
>
>          * riscv-opc.c: New instructions def.
It doesn't look like this ever got pushed to the trunk.? I've taken care 
of that.

Jeff

From alice.carlotti@arm.com  Mon Jun 22 14:50:01 2026
From: alice.carlotti@arm.com (Alice Carlotti)
Date: Mon, 22 Jun 2026 15:50:01 +0100
Subject: [PATCH v9 1/1] aarch64: Implement Structured Exception Handling
 (SEH) on AArch64
In-Reply-To: <20260617083947.8097-2-evgeny.karpov@arm.com>
References: <20260617083947.8097-1-evgeny.karpov@arm.com>
 <20260617083947.8097-2-evgeny.karpov@arm.com>
Message-ID: <5abc847a-7a83-3ffb-cedd-e439e3043334@e124511.cambridge.arm.com>

On Wed, Jun 17, 2026 at 10:39:47AM +0200, Evgeny Karpov wrote:
...
> +/* Write out the xdata information for one function.  */
> +static void
> +seh_aarch64_write_function_xdata (struct seh_aarch64_context *seh_ctx)

Oops, I forgot to write my comments on this functions.

In general, I think this function ought handle function fragmention, but the
encoding details (including choosing between compact or extended header fields)
should be handled in seh_aarch64_emit_xdata_record.  This separation of
concerns should help with readability.

I think there are also several corner cases that are mishandled in this code,
but I've been struggling to work out what's going on well enough to say that
particular pieces are right or wrong.  I'll try to point any specific issues I
see, but I'd appreciate if you could also see whether you can do anything more
to improve the structure of this code.

> +{
> +  if (!seh_ctx->unwind_codes_byte_count)
> +    return;
> +
> +  const segT save_seg = now_seg;
> +  const subsegT save_subseg = now_subseg;
> +
> +  switch_xdata (seh_ctx->subsection, seh_ctx->code_seg);
> +
> +  /* Set 4-byte alignment.  */
> +  frag_align (2, 0, 0);
> +
> +  uintptr_t func_size = 0;
> +  if (!seh_function_size (seh_ctx, &func_size))
> +    {
> +      as_bad (_("the function size for %s has not been evaluated"),
> +	      seh_ctx->func_name);
> +      return;
> +    }
> +
> +  /* The large functions should be split into fragments smaller than 1MB with
> +     4 bytes alignment, based on
> +     "Microsoft ARM64 exception handling, large functions documentation".  */
> +  const unsigned max_frag_size = (1 << 20) - 4;
> +  const bool is_fragmented_function = func_size > max_frag_size;
> +
> +  unsigned prologue_insn_count = 0;
> +  for (unsigned i = 0; i < seh_ctx->unwind_codes_count; ++i)
> +    {
> +      if (seh_ctx->unwind_codes[i].type == unwind_end)
> +	{
> +	  prologue_insn_count = i + 1;
> +	  break;
> +	}
> +    }
> +
> +  unsigned prologue_size = seh_ctx->unwind_codes_byte_count;
> +
> +  seh_aarch64_func_fragment *fragment;
> +  fragment = &seh_ctx->func_fragment;
> +  uintptr_t fragment_offset = 0;
> +  unsigned first_fragment_scope = 0;
> +  unsigned last_fragment_scope = 0;
> +
> +  /* Large functions (>= 1MB) will be split into multiple fragments.
> +     However, it is expected the most of the functions will have only one
> +     fragment. This loop iterates fragments and emit them.  */

See previous review comments about how this implementation doesn't currently
support (or need to handle) fragmenting due to too many unwind codes or too
many epilogue scopes.


> +  while (true)
> +    {
> +      fragment->xdata_addr = symbol_temp_new_now ();
> +      fragment->offset = fragment_offset;
> +      fragment->next = NULL;
> +
> +      /* Calculate current fragment size.  */
> +      uintptr_t frag_size = func_size - fragment_offset;
> +      if (frag_size > max_frag_size)
> +	frag_size = max_frag_size;
> +
> +      const bool is_last_frag = (fragment_offset + frag_size) == func_size;
> +
> +      /* If it is a fragmented function, the epilogue range should be calculated
> +	 and will be emitted for the current fragment, otherwise all epilogues
> +	 will be emitted.  */
> +      if (!is_fragmented_function)
> +	last_fragment_scope = seh_ctx->epilogue_scopes_count;
> +      else
> +	{
> +	  first_fragment_scope = last_fragment_scope;
> +	  for (unsigned i = first_fragment_scope;
> +	       i < seh_ctx->epilogue_scopes_count; ++i)
> +	    {
> +	      const seh_aarch64_epilogue_scope *scope
> +		= seh_ctx->epilogue_scopes;
> +	      scope += i;
> +	      if (scope->epilogue_start_offset >= (fragment_offset + frag_size))
> +		break;
> +
> +	      if (scope->epilogue_end_offset >= (fragment_offset + frag_size))
> +		{
> +		  frag_size = scope->epilogue_start_offset - fragment_offset;
> +		  break;
> +		}
> +
> +	      if (scope->epilogue_start_offset >= fragment_offset)
> +		last_fragment_scope = i + 1;
> +	    }
> +	}
> +
> +      seh_aarch64_xdata_header *header = &seh_ctx->xdata_header;
> +      const seh_aarch64_epilogue_scope *scopes = seh_ctx->epilogue_scopes;
> +
> +      /* Initialize the .xdata record.  */
> +      const uint32_t func_length_encoded = frag_size >> 2;
> +      header->func_length = func_length_encoded;
> +      header->vers = 0;
> +      header->e = 0;
> +      header->code_words = 0;
> +      header->epilogue_count = 0;
> +
> +      header->ext_code_words = 0;
> +      header->ext_epilogue_count = last_fragment_scope
> +				   - first_fragment_scope;

It would be clearer to use separate variables here, and only combine them into
a single header value within seh_aarch64_emit_xdata_record.   We can't do the
type-punning anyway, so there's no benefit to putting the values into a struct.
This also avoids any ambiguity about whether the short or extended fields
should be used for computations in this function.

> +      header->reserved = 0;
> +
> +      /* Calculate epilogue indexes for the current fragment.  */
> +      unsigned first_epilogue_index = 0;
> +      unsigned last_epilogue_index = 0;
> +      if (!header->ext_epilogue_count)
> +	{
> +	  first_epilogue_index = prologue_size;
> +	  last_epilogue_index = prologue_size;
> +	}
> +      else
> +	{
> +	  const seh_aarch64_epilogue_scope *scope;
> +	  scope = scopes + first_fragment_scope;
> +	  first_epilogue_index = scope->epilogue_start_index;
> +	  last_epilogue_index = seh_ctx->unwind_codes_byte_count;
> +	}
> +
> +      /* Calculate how many unwind bytes will be emitted in .xdata record.  */
> +      unsigned unwind_bytes = prologue_size;
> +
> +      /* Check if current fragment has a phantom prologue. If yes, then
> +	 the unwinding size should be adjusted.  */
> +      const bool has_phantom_prologue = is_fragmented_function && is_last_frag;
The is_last_frag part looks wrong - for a typical function layout, I'd expect
only the first fragment to have a real prologue, and the rest to have a phantom
prologue.

> +      if (has_phantom_prologue && unwind_bytes)
> +	{
> +	  /* One more epilogue scope and unwind code are emitted with phantom
> +	     prologue.  */
> +	  unwind_bytes += 1;
> +	  ++header->ext_epilogue_count;
> +	}
> +


> +      /* Calculate the number of code words with 4-byte alignment.  */
> +      header->ext_code_words = (unwind_bytes + 3) / 4;
> +
> +      /* Check if short or extended header for a .xdata record should be
> +	 used.  */
> +      unsigned header_size = 8;
> +      if ((header->ext_code_words != 0 || header->ext_epilogue_count != 0)
> +	  && header->ext_code_words < 32
> +	  && header->ext_epilogue_count < 32)
> +	{
> +	  header_size = 4;
> +	  header->code_words = header->ext_code_words;
> +	  header->epilogue_count = header->ext_epilogue_count;
> +	  if (header->epilogue_count == 1)
> +	    {
> +	      header->e = 1;
> +	      if (has_phantom_prologue)
> +		header->ext_epilogue_count = 0;
> +	      else
> +		{
> +		  const seh_aarch64_epilogue_scope *scope;
> +		  scope = scopes + first_fragment_scope;
> +		  header->ext_epilogue_count = scope->epilogue_start_index;
> +		}
> +	    }
> +	}
This code is mostly selecting between different header formats, so I think it
should be part of seh_aarch64_emit_xdata_record.

> +
> +      /* Emit a .xdata record for the current fragment.  */
> +      seh_aarch64_emit_xdata_record(seh_ctx, frag_size, fragment_offset,
> +				    header_size,
> +				    prologue_size, prologue_insn_count,
> +				    has_phantom_prologue,
> +				    first_fragment_scope, last_fragment_scope,
> +				    first_epilogue_index, last_epilogue_index);
> +
> +      fragment_offset += frag_size;
> +      /* Exit the loop if it is the latest fragment.  */
> +      if (is_last_frag)
> +	break;
> +
> +      /* Allocate a new fragment that will be used also for emitting a .pdata
> +	 record.  */
> +      fragment->next = XCNEW (seh_aarch64_func_fragment);
> +      fragment = fragment->next;
> +    }
> +
> +  subseg_set (save_seg, save_subseg);
> +}


Thanks,

Alice

From jefflaw@qti.qualcomm.com  Mon Jun 22 16:48:35 2026
From: jefflaw@qti.qualcomm.com (Jeffrey Law)
Date: Mon, 22 Jun 2026 16:48:35 +0000
Subject: [PATCH v6 1/2] RISC-V: Add SpacemiT vendor extension xsmtvdot
In-Reply-To: <20260525082008.1219171-2-zhuangqiubin@linux.spacemit.com>
References: <e066f12c-6e51-4d5f-ad2a-2955e99b5008@iscas.ac.cn>
 <20260525082008.1219171-1-zhuangqiubin@linux.spacemit.com>
 <20260525082008.1219171-2-zhuangqiubin@linux.spacemit.com>
Message-ID: <67c08e17-5721-4a68-afe0-11bb5e766605@qti.qualcomm.com>

On 5/25/2026 2:20 AM, Mark Zhuang wrote:
> From: Mark Zhuang <mark.zhuang@spacemit.com>
>
> SpacemiT defines Intrinsic Matrix Extension (IME) specification [1].
> SpacemiT X60 implements version 1.0 of the SpacemiT Vector Dot Product
> Extension (XsmtVdot v1.0) [2], a subset of the full IME specification.
>
> [1] https://github.com/spacemit-com/riscv-ime-extension-spec/releases/download/v1.0/spacemit-ime-asciidoc.pdf
> [2] https://github.com/spacemit-com/docs-ai/blob/main/en/architecture/ime_extension.md
> ---
>   bfd/elfxx-riscv.c                         |  7 ++
>   gas/NEWS                                  |  3 +
>   gas/config/tc-riscv.c                     | 81 +++++++++++++++++++++++
>   gas/doc/c-riscv.texi                      |  8 +++
>   gas/testsuite/gas/riscv/march-help.l      |  1 +
>   gas/testsuite/gas/riscv/x-smt-vdot-fail.d |  3 +
>   gas/testsuite/gas/riscv/x-smt-vdot-fail.l | 73 ++++++++++++++++++++
>   gas/testsuite/gas/riscv/x-smt-vdot-fail.s | 50 ++++++++++++++
>   gas/testsuite/gas/riscv/x-smt-vdot.d      | 41 ++++++++++++
>   gas/testsuite/gas/riscv/x-smt-vdot.s      | 33 +++++++++
>   include/opcode/riscv-opc.h                | 38 +++++++++++
>   include/opcode/riscv.h                    |  9 +++
>   opcodes/riscv-dis.c                       | 33 +++++++++
>   opcodes/riscv-opc.c                       | 23 +++++++
>   14 files changed, 403 insertions(+)
>   create mode 100644 gas/testsuite/gas/riscv/x-smt-vdot-fail.d
>   create mode 100644 gas/testsuite/gas/riscv/x-smt-vdot-fail.l
>   create mode 100644 gas/testsuite/gas/riscv/x-smt-vdot-fail.s
>   create mode 100644 gas/testsuite/gas/riscv/x-smt-vdot.d
>   create mode 100644 gas/testsuite/gas/riscv/x-smt-vdot.s
THanks.? I've pushed this to the trunk.

jeff

From jeffrey.law@oss.qualcomm.com  Mon Jun 22 16:57:26 2026
From: jeffrey.law@oss.qualcomm.com (Jeffrey Law)
Date: Mon, 22 Jun 2026 10:57:26 -0600
Subject: [PATCH v6 2/2] RISC-V: Add SpacemiT vendor extension xsmtvdotii
In-Reply-To: <20260525082008.1219171-3-zhuangqiubin@linux.spacemit.com>
References: <e066f12c-6e51-4d5f-ad2a-2955e99b5008@iscas.ac.cn>
 <20260525082008.1219171-1-zhuangqiubin@linux.spacemit.com>
 <20260525082008.1219171-3-zhuangqiubin@linux.spacemit.com>
Message-ID: <6df893c8-affe-4a12-a0de-f205cd1e0055@oss.qualcomm.com>



On 5/25/2026 2:20 AM, Mark Zhuang wrote:
> From: Mark Zhuang <mark.zhuang@spacemit.com>
>
> SpacemiT defines Intrinsic Matrix Extension (IME) specification [1].
> SpacemiT A100 implements version 1.0 of the SpacemiT Vector Dot Product
> II Extension (XsmtVdotII v1.0) [2], a subset of the full IME specification.
>
> [1] https://github.com/spacemit-com/riscv-ime-extension-spec/releases/download/v1.0/spacemit-ime-asciidoc.pdf
> [2] https://github.com/spacemit-com/docs-ai/blob/main/en/architecture/ime_extension.md
> ---
>   bfd/elfxx-riscv.c                            |  11 ++
>   gas/NEWS                                     |   2 +-
>   gas/config/tc-riscv.c                        | 102 ++++++++++++++++
>   gas/doc/c-riscv.texi                         |   8 ++
>   gas/testsuite/gas/riscv/march-help.l         |   1 +
>   gas/testsuite/gas/riscv/x-smt-vdot-fail.l    |  64 +++++-----
>   gas/testsuite/gas/riscv/x-smt-vdot-ii-fail.d |   3 +
>   gas/testsuite/gas/riscv/x-smt-vdot-ii-fail.l |  99 ++++++++++++++++
>   gas/testsuite/gas/riscv/x-smt-vdot-ii-fail.s | 118 +++++++++++++++++++
>   gas/testsuite/gas/riscv/x-smt-vdot-ii.d      |  69 +++++++++++
>   gas/testsuite/gas/riscv/x-smt-vdot-ii.s      |  73 ++++++++++++
>   include/opcode/riscv-opc.h                   |  41 +++++++
>   include/opcode/riscv.h                       |   7 ++
>   opcodes/riscv-dis.c                          |  36 ++++++
>   opcodes/riscv-opc.c                          |  63 +++++++---
I've pushed this to the trunk as well.? Thanks!

jeff

From jeffrey.law@oss.qualcomm.com  Mon Jun 22 18:12:24 2026
From: jeffrey.law@oss.qualcomm.com (Jeffrey Law)
Date: Mon, 22 Jun 2026 12:12:24 -0600
Subject: [PATCH] RISC-V: Support Svrsw60t59b extension.
In-Reply-To: <20260203023726.15025-1-jiawei@iscas.ac.cn>
References: <20260203023726.15025-1-jiawei@iscas.ac.cn>
Message-ID: <d4b9b5ae-e6c5-4904-bb0a-413c5228568a@oss.qualcomm.com>



On 2/2/2026 7:37 PM, Jiawei wrote:
> This patch adds RISC-V Svrsw60t59b extension minimal support.
>
> https://github.com/riscv/riscv-isa-manual/blob/f30292bb486d735e186f06f705fcd7beff1e3e97/src/supervisor.adoc#L2550
>
> bfd/ChangeLog:
>
> 	* elfxx-riscv.c: New ext.
>
> gas/ChangeLog:
>
> 	* NEWS: New ext.
> 	* testsuite/gas/riscv/march-help.l: Ditto.
THanks.? I've pushed this to the trunk.
jeff

From jefflaw@qti.qualcomm.com  Mon Jun 22 18:32:46 2026
From: jefflaw@qti.qualcomm.com (Jeffrey Law)
Date: Mon, 22 Jun 2026 18:32:46 +0000
Subject: [PATCH] RISC-V: Support Svrsw60t59b extension.
In-Reply-To: <20260203023726.15025-1-jiawei@iscas.ac.cn>
References: <20260203023726.15025-1-jiawei@iscas.ac.cn>
Message-ID: <e21ae7c0-ffec-455c-a3c8-cce51e31ab43@qti.qualcomm.com>

On 2/2/2026 7:37 PM, Jiawei wrote:
> This patch adds RISC-V Svrsw60t59b extension minimal support.
>
> https://github.com/riscv/riscv-isa-manual/blob/f30292bb486d735e186f06f705fcd7beff1e3e97/src/supervisor.adoc#L2550
>
> bfd/ChangeLog:
>
> 	* elfxx-riscv.c: New ext.
>
> gas/ChangeLog:
>
> 	* NEWS: New ext.
> 	* testsuite/gas/riscv/march-help.l: Ditto.
I've pushed this to the trunk.

jeff

From jefflaw@qti.qualcomm.com  Mon Jun 22 18:33:05 2026
From: jefflaw@qti.qualcomm.com (Jeffrey Law)
Date: Mon, 22 Jun 2026 18:33:05 +0000
Subject: [PATCH] RISC-V: Support Zvabd extension instructions.
In-Reply-To: <20260528100602.475331-1-jiawei@iscas.ac.cn>
References: <20260528100602.475331-1-jiawei@iscas.ac.cn>
Message-ID: <950c6d23-1133-42aa-a1de-6ccf81becbd8@qti.qualcomm.com>

On 5/28/2026 4:06 AM, Jiawei wrote:
> This patch adds support for the Zvabd extension instructions:
> https://github.com/riscv/integer-vector-absolute-difference
>
> The Zvabd extension provides RISC-V vector integer absolute difference
> operations.
>
> The widening accumulate mnemonics follow the current frozen specification
> are vwabda.vv and vwabdau.vv.
>
> bfd/ChangeLog:
>
> 	* elfxx-riscv.c (riscv_multi_subset_supports): Add Zvabd implication
>    of zve32x.
> 	(riscv_multi_subset_supports_ext): Add Zvabd.
>
> gas/ChangeLog:
>
> 	* NEWS:
> 	* testsuite/gas/riscv/march-help.l: Add Zvabd.
> 	* testsuite/gas/riscv/zvabd.d: New test.
> 	* testsuite/gas/riscv/zvabd.s: New test.
>
> include/ChangeLog:
>
> 	* opcode/riscv-opc.h (MATCH_VABS_V): New macro.
> 	(MASK_VABS_V): Ditto.
> 	(MATCH_VABD_VV): Ditto.
> 	(MASK_VABD_VV): Ditto.
> 	(MATCH_VABDU_VV): Ditto.
> 	(MASK_VABDU_VV): Ditto.
> 	(MATCH_VWABDA_VV): Ditto.
> 	(MASK_VWABDA_VV): Ditto.
> 	(MATCH_VWABDAU_VV): Ditto.
> 	(MASK_VWABDAU_VV): Ditto.
> 	* opcode/riscv.h (enum riscv_insn_class): New extension.
>
> opcodes/ChangeLog:
>
> 	* riscv-opc.c: New instructions.
I've pushed this to the trunk.? Thanks.
jeff

From oleg.tolmatcev@gmail.com  Mon Jun 22 19:26:11 2026
From: oleg.tolmatcev@gmail.com (Oleg Tolmatcev)
Date: Mon, 22 Jun 2026 21:26:11 +0200
Subject: [PATCH] PE/COFF: auto-promote to bigobj target when section count
 overflows
In-Reply-To: <5b3cf7f1-a1a9-46fe-a0ec-2267f5a0cf22@suse.com>
References: <20260621174919.1150-3-oleg.tolmatcev@gmail.com>
 <5b3cf7f1-a1a9-46fe-a0ec-2267f5a0cf22@suse.com>
Message-ID: <CACcXsZjZf7zNWv8M9pJF6wFFE5KvdGQQoc7TUafR5FMXVM8_dA@mail.gmail.com>

Am Mo., 22. Juni 2026 um 09:46 Uhr schrieb Jan Beulich <jbeulich@suse.com>:
>
> On 21.06.2026 19:49, Oleg Tolmatcev wrote:
> > Regular PE/COFF uses 16-bit section numbers in the symbol table,
> > limiting objects to at most 65535 sections.  When this limit is
> > exceeded, the assembler silently truncates section numbers, producing
> > corrupt objects that cause confusing linker errors like:
> >
> >   undefined reference to `vtable for ...'
> >
> > Fix this by automatically switching the xvec to the matching bigobj
> > target before any headers or symbols are finalized, so the object is
> > written out using the extended COFF format which supports 32-bit
> > section numbers.
>
> It has never really become clear to me why this wouldn't have been the
> default behavior from the very beginning. Perhaps with a way to opt out
> (rather than one to opt in).
>
> > --- a/bfd/coffcode.h
> > +++ b/bfd/coffcode.h
> > @@ -360,6 +360,10 @@ CODE_FRAGMENT
> >  #include "coffswap.h"
> >  #endif
> >
> > +#ifdef COFF_WITH_PE_BIGOBJ
> > +extern const bfd_target TARGET_SYM_BIG;
> > +#endif
> > +
> >  #define STRING_SIZE_SIZE 4
> >
> >  #define DOT_DEBUG    ".debug"
> > @@ -3154,6 +3158,16 @@ coff_compute_section_file_positions (bfd * abfd)
> >
> >    if (target_index >= bfd_coff_max_nscns (abfd))
> >      {
> > +#ifdef COFF_WITH_PE_BIGOBJ
> > +      if (abfd->xvec != &TARGET_SYM_BIG)
> > +     {
> > +       /* Regular PE/COFF uses 16-bit section numbers in symbols.
> > +          Promote oversized objects to the matching bigobj target
> > +          before any headers or symbols are finalized.  */
> > +       abfd->xvec = &TARGET_SYM_BIG;
> > +       return coff_compute_section_file_positions (abfd);
> > +     }
> > +#endif
> >        bfd_set_error (bfd_error_file_too_big);
> >        _bfd_error_handler
> >       /* xgettext:c-format */
>
> In the description you mention silent generation of a corrupt output. Yet then
> you place your addition next to the emission of an error. If this error path
> wasn't taken in the case of interest, your new addition also would take any
> effect. What am I missing?

I looked into it and discovered that the silent corruption was not caused by
upstream code. I am using MSYS2 UCRT64 and MSYS2 applies a patch
"0010-bfd-Increase-_bfd_coff_max_nscns-to-65279.patch" which raises
the maximum section number from 32768 to 65279. This disables
the check that produces the error message "too many sections" and
leads to silent miscompilation because the code still treats the section
numbers as signed integers.

I didn't know that and that's why the commit message is wrong. The
fix itself is correct though. I guess I'll need to send a v2 of the patch
with a new message.

> > --- /dev/null
> > +++ b/gas/testsuite/gas/pe/big-obj-auto.d
> > @@ -0,0 +1,9 @@
> > +#objdump: -h
> > +#name: PE big obj auto-promotion
> > +
> > +.*: *file format pe-bigobj-.*
> > +
> > +Sections:
> > +#...
> > +5000. \.data\$a49999  .*
>
> 5000. still fits in 16 bits. How is this sufficient a test for the new behavior?
> I expect you want ...

I can fix it in v2 of the patch.

> > --- /dev/null
> > +++ b/gas/testsuite/gas/pe/big-obj-auto.s
> > @@ -0,0 +1,16 @@
> > +     .file "big-obj-auto.s"
> > +
> > +     .irp n,0,1,2,3,4
>
>         .irp n,0,1,2,3,4,5,6,7
>
> here.
>
> > +     .irp m,0,1,2,3,4,5,6,7,8,9
> > +     .irp c,0,1,2,3,4,5,6,7,8,9
> > +     .irp d,0,1,2,3,4,5,6,7,8,9
> > +     .irp u,0,1,2,3,4,5,6,7,8,9
> > +     .globl a\n\m\c\d\u
> > +     .section .data$a\n\m\c\d\u,"w"
> > +a\n\m\c\d\u :
> > +     .byte 1
> > +     .endr
> > +     .endr
> > +     .endr
> > +     .endr
> > +     .endr
> > --- a/gas/testsuite/gas/pe/pe.exp
> > +++ b/gas/testsuite/gas/pe/pe.exp
> > @@ -70,4 +70,5 @@ if {[istarget "aarch64-*-pe*"] || [istarget "aarch64-*-mingw*"]} {
> >
> >  if ([istarget "*-*-mingw*"]) then {
> >       run_dump_test "big-obj"
> > +     run_dump_test "big-obj-auto"
> >  }
>
> Why would the test want limiting to MinGW?

I don't know because I didn't write that code.

> Jan

Oleg

From mark@klomp.org  Mon Jun 22 21:14:00 2026
From: mark@klomp.org (Mark Wielaard)
Date: Mon, 22 Jun 2026 23:14:00 +0200
Subject: [PATCH v6 1/2] RISC-V: Add SpacemiT vendor extension xsmtvdot
In-Reply-To: <67c08e17-5721-4a68-afe0-11bb5e766605@qti.qualcomm.com>
References: <e066f12c-6e51-4d5f-ad2a-2955e99b5008@iscas.ac.cn>
 <20260525082008.1219171-1-zhuangqiubin@linux.spacemit.com>
 <20260525082008.1219171-2-zhuangqiubin@linux.spacemit.com>
 <67c08e17-5721-4a68-afe0-11bb5e766605@qti.qualcomm.com>
Message-ID: <20260622211400.GM30116@gnu.wildebeest.org>

Hi,

On Mon, Jun 22, 2026 at 04:48:35PM +0000, Jeffrey Law via Binutils wrote:
> On 5/25/2026 2:20 AM, Mark Zhuang wrote:
> > From: Mark Zhuang <mark.zhuang@spacemit.com>
> >
> > SpacemiT defines Intrinsic Matrix Extension (IME) specification [1].
> > SpacemiT X60 implements version 1.0 of the SpacemiT Vector Dot Product
> > Extension (XsmtVdot v1.0) [2], a subset of the full IME specification.
> >
> > [1] https://github.com/spacemit-com/riscv-ime-extension-spec/releases/download/v1.0/spacemit-ime-asciidoc.pdf
> > [2] https://github.com/spacemit-com/docs-ai/blob/main/en/architecture/ime_extension.md
> > ---
> >   bfd/elfxx-riscv.c                         |  7 ++
> >   gas/NEWS                                  |  3 +
> >   gas/config/tc-riscv.c                     | 81 +++++++++++++++++++++++
> >   gas/doc/c-riscv.texi                      |  8 +++
> >   gas/testsuite/gas/riscv/march-help.l      |  1 +
> >   gas/testsuite/gas/riscv/x-smt-vdot-fail.d |  3 +
> >   gas/testsuite/gas/riscv/x-smt-vdot-fail.l | 73 ++++++++++++++++++++
> >   gas/testsuite/gas/riscv/x-smt-vdot-fail.s | 50 ++++++++++++++
> >   gas/testsuite/gas/riscv/x-smt-vdot.d      | 41 ++++++++++++
> >   gas/testsuite/gas/riscv/x-smt-vdot.s      | 33 +++++++++
> >   include/opcode/riscv-opc.h                | 38 +++++++++++
> >   include/opcode/riscv.h                    |  9 +++
> >   opcodes/riscv-dis.c                       | 33 +++++++++
> >   opcodes/riscv-opc.c                       | 23 +++++++
> >   14 files changed, 403 insertions(+)
> >   create mode 100644 gas/testsuite/gas/riscv/x-smt-vdot-fail.d
> >   create mode 100644 gas/testsuite/gas/riscv/x-smt-vdot-fail.l
> >   create mode 100644 gas/testsuite/gas/riscv/x-smt-vdot-fail.s
> >   create mode 100644 gas/testsuite/gas/riscv/x-smt-vdot.d
> >   create mode 100644 gas/testsuite/gas/riscv/x-smt-vdot.s
> THanks.? I've pushed this to the trunk.

This does break the build with older gcc versions (8.5.0):

../../binutils-gdb/opcodes/riscv-dis.c: In function ?print_insn_args?:
../../binutils-gdb/opcodes/riscv-dis.c:927:9: error: a label can only be part of a statement and a declaration is not a statement
         unsigned vd = EXTRACT_OPERAND (SPACEMIT_IME_VD, l) * 2;
         ^~~~~~~~
../../binutils-gdb/opcodes/riscv-dis.c:932:9: error: a label can only be part of a statement and a declaration is not a statement
         unsigned vs = EXTRACT_OPERAND (SPACEMIT_IME_VS1, l) * 2;
         ^~~~~~~~

It wants a block after a case label when declaring new variables.

See also
https://builder.sourceware.org/buildbot/#/builders/290/builds/6952/steps/4/logs/stdio

Cheers,

Mark

From hjl.tools@gmail.com  Tue Jun 23 01:10:53 2026
From: hjl.tools@gmail.com (H.J. Lu)
Date: Tue, 23 Jun 2026 09:10:53 +0800
Subject: [PATCH 2/3] gas/ELF: warn upon non-default visibility of local
 symbols
In-Reply-To: <b4ec2334-1821-4780-9876-f8a12d20dc4b@suse.com>
References: <bcd40b22-b90f-4334-8ab4-e8afeea2a6a9@suse.com>
 <193f86ed-f34b-4da8-9eac-68005830d369@suse.com>
 <e6007e9e-2cb7-4635-a974-5f753b212133@arm.com>
 <1397563c-32ca-4343-9587-99c197dd4029@suse.com>
 <b4ec2334-1821-4780-9876-f8a12d20dc4b@suse.com>
Message-ID: <CAMe9rOoqhA+o278P+bPWOvHSxENbjyiN=o+Goep-6MUt2--_-w@mail.gmail.com>

On Fri, May 8, 2026 at 2:54?PM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 10.04.2026 16:17, Jan Beulich wrote:
> > On 10.04.2026 15:35, Richard Earnshaw (foss) wrote:
> >> On 10/04/2026 14:31, Jan Beulich wrote:
> >>> The spec explicitly precludes STB_LOCAL together with STV_PROTECTED (and,
> >>> implicity, STV_HIDDEN or STV_INTERNAL), so we better wouldn't entirely
> >>> silently write out symbols violating this.
> >>>
> >>> LoongArch's tc_symbol_new_hook() simply needs dropping. If FAKE_LABEL_NAME
> >>> symbols can end up global, marking them hidden would need doing elsewhere.
> >>> There not being a need to make any testsuite adjustments suggests though
> >>> that this won't normally (ever?) happen.
> >>>
> >>> A couple of testcases then also need adjustment.
> >>> ---
> >>> It would be nice to re-use an existing loop, yet the one in
> >>> elf_frob_file_before_adjust() comes too early, as does elf_frob_symbol().
> >>>
> >>> An alternative may be to imply .global from .hidden etc also for defined
> >>> symbols (as looks to have been implied by some of the testcases being
> >>> adjusted). This would then require to reject .local when a visibility was
> >>> already set.
> >
> > As you can see from this, ...
> >
> >>> I wonder what purpose STV_* serve with e.g. STT_SECTION. Yet I also wonder
> >>> what purpose STB_* other than STB_LOCAL serve with STT_SECTION (seeing how
> >>> bfd/elf.c:swap_out_syms() explicitly uses STB_GLOBAL).
> >>>
> >>> The TI C6x testcase adjustments suggest that PLT relocations are
> >>> needlessly emitted by gas for non-default visibility globals.
> >>
> >>
> >> Do we know that this won't cause issues for real code out in the wild?  Might it not be better to just treat .hidden as making the symbol global, but hidden?
> >
> > ... I'm wondering the same. I meant to be conservative (as to exposing new
> > globals) for v1. If collectively we think changing the behavior that way
> > makes sense, I'll be happy to try that out for v2.
>
> Having thought about this more, implying global from hidden (etc) feels more
> risky than keeping things as they are in v1: People suddenly may face
> duplicate symbol linker errors that way. Short of any other comments /
> opinions, I'll get the series in as is.
>

This warning isn't very useful and annoying:

https://sourceware.org/bugzilla/show_bug.cgi?id=34312


--
H.J.

From jefflaw@qti.qualcomm.com  Tue Jun 23 01:59:41 2026
From: jefflaw@qti.qualcomm.com (Jeffrey Law)
Date: Tue, 23 Jun 2026 01:59:41 +0000
Subject: [PATCH v6 1/2] RISC-V: Add SpacemiT vendor extension xsmtvdot
In-Reply-To: <20260622211400.GM30116@gnu.wildebeest.org>
References: <e066f12c-6e51-4d5f-ad2a-2955e99b5008@iscas.ac.cn>
 <20260525082008.1219171-1-zhuangqiubin@linux.spacemit.com>
 <20260525082008.1219171-2-zhuangqiubin@linux.spacemit.com>
 <67c08e17-5721-4a68-afe0-11bb5e766605@qti.qualcomm.com>
 <20260622211400.GM30116@gnu.wildebeest.org>
Message-ID: <2f3139c1-cdbb-4452-b575-dc06740d9198@qti.qualcomm.com>



On 6/22/2026 3:14 PM, Mark Wielaard wrote:
> WARNING: This email originated from outside of Qualcomm. Please be wary of any links or attachments, and do not enable macros.
>
> Hi,
>
> On Mon, Jun 22, 2026 at 04:48:35PM +0000, Jeffrey Law via Binutils wrote:
>> On 5/25/2026 2:20 AM, Mark Zhuang wrote:
>>> From: Mark Zhuang <mark.zhuang@spacemit.com>
>>>
>>> SpacemiT defines Intrinsic Matrix Extension (IME) specification [1].
>>> SpacemiT X60 implements version 1.0 of the SpacemiT Vector Dot Product
>>> Extension (XsmtVdot v1.0) [2], a subset of the full IME specification.
>>>
>>> [1] https://github.com/spacemit-com/riscv-ime-extension-spec/releases/download/v1.0/spacemit-ime-asciidoc.pdf
>>> [2] https://github.com/spacemit-com/docs-ai/blob/main/en/architecture/ime_extension.md
>>> ---
>>>    bfd/elfxx-riscv.c                         |  7 ++
>>>    gas/NEWS                                  |  3 +
>>>    gas/config/tc-riscv.c                     | 81 +++++++++++++++++++++++
>>>    gas/doc/c-riscv.texi                      |  8 +++
>>>    gas/testsuite/gas/riscv/march-help.l      |  1 +
>>>    gas/testsuite/gas/riscv/x-smt-vdot-fail.d |  3 +
>>>    gas/testsuite/gas/riscv/x-smt-vdot-fail.l | 73 ++++++++++++++++++++
>>>    gas/testsuite/gas/riscv/x-smt-vdot-fail.s | 50 ++++++++++++++
>>>    gas/testsuite/gas/riscv/x-smt-vdot.d      | 41 ++++++++++++
>>>    gas/testsuite/gas/riscv/x-smt-vdot.s      | 33 +++++++++
>>>    include/opcode/riscv-opc.h                | 38 +++++++++++
>>>    include/opcode/riscv.h                    |  9 +++
>>>    opcodes/riscv-dis.c                       | 33 +++++++++
>>>    opcodes/riscv-opc.c                       | 23 +++++++
>>>    14 files changed, 403 insertions(+)
>>>    create mode 100644 gas/testsuite/gas/riscv/x-smt-vdot-fail.d
>>>    create mode 100644 gas/testsuite/gas/riscv/x-smt-vdot-fail.l
>>>    create mode 100644 gas/testsuite/gas/riscv/x-smt-vdot-fail.s
>>>    create mode 100644 gas/testsuite/gas/riscv/x-smt-vdot.d
>>>    create mode 100644 gas/testsuite/gas/riscv/x-smt-vdot.s
>> THanks.  I've pushed this to the trunk.
> This does break the build with older gcc versions (8.5.0):
>
> ../../binutils-gdb/opcodes/riscv-dis.c: In function ?print_insn_args?:
> ../../binutils-gdb/opcodes/riscv-dis.c:927:9: error: a label can only be part of a statement and a declaration is not a statement
>           unsigned vd = EXTRACT_OPERAND (SPACEMIT_IME_VD, l) * 2;
>           ^~~~~~~~
> ../../binutils-gdb/opcodes/riscv-dis.c:932:9: error: a label can only be part of a statement and a declaration is not a statement
>           unsigned vs = EXTRACT_OPERAND (SPACEMIT_IME_VS1, l) * 2;
>           ^~~~~~~~
>
> It wants a block after a case label when declaring new variables.
>
> See also
> https://builder.sourceware.org/buildbot/#/builders/290/builds/6952/steps/4/logs/stdio
Ugh.? gcc-8 era.? ?I don't recall the default C language dialect used in 
that era, but definitely old and crusty.? I think the whole block can be 
wrapped in a curly block to fix this.

jeff

From zhaofujin@nucleisys.com  Tue Jun 23 02:55:51 2026
From: zhaofujin@nucleisys.com (=?utf-8?B?QmlnbWFnaWM=?=)
Date: Tue, 23 Jun 2026 10:55:51 +0800
Subject: [PATCH 1/3] RISC-V: Add ZCMT table jump relaxation
Message-ID: <tencent_7FF41A551F6ECE146558E6F8@qq.com>

Hi RISC-V maintainers and contributors,

When testing ZCMT functionality, I found that .option norelax does not actually prevent ZCMT instruction generation. Here's the test case I wrote:


Assembly
.section .text
.globl _start
.type _start, %function
_start:
&nbsp; &nbsp; .option push
&nbsp; &nbsp; .option norelax
&nbsp; &nbsp; .rept 70
&nbsp; &nbsp; call local_func
&nbsp; &nbsp; .endr
&nbsp; &nbsp; .option pop
&nbsp; &nbsp; .rept 70
&nbsp; &nbsp; call global_func
&nbsp; &nbsp; .endr
&nbsp; &nbsp; li a7, 93 &nbsp; &nbsp; &nbsp; &nbsp;# sys_exit
&nbsp; &nbsp; li a0, 0 &nbsp; &nbsp; &nbsp; &nbsp; # exit code
&nbsp; &nbsp; ecall
.type local_func, %function
local_func:
&nbsp; &nbsp; ret
.globl global_func
.type global_func, %function
global_func:
&nbsp; &nbsp; ret
With the following linker script:


Text
ENTRY(_start)
SECTIONS
{
&nbsp; &nbsp; .text 0x80000000 : {
&nbsp; &nbsp; &nbsp; &nbsp; *(.text)
&nbsp; &nbsp; }
&nbsp; &nbsp; .riscv.jvt : {
&nbsp; &nbsp; &nbsp; &nbsp; *(.riscv.jvt)
&nbsp; &nbsp; }
&nbsp; &nbsp; .data : {
&nbsp; &nbsp; &nbsp; &nbsp; *(.data)
&nbsp; &nbsp; }
}
Observation:
The .option push / .option norelax / .option pop block should prevent relaxation for the enclosed call instructions, but ZCMT transformations are still being applied.


Root Cause:
In _bfd_riscv_relax_section(), the ZCMT relaxation path does not check whether the relocation is paired with R_RISCV_RELAX. When .option norelax is used, the assembler does not emit R_RISCV_RELAX relocations alongside the call instructions, but the linker still applies ZCMT relaxation unconditionally.


Proposed Fix:
Skip ZCMT relaxation if the call relocation is not paired with R_RISCV_RELAX:


Diff
--- a/bfd/elfnn-riscv.c
+++ b/bfd/elfnn-riscv.c
@@ -6067,6 +6067,12 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; relax_func = _bfd_riscv_jvt_record;
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;else
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; continue;
+&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; /* Skip if not paired with R_RISCV_RELAX (i.e. .option norelax). &nbsp;*/
+&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; if (i == sec-&gt;reloc_count - 1
+&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;|| ELFNN_R_TYPE ((rel + 1)-&gt;r_info) != R_RISCV_RELAX
+&nbsp; &nbsp; &nbsp; &nbsp; &nbsp;|| rel-&gt;r_offset != (rel + 1)-&gt;r_offset)
+&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;continue;
+&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; i++;
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; *again = true;
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; }
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; else if (info-&gt;relax_trip == JVT_PROFILING_DETERMINE)
@@ -6076,6 +6082,12 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; relax_func = _bfd_riscv_jvt_mark;
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; else
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; continue;
+&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;/* Skip if not paired with R_RISCV_RELAX (i.e. .option norelax). &nbsp;*/
+&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;if (i == sec-&gt;reloc_count - 1
+&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;|| ELFNN_R_TYPE ((rel + 1)-&gt;r_info) != R_RISCV_RELAX
+&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;|| rel-&gt;r_offset != (rel + 1)-&gt;r_offset)
+&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;continue;
+&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;i++;
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; }
&nbsp; &nbsp; &nbsp; &nbsp; }
&nbsp; &nbsp; &nbsp;else if (info-&gt;relax_pass == RELAX_PASS_SHORTEN_LUI_CALL_TRREL_PCREL)
Explanation of the check:


i == sec-&gt;reloc_count - 1 ? ensure there's a next relocation to check
ELFNN_R_TYPE ((rel + 1)-&gt;r_info) != R_RISCV_RELAX ? verify the next relocation is R_RISCV_RELAX
rel-&gt;r_offset != (rel + 1)-&gt;r_offset ? ensure the relax relocation is at the same offset (paired)
Testing:
With this patch applied, the test case correctly preserves the call instructions inside the .option norelax block while still applying ZCMT relaxation to the unprotected calls outside the block.
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From hjl.tools@gmail.com  Tue Jun 23 05:01:22 2026
From: hjl.tools@gmail.com (H.J. Lu)
Date: Tue, 23 Jun 2026 13:01:22 +0800
Subject: Upcoming 2.47 branch and release dates
In-Reply-To: <CAMe9rOpMuwTZDkKqWCx9J5d+SRO9ySUiTKjdY7G=04wOE2cGYA@mail.gmail.com>
References: <87h5mvym74.fsf@redhat.com>
 <CAMe9rOpMuwTZDkKqWCx9J5d+SRO9ySUiTKjdY7G=04wOE2cGYA@mail.gmail.com>
Message-ID: <CAMe9rOr+pzBnpQ8VbVh9VJCH-=6nqTJ39rgcVdrAFPwDD4GHvQ@mail.gmail.com>

On Mon, Jun 22, 2026 at 5:29?PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Mon, Jun 22, 2026 at 5:11?PM Nick Clifton <nickc@redhat.com> wrote:
> >
> > Hi Guys,
> >
> >   The time for the 2.47 release is coming up fast.  My current plans
> >   are:
> >
> >     Create the branch:   Sat 11 July
> >     Create the release:  Sat 25 July
> >
> >   So now is the time to get any important fixes or features in...
>
> Hi Nick,
>
> Can you review the fix
>
> https://sourceware.org/pipermail/binutils/2026-June/149706.html
>
> for
>
> https://sourceware.org/bugzilla/show_bug.cgi?id=34184
>

Also avoid this regression:

https://sourceware.org/bugzilla/show_bug.cgi?id=34312

-- 
H.J.

From jbeulich@suse.com  Tue Jun 23 07:17:22 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Tue, 23 Jun 2026 09:17:22 +0200
Subject: [PATCH 2/3] gas/ELF: warn upon non-default visibility of local
 symbols
In-Reply-To: <CAMe9rOoqhA+o278P+bPWOvHSxENbjyiN=o+Goep-6MUt2--_-w@mail.gmail.com>
References: <bcd40b22-b90f-4334-8ab4-e8afeea2a6a9@suse.com>
 <193f86ed-f34b-4da8-9eac-68005830d369@suse.com>
 <e6007e9e-2cb7-4635-a974-5f753b212133@arm.com>
 <1397563c-32ca-4343-9587-99c197dd4029@suse.com>
 <b4ec2334-1821-4780-9876-f8a12d20dc4b@suse.com>
 <CAMe9rOoqhA+o278P+bPWOvHSxENbjyiN=o+Goep-6MUt2--_-w@mail.gmail.com>
Message-ID: <e43bc9d8-260e-46f1-9afc-c52eacd4ac60@suse.com>

On 23.06.2026 03:10, H.J. Lu wrote:
> On Fri, May 8, 2026 at 2:54?PM Jan Beulich <jbeulich@suse.com> wrote:
>>
>> On 10.04.2026 16:17, Jan Beulich wrote:
>>> On 10.04.2026 15:35, Richard Earnshaw (foss) wrote:
>>>> On 10/04/2026 14:31, Jan Beulich wrote:
>>>>> The spec explicitly precludes STB_LOCAL together with STV_PROTECTED (and,
>>>>> implicity, STV_HIDDEN or STV_INTERNAL), so we better wouldn't entirely
>>>>> silently write out symbols violating this.
>>>>>
>>>>> LoongArch's tc_symbol_new_hook() simply needs dropping. If FAKE_LABEL_NAME
>>>>> symbols can end up global, marking them hidden would need doing elsewhere.
>>>>> There not being a need to make any testsuite adjustments suggests though
>>>>> that this won't normally (ever?) happen.
>>>>>
>>>>> A couple of testcases then also need adjustment.
>>>>> ---
>>>>> It would be nice to re-use an existing loop, yet the one in
>>>>> elf_frob_file_before_adjust() comes too early, as does elf_frob_symbol().
>>>>>
>>>>> An alternative may be to imply .global from .hidden etc also for defined
>>>>> symbols (as looks to have been implied by some of the testcases being
>>>>> adjusted). This would then require to reject .local when a visibility was
>>>>> already set.
>>>
>>> As you can see from this, ...
>>>
>>>>> I wonder what purpose STV_* serve with e.g. STT_SECTION. Yet I also wonder
>>>>> what purpose STB_* other than STB_LOCAL serve with STT_SECTION (seeing how
>>>>> bfd/elf.c:swap_out_syms() explicitly uses STB_GLOBAL).
>>>>>
>>>>> The TI C6x testcase adjustments suggest that PLT relocations are
>>>>> needlessly emitted by gas for non-default visibility globals.
>>>>
>>>>
>>>> Do we know that this won't cause issues for real code out in the wild?  Might it not be better to just treat .hidden as making the symbol global, but hidden?
>>>
>>> ... I'm wondering the same. I meant to be conservative (as to exposing new
>>> globals) for v1. If collectively we think changing the behavior that way
>>> makes sense, I'll be happy to try that out for v2.
>>
>> Having thought about this more, implying global from hidden (etc) feels more
>> risky than keeping things as they are in v1: People suddenly may face
>> duplicate symbol linker errors that way. Short of any other comments /
>> opinions, I'll get the series in as is.
> 
> This warning isn't very useful and annoying:
> 
> https://sourceware.org/bugzilla/show_bug.cgi?id=34312

Your judgement feels pretty subjective to me. As said in the bug - people really
should decide: Do they want a local symbol or a hidden one?

Jan

From jbeulich@suse.com  Tue Jun 23 07:19:18 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Tue, 23 Jun 2026 09:19:18 +0200
Subject: Upcoming 2.47 branch and release dates
In-Reply-To: <CAMe9rOr+pzBnpQ8VbVh9VJCH-=6nqTJ39rgcVdrAFPwDD4GHvQ@mail.gmail.com>
References: <87h5mvym74.fsf@redhat.com>
 <CAMe9rOpMuwTZDkKqWCx9J5d+SRO9ySUiTKjdY7G=04wOE2cGYA@mail.gmail.com>
 <CAMe9rOr+pzBnpQ8VbVh9VJCH-=6nqTJ39rgcVdrAFPwDD4GHvQ@mail.gmail.com>
Message-ID: <cf2752b0-05d6-4a3f-91f9-aa97cee5b3ee@suse.com>

On 23.06.2026 07:01, H.J. Lu wrote:
> Also avoid this regression:
> 
> https://sourceware.org/bugzilla/show_bug.cgi?id=34312

Imo this isn't a regression, but new and improved behavior. The source has
an issue, and it is legitimate for gas to point out that there is one. It
should have been that way from the very introduction of ELF visibility.

Jan

From jbeulich@suse.com  Tue Jun 23 07:27:47 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Tue, 23 Jun 2026 09:27:47 +0200
Subject: [PATCH] PE/COFF: auto-promote to bigobj target when section count
 overflows
In-Reply-To: <CACcXsZjZf7zNWv8M9pJF6wFFE5KvdGQQoc7TUafR5FMXVM8_dA@mail.gmail.com>
References: <20260621174919.1150-3-oleg.tolmatcev@gmail.com>
 <5b3cf7f1-a1a9-46fe-a0ec-2267f5a0cf22@suse.com>
 <CACcXsZjZf7zNWv8M9pJF6wFFE5KvdGQQoc7TUafR5FMXVM8_dA@mail.gmail.com>
Message-ID: <f510870a-2069-4a30-8045-a9607059be2f@suse.com>

On 22.06.2026 21:26, Oleg Tolmatcev wrote:
> Am Mo., 22. Juni 2026 um 09:46 Uhr schrieb Jan Beulich <jbeulich@suse.com>:
>>> --- a/gas/testsuite/gas/pe/pe.exp
>>> +++ b/gas/testsuite/gas/pe/pe.exp
>>> @@ -70,4 +70,5 @@ if {[istarget "aarch64-*-pe*"] || [istarget "aarch64-*-mingw*"]} {
>>>
>>>  if ([istarget "*-*-mingw*"]) then {
>>>       run_dump_test "big-obj"
>>> +     run_dump_test "big-obj-auto"
>>>  }
>>
>> Why would the test want limiting to MinGW?
> 
> I don't know because I didn't write that code.

You didn't write the original code, but it was you who decided to insert the
new test's running inside the conditional, rather than outside (or in a new,
less restrictive one). Especially since the new "default to big-obj if needed"
isn't (directly) target dependent, the new test also should cover all targets
which are affected by the change.

Of course there's the orthogonal issue of the pre-existing conditional wanting
relaxing. That's not something I'm demanding you to do at the same time (yet
of course I wouldn't mind if you did). The three bfd/pe-*.c which #define
COFF_WITH_PE_BIGOBJ do so entirely unconditionally, afaics. Hence that's the
pattern we want to also use for engaging the pre-existing and the new test.

Jan

From hjl.tools@gmail.com  Tue Jun 23 07:37:03 2026
From: hjl.tools@gmail.com (H.J. Lu)
Date: Tue, 23 Jun 2026 15:37:03 +0800
Subject: [PATCH 2/3] gas/ELF: warn upon non-default visibility of local
 symbols
In-Reply-To: <e43bc9d8-260e-46f1-9afc-c52eacd4ac60@suse.com>
References: <bcd40b22-b90f-4334-8ab4-e8afeea2a6a9@suse.com>
 <193f86ed-f34b-4da8-9eac-68005830d369@suse.com>
 <e6007e9e-2cb7-4635-a974-5f753b212133@arm.com>
 <1397563c-32ca-4343-9587-99c197dd4029@suse.com>
 <b4ec2334-1821-4780-9876-f8a12d20dc4b@suse.com>
 <CAMe9rOoqhA+o278P+bPWOvHSxENbjyiN=o+Goep-6MUt2--_-w@mail.gmail.com>
 <e43bc9d8-260e-46f1-9afc-c52eacd4ac60@suse.com>
Message-ID: <CAMe9rOpVyKapj7FrC1k+MZRqO1J+FZhq-HnfarzpuPedkJ0snA@mail.gmail.com>

On Tue, Jun 23, 2026 at 3:17?PM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 23.06.2026 03:10, H.J. Lu wrote:
> > On Fri, May 8, 2026 at 2:54?PM Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> On 10.04.2026 16:17, Jan Beulich wrote:
> >>> On 10.04.2026 15:35, Richard Earnshaw (foss) wrote:
> >>>> On 10/04/2026 14:31, Jan Beulich wrote:
> >>>>> The spec explicitly precludes STB_LOCAL together with STV_PROTECTED (and,
> >>>>> implicity, STV_HIDDEN or STV_INTERNAL), so we better wouldn't entirely
> >>>>> silently write out symbols violating this.
> >>>>>
> >>>>> LoongArch's tc_symbol_new_hook() simply needs dropping. If FAKE_LABEL_NAME
> >>>>> symbols can end up global, marking them hidden would need doing elsewhere.
> >>>>> There not being a need to make any testsuite adjustments suggests though
> >>>>> that this won't normally (ever?) happen.
> >>>>>
> >>>>> A couple of testcases then also need adjustment.
> >>>>> ---
> >>>>> It would be nice to re-use an existing loop, yet the one in
> >>>>> elf_frob_file_before_adjust() comes too early, as does elf_frob_symbol().
> >>>>>
> >>>>> An alternative may be to imply .global from .hidden etc also for defined
> >>>>> symbols (as looks to have been implied by some of the testcases being
> >>>>> adjusted). This would then require to reject .local when a visibility was
> >>>>> already set.
> >>>
> >>> As you can see from this, ...
> >>>
> >>>>> I wonder what purpose STV_* serve with e.g. STT_SECTION. Yet I also wonder
> >>>>> what purpose STB_* other than STB_LOCAL serve with STT_SECTION (seeing how
> >>>>> bfd/elf.c:swap_out_syms() explicitly uses STB_GLOBAL).
> >>>>>
> >>>>> The TI C6x testcase adjustments suggest that PLT relocations are
> >>>>> needlessly emitted by gas for non-default visibility globals.
> >>>>
> >>>>
> >>>> Do we know that this won't cause issues for real code out in the wild?  Might it not be better to just treat .hidden as making the symbol global, but hidden?
> >>>
> >>> ... I'm wondering the same. I meant to be conservative (as to exposing new
> >>> globals) for v1. If collectively we think changing the behavior that way
> >>> makes sense, I'll be happy to try that out for v2.
> >>
> >> Having thought about this more, implying global from hidden (etc) feels more
> >> risky than keeping things as they are in v1: People suddenly may face
> >> duplicate symbol linker errors that way. Short of any other comments /
> >> opinions, I'll get the series in as is.
> >
> > This warning isn't very useful and annoying:
> >
> > https://sourceware.org/bugzilla/show_bug.cgi?id=34312
>
> Your judgement feels pretty subjective to me. As said in the bug - people really
> should decide: Do they want a local symbol or a hidden one?
>

The source code is extracted from glibc:

#include <stdint.h>

extern void _dl_sysinfo_int80 (void)
  __attribute__ ((visibility ("hidden")));

asm (".text\n\t"
     ".type _dl_sysinfo_int80,@function\n\t"
     "_dl_sysinfo_int80:\n\t"
     "int $0x80;\n\t"
     "ret");

uintptr_t
foo ()
{
  return (uintptr_t) _dl_sysinfo_int80;
}

_dl_sysinfo_int80 is a local function, but it is defined in an asm statement.
Since it is referenced in C, it needs to be declared as hidden.  ELF spec
doesn't forbid the hidden visibility on a local symbol.  It is just a no-op.

-- 
H.J.

From jbeulich@suse.com  Tue Jun 23 07:55:51 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Tue, 23 Jun 2026 09:55:51 +0200
Subject: [PATCH 2/3] gas/ELF: warn upon non-default visibility of local
 symbols
In-Reply-To: <CAMe9rOpVyKapj7FrC1k+MZRqO1J+FZhq-HnfarzpuPedkJ0snA@mail.gmail.com>
References: <bcd40b22-b90f-4334-8ab4-e8afeea2a6a9@suse.com>
 <193f86ed-f34b-4da8-9eac-68005830d369@suse.com>
 <e6007e9e-2cb7-4635-a974-5f753b212133@arm.com>
 <1397563c-32ca-4343-9587-99c197dd4029@suse.com>
 <b4ec2334-1821-4780-9876-f8a12d20dc4b@suse.com>
 <CAMe9rOoqhA+o278P+bPWOvHSxENbjyiN=o+Goep-6MUt2--_-w@mail.gmail.com>
 <e43bc9d8-260e-46f1-9afc-c52eacd4ac60@suse.com>
 <CAMe9rOpVyKapj7FrC1k+MZRqO1J+FZhq-HnfarzpuPedkJ0snA@mail.gmail.com>
Message-ID: <67a1182c-e7d0-40ad-98ec-9b49c1d28410@suse.com>

On 23.06.2026 09:37, H.J. Lu wrote:
> On Tue, Jun 23, 2026 at 3:17?PM Jan Beulich <jbeulich@suse.com> wrote:
>>
>> On 23.06.2026 03:10, H.J. Lu wrote:
>>> On Fri, May 8, 2026 at 2:54?PM Jan Beulich <jbeulich@suse.com> wrote:
>>>>
>>>> On 10.04.2026 16:17, Jan Beulich wrote:
>>>>> On 10.04.2026 15:35, Richard Earnshaw (foss) wrote:
>>>>>> On 10/04/2026 14:31, Jan Beulich wrote:
>>>>>>> The spec explicitly precludes STB_LOCAL together with STV_PROTECTED (and,
>>>>>>> implicity, STV_HIDDEN or STV_INTERNAL), so we better wouldn't entirely
>>>>>>> silently write out symbols violating this.
>>>>>>>
>>>>>>> LoongArch's tc_symbol_new_hook() simply needs dropping. If FAKE_LABEL_NAME
>>>>>>> symbols can end up global, marking them hidden would need doing elsewhere.
>>>>>>> There not being a need to make any testsuite adjustments suggests though
>>>>>>> that this won't normally (ever?) happen.
>>>>>>>
>>>>>>> A couple of testcases then also need adjustment.
>>>>>>> ---
>>>>>>> It would be nice to re-use an existing loop, yet the one in
>>>>>>> elf_frob_file_before_adjust() comes too early, as does elf_frob_symbol().
>>>>>>>
>>>>>>> An alternative may be to imply .global from .hidden etc also for defined
>>>>>>> symbols (as looks to have been implied by some of the testcases being
>>>>>>> adjusted). This would then require to reject .local when a visibility was
>>>>>>> already set.
>>>>>
>>>>> As you can see from this, ...
>>>>>
>>>>>>> I wonder what purpose STV_* serve with e.g. STT_SECTION. Yet I also wonder
>>>>>>> what purpose STB_* other than STB_LOCAL serve with STT_SECTION (seeing how
>>>>>>> bfd/elf.c:swap_out_syms() explicitly uses STB_GLOBAL).
>>>>>>>
>>>>>>> The TI C6x testcase adjustments suggest that PLT relocations are
>>>>>>> needlessly emitted by gas for non-default visibility globals.
>>>>>>
>>>>>>
>>>>>> Do we know that this won't cause issues for real code out in the wild?  Might it not be better to just treat .hidden as making the symbol global, but hidden?
>>>>>
>>>>> ... I'm wondering the same. I meant to be conservative (as to exposing new
>>>>> globals) for v1. If collectively we think changing the behavior that way
>>>>> makes sense, I'll be happy to try that out for v2.
>>>>
>>>> Having thought about this more, implying global from hidden (etc) feels more
>>>> risky than keeping things as they are in v1: People suddenly may face
>>>> duplicate symbol linker errors that way. Short of any other comments /
>>>> opinions, I'll get the series in as is.
>>>
>>> This warning isn't very useful and annoying:
>>>
>>> https://sourceware.org/bugzilla/show_bug.cgi?id=34312
>>
>> Your judgement feels pretty subjective to me. As said in the bug - people really
>> should decide: Do they want a local symbol or a hidden one?
>>
> 
> The source code is extracted from glibc:
> 
> #include <stdint.h>
> 
> extern void _dl_sysinfo_int80 (void)
>   __attribute__ ((visibility ("hidden")));

This results in a .hidden directive, which is in principle fine. In combination
with ...

> asm (".text\n\t"
>      ".type _dl_sysinfo_int80,@function\n\t"
>      "_dl_sysinfo_int80:\n\t"
>      "int $0x80;\n\t"
>      "ret");
> 
> uintptr_t
> foo ()
> {
>   return (uintptr_t) _dl_sysinfo_int80;

... this actual reference, arguably the compiler should also emit a .global
directive. It generally gets away without doing so because referenced symbols
which aren't otherwise defined are implicitly global (which, seeing how
other assemblers behave, can be argued as being a bug, but apparently is
"traditional behavior" on UNIXes).

> }
> 
> _dl_sysinfo_int80 is a local function, but it is defined in an asm statement.
> Since it is referenced in C, it needs to be declared as hidden.

It doesn't need to be. It could as well be declared non-hidden (accepting
that it then will be visible to the linker).

>  ELF spec
> doesn't forbid the hidden visibility on a local symbol.  It is just a no-op.

You did read

"The spec explicitly precludes STB_LOCAL together with STV_PROTECTED (and,
 implicity, STV_HIDDEN or STV_INTERNAL), so we better wouldn't entirely
 silently write out symbols violating this."

in the patch description, didn't you? If you think that's wrong, did you
then not consider going back to the ELF spec to find what exactly is said
there: "A symbol with STB_LOCAL binding may not have STV_PROTECTED
visibility." And then for STV_HIDDEN: "Such a symbol is necessarily
protected." I.e. what is said for STV_PROTECTED applies to STV_HIDDEN (and
STV_INTERNAL) as well, at least according to my interpretation of that
wording.

Jan

From krebbel@linux.ibm.com  Tue Jun 23 07:57:05 2026
From: krebbel@linux.ibm.com (Andreas Krebbel)
Date: Tue, 23 Jun 2026 09:57:05 +0200
Subject: [PATCH] s390: Add store CPU counter multiple instruction
In-Reply-To: <20260424084026.2959245-1-jremus@linux.ibm.com>
References: <20260424084026.2959245-1-jremus@linux.ibm.com>
Message-ID: <4a288de2-674e-4ae8-80da-f2d430cf332e@linux.ibm.com>

On 4/24/26 10:40 AM, Jens Remus wrote:
> IBM z13 introduced the "store CPU counter multiple" (stcctm) instruction
> with the Store-CPU-Counter-Multiple Facility, which is part of the
> CPU-Measurement Facilities (CPUMF) [1].
>
> While at it add a comment to the s390 opcode table for the existing
> CPUMF instructions.
>
> [1]: The Load-Program-Parameter and the CPU-Measurement Facilities,
>       SA23-2260-08,
>       https://www.ibm.com/docs/en/module_1678991624569/pdf/SA23-2260-08.pdf
>
> opcodes/
> 	* s390-opc.txt (stcctm): Add store CPU counter multiple
> 	instruction.  Add comment on CPUMF instructions.
>
> gas/testsuite/
> 	* gas/s390/zarch-z13.d (stcctm): Add test for store CPU counter
> 	multiple instruction.
> 	* gas/s390/zarch-z13.s (stcctm): Likewise.
>
> Signed-off-by: Jens Remus <jremus@linux.ibm.com>

Ok, Thanks!

Andreas

> ---
>   gas/testsuite/gas/s390/zarch-z13.d | 2 ++
>   gas/testsuite/gas/s390/zarch-z13.s | 1 +
>   opcodes/s390-opc.txt               | 8 ++++++++
>   3 files changed, 11 insertions(+)
>
> diff --git a/gas/testsuite/gas/s390/zarch-z13.d b/gas/testsuite/gas/s390/zarch-z13.d
> index d768e0b9db59..54c42f858f94 100644
> --- a/gas/testsuite/gas/s390/zarch-z13.d
> +++ b/gas/testsuite/gas/s390/zarch-z13.d
> @@ -684,3 +684,5 @@ Disassembly of section .text:
>   .*:	e7 f6 9f a0 d0 0e [	]*vst	%v15,4000\(%r6,%r9\),13
>   .*:	e7 f1 6f a0 04 3e [	]*vstm	%v15,%v17,4000\(%r6\)
>   .*:	e7 f1 6f a0 d4 3e [	]*vstm	%v15,%v17,4000\(%r6\),13
> +.*:	eb 13 26 ce 05 17 [	 ]*stcctm	%r1,3,22222\(%r2\)
> +#?.*:	07 07 [	 ]*nopr	%r7
> diff --git a/gas/testsuite/gas/s390/zarch-z13.s b/gas/testsuite/gas/s390/zarch-z13.s
> index 8c2fb706e0c0..370aed0830aa 100644
> --- a/gas/testsuite/gas/s390/zarch-z13.s
> +++ b/gas/testsuite/gas/s390/zarch-z13.s
> @@ -678,3 +678,4 @@ foo:
>   	vst		%v15,4000(%r6,%r9),13
>   	vstm		%v15,%v17,4000(%r6)
>   	vstm		%v15,%v17,4000(%r6),13
> +	stcctm	%r1,3,22222(2)
> diff --git a/opcodes/s390-opc.txt b/opcodes/s390-opc.txt
> index 6511059400b8..d40fa8c70cf4 100644
> --- a/opcodes/s390-opc.txt
> +++ b/opcodes/s390-opc.txt
> @@ -991,6 +991,10 @@ b9a2 ptf RRE_R0 "perform topology function" z10 zarch
>   b9af pfmf RRE_RR "perform frame management function" z10 zarch
>   b9bf trte RRF_U0RER "translate and test extended" z10 zarch optparm
>   b9bd trtre RRF_U0RER "translate and test reverse extended" z10 zarch optparm
> +
> +# CPUMF: CPU-Measurement Counter Facility, CPU-Measurement Sampling Facility,
> +# Load-Program-Parameter Facility
> +
>   b2ed ecpga RRE_RR "extract coprocessor-group address" z10 zarch
>   b2e4 ecctr RRE_RR "extract cpu counter" z10 zarch
>   b2e5 epctr RRE_RR "extract peripheral counter" z10 zarch
> @@ -1713,6 +1717,10 @@ e70000000036 vlm VRS_VVRDU "vector load multiple" z13 zarch optparm,vx
>   e7000000000e vst VRX_VRRDU "vector store" z13 zarch optparm,vx
>   e7000000003e vstm VRS_VVRDU "vector store multiple" z13 zarch optparm,vx
>   
> +# CPUMF: Store-CPU-Counter-Multiple Facility
> +
> +eb0000000017 stcctm RSY_RURD "store cpu counter multiple" z13 zarch
> +
>   # arch12 instructions
>   
>   # Vector Enhancements Facility 1

From zhuangqiubin@linux.spacemit.com  Tue Jun 23 09:52:21 2026
From: zhuangqiubin@linux.spacemit.com (Mark Zhuang)
Date: Tue, 23 Jun 2026 17:52:21 +0800
Subject: [PATCH] RISC-V: Fix build with GCC-8
Message-ID: <20260623095221.1792011-1-zhuangqiubin@linux.spacemit.com>

From: Mark Zhuang <mark.zhuang@spacemit.com>

GCC 8.5.0 rejects a declaration right after a case label.
Add braces to fix it.
---
 gas/config/tc-riscv.c | 335 ++++++++++++++++++++++--------------------
 opcodes/riscv-dis.c   |  16 +-
 2 files changed, 182 insertions(+), 169 deletions(-)

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 5ffa2ef1f1d..cec3c1f65a2 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1791,49 +1791,53 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 		}
 		break;
 	    case 'p': /* Vendor-specific (SpacemiT) operands.  */
-	      size_t n;
-	      size_t s;
-	      switch (*++oparg)
-		{
-		case 'V':
-		  switch (*++oparg)
-		    {
-		    case 'd':
-		      USE_BITS (OP_MASK_SPACEMIT_IME_VD, OP_SH_SPACEMIT_IME_VD);
+	      {
+		size_t n;
+		size_t s;
+		switch (*++oparg)
+		  {
+		    case 'V':
+		      switch (*++oparg)
+			{
+			  case 'd':
+			    USE_BITS (OP_MASK_SPACEMIT_IME_VD,
+				      OP_SH_SPACEMIT_IME_VD);
+			    break;
+			  case 's':
+			    USE_BITS (OP_MASK_SPACEMIT_IME_VS1,
+				      OP_SH_SPACEMIT_IME_VS1);
+			    break;
+			  case 'm':
+			    USE_BITS (OP_MASK_SPACEMIT_IME_VMASK,
+				      OP_SH_SPACEMIT_IME_VMASK);
+			    break;
+			  default:
+			    goto unknown_validate_operand;
+			}
 		      break;
-		    case 's':
-		      USE_BITS (OP_MASK_SPACEMIT_IME_VS1,
-				OP_SH_SPACEMIT_IME_VS1);
+		    case 'u': /* Integer immediate, 'XpuN@S' ...
+				 N-bit unsigned immediate at bit S.  */
+		      n = strtol (oparg + 1, (char **)&oparg, 10);
+		      if (*oparg != '@')
+			goto unknown_validate_operand;
+		      s = strtol (oparg + 1, (char **)&oparg, 10);
+		      oparg--;
+		      USE_IMM (n, s);
 		      break;
-		    case 'm':
-		      USE_BITS (OP_MASK_SPACEMIT_IME_VMASK,
-				OP_SH_SPACEMIT_IME_VMASK);
+		    case 'n':
+		    case 'b':
+		      used_bits |= ENCODE_SPACEMIT_IME_UIMM2_SP (-1U);
+		      break;
+		    case 'w':
+		    case 'x':
+		      USE_BITS (OP_MASK_SPACEMIT_IME_WI,
+				OP_SH_SPACEMIT_IME_WI);
 		      break;
 		    default:
 		      goto unknown_validate_operand;
-		    }
-		  break;
-		case 'u': /* Integer immediate, 'XpuN@S' ...
-			     N-bit unsigned immediate at bit S.  */
-		  n = strtol (oparg + 1, (char **)&oparg, 10);
-		  if (*oparg != '@')
-		    goto unknown_validate_operand;
-		  s = strtol (oparg + 1, (char **)&oparg, 10);
-		  oparg--;
-		  USE_IMM (n, s);
-		  break;
-		case 'n':
-		case 'b':
-		  used_bits |= ENCODE_SPACEMIT_IME_UIMM2_SP (-1U);
-		  break;
-		case 'w':
-		case 'x':
-		  USE_BITS (OP_MASK_SPACEMIT_IME_WI, OP_SH_SPACEMIT_IME_WI);
-		  break;
-		default:
-		  goto unknown_validate_operand;
-		}
-	      break;
+		  }
+		break;
+	      }
 	    default:
 	      goto unknown_validate_operand;
 	    }
@@ -4309,144 +4313,149 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		  break;
 
 		case 'p': /* Vendor-specific (SpacemiT) operands.  */
-		  size_t n;
-		  size_t s;
-		  switch (*++oparg)
-		    {
-		    case 'V':
-		      switch (*++oparg)
-			{
-			case 'd':
-			  if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
-			    break;
-			  if ((regno & 0x1) != 0)
+		  {
+		    size_t n;
+		    size_t s;
+		    switch (*++oparg)
+		      {
+			case 'V':
+			  switch (*++oparg)
 			    {
-			      error.msg
-				= _("illegal operands (vd must be even)");
-			      error.missing_ext = NULL;
-			      goto out;
+			      case 'd':
+				if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
+				  break;
+				if ((regno & 0x1) != 0)
+				  {
+				    error.msg
+				      = _("illegal operands (vd must be even)");
+				    error.missing_ext = NULL;
+				    goto out;
+				  }
+				INSERT_OPERAND (SPACEMIT_IME_VD, *ip, regno>>1);
+				continue;
+			      case 's':
+				if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
+				  break;
+				if ((regno & 0x1) != 0)
+				  {
+				    error.msg
+				      = _("illegal operands "
+					  "(vs1 must be even)");
+				    error.missing_ext = NULL;
+				    goto out;
+				  }
+				INSERT_OPERAND (SPACEMIT_IME_VS1,
+						*ip, regno>>1);
+				continue;
+			      case 'm':
+				if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
+				  break;
+				if (regno >= 2)
+				  {
+				    error.msg
+				      = _("illegal operands "
+					  "(mask must be v0/v1)");
+				    error.missing_ext = NULL;
+				    goto out;
+				  }
+				INSERT_OPERAND (SPACEMIT_IME_VMASK, *ip, regno);
+				continue;
+			      default:
+				goto unknown_riscv_ip_operand;
 			    }
-			  INSERT_OPERAND (SPACEMIT_IME_VD, *ip, regno>>1);
+			  break;
+			case 'u': /* Integer immediate, 'XpuN@S' ...
+				     N-bit unsigned immediate at bit S.  */
+			  n = strtol (oparg + 1, (char **)&oparg, 10);
+			  if (*oparg != '@')
+			    goto unknown_riscv_ip_operand;
+			  s = strtol (oparg + 1, (char **)&oparg, 10);
+			  oparg--;
+			  my_getExpression (imm_expr, asarg, force_reloc);
+			  check_absolute_expr (ip, imm_expr, false);
+			  if (!VALIDATE_U_IMM (imm_expr->X_add_number, n))
+			    as_bad (_("improper immediate value (%"PRIu64")"),
+				    imm_expr->X_add_number);
+			  INSERT_IMM (n, s, *ip, imm_expr->X_add_number);
+			  imm_expr->X_op = O_absent;
+			  asarg = expr_parse_end;
 			  continue;
-			case 's':
-			  if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
+			case 'n': /* Xpn: stride (0-1), paired with Xpx.  */
+			  my_getExpression (imm_expr, asarg, force_reloc);
+			  check_absolute_expr (ip, imm_expr, false);
+			  if (imm_expr->X_add_number < 0
+			      || imm_expr->X_add_number >= 2)
 			    break;
-			  if ((regno & 0x1) != 0)
+			  ip->insn_opcode
+			    |= ENCODE_SPACEMIT_IME_UIMM2_SP
+				 (imm_expr->X_add_number);
+			  imm_expr->X_op = O_absent;
+			  asarg = expr_parse_end;
+			  continue;
+			case 'b': /* Xpb: stride (0-3), paired with Xpw.  */
+			  my_getExpression (imm_expr, asarg, force_reloc);
+			  check_absolute_expr (ip, imm_expr, false);
+			  if (imm_expr->X_add_number < 0
+			      || imm_expr->X_add_number >= 4)
 			    {
-			      error.msg
-				= _("illegal operands (vs1 must be even)");
-			      error.missing_ext = NULL;
-			      goto out;
+			      as_bad (_("bad value for stride field,"
+					" value must be 0..3"));
+			      break;
 			    }
-			  INSERT_OPERAND (SPACEMIT_IME_VS1, *ip, regno>>1);
+			  ip->insn_opcode
+			    |= ENCODE_SPACEMIT_IME_UIMM2_SP
+				 (imm_expr->X_add_number);
+			  imm_expr->X_op = O_absent;
+			  asarg = expr_parse_end;
 			  continue;
-			case 'm':
-			  if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
-			    break;
-			  if (regno >= 2)
+			case 'w':
+			  /* Xpw: optional data-width suffix, i8 only (WI=3).
+			     If omitted, defaults to i8.  */
+			  if (*asarg == ',')
 			    {
-			      error.msg
-				= _("illegal operands (mask must be v0/v1)");
-			      error.missing_ext = NULL;
-			      goto out;
+			      if (strcmp (asarg + 1, "i8") != 0)
+				{
+				  error.msg
+				    = _("illegal operands (invalid data type)");
+				  error.missing_ext = NULL;
+				  goto out;
+				}
+			      asarg += 3;
 			    }
-			  INSERT_OPERAND (SPACEMIT_IME_VMASK, *ip, regno);
+			  else if (*asarg != '\0')
+			    goto unknown_riscv_ip_operand;
+			  regno = 3;
+			  INSERT_OPERAND (SPACEMIT_IME_WI, *ip, regno);
 			  continue;
-			default:
-			  goto unknown_riscv_ip_operand;
-			}
-		      break;
-		    case 'u': /* Integer immediate, 'XpuN@S' ...
-				 N-bit unsigned immediate at bit S.  */
-		      n = strtol (oparg + 1, (char **)&oparg, 10);
-		      if (*oparg != '@')
-			goto unknown_riscv_ip_operand;
-		      s = strtol (oparg + 1, (char **)&oparg, 10);
-		      oparg--;
-		      my_getExpression (imm_expr, asarg, force_reloc);
-		      check_absolute_expr (ip, imm_expr, false);
-		      if (!VALIDATE_U_IMM (imm_expr->X_add_number, n))
-			as_bad (_("improper immediate value (%"PRIu64")"),
-				imm_expr->X_add_number);
-		      INSERT_IMM (n, s, *ip, imm_expr->X_add_number);
-		      imm_expr->X_op = O_absent;
-		      asarg = expr_parse_end;
-		      continue;
-		    case 'n': /* Xpn: stride (0-1), paired with Xpx.  */
-		      my_getExpression (imm_expr, asarg, force_reloc);
-		      check_absolute_expr (ip, imm_expr, false);
-		      if (imm_expr->X_add_number < 0
-			  || imm_expr->X_add_number >= 2)
-			break;
-		      ip->insn_opcode
-			|= ENCODE_SPACEMIT_IME_UIMM2_SP
-			     (imm_expr->X_add_number);
-		      imm_expr->X_op = O_absent;
-		      asarg = expr_parse_end;
-		      continue;
-		    case 'b': /* Xpb: stride (0-3), paired with Xpw.  */
-		      my_getExpression (imm_expr, asarg, force_reloc);
-		      check_absolute_expr (ip, imm_expr, false);
-		      if (imm_expr->X_add_number < 0
-			  || imm_expr->X_add_number >= 4)
-			{
-			  as_bad (_("bad value for stride field,"
-				    " value must be 0..3"));
-			  break;
-			}
-		      ip->insn_opcode
-			|= ENCODE_SPACEMIT_IME_UIMM2_SP
-			     (imm_expr->X_add_number);
-		      imm_expr->X_op = O_absent;
-		      asarg = expr_parse_end;
-		      continue;
-		    case 'w':
-		      /* Xpw: optional data-width suffix, i8 only (WI=3).
-			 If omitted, defaults to i8.  */
-		      if (*asarg == ',')
-			{
-			  if (strcmp (asarg + 1, "i8") != 0)
+			case 'x':
+			  /* Xpx: optional data-width suffix, i4 or i8 (WI=2/3).
+			     If omitted, defaults to i8.  */
+			  if (*asarg == ',')
 			    {
-			      error.msg
-				= _("illegal operands (invalid data type)");
-			      error.missing_ext = NULL;
-			      goto out;
+			      if (strcmp (asarg + 1, "i4") == 0)
+				regno = 2;
+			      else if (strcmp (asarg + 1, "i8") == 0)
+				regno = 3;
+			      else
+				{
+				  error.msg
+				    = _("illegal operands (invalid data type)");
+				  error.missing_ext = NULL;
+				  goto out;
+				}
+			      asarg += 3;
 			    }
-			  asarg += 3;
-			}
-		      else if (*asarg != '\0')
-			goto unknown_riscv_ip_operand;
-		      regno = 3;
-		      INSERT_OPERAND (SPACEMIT_IME_WI, *ip, regno);
-		      continue;
-		    case 'x':
-		      /* Xpx: optional data-width suffix, i4 or i8 (WI=2/3).
-			 If omitted, defaults to i8.  */
-		      if (*asarg == ',')
-			{
-			  if (strcmp (asarg + 1, "i4") == 0)
-			    regno = 2;
-			  else if (strcmp (asarg + 1, "i8") == 0)
-			    regno = 3;
+			  else if (*asarg != '\0')
+			    goto unknown_riscv_ip_operand;
 			  else
-			    {
-			      error.msg
-				= _("illegal operands (invalid data type)");
-			      error.missing_ext = NULL;
-			      goto out;
-			    }
-			  asarg += 3;
-			}
-		      else if (*asarg != '\0')
-			goto unknown_riscv_ip_operand;
-		      else
-			regno = 3;
-		      INSERT_OPERAND (SPACEMIT_IME_WI, *ip, regno);
-		      continue;
-		    default:
-		      goto unknown_riscv_ip_operand;
-		    }
-		  break;
+			    regno = 3;
+			  INSERT_OPERAND (SPACEMIT_IME_WI, *ip, regno);
+			  continue;
+			default:
+			  goto unknown_riscv_ip_operand;
+		      }
+		    break;
+		  }
 		default:
 		  goto unknown_riscv_ip_operand;
 		}
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index ca0d9bfd121..edb9ce04778 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -924,14 +924,18 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 		  switch (*++oparg)
 		    {
 		    case 'd':
-		      unsigned vd = EXTRACT_OPERAND (SPACEMIT_IME_VD, l) * 2;
-		      print (info->stream, dis_style_register, "%s",
-			     riscv_vecr_names_numeric[vd]);
+		      {
+			unsigned vd = EXTRACT_OPERAND (SPACEMIT_IME_VD, l) * 2;
+			print (info->stream, dis_style_register, "%s",
+			       riscv_vecr_names_numeric[vd]);
+		      }
 		      break;
 		    case 's':
-		      unsigned vs = EXTRACT_OPERAND (SPACEMIT_IME_VS1, l) * 2;
-		      print (info->stream, dis_style_register, "%s",
-			     riscv_vecr_names_numeric[vs]);
+		      {
+			unsigned vs = EXTRACT_OPERAND (SPACEMIT_IME_VS1, l) * 2;
+			print (info->stream, dis_style_register, "%s",
+			       riscv_vecr_names_numeric[vs]);
+		      }
 		      break;
 		    case 'm':
 		      {
-- 
2.34.1


From zhuangqiubin@linux.spacemit.com  Tue Jun 23 10:10:40 2026
From: zhuangqiubin@linux.spacemit.com (Mark Zhuang)
Date: Tue, 23 Jun 2026 18:10:40 +0800
Subject: [PATCH v6 1/2] RISC-V: Add SpacemiT vendor extension xsmtvdot
In-Reply-To: <2f3139c1-cdbb-4452-b575-dc06740d9198@qti.qualcomm.com>
References: <2f3139c1-cdbb-4452-b575-dc06740d9198@qti.qualcomm.com>
Message-ID: <20260623101040.1804152-1-zhuangqiubin@linux.spacemit.com>

Thank you, Jeffrey and Mark!

I have sent a fix patch to the mailing list:
https://sourceware.org/pipermail/binutils/2026-June/149757.html

Best regards,
Mark Zhuang

From aburgess@redhat.com  Tue Jun 23 10:18:12 2026
From: aburgess@redhat.com (Andrew Burgess)
Date: Tue, 23 Jun 2026 11:18:12 +0100
Subject: [PATCH] RISC-V: Fix build with GCC-8
In-Reply-To: <20260623095221.1792011-1-zhuangqiubin@linux.spacemit.com>
References: <20260623095221.1792011-1-zhuangqiubin@linux.spacemit.com>
Message-ID: <87wlvpo90b.fsf@redhat.com>

Mark Zhuang <zhuangqiubin@linux.spacemit.com> writes:

> From: Mark Zhuang <mark.zhuang@spacemit.com>
>
> GCC 8.5.0 rejects a declaration right after a case label.
> Add braces to fix it.

I cannot approve this patch, but I also ran into this issue building GDB
because of the opcodes/ part, and your fix looks good to me (and fixes
my build), so +1 here.

Thanks,
Andrew


> ---
>  gas/config/tc-riscv.c | 335 ++++++++++++++++++++++--------------------
>  opcodes/riscv-dis.c   |  16 +-
>  2 files changed, 182 insertions(+), 169 deletions(-)
>
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index 5ffa2ef1f1d..cec3c1f65a2 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -1791,49 +1791,53 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
>  		}
>  		break;
>  	    case 'p': /* Vendor-specific (SpacemiT) operands.  */
> -	      size_t n;
> -	      size_t s;
> -	      switch (*++oparg)
> -		{
> -		case 'V':
> -		  switch (*++oparg)
> -		    {
> -		    case 'd':
> -		      USE_BITS (OP_MASK_SPACEMIT_IME_VD, OP_SH_SPACEMIT_IME_VD);
> +	      {
> +		size_t n;
> +		size_t s;
> +		switch (*++oparg)
> +		  {
> +		    case 'V':
> +		      switch (*++oparg)
> +			{
> +			  case 'd':
> +			    USE_BITS (OP_MASK_SPACEMIT_IME_VD,
> +				      OP_SH_SPACEMIT_IME_VD);
> +			    break;
> +			  case 's':
> +			    USE_BITS (OP_MASK_SPACEMIT_IME_VS1,
> +				      OP_SH_SPACEMIT_IME_VS1);
> +			    break;
> +			  case 'm':
> +			    USE_BITS (OP_MASK_SPACEMIT_IME_VMASK,
> +				      OP_SH_SPACEMIT_IME_VMASK);
> +			    break;
> +			  default:
> +			    goto unknown_validate_operand;
> +			}
>  		      break;
> -		    case 's':
> -		      USE_BITS (OP_MASK_SPACEMIT_IME_VS1,
> -				OP_SH_SPACEMIT_IME_VS1);
> +		    case 'u': /* Integer immediate, 'XpuN@S' ...
> +				 N-bit unsigned immediate at bit S.  */
> +		      n = strtol (oparg + 1, (char **)&oparg, 10);
> +		      if (*oparg != '@')
> +			goto unknown_validate_operand;
> +		      s = strtol (oparg + 1, (char **)&oparg, 10);
> +		      oparg--;
> +		      USE_IMM (n, s);
>  		      break;
> -		    case 'm':
> -		      USE_BITS (OP_MASK_SPACEMIT_IME_VMASK,
> -				OP_SH_SPACEMIT_IME_VMASK);
> +		    case 'n':
> +		    case 'b':
> +		      used_bits |= ENCODE_SPACEMIT_IME_UIMM2_SP (-1U);
> +		      break;
> +		    case 'w':
> +		    case 'x':
> +		      USE_BITS (OP_MASK_SPACEMIT_IME_WI,
> +				OP_SH_SPACEMIT_IME_WI);
>  		      break;
>  		    default:
>  		      goto unknown_validate_operand;
> -		    }
> -		  break;
> -		case 'u': /* Integer immediate, 'XpuN@S' ...
> -			     N-bit unsigned immediate at bit S.  */
> -		  n = strtol (oparg + 1, (char **)&oparg, 10);
> -		  if (*oparg != '@')
> -		    goto unknown_validate_operand;
> -		  s = strtol (oparg + 1, (char **)&oparg, 10);
> -		  oparg--;
> -		  USE_IMM (n, s);
> -		  break;
> -		case 'n':
> -		case 'b':
> -		  used_bits |= ENCODE_SPACEMIT_IME_UIMM2_SP (-1U);
> -		  break;
> -		case 'w':
> -		case 'x':
> -		  USE_BITS (OP_MASK_SPACEMIT_IME_WI, OP_SH_SPACEMIT_IME_WI);
> -		  break;
> -		default:
> -		  goto unknown_validate_operand;
> -		}
> -	      break;
> +		  }
> +		break;
> +	      }
>  	    default:
>  	      goto unknown_validate_operand;
>  	    }
> @@ -4309,144 +4313,149 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
>  		  break;
>  
>  		case 'p': /* Vendor-specific (SpacemiT) operands.  */
> -		  size_t n;
> -		  size_t s;
> -		  switch (*++oparg)
> -		    {
> -		    case 'V':
> -		      switch (*++oparg)
> -			{
> -			case 'd':
> -			  if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
> -			    break;
> -			  if ((regno & 0x1) != 0)
> +		  {
> +		    size_t n;
> +		    size_t s;
> +		    switch (*++oparg)
> +		      {
> +			case 'V':
> +			  switch (*++oparg)
>  			    {
> -			      error.msg
> -				= _("illegal operands (vd must be even)");
> -			      error.missing_ext = NULL;
> -			      goto out;
> +			      case 'd':
> +				if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
> +				  break;
> +				if ((regno & 0x1) != 0)
> +				  {
> +				    error.msg
> +				      = _("illegal operands (vd must be even)");
> +				    error.missing_ext = NULL;
> +				    goto out;
> +				  }
> +				INSERT_OPERAND (SPACEMIT_IME_VD, *ip, regno>>1);
> +				continue;
> +			      case 's':
> +				if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
> +				  break;
> +				if ((regno & 0x1) != 0)
> +				  {
> +				    error.msg
> +				      = _("illegal operands "
> +					  "(vs1 must be even)");
> +				    error.missing_ext = NULL;
> +				    goto out;
> +				  }
> +				INSERT_OPERAND (SPACEMIT_IME_VS1,
> +						*ip, regno>>1);
> +				continue;
> +			      case 'm':
> +				if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
> +				  break;
> +				if (regno >= 2)
> +				  {
> +				    error.msg
> +				      = _("illegal operands "
> +					  "(mask must be v0/v1)");
> +				    error.missing_ext = NULL;
> +				    goto out;
> +				  }
> +				INSERT_OPERAND (SPACEMIT_IME_VMASK, *ip, regno);
> +				continue;
> +			      default:
> +				goto unknown_riscv_ip_operand;
>  			    }
> -			  INSERT_OPERAND (SPACEMIT_IME_VD, *ip, regno>>1);
> +			  break;
> +			case 'u': /* Integer immediate, 'XpuN@S' ...
> +				     N-bit unsigned immediate at bit S.  */
> +			  n = strtol (oparg + 1, (char **)&oparg, 10);
> +			  if (*oparg != '@')
> +			    goto unknown_riscv_ip_operand;
> +			  s = strtol (oparg + 1, (char **)&oparg, 10);
> +			  oparg--;
> +			  my_getExpression (imm_expr, asarg, force_reloc);
> +			  check_absolute_expr (ip, imm_expr, false);
> +			  if (!VALIDATE_U_IMM (imm_expr->X_add_number, n))
> +			    as_bad (_("improper immediate value (%"PRIu64")"),
> +				    imm_expr->X_add_number);
> +			  INSERT_IMM (n, s, *ip, imm_expr->X_add_number);
> +			  imm_expr->X_op = O_absent;
> +			  asarg = expr_parse_end;
>  			  continue;
> -			case 's':
> -			  if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
> +			case 'n': /* Xpn: stride (0-1), paired with Xpx.  */
> +			  my_getExpression (imm_expr, asarg, force_reloc);
> +			  check_absolute_expr (ip, imm_expr, false);
> +			  if (imm_expr->X_add_number < 0
> +			      || imm_expr->X_add_number >= 2)
>  			    break;
> -			  if ((regno & 0x1) != 0)
> +			  ip->insn_opcode
> +			    |= ENCODE_SPACEMIT_IME_UIMM2_SP
> +				 (imm_expr->X_add_number);
> +			  imm_expr->X_op = O_absent;
> +			  asarg = expr_parse_end;
> +			  continue;
> +			case 'b': /* Xpb: stride (0-3), paired with Xpw.  */
> +			  my_getExpression (imm_expr, asarg, force_reloc);
> +			  check_absolute_expr (ip, imm_expr, false);
> +			  if (imm_expr->X_add_number < 0
> +			      || imm_expr->X_add_number >= 4)
>  			    {
> -			      error.msg
> -				= _("illegal operands (vs1 must be even)");
> -			      error.missing_ext = NULL;
> -			      goto out;
> +			      as_bad (_("bad value for stride field,"
> +					" value must be 0..3"));
> +			      break;
>  			    }
> -			  INSERT_OPERAND (SPACEMIT_IME_VS1, *ip, regno>>1);
> +			  ip->insn_opcode
> +			    |= ENCODE_SPACEMIT_IME_UIMM2_SP
> +				 (imm_expr->X_add_number);
> +			  imm_expr->X_op = O_absent;
> +			  asarg = expr_parse_end;
>  			  continue;
> -			case 'm':
> -			  if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
> -			    break;
> -			  if (regno >= 2)
> +			case 'w':
> +			  /* Xpw: optional data-width suffix, i8 only (WI=3).
> +			     If omitted, defaults to i8.  */
> +			  if (*asarg == ',')
>  			    {
> -			      error.msg
> -				= _("illegal operands (mask must be v0/v1)");
> -			      error.missing_ext = NULL;
> -			      goto out;
> +			      if (strcmp (asarg + 1, "i8") != 0)
> +				{
> +				  error.msg
> +				    = _("illegal operands (invalid data type)");
> +				  error.missing_ext = NULL;
> +				  goto out;
> +				}
> +			      asarg += 3;
>  			    }
> -			  INSERT_OPERAND (SPACEMIT_IME_VMASK, *ip, regno);
> +			  else if (*asarg != '\0')
> +			    goto unknown_riscv_ip_operand;
> +			  regno = 3;
> +			  INSERT_OPERAND (SPACEMIT_IME_WI, *ip, regno);
>  			  continue;
> -			default:
> -			  goto unknown_riscv_ip_operand;
> -			}
> -		      break;
> -		    case 'u': /* Integer immediate, 'XpuN@S' ...
> -				 N-bit unsigned immediate at bit S.  */
> -		      n = strtol (oparg + 1, (char **)&oparg, 10);
> -		      if (*oparg != '@')
> -			goto unknown_riscv_ip_operand;
> -		      s = strtol (oparg + 1, (char **)&oparg, 10);
> -		      oparg--;
> -		      my_getExpression (imm_expr, asarg, force_reloc);
> -		      check_absolute_expr (ip, imm_expr, false);
> -		      if (!VALIDATE_U_IMM (imm_expr->X_add_number, n))
> -			as_bad (_("improper immediate value (%"PRIu64")"),
> -				imm_expr->X_add_number);
> -		      INSERT_IMM (n, s, *ip, imm_expr->X_add_number);
> -		      imm_expr->X_op = O_absent;
> -		      asarg = expr_parse_end;
> -		      continue;
> -		    case 'n': /* Xpn: stride (0-1), paired with Xpx.  */
> -		      my_getExpression (imm_expr, asarg, force_reloc);
> -		      check_absolute_expr (ip, imm_expr, false);
> -		      if (imm_expr->X_add_number < 0
> -			  || imm_expr->X_add_number >= 2)
> -			break;
> -		      ip->insn_opcode
> -			|= ENCODE_SPACEMIT_IME_UIMM2_SP
> -			     (imm_expr->X_add_number);
> -		      imm_expr->X_op = O_absent;
> -		      asarg = expr_parse_end;
> -		      continue;
> -		    case 'b': /* Xpb: stride (0-3), paired with Xpw.  */
> -		      my_getExpression (imm_expr, asarg, force_reloc);
> -		      check_absolute_expr (ip, imm_expr, false);
> -		      if (imm_expr->X_add_number < 0
> -			  || imm_expr->X_add_number >= 4)
> -			{
> -			  as_bad (_("bad value for stride field,"
> -				    " value must be 0..3"));
> -			  break;
> -			}
> -		      ip->insn_opcode
> -			|= ENCODE_SPACEMIT_IME_UIMM2_SP
> -			     (imm_expr->X_add_number);
> -		      imm_expr->X_op = O_absent;
> -		      asarg = expr_parse_end;
> -		      continue;
> -		    case 'w':
> -		      /* Xpw: optional data-width suffix, i8 only (WI=3).
> -			 If omitted, defaults to i8.  */
> -		      if (*asarg == ',')
> -			{
> -			  if (strcmp (asarg + 1, "i8") != 0)
> +			case 'x':
> +			  /* Xpx: optional data-width suffix, i4 or i8 (WI=2/3).
> +			     If omitted, defaults to i8.  */
> +			  if (*asarg == ',')
>  			    {
> -			      error.msg
> -				= _("illegal operands (invalid data type)");
> -			      error.missing_ext = NULL;
> -			      goto out;
> +			      if (strcmp (asarg + 1, "i4") == 0)
> +				regno = 2;
> +			      else if (strcmp (asarg + 1, "i8") == 0)
> +				regno = 3;
> +			      else
> +				{
> +				  error.msg
> +				    = _("illegal operands (invalid data type)");
> +				  error.missing_ext = NULL;
> +				  goto out;
> +				}
> +			      asarg += 3;
>  			    }
> -			  asarg += 3;
> -			}
> -		      else if (*asarg != '\0')
> -			goto unknown_riscv_ip_operand;
> -		      regno = 3;
> -		      INSERT_OPERAND (SPACEMIT_IME_WI, *ip, regno);
> -		      continue;
> -		    case 'x':
> -		      /* Xpx: optional data-width suffix, i4 or i8 (WI=2/3).
> -			 If omitted, defaults to i8.  */
> -		      if (*asarg == ',')
> -			{
> -			  if (strcmp (asarg + 1, "i4") == 0)
> -			    regno = 2;
> -			  else if (strcmp (asarg + 1, "i8") == 0)
> -			    regno = 3;
> +			  else if (*asarg != '\0')
> +			    goto unknown_riscv_ip_operand;
>  			  else
> -			    {
> -			      error.msg
> -				= _("illegal operands (invalid data type)");
> -			      error.missing_ext = NULL;
> -			      goto out;
> -			    }
> -			  asarg += 3;
> -			}
> -		      else if (*asarg != '\0')
> -			goto unknown_riscv_ip_operand;
> -		      else
> -			regno = 3;
> -		      INSERT_OPERAND (SPACEMIT_IME_WI, *ip, regno);
> -		      continue;
> -		    default:
> -		      goto unknown_riscv_ip_operand;
> -		    }
> -		  break;
> +			    regno = 3;
> +			  INSERT_OPERAND (SPACEMIT_IME_WI, *ip, regno);
> +			  continue;
> +			default:
> +			  goto unknown_riscv_ip_operand;
> +		      }
> +		    break;
> +		  }
>  		default:
>  		  goto unknown_riscv_ip_operand;
>  		}
> diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> index ca0d9bfd121..edb9ce04778 100644
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -924,14 +924,18 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
>  		  switch (*++oparg)
>  		    {
>  		    case 'd':
> -		      unsigned vd = EXTRACT_OPERAND (SPACEMIT_IME_VD, l) * 2;
> -		      print (info->stream, dis_style_register, "%s",
> -			     riscv_vecr_names_numeric[vd]);
> +		      {
> +			unsigned vd = EXTRACT_OPERAND (SPACEMIT_IME_VD, l) * 2;
> +			print (info->stream, dis_style_register, "%s",
> +			       riscv_vecr_names_numeric[vd]);
> +		      }
>  		      break;
>  		    case 's':
> -		      unsigned vs = EXTRACT_OPERAND (SPACEMIT_IME_VS1, l) * 2;
> -		      print (info->stream, dis_style_register, "%s",
> -			     riscv_vecr_names_numeric[vs]);
> +		      {
> +			unsigned vs = EXTRACT_OPERAND (SPACEMIT_IME_VS1, l) * 2;
> +			print (info->stream, dis_style_register, "%s",
> +			       riscv_vecr_names_numeric[vs]);
> +		      }
>  		      break;
>  		    case 'm':
>  		      {
> -- 
> 2.34.1


From schwab@suse.de  Tue Jun 23 10:32:53 2026
From: schwab@suse.de (Andreas Schwab)
Date: Tue, 23 Jun 2026 12:32:53 +0200
Subject: [PATCH v6 1/2] RISC-V: Add SpacemiT vendor extension xsmtvdot
In-Reply-To: <2f3139c1-cdbb-4452-b575-dc06740d9198@qti.qualcomm.com> (Jeffrey
 Law via Binutils's message of "Tue, 23 Jun 2026 01:59:41 +0000")
References: <e066f12c-6e51-4d5f-ad2a-2955e99b5008@iscas.ac.cn>
 <20260525082008.1219171-1-zhuangqiubin@linux.spacemit.com>
 <20260525082008.1219171-2-zhuangqiubin@linux.spacemit.com>
 <67c08e17-5721-4a68-afe0-11bb5e766605@qti.qualcomm.com>
 <20260622211400.GM30116@gnu.wildebeest.org>
 <2f3139c1-cdbb-4452-b575-dc06740d9198@qti.qualcomm.com>
Message-ID: <mvmtsqtzgve.fsf@suse.de>

On Jun 23 2026, Jeffrey Law via Binutils wrote:

> Ugh.? gcc-8 era.? ?I don't recall the default C language dialect used in 
> that era, but definitely old and crusty.

You need at least C23 for that, or gcc >= 11 with GNU extensions.

-- 
Andreas Schwab, SUSE Labs, schwab@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE  1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."

From jbeulich@suse.com  Tue Jun 23 10:54:25 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Tue, 23 Jun 2026 12:54:25 +0200
Subject: [PATCH] RISC-V: Fix build with GCC-8
In-Reply-To: <20260623095221.1792011-1-zhuangqiubin@linux.spacemit.com>
References: <20260623095221.1792011-1-zhuangqiubin@linux.spacemit.com>
Message-ID: <8858c007-5891-452a-93a3-07f239b237f5@suse.com>

On 23.06.2026 11:52, Mark Zhuang wrote:
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -1791,49 +1791,53 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
>  		}
>  		break;
>  	    case 'p': /* Vendor-specific (SpacemiT) operands.  */
> -	      size_t n;
> -	      size_t s;
> -	      switch (*++oparg)
> -		{
> -		case 'V':
> -		  switch (*++oparg)
> -		    {
> -		    case 'd':
> -		      USE_BITS (OP_MASK_SPACEMIT_IME_VD, OP_SH_SPACEMIT_IME_VD);
> +	      {
> +		size_t n;
> +		size_t s;
> +		switch (*++oparg)
> +		  {
> +		    case 'V':
> +		      switch (*++oparg)
> +			{
> +			  case 'd':
> +			    USE_BITS (OP_MASK_SPACEMIT_IME_VD,
> +				      OP_SH_SPACEMIT_IME_VD);
> +			    break;
> +			  case 's':
> +			    USE_BITS (OP_MASK_SPACEMIT_IME_VS1,
> +				      OP_SH_SPACEMIT_IME_VS1);
> +			    break;
> +			  case 'm':
> +			    USE_BITS (OP_MASK_SPACEMIT_IME_VMASK,
> +				      OP_SH_SPACEMIT_IME_VMASK);
> +			    break;
> +			  default:
> +			    goto unknown_validate_operand;
> +			}
>  		      break;
> -		    case 's':
> -		      USE_BITS (OP_MASK_SPACEMIT_IME_VS1,
> -				OP_SH_SPACEMIT_IME_VS1);
> +		    case 'u': /* Integer immediate, 'XpuN@S' ...
> +				 N-bit unsigned immediate at bit S.  */
> +		      n = strtol (oparg + 1, (char **)&oparg, 10);
> +		      if (*oparg != '@')
> +			goto unknown_validate_operand;
> +		      s = strtol (oparg + 1, (char **)&oparg, 10);
> +		      oparg--;
> +		      USE_IMM (n, s);
>  		      break;

Both variables are used only here, if I'm not mistaken. Can't we go with
less churn and less excessively deep indentation by limiting the change
to just this inner case block (moving the decls here)?

> @@ -4309,144 +4313,149 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
>  		  break;
>  
>  		case 'p': /* Vendor-specific (SpacemiT) operands.  */
> -		  size_t n;
> -		  size_t s;
> -		  switch (*++oparg)
> -		    {
> -		    case 'V':
> -		      switch (*++oparg)
> -			{
> -			case 'd':
> -			  if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
> -			    break;
> -			  if ((regno & 0x1) != 0)
> +		  {
> +		    size_t n;
> +		    size_t s;
> +		    switch (*++oparg)
> +		      {
> +			case 'V':
> +			  switch (*++oparg)
>  			    {
> -			      error.msg
> -				= _("illegal operands (vd must be even)");
> -			      error.missing_ext = NULL;
> -			      goto out;
> +			      case 'd':
> +				if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
> +				  break;
> +				if ((regno & 0x1) != 0)
> +				  {
> +				    error.msg
> +				      = _("illegal operands (vd must be even)");
> +				    error.missing_ext = NULL;
> +				    goto out;
> +				  }
> +				INSERT_OPERAND (SPACEMIT_IME_VD, *ip, regno>>1);
> +				continue;
> +			      case 's':
> +				if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
> +				  break;
> +				if ((regno & 0x1) != 0)
> +				  {
> +				    error.msg
> +				      = _("illegal operands "
> +					  "(vs1 must be even)");
> +				    error.missing_ext = NULL;
> +				    goto out;
> +				  }
> +				INSERT_OPERAND (SPACEMIT_IME_VS1,
> +						*ip, regno>>1);
> +				continue;
> +			      case 'm':
> +				if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
> +				  break;
> +				if (regno >= 2)
> +				  {
> +				    error.msg
> +				      = _("illegal operands "
> +					  "(mask must be v0/v1)");
> +				    error.missing_ext = NULL;
> +				    goto out;
> +				  }
> +				INSERT_OPERAND (SPACEMIT_IME_VMASK, *ip, regno);
> +				continue;
> +			      default:
> +				goto unknown_riscv_ip_operand;
>  			    }
> -			  INSERT_OPERAND (SPACEMIT_IME_VD, *ip, regno>>1);
> +			  break;
> +			case 'u': /* Integer immediate, 'XpuN@S' ...
> +				     N-bit unsigned immediate at bit S.  */
> +			  n = strtol (oparg + 1, (char **)&oparg, 10);
> +			  if (*oparg != '@')
> +			    goto unknown_riscv_ip_operand;
> +			  s = strtol (oparg + 1, (char **)&oparg, 10);
> +			  oparg--;
> +			  my_getExpression (imm_expr, asarg, force_reloc);
> +			  check_absolute_expr (ip, imm_expr, false);
> +			  if (!VALIDATE_U_IMM (imm_expr->X_add_number, n))
> +			    as_bad (_("improper immediate value (%"PRIu64")"),
> +				    imm_expr->X_add_number);
> +			  INSERT_IMM (n, s, *ip, imm_expr->X_add_number);
> +			  imm_expr->X_op = O_absent;
> +			  asarg = expr_parse_end;
>  			  continue;

Similarly here then.

Jan

From avr@gjlay.de  Tue Jun 23 12:24:47 2026
From: avr@gjlay.de (Georg-Johann Lay)
Date: Tue, 23 Jun 2026 14:24:47 +0200
Subject: [patch, avr, applied] PR17107: Add more .gnu.linkonce section
 patterns to avr.sc
Message-ID: <28685df3-ca1e-4659-8271-baedb8937bfe@gjlay.de>

Added rules for .gnu.linkonce.t* and .gnu.linkone.b* to avr.sc.

Applied to trunk as obvious.

Johann

--

AVR: PR17107 - Add more .gnu.linkonce to avr.sc

This patch adds pattern rules for .gnu.linkonce.t* and .gnu.linkone.b*
to the .text resp. .bss output sections.  Though that's probably
not needed any more since G++ is using COMDAT today.
.gnu.linkonce.d* for .data and .gnu.linkone.r* for .rodata are
already there.

	PR ld/17107
ld/
	* scripttempl/avr.sc (.bss) [RELOCATING]: Add *(.gnu.linkonce.b*).
	(.text) [RELOCATING]: Add *(.gnu.linkonce.t*).
-------------- next part --------------
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From zhuangqiubin@linux.spacemit.com  Tue Jun 23 12:47:57 2026
From: zhuangqiubin@linux.spacemit.com (Mark Zhuang)
Date: Tue, 23 Jun 2026 20:47:57 +0800
Subject: [PATCH v2 0/1] RISC-V: Fix build with GCC-8
In-Reply-To: <8858c007-5891-452a-93a3-07f239b237f5@suse.com>
References: <8858c007-5891-452a-93a3-07f239b237f5@suse.com>
Message-ID: <20260623124758.2412307-1-zhuangqiubin@linux.spacemit.com>

From: Mark Zhuang <mark.zhuang@spacemit.com>

Thanks, Jan ? indeed, this makes the code much more readable.

Changes in v2:
- move the decls to inner case block

Mark Zhuang (1):
  RISC-V: Fix build with GCC-8

 gas/config/tc-riscv.c | 54 +++++++++++++++++++++++--------------------
 opcodes/riscv-dis.c   | 16 ++++++++-----
 2 files changed, 39 insertions(+), 31 deletions(-)

-- 
2.34.1


From zhuangqiubin@linux.spacemit.com  Tue Jun 23 12:47:58 2026
From: zhuangqiubin@linux.spacemit.com (Mark Zhuang)
Date: Tue, 23 Jun 2026 20:47:58 +0800
Subject: [PATCH v2 1/1] RISC-V: Fix build with GCC-8
In-Reply-To: <20260623124758.2412307-1-zhuangqiubin@linux.spacemit.com>
References: <8858c007-5891-452a-93a3-07f239b237f5@suse.com>
 <20260623124758.2412307-1-zhuangqiubin@linux.spacemit.com>
Message-ID: <20260623124758.2412307-2-zhuangqiubin@linux.spacemit.com>

From: Mark Zhuang <mark.zhuang@spacemit.com>

GCC 8.5.0 rejects a declaration right after a case label.
Add braces to fix it.
---
 gas/config/tc-riscv.c | 54 +++++++++++++++++++++++--------------------
 opcodes/riscv-dis.c   | 16 ++++++++-----
 2 files changed, 39 insertions(+), 31 deletions(-)

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 5ffa2ef1f1d..cb639b48fe0 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1791,8 +1791,6 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 		}
 		break;
 	    case 'p': /* Vendor-specific (SpacemiT) operands.  */
-	      size_t n;
-	      size_t s;
 	      switch (*++oparg)
 		{
 		case 'V':
@@ -1815,13 +1813,17 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 		  break;
 		case 'u': /* Integer immediate, 'XpuN@S' ...
 			     N-bit unsigned immediate at bit S.  */
-		  n = strtol (oparg + 1, (char **)&oparg, 10);
-		  if (*oparg != '@')
-		    goto unknown_validate_operand;
-		  s = strtol (oparg + 1, (char **)&oparg, 10);
-		  oparg--;
-		  USE_IMM (n, s);
-		  break;
+		  {
+		    size_t n;
+		    size_t s;
+		    n = strtol (oparg + 1, (char **)&oparg, 10);
+		    if (*oparg != '@')
+		      goto unknown_validate_operand;
+		    s = strtol (oparg + 1, (char **)&oparg, 10);
+		    oparg--;
+		    USE_IMM (n, s);
+		    break;
+		  }
 		case 'n':
 		case 'b':
 		  used_bits |= ENCODE_SPACEMIT_IME_UIMM2_SP (-1U);
@@ -4309,8 +4311,6 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		  break;
 
 		case 'p': /* Vendor-specific (SpacemiT) operands.  */
-		  size_t n;
-		  size_t s;
 		  switch (*++oparg)
 		    {
 		    case 'V':
@@ -4358,20 +4358,24 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		      break;
 		    case 'u': /* Integer immediate, 'XpuN@S' ...
 				 N-bit unsigned immediate at bit S.  */
-		      n = strtol (oparg + 1, (char **)&oparg, 10);
-		      if (*oparg != '@')
-			goto unknown_riscv_ip_operand;
-		      s = strtol (oparg + 1, (char **)&oparg, 10);
-		      oparg--;
-		      my_getExpression (imm_expr, asarg, force_reloc);
-		      check_absolute_expr (ip, imm_expr, false);
-		      if (!VALIDATE_U_IMM (imm_expr->X_add_number, n))
-			as_bad (_("improper immediate value (%"PRIu64")"),
-				imm_expr->X_add_number);
-		      INSERT_IMM (n, s, *ip, imm_expr->X_add_number);
-		      imm_expr->X_op = O_absent;
-		      asarg = expr_parse_end;
-		      continue;
+		      {
+			size_t n;
+			size_t s;
+			n = strtol (oparg + 1, (char **)&oparg, 10);
+			if (*oparg != '@')
+			  goto unknown_riscv_ip_operand;
+			s = strtol (oparg + 1, (char **)&oparg, 10);
+			oparg--;
+			my_getExpression (imm_expr, asarg, force_reloc);
+			check_absolute_expr (ip, imm_expr, false);
+			if (!VALIDATE_U_IMM (imm_expr->X_add_number, n))
+			  as_bad (_("improper immediate value (%"PRIu64")"),
+				  imm_expr->X_add_number);
+			INSERT_IMM (n, s, *ip, imm_expr->X_add_number);
+			imm_expr->X_op = O_absent;
+			asarg = expr_parse_end;
+			continue;
+		      }
 		    case 'n': /* Xpn: stride (0-1), paired with Xpx.  */
 		      my_getExpression (imm_expr, asarg, force_reloc);
 		      check_absolute_expr (ip, imm_expr, false);
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index ca0d9bfd121..edb9ce04778 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -924,14 +924,18 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 		  switch (*++oparg)
 		    {
 		    case 'd':
-		      unsigned vd = EXTRACT_OPERAND (SPACEMIT_IME_VD, l) * 2;
-		      print (info->stream, dis_style_register, "%s",
-			     riscv_vecr_names_numeric[vd]);
+		      {
+			unsigned vd = EXTRACT_OPERAND (SPACEMIT_IME_VD, l) * 2;
+			print (info->stream, dis_style_register, "%s",
+			       riscv_vecr_names_numeric[vd]);
+		      }
 		      break;
 		    case 's':
-		      unsigned vs = EXTRACT_OPERAND (SPACEMIT_IME_VS1, l) * 2;
-		      print (info->stream, dis_style_register, "%s",
-			     riscv_vecr_names_numeric[vs]);
+		      {
+			unsigned vs = EXTRACT_OPERAND (SPACEMIT_IME_VS1, l) * 2;
+			print (info->stream, dis_style_register, "%s",
+			       riscv_vecr_names_numeric[vs]);
+		      }
 		      break;
 		    case 'm':
 		      {
-- 
2.34.1


From jbeulich@suse.com  Tue Jun 23 12:53:22 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Tue, 23 Jun 2026 14:53:22 +0200
Subject: [PATCH v2 1/1] RISC-V: Fix build with GCC-8
In-Reply-To: <20260623124758.2412307-2-zhuangqiubin@linux.spacemit.com>
References: <8858c007-5891-452a-93a3-07f239b237f5@suse.com>
 <20260623124758.2412307-1-zhuangqiubin@linux.spacemit.com>
 <20260623124758.2412307-2-zhuangqiubin@linux.spacemit.com>
Message-ID: <f2abf263-4730-4ccd-af87-e3de2289b35c@suse.com>

On 23.06.2026 14:47, Mark Zhuang wrote:
> From: Mark Zhuang <mark.zhuang@spacemit.com>
> 
> GCC 8.5.0 rejects a declaration right after a case label.
> Add braces to fix it.
> ---
>  gas/config/tc-riscv.c | 54 +++++++++++++++++++++++--------------------
>  opcodes/riscv-dis.c   | 16 ++++++++-----
>  2 files changed, 39 insertions(+), 31 deletions(-)

Thanks for making the adjustments. I'll give RISC-V maintainers until the
end of the week to approve this. Otherwise I'll take care of it. In that
case, however, I'd likely ...

> @@ -1815,13 +1813,17 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
>  		  break;
>  		case 'u': /* Integer immediate, 'XpuN@S' ...
>  			     N-bit unsigned immediate at bit S.  */
> -		  n = strtol (oparg + 1, (char **)&oparg, 10);
> -		  if (*oparg != '@')
> -		    goto unknown_validate_operand;
> -		  s = strtol (oparg + 1, (char **)&oparg, 10);
> -		  oparg--;
> -		  USE_IMM (n, s);
> -		  break;
> +		  {
> +		    size_t n;
> +		    size_t s;
> +		    n = strtol (oparg + 1, (char **)&oparg, 10);

... make this the initializer of n and ...

> +		    if (*oparg != '@')
> +		      goto unknown_validate_operand;
> +		    s = strtol (oparg + 1, (char **)&oparg, 10);

... declare s only here (with initializer).

> +		    oparg--;
> +		    USE_IMM (n, s);
> +		    break;
> +		  }
>  		case 'n':
>  		case 'b':
>  		  used_bits |= ENCODE_SPACEMIT_IME_UIMM2_SP (-1U);
> @@ -4309,8 +4311,6 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
>  		  break;
>  
>  		case 'p': /* Vendor-specific (SpacemiT) operands.  */
> -		  size_t n;
> -		  size_t s;
>  		  switch (*++oparg)
>  		    {
>  		    case 'V':
> @@ -4358,20 +4358,24 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
>  		      break;
>  		    case 'u': /* Integer immediate, 'XpuN@S' ...
>  				 N-bit unsigned immediate at bit S.  */
> -		      n = strtol (oparg + 1, (char **)&oparg, 10);
> -		      if (*oparg != '@')
> -			goto unknown_riscv_ip_operand;
> -		      s = strtol (oparg + 1, (char **)&oparg, 10);
> -		      oparg--;
> -		      my_getExpression (imm_expr, asarg, force_reloc);
> -		      check_absolute_expr (ip, imm_expr, false);
> -		      if (!VALIDATE_U_IMM (imm_expr->X_add_number, n))
> -			as_bad (_("improper immediate value (%"PRIu64")"),
> -				imm_expr->X_add_number);
> -		      INSERT_IMM (n, s, *ip, imm_expr->X_add_number);
> -		      imm_expr->X_op = O_absent;
> -		      asarg = expr_parse_end;
> -		      continue;
> +		      {
> +			size_t n;
> +			size_t s;
> +			n = strtol (oparg + 1, (char **)&oparg, 10);
> +			if (*oparg != '@')
> +			  goto unknown_riscv_ip_operand;
> +			s = strtol (oparg + 1, (char **)&oparg, 10);

Again same here then. In both cases of course only if you don't
vehemently object.

Jan

From jbeulich@suse.com  Tue Jun 23 12:55:06 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Tue, 23 Jun 2026 14:55:06 +0200
Subject: [PATCH v2 1/1] RISC-V: Fix build with GCC-8
In-Reply-To: <f2abf263-4730-4ccd-af87-e3de2289b35c@suse.com>
References: <8858c007-5891-452a-93a3-07f239b237f5@suse.com>
 <20260623124758.2412307-1-zhuangqiubin@linux.spacemit.com>
 <20260623124758.2412307-2-zhuangqiubin@linux.spacemit.com>
 <f2abf263-4730-4ccd-af87-e3de2289b35c@suse.com>
Message-ID: <dcbaeb58-41a9-42de-817a-e19fd36bf553@suse.com>

On 23.06.2026 14:53, Jan Beulich wrote:
> On 23.06.2026 14:47, Mark Zhuang wrote:
>> From: Mark Zhuang <mark.zhuang@spacemit.com>
>>
>> GCC 8.5.0 rejects a declaration right after a case label.
>> Add braces to fix it.
>> ---
>>  gas/config/tc-riscv.c | 54 +++++++++++++++++++++++--------------------
>>  opcodes/riscv-dis.c   | 16 ++++++++-----
>>  2 files changed, 39 insertions(+), 31 deletions(-)
> 
> Thanks for making the adjustments. I'll give RISC-V maintainers until the
> end of the week to approve this.

Noticing only now: To catch their attention, it helps greatly if you actually
Cc them on patch submissions. I've added the missing Cc-s here.

Jan

From matz@suse.de  Tue Jun 23 13:14:46 2026
From: matz@suse.de (Michael Matz)
Date: Tue, 23 Jun 2026 15:14:46 +0200 (CEST)
Subject: [PATCH 2/3] gas/ELF: warn upon non-default visibility of local
 symbols
In-Reply-To: <67a1182c-e7d0-40ad-98ec-9b49c1d28410@suse.com>
References: <bcd40b22-b90f-4334-8ab4-e8afeea2a6a9@suse.com>
 <193f86ed-f34b-4da8-9eac-68005830d369@suse.com>
 <e6007e9e-2cb7-4635-a974-5f753b212133@arm.com>
 <1397563c-32ca-4343-9587-99c197dd4029@suse.com>
 <b4ec2334-1821-4780-9876-f8a12d20dc4b@suse.com>
 <CAMe9rOoqhA+o278P+bPWOvHSxENbjyiN=o+Goep-6MUt2--_-w@mail.gmail.com>
 <e43bc9d8-260e-46f1-9afc-c52eacd4ac60@suse.com>
 <CAMe9rOpVyKapj7FrC1k+MZRqO1J+FZhq-HnfarzpuPedkJ0snA@mail.gmail.com>
 <67a1182c-e7d0-40ad-98ec-9b49c1d28410@suse.com>
Message-ID: <17f9a3cc-7994-ad25-692b-e3e9441ff481@suse.de>

Hello,

On Tue, 23 Jun 2026, Jan Beulich wrote:

> ... this actual reference, arguably the compiler should also emit a .global
> directive. It generally gets away without doing so because referenced symbols
> which aren't otherwise defined are implicitly global (which, seeing how
> other assemblers behave, can be argued as being a bug, but apparently is
> "traditional behavior" on UNIXes).

An assembler isn't a structured programming language environment, I think 
the quotes are undeserved: its entirely sensible that an assembler that 
sees a symbol reference for a symbol that at file-end is still undefined 
assumes that such symbol then obviously must come from a different file 
and hence be global (binding).

> > ELF spec
> > doesn't forbid the hidden visibility on a local symbol.  It is just a no-op.
> 
> You did read
> 
> "The spec explicitly precludes STB_LOCAL together with STV_PROTECTED (and,
>  implicity, STV_HIDDEN or STV_INTERNAL), so we better wouldn't entirely
>  silently write out symbols violating this."
> 
> in the patch description, didn't you? If you think that's wrong, did you
> then not consider going back to the ELF spec to find what exactly is said
> there: "A symbol with STB_LOCAL binding may not have STV_PROTECTED
> visibility." And then for STV_HIDDEN: "Such a symbol is necessarily
> protected." I.e. what is said for STV_PROTECTED applies to STV_HIDDEN (and
> STV_INTERNAL) as well, at least according to my interpretation of that
> wording.

I think that's a misinterpretation.  "a symbol is protected" is different 
from "a symbol has STV_PROTECTED visibility".  The former is defined in 
the section for the latter: 

  A symbol defined in the current component is protected if it is visible 
  in other components but cannot be preempted. Any reference to such a 
  symbol from within the defining component must be resolved to the 
  definition in that component, even if there is a definition in another 
  component that would interpose by the default rules. A symbol with 
  STB_LOCAL binding will not have STV_PROTECTED visibility.

and _that definition_ is invoked by STV_HIDDEN:

  A symbol defined in the current component is hidden if its name is not 
  visible to other components. Such a symbol is necessarily protected.

IMHO it's clear that a symbol hence "can be protected" without having its 
visibility be STV_PROTECTED.  Namely when it is STV_HIDDEN: its then 
protected _and_ hidden (which is of course redundant, because hidden 
implies protected, but as we are word-smithing, lets be precise).

That a STB_LOCAL symbol cannot have STV_PROTECTED visibility doesn't 
transfer to STV_HIDDEN from this wording, and from nothing else either, 
conceptually binding and visibility are orthogonal concepts and this 
specific disallowance for the STB_LOCAL+STV_PROTECTED combination is ... 
well, specific.  That is the wart, not that STB_LOCAL+STV_HIDDEN was 
"forgotten" to be disallowed.


Ciao,
Michael.

From jbeulich@suse.com  Tue Jun 23 13:26:44 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Tue, 23 Jun 2026 15:26:44 +0200
Subject: [PATCH 2/3] gas/ELF: warn upon non-default visibility of local
 symbols
In-Reply-To: <17f9a3cc-7994-ad25-692b-e3e9441ff481@suse.de>
References: <bcd40b22-b90f-4334-8ab4-e8afeea2a6a9@suse.com>
 <193f86ed-f34b-4da8-9eac-68005830d369@suse.com>
 <e6007e9e-2cb7-4635-a974-5f753b212133@arm.com>
 <1397563c-32ca-4343-9587-99c197dd4029@suse.com>
 <b4ec2334-1821-4780-9876-f8a12d20dc4b@suse.com>
 <CAMe9rOoqhA+o278P+bPWOvHSxENbjyiN=o+Goep-6MUt2--_-w@mail.gmail.com>
 <e43bc9d8-260e-46f1-9afc-c52eacd4ac60@suse.com>
 <CAMe9rOpVyKapj7FrC1k+MZRqO1J+FZhq-HnfarzpuPedkJ0snA@mail.gmail.com>
 <67a1182c-e7d0-40ad-98ec-9b49c1d28410@suse.com>
 <17f9a3cc-7994-ad25-692b-e3e9441ff481@suse.de>
Message-ID: <3d038b03-8b0f-46c5-a663-d1eacebaa6c9@suse.com>

On 23.06.2026 15:14, Michael Matz wrote:
> On Tue, 23 Jun 2026, Jan Beulich wrote:
> 
>> ... this actual reference, arguably the compiler should also emit a .global
>> directive. It generally gets away without doing so because referenced symbols
>> which aren't otherwise defined are implicitly global (which, seeing how
>> other assemblers behave, can be argued as being a bug, but apparently is
>> "traditional behavior" on UNIXes).
> 
> An assembler isn't a structured programming language environment, I think 
> the quotes are undeserved: its entirely sensible that an assembler that 
> sees a symbol reference for a symbol that at file-end is still undefined 
> assumes that such symbol then obviously must come from a different file 
> and hence be global (binding).

Well, I grew up (in the DOS / Windows / OS/2 world) with assemblers behaving
differently.

>>> ELF spec
>>> doesn't forbid the hidden visibility on a local symbol.  It is just a no-op.
>>
>> You did read
>>
>> "The spec explicitly precludes STB_LOCAL together with STV_PROTECTED (and,
>>  implicity, STV_HIDDEN or STV_INTERNAL), so we better wouldn't entirely
>>  silently write out symbols violating this."
>>
>> in the patch description, didn't you? If you think that's wrong, did you
>> then not consider going back to the ELF spec to find what exactly is said
>> there: "A symbol with STB_LOCAL binding may not have STV_PROTECTED
>> visibility." And then for STV_HIDDEN: "Such a symbol is necessarily
>> protected." I.e. what is said for STV_PROTECTED applies to STV_HIDDEN (and
>> STV_INTERNAL) as well, at least according to my interpretation of that
>> wording.
> 
> I think that's a misinterpretation.  "a symbol is protected" is different 
> from "a symbol has STV_PROTECTED visibility".  The former is defined in 
> the section for the latter: 
> 
>   A symbol defined in the current component is protected if it is visible 
>   in other components but cannot be preempted. Any reference to such a 
>   symbol from within the defining component must be resolved to the 
>   definition in that component, even if there is a definition in another 
>   component that would interpose by the default rules. A symbol with 
>   STB_LOCAL binding will not have STV_PROTECTED visibility.
> 
> and _that definition_ is invoked by STV_HIDDEN:
> 
>   A symbol defined in the current component is hidden if its name is not 
>   visible to other components. Such a symbol is necessarily protected.
> 
> IMHO it's clear that a symbol hence "can be protected" without having its 
> visibility be STV_PROTECTED.  Namely when it is STV_HIDDEN: its then 
> protected _and_ hidden (which is of course redundant, because hidden 
> implies protected, but as we are word-smithing, lets be precise).
> 
> That a STB_LOCAL symbol cannot have STV_PROTECTED visibility doesn't 
> transfer to STV_HIDDEN from this wording, and from nothing else either, 
> conceptually binding and visibility are orthogonal concepts and this 
> specific disallowance for the STB_LOCAL+STV_PROTECTED combination is ... 
> well, specific.  That is the wart, not that STB_LOCAL+STV_HIDDEN was 
> "forgotten" to be disallowed.

IOW what you're suggesting as interpretation is that while STV_PROTECTED
and STB_LOCAL may not combine, the visibility-wise more restricting
STV_HIDDEN may combine with STB_LOCAL? Make no sense to me, I'm afraid.
(And would also make the implementation harder.)

Jan

From zhuangqiubin@linux.spacemit.com  Tue Jun 23 13:35:08 2026
From: zhuangqiubin@linux.spacemit.com (Mark Zhuang)
Date: Tue, 23 Jun 2026 21:35:08 +0800
Subject: [PATCH v3] RISC-V: Fix build with GCC-8
In-Reply-To: <f2abf263-4730-4ccd-af87-e3de2289b35c@suse.com>
References: <f2abf263-4730-4ccd-af87-e3de2289b35c@suse.com>
Message-ID: <20260623133508.2896582-1-zhuangqiubin@linux.spacemit.com>

From: Mark Zhuang <mark.zhuang@spacemit.com>

GCC 8.5.0 rejects a declaration right after a case label.
Add braces to fix it.
---
 gas/config/tc-riscv.c | 50 +++++++++++++++++++++----------------------
 opcodes/riscv-dis.c   | 16 ++++++++------
 2 files changed, 35 insertions(+), 31 deletions(-)

diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 5ffa2ef1f1d..f11dabb7c95 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1791,8 +1791,6 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 		}
 		break;
 	    case 'p': /* Vendor-specific (SpacemiT) operands.  */
-	      size_t n;
-	      size_t s;
 	      switch (*++oparg)
 		{
 		case 'V':
@@ -1815,13 +1813,15 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 		  break;
 		case 'u': /* Integer immediate, 'XpuN@S' ...
 			     N-bit unsigned immediate at bit S.  */
-		  n = strtol (oparg + 1, (char **)&oparg, 10);
-		  if (*oparg != '@')
-		    goto unknown_validate_operand;
-		  s = strtol (oparg + 1, (char **)&oparg, 10);
-		  oparg--;
-		  USE_IMM (n, s);
-		  break;
+		  {
+		    size_t n = strtol (oparg + 1, (char **)&oparg, 10);
+		    if (*oparg != '@')
+		      goto unknown_validate_operand;
+		    size_t s = strtol (oparg + 1, (char **)&oparg, 10);
+		    oparg--;
+		    USE_IMM (n, s);
+		    break;
+		  }
 		case 'n':
 		case 'b':
 		  used_bits |= ENCODE_SPACEMIT_IME_UIMM2_SP (-1U);
@@ -4309,8 +4309,6 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		  break;
 
 		case 'p': /* Vendor-specific (SpacemiT) operands.  */
-		  size_t n;
-		  size_t s;
 		  switch (*++oparg)
 		    {
 		    case 'V':
@@ -4358,20 +4356,22 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		      break;
 		    case 'u': /* Integer immediate, 'XpuN@S' ...
 				 N-bit unsigned immediate at bit S.  */
-		      n = strtol (oparg + 1, (char **)&oparg, 10);
-		      if (*oparg != '@')
-			goto unknown_riscv_ip_operand;
-		      s = strtol (oparg + 1, (char **)&oparg, 10);
-		      oparg--;
-		      my_getExpression (imm_expr, asarg, force_reloc);
-		      check_absolute_expr (ip, imm_expr, false);
-		      if (!VALIDATE_U_IMM (imm_expr->X_add_number, n))
-			as_bad (_("improper immediate value (%"PRIu64")"),
-				imm_expr->X_add_number);
-		      INSERT_IMM (n, s, *ip, imm_expr->X_add_number);
-		      imm_expr->X_op = O_absent;
-		      asarg = expr_parse_end;
-		      continue;
+		      {
+			size_t n = strtol (oparg + 1, (char **)&oparg, 10);
+			if (*oparg != '@')
+			  goto unknown_riscv_ip_operand;
+			size_t s = strtol (oparg + 1, (char **)&oparg, 10);
+			oparg--;
+			my_getExpression (imm_expr, asarg, force_reloc);
+			check_absolute_expr (ip, imm_expr, false);
+			if (!VALIDATE_U_IMM (imm_expr->X_add_number, n))
+			  as_bad (_("improper immediate value (%"PRIu64")"),
+				  imm_expr->X_add_number);
+			INSERT_IMM (n, s, *ip, imm_expr->X_add_number);
+			imm_expr->X_op = O_absent;
+			asarg = expr_parse_end;
+			continue;
+		      }
 		    case 'n': /* Xpn: stride (0-1), paired with Xpx.  */
 		      my_getExpression (imm_expr, asarg, force_reloc);
 		      check_absolute_expr (ip, imm_expr, false);
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index ca0d9bfd121..edb9ce04778 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -924,14 +924,18 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 		  switch (*++oparg)
 		    {
 		    case 'd':
-		      unsigned vd = EXTRACT_OPERAND (SPACEMIT_IME_VD, l) * 2;
-		      print (info->stream, dis_style_register, "%s",
-			     riscv_vecr_names_numeric[vd]);
+		      {
+			unsigned vd = EXTRACT_OPERAND (SPACEMIT_IME_VD, l) * 2;
+			print (info->stream, dis_style_register, "%s",
+			       riscv_vecr_names_numeric[vd]);
+		      }
 		      break;
 		    case 's':
-		      unsigned vs = EXTRACT_OPERAND (SPACEMIT_IME_VS1, l) * 2;
-		      print (info->stream, dis_style_register, "%s",
-			     riscv_vecr_names_numeric[vs]);
+		      {
+			unsigned vs = EXTRACT_OPERAND (SPACEMIT_IME_VS1, l) * 2;
+			print (info->stream, dis_style_register, "%s",
+			       riscv_vecr_names_numeric[vs]);
+		      }
 		      break;
 		    case 'm':
 		      {
-- 
2.34.1


From xry111@xry111.site  Tue Jun 23 13:38:09 2026
From: xry111@xry111.site (Xi Ruoyao)
Date: Tue, 23 Jun 2026 21:38:09 +0800
Subject: Does commit c2bf7de1 fix CVE-2026-3441 and CVE-2026-3442?
In-Reply-To: <DS0PR11MB7901E161B4E1B75EFA3655BBE0EF2@DS0PR11MB7901.namprd11.prod.outlook.com>
References: <DS0PR11MB7901E161B4E1B75EFA3655BBE0EF2@DS0PR11MB7901.namprd11.prod.outlook.com>
Message-ID: <a7160ac10cacaec3641d314d70fae5795a00a63d.camel@xry111.site>

On Mon, 2026-06-22 at 11:06 +0000, Dora, Sunil Kumar via Binutils wrote:
> 
> Hi,
> 
> 
> I'm?looking at commit c2bf7de1eb7
> ("xcofflink buffer overflows") for a downstream update and want to tag
> it correctly.
> 
> 
> The diff fixes two out-of-bounds reads in xcoff_link_add_symbols: the
> x_scnlen index check and the r_symndx check. That looks like it
> matches Red Hat'sCVE-2026-3441?and CVE-2026-3442?(bugs 2443826 and
> 2443828).


Per the binutils security policy:

    The tools assume that the input is to be trusted.  If this is not 
    the case then the tools should be run inside a sandboxed
    environment to ensure that they do not compromise the host
    environment.  In the context of this document then a bug which
    relies upon using untrusted input, eg a crafted binary, must show
    that the result is a breach of trust boundary, e.g. being able to
    execute code as another user or root, or escape from the sandboxed
    environment.  If this is not possible then the bug will not be
    considered a security bug.

Thus a buffer overflow handling a crafted input file is not considered a
security issue, so it should not have been assigned the CVE in the first
place.


-- 
Xi Ruoyao <xry111@xry111.site>

From matz@suse.de  Tue Jun 23 13:54:12 2026
From: matz@suse.de (Michael Matz)
Date: Tue, 23 Jun 2026 15:54:12 +0200 (CEST)
Subject: [PATCH 2/3] gas/ELF: warn upon non-default visibility of local
 symbols
In-Reply-To: <3d038b03-8b0f-46c5-a663-d1eacebaa6c9@suse.com>
References: <bcd40b22-b90f-4334-8ab4-e8afeea2a6a9@suse.com>
 <193f86ed-f34b-4da8-9eac-68005830d369@suse.com>
 <e6007e9e-2cb7-4635-a974-5f753b212133@arm.com>
 <1397563c-32ca-4343-9587-99c197dd4029@suse.com>
 <b4ec2334-1821-4780-9876-f8a12d20dc4b@suse.com>
 <CAMe9rOoqhA+o278P+bPWOvHSxENbjyiN=o+Goep-6MUt2--_-w@mail.gmail.com>
 <e43bc9d8-260e-46f1-9afc-c52eacd4ac60@suse.com>
 <CAMe9rOpVyKapj7FrC1k+MZRqO1J+FZhq-HnfarzpuPedkJ0snA@mail.gmail.com>
 <67a1182c-e7d0-40ad-98ec-9b49c1d28410@suse.com>
 <17f9a3cc-7994-ad25-692b-e3e9441ff481@suse.de>
 <3d038b03-8b0f-46c5-a663-d1eacebaa6c9@suse.com>
Message-ID: <f16445c4-e3e4-72ca-f5ee-9b5ede84de3d@suse.de>

Hello,

On Tue, 23 Jun 2026, Jan Beulich wrote:

> > I think that's a misinterpretation.  "a symbol is protected" is different 
> > from "a symbol has STV_PROTECTED visibility".  The former is defined in 
> > the section for the latter: 
> > 
> >   A symbol defined in the current component is protected if it is visible 
> >   in other components but cannot be preempted. Any reference to such a 
> >   symbol from within the defining component must be resolved to the 
> >   definition in that component, even if there is a definition in another 
> >   component that would interpose by the default rules. A symbol with 
> >   STB_LOCAL binding will not have STV_PROTECTED visibility.
> > 
> > and _that definition_ is invoked by STV_HIDDEN:
> > 
> >   A symbol defined in the current component is hidden if its name is not 
> >   visible to other components. Such a symbol is necessarily protected.
> > 
> > IMHO it's clear that a symbol hence "can be protected" without having its 
> > visibility be STV_PROTECTED.  Namely when it is STV_HIDDEN: its then 
> > protected _and_ hidden (which is of course redundant, because hidden 
> > implies protected, but as we are word-smithing, lets be precise).
> > 
> > That a STB_LOCAL symbol cannot have STV_PROTECTED visibility doesn't 
> > transfer to STV_HIDDEN from this wording, and from nothing else either, 
> > conceptually binding and visibility are orthogonal concepts and this 
> > specific disallowance for the STB_LOCAL+STV_PROTECTED combination is ... 
> > well, specific.  That is the wart, not that STB_LOCAL+STV_HIDDEN was 
> > "forgotten" to be disallowed.
> 
> IOW what you're suggesting as interpretation is that while STV_PROTECTED 
> and STB_LOCAL may not combine, the visibility-wise more restricting 
> STV_HIDDEN may combine with STB_LOCAL?

Yes.

> Make no sense to me, I'm afraid. 

That may be, and I agree that creating such situation willingly would 
be suspect.  But as we just saw, such combinations might be created 
by an unlucky reality.  And again: binding and visiblity are _orthogonal_.  
One is for link-editing, the other for runtime linking.  In principle all 
combinations are "okay" (if questionable), and have obvious 
implementations.  But it's only that specific combination 
STB_LOCAL+STV_PROTECTED that is explicitely made ill-formed in the spec 
(despite it being also obviously implementable).  So, sure, warning on 
that combination can be done on the grounds of following the spec.  But no 
other combination is so spelled out, so there's no basis for trying to 
disallow them.

> (And would also make the implementation harder.)

If a warning is too costly to implement, then it shouldn't be there.
Though it seems surprising that checking for "is_local && is_protected" 
should be materially more difficult than for "is_local && !is_default_vis".
(I haven't looked at the concrete patch, though).


Ciao,
Michael.

From jbeulich@suse.com  Tue Jun 23 14:22:54 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Tue, 23 Jun 2026 16:22:54 +0200
Subject: [PATCH 2/3] gas/ELF: warn upon non-default visibility of local
 symbols
In-Reply-To: <f16445c4-e3e4-72ca-f5ee-9b5ede84de3d@suse.de>
References: <bcd40b22-b90f-4334-8ab4-e8afeea2a6a9@suse.com>
 <193f86ed-f34b-4da8-9eac-68005830d369@suse.com>
 <e6007e9e-2cb7-4635-a974-5f753b212133@arm.com>
 <1397563c-32ca-4343-9587-99c197dd4029@suse.com>
 <b4ec2334-1821-4780-9876-f8a12d20dc4b@suse.com>
 <CAMe9rOoqhA+o278P+bPWOvHSxENbjyiN=o+Goep-6MUt2--_-w@mail.gmail.com>
 <e43bc9d8-260e-46f1-9afc-c52eacd4ac60@suse.com>
 <CAMe9rOpVyKapj7FrC1k+MZRqO1J+FZhq-HnfarzpuPedkJ0snA@mail.gmail.com>
 <67a1182c-e7d0-40ad-98ec-9b49c1d28410@suse.com>
 <17f9a3cc-7994-ad25-692b-e3e9441ff481@suse.de>
 <3d038b03-8b0f-46c5-a663-d1eacebaa6c9@suse.com>
 <f16445c4-e3e4-72ca-f5ee-9b5ede84de3d@suse.de>
Message-ID: <888a0461-7875-411b-bde9-dd7960e1536e@suse.com>

On 23.06.2026 15:54, Michael Matz wrote:
> On Tue, 23 Jun 2026, Jan Beulich wrote:
>>> I think that's a misinterpretation.  "a symbol is protected" is different 
>>> from "a symbol has STV_PROTECTED visibility".  The former is defined in 
>>> the section for the latter: 
>>>
>>>   A symbol defined in the current component is protected if it is visible 
>>>   in other components but cannot be preempted. Any reference to such a 
>>>   symbol from within the defining component must be resolved to the 
>>>   definition in that component, even if there is a definition in another 
>>>   component that would interpose by the default rules. A symbol with 
>>>   STB_LOCAL binding will not have STV_PROTECTED visibility.
>>>
>>> and _that definition_ is invoked by STV_HIDDEN:
>>>
>>>   A symbol defined in the current component is hidden if its name is not 
>>>   visible to other components. Such a symbol is necessarily protected.
>>>
>>> IMHO it's clear that a symbol hence "can be protected" without having its 
>>> visibility be STV_PROTECTED.  Namely when it is STV_HIDDEN: its then 
>>> protected _and_ hidden (which is of course redundant, because hidden 
>>> implies protected, but as we are word-smithing, lets be precise).
>>>
>>> That a STB_LOCAL symbol cannot have STV_PROTECTED visibility doesn't 
>>> transfer to STV_HIDDEN from this wording, and from nothing else either, 
>>> conceptually binding and visibility are orthogonal concepts and this 
>>> specific disallowance for the STB_LOCAL+STV_PROTECTED combination is ... 
>>> well, specific.  That is the wart, not that STB_LOCAL+STV_HIDDEN was 
>>> "forgotten" to be disallowed.
>>
>> IOW what you're suggesting as interpretation is that while STV_PROTECTED 
>> and STB_LOCAL may not combine, the visibility-wise more restricting 
>> STV_HIDDEN may combine with STB_LOCAL?
> 
> Yes.
> 
>> Make no sense to me, I'm afraid. 
> 
> That may be, and I agree that creating such situation willingly would 
> be suspect.  But as we just saw, such combinations might be created 
> by an unlucky reality.

Because of shortcomings in the tools used. I bet if there had been a
warning, the approach chosen would have been a different one. (The
approach chosen also isn't portable to non-ELF targets.)

>  And again: binding and visiblity are _orthogonal_.  
> One is for link-editing, the other for runtime linking.  In principle all 
> combinations are "okay" (if questionable), and have obvious 
> implementations.  But it's only that specific combination 
> STB_LOCAL+STV_PROTECTED that is explicitely made ill-formed in the spec 
> (despite it being also obviously implementable).  So, sure, warning on 
> that combination can be done on the grounds of following the spec.  But no 
> other combination is so spelled out, so there's no basis for trying to 
> disallow them.

As with many things in specs, what's spelled out and what's implied
is a matter of interpretation. As I think follows from earlier replies,
I can see that there is room for interpretation here, and hence mine
may not match what was intended. Yet we won't know for any other
interpretation either, seeing the state the ELF spec is in.

If others are in favor of following your interpretation, then I'm not
going to stand in the way. But as of now it's not going to be me to
make a patch to that effect. I simply couldn't write a description
for it in good faith.

>> (And would also make the implementation harder.)
> 
> If a warning is too costly to implement, then it shouldn't be there.
> Though it seems surprising that checking for "is_local && is_protected" 
> should be materially more difficult than for "is_local && !is_default_vis".
> (I haven't looked at the concrete patch, though).

Well, you may be right and it's not really more complex.

Jan

From avr@gjlay.de  Tue Jun 23 17:14:38 2026
From: avr@gjlay.de (Georg-Johann Lay)
Date: Tue, 23 Jun 2026 19:14:38 +0200
Subject: [patch, avr] Overhaul section AVR modifiers and document gs()
Message-ID: <d3e8a57c-da3b-47fb-a0d0-4114fc222803@gjlay.de>

This patch overhauls the "AVR modifiers" section of the GAS manual.
It adds documentation for gs() that is still missing to this day.

Ok for trunk?

Johann

--

AVR: PR13129 - Overhaul section AVR modifiers and document gs().

This patch adds documentation for gs() to the GAS manual,
and it overhauls the "AVR modifiers" section.

	PR gas/13129
gas/
	* doc/c-avr.texi (AVR modifiers): Overhaul and add gs()
	documentation.

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From peter0x44@disroot.org  Tue Jun 23 21:38:03 2026
From: peter0x44@disroot.org (Peter Damianov)
Date: Tue, 23 Jun 2026 17:38:03 -0400
Subject: [PATCH v3 0/4] PE-COFF weak external fixes
In-Reply-To: <20260622033926.220317-1-peter0x44@disroot.org>
References: <20260622033926.220317-1-peter0x44@disroot.org>
Message-ID: <cover.1782245474.git.peter0x44@disroot.org>

After I sent my last patch series, I was reminded of:
https://gcc.gnu.org/PR124263 and
https://github.com/skeeto/w64devkit/issues/393 , which looked 
related and like this patch could fix them. It turned out to be
a related issue but with archives instead. This submission adds
an extra patch to fix that reported issue and adds extra tests
covering that issue. I tested that it also fixes the upstream GCC
issue.

Changes from v2:

  * Add a new BFD archive fix for GCC PR124263.  PE weak externals are
    canonicalized as undefined BFD symbols even when their aux entry
    names a real fallback definition.  The archive map now advertises
    those public weak names, while still excluding weak declarations
    whose fallback is the absolute-zero null symbol.
  * Avoid extracting the same archive member again during repeated
    archive searches once a PE weak external resolves through a real
    fallback definition.
  * Extend the testsuite patch with an archive regression test covering
    the positive real-fallback armap case, the negative null-fallback
    declaration case, and the duplicate archive search case.

The first two patches are unchanged from v2.  The new archive fix is
patch 3, and the testsuite patch is modified with extra tests exercising
the fix.

Peter Damianov (4):
  PE-COFF: Fix weak external symbol resolution when strong undef is seen
    first
  PE-COFF: Prefer weak external with defined fallback over null fallback
  bfd: Handle PE weak externals with real fallbacks in archives
  ld/testsuite: Add comprehensive PE COFF weak external tests

 bfd/archive.c                                 |  22 ++-
 bfd/coff-bfd.c                                |  47 +++++
 bfd/coff-bfd.h                                |   3 +
 bfd/cofflink.c                                | 183 ++++++++++++++++--
 ld/testsuite/ld-pe/pe-compile.exp             | 167 ++++++++++++++++
 .../ld-pe/weak-ext-add1-weak-chained.c        |  13 ++
 ld/testsuite/ld-pe/weak-ext-add2.c            |   8 +
 ld/testsuite/ld-pe/weak-ext-dummy.c           |   5 +
 ld/testsuite/ld-pe/weak-ext-expected1.c       |   1 +
 .../ld-pe/weak-ext-expected3-add1-weak.c      |   9 +
 ld/testsuite/ld-pe/weak-ext-expected3.c       |   1 +
 ld/testsuite/ld-pe/weak-ext-expected5.c       |   1 +
 ld/testsuite/ld-pe/weak-ext-main-weak-def.c   |  26 +++
 ld/testsuite/ld-pe/weak-ext-main-weak.c       |  22 +++
 ld/testsuite/ld-pe/weak-ext-main.c            |  21 ++
 15 files changed, 510 insertions(+), 19 deletions(-)
 create mode 100644 ld/testsuite/ld-pe/weak-ext-add1-weak-chained.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-add2.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-dummy.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-expected1.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-expected3-add1-weak.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-expected3.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-expected5.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-main-weak-def.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-main-weak.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-main.c

-- 
2.54.0


From peter0x44@disroot.org  Tue Jun 23 21:38:04 2026
From: peter0x44@disroot.org (Peter Damianov)
Date: Tue, 23 Jun 2026 17:38:04 -0400
Subject: [PATCH v3 1/4] PE-COFF: Fix weak external symbol resolution when
 strong undef is seen first
In-Reply-To: <cover.1782245474.git.peter0x44@disroot.org>
References: <cover.1782245474.git.peter0x44@disroot.org>
Message-ID: <4eed3fce357c58ef817e3cf3003735233ff85268.1782245474.git.peter0x44@disroot.org>

When linking PE-COFF objects, a weak external symbol (C_NT_WEAK with an
aux record specifying a fallback alias) may fail to resolve if a strong
undefined reference to the same symbol is encountered before the weak
definition.  This causes "undefined reference" errors for symbols like
operator new or personality routines that GCC emits as weak externals
with a fallback to a default implementation.

There are two problems:

1. In coff_link_add_symbols, when the generic linker resolves a weak
   undefined against an existing strong undefined (NOACT in the action
   table), the COFF-specific symbol_class and aux record were not stored
   because the existing hash entry already had non-null class/type from
   the first (strong) object file.

2. In _bfd_coff_generic_relocate_section, the weak alias fallback only
   triggered for bfd_link_hash_undefweak symbols.  When a strong undef
   is seen first, the hash type stays bfd_link_hash_undefined (the
   generic linker does not downgrade it), so the fallback was skipped.

Fix by extending the condition in coff_link_add_symbols to also update
symbol_class and aux when the incoming symbol is a PE weak external
with aux and the existing hash is still undefined.  Also extend the
relocation handler to resolve the weak alias fallback for
bfd_link_hash_undefined symbols that carry C_NT_WEAK class and have
an aux record.

bfd/
        * cofflink.c (coff_link_add_symbols): Also store symbol_class
        and aux record when a PE weak external with aux meets an
        existing undefined hash entry.
        (_bfd_coff_generic_relocate_section): Also resolve weak alias
        fallback for undefined symbols with C_NT_WEAK class and aux.
---
 bfd/cofflink.c | 55 ++++++++++++++++++++++++++++++++++++++------------
 1 file changed, 42 insertions(+), 13 deletions(-)

diff --git a/bfd/cofflink.c b/bfd/cofflink.c
index e5c8a987d69..eba0fad4c3f 100644
--- a/bfd/cofflink.c
+++ b/bfd/cofflink.c
@@ -477,13 +477,20 @@ coff_link_add_symbols (bfd *abfd,
 	      /* If we don't have any symbol information currently in
 		 the hash table, or if we are looking at a symbol
 		 definition, then update the symbol class and type in
-		 the hash table.  */
+		 the hash table.  Also update if the incoming symbol is
+		 a weak external with an aux record (PE COFF weak alias)
+		 and the existing symbol is still undefined, so the
+		 fallback alias information is preserved for the linker's
+		 relocation resolution.  */
 	      if (((*sym_hash)->symbol_class == C_NULL
 		   && (*sym_hash)->type == T_NULL)
 		  || sym.n_scnum != 0
 		  || (sym.n_value != 0
 		      && (*sym_hash)->root.type != bfd_link_hash_defined
-		      && (*sym_hash)->root.type != bfd_link_hash_defweak))
+		      && (*sym_hash)->root.type != bfd_link_hash_defweak)
+		  || (IS_WEAK_EXTERNAL (abfd, sym)
+		      && sym.n_numaux > 0
+		      && (*sym_hash)->root.type == bfd_link_hash_undefined))
 		{
 		  (*sym_hash)->symbol_class = sym.n_sclass;
 		  if (sym.n_type != T_NULL)
@@ -521,10 +528,9 @@ coff_link_add_symbols (bfd *abfd,
 		      union internal_auxent *iaux;
 
 		      (*sym_hash)->numaux = sym.n_numaux;
-		      alloc = ((union internal_auxent *)
-			       bfd_hash_allocate (&info->hash->table,
-						  (sym.n_numaux
-						   * sizeof (*alloc))));
+		      alloc = bfd_hash_allocate (&info->hash->table,
+						 (sym.n_numaux
+						  * sizeof (*alloc)));
 		      if (alloc == NULL)
 			goto error_return;
 		      for (i = 0, eaux = esym + symesz, iaux = alloc;
@@ -3065,14 +3071,24 @@ _bfd_coff_generic_relocate_section (bfd *output_bfd,
 		     + sec->output_offset);
 	    }
 
-	  else if (h->root.type == bfd_link_hash_undefweak)
+	  else if (h->root.type == bfd_link_hash_undefweak
+		   || (h->root.type == bfd_link_hash_undefined
+		       && h->symbol_class == C_NT_WEAK && h->numaux == 1))
 	    {
-	      if (h->symbol_class == C_NT_WEAK && h->numaux == 1)
+	      /* Weak undefined symbol: either GNU weak (no aux record) or
+		 PE COFF weak external (C_NT_WEAK with aux record).
+		 Also handles strong undefined symbols that carry PE weak
+		 external metadata (when strong undef is seen before weak def,
+		 the hash type stays bfd_link_hash_undefined but we preserve
+		 the weak external class and aux for later resolution).  */
+
+	      bool is_pe_weak = (h->symbol_class == C_NT_WEAK && h->numaux == 1);
+
+	      if (is_pe_weak)
 		{
-		  /* See _Microsoft Portable Executable and Common Object
+		  /* PE COFF weak external: resolve via fallback alias.
+		     See _Microsoft Portable Executable and Common Object
 		     File Format Specification_, section 5.5.3.
-		     Note that weak symbols without aux records are a GNU
-		     extension.
 		     FIXME: All weak externals are treated as having
 		     characteristic IMAGE_WEAK_EXTERN_SEARCH_NOLIBRARY (1).
 		     These behave as per SVR4 ABI:  A library member
@@ -3081,24 +3097,37 @@ _bfd_coff_generic_relocate_section (bfd *output_bfd,
 		     See also linker.c: generic_link_check_archive_element. */
 		  struct coff_link_hash_entry *h2 = NULL;
 		  unsigned long symndx2 = h->aux->x_sym.x_tagndx.u32;
+
 		  if (symndx2 < obj_raw_syment_count (h->auxbfd))
 		    h2 = obj_coff_sym_hashes (h->auxbfd)[symndx2];
 
 		  if (!h2 || h2->root.type == bfd_link_hash_undefined)
 		    {
+		      /* Fallback alias not found or still undefined.
+			 Resolve to NULL.  */
 		      sec = bfd_abs_section_ptr;
 		      val = 0;
 		    }
 		  else
 		    {
+		      /* Use fallback alias target.  */
 		      sec = h2->root.u.def.section;
 		      val = h2->root.u.def.value
 			+ sec->output_section->vma + sec->output_offset;
 		    }
 		}
 	      else
-		/* This is a GNU extension.  */
-		val = 0;
+		{
+		  /* GNU extension: ELF-style weak symbol in COFF without
+		     PE weak external aux record.  COFF has no native support
+		     for weak symbols (unlike ELF where they're part of the
+		     format).  PE COFF adds them via C_NT_WEAK storage class
+		     with an aux record pointing to a fallback symbol.  GNU ld
+		     extends this by allowing __attribute__((weak)) in COFF
+		     objects even without the PE aux structure, treating them
+		     like ELF weak symbols: resolve to NULL if not defined.  */
+		  val = 0;
+		}
 	    }
 
 	  else if (! bfd_link_relocatable (info))
-- 
2.54.0


From peter0x44@disroot.org  Tue Jun 23 21:38:05 2026
From: peter0x44@disroot.org (Peter Damianov)
Date: Tue, 23 Jun 2026 17:38:05 -0400
Subject: [PATCH v3 2/4] PE-COFF: Prefer weak external with defined fallback
 over null fallback
In-Reply-To: <cover.1782245474.git.peter0x44@disroot.org>
References: <cover.1782245474.git.peter0x44@disroot.org>
Message-ID: <b7f7a2605551f171c1af3b4e90f0c492bce28614.1782245474.git.peter0x44@disroot.org>

When two PE COFF weak externals for the same symbol are linked (both
C_NT_WEAK with aux records), the generic linker takes no action on the
second one (NOACT: weak undef meets existing weak undef).  This means
the first file's fallback alias always wins regardless of whether it
points to a real definition or to NULL.

This causes a problem when a weak declaration (fallback = NULL,
i.e. "resolve to NULL if nothing provides it") is linked before a
weak definition (fallback = actual function body).  The symbol resolves
to address 0 at runtime, causing a crash when called.

Fix this by comparing the fallback targets when two weak externals
meet: if the incoming weak external's fallback resolves to a defined
symbol and the existing one does not (or points to NULL),
update the aux record to use the better fallback.

This matches the behavior of lld after:
  https://github.com/llvm/llvm-project/commit/7ca5698b4c3698d06065e0941df7f23d72913d23

bfd/
	* cofflink.c (coff_link_add_symbols): When two PE COFF weak
	externals meet, prefer the one whose fallback alias resolves
	to a defined symbol.
---
 bfd/cofflink.c | 82 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 82 insertions(+)

diff --git a/bfd/cofflink.c b/bfd/cofflink.c
index eba0fad4c3f..75b4c47eacf 100644
--- a/bfd/cofflink.c
+++ b/bfd/cofflink.c
@@ -542,6 +542,88 @@ coff_link_add_symbols (bfd *abfd,
 		      (*sym_hash)->aux = alloc;
 		    }
 		}
+
+	      /* When two PE COFF weak externals meet (both with aux
+		 records specifying fallback aliases), prefer the one
+		 whose fallback resolves to a defined symbol over one
+		 whose fallback is undefined or NULL.  This
+		 handles the case where a weak declaration (with a
+		 fallback of NULL) is seen before a weak
+		 definition (with a fallback of the actual function
+		 body).  */
+	      else if (IS_WEAK_EXTERNAL (abfd, sym)
+		       && sym.n_numaux > 0
+		       && (*sym_hash)->root.type == bfd_link_hash_undefweak
+		       && (*sym_hash)->symbol_class == C_NT_WEAK
+		       && (*sym_hash)->numaux == 1)
+		{
+		  /* Parse the incoming aux to get the fallback tagndx.  */
+		  union internal_auxent new_aux;
+		  unsigned long new_tagndx;
+		  unsigned long old_tagndx;
+		  struct coff_link_hash_entry *h2_new = NULL;
+		  struct coff_link_hash_entry *h2_old = NULL;
+		  bool new_is_real_fallback;
+		  bool old_is_unresolved_fallback;
+
+		  bfd_coff_swap_aux_in (abfd, esym + symesz, sym.n_type,
+					sym.n_sclass, 0, sym.n_numaux,
+					&new_aux);
+		  new_tagndx = new_aux.x_sym.x_tagndx.u32;
+
+		  if (new_tagndx < obj_raw_syment_count (abfd))
+		    h2_new = obj_coff_sym_hashes (abfd)[new_tagndx];
+
+		  old_tagndx = (*sym_hash)->aux->x_sym.x_tagndx.u32;
+		  if (old_tagndx
+		      < obj_raw_syment_count ((*sym_hash)->auxbfd))
+		    h2_old = obj_coff_sym_hashes
+		      ((*sym_hash)->auxbfd)[old_tagndx];
+
+		  /* Update if the new fallback is a real definition but
+		     the old one is not.  A weak declaration with no
+		     definition uses the COFF null symbol as its fallback.
+		     In the hash table that fallback looks like a defined
+		     absolute symbol with value zero, so treat that case as
+		     unresolved here.  */
+		  new_is_real_fallback
+		    = (h2_new != NULL
+		       && (h2_new->root.type == bfd_link_hash_defined
+			   || h2_new->root.type == bfd_link_hash_defweak)
+		       && !(bfd_is_abs_section (h2_new->root.u.def.section)
+			    && h2_new->root.u.def.value == 0));
+		  old_is_unresolved_fallback
+		    = (h2_old == NULL
+		       || h2_old->root.type == bfd_link_hash_undefined
+		       || h2_old->root.type == bfd_link_hash_undefweak
+		       || (h2_old->root.type == bfd_link_hash_defined
+			   && bfd_is_abs_section (h2_old->root.u.def.section)
+			   && h2_old->root.u.def.value == 0));
+
+		  if (new_is_real_fallback && old_is_unresolved_fallback)
+		    {
+		      union internal_auxent *alloc;
+		      unsigned int i;
+		      bfd_byte *eaux;
+		      union internal_auxent *iaux;
+
+		      (*sym_hash)->symbol_class = sym.n_sclass;
+		      (*sym_hash)->auxbfd = abfd;
+		      (*sym_hash)->numaux = sym.n_numaux;
+		      alloc = bfd_hash_allocate (&info->hash->table,
+						 (sym.n_numaux
+						  * sizeof (*alloc)));
+		      if (alloc == NULL)
+			goto error_return;
+		      for (i = 0, eaux = esym + symesz, iaux = alloc;
+			   i < sym.n_numaux;
+			   i++, eaux += symesz, iaux++)
+			bfd_coff_swap_aux_in (abfd, eaux, sym.n_type,
+					      sym.n_sclass, (int) i,
+					      sym.n_numaux, iaux);
+		      (*sym_hash)->aux = alloc;
+		    }
+		}
 	    }
 
 	  if (classification == COFF_SYMBOL_PE_SECTION
-- 
2.54.0


From peter0x44@disroot.org  Tue Jun 23 21:38:06 2026
From: peter0x44@disroot.org (Peter Damianov)
Date: Tue, 23 Jun 2026 17:38:06 -0400
Subject: [PATCH v3 3/4] bfd: Handle PE weak externals with real fallbacks in
 archives
In-Reply-To: <cover.1782245474.git.peter0x44@disroot.org>
References: <cover.1782245474.git.peter0x44@disroot.org>
Message-ID: <8292b88c6b7216d8eedba27e1d1bd6a8c7da34d5.1782245474.git.peter0x44@disroot.org>

PE weak externals are canonicalized as undefined BFD symbols, even
when their auxiliary entry names a real fallback definition in the same
object.  Archive map generation therefore skipped the public weak name,
so a strong undefined reference to that name could not extract the
archive member.

Include such PE weak externals in the archive map, but only when the
fallback is a real definition rather than the absolute-zero null symbol
used for weak declarations with no fallback.  Also avoid extracting an
archive member again during repeated archive searches once the weak
external resolves through a defined fallback.

Fixes: https://gcc.gnu.org/PR124263

bfd/

	* archive.c: Include coff-bfd.h.
	(_bfd_compute_and_push_armap): Include PE weak externals in
	the archive map when their fallback is a real definition.
	* coff-bfd.c (bfd_coff_pe_weak_external_has_real_fallback): New
	function.
	* coff-bfd.h (bfd_coff_pe_weak_external_has_real_fallback):
	Declare.
	* cofflink.c (coff_link_hash_pe_weak_external_has_real_fallback):
	New function.
	(coff_link_check_archive_element): Avoid extracting an archive
	member again for a PE weak external whose real fallback is
	already defined.
---
 bfd/archive.c  | 22 ++++++++++++++++------
 bfd/coff-bfd.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
 bfd/coff-bfd.h |  3 +++
 bfd/cofflink.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 112 insertions(+), 6 deletions(-)

diff --git a/bfd/archive.c b/bfd/archive.c
index 44030eb3d63..1bff31b6d09 100644
--- a/bfd/archive.c
+++ b/bfd/archive.c
@@ -142,6 +142,7 @@ SUBSECTION
 #include "filenames.h"
 #include "bfdlink.h"
 #include "plugin.h"
+#include "coff-bfd.h"
 
 #ifndef errno
 extern int errno;
@@ -2535,12 +2536,21 @@ _bfd_compute_and_push_armap
 		  flagword flags = (syms[src_count])->flags;
 		  asection *sec = syms[src_count]->section;
 
-		  if (((flags & (BSF_GLOBAL
-				 | BSF_WEAK
-				 | BSF_INDIRECT
-				 | BSF_GNU_UNIQUE)) != 0
-		       || bfd_is_com_section (sec))
-		      && ! bfd_is_und_section (sec))
+		  /* Include symbols that normally define archive-map entries, plus
+		     PE weak externals whose fallback is a real definition.  Those
+		     weak externals are canonicalized as undefined symbols, but their
+		     public names can still be needed to pull the archive member.  */
+		  bool include_in_armap
+		    = ((((flags & (BSF_GLOBAL
+			      | BSF_WEAK
+			      | BSF_INDIRECT
+			      | BSF_GNU_UNIQUE)) != 0
+			 || bfd_is_com_section (sec))
+			&& ! bfd_is_und_section (sec))
+		       || bfd_coff_pe_weak_external_has_real_fallback
+			    (bfd_asymbol_bfd (syms[src_count]), syms[src_count]));
+
+		  if (include_in_armap)
 		    {
 		      bfd_size_type namelen;
 		      struct orl *new_map;
diff --git a/bfd/coff-bfd.c b/bfd/coff-bfd.c
index d836355aa64..e57135ddd18 100644
--- a/bfd/coff-bfd.c
+++ b/bfd/coff-bfd.c
@@ -110,3 +110,50 @@ bfd_coff_get_auxent (bfd *abfd,
 
   return true;
 }
+
+/* Return TRUE if SYMBOL is a PE weak external whose fallback symbol is
+   a real definition.  A weak declaration with no fallback uses the COFF
+   null symbol as its fallback; do not treat that as an archive provider.  */
+
+bool
+bfd_coff_pe_weak_external_has_real_fallback (bfd *abfd,
+					    asymbol *symbol)
+{
+  coff_symbol_type *csym;
+  combined_entry_type *aux;
+  combined_entry_type *fallback;
+
+  if (bfd_get_flavour (abfd) != bfd_target_coff_flavour
+      || coff_data (abfd) == NULL
+      || ! obj_pe (abfd))
+    return false;
+
+  csym = coff_symbol_from (symbol);
+  if (csym == NULL
+      || csym->native == NULL
+      || ! csym->native->is_sym
+      || csym->native->u.syment.n_sclass != C_NT_WEAK
+      || csym->native->u.syment.n_numaux != 1)
+    return false;
+
+  aux = csym->native + 1;
+  if (aux->is_sym)
+    return false;
+
+  if (aux->fix_tag)
+    fallback = (combined_entry_type *) aux->u.auxent.x_sym.x_tagndx.p;
+  else
+    {
+      uint32_t tagndx = aux->u.auxent.x_sym.x_tagndx.u32;
+
+      if (tagndx >= obj_raw_syment_count (abfd))
+	return false;
+      fallback = obj_raw_syments (abfd) + tagndx;
+    }
+
+  return (fallback != NULL
+	  && fallback->is_sym
+	  && fallback->u.syment.n_scnum != N_UNDEF
+	  && !(fallback->u.syment.n_scnum == N_ABS
+	       && fallback->u.syment.n_value == 0));
+}
diff --git a/bfd/coff-bfd.h b/bfd/coff-bfd.h
index 70cc0c36902..6626c491ebb 100644
--- a/bfd/coff-bfd.h
+++ b/bfd/coff-bfd.h
@@ -81,5 +81,8 @@ extern bool bfd_coff_get_syment
 extern bool bfd_coff_get_auxent
   (bfd *, struct bfd_symbol *, int, union internal_auxent *);
 
+extern bool bfd_coff_pe_weak_external_has_real_fallback
+  (bfd *, struct bfd_symbol *);
+
 extern bool bfd_coff_set_symbol_class
   (bfd *, struct bfd_symbol *, unsigned int);
diff --git a/bfd/cofflink.c b/bfd/cofflink.c
index 75b4c47eacf..d029bec1678 100644
--- a/bfd/cofflink.c
+++ b/bfd/cofflink.c
@@ -36,6 +36,45 @@ static bool coff_link_check_archive_element
    bool *);
 static bool coff_link_add_symbols (bfd *, struct bfd_link_info *);
 
+static bool
+coff_link_hash_pe_weak_external_has_real_fallback
+  (struct coff_link_hash_entry *h)
+{
+  struct coff_link_hash_entry *h2;
+  unsigned long symndx;
+
+  if (h->symbol_class != C_NT_WEAK
+      || h->numaux != 1
+      || h->aux == NULL
+      || h->auxbfd == NULL
+      || ! obj_pe (h->auxbfd)
+      || obj_coff_sym_hashes (h->auxbfd) == NULL)
+    return false;
+
+  /* The PE weak-external aux entry names the fallback symbol by raw
+     symbol index.  Look up the corresponding link hash entry so we can
+     test the fallback's resolved state, not just its object-file entry.  */
+  symndx = h->aux->x_sym.x_tagndx.u32;
+  if (symndx >= obj_raw_syment_count (h->auxbfd))
+    return false;
+
+  h2 = obj_coff_sym_hashes (h->auxbfd)[symndx];
+  if (h2 == NULL)
+    return false;
+
+  while (h2->root.type == bfd_link_hash_indirect
+	 || h2->root.type == bfd_link_hash_warning)
+    h2 = (struct coff_link_hash_entry *) h2->root.u.i.link;
+
+  /* A weak declaration with no fallback uses the absolute-zero null
+     symbol.  Only a defined real fallback means this archive member has
+     already satisfied the weak external.  */
+  return ((h2->root.type == bfd_link_hash_defined
+	   || h2->root.type == bfd_link_hash_defweak)
+	  && !(bfd_is_abs_section (h2->root.u.def.section)
+	       && h2->root.u.def.value == 0));
+}
+
 /* Return TRUE if SYM is a weak, external symbol.  */
 #define IS_WEAK_EXTERNAL(abfd, sym)			\
   ((sym).n_sclass == C_WEAKEXT				\
@@ -255,6 +294,13 @@ coff_link_check_archive_element (bfd *abfd,
   if (((struct coff_link_hash_entry *) h)->indx == -3)
     return true;
 
+  /* A PE weak external can stay undefined even after its fallback has
+     been defined by this archive member.  Avoid extracting the member
+     again if the same archive is searched more than once.  */
+  if (coff_link_hash_pe_weak_external_has_real_fallback
+      ((struct coff_link_hash_entry *) h))
+    return true;
+
   /* Include this element?  */
   if (!(*info->callbacks->add_archive_element) (info, abfd, name, &abfd))
     return true;
-- 
2.54.0


From peter0x44@disroot.org  Tue Jun 23 21:38:07 2026
From: peter0x44@disroot.org (Peter Damianov)
Date: Tue, 23 Jun 2026 17:38:07 -0400
Subject: [PATCH v3 4/4] ld/testsuite: Add comprehensive PE COFF weak external
 tests
In-Reply-To: <cover.1782245474.git.peter0x44@disroot.org>
References: <cover.1782245474.git.peter0x44@disroot.org>
Message-ID: <b5ef2defd67ee7bf3e5c6d9051dcde773e9f5326.1782245474.git.peter0x44@disroot.org>

Add tests covering the full matrix of weak/strong symbol interactions
for PE COFF weak externals, based on testcases by Martin Storsjo.
The archive test covers PE weak externals whose public name is backed
by a real fallback definition, and ensures weak declarations with the
null fallback are not advertised as archive providers.

ld/testsuite/

	* ld-pe/pe-compile.exp (weak_ext_test): New proc.  Compiles
	source files, links via gcc, and runs natively if possible.
	(weak_ext_archive_test): New proc.
	Add tests: normal, weak-undef, weak-defined,
	weak-decl-weak-def, strong-undef-weak-def-archive, weak-use,
	weak-override, weak-duplicate, weak-def-override, weak-def-use.
	* ld-pe/weak-ext-main.c: New file.
	* ld-pe/weak-ext-main-weak.c: New file.
	* ld-pe/weak-ext-main-weak-def.c: New file.
	* ld-pe/weak-ext-add2.c: New file.
	* ld-pe/weak-ext-add1-weak-chained.c: New file.
	* ld-pe/weak-ext-dummy.c: New file.
	* ld-pe/weak-ext-expected1.c: New file.
	* ld-pe/weak-ext-expected3.c: New file.
	* ld-pe/weak-ext-expected5.c: New file.
	* ld-pe/weak-ext-expected3-add1-weak.c: New file.
---
 ld/testsuite/ld-pe/pe-compile.exp             | 167 ++++++++++++++++++
 .../ld-pe/weak-ext-add1-weak-chained.c        |  13 ++
 ld/testsuite/ld-pe/weak-ext-add2.c            |   8 +
 ld/testsuite/ld-pe/weak-ext-dummy.c           |   5 +
 ld/testsuite/ld-pe/weak-ext-expected1.c       |   1 +
 .../ld-pe/weak-ext-expected3-add1-weak.c      |   9 +
 ld/testsuite/ld-pe/weak-ext-expected3.c       |   1 +
 ld/testsuite/ld-pe/weak-ext-expected5.c       |   1 +
 ld/testsuite/ld-pe/weak-ext-main-weak-def.c   |  26 +++
 ld/testsuite/ld-pe/weak-ext-main-weak.c       |  22 +++
 ld/testsuite/ld-pe/weak-ext-main.c            |  21 +++
 11 files changed, 274 insertions(+)
 create mode 100644 ld/testsuite/ld-pe/weak-ext-add1-weak-chained.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-add2.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-dummy.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-expected1.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-expected3-add1-weak.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-expected3.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-expected5.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-main-weak-def.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-main-weak.c
 create mode 100644 ld/testsuite/ld-pe/weak-ext-main.c

diff --git a/ld/testsuite/ld-pe/pe-compile.exp b/ld/testsuite/ld-pe/pe-compile.exp
index 041a1cb9344..aac8711dff2 100644
--- a/ld/testsuite/ld-pe/pe-compile.exp
+++ b/ld/testsuite/ld-pe/pe-compile.exp
@@ -138,3 +138,170 @@ set align_tests {
 }
 
 run_ld_link_tests $align_tests
+
+# Test PE COFF weak external symbol resolution.
+# These tests cover the full matrix of weak/strong interactions to verify
+# that the linker correctly resolves weak externals in PE COFF objects.
+# Based on testcases by Martin Storsjo.
+
+proc weak_ext_test { testname sources } {
+    global CC_FOR_TARGET
+    global srcdir
+    global subdir
+
+    set objfiles {}
+    foreach src $sources {
+	set fileroot [file rootname [file tail $src]]
+	set obj "tmpdir/$fileroot.o"
+	if ![ld_compile $CC_FOR_TARGET $srcdir/$subdir/$src $obj] {
+	    fail "$testname (compile $src)"
+	    return
+	}
+	lappend objfiles $obj
+    }
+
+    set output "tmpdir/weak-ext-test.exe"
+    if ![ld_link $CC_FOR_TARGET $output $objfiles] {
+	fail "$testname (link)"
+	return
+    }
+
+    if ![isnative] {
+	pass "$testname (link only)"
+	return
+    }
+
+    catch "exec $output" prog_output
+    if { $prog_output eq "" } {
+	pass $testname
+    } else {
+	verbose $prog_output
+	fail "$testname ($prog_output)"
+    }
+}
+
+proc weak_ext_archive_test { } {
+    global CC_FOR_TARGET
+    global ar
+    global nm
+    global srcdir
+    global subdir
+
+    set testname "weak external: archive strong undef + weak def"
+    set main_obj "tmpdir/weak-ext-main.o"
+    set weak_decl_obj "tmpdir/weak-ext-main-weak.o"
+    set weak_obj "tmpdir/weak-ext-add1-weak-chained.o"
+    set expected_obj "tmpdir/weak-ext-expected3.o"
+    set weak_decl_archive "tmpdir/weak-ext-decl-archive.a"
+    set archive "tmpdir/weak-ext-archive.a"
+    set output "tmpdir/weak-ext-archive-test.exe"
+
+    set sources {weak-ext-main.c weak-ext-main-weak.c \
+	weak-ext-add1-weak-chained.c weak-ext-expected3.c}
+    set objects [list $main_obj $weak_decl_obj $weak_obj $expected_obj]
+    foreach src $sources obj $objects {
+	if ![ld_compile $CC_FOR_TARGET $srcdir/$subdir/$src $obj] {
+	    fail "$testname (compile $src)"
+	    return
+	}
+    }
+
+    set got [run_host_cmd "$ar" "rcs $weak_decl_archive $weak_decl_obj"]
+    if ![string match "" $got] {
+	fail "$testname (weak decl archive)"
+	return
+    }
+
+    # A weak declaration with the null fallback must not advertise its
+    # public name as an archive-map provider.
+    set got [run_host_cmd "$nm" "--print-armap $weak_decl_archive"]
+    if [regexp "(^|\n)_?func in weak-ext-main-weak\\.o" $got] {
+	verbose -log $got
+	fail "$testname (weak decl armap)"
+	return
+    }
+
+    set got [run_host_cmd "$ar" "rcs $archive $weak_obj"]
+    if ![string match "" $got] {
+	fail "$testname (archive)"
+	return
+    }
+
+    # A weak external with a real fallback should advertise the public
+    # alias, so a strong undefined reference can extract the member.
+    set got [run_host_cmd "$nm" "--print-armap $archive"]
+    if ![regexp "(^|\n)_?func in weak-ext-add1-weak-chained\\.o" $got] {
+	verbose -log $got
+	fail "$testname (armap)"
+	return
+    }
+
+    # Search the archive twice to cover command lines where the driver
+    # adds a library implicitly and the user also names it explicitly.
+    if ![ld_link $CC_FOR_TARGET $output \
+	     [list $main_obj $expected_obj $archive $archive]] {
+	fail "$testname (link)"
+	return
+    }
+
+    if ![isnative] {
+	pass "$testname (link only)"
+	return
+    }
+
+    catch "exec $output" prog_output
+    if { $prog_output eq "" } {
+	pass $testname
+    } else {
+	verbose $prog_output
+	fail "$testname ($prog_output)"
+    }
+}
+
+# Strong undefined reference + strong definition: basic sanity check.
+weak_ext_test "weak external: normal (strong undef + strong def)" \
+    {weak-ext-main.c weak-ext-add2.c weak-ext-expected3.c weak-ext-dummy.c}
+
+# Weak declaration with no definition available: func remains NULL,
+# never called.
+weak_ext_test "weak external: weak undef (no def)" \
+    {weak-ext-main-weak.c weak-ext-expected1.c weak-ext-dummy.c}
+
+# Weak declaration resolved by a strong definition in another object.
+weak_ext_test "weak external: weak decl + strong def" \
+    {weak-ext-main-weak.c weak-ext-add2.c weak-ext-expected3.c weak-ext-dummy.c}
+
+# Two weak externals for the same symbol meet: the one whose fallback
+# alias points to an actual function body should win over the one whose
+# fallback is NULL.
+weak_ext_test "weak external: weak decl + weak def" \
+    {weak-ext-main-weak.c weak-ext-add1-weak-chained.c weak-ext-expected3.c}
+
+# Strong undefined reference is seen before the weak definition: the
+# linker must still store the weak external's aux record so the fallback
+# alias can be resolved later.
+weak_ext_test "weak external: strong undef + weak def" \
+    {weak-ext-main.c weak-ext-add1-weak-chained.c weak-ext-expected3.c}
+
+weak_ext_archive_test
+
+# Strong definition overrides a weak definition: both call sites (in
+# main and in dummy) should resolve to the strong def.
+weak_ext_test "weak external: strong override of weak" \
+    {weak-ext-main.c weak-ext-add1-weak-chained.c weak-ext-add2.c \
+     weak-ext-expected5.c}
+
+# Two identical weak definitions for the same symbol: no conflict,
+# the linker picks one (first wins) and discards the duplicate.
+weak_ext_test "weak external: duplicate weak defs" \
+    {weak-ext-main.c weak-ext-add1-weak-chained.c \
+     weak-ext-expected3-add1-weak.c}
+
+# Weak definition in main overridden by a strong definition elsewhere.
+weak_ext_test "weak external: weak def overridden by strong" \
+    {weak-ext-main-weak-def.c weak-ext-add2.c weak-ext-expected3.c \
+     weak-ext-dummy.c}
+
+# Weak definition in main used directly when no strong definition exists.
+weak_ext_test "weak external: weak def used (no strong)" \
+    {weak-ext-main-weak-def.c weak-ext-expected5.c weak-ext-dummy.c}
diff --git a/ld/testsuite/ld-pe/weak-ext-add1-weak-chained.c b/ld/testsuite/ld-pe/weak-ext-add1-weak-chained.c
new file mode 100644
index 00000000000..5b68b8435e2
--- /dev/null
+++ b/ld/testsuite/ld-pe/weak-ext-add1-weak-chained.c
@@ -0,0 +1,13 @@
+/* Weak definition of func (adds 1), plus dummy that calls func.  */
+extern int value;
+
+__attribute__((weak)) void func (void)
+{
+  value += 1;
+}
+
+void
+dummy (void)
+{
+  func ();
+}
diff --git a/ld/testsuite/ld-pe/weak-ext-add2.c b/ld/testsuite/ld-pe/weak-ext-add2.c
new file mode 100644
index 00000000000..691554d17e3
--- /dev/null
+++ b/ld/testsuite/ld-pe/weak-ext-add2.c
@@ -0,0 +1,8 @@
+/* Strong definition of func (adds 2).  */
+extern int value;
+
+void
+func (void)
+{
+  value += 2;
+}
diff --git a/ld/testsuite/ld-pe/weak-ext-dummy.c b/ld/testsuite/ld-pe/weak-ext-dummy.c
new file mode 100644
index 00000000000..1c97c3cf97f
--- /dev/null
+++ b/ld/testsuite/ld-pe/weak-ext-dummy.c
@@ -0,0 +1,5 @@
+/* Empty dummy function.  */
+void
+dummy (void)
+{
+}
diff --git a/ld/testsuite/ld-pe/weak-ext-expected1.c b/ld/testsuite/ld-pe/weak-ext-expected1.c
new file mode 100644
index 00000000000..5b4138b0bb1
--- /dev/null
+++ b/ld/testsuite/ld-pe/weak-ext-expected1.c
@@ -0,0 +1 @@
+int expected = 1;
diff --git a/ld/testsuite/ld-pe/weak-ext-expected3-add1-weak.c b/ld/testsuite/ld-pe/weak-ext-expected3-add1-weak.c
new file mode 100644
index 00000000000..585830bd304
--- /dev/null
+++ b/ld/testsuite/ld-pe/weak-ext-expected3-add1-weak.c
@@ -0,0 +1,9 @@
+/* Second weak definition of func (adds 1) plus expected value.  */
+extern int value;
+
+__attribute__((weak)) void func (void)
+{
+  value += 1;
+}
+
+int expected = 3;
diff --git a/ld/testsuite/ld-pe/weak-ext-expected3.c b/ld/testsuite/ld-pe/weak-ext-expected3.c
new file mode 100644
index 00000000000..3d67d70bcb0
--- /dev/null
+++ b/ld/testsuite/ld-pe/weak-ext-expected3.c
@@ -0,0 +1 @@
+int expected = 3;
diff --git a/ld/testsuite/ld-pe/weak-ext-expected5.c b/ld/testsuite/ld-pe/weak-ext-expected5.c
new file mode 100644
index 00000000000..fef6b322c03
--- /dev/null
+++ b/ld/testsuite/ld-pe/weak-ext-expected5.c
@@ -0,0 +1 @@
+int expected = 5;
diff --git a/ld/testsuite/ld-pe/weak-ext-main-weak-def.c b/ld/testsuite/ld-pe/weak-ext-main-weak-def.c
new file mode 100644
index 00000000000..05f81d189b4
--- /dev/null
+++ b/ld/testsuite/ld-pe/weak-ext-main-weak-def.c
@@ -0,0 +1,26 @@
+/* Weak definition of func in main (adds 4).  */
+#include <stdio.h>
+
+int value = 1;
+
+__attribute__((weak)) void func (void)
+{
+  value += 4;
+}
+
+void dummy (void);
+extern int expected;
+
+int
+main (void)
+{
+  if (func)
+    func ();
+  dummy ();
+  if (value != expected)
+    {
+      printf ("expected %d, got %d\n", expected, value);
+      return 1;
+    }
+  return 0;
+}
diff --git a/ld/testsuite/ld-pe/weak-ext-main-weak.c b/ld/testsuite/ld-pe/weak-ext-main-weak.c
new file mode 100644
index 00000000000..bc1501f62c0
--- /dev/null
+++ b/ld/testsuite/ld-pe/weak-ext-main-weak.c
@@ -0,0 +1,22 @@
+/* Weak declaration of func (no definition).  */
+#include <stdio.h>
+
+__attribute__((weak)) void func (void);
+void dummy (void);
+
+int value = 1;
+extern int expected;
+
+int
+main (void)
+{
+  if (func)
+    func ();
+  dummy ();
+  if (value != expected)
+    {
+      printf ("expected %d, got %d\n", expected, value);
+      return 1;
+    }
+  return 0;
+}
diff --git a/ld/testsuite/ld-pe/weak-ext-main.c b/ld/testsuite/ld-pe/weak-ext-main.c
new file mode 100644
index 00000000000..916bb246e5f
--- /dev/null
+++ b/ld/testsuite/ld-pe/weak-ext-main.c
@@ -0,0 +1,21 @@
+/* Strong undefined reference to func.  */
+#include <stdio.h>
+
+void func (void);
+void dummy (void);
+
+int value = 1;
+extern int expected;
+
+int
+main (void)
+{
+  func ();
+  dummy ();
+  if (value != expected)
+    {
+      printf ("expected %d, got %d\n", expected, value);
+      return 1;
+    }
+  return 0;
+}
-- 
2.54.0


From oleg.tolmatcev@gmail.com  Tue Jun 23 21:39:01 2026
From: oleg.tolmatcev@gmail.com (Oleg Tolmatcev)
Date: Tue, 23 Jun 2026 23:39:01 +0200
Subject: [PATCH v2] PE/COFF: auto-promote oversized objects to bigobj
Message-ID: <20260623213900.2000-2-oleg.tolmatcev@gmail.com>

PE/COFF object files use 16-bit section numbers in normal symbols.
When an object grows past that limit, current BFD already rejects it with
a "too many sections" / "file too big" error.

BFD already has PE bigobj targets for the backends that support them, but
oversized PE/COFF output still requires selecting bigobj explicitly.

Teach coff_compute_section_file_positions to switch PE/COFF output to the
corresponding bigobj target when the normal section-number limit is
exceeded. This preserves the existing hard error for targets without
bigobj support, but lets supported PE targets transparently emit a valid
bigobj object instead of requiring manual selection.

bfd/
	* coffcode.h (coff_compute_section_file_positions): Auto-promote
	oversized PE/COFF objects to the bigobj target.

gas/
	* testsuite/gas/pe/big-obj-auto.d: New test.
	* testsuite/gas/pe/big-obj-auto.s: New test.
	* testsuite/gas/pe/pe.exp: Run big-obj-auto.

Signed-off-by: Oleg Tolmatcev <oleg.tolmatcev@gmail.com>
---
 bfd/coffcode.h                      | 14 ++++++++++++++
 gas/testsuite/gas/pe/big-obj-auto.d |  9 +++++++++
 gas/testsuite/gas/pe/big-obj-auto.s | 16 ++++++++++++++++
 gas/testsuite/gas/pe/pe.exp         |  4 +++-
 4 files changed, 42 insertions(+), 1 deletion(-)
 create mode 100644 gas/testsuite/gas/pe/big-obj-auto.d
 create mode 100644 gas/testsuite/gas/pe/big-obj-auto.s

diff --git a/bfd/coffcode.h b/bfd/coffcode.h
index 7439fca676..5c9722a15e 100644
--- a/bfd/coffcode.h
+++ b/bfd/coffcode.h
@@ -360,6 +360,10 @@ CODE_FRAGMENT
 #include "coffswap.h"
 #endif
 
+#ifdef COFF_WITH_PE_BIGOBJ
+extern const bfd_target TARGET_SYM_BIG;
+#endif
+
 #define STRING_SIZE_SIZE 4
 
 #define DOT_DEBUG	".debug"
@@ -3154,6 +3158,16 @@ coff_compute_section_file_positions (bfd * abfd)
 
   if (target_index >= bfd_coff_max_nscns (abfd))
     {
+#ifdef COFF_WITH_PE_BIGOBJ
+      if (abfd->xvec != &TARGET_SYM_BIG)
+	{
+	  /* Regular PE/COFF uses 16-bit section numbers in symbols.
+	     Promote oversized objects to the matching bigobj target
+	     before any headers or symbols are finalized.  */
+	  abfd->xvec = &TARGET_SYM_BIG;
+	  return coff_compute_section_file_positions (abfd);
+	}
+#endif
       bfd_set_error (bfd_error_file_too_big);
       _bfd_error_handler
 	/* xgettext:c-format */
diff --git a/gas/testsuite/gas/pe/big-obj-auto.d b/gas/testsuite/gas/pe/big-obj-auto.d
new file mode 100644
index 0000000000..985c1270e2
--- /dev/null
+++ b/gas/testsuite/gas/pe/big-obj-auto.d
@@ -0,0 +1,9 @@
+#objdump: -h
+#name: PE big obj auto-promotion
+
+.*: *file format pe-bigobj-.*
+
+Sections:
+#...
+80002 +\.data\$a79999  .*
+                  CONTENTS, ALLOC, LOAD, DATA
diff --git a/gas/testsuite/gas/pe/big-obj-auto.s b/gas/testsuite/gas/pe/big-obj-auto.s
new file mode 100644
index 0000000000..8c010716c6
--- /dev/null
+++ b/gas/testsuite/gas/pe/big-obj-auto.s
@@ -0,0 +1,16 @@
+	.file "big-obj-auto.s"
+
+	.irp n,0,1,2,3,4,5,6,7
+	.irp m,0,1,2,3,4,5,6,7,8,9
+	.irp c,0,1,2,3,4,5,6,7,8,9
+	.irp d,0,1,2,3,4,5,6,7,8,9
+	.irp u,0,1,2,3,4,5,6,7,8,9
+	.globl a\n\m\c\d\u
+	.section .data$a\n\m\c\d\u,"w"
+a\n\m\c\d\u :
+	.byte 1
+	.endr
+	.endr
+	.endr
+	.endr
+	.endr
diff --git a/gas/testsuite/gas/pe/pe.exp b/gas/testsuite/gas/pe/pe.exp
index e25de3cfa9..2aba5ecb3d 100644
--- a/gas/testsuite/gas/pe/pe.exp
+++ b/gas/testsuite/gas/pe/pe.exp
@@ -68,6 +68,8 @@ if {[istarget "aarch64-*-pe*"] || [istarget "aarch64-*-mingw*"]} {
 # Big obj
 
 
-if ([istarget "*-*-mingw*"]) then {
+if { [istarget "aarch64-*-*"] || [istarget "i*86-*-*"]
+    || [istarget "x86_64-*-*"] } then {
 	run_dump_test "big-obj"
+	run_dump_test "big-obj-auto"
 }
-- 
2.54.0.windows.1


From peter0x44@disroot.org  Wed Jun 24 00:09:23 2026
From: peter0x44@disroot.org (Peter0x44)
Date: Tue, 23 Jun 2026 20:09:23 -0400
Subject: [PATCH v3 4/4] ld/testsuite: Add comprehensive PE COFF weak
 external tests
In-Reply-To: <b5ef2defd67ee7bf3e5c6d9051dcde773e9f5326.1782245474.git.peter0x44@disroot.org>
References: <cover.1782245474.git.peter0x44@disroot.org>
 <b5ef2defd67ee7bf3e5c6d9051dcde773e9f5326.1782245474.git.peter0x44@disroot.org>
Message-ID: <ce908e20-2b8a-4e6d-9474-ec03842a2c3c@disroot.org>

Oops I forgot to amend this commit with my testsuite changes exercising the issue with archives. Will have to submit a v4. But otherwise, the practical changes are good and I tested them thoroughly. Including the fix for gcc PR124263

Jun 23, 2026 5:38:29 PM Peter Damianov <peter0x44@disroot.org>:

> Add tests covering the full matrix of weak/strong symbol interactions
> for PE COFF weak externals, based on testcases by Martin Storsjo.
> The archive test covers PE weak externals whose public name is backed
> by a real fallback definition, and ensures weak declarations with the
> null fallback are not advertised as archive providers.
> 
> ld/testsuite/
> 
> ??? * ld-pe/pe-compile.exp (weak_ext_test): New proc.? Compiles
> ??? source files, links via gcc, and runs natively if possible.
> ??? (weak_ext_archive_test): New proc.
> ??? Add tests: normal, weak-undef, weak-defined,
> ??? weak-decl-weak-def, strong-undef-weak-def-archive, weak-use,
> ??? weak-override, weak-duplicate, weak-def-override, weak-def-use.
> ??? * ld-pe/weak-ext-main.c: New file.
> ??? * ld-pe/weak-ext-main-weak.c: New file.
> ??? * ld-pe/weak-ext-main-weak-def.c: New file.
> ??? * ld-pe/weak-ext-add2.c: New file.
> ??? * ld-pe/weak-ext-add1-weak-chained.c: New file.
> ??? * ld-pe/weak-ext-dummy.c: New file.
> ??? * ld-pe/weak-ext-expected1.c: New file.
> ??? * ld-pe/weak-ext-expected3.c: New file.
> ??? * ld-pe/weak-ext-expected5.c: New file.
> ??? * ld-pe/weak-ext-expected3-add1-weak.c: New file.
> ---
> ld/testsuite/ld-pe/pe-compile.exp???????????? | 167 ++++++++++++++++++
> .../ld-pe/weak-ext-add1-weak-chained.c??????? |? 13 ++
> ld/testsuite/ld-pe/weak-ext-add2.c??????????? |?? 8 +
> ld/testsuite/ld-pe/weak-ext-dummy.c?????????? |?? 5 +
> ld/testsuite/ld-pe/weak-ext-expected1.c?????? |?? 1 +
> .../ld-pe/weak-ext-expected3-add1-weak.c????? |?? 9 +
> ld/testsuite/ld-pe/weak-ext-expected3.c?????? |?? 1 +
> ld/testsuite/ld-pe/weak-ext-expected5.c?????? |?? 1 +
> ld/testsuite/ld-pe/weak-ext-main-weak-def.c?? |? 26 +++
> ld/testsuite/ld-pe/weak-ext-main-weak.c?????? |? 22 +++
> ld/testsuite/ld-pe/weak-ext-main.c??????????? |? 21 +++
> 11 files changed, 274 insertions(+)
> create mode 100644 ld/testsuite/ld-pe/weak-ext-add1-weak-chained.c
> create mode 100644 ld/testsuite/ld-pe/weak-ext-add2.c
> create mode 100644 ld/testsuite/ld-pe/weak-ext-dummy.c
> create mode 100644 ld/testsuite/ld-pe/weak-ext-expected1.c
> create mode 100644 ld/testsuite/ld-pe/weak-ext-expected3-add1-weak.c
> create mode 100644 ld/testsuite/ld-pe/weak-ext-expected3.c
> create mode 100644 ld/testsuite/ld-pe/weak-ext-expected5.c
> create mode 100644 ld/testsuite/ld-pe/weak-ext-main-weak-def.c
> create mode 100644 ld/testsuite/ld-pe/weak-ext-main-weak.c
> create mode 100644 ld/testsuite/ld-pe/weak-ext-main.c
> 
> diff --git a/ld/testsuite/ld-pe/pe-compile.exp b/ld/testsuite/ld-pe/pe-compile.exp
> index 041a1cb9344..aac8711dff2 100644
> --- a/ld/testsuite/ld-pe/pe-compile.exp
> +++ b/ld/testsuite/ld-pe/pe-compile.exp
> @@ -138,3 +138,170 @@ set align_tests {
> }
> 
> run_ld_link_tests $align_tests
> +
> +# Test PE COFF weak external symbol resolution.
> +# These tests cover the full matrix of weak/strong interactions to verify
> +# that the linker correctly resolves weak externals in PE COFF objects.
> +# Based on testcases by Martin Storsjo.
> +
> +proc weak_ext_test { testname sources } {
> +??? global CC_FOR_TARGET
> +??? global srcdir
> +??? global subdir
> +
> +??? set objfiles {}
> +??? foreach src $sources {
> +?? set fileroot [file rootname [file tail $src]]
> +?? set obj "tmpdir/$fileroot.o"
> +?? if ![ld_compile $CC_FOR_TARGET $srcdir/$subdir/$src $obj] {
> +?????? fail "$testname (compile $src)"
> +?????? return
> +?? }
> +?? lappend objfiles $obj
> +??? }
> +
> +??? set output "tmpdir/weak-ext-test.exe"
> +??? if ![ld_link $CC_FOR_TARGET $output $objfiles] {
> +?? fail "$testname (link)"
> +?? return
> +??? }
> +
> +??? if ![isnative] {
> +?? pass "$testname (link only)"
> +?? return
> +??? }
> +
> +??? catch "exec $output" prog_output
> +??? if { $prog_output eq "" } {
> +?? pass $testname
> +??? } else {
> +?? verbose $prog_output
> +?? fail "$testname ($prog_output)"
> +??? }
> +}
> +
> +proc weak_ext_archive_test { } {
> +??? global CC_FOR_TARGET
> +??? global ar
> +??? global nm
> +??? global srcdir
> +??? global subdir
> +
> +??? set testname "weak external: archive strong undef + weak def"
> +??? set main_obj "tmpdir/weak-ext-main.o"
> +??? set weak_decl_obj "tmpdir/weak-ext-main-weak.o"
> +??? set weak_obj "tmpdir/weak-ext-add1-weak-chained.o"
> +??? set expected_obj "tmpdir/weak-ext-expected3.o"
> +??? set weak_decl_archive "tmpdir/weak-ext-decl-archive.a"
> +??? set archive "tmpdir/weak-ext-archive.a"
> +??? set output "tmpdir/weak-ext-archive-test.exe"
> +
> +??? set sources {weak-ext-main.c weak-ext-main-weak.c \
> +?? weak-ext-add1-weak-chained.c weak-ext-expected3.c}
> +??? set objects [list $main_obj $weak_decl_obj $weak_obj $expected_obj]
> +??? foreach src $sources obj $objects {
> +?? if ![ld_compile $CC_FOR_TARGET $srcdir/$subdir/$src $obj] {
> +?????? fail "$testname (compile $src)"
> +?????? return
> +?? }
> +??? }
> +
> +??? set got [run_host_cmd "$ar" "rcs $weak_decl_archive $weak_decl_obj"]
> +??? if ![string match "" $got] {
> +?? fail "$testname (weak decl archive)"
> +?? return
> +??? }
> +
> +??? # A weak declaration with the null fallback must not advertise its
> +??? # public name as an archive-map provider.
> +??? set got [run_host_cmd "$nm" "--print-armap $weak_decl_archive"]
> +??? if [regexp "(^|\n)_?func in weak-ext-main-weak\\.o" $got] {
> +?? verbose -log $got
> +?? fail "$testname (weak decl armap)"
> +?? return
> +??? }
> +
> +??? set got [run_host_cmd "$ar" "rcs $archive $weak_obj"]
> +??? if ![string match "" $got] {
> +?? fail "$testname (archive)"
> +?? return
> +??? }
> +
> +??? # A weak external with a real fallback should advertise the public
> +??? # alias, so a strong undefined reference can extract the member.
> +??? set got [run_host_cmd "$nm" "--print-armap $archive"]
> +??? if ![regexp "(^|\n)_?func in weak-ext-add1-weak-chained\\.o" $got] {
> +?? verbose -log $got
> +?? fail "$testname (armap)"
> +?? return
> +??? }
> +
> +??? # Search the archive twice to cover command lines where the driver
> +??? # adds a library implicitly and the user also names it explicitly.
> +??? if ![ld_link $CC_FOR_TARGET $output \
> +??????? [list $main_obj $expected_obj $archive $archive]] {
> +?? fail "$testname (link)"
> +?? return
> +??? }
> +
> +??? if ![isnative] {
> +?? pass "$testname (link only)"
> +?? return
> +??? }
> +
> +??? catch "exec $output" prog_output
> +??? if { $prog_output eq "" } {
> +?? pass $testname
> +??? } else {
> +?? verbose $prog_output
> +?? fail "$testname ($prog_output)"
> +??? }
> +}
> +
> +# Strong undefined reference + strong definition: basic sanity check.
> +weak_ext_test "weak external: normal (strong undef + strong def)" \
> +??? {weak-ext-main.c weak-ext-add2.c weak-ext-expected3.c weak-ext-dummy.c}
> +
> +# Weak declaration with no definition available: func remains NULL,
> +# never called.
> +weak_ext_test "weak external: weak undef (no def)" \
> +??? {weak-ext-main-weak.c weak-ext-expected1.c weak-ext-dummy.c}
> +
> +# Weak declaration resolved by a strong definition in another object.
> +weak_ext_test "weak external: weak decl + strong def" \
> +??? {weak-ext-main-weak.c weak-ext-add2.c weak-ext-expected3.c weak-ext-dummy.c}
> +
> +# Two weak externals for the same symbol meet: the one whose fallback
> +# alias points to an actual function body should win over the one whose
> +# fallback is NULL.
> +weak_ext_test "weak external: weak decl + weak def" \
> +??? {weak-ext-main-weak.c weak-ext-add1-weak-chained.c weak-ext-expected3.c}
> +
> +# Strong undefined reference is seen before the weak definition: the
> +# linker must still store the weak external's aux record so the fallback
> +# alias can be resolved later.
> +weak_ext_test "weak external: strong undef + weak def" \
> +??? {weak-ext-main.c weak-ext-add1-weak-chained.c weak-ext-expected3.c}
> +
> +weak_ext_archive_test
> +
> +# Strong definition overrides a weak definition: both call sites (in
> +# main and in dummy) should resolve to the strong def.
> +weak_ext_test "weak external: strong override of weak" \
> +??? {weak-ext-main.c weak-ext-add1-weak-chained.c weak-ext-add2.c \
> +???? weak-ext-expected5.c}
> +
> +# Two identical weak definitions for the same symbol: no conflict,
> +# the linker picks one (first wins) and discards the duplicate.
> +weak_ext_test "weak external: duplicate weak defs" \
> +??? {weak-ext-main.c weak-ext-add1-weak-chained.c \
> +???? weak-ext-expected3-add1-weak.c}
> +
> +# Weak definition in main overridden by a strong definition elsewhere.
> +weak_ext_test "weak external: weak def overridden by strong" \
> +??? {weak-ext-main-weak-def.c weak-ext-add2.c weak-ext-expected3.c \
> +???? weak-ext-dummy.c}
> +
> +# Weak definition in main used directly when no strong definition exists.
> +weak_ext_test "weak external: weak def used (no strong)" \
> +??? {weak-ext-main-weak-def.c weak-ext-expected5.c weak-ext-dummy.c}
> diff --git a/ld/testsuite/ld-pe/weak-ext-add1-weak-chained.c b/ld/testsuite/ld-pe/weak-ext-add1-weak-chained.c
> new file mode 100644
> index 00000000000..5b68b8435e2
> --- /dev/null
> +++ b/ld/testsuite/ld-pe/weak-ext-add1-weak-chained.c
> @@ -0,0 +1,13 @@
> +/* Weak definition of func (adds 1), plus dummy that calls func.? */
> +extern int value;
> +
> +__attribute__((weak)) void func (void)
> +{
> +? value += 1;
> +}
> +
> +void
> +dummy (void)
> +{
> +? func ();
> +}
> diff --git a/ld/testsuite/ld-pe/weak-ext-add2.c b/ld/testsuite/ld-pe/weak-ext-add2.c
> new file mode 100644
> index 00000000000..691554d17e3
> --- /dev/null
> +++ b/ld/testsuite/ld-pe/weak-ext-add2.c
> @@ -0,0 +1,8 @@
> +/* Strong definition of func (adds 2).? */
> +extern int value;
> +
> +void
> +func (void)
> +{
> +? value += 2;
> +}
> diff --git a/ld/testsuite/ld-pe/weak-ext-dummy.c b/ld/testsuite/ld-pe/weak-ext-dummy.c
> new file mode 100644
> index 00000000000..1c97c3cf97f
> --- /dev/null
> +++ b/ld/testsuite/ld-pe/weak-ext-dummy.c
> @@ -0,0 +1,5 @@
> +/* Empty dummy function.? */
> +void
> +dummy (void)
> +{
> +}
> diff --git a/ld/testsuite/ld-pe/weak-ext-expected1.c b/ld/testsuite/ld-pe/weak-ext-expected1.c
> new file mode 100644
> index 00000000000..5b4138b0bb1
> --- /dev/null
> +++ b/ld/testsuite/ld-pe/weak-ext-expected1.c
> @@ -0,0 +1 @@
> +int expected = 1;
> diff --git a/ld/testsuite/ld-pe/weak-ext-expected3-add1-weak.c b/ld/testsuite/ld-pe/weak-ext-expected3-add1-weak.c
> new file mode 100644
> index 00000000000..585830bd304
> --- /dev/null
> +++ b/ld/testsuite/ld-pe/weak-ext-expected3-add1-weak.c
> @@ -0,0 +1,9 @@
> +/* Second weak definition of func (adds 1) plus expected value.? */
> +extern int value;
> +
> +__attribute__((weak)) void func (void)
> +{
> +? value += 1;
> +}
> +
> +int expected = 3;
> diff --git a/ld/testsuite/ld-pe/weak-ext-expected3.c b/ld/testsuite/ld-pe/weak-ext-expected3.c
> new file mode 100644
> index 00000000000..3d67d70bcb0
> --- /dev/null
> +++ b/ld/testsuite/ld-pe/weak-ext-expected3.c
> @@ -0,0 +1 @@
> +int expected = 3;
> diff --git a/ld/testsuite/ld-pe/weak-ext-expected5.c b/ld/testsuite/ld-pe/weak-ext-expected5.c
> new file mode 100644
> index 00000000000..fef6b322c03
> --- /dev/null
> +++ b/ld/testsuite/ld-pe/weak-ext-expected5.c
> @@ -0,0 +1 @@
> +int expected = 5;
> diff --git a/ld/testsuite/ld-pe/weak-ext-main-weak-def.c b/ld/testsuite/ld-pe/weak-ext-main-weak-def.c
> new file mode 100644
> index 00000000000..05f81d189b4
> --- /dev/null
> +++ b/ld/testsuite/ld-pe/weak-ext-main-weak-def.c
> @@ -0,0 +1,26 @@
> +/* Weak definition of func in main (adds 4).? */
> +#include <stdio.h>
> +
> +int value = 1;
> +
> +__attribute__((weak)) void func (void)
> +{
> +? value += 4;
> +}
> +
> +void dummy (void);
> +extern int expected;
> +
> +int
> +main (void)
> +{
> +? if (func)
> +??? func ();
> +? dummy ();
> +? if (value != expected)
> +??? {
> +????? printf ("expected %d, got %d\n", expected, value);
> +????? return 1;
> +??? }
> +? return 0;
> +}
> diff --git a/ld/testsuite/ld-pe/weak-ext-main-weak.c b/ld/testsuite/ld-pe/weak-ext-main-weak.c
> new file mode 100644
> index 00000000000..bc1501f62c0
> --- /dev/null
> +++ b/ld/testsuite/ld-pe/weak-ext-main-weak.c
> @@ -0,0 +1,22 @@
> +/* Weak declaration of func (no definition).? */
> +#include <stdio.h>
> +
> +__attribute__((weak)) void func (void);
> +void dummy (void);
> +
> +int value = 1;
> +extern int expected;
> +
> +int
> +main (void)
> +{
> +? if (func)
> +??? func ();
> +? dummy ();
> +? if (value != expected)
> +??? {
> +????? printf ("expected %d, got %d\n", expected, value);
> +????? return 1;
> +??? }
> +? return 0;
> +}
> diff --git a/ld/testsuite/ld-pe/weak-ext-main.c b/ld/testsuite/ld-pe/weak-ext-main.c
> new file mode 100644
> index 00000000000..916bb246e5f
> --- /dev/null
> +++ b/ld/testsuite/ld-pe/weak-ext-main.c
> @@ -0,0 +1,21 @@
> +/* Strong undefined reference to func.? */
> +#include <stdio.h>
> +
> +void func (void);
> +void dummy (void);
> +
> +int value = 1;
> +extern int expected;
> +
> +int
> +main (void)
> +{
> +? func ();
> +? dummy ();
> +? if (value != expected)
> +??? {
> +????? printf ("expected %d, got %d\n", expected, value);
> +????? return 1;
> +??? }
> +? return 0;
> +}
> -- 
> 2.54.0
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From hjl.tools@gmail.com  Wed Jun 24 00:23:07 2026
From: hjl.tools@gmail.com (H.J. Lu)
Date: Wed, 24 Jun 2026 08:23:07 +0800
Subject: [PATCH] gas/ELF: Allow local symbol with hidden visibility
In-Reply-To: <888a0461-7875-411b-bde9-dd7960e1536e@suse.com>
References: <bcd40b22-b90f-4334-8ab4-e8afeea2a6a9@suse.com>
 <193f86ed-f34b-4da8-9eac-68005830d369@suse.com>
 <e6007e9e-2cb7-4635-a974-5f753b212133@arm.com>
 <1397563c-32ca-4343-9587-99c197dd4029@suse.com>
 <b4ec2334-1821-4780-9876-f8a12d20dc4b@suse.com>
 <CAMe9rOoqhA+o278P+bPWOvHSxENbjyiN=o+Goep-6MUt2--_-w@mail.gmail.com>
 <e43bc9d8-260e-46f1-9afc-c52eacd4ac60@suse.com>
 <CAMe9rOpVyKapj7FrC1k+MZRqO1J+FZhq-HnfarzpuPedkJ0snA@mail.gmail.com>
 <67a1182c-e7d0-40ad-98ec-9b49c1d28410@suse.com>
 <17f9a3cc-7994-ad25-692b-e3e9441ff481@suse.de>
 <3d038b03-8b0f-46c5-a663-d1eacebaa6c9@suse.com>
 <f16445c4-e3e4-72ca-f5ee-9b5ede84de3d@suse.de>
 <888a0461-7875-411b-bde9-dd7960e1536e@suse.com>
Message-ID: <CAMe9rOrdHFXyxhZhfmzrBnJFWW6ji+Mam0SPjoqASxufpX2LaA@mail.gmail.com>

On Tue, Jun 23, 2026 at 10:22?PM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 23.06.2026 15:54, Michael Matz wrote:
> > On Tue, 23 Jun 2026, Jan Beulich wrote:
> >>> I think that's a misinterpretation.  "a symbol is protected" is different
> >>> from "a symbol has STV_PROTECTED visibility".  The former is defined in
> >>> the section for the latter:
> >>>
> >>>   A symbol defined in the current component is protected if it is visible
> >>>   in other components but cannot be preempted. Any reference to such a
> >>>   symbol from within the defining component must be resolved to the
> >>>   definition in that component, even if there is a definition in another
> >>>   component that would interpose by the default rules. A symbol with
> >>>   STB_LOCAL binding will not have STV_PROTECTED visibility.
> >>>
> >>> and _that definition_ is invoked by STV_HIDDEN:
> >>>
> >>>   A symbol defined in the current component is hidden if its name is not
> >>>   visible to other components. Such a symbol is necessarily protected.
> >>>
> >>> IMHO it's clear that a symbol hence "can be protected" without having its
> >>> visibility be STV_PROTECTED.  Namely when it is STV_HIDDEN: its then
> >>> protected _and_ hidden (which is of course redundant, because hidden
> >>> implies protected, but as we are word-smithing, lets be precise).
> >>>
> >>> That a STB_LOCAL symbol cannot have STV_PROTECTED visibility doesn't
> >>> transfer to STV_HIDDEN from this wording, and from nothing else either,
> >>> conceptually binding and visibility are orthogonal concepts and this
> >>> specific disallowance for the STB_LOCAL+STV_PROTECTED combination is ...
> >>> well, specific.  That is the wart, not that STB_LOCAL+STV_HIDDEN was
> >>> "forgotten" to be disallowed.
> >>
> >> IOW what you're suggesting as interpretation is that while STV_PROTECTED
> >> and STB_LOCAL may not combine, the visibility-wise more restricting
> >> STV_HIDDEN may combine with STB_LOCAL?
> >
> > Yes.
> >
> >> Make no sense to me, I'm afraid.
> >
> > That may be, and I agree that creating such situation willingly would
> > be suspect.  But as we just saw, such combinations might be created
> > by an unlucky reality.
>
> Because of shortcomings in the tools used. I bet if there had been a
> warning, the approach chosen would have been a different one. (The
> approach chosen also isn't portable to non-ELF targets.)
>
> >  And again: binding and visiblity are _orthogonal_.
> > One is for link-editing, the other for runtime linking.  In principle all
> > combinations are "okay" (if questionable), and have obvious
> > implementations.  But it's only that specific combination
> > STB_LOCAL+STV_PROTECTED that is explicitely made ill-formed in the spec
> > (despite it being also obviously implementable).  So, sure, warning on
> > that combination can be done on the grounds of following the spec.  But no
> > other combination is so spelled out, so there's no basis for trying to
> > disallow them.
>
> As with many things in specs, what's spelled out and what's implied
> is a matter of interpretation. As I think follows from earlier replies,
> I can see that there is room for interpretation here, and hence mine
> may not match what was intended. Yet we won't know for any other
> interpretation either, seeing the state the ELF spec is in.
>
> If others are in favor of following your interpretation, then I'm not
> going to stand in the way. But as of now it's not going to be me to
> make a patch to that effect. I simply couldn't write a description
> for it in good faith.
>
> >> (And would also make the implementation harder.)
> >
> > If a warning is too costly to implement, then it shouldn't be there.
> > Though it seems surprising that checking for "is_local && is_protected"
> > should be materially more difficult than for "is_local && !is_default_vis".
> > (I haven't looked at the concrete patch, though).
>
> Well, you may be right and it's not really more complex.
>
> Jan

Here is the patch.

-- 
H.J.
---
In the source code extracted from glibc:

extern void _dl_sysinfo_int80 (void)
  __attribute__ ((visibility ("hidden")));

asm (".text\n\t"
     ".type _dl_sysinfo_int80,@function\n"
     "_dl_sysinfo_int80:\n\t"
     "int $0x80;\n\t"
     "ret");

uintptr_t
foo ()
{
  return (uintptr_t) _dl_sysinfo_int80;
}

_dl_sysinfo_int80 is a local function, but it is defined in an asm
statement.  Since it is referenced in C, it is declared as hidden,
which leads to an assembler warning:

Warning: local symbol `_dl_sysinfo_int80' has non-default visibility

Symbol binding and visiblity are orthogonal.  One is for link-editing,
the other for runtime linking.  In principle, all combinations are "okay"
(if questionable), and have obvious implementations.  But it's only that
specific combination STB_LOCAL+STV_PROTECTED that is explicitely made
ill-formed in the spec (despite it being also obviously implementable).
Warning on that combination can be done on the grounds of following the
spec.  But no other combination is so spelled out, so there's no basis
for trying to disallow them.

Update elf_adjust_symtab to avoid such warning.

binutils/

PR gas/34312
* testsuite/binutils-all/localize-hidden-1.l: Adjusted.

gas/

PR gas/34312
* config/obj-elf.c (elf_adjust_symtab): Allow local symbol with
hidden visibility.
* testsuite/gas/elf/visibility.l: Adjusted.
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From jbeulich@suse.com  Wed Jun 24 05:59:30 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Wed, 24 Jun 2026 07:59:30 +0200
Subject: [PATCH] gas/ELF: Allow local symbol with hidden visibility
In-Reply-To: <CAMe9rOrdHFXyxhZhfmzrBnJFWW6ji+Mam0SPjoqASxufpX2LaA@mail.gmail.com>
References: <bcd40b22-b90f-4334-8ab4-e8afeea2a6a9@suse.com>
 <193f86ed-f34b-4da8-9eac-68005830d369@suse.com>
 <e6007e9e-2cb7-4635-a974-5f753b212133@arm.com>
 <1397563c-32ca-4343-9587-99c197dd4029@suse.com>
 <b4ec2334-1821-4780-9876-f8a12d20dc4b@suse.com>
 <CAMe9rOoqhA+o278P+bPWOvHSxENbjyiN=o+Goep-6MUt2--_-w@mail.gmail.com>
 <e43bc9d8-260e-46f1-9afc-c52eacd4ac60@suse.com>
 <CAMe9rOpVyKapj7FrC1k+MZRqO1J+FZhq-HnfarzpuPedkJ0snA@mail.gmail.com>
 <67a1182c-e7d0-40ad-98ec-9b49c1d28410@suse.com>
 <17f9a3cc-7994-ad25-692b-e3e9441ff481@suse.de>
 <3d038b03-8b0f-46c5-a663-d1eacebaa6c9@suse.com>
 <f16445c4-e3e4-72ca-f5ee-9b5ede84de3d@suse.de>
 <888a0461-7875-411b-bde9-dd7960e1536e@suse.com>
 <CAMe9rOrdHFXyxhZhfmzrBnJFWW6ji+Mam0SPjoqASxufpX2LaA@mail.gmail.com>
Message-ID: <a21829ab-0f1a-4247-a670-12ddaf38078e@suse.com>

On 24.06.2026 02:23, H.J. Lu wrote:
> On Tue, Jun 23, 2026 at 10:22?PM Jan Beulich <jbeulich@suse.com> wrote:
>>
>> On 23.06.2026 15:54, Michael Matz wrote:
>>> On Tue, 23 Jun 2026, Jan Beulich wrote:
>>>>> I think that's a misinterpretation.  "a symbol is protected" is different
>>>>> from "a symbol has STV_PROTECTED visibility".  The former is defined in
>>>>> the section for the latter:
>>>>>
>>>>>   A symbol defined in the current component is protected if it is visible
>>>>>   in other components but cannot be preempted. Any reference to such a
>>>>>   symbol from within the defining component must be resolved to the
>>>>>   definition in that component, even if there is a definition in another
>>>>>   component that would interpose by the default rules. A symbol with
>>>>>   STB_LOCAL binding will not have STV_PROTECTED visibility.
>>>>>
>>>>> and _that definition_ is invoked by STV_HIDDEN:
>>>>>
>>>>>   A symbol defined in the current component is hidden if its name is not
>>>>>   visible to other components. Such a symbol is necessarily protected.
>>>>>
>>>>> IMHO it's clear that a symbol hence "can be protected" without having its
>>>>> visibility be STV_PROTECTED.  Namely when it is STV_HIDDEN: its then
>>>>> protected _and_ hidden (which is of course redundant, because hidden
>>>>> implies protected, but as we are word-smithing, lets be precise).
>>>>>
>>>>> That a STB_LOCAL symbol cannot have STV_PROTECTED visibility doesn't
>>>>> transfer to STV_HIDDEN from this wording, and from nothing else either,
>>>>> conceptually binding and visibility are orthogonal concepts and this
>>>>> specific disallowance for the STB_LOCAL+STV_PROTECTED combination is ...
>>>>> well, specific.  That is the wart, not that STB_LOCAL+STV_HIDDEN was
>>>>> "forgotten" to be disallowed.
>>>>
>>>> IOW what you're suggesting as interpretation is that while STV_PROTECTED
>>>> and STB_LOCAL may not combine, the visibility-wise more restricting
>>>> STV_HIDDEN may combine with STB_LOCAL?
>>>
>>> Yes.
>>>
>>>> Make no sense to me, I'm afraid.
>>>
>>> That may be, and I agree that creating such situation willingly would
>>> be suspect.  But as we just saw, such combinations might be created
>>> by an unlucky reality.
>>
>> Because of shortcomings in the tools used. I bet if there had been a
>> warning, the approach chosen would have been a different one. (The
>> approach chosen also isn't portable to non-ELF targets.)
>>
>>>  And again: binding and visiblity are _orthogonal_.
>>> One is for link-editing, the other for runtime linking.  In principle all
>>> combinations are "okay" (if questionable), and have obvious
>>> implementations.  But it's only that specific combination
>>> STB_LOCAL+STV_PROTECTED that is explicitely made ill-formed in the spec
>>> (despite it being also obviously implementable).  So, sure, warning on
>>> that combination can be done on the grounds of following the spec.  But no
>>> other combination is so spelled out, so there's no basis for trying to
>>> disallow them.
>>
>> As with many things in specs, what's spelled out and what's implied
>> is a matter of interpretation. As I think follows from earlier replies,
>> I can see that there is room for interpretation here, and hence mine
>> may not match what was intended. Yet we won't know for any other
>> interpretation either, seeing the state the ELF spec is in.
>>
>> If others are in favor of following your interpretation, then I'm not
>> going to stand in the way. But as of now it's not going to be me to
>> make a patch to that effect. I simply couldn't write a description
>> for it in good faith.
>>
>>>> (And would also make the implementation harder.)
>>>
>>> If a warning is too costly to implement, then it shouldn't be there.
>>> Though it seems surprising that checking for "is_local && is_protected"
>>> should be materially more difficult than for "is_local && !is_default_vis".
>>> (I haven't looked at the concrete patch, though).
>>
>> Well, you may be right and it's not really more complex.
>>
>> Jan
> 
> Here is the patch.

The "& ~STV_HIDDEN" is clearly bogus there. If we follow that alternative
interpretation of the spec, no warning should be issued for STV_INTERNAL
either. I'm also surprised you don't undo more of the respective testsuite
changes then (i.e. about everywhere I had added .global to avoid the
warning).

Jan

From mengqinggang@loongson.cn  Wed Jun 24 06:11:28 2026
From: mengqinggang@loongson.cn (mengqinggang)
Date: Wed, 24 Jun 2026 14:11:28 +0800
Subject: [PATCH v3] LoongArch: Fix relaxation alignment with ld -r (PR 33236)
Message-ID: <20260624061128.3917927-1-mengqinggang@loongson.cn>

LoongArch has the same issue as RISC-V for PR 33236 [1].

Section alignment can't be adjusted for objects generated by ld -r.
If previous sections are relaxed, the subsequent section maybe misaligned.

To fix this, add an align section and an align relocation before each
section when ld -r. And change the section alignment to 4 to disable
the default section start address calculation.

ld.lld has fixed this issue in the following two patches [2] [3].

[1] https://sourceware.org/bugzilla/show_bug.cgi?id=33236
[2] https://github.com/llvm/llvm-project/pull/151639
[3] https://github.com/llvm/llvm-project/pull/198147
---
v2 -> v3:
- Delete redundant comment code.

v1 -> v2:
- Remove changes in ldlang.c.
- Stop ldlang.c:size_input_section padding by changing
  the input section alignment_power.

 bfd/elfnn-loongarch.c                         | 150 +++++++++++++++
 bfd/elfxx-loongarch.h                         |  10 +
 ld/emultempl/loongarchelf.em                  | 180 ++++++++++++++++++
 .../ld-loongarch-elf/relax-align-ld-r.d       |   9 +
 .../ld-loongarch-elf/relax-align-ld-r.s       |  12 ++
 ld/testsuite/ld-loongarch-elf/relax.exp       |   1 +
 6 files changed, 362 insertions(+)
 create mode 100644 ld/testsuite/ld-loongarch-elf/relax-align-ld-r.d
 create mode 100644 ld/testsuite/ld-loongarch-elf/relax-align-ld-r.s

diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c
index b7af2041238..91b5d8d4d76 100644
--- a/bfd/elfnn-loongarch.c
+++ b/bfd/elfnn-loongarch.c
@@ -7054,6 +7054,156 @@ elf_loongarch64_hash_symbol (struct elf_link_hash_entry *h)
   return _bfd_elf_hash_symbol (h);
 }
 
+/* Write nops to align section.  */
+
+static bool
+loongarch_build_align_nops (asection *section, asection *align_section)
+{
+  if (section->output_section == NULL
+      || align_section->output_section == NULL)
+    {
+      _bfd_error_handler (_("Could not assign to an output section."));
+      return false;
+    }
+
+  bfd_byte *loc = align_section->contents;
+  for (bfd_size_type i = 0; i < (align_section->size / 4); i++)
+    {
+      bfd_putl32 (LARCH_NOP, loc);
+      loc += 4;
+    }
+
+  return true;
+}
+
+/* Emit an align relocation and a related undefined symbol.  */
+
+static bool
+loongarch_add_align_relocs (asection *align_sec, bfd* align_bfd)
+{
+  elf_backend_data *bed = get_elf_backend_data (align_bfd);
+
+  if (elf_section_data (align_sec)->relocs == NULL)
+    {
+      align_sec->reloc_count = 1;
+      align_sec->flags |= SEC_RELOC;
+
+      Elf_Internal_Rela *rela = (Elf_Internal_Rela *)
+	bfd_malloc (sizeof (Elf_Internal_Rela));
+      if (rela == NULL)
+	return false;
+
+      rela->r_offset = 0;
+      rela->r_addend = align_sec->size;
+      rela->r_info = ELFNN_R_INFO (0, R_LARCH_ALIGN);
+      elf_section_data (align_sec)->relocs = rela;
+
+      Elf_Internal_Shdr *rela_hdr = (Elf_Internal_Shdr *)
+	bfd_zalloc (align_bfd, sizeof (Elf_Internal_Shdr));
+      if (rela_hdr == NULL)
+       return false;
+
+      rela_hdr->sh_size = sizeof (Elf_Internal_Rela);
+      rela_hdr->sh_entsize = sizeof (Elf_Internal_Rela);
+      rela_hdr->sh_type = SHT_RELA;
+      rela_hdr->sh_addralign = (bfd_vma) 1 << bed->s->log_file_align;
+      elf_section_data (align_sec)->rela.hdr = rela_hdr;
+    }
+
+  /* Used in loongarch_elf_relax_section for align relocations.  */
+  Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (align_bfd);
+  if (symtab_hdr->contents == NULL)
+    {
+      Elf_Internal_Sym *sym = (Elf_Internal_Sym *)
+	bfd_zmalloc (sizeof (Elf_Internal_Sym));
+      if (sym == NULL)
+	return false;
+
+      /* Match if (r_symndx < symtab_hdr->sh_info) branch in
+	 loongarch_elf_relocate_section to avoid find link failed.  */
+      symtab_hdr->sh_info = 1;
+      symtab_hdr->contents = (unsigned char *) sym;
+    }
+
+  return true;
+}
+
+/* Section name for aligns is the associated section name plus this
+   string.  */
+#define ALIGN_SUFFIX ".align"
+
+/* Determine and set the size of the align section for a final link.  */
+
+bool
+elfNN_loongarch_size_aligns (bfd *output_bfd,
+			     bfd *align_bfd,
+			     struct bfd_link_info *info,
+			     asection * (*add_align_section)
+					  (const char *, asection *),
+			     void (*layout_sections_again) (void))
+{
+  bool need_laying_out = false;
+  for (bfd *input_bfd = info->input_bfds; input_bfd != NULL;
+       input_bfd = input_bfd->link.next)
+    {
+      asection *sec;
+      asection *align_sec;
+
+      if (!is_loongarch_elf (input_bfd)
+	  || (input_bfd->flags & BFD_LINKER_CREATED) != 0)
+	continue;
+
+      for (sec = input_bfd->sections; sec != NULL; sec = sec->next)
+	{
+	  /* If this section is not a code section, do nothing.  */
+	  if ((sec->flags & SEC_CODE) == 0)
+	    continue;
+
+	  /* If this section is a link-once section that will be
+	     discarded, then don't create any stubs.  */
+	  if (sec->output_section == NULL
+	      || sec->output_section->owner != output_bfd)
+	    continue;
+
+	  if (sec->alignment_power > 2)
+	    {
+	      char *s_name;
+	      size_t namelen;
+	      bfd_size_type len;
+	      namelen = strlen (sec->name);
+	      len = namelen + sizeof (ALIGN_SUFFIX);
+	      s_name = bfd_alloc (align_bfd, len);
+	      if (s_name == NULL)
+		return false;
+	      memcpy (s_name, sec->name, namelen);
+	      memcpy (s_name + namelen, ALIGN_SUFFIX, sizeof (ALIGN_SUFFIX));
+
+	      align_sec = add_align_section (s_name, sec);
+
+	      if (align_sec == NULL)
+		return false;
+
+	      if (! loongarch_build_align_nops (sec, align_sec))
+		return false;
+
+	      if (! loongarch_add_align_relocs (align_sec, align_bfd))
+		return false;
+
+	      /* Change the section alignment to 4 to disable the default
+		 behavior of "dot += alignment_needed" in ldlang.c.  */
+	      bfd_set_section_alignment (sec, 2);
+
+	      need_laying_out = true;
+	    }
+	}
+    }
+
+  if (need_laying_out)
+    layout_sections_again ();
+
+  return true;
+}
+
 #define TARGET_LITTLE_SYM loongarch_elfNN_vec
 #define TARGET_LITTLE_NAME "elfNN-loongarch"
 #define ELF_ARCH bfd_arch_loongarch
diff --git a/bfd/elfxx-loongarch.h b/bfd/elfxx-loongarch.h
index 400b7377ccd..b295b7a9070 100644
--- a/bfd/elfxx-loongarch.h
+++ b/bfd/elfxx-loongarch.h
@@ -45,6 +45,16 @@ bfd_elf64_loongarch_set_data_segment_info (struct bfd_link_info *, int *);
 bfd_byte *
 loongarch_write_unsigned_leb128 (bfd_byte *, size_t, bfd_vma) ATTRIBUTE_HIDDEN;
 
+extern bool elf64_loongarch_size_aligns
+  (bfd *, bfd *, struct bfd_link_info *,
+   struct bfd_section * (*) (const char *, struct bfd_section *),
+   void (*) (void));
+
+extern bool elf32_loongarch_size_aligns
+  (bfd *, bfd *, struct bfd_link_info *,
+   struct bfd_section * (*) (const char *, struct bfd_section *),
+   void (*) (void));
+
 /* TRUE if this is a PLT reference to a local IFUNC.  */
 #define PLT_LOCAL_IFUNC_P(INFO, H) \
   ((H)->dynindx == -1 \
diff --git a/ld/emultempl/loongarchelf.em b/ld/emultempl/loongarchelf.em
index 713331d30fc..901186cd114 100644
--- a/ld/emultempl/loongarchelf.em
+++ b/ld/emultempl/loongarchelf.em
@@ -41,6 +41,10 @@ PARSE_AND_LIST_ARGS_CASES=${PARSE_AND_LIST_ARGS_CASES}'
 '
 
 fragment <<EOF
+
+/* Fake input file for align.  */
+static lang_input_statement_type *align_file;
+
 static void
 larch_elf_before_allocation (void)
 {
@@ -61,6 +65,134 @@ larch_elf_before_allocation (void)
   link_info.relax_pass = 3;
 }
 
+/* Traverse the linker tree to insert the align section
+   before input section.  */
+
+static bool
+hook_in_align (lang_statement_list_type add,
+	       asection *input_section,
+	       lang_statement_union_type **lp)
+{
+  bool ret;
+  lang_statement_union_type *l;
+
+  for (; (l = *lp) != NULL; lp = &l->header.next)
+    {
+      switch (l->header.type)
+	{
+	case lang_constructors_statement_enum:
+	  ret = hook_in_align (add, input_section, &constructor_list.head);
+	  if (ret)
+	    return ret;
+	  break;
+
+	case lang_output_section_statement_enum:
+	  ret = hook_in_align (add, input_section,
+			       &l->output_section_statement.children.head);
+	  if (ret)
+	    return ret;
+	  break;
+
+	case lang_wild_statement_enum:
+	  ret = hook_in_align (add, input_section,
+			       &l->wild_statement.children.head);
+	  if (ret)
+	    return ret;
+	  break;
+
+	case lang_group_statement_enum:
+	  ret = hook_in_align (add, input_section,
+			       &l->group_statement.children.head);
+	  if (ret)
+	    return ret;
+	  break;
+
+	case lang_input_section_enum:
+	  if (l->input_section.section == input_section)
+	    {
+	      /* We've found our section.  Insert the align immediately
+		 before its associated input section.  */
+	      *lp = add.head;
+	      add.head->header.next = l;
+	      return true;
+	    }
+	  break;
+
+	case lang_data_statement_enum:
+	case lang_reloc_statement_enum:
+	case lang_object_symbols_statement_enum:
+	case lang_output_statement_enum:
+	case lang_target_statement_enum:
+	case lang_input_statement_enum:
+	case lang_assignment_statement_enum:
+	case lang_padding_statement_enum:
+	case lang_address_statement_enum:
+	case lang_fill_statement_enum:
+	  break;
+
+	default:
+	  FAIL ();
+	  break;
+	}
+    }
+
+  return false;
+}
+
+/* Create a new align section, and arrange for it to be linked
+   immediately before INPUT_SECTION.  */
+
+static asection *
+elf${ELFSIZE}_loongarch_add_align_section (const char *align_sec_name,
+					   asection *input_section)
+{
+  flagword flags;
+  asection *align_sec;
+  asection *output_section;
+  lang_statement_list_type add_child;
+  lang_output_section_statement_type *os;
+
+  flags = (SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
+	   | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY | SEC_KEEP);
+  align_sec = bfd_make_section_anyway_with_flags (align_file->the_bfd,
+						  align_sec_name, flags);
+  if (align_sec == NULL)
+    goto err_ret;
+
+  align_sec->veneer = 1;
+  bfd_set_section_alignment (align_sec, 2);
+
+  output_section = input_section->output_section;
+  os = lang_output_section_get (output_section);
+
+  lang_list_init (&add_child);
+  lang_add_section (&add_child, align_sec, NULL, NULL, os);
+
+  if (add_child.head == NULL)
+    goto err_ret;
+
+  align_sec->size = (1 << input_section->alignment_power) - 4;
+  align_sec->contents = bfd_alloc (align_file->the_bfd, align_sec->size);
+  if (align_sec->contents == NULL && align_sec->size != 0)
+    goto err_ret;
+  align_sec->alloced = 1;
+
+  if (hook_in_align (add_child, input_section, &os->children.head))
+    return align_sec;
+
+ err_ret:
+  einfo (_("%X%P: can not make align section: %E\n"));
+  return NULL;
+}
+
+static void
+gldloongarch_layout_sections_again (void)
+{
+  /* If we have changed sizes of the align sections, then we need
+     to recalculate all the section offsets.  */
+  ldelf_map_segments (true);
+}
+
 static void
 gld${EMULATION_NAME}_after_allocation (void)
 {
@@ -78,6 +210,21 @@ gld${EMULATION_NAME}_after_allocation (void)
 	}
     }
 
+  /* If generating a relocatable output file, we have to add align
+     at the start of sections.  */
+  if (align_file != NULL && bfd_link_relocatable (&link_info))
+    {
+      if (! elf${ELFSIZE}_loongarch_size_aligns (link_info.output_bfd,
+			align_file->the_bfd,
+			&link_info,
+			&elf${ELFSIZE}_loongarch_add_align_section,
+			&gldloongarch_layout_sections_again))
+	{
+	  einfo (_("%X%P: can not size align section: %E\n"));
+	  return;
+	}
+    }
+
   /* The program header size of executable file may increase.  */
   if (bfd_get_flavour (link_info.output_bfd) == bfd_target_elf_flavour
       && !bfd_link_relocatable (&link_info))
@@ -101,7 +248,40 @@ gld${EMULATION_NAME}_after_allocation (void)
   ldelf_map_segments (need_layout);
 }
 
+/* This is called before the input files are opened.  We create a new
+   fake input file to hold the align sections.  */
+
+static void
+loongarch_elf_create_output_section_statements (void)
+{
+  if (! bfd_link_relocatable (&link_info))
+    return;
+
+  align_file = lang_add_input_file ("linker aligns",
+				    lang_input_file_is_fake_enum,
+				    NULL);
+  align_file->the_bfd = bfd_create ("linker aligns",
+				    link_info.output_bfd);
+  if (align_file->the_bfd == NULL
+      || ! bfd_set_arch_mach (align_file->the_bfd,
+			      bfd_get_arch (link_info.output_bfd),
+			      bfd_get_mach (link_info.output_bfd)))
+    {
+      fatal (_("%P: can not create BFD: %E\n"));
+      return;
+    }
+
+  align_file->the_bfd->flags |= BFD_LINKER_CREATED;
+
+  Elf_Internal_Ehdr *ehdr = elf_elfheader (align_file->the_bfd);
+  elf_backend_data *bed = get_elf_backend_data (link_info.output_bfd);
+  ehdr->e_ident[EI_CLASS] = bed->s->elfclass;
+
+  ldlang_add_file (align_file);
+}
+
 EOF
 
 LDEMUL_BEFORE_ALLOCATION=larch_elf_before_allocation
 LDEMUL_AFTER_ALLOCATION=gld${EMULATION_NAME}_after_allocation
+LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS=loongarch_elf_create_output_section_statements
diff --git a/ld/testsuite/ld-loongarch-elf/relax-align-ld-r.d b/ld/testsuite/ld-loongarch-elf/relax-align-ld-r.d
new file mode 100644
index 00000000000..a2d19734a59
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/relax-align-ld-r.d
@@ -0,0 +1,9 @@
+#as:
+#ld: -r
+#objdump: -Dr
+
+#...
+.*R_LARCH_ALIGN.*
+#...
+.*R_LARCH_ALIGN.*
+#...
diff --git a/ld/testsuite/ld-loongarch-elf/relax-align-ld-r.s b/ld/testsuite/ld-loongarch-elf/relax-align-ld-r.s
new file mode 100644
index 00000000000..19555a7148e
--- /dev/null
+++ b/ld/testsuite/ld-loongarch-elf/relax-align-ld-r.s
@@ -0,0 +1,12 @@
+# Add an align section before text section when ld -r.
+# There will be two R_LARCH_ALIGN relocations after ld -r.
+.text
+  addi.d $a0, $a0, 1
+  call36 func
+  .align 3
+func:
+  addi.d $a0, $a0, 1
+
+# Only add a align section for code section.
+.data
+  .4byte 0x1234
diff --git a/ld/testsuite/ld-loongarch-elf/relax.exp b/ld/testsuite/ld-loongarch-elf/relax.exp
index 31787a93967..bb8429ab515 100644
--- a/ld/testsuite/ld-loongarch-elf/relax.exp
+++ b/ld/testsuite/ld-loongarch-elf/relax.exp
@@ -48,6 +48,7 @@ proc run_partial_linking_align_test {} {
 
 if [istarget loongarch*-*-*] {
   run_dump_test "relax-align-1"
+  run_dump_test "relax-align-ld-r"
 }
 
 if [istarget loongarch64-*-*] {
-- 
2.34.1


From i@maskray.me  Wed Jun 24 06:19:21 2026
From: i@maskray.me (Fangrui Song)
Date: Tue, 23 Jun 2026 23:19:21 -0700
Subject: [PATCH 2/3] gas/ELF: warn upon non-default visibility of local
 symbols
In-Reply-To: <888a0461-7875-411b-bde9-dd7960e1536e@suse.com>
References: <bcd40b22-b90f-4334-8ab4-e8afeea2a6a9@suse.com>
 <193f86ed-f34b-4da8-9eac-68005830d369@suse.com>
 <e6007e9e-2cb7-4635-a974-5f753b212133@arm.com>
 <1397563c-32ca-4343-9587-99c197dd4029@suse.com>
 <b4ec2334-1821-4780-9876-f8a12d20dc4b@suse.com>
 <CAMe9rOoqhA+o278P+bPWOvHSxENbjyiN=o+Goep-6MUt2--_-w@mail.gmail.com>
 <e43bc9d8-260e-46f1-9afc-c52eacd4ac60@suse.com>
 <CAMe9rOpVyKapj7FrC1k+MZRqO1J+FZhq-HnfarzpuPedkJ0snA@mail.gmail.com>
 <67a1182c-e7d0-40ad-98ec-9b49c1d28410@suse.com>
 <17f9a3cc-7994-ad25-692b-e3e9441ff481@suse.de>
 <3d038b03-8b0f-46c5-a663-d1eacebaa6c9@suse.com>
 <f16445c4-e3e4-72ca-f5ee-9b5ede84de3d@suse.de>
 <888a0461-7875-411b-bde9-dd7960e1536e@suse.com>
Message-ID: <CAN30aBFZws88BF4QVYs_EdR=h7RXDWP+SsCt7Wj81mKUnwhTyA@mail.gmail.com>

On Tue, Jun 23, 2026 at 7:23?AM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 23.06.2026 15:54, Michael Matz wrote:
> > On Tue, 23 Jun 2026, Jan Beulich wrote:
> >>> I think that's a misinterpretation.  "a symbol is protected" is different
> >>> from "a symbol has STV_PROTECTED visibility".  The former is defined in
> >>> the section for the latter:
> >>>
> >>>   A symbol defined in the current component is protected if it is visible
> >>>   in other components but cannot be preempted. Any reference to such a
> >>>   symbol from within the defining component must be resolved to the
> >>>   definition in that component, even if there is a definition in another
> >>>   component that would interpose by the default rules. A symbol with
> >>>   STB_LOCAL binding will not have STV_PROTECTED visibility.
> >>>
> >>> and _that definition_ is invoked by STV_HIDDEN:
> >>>
> >>>   A symbol defined in the current component is hidden if its name is not
> >>>   visible to other components. Such a symbol is necessarily protected.
> >>>
> >>> IMHO it's clear that a symbol hence "can be protected" without having its
> >>> visibility be STV_PROTECTED.  Namely when it is STV_HIDDEN: its then
> >>> protected _and_ hidden (which is of course redundant, because hidden
> >>> implies protected, but as we are word-smithing, lets be precise).
> >>>
> >>> That a STB_LOCAL symbol cannot have STV_PROTECTED visibility doesn't
> >>> transfer to STV_HIDDEN from this wording, and from nothing else either,
> >>> conceptually binding and visibility are orthogonal concepts and this
> >>> specific disallowance for the STB_LOCAL+STV_PROTECTED combination is ...
> >>> well, specific.  That is the wart, not that STB_LOCAL+STV_HIDDEN was
> >>> "forgotten" to be disallowed.
> >>
> >> IOW what you're suggesting as interpretation is that while STV_PROTECTED
> >> and STB_LOCAL may not combine, the visibility-wise more restricting
> >> STV_HIDDEN may combine with STB_LOCAL?
> >
> > Yes.
> >
> >> Make no sense to me, I'm afraid.
> >
> > That may be, and I agree that creating such situation willingly would
> > be suspect.  But as we just saw, such combinations might be created
> > by an unlucky reality.
>
> Because of shortcomings in the tools used. I bet if there had been a
> warning, the approach chosen would have been a different one. (The
> approach chosen also isn't portable to non-ELF targets.)
>
> >  And again: binding and visiblity are _orthogonal_.
> > One is for link-editing, the other for runtime linking.  In principle all
> > combinations are "okay" (if questionable), and have obvious
> > implementations.  But it's only that specific combination
> > STB_LOCAL+STV_PROTECTED that is explicitely made ill-formed in the spec
> > (despite it being also obviously implementable).  So, sure, warning on
> > that combination can be done on the grounds of following the spec.  But no
> > other combination is so spelled out, so there's no basis for trying to
> > disallow them.
>
> As with many things in specs, what's spelled out and what's implied
> is a matter of interpretation. As I think follows from earlier replies,
> I can see that there is room for interpretation here, and hence mine
> may not match what was intended. Yet we won't know for any other
> interpretation either, seeing the state the ELF spec is in.
>
> If others are in favor of following your interpretation, then I'm not
> going to stand in the way. But as of now it's not going to be me to
> make a patch to that effect. I simply couldn't write a description
> for it in good faith.
>
> >> (And would also make the implementation harder.)
> >
> > If a warning is too costly to implement, then it shouldn't be there.
> > Though it seems surprising that checking for "is_local && is_protected"
> > should be materially more difficult than for "is_local && !is_default_vis".
> > (I haven't looked at the concrete patch, though).
>
> Well, you may be right and it's not really more complex.
>
> Jan

Since known ELF linkers ignore visibility on STB_LOCAL symbols, this
warning is likely unnecessary. We shouldn't over-read the gABI rule
stating that "A symbol with STB_LOCAL binding may not have
STV_PROTECTED visibility."
For STV_HIDDEN, linkers are required to convert the symbol to
STB_LOCAL. Retaining STV_HIDDEN is useful because it documents why the
symbol became STB_LOCAL in the first place.
It's natural to allow STV_HIDDEN/STB_LOCAL in assemblers as well.

From hjl.tools@gmail.com  Wed Jun 24 10:37:57 2026
From: hjl.tools@gmail.com (H.J. Lu)
Date: Wed, 24 Jun 2026 18:37:57 +0800
Subject: [PATCH v2] gas/ELF: Allow local symbol with non-protected visibility
In-Reply-To: <a21829ab-0f1a-4247-a670-12ddaf38078e@suse.com>
References: <bcd40b22-b90f-4334-8ab4-e8afeea2a6a9@suse.com>
 <193f86ed-f34b-4da8-9eac-68005830d369@suse.com>
 <e6007e9e-2cb7-4635-a974-5f753b212133@arm.com>
 <1397563c-32ca-4343-9587-99c197dd4029@suse.com>
 <b4ec2334-1821-4780-9876-f8a12d20dc4b@suse.com>
 <CAMe9rOoqhA+o278P+bPWOvHSxENbjyiN=o+Goep-6MUt2--_-w@mail.gmail.com>
 <e43bc9d8-260e-46f1-9afc-c52eacd4ac60@suse.com>
 <CAMe9rOpVyKapj7FrC1k+MZRqO1J+FZhq-HnfarzpuPedkJ0snA@mail.gmail.com>
 <67a1182c-e7d0-40ad-98ec-9b49c1d28410@suse.com>
 <17f9a3cc-7994-ad25-692b-e3e9441ff481@suse.de>
 <3d038b03-8b0f-46c5-a663-d1eacebaa6c9@suse.com>
 <f16445c4-e3e4-72ca-f5ee-9b5ede84de3d@suse.de>
 <888a0461-7875-411b-bde9-dd7960e1536e@suse.com>
 <CAMe9rOrdHFXyxhZhfmzrBnJFWW6ji+Mam0SPjoqASxufpX2LaA@mail.gmail.com>
 <a21829ab-0f1a-4247-a670-12ddaf38078e@suse.com>
Message-ID: <CAMe9rOrLRxD0iA3gjQhi=Qh_iRbHhuV2EkKu1u7UuzbS2fAzpA@mail.gmail.com>

On Wed, Jun 24, 2026 at 1:59?PM Jan Beulich <jbeulich@suse.com> wrote:
>
> On 24.06.2026 02:23, H.J. Lu wrote:
> > On Tue, Jun 23, 2026 at 10:22?PM Jan Beulich <jbeulich@suse.com> wrote:
> >>
> >> On 23.06.2026 15:54, Michael Matz wrote:
> >>> On Tue, 23 Jun 2026, Jan Beulich wrote:
> >>>>> I think that's a misinterpretation.  "a symbol is protected" is different
> >>>>> from "a symbol has STV_PROTECTED visibility".  The former is defined in
> >>>>> the section for the latter:
> >>>>>
> >>>>>   A symbol defined in the current component is protected if it is visible
> >>>>>   in other components but cannot be preempted. Any reference to such a
> >>>>>   symbol from within the defining component must be resolved to the
> >>>>>   definition in that component, even if there is a definition in another
> >>>>>   component that would interpose by the default rules. A symbol with
> >>>>>   STB_LOCAL binding will not have STV_PROTECTED visibility.
> >>>>>
> >>>>> and _that definition_ is invoked by STV_HIDDEN:
> >>>>>
> >>>>>   A symbol defined in the current component is hidden if its name is not
> >>>>>   visible to other components. Such a symbol is necessarily protected.
> >>>>>
> >>>>> IMHO it's clear that a symbol hence "can be protected" without having its
> >>>>> visibility be STV_PROTECTED.  Namely when it is STV_HIDDEN: its then
> >>>>> protected _and_ hidden (which is of course redundant, because hidden
> >>>>> implies protected, but as we are word-smithing, lets be precise).
> >>>>>
> >>>>> That a STB_LOCAL symbol cannot have STV_PROTECTED visibility doesn't
> >>>>> transfer to STV_HIDDEN from this wording, and from nothing else either,
> >>>>> conceptually binding and visibility are orthogonal concepts and this
> >>>>> specific disallowance for the STB_LOCAL+STV_PROTECTED combination is ...
> >>>>> well, specific.  That is the wart, not that STB_LOCAL+STV_HIDDEN was
> >>>>> "forgotten" to be disallowed.
> >>>>
> >>>> IOW what you're suggesting as interpretation is that while STV_PROTECTED
> >>>> and STB_LOCAL may not combine, the visibility-wise more restricting
> >>>> STV_HIDDEN may combine with STB_LOCAL?
> >>>
> >>> Yes.
> >>>
> >>>> Make no sense to me, I'm afraid.
> >>>
> >>> That may be, and I agree that creating such situation willingly would
> >>> be suspect.  But as we just saw, such combinations might be created
> >>> by an unlucky reality.
> >>
> >> Because of shortcomings in the tools used. I bet if there had been a
> >> warning, the approach chosen would have been a different one. (The
> >> approach chosen also isn't portable to non-ELF targets.)
> >>
> >>>  And again: binding and visiblity are _orthogonal_.
> >>> One is for link-editing, the other for runtime linking.  In principle all
> >>> combinations are "okay" (if questionable), and have obvious
> >>> implementations.  But it's only that specific combination
> >>> STB_LOCAL+STV_PROTECTED that is explicitely made ill-formed in the spec
> >>> (despite it being also obviously implementable).  So, sure, warning on
> >>> that combination can be done on the grounds of following the spec.  But no
> >>> other combination is so spelled out, so there's no basis for trying to
> >>> disallow them.
> >>
> >> As with many things in specs, what's spelled out and what's implied
> >> is a matter of interpretation. As I think follows from earlier replies,
> >> I can see that there is room for interpretation here, and hence mine
> >> may not match what was intended. Yet we won't know for any other
> >> interpretation either, seeing the state the ELF spec is in.
> >>
> >> If others are in favor of following your interpretation, then I'm not
> >> going to stand in the way. But as of now it's not going to be me to
> >> make a patch to that effect. I simply couldn't write a description
> >> for it in good faith.
> >>
> >>>> (And would also make the implementation harder.)
> >>>
> >>> If a warning is too costly to implement, then it shouldn't be there.
> >>> Though it seems surprising that checking for "is_local && is_protected"
> >>> should be materially more difficult than for "is_local && !is_default_vis".
> >>> (I haven't looked at the concrete patch, though).
> >>
> >> Well, you may be right and it's not really more complex.
> >>
> >> Jan
> >
> > Here is the patch.
>
> The "& ~STV_HIDDEN" is clearly bogus there. If we follow that alternative
> interpretation of the spec, no warning should be issued for STV_INTERNAL
> either. I'm also surprised you don't undo more of the respective testsuite
> changes then (i.e. about everywhere I had added .global to avoid the
> warning).
>
> Jan

Here is the v2 path to partially revert:

commit c4150acbda1b3ce0602f79cbb7700b39e577be7e
Author: Jan Beulich <jbeulich@suse.com>
Date:   Fri May 8 11:45:04 2026 +0200

    gas/ELF: warn upon non-default visibility of local symbols

and update elf_adjust_symtab to only warn local symbol with protected
visibility.


-- 
H.J.
---
In the source code extracted from glibc:

extern void _dl_sysinfo_int80 (void)
  __attribute__ ((visibility ("hidden")));

asm (".text\n\t"
     ".type _dl_sysinfo_int80,@function\n"
     "_dl_sysinfo_int80:\n\t"
     "int $0x80;\n\t"
     "ret");

uintptr_t
foo ()
{
  return (uintptr_t) _dl_sysinfo_int80;
}

_dl_sysinfo_int80 is a local function, but it is defined in an asm
statement.  Since it is referenced in C, it is declared as hidden,
which leads to an assembler warning:

Warning: local symbol `_dl_sysinfo_int80' has non-default visibility

Symbol binding and visiblity are orthogonal.  One is for link-editing,
the other for runtime linking.  In principle, all combinations are "okay"
(if questionable), and have obvious implementations.  But it's only that
specific combination STB_LOCAL+STV_PROTECTED that is explicitely made
ill-formed in the spec (despite it being also obviously implementable).
Warning on that combination can be done on the grounds of following the
spec.  But no other combination is so spelled out, so there's no basis
for trying to disallow them.

Partially revert:

commit c4150acbda1b3ce0602f79cbb7700b39e577be7e
Author: Jan Beulich <jbeulich@suse.com>
Date:   Fri May 8 11:45:04 2026 +0200

    gas/ELF: warn upon non-default visibility of local symbols

and update elf_adjust_symtab to only warn local symbol with protected
visibility.

binutils/

PR gas/34312
* testsuite/binutils-all/localize-hidden-1.l: Adjusted.
* testsuite/binutils-all/nm-ver.s: Revert commit c4150acbda1.

gas/

PR gas/34312
* config/obj-elf.c (elf_adjust_symtab): Allow local symbol with
non-protected visibility.
* testsuite/gas/elf/visibility.l: Adjusted.
* testsuite/gas/i386/tlsnopic.s: Revert commit c4150acbda1.

ld/

PR gas/34312
* testsuite/ld-aarch64/ifunc-21.s: Revert commit c4150acbda1.
* testsuite/ld-aarch64/ifunc-21.s: Likewise.
* testsuite/ld-tic6x/shlib-1.rd: Likewise.
* testsuite/ld-tic6x/shlib-1.s: Likewise.
* testsuite/ld-tic6x/shlib-1b.rd: Likewise.
* testsuite/ld-tic6x/shlib-1r.dd: Likewise.
* testsuite/ld-tic6x/shlib-1r.rd: Likewise.
* testsuite/ld-tic6x/shlib-1rb.dd: Likewise.
* testsuite/ld-tic6x/shlib-1rb.rd: Likewise.
* testsuite/ld-tic6x/shlib-noindex.rd: Likewise.
* testsuite/ld-tic6x/static-app-1.rd: Likewise.
* testsuite/ld-tic6x/static-app-1b.rd: Likewise.
* testsuite/ld-tic6x/static-app-1r.dd: Likewise.
* testsuite/ld-tic6x/static-app-1r.rd: Likewise.
* testsuite/ld-tic6x/static-app-1rb.dd: Likewise.
* testsuite/ld-tic6x/static-app-1rb.rd: Likewise.
-------------- next part --------------
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From jbeulich@suse.com  Wed Jun 24 12:37:26 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Wed, 24 Jun 2026 14:37:26 +0200
Subject: [PATCH v2] gas/ELF: Allow local symbol with non-protected
 visibility
In-Reply-To: <CAMe9rOrLRxD0iA3gjQhi=Qh_iRbHhuV2EkKu1u7UuzbS2fAzpA@mail.gmail.com>
References: <bcd40b22-b90f-4334-8ab4-e8afeea2a6a9@suse.com>
 <193f86ed-f34b-4da8-9eac-68005830d369@suse.com>
 <e6007e9e-2cb7-4635-a974-5f753b212133@arm.com>
 <1397563c-32ca-4343-9587-99c197dd4029@suse.com>
 <b4ec2334-1821-4780-9876-f8a12d20dc4b@suse.com>
 <CAMe9rOoqhA+o278P+bPWOvHSxENbjyiN=o+Goep-6MUt2--_-w@mail.gmail.com>
 <e43bc9d8-260e-46f1-9afc-c52eacd4ac60@suse.com>
 <CAMe9rOpVyKapj7FrC1k+MZRqO1J+FZhq-HnfarzpuPedkJ0snA@mail.gmail.com>
 <67a1182c-e7d0-40ad-98ec-9b49c1d28410@suse.com>
 <17f9a3cc-7994-ad25-692b-e3e9441ff481@suse.de>
 <3d038b03-8b0f-46c5-a663-d1eacebaa6c9@suse.com>
 <f16445c4-e3e4-72ca-f5ee-9b5ede84de3d@suse.de>
 <888a0461-7875-411b-bde9-dd7960e1536e@suse.com>
 <CAMe9rOrdHFXyxhZhfmzrBnJFWW6ji+Mam0SPjoqASxufpX2LaA@mail.gmail.com>
 <a21829ab-0f1a-4247-a670-12ddaf38078e@suse.com>
 <CAMe9rOrLRxD0iA3gjQhi=Qh_iRbHhuV2EkKu1u7UuzbS2fAzpA@mail.gmail.com>
Message-ID: <dfa87cdf-a814-4135-875b-90269126d37d@suse.com>

On 24.06.2026 12:37, H.J. Lu wrote:
> Here is the v2 path to partially revert:
> 
> commit c4150acbda1b3ce0602f79cbb7700b39e577be7e
> Author: Jan Beulich <jbeulich@suse.com>
> Date:   Fri May 8 11:45:04 2026 +0200
> 
>     gas/ELF: warn upon non-default visibility of local symbols
> 
> and update elf_adjust_symtab to only warn local symbol with protected
> visibility.

Looks plausible to me now, yet as indicated I'm not going to approve it.
I'm merely not going to stand in the way.

Jan

From jeffrey.law@oss.qualcomm.com  Wed Jun 24 14:51:36 2026
From: jeffrey.law@oss.qualcomm.com (Jeffrey Law)
Date: Wed, 24 Jun 2026 08:51:36 -0600
Subject: [PATCH] RISC-V: Add support for Smpmpmt v0.6 extension
In-Reply-To: <20251105032623.50510-1-jerry.zhangjian@sifive.com>
References: <20251105032623.50510-1-jerry.zhangjian@sifive.com>
Message-ID: <e6678628-d55a-4ae7-9e95-718ce11f1709@oss.qualcomm.com>



On 11/4/2025 8:26 PM, Jerry Zhang Jian wrote:
> This implements the Smpmpmt (PMP-based Memory Types) extension,
> version 0.6[1].
>
> The Smpmpmt extension provides a mechanism to control memory
> attributes at the granularity of PMP regions, analogous to Svpbmt
> but associated with PMP registers rather than page-table entries.
>
> The extension is currently in frozen state[2].
>
> [1]https://github.com/riscv/riscv-isa-manual/blob/smpmpmt/src/smpmpmt.adoc
> [2]https://riscv.atlassian.net/browse/RVS-2948
>
> bfd/ChangeLog:
>
> 	* elfxx-riscv.c: Add Smpmpmt v0.6 extension.
>
> gas/ChangeLog:
>
> 	* NEWS: Updated.
> 	* testsuite/gas/riscv/march-help.l: Ditto.
>
> Signed-off-by: Jerry Zhang Jian<jerry.zhangjian@sifive.com>
I made the trivial updates as this spec has moved to v1.0 and moved the 
NEWS entry and pushed this.

Jeff


From builder@sourceware.org  Wed Jun 24 15:39:16 2026
From: builder@sourceware.org (builder@sourceware.org)
Date: Wed, 24 Jun 2026 15:39:16 +0000
Subject: =?utf-8?q?=E2=98=A0_Buildbot_=28Sourceware=29=3A_binutils-gdb_-_failed_test_=28failure=29_=28master=29?=
Message-ID: <20260624153916.88EAB4BA543C@sourceware.org>

A new failure has been detected on builder binutils-ubuntu-riscv while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/283/builds/3193

Build state: failed test (failure)
Revision: e56bd09181016800870de47c1f3a1091f71d9120
Worker: starfive-2
Build Reason: (unknown)
Blamelist: Aditya Kamath <Aditya.Kamath1@ibm.com>, Andrew Burgess <aburgess@redhat.com>, Guinevere Larsen <guinevere@redhat.com>, Jerry Zhang Jian <jerry.zhangjian@sifive.com>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/3/logs/config_log

- 4: make ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/4/logs/stdio
        - warnings (12): https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/4/logs/warnings__12_

- 5: make check (no ld) ( failure )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/5/logs/stdio
        - gas.sum: https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/5/logs/gas_sum
        - gas.log: https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/5/logs/gas_log
        - binutils.sum: https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/5/logs/binutils_sum
        - binutils.log: https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/5/logs/binutils_log
        - libsframe.sum: https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/5/logs/libsframe_sum
        - libsframe.log: https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/5/logs/libsframe_log
        - libctf.sum: https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/5/logs/libctf_sum
        - libctf.log: https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/5/logs/libctf_log
        - warnings (8): https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/5/logs/warnings__8_

- 6: make check ld ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/6/logs/stdio
        - ld.sum: https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/6/logs/ld_sum
        - ld.log: https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/6/logs/ld_log
        - warnings (2): https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/6/logs/warnings__2_

- 7: prep ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/7/logs/stdio

- 8: collect system versions ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/8/logs/stdio

- 9: fetch .bunsen.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/9/logs/stdio

- 10: build bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/10/logs/stdio

- 11: fetch bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/11/logs/stdio

- 12: unpack bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/12/logs/stdio

- 13: pass .bunsen.source.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/13/logs/stdio

- 14: upload to bunsen ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/14/logs/stdio

- 15: clean up ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/15/logs/stdio

- 16: rm -rf binutils-build_1 ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3193/steps/16/logs/stdio


From amodra@gmail.com  Thu Jun 25 01:28:07 2026
From: amodra@gmail.com (Alan Modra)
Date: Thu, 25 Jun 2026 10:58:07 +0930
Subject: [PATCH 2/3] gas/ELF: warn upon non-default visibility of local
 symbols
In-Reply-To: <CAN30aBFZws88BF4QVYs_EdR=h7RXDWP+SsCt7Wj81mKUnwhTyA@mail.gmail.com>
References: <b4ec2334-1821-4780-9876-f8a12d20dc4b@suse.com>
 <CAMe9rOoqhA+o278P+bPWOvHSxENbjyiN=o+Goep-6MUt2--_-w@mail.gmail.com>
 <e43bc9d8-260e-46f1-9afc-c52eacd4ac60@suse.com>
 <CAMe9rOpVyKapj7FrC1k+MZRqO1J+FZhq-HnfarzpuPedkJ0snA@mail.gmail.com>
 <67a1182c-e7d0-40ad-98ec-9b49c1d28410@suse.com>
 <17f9a3cc-7994-ad25-692b-e3e9441ff481@suse.de>
 <3d038b03-8b0f-46c5-a663-d1eacebaa6c9@suse.com>
 <f16445c4-e3e4-72ca-f5ee-9b5ede84de3d@suse.de>
 <888a0461-7875-411b-bde9-dd7960e1536e@suse.com>
 <CAN30aBFZws88BF4QVYs_EdR=h7RXDWP+SsCt7Wj81mKUnwhTyA@mail.gmail.com>
Message-ID: <ajyEJ7hTx1rpqj6g@squeak.grove.modra.org>

On Tue, Jun 23, 2026 at 11:19:21PM -0700, Fangrui Song wrote:
> On Tue, Jun 23, 2026 at 7:23?AM Jan Beulich <jbeulich@suse.com> wrote:
> >
> > On 23.06.2026 15:54, Michael Matz wrote:
> > > On Tue, 23 Jun 2026, Jan Beulich wrote:
> > >>> I think that's a misinterpretation.  "a symbol is protected" is different
> > >>> from "a symbol has STV_PROTECTED visibility".  The former is defined in
> > >>> the section for the latter:
> > >>>
> > >>>   A symbol defined in the current component is protected if it is visible
> > >>>   in other components but cannot be preempted. Any reference to such a
> > >>>   symbol from within the defining component must be resolved to the
> > >>>   definition in that component, even if there is a definition in another
> > >>>   component that would interpose by the default rules. A symbol with
> > >>>   STB_LOCAL binding will not have STV_PROTECTED visibility.
> > >>>
> > >>> and _that definition_ is invoked by STV_HIDDEN:
> > >>>
> > >>>   A symbol defined in the current component is hidden if its name is not
> > >>>   visible to other components. Such a symbol is necessarily protected.
> > >>>
> > >>> IMHO it's clear that a symbol hence "can be protected" without having its
> > >>> visibility be STV_PROTECTED.  Namely when it is STV_HIDDEN: its then
> > >>> protected _and_ hidden (which is of course redundant, because hidden
> > >>> implies protected, but as we are word-smithing, lets be precise).
> > >>>
> > >>> That a STB_LOCAL symbol cannot have STV_PROTECTED visibility doesn't
> > >>> transfer to STV_HIDDEN from this wording, and from nothing else either,
> > >>> conceptually binding and visibility are orthogonal concepts and this
> > >>> specific disallowance for the STB_LOCAL+STV_PROTECTED combination is ...
> > >>> well, specific.  That is the wart, not that STB_LOCAL+STV_HIDDEN was
> > >>> "forgotten" to be disallowed.
> > >>
> > >> IOW what you're suggesting as interpretation is that while STV_PROTECTED
> > >> and STB_LOCAL may not combine, the visibility-wise more restricting
> > >> STV_HIDDEN may combine with STB_LOCAL?
> > >
> > > Yes.
> > >
> > >> Make no sense to me, I'm afraid.
> > >
> > > That may be, and I agree that creating such situation willingly would
> > > be suspect.  But as we just saw, such combinations might be created
> > > by an unlucky reality.
> >
> > Because of shortcomings in the tools used. I bet if there had been a
> > warning, the approach chosen would have been a different one. (The
> > approach chosen also isn't portable to non-ELF targets.)
> >
> > >  And again: binding and visiblity are _orthogonal_.
> > > One is for link-editing, the other for runtime linking.  In principle all
> > > combinations are "okay" (if questionable), and have obvious
> > > implementations.  But it's only that specific combination
> > > STB_LOCAL+STV_PROTECTED that is explicitely made ill-formed in the spec
> > > (despite it being also obviously implementable).  So, sure, warning on
> > > that combination can be done on the grounds of following the spec.  But no
> > > other combination is so spelled out, so there's no basis for trying to
> > > disallow them.
> >
> > As with many things in specs, what's spelled out and what's implied
> > is a matter of interpretation. As I think follows from earlier replies,
> > I can see that there is room for interpretation here, and hence mine
> > may not match what was intended. Yet we won't know for any other
> > interpretation either, seeing the state the ELF spec is in.
> >
> > If others are in favor of following your interpretation, then I'm not
> > going to stand in the way. But as of now it's not going to be me to
> > make a patch to that effect. I simply couldn't write a description
> > for it in good faith.
> >
> > >> (And would also make the implementation harder.)
> > >
> > > If a warning is too costly to implement, then it shouldn't be there.
> > > Though it seems surprising that checking for "is_local && is_protected"
> > > should be materially more difficult than for "is_local && !is_default_vis".
> > > (I haven't looked at the concrete patch, though).
> >
> > Well, you may be right and it's not really more complex.
> >
> > Jan
> 
> Since known ELF linkers ignore visibility on STB_LOCAL symbols, this
> warning is likely unnecessary.

I agree.

> We shouldn't over-read the gABI rule
> stating that "A symbol with STB_LOCAL binding may not have
> STV_PROTECTED visibility."

Yes, the gABI could have omitted the rule you quote and simply stated
that symbol binding takes precedence over visibility.

I see some utility in gas warning about local protected symbols
because it is a contradiction, with STV_PROTETED "visible in other
components but not preemptable" while STB_LOCAL is "not visible
outside the object file containing their definition".  So perhaps
worth warning naive users that ".protected" doesn't make a symbol
global.

> For STV_HIDDEN, linkers are required to convert the symbol to
> STB_LOCAL. Retaining STV_HIDDEN is useful because it documents why the
> symbol became STB_LOCAL in the first place.
> It's natural to allow STV_HIDDEN/STB_LOCAL in assemblers as well.

-- 
Alan Modra

From amodra@gmail.com  Thu Jun 25 01:30:02 2026
From: amodra@gmail.com (Alan Modra)
Date: Thu, 25 Jun 2026 11:00:02 +0930
Subject: [PATCH v2] gas/ELF: Allow local symbol with non-protected
 visibility
In-Reply-To: <CAMe9rOrLRxD0iA3gjQhi=Qh_iRbHhuV2EkKu1u7UuzbS2fAzpA@mail.gmail.com>
References: <e43bc9d8-260e-46f1-9afc-c52eacd4ac60@suse.com>
 <CAMe9rOpVyKapj7FrC1k+MZRqO1J+FZhq-HnfarzpuPedkJ0snA@mail.gmail.com>
 <67a1182c-e7d0-40ad-98ec-9b49c1d28410@suse.com>
 <17f9a3cc-7994-ad25-692b-e3e9441ff481@suse.de>
 <3d038b03-8b0f-46c5-a663-d1eacebaa6c9@suse.com>
 <f16445c4-e3e4-72ca-f5ee-9b5ede84de3d@suse.de>
 <888a0461-7875-411b-bde9-dd7960e1536e@suse.com>
 <CAMe9rOrdHFXyxhZhfmzrBnJFWW6ji+Mam0SPjoqASxufpX2LaA@mail.gmail.com>
 <a21829ab-0f1a-4247-a670-12ddaf38078e@suse.com>
 <CAMe9rOrLRxD0iA3gjQhi=Qh_iRbHhuV2EkKu1u7UuzbS2fAzpA@mail.gmail.com>
Message-ID: <ajyEmjX6pTQ8n-gz@squeak.grove.modra.org>

On Wed, Jun 24, 2026 at 06:37:57PM +0800, H.J. Lu wrote:
> Here is the v2 path to partially revert:
> 
> commit c4150acbda1b3ce0602f79cbb7700b39e577be7e
> Author: Jan Beulich <jbeulich@suse.com>
> Date:   Fri May 8 11:45:04 2026 +0200
> 
>     gas/ELF: warn upon non-default visibility of local symbols
> 
> and update elf_adjust_symtab to only warn local symbol with protected
> visibility.

OK if this has been tested over a reasonable set of targets, ie. not
just x86.

-- 
Alan Modra

From hjl.tools@gmail.com  Thu Jun 25 02:11:45 2026
From: hjl.tools@gmail.com (H.J. Lu)
Date: Thu, 25 Jun 2026 10:11:45 +0800
Subject: [PATCH v2] gas/ELF: Allow local symbol with non-protected
 visibility
In-Reply-To: <ajyEmjX6pTQ8n-gz@squeak.grove.modra.org>
References: <e43bc9d8-260e-46f1-9afc-c52eacd4ac60@suse.com>
 <CAMe9rOpVyKapj7FrC1k+MZRqO1J+FZhq-HnfarzpuPedkJ0snA@mail.gmail.com>
 <67a1182c-e7d0-40ad-98ec-9b49c1d28410@suse.com>
 <17f9a3cc-7994-ad25-692b-e3e9441ff481@suse.de>
 <3d038b03-8b0f-46c5-a663-d1eacebaa6c9@suse.com>
 <f16445c4-e3e4-72ca-f5ee-9b5ede84de3d@suse.de>
 <888a0461-7875-411b-bde9-dd7960e1536e@suse.com>
 <CAMe9rOrdHFXyxhZhfmzrBnJFWW6ji+Mam0SPjoqASxufpX2LaA@mail.gmail.com>
 <a21829ab-0f1a-4247-a670-12ddaf38078e@suse.com>
 <CAMe9rOrLRxD0iA3gjQhi=Qh_iRbHhuV2EkKu1u7UuzbS2fAzpA@mail.gmail.com>
 <ajyEmjX6pTQ8n-gz@squeak.grove.modra.org>
Message-ID: <CAMe9rOpKu4n9ZYdYOR=MuUhvW4SsckR7FXT5PWv0F3nJhwUjoQ@mail.gmail.com>

On Thu, Jun 25, 2026 at 9:30?AM Alan Modra <amodra@gmail.com> wrote:
>
> On Wed, Jun 24, 2026 at 06:37:57PM +0800, H.J. Lu wrote:
> > Here is the v2 path to partially revert:
> >
> > commit c4150acbda1b3ce0602f79cbb7700b39e577be7e
> > Author: Jan Beulich <jbeulich@suse.com>
> > Date:   Fri May 8 11:45:04 2026 +0200
> >
> >     gas/ELF: warn upon non-default visibility of local symbols
> >
> > and update elf_adjust_symtab to only warn local symbol with protected
> > visibility.
>
> OK if this has been tested over a reasonable set of targets, ie. not
> just x86.
>
> --
> Alan Modra

I also tested it with aarch64-linux-gnu and tic6x-elf.  No regressions.
I am checking it in.

-- 
H.J.

From avr@gjlay.de  Thu Jun 25 11:37:21 2026
From: avr@gjlay.de (Georg-Johann Lay)
Date: Thu, 25 Jun 2026 13:37:21 +0200
Subject: [patch, avr, applied] Fix indentations to follow GNU style
Message-ID: <23934801-2f1c-4fbb-b3dc-23ebe4dc7fc9@gjlay.de>

This no-op patch uses TABs for indentation in all places instead
of blanks.

Applied to trunk.

Johann

--

AVR: Fix GNU coding style.

This patch uses TABs for indentation in all places instead of blanks.

gas/
	* config/tc-avr.c: Fix indentations to follow GNU style.
	* config/tc-avr.h: Same.
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From evgeny.karpov@arm.com  Thu Jun 25 11:38:13 2026
From: evgeny.karpov@arm.com (Evgeny Karpov)
Date: Thu, 25 Jun 2026 13:38:13 +0200
Subject: [PATCH v9 1/1] aarch64: Implement Structured Exception Handling
 (SEH) on AArch64
In-Reply-To: <20260617083947.8097-2-evgeny.karpov@arm.com>
Message-ID: <aj0TJff5MtpLqb57@arm.com>

On Mon, 22 Jun 2026, Alice Carlotti wrote:
> > Yes, it makes sense to stop compilation when function size cannot be properly calculated.
> > It means the assembler has an internal issue and should be fixed.
> 
> I think you missed my point - I'm asking whether "the function size has not
> been evaluated" only happens when func_size < 0, or can it happen with
> func_size >= 0 as well?

Yes, something should be wrong if func_size < 0, no need to check if func_size >= 0.

> > Unwind capacity is handled in seh_aarch64_add_unwind_element,
> > and epilogue capacity is handled in obj_coff_seh_startepilogue,
> > by AARCH64_MAX_UNWIND_CODES_SIZE and AARCH64_MAX_EPILOGUE_SCOPES.
> 
> I see - we currently apply the per-fragment limits on number of unwind codes
> and epilogue scopes to the entire function, so we don't need to check those
> limits when we later split the function into fragments.  But the downside is
> that we bail out in some cases where we could have used fragments instead.
> 
> I'm ok with this limitation remaining in the current patch for now, as long as
> it is explicitly called out in both:
> - any lists of currently unsupported functionality, and
> - a comment in this function explaining why we don't currently consider those
>   limits during fragmentation (the comment above the "while (true)" would be a
>   good place to mention this).

Ok, the description with the limitations will be extended.

> > Ok, it makes sense.
> > "Reuse of identical unwind code sequences" is not applicable for 
> > aarch64-w64-mingw32.
> 
> Really?  I see no reason why it wouldn't be applicable, and the documentation
> itself implicitly mentions reusing unwind codes:
> 
>     These assumptions are made in the exception handling description:
> 
>     - Prologs and epilogs tend to mirror each other. By taking advantage of
>       this common trait, the size of the metadata needed to describe unwinding
>       can be greatly reduced. Within the body of the function, it doesn't
>       matter whether the prolog's operations are undone, or the epilog's
>       operations are done in a forward manner. Both should produce identical
>       results.
> 
> (https://learn.microsoft.com/en-us/cpp/build/arm64-exception-handling?view=msvc-170#assumptions)

It can be done by supporting the packaged .pdata or reusing the same codes for
epilog scopes, however both are not supported yet.

> > The big endian host should be supported properly by md_number_to_chars that is used
> > for emitting pdata/xdata records.
> 
> That only ensures that the conversion from valueT to bytes-on-disk is handled
> correctly.  The issue is with the bit-field to valueT conversion - on a
> big-endian host I think this would pack the bitfields in the wrong order. 

The description will be extended with text that big endian host has not been validated.
It will be validated, and a separate patch will be submitted if needed.

> > +  unsigned char code;
> > +  unsigned char offset_shift;
> > +  unsigned char offset_addend;
> > +  unsigned char reg_shift;
> > +  unsigned char reg_addend;
> > +  unsigned char size;
> > +};
> Could you reorder the fields in the struct definition as well, to match the
> improved instantiation order?

It will be reordered.

> > +    as_bad (_("no unwind element available."));
> > +
> > +  unsigned value = 0;
> > +
> > +  if (info->offset_bits)
> > +    {
> > +      const unsigned divided_by = 1u << info->offset_shift;
> offset_multiplier would be a better name

It will be renamed.

> > +      if (offset & (divided_by - 1))
> > +	as_bad (_("offset should be divided by %u"), divided_by);
> "offset should be a multiple of %u"

It will be changed.
 
> > +      value |= offset << value_offset_bits;
> > +      value_offset_bits += info->offset_bits;
> > +    }
> > +
> > +  if (info->reg_bits)
> > +    {
> > +      const unsigned regn_divided_by = 1u << info->reg_shift;
> similiarly reg_multiplier

It will be renamed.
 
> > +      if (!skip_whitespace_and_comma (1))
> > +	return;
> > +
> > +      const unsigned reg_max = info->reg_max ? info->reg_max: 30;
> > +      if (reg > reg_max)
> > +	as_bad (_("unexpected register number"));
> > +    }
> This feels awkward, because the maximum isn't actually 30 in some cases.  I
> think it would be clearer to have a reg_pair field (instead of the reg_max)
> field, and replace this check with:
> 
> 
> +      /* Most range checks are applied during encoding.  Check here that we
> +	 don't reference registers higher than x30.  */
> +      if (info->reg_type == 'x'
> +	  && reg + (info->reg_pair ? 1 : 0) > 30)
> +	as_bad (_("unexpected register number"));
> 
> Although now I look at it some more, I think we should put all of the range
> checking in the same place (checking it during parsing might give better error
> locations, but I haven't verified this).

Ok, reg_pair will be used.

> > +	.seh_handler _ZN9exception6handleEPvS0_S0_S0_, @except
> > +	.seh_handlerdata
> > +	.long 1
> > +	.seh_code
> > +	.seh_startepilogue
> > +	.seh_endepilogue
> > +	.seh_endproc
> 
> Shouldn't seh directives be interleaved with the matching assembly
> instructions?  We don't check the offsets of individual seh unwind codes, but
> this test file looks like it would have a prologue that overlaps the epilogue
> and extends beyond the end of the function (which is something that we should
> probably check for).

It is not necessary now. The test will be extended with the instructions once
the packed .pdata is supported. 
Offsets for unwind codes are validated by tests.
Regarding "prologue that overlaps the epilogue", could it be clarified what
should be checked?
 
> Additionally, why is there a mismatch between .seh_set_fp near the end of the
> prologue in the .s file, and .seh_save_fp near the start of the reversed
> prologue in the .d file?

It is a typo in the comments. It will be changed to .seh_set_fp.

Regards,
Evgeny


From builder@sourceware.org  Thu Jun 25 12:37:27 2026
From: builder@sourceware.org (builder@sourceware.org)
Date: Thu, 25 Jun 2026 12:37:27 +0000
Subject: =?utf-8?q?=E2=98=A0_Buildbot_=28Sourceware=29=3A_binutils-gdb_-_failed_update_=28failure=29_=28master=29?=
Message-ID: <20260625123727.D415E4BA2E0B@sourceware.org>

A new failure has been detected on builder binutils-fedora-arm64 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/176/builds/6033

Build state: failed update (failure)
Revision: (unknown)
Worker: fedora-arm64
Build Reason: (unknown)
Blamelist: Georg-Johann Lay <avr@gjlay.de>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( failure )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/176/builds/6033/steps/1/logs/stdio


From rearnsha@arm.com  Thu Jun 25 14:36:36 2026
From: rearnsha@arm.com (Richard Earnshaw)
Date: Thu, 25 Jun 2026 15:36:36 +0100
Subject: [PATCH 0/3] aarch64: deprecate some ISA features
Message-ID: <20260625143639.3909071-1-rearnsha@arm.com>

A couple of features which were specified in the architecture, but
never implemented in products have been withdrawn.  This short series
adjusts the assembler to warn if they are used in real code.  The
intent is to ultimately remove support entirely from the tools, but
we'll do that in stages and deprecation is the first step.

I'd like to get this committed some time next week, so that it's in
with plenty of time before for the upcoming branch.

Richard Earnshaw (3):
  aarch64: Remove a stray comment from opcode/aarch64.h
  aarch64: warn if the TME feature is used during assembly.
  aarch64: deprecate mpamv2_vid sysregs

 gas/NEWS                                      |  5 +++++
 gas/config/tc-aarch64.c                       | 22 ++++++++++++++++++-
 .../gas/aarch64/sysreg/mpamv2_vid-bad.l       | 12 ++++++++++
 .../gas/aarch64/sysreg/mpamv2_vid-depr.l      | 13 +++++++++++
 gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.d | 13 ++++++-----
 gas/testsuite/gas/aarch64/tme-warn.l          | 15 +++++++++++++
 gas/testsuite/gas/aarch64/tme.d               |  1 +
 include/opcode/aarch64.h                      |  6 +++--
 opcodes/aarch64-sys-regs.def                  |  6 ++---
 opcodes/aarch64-tbl.h                         | 10 ++++-----
 10 files changed, 86 insertions(+), 17 deletions(-)
 create mode 100644 gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-depr.l
 create mode 100644 gas/testsuite/gas/aarch64/tme-warn.l

-- 
2.43.0


From rearnsha@arm.com  Thu Jun 25 14:36:37 2026
From: rearnsha@arm.com (Richard Earnshaw)
Date: Thu, 25 Jun 2026 15:36:37 +0100
Subject: [PATCH 1/3] aarch64: Remove a stray comment from opcode/aarch64.h
In-Reply-To: <20260625143639.3909071-1-rearnsha@arm.com>
References: <20260625143639.3909071-1-rearnsha@arm.com>
Message-ID: <20260625143639.3909071-2-rearnsha@arm.com>

When flag bit 28 was removed in an earlier patch, the comment describing
it was left behind.  This just cleans that up.
---
 include/opcode/aarch64.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 6d1b414444a..f51045210c9 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1479,7 +1479,7 @@ extern const aarch64_opcode aarch64_opcode_table[];
 #define F_OD(X) (((X) & 0x7) << 24)
 /* Instruction has the field of 'sz'.  */
 #define F_LSE_SZ (1 << 27)
-/* Require an exact qualifier match, even for NIL qualifiers.  */
+
 
 #define F_SYS_READ (1ULL << 29)
 /* This system instruction is used to write system registers.  */
-- 
2.43.0


From rearnsha@arm.com  Thu Jun 25 14:36:38 2026
From: rearnsha@arm.com (Richard Earnshaw)
Date: Thu, 25 Jun 2026 15:36:38 +0100
Subject: [PATCH 2/3] aarch64: warn if the TME feature is used during assembly.
In-Reply-To: <20260625143639.3909071-1-rearnsha@arm.com>
References: <20260625143639.3909071-1-rearnsha@arm.com>
Message-ID: <20260625143639.3909071-3-rearnsha@arm.com>

Arm has obsoleted the unimplemented TME feature.  Warn if instructions
from this feature are encountered.
---
 gas/NEWS                             |  4 ++++
 gas/config/tc-aarch64.c              | 22 +++++++++++++++++++++-
 gas/testsuite/gas/aarch64/tme-warn.l | 15 +++++++++++++++
 gas/testsuite/gas/aarch64/tme.d      |  1 +
 include/opcode/aarch64.h             |  6 ++++--
 opcodes/aarch64-tbl.h                | 10 +++++-----
 6 files changed, 50 insertions(+), 8 deletions(-)
 create mode 100644 gas/testsuite/gas/aarch64/tme-warn.l

diff --git a/gas/NEWS b/gas/NEWS
index 4c55a544f25..db6135b90d0 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,9 @@
 -*- text -*-
 
+* Arm has obsoleted the TME feature from the architecture because no
+  implementations were ever produced.  The assembler will now warn if
+  instructions from this extension are detected during assembly.
+
 * The legacy .vtable_entry and .vtable_inherit directives that were
   needed for versions of GCC prior to gcc-3.0 (when the generic C++
   ABI was adopted) are now considered obsolete.  They are now deprecated
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 9632a5b2a01..f7feddf21ba 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -8775,7 +8775,7 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
     case ldstnapair_offs:
     case ldstpair_indexed:
       /* Loading/storing the base register is unpredictable if writeback.  */
-      if ((aarch64_get_operand_class (opnds[0].type)
+       if ((aarch64_get_operand_class (opnds[0].type)
 	   == AARCH64_OPND_CLASS_INT_REG)
 	  && (opnds[0].reg.regno == opnds[2].addr.base_regno
 	    || opnds[1].reg.regno == opnds[2].addr.base_regno)
@@ -8841,6 +8841,25 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
     }
 }
 
+static void
+warn_deprecated (aarch64_instruction *instr, char *str)
+{
+  aarch64_inst *base = &instr->base;
+  const aarch64_opcode *opcode = base->opcode;
+  if (!(opcode->flags & F_DEPRECATED_INSN))
+    return;
+  switch (opcode->iclass)
+    {
+    case tme:
+      as_warn (_("the TME feature has been deprecated -- `%s'"), str);
+      break;
+    default:
+      /* Instruction marked as deprecated, but a suitable warning not
+	 added above.  */
+      abort();
+    }
+}
+
 static void
 force_automatic_sequence_close (void)
 {
@@ -9019,6 +9038,7 @@ md_assemble (char *str)
 	    }
 
 	  warn_unpredictable_ldst (&inst, str);
+	  warn_deprecated (&inst, str);
 
 	  if (inst.reloc.type == BFD_RELOC_UNUSED
 	      || !inst.reloc.need_libopcodes_p)
diff --git a/gas/testsuite/gas/aarch64/tme-warn.l b/gas/testsuite/gas/aarch64/tme-warn.l
new file mode 100644
index 00000000000..ed26e4ed95c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tme-warn.l
@@ -0,0 +1,15 @@
+[^:]*: Assembler messages:
+.*: Warning: the TME feature has been deprecated -- `tstart x0'
+.*: Warning: the TME feature has been deprecated -- `tstart X0'
+.*: Warning: the TME feature has been deprecated -- `tstart x15'
+.*: Warning: the TME feature has been deprecated -- `tstart X15'
+.*: Warning: the TME feature has been deprecated -- `tstart x30'
+.*: Warning: the TME feature has been deprecated -- `tstart X30'
+.*: Warning: the TME feature has been deprecated -- `tcommit'
+.*: Warning: the TME feature has been deprecated -- `tcommit'
+.*: Warning: the TME feature has been deprecated -- `ttest x0'
+.*: Warning: the TME feature has been deprecated -- `ttest X30'
+.*: Warning: the TME feature has been deprecated -- `tcancel 0'
+.*: Warning: the TME feature has been deprecated -- `tcancel 65535'
+.*: Warning: the TME feature has been deprecated -- `tcancel 0xffff'
+.*: Warning: the TME feature has been deprecated -- `tcancel 0XA'
diff --git a/gas/testsuite/gas/aarch64/tme.d b/gas/testsuite/gas/aarch64/tme.d
index 24d34ea9561..66527b03921 100644
--- a/gas/testsuite/gas/aarch64/tme.d
+++ b/gas/testsuite/gas/aarch64/tme.d
@@ -1,4 +1,5 @@
 #as: -march=armv8-a+tme
+#warning_output: tme-warn.l
 #objdump: -dr
 
 .* file format .*
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index f51045210c9..2d8514b8e7d 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1219,6 +1219,7 @@ enum aarch64_insn_class
   sve_shift_tsz_bhsd,
   sve_size_tsz_bhs,
   testbranch,
+  tme,
   cryptosm3,
   cryptosm4,
   dotproduct,
@@ -1479,7 +1480,8 @@ extern const aarch64_opcode aarch64_opcode_table[];
 #define F_OD(X) (((X) & 0x7) << 24)
 /* Instruction has the field of 'sz'.  */
 #define F_LSE_SZ (1 << 27)
-
+/* The instruction has been deprecated.  */
+#define F_DEPRECATED_INSN (1 << 28)
 
 #define F_SYS_READ (1ULL << 29)
 /* This system instruction is used to write system registers.  */
@@ -1542,7 +1544,7 @@ extern const aarch64_opcode aarch64_opcode_table[];
 /* As above, plus PN registers.  */
 #define F_INVALID_IMM_SYMS_3 (3ULL << 42)
 
-/* Next bit is 44, and 28 is also unused.  */
+/* Next bit is 44.  */
 
 /* Instruction constraints.  */
 /* This instruction has a predication constraint on the instruction at PC+4.  */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 518109ecfd6..c6cb5257008 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -3374,7 +3374,7 @@ static const aarch64_feature_set aarch64_feature_mpamv2 =
 #define MEMTAG_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
 #define _TME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
-  { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
+  { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1 | F_DEPRECATED_INSN, 0, 0, NULL }
 #define SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
   { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
     FLAGS | F_INVALID_IMM_SYMS_2, 0, TIED, NULL }
@@ -5154,10 +5154,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   CORE_INSN ("adr",  0x10000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_PCREL21), QL_ADRP, 0),
   CORE_INSN ("adrp", 0x90000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_ADRP), QL_ADRP, 0),
   /* TME Instructions.  */
-  _TME_INSN ("tstart", 0xd5233060, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
-  _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, 0, 0, OP0 (), QL_0, 0),
-  _TME_INSN ("ttest", 0xd5233160, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
-  _TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, 0, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0),
+  _TME_INSN ("tstart", 0xd5233060, 0xffffffe0, tme, 0, OP1 (Rd), QL_I1X, 0),
+  _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, tme, 0, OP0 (), QL_0, 0),
+  _TME_INSN ("ttest", 0xd5233160, 0xffffffe0, tme, 0, OP1 (Rd), QL_I1X, 0),
+  _TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, tme, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0),
   /* SME instructions (aliases for MSR <sysreg> operations.  */
   SME_INSN ("smstart", 0xd503477f, 0xffffffff, sme_start, 0, OP0 (), QL_0, F_SYS_WRITE, 0),
   SME_INSN ("smstop",  0xd503467f, 0xffffffff, sme_stop,  0, OP0 (), QL_0, F_SYS_WRITE, 0),
-- 
2.43.0


From rearnsha@arm.com  Thu Jun 25 14:36:39 2026
From: rearnsha@arm.com (Richard Earnshaw)
Date: Thu, 25 Jun 2026 15:36:39 +0100
Subject: [PATCH 3/3] aarch64: deprecate mpamv2_vid sysregs
In-Reply-To: <20260625143639.3909071-1-rearnsha@arm.com>
References: <20260625143639.3909071-1-rearnsha@arm.com>
Message-ID: <20260625143639.3909071-4-rearnsha@arm.com>

These registers were never implemented in any products and have been
withdrawn from the architecture.  Mark the registers as deprecated
and update the testsuite accordingly.
---
 gas/NEWS                                           |  7 ++++---
 gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.l  | 12 ++++++++++++
 gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-depr.l | 13 +++++++++++++
 gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.d      | 13 +++++++------
 opcodes/aarch64-sys-regs.def                       |  6 +++---
 5 files changed, 39 insertions(+), 12 deletions(-)
 create mode 100644 gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-depr.l

diff --git a/gas/NEWS b/gas/NEWS
index db6135b90d0..8b077351356 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,8 +1,9 @@
 -*- text -*-
 
-* Arm has obsoleted the TME feature from the architecture because no
-  implementations were ever produced.  The assembler will now warn if
-  instructions from this extension are detected during assembly.
+* The aarch64 extensions TME and MPAMv2_VID have never been implemented in any
+  products.  Arm has withdrawn the from the architecture.  The assembler will
+  now warn if instructions or system registers from either extension are
+  detected during assembly.
 
 * The legacy .vtable_entry and .vtable_inherit directives that were
   needed for versions of GCC prior to gcc-3.0 (when the generic C++
diff --git a/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.l b/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.l
index 6ab3d16fba0..a61ec858e73 100644
--- a/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.l
+++ b/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.l
@@ -1,13 +1,25 @@
 .*: Assembler messages:
 .*: Error: selected processor does not support system register name 'mpamvidcr_el2'
 .*:  Info: macro invoked from here
+.*: Warning: system register name 'mpamvidcr_el2' is deprecated and may be removed in a future release
+.*:  Info: macro invoked from here
 .*: Error: selected processor does not support system register name 'mpamvidcr_el2'
 .*:  Info: macro invoked from here
+.*: Warning: system register name 'mpamvidcr_el2' is deprecated and may be removed in a future release
+.*:  Info: macro invoked from here
 .*: Error: selected processor does not support system register name 'mpamvidsr_el2'
 .*:  Info: macro invoked from here
+.*: Warning: system register name 'mpamvidsr_el2' is deprecated and may be removed in a future release
+.*:  Info: macro invoked from here
 .*: Error: selected processor does not support system register name 'mpamvidsr_el2'
 .*:  Info: macro invoked from here
+.*: Warning: system register name 'mpamvidsr_el2' is deprecated and may be removed in a future release
+.*:  Info: macro invoked from here
 .*: Error: selected processor does not support system register name 'mpamvidsr_el3'
 .*:  Info: macro invoked from here
+.*: Warning: system register name 'mpamvidsr_el3' is deprecated and may be removed in a future release
+.*:  Info: macro invoked from here
 .*: Error: selected processor does not support system register name 'mpamvidsr_el3'
 .*:  Info: macro invoked from here
+.*: Warning: system register name 'mpamvidsr_el3' is deprecated and may be removed in a future release
+.*:  Info: macro invoked from here
diff --git a/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-depr.l b/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-depr.l
new file mode 100644
index 00000000000..36636384020
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-depr.l
@@ -0,0 +1,13 @@
+.*: Assembler messages:
+.*: Warning: system register name 'mpamvidcr_el2' is deprecated and may be removed in a future release
+.*:  Info: macro invoked from here
+.*: Warning: system register name 'mpamvidcr_el2' is deprecated and may be removed in a future release
+.*:  Info: macro invoked from here
+.*: Warning: system register name 'mpamvidsr_el2' is deprecated and may be removed in a future release
+.*:  Info: macro invoked from here
+.*: Warning: system register name 'mpamvidsr_el2' is deprecated and may be removed in a future release
+.*:  Info: macro invoked from here
+.*: Warning: system register name 'mpamvidsr_el3' is deprecated and may be removed in a future release
+.*:  Info: macro invoked from here
+.*: Warning: system register name 'mpamvidsr_el3' is deprecated and may be removed in a future release
+.*:  Info: macro invoked from here
diff --git a/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.d b/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.d
index 88c0c1883d8..feab902a3b8 100644
--- a/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.d
+++ b/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.d
@@ -1,4 +1,5 @@
 #as: -menable-sysreg-checking -march=armv8-a+mpamv2 -I$srcdir/$subdir
+#warning_output: mpamv2_vid-depr.l
 #objdump: -dr
 
 .*:     file format .*
@@ -6,9 +7,9 @@
 Disassembly of section \.text:
 
 0+ <.*>:
-.*:	d51ca700 	msr	mpamvidcr_el2, x0
-.*:	d53ca700 	mrs	x0, mpamvidcr_el2
-.*:	d51ca720 	msr	mpamvidsr_el2, x0
-.*:	d53ca720 	mrs	x0, mpamvidsr_el2
-.*:	d51ea720 	msr	mpamvidsr_el3, x0
-.*:	d53ea720 	mrs	x0, mpamvidsr_el3
+.*:	d51ca700 	msr	s3_4_c10_c7_0, x0
+.*:	d53ca700 	mrs	x0, s3_4_c10_c7_0
+.*:	d51ca720 	msr	s3_4_c10_c7_1, x0
+.*:	d53ca720 	mrs	x0, s3_4_c10_c7_1
+.*:	d51ea720 	msr	s3_6_c10_c7_1, x0
+.*:	d53ea720 	mrs	x0, s3_6_c10_c7_1
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index 9daa178ed7b..e8eee8a7c66 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -929,9 +929,9 @@
   SYSREG ("mpamhcr_el2",	CPENC (3,4,10,4,0),	0,		AARCH64_FEATURE (V8_2A)) /* MPAM */
   SYSREG ("mpamidr_el1",	CPENC (3,0,10,4,4),	F_REG_READ,	AARCH64_FEATURE (V8_2A)) /* MPAM */
   SYSREG ("mpamsm_el1",		CPENC (3,0,10,5,3),	0,		AARCH64_FEATURES (2, SME, V8_2A)) /* SME && MPAM */
-  SYSREG ("mpamvidcr_el2",	CPENC (3,4,10,7,0),	0,		AARCH64_FEATURE (MPAMv2))
-  SYSREG ("mpamvidsr_el2",	CPENC (3,4,10,7,1),	0,		AARCH64_FEATURE (MPAMv2))
-  SYSREG ("mpamvidsr_el3",	CPENC (3,6,10,7,1),	0,		AARCH64_FEATURE (MPAMv2))
+  SYSREG ("mpamvidcr_el2",	CPENC (3,4,10,7,0),	F_DEPRECATED,	AARCH64_FEATURE (MPAMv2))
+  SYSREG ("mpamvidsr_el2",	CPENC (3,4,10,7,1),	F_DEPRECATED,	AARCH64_FEATURE (MPAMv2))
+  SYSREG ("mpamvidsr_el3",	CPENC (3,6,10,7,1),	F_DEPRECATED,	AARCH64_FEATURE (MPAMv2))
   SYSREG ("mpamvpm0_el2",	CPENC (3,4,10,6,0),	0,		AARCH64_FEATURE (V8_2A)) /* MPAM */
   SYSREG ("mpamvpm1_el2",	CPENC (3,4,10,6,1),	0,		AARCH64_FEATURE (V8_2A)) /* MPAM */
   SYSREG ("mpamvpm2_el2",	CPENC (3,4,10,6,2),	0,		AARCH64_FEATURE (V8_2A)) /* MPAM */
-- 
2.43.0


From evgeny.karpov@arm.com  Thu Jun 25 14:39:12 2026
From: evgeny.karpov@arm.com (Evgeny Karpov)
Date: Thu, 25 Jun 2026 16:39:12 +0200
Subject: [PATCH v9 1/1] aarch64: Implement Structured Exception Handling
 (SEH) on AArch64
In-Reply-To: <20260617083947.8097-2-evgeny.karpov@arm.com>
Message-ID: <aj09kCmX1X_cPB31@arm.com>

On Mon, 22 Jun 2026, Alice Carlotti wrote:
> On Wed, Jun 17, 2026 at 10:39:47AM +0200, Evgeny Karpov wrote:
> ...
> > +/* Write out the xdata information for one function.  */
> > +static void
> > +seh_aarch64_write_function_xdata (struct seh_aarch64_context *seh_ctx)
> 
> Oops, I forgot to write my comments on this functions.
> 
> In general, I think this function ought handle function fragmention, but the
> encoding details (including choosing between compact or extended header fields)
> should be handled in seh_aarch64_emit_xdata_record.  This separation of
> concerns should help with readability.
> 
> I think there are also several corner cases that are mishandled in this code,
> but I've been struggling to work out what's going on well enough to say that
> particular pieces are right or wrong.  I'll try to point any specific issues I
> see, but I'd appreciate if you could also see whether you can do anything more
> to improve the structure of this code.

Some checks will be moved to seh_aarch64_emit_xdata_record when it makes sense.
 
> > +  uintptr_t fragment_offset = 0;
> > +  unsigned first_fragment_scope = 0;
> > +  unsigned last_fragment_scope = 0;
> > +
> > +  /* Large functions (>= 1MB) will be split into multiple fragments.
> > +     However, it is expected the most of the functions will have only one
> > +     fragment. This loop iterates fragments and emit them.  */
> 
> See previous review comments about how this implementation doesn't currently
> support (or need to handle) fragmenting due to too many unwind codes or too
> many epilogue scopes.

The description with limitations will be extended mentioning this.

> > +      header->e = 0;
> > +      header->code_words = 0;
> > +      header->epilogue_count = 0;
> > +
> > +      header->ext_code_words = 0;
> > +      header->ext_epilogue_count = last_fragment_scope
> > +				   - first_fragment_scope;
> 
> It would be clearer to use separate variables here, and only combine them into
> a single header value within seh_aarch64_emit_xdata_record.   We can't do the
> type-punning anyway, so there's no benefit to putting the values into a struct.
> This also avoids any ambiguity about whether the short or extended fields
> should be used for computations in this function.

This can be done after validating big endian host if needed.
 
> > +
> > +      /* Calculate how many unwind bytes will be emitted in .xdata record.  */
> > +      unsigned unwind_bytes = prologue_size;
> > +
> > +      /* Check if current fragment has a phantom prologue. If yes, then
> > +	 the unwinding size should be adjusted.  */
> > +      const bool has_phantom_prologue = is_fragmented_function && is_last_frag;
> The is_last_frag part looks wrong - for a typical function layout, I'd expect
> only the first fragment to have a real prologue, and the rest to have a phantom
> prologue.

Ok, it will be validated and addressed if needed in v10.
 
> > +		{
> > +		  const seh_aarch64_epilogue_scope *scope;
> > +		  scope = scopes + first_fragment_scope;
> > +		  header->ext_epilogue_count = scope->epilogue_start_index;
> > +		}
> > +	    }
> > +	}
> This code is mostly selecting between different header formats, so I think it
> should be part of seh_aarch64_emit_xdata_record.

It will be moved to seh_aarch64_emit_xdata_record.

Regards,
Evgeny


From nickc@redhat.com  Thu Jun 25 14:42:25 2026
From: nickc@redhat.com (Nick Clifton)
Date: Thu, 25 Jun 2026 15:42:25 +0100
Subject: [PATCH] elf: Set text-segment address to the maximum page size
Message-ID: <05c74589-fa62-4673-bb6e-9154d37024ee@redhat.com>

Hi H.J.

> 	PR ld/34184
> 	* ldexp.c (fold_binary): Set text-segment address to the maximum
> 	page size for ELF PDE output with -z max-page-size=SIZE.
> 	* testsuite/ld-elf/elf.exp: Add ld/34184 test.
> 	* testsuite/ld-elf/pr34184.c: New file.

I like this patch, but I do have a couple of comments:

> +      /* When generating Position Dependent Executable for ELF with the
> +	 maximum page size set on command-line, if text-segment address
> +	 is lower than the maximum page size, set text-segment address
> +	 to the maximum page size.  */
> +      if ((bfd_get_flavour (link_info.output_bfd)
> +	   == bfd_target_elf_flavour)
> +	  && bfd_link_pde (&link_info)
> +	  && link_info.maxpagesize_is_set
> +	  && link_info.maxpagesize > value
> +	  && strcmp (segment_name, "text-segment") == 0)
> +	value = link_info.maxpagesize;

I think that it would be helpful to inform the user that the text
segment address is being changed - *if* they have tried to set it
using --image-base or --Ttext-segment.  Otherwise they may wonder
why their command line option is being ignored.


> +    [list \
> +	"Run pr34184" \
> +	"-Wl,-z,max-page-size=0x800000" \
> +	"" \
> +	{pr34184.c} \
> +	"pr34184" \
> +	"pass.out" \
> +    ] \

As far as I can tell, this test does not actually check that
the text segment's address is now a multiple of the max page
size...


Cheers
   Nick



From jbeulich@suse.com  Thu Jun 25 14:58:49 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Thu, 25 Jun 2026 16:58:49 +0200
Subject: [PATCH 2/3] aarch64: warn if the TME feature is used during
 assembly.
In-Reply-To: <20260625143639.3909071-3-rearnsha@arm.com>
References: <20260625143639.3909071-1-rearnsha@arm.com>
 <20260625143639.3909071-3-rearnsha@arm.com>
Message-ID: <bd5d99a4-8a6d-4f45-99c6-8268c28b21a6@suse.com>

On 25.06.2026 16:36, Richard Earnshaw wrote:
> --- a/gas/NEWS
> +++ b/gas/NEWS
> @@ -1,5 +1,9 @@
>  -*- text -*-
>  
> +* Arm has obsoleted the TME feature from the architecture because no
> +  implementations were ever produced.  The assembler will now warn if
> +  instructions from this extension are detected during assembly.

The only reference to which targets are affected is "Arm" at the start of
the sentence. Yet it's not arm*-*-* that this talks about. May I ask for
clarifying this here?

> --- a/gas/config/tc-aarch64.c
> +++ b/gas/config/tc-aarch64.c
> @@ -8775,7 +8775,7 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
>      case ldstnapair_offs:
>      case ldstpair_indexed:
>        /* Loading/storing the base register is unpredictable if writeback.  */
> -      if ((aarch64_get_operand_class (opnds[0].type)
> +       if ((aarch64_get_operand_class (opnds[0].type)
>  	   == AARCH64_OPND_CLASS_INT_REG)
>  	  && (opnds[0].reg.regno == opnds[2].addr.base_regno
>  	    || opnds[1].reg.regno == opnds[2].addr.base_regno)

Stray change?

> @@ -8841,6 +8841,25 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
>      }
>  }
>  
> +static void
> +warn_deprecated (aarch64_instruction *instr, char *str)

Mind me suggesting to use, in new code, proper pointer-to-const wherever
possible?

> +{
> +  aarch64_inst *base = &instr->base;

I.e. also here then.

> --- a/opcodes/aarch64-tbl.h
> +++ b/opcodes/aarch64-tbl.h
> @@ -3374,7 +3374,7 @@ static const aarch64_feature_set aarch64_feature_mpamv2 =
>  #define MEMTAG_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
>    { NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
>  #define _TME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
> -  { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
> +  { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1 | F_DEPRECATED_INSN, 0, 0, NULL }
>  #define SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
>    { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
>      FLAGS | F_INVALID_IMM_SYMS_2, 0, TIED, NULL }
> @@ -5154,10 +5154,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =
>    CORE_INSN ("adr",  0x10000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_PCREL21), QL_ADRP, 0),
>    CORE_INSN ("adrp", 0x90000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_ADRP), QL_ADRP, 0),
>    /* TME Instructions.  */
> -  _TME_INSN ("tstart", 0xd5233060, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
> -  _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, 0, 0, OP0 (), QL_0, 0),
> -  _TME_INSN ("ttest", 0xd5233160, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
> -  _TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, 0, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0),
> +  _TME_INSN ("tstart", 0xd5233060, 0xffffffe0, tme, 0, OP1 (Rd), QL_I1X, 0),
> +  _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, tme, 0, OP0 (), QL_0, 0),
> +  _TME_INSN ("ttest", 0xd5233160, 0xffffffe0, tme, 0, OP1 (Rd), QL_I1X, 0),
> +  _TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, tme, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0),
>    /* SME instructions (aliases for MSR <sysreg> operations.  */
>    SME_INSN ("smstart", 0xd503477f, 0xffffffff, sme_start, 0, OP0 (), QL_0, F_SYS_WRITE, 0),
>    SME_INSN ("smstop",  0xd503467f, 0xffffffff, sme_stop,  0, OP0 (), QL_0, F_SYS_WRITE, 0),

Couldn't _TME_INSN() take care of setting the (uniform) class?

As per what the cover letter says, later you may mean to remove support
altogether. Might it make sense to remove support only from the
assembler, but keep the disassembler recognize the encodings (unless they
are intended to be re-used for other purposes)?

Jan

From jbeulich@suse.com  Thu Jun 25 15:07:10 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Thu, 25 Jun 2026 17:07:10 +0200
Subject: [PATCH 3/3] aarch64: deprecate mpamv2_vid sysregs
In-Reply-To: <20260625143639.3909071-4-rearnsha@arm.com>
References: <20260625143639.3909071-1-rearnsha@arm.com>
 <20260625143639.3909071-4-rearnsha@arm.com>
Message-ID: <f513f0a3-bee9-41fd-b6f2-c2e015a29456@suse.com>

On 25.06.2026 16:36, Richard Earnshaw wrote:
> --- a/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.l
> +++ b/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.l
> @@ -1,13 +1,25 @@
>  .*: Assembler messages:
>  .*: Error: selected processor does not support system register name 'mpamvidcr_el2'
>  .*:  Info: macro invoked from here
> +.*: Warning: system register name 'mpamvidcr_el2' is deprecated and may be removed in a future release
> +.*:  Info: macro invoked from here

Why a warning when there was an earlier error?

> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-depr.l
> @@ -0,0 +1,13 @@
> +.*: Assembler messages:
> +.*: Warning: system register name 'mpamvidcr_el2' is deprecated and may be removed in a future release
> +.*:  Info: macro invoked from here
> +.*: Warning: system register name 'mpamvidcr_el2' is deprecated and may be removed in a future release
> +.*:  Info: macro invoked from here
> +.*: Warning: system register name 'mpamvidsr_el2' is deprecated and may be removed in a future release
> +.*:  Info: macro invoked from here
> +.*: Warning: system register name 'mpamvidsr_el2' is deprecated and may be removed in a future release
> +.*:  Info: macro invoked from here
> +.*: Warning: system register name 'mpamvidsr_el3' is deprecated and may be removed in a future release
> +.*:  Info: macro invoked from here
> +.*: Warning: system register name 'mpamvidsr_el3' is deprecated and may be removed in a future release
> +.*:  Info: macro invoked from here

To get rid of the (useless here) Info: lines, you may want to pass --no-info
to the assembler.

Jan

From hjl.tools@gmail.com  Thu Jun 25 15:46:58 2026
From: hjl.tools@gmail.com (H.J. Lu)
Date: Thu, 25 Jun 2026 23:46:58 +0800
Subject: [PATCH] elf: Set text-segment address to the maximum page size
In-Reply-To: <05c74589-fa62-4673-bb6e-9154d37024ee@redhat.com>
References: <05c74589-fa62-4673-bb6e-9154d37024ee@redhat.com>
Message-ID: <CAMe9rOpmyweh-+Dp4F_K2H15C4x+aTSO__fLRFxCivMnA+oDKg@mail.gmail.com>

On Thu, Jun 25, 2026 at 10:42?PM Nick Clifton <nickc@redhat.com> wrote:
>
> Hi H.J.
>
> >       PR ld/34184
> >       * ldexp.c (fold_binary): Set text-segment address to the maximum
> >       page size for ELF PDE output with -z max-page-size=SIZE.
> >       * testsuite/ld-elf/elf.exp: Add ld/34184 test.
> >       * testsuite/ld-elf/pr34184.c: New file.
>
> I like this patch, but I do have a couple of comments:
>
> > +      /* When generating Position Dependent Executable for ELF with the
> > +      maximum page size set on command-line, if text-segment address
> > +      is lower than the maximum page size, set text-segment address
> > +      to the maximum page size.  */
> > +      if ((bfd_get_flavour (link_info.output_bfd)
> > +        == bfd_target_elf_flavour)
> > +       && bfd_link_pde (&link_info)
> > +       && link_info.maxpagesize_is_set
> > +       && link_info.maxpagesize > value
> > +       && strcmp (segment_name, "text-segment") == 0)
> > +     value = link_info.maxpagesize;
>
> I think that it would be helpful to inform the user that the text
> segment address is being changed - *if* they have tried to set it
> using --image-base or --Ttext-segment.  Otherwise they may wonder
> why their command line option is being ignored.

Will do.

>
> > +    [list \
> > +     "Run pr34184" \
> > +     "-Wl,-z,max-page-size=0x800000" \
> > +     "" \
> > +     {pr34184.c} \
> > +     "pr34184" \
> > +     "pass.out" \
> > +    ] \
>
> As far as I can tell, this test does not actually check that
> the text segment's address is now a multiple of the max page
> size...

This is a run-time test.  Without the fix, we get segfault:

[hjl@gnu-tgl-3 tmp]$ cat x.c
int
main ()
{
  return 0;
}
[hjl@gnu-tgl-3 tmp]$ gcc -Wl,-z,max-page-size=0x800000 x.c
[hjl@gnu-tgl-3 tmp]$ ./a.out
Segmentation fault         ./a.out
[hjl@gnu-tgl-3 tmp]$


-- 
H.J.

From Richard.Earnshaw@arm.com  Thu Jun 25 15:56:04 2026
From: Richard.Earnshaw@arm.com (Richard Earnshaw (foss))
Date: Thu, 25 Jun 2026 16:56:04 +0100
Subject: [PATCH 3/3] aarch64: deprecate mpamv2_vid sysregs
In-Reply-To: <f513f0a3-bee9-41fd-b6f2-c2e015a29456@suse.com>
References: <20260625143639.3909071-1-rearnsha@arm.com>
 <20260625143639.3909071-4-rearnsha@arm.com>
 <f513f0a3-bee9-41fd-b6f2-c2e015a29456@suse.com>
Message-ID: <b59017c7-f41b-41a0-8525-48fdd92545b1@arm.com>

On 25/06/2026 16:07, Jan Beulich wrote:
> On 25.06.2026 16:36, Richard Earnshaw wrote:
>> --- a/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.l
>> +++ b/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.l
>> @@ -1,13 +1,25 @@
>>  .*: Assembler messages:
>>  .*: Error: selected processor does not support system register name 'mpamvidcr_el2'
>>  .*:  Info: macro invoked from here
>> +.*: Warning: system register name 'mpamvidcr_el2' is deprecated and may be removed in a future release
>> +.*:  Info: macro invoked from here
> 
> Why a warning when there was an earlier error?

Well technically both are correct.  The selected processor (architecture) forbids it, and there's no point in trying to enable it because it's deprecated.  Two reasons not to use it :)

> 
>> --- /dev/null
>> +++ b/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-depr.l
>> @@ -0,0 +1,13 @@
>> +.*: Assembler messages:
>> +.*: Warning: system register name 'mpamvidcr_el2' is deprecated and may be removed in a future release
>> +.*:  Info: macro invoked from here
>> +.*: Warning: system register name 'mpamvidcr_el2' is deprecated and may be removed in a future release
>> +.*:  Info: macro invoked from here
>> +.*: Warning: system register name 'mpamvidsr_el2' is deprecated and may be removed in a future release
>> +.*:  Info: macro invoked from here
>> +.*: Warning: system register name 'mpamvidsr_el2' is deprecated and may be removed in a future release
>> +.*:  Info: macro invoked from here
>> +.*: Warning: system register name 'mpamvidsr_el3' is deprecated and may be removed in a future release
>> +.*:  Info: macro invoked from here
>> +.*: Warning: system register name 'mpamvidsr_el3' is deprecated and may be removed in a future release
>> +.*:  Info: macro invoked from here
> 
> To get rid of the (useless here) Info: lines, you may want to pass --no-info
> to the assembler.
> 

I could, but it's not like this code is going to be around for ever in this case.

> Jan

R.

From Richard.Earnshaw@arm.com  Thu Jun 25 16:12:05 2026
From: Richard.Earnshaw@arm.com (Richard Earnshaw (foss))
Date: Thu, 25 Jun 2026 17:12:05 +0100
Subject: [PATCH 2/3] aarch64: warn if the TME feature is used during
 assembly.
In-Reply-To: <bd5d99a4-8a6d-4f45-99c6-8268c28b21a6@suse.com>
References: <20260625143639.3909071-1-rearnsha@arm.com>
 <20260625143639.3909071-3-rearnsha@arm.com>
 <bd5d99a4-8a6d-4f45-99c6-8268c28b21a6@suse.com>
Message-ID: <2591315c-7bd8-4c5c-a6ab-d4b653ebb28f@arm.com>

On 25/06/2026 15:58, Jan Beulich wrote:
> On 25.06.2026 16:36, Richard Earnshaw wrote:
>> --- a/gas/NEWS
>> +++ b/gas/NEWS
>> @@ -1,5 +1,9 @@
>>  -*- text -*-
>>  
>> +* Arm has obsoleted the TME feature from the architecture because no
>> +  implementations were ever produced.  The assembler will now warn if
>> +  instructions from this extension are detected during assembly.
> 
> The only reference to which targets are affected is "Arm" at the start of
> the sentence. Yet it's not arm*-*-* that this talks about. May I ask for
> clarifying this here?
> 

Fair point.  Will clarify.

>> --- a/gas/config/tc-aarch64.c
>> +++ b/gas/config/tc-aarch64.c
>> @@ -8775,7 +8775,7 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
>>      case ldstnapair_offs:
>>      case ldstpair_indexed:
>>        /* Loading/storing the base register is unpredictable if writeback.  */
>> -      if ((aarch64_get_operand_class (opnds[0].type)
>> +       if ((aarch64_get_operand_class (opnds[0].type)
>>  	   == AARCH64_OPND_CLASS_INT_REG)
>>  	  && (opnds[0].reg.regno == opnds[2].addr.base_regno
>>  	    || opnds[1].reg.regno == opnds[2].addr.base_regno)
> 
> Stray change?

Yep. Not sure how that happened, it certainly wasn't deliberate.

> 
>> @@ -8841,6 +8841,25 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
>>      }
>>  }
>>  
>> +static void
>> +warn_deprecated (aarch64_instruction *instr, char *str)
> 
> Mind me suggesting to use, in new code, proper pointer-to-const wherever
> possible?
> 
I was templating it on the function immediately above it, which is defined identically.

I'll have a look though.

>> +{
>> +  aarch64_inst *base = &instr->base;
> 
> I.e. also here then.
> 
>> --- a/opcodes/aarch64-tbl.h
>> +++ b/opcodes/aarch64-tbl.h
>> @@ -3374,7 +3374,7 @@ static const aarch64_feature_set aarch64_feature_mpamv2 =
>>  #define MEMTAG_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
>>    { NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
>>  #define _TME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
>> -  { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
>> +  { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1 | F_DEPRECATED_INSN, 0, 0, NULL }
>>  #define SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
>>    { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
>>      FLAGS | F_INVALID_IMM_SYMS_2, 0, TIED, NULL }
>> @@ -5154,10 +5154,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =
>>    CORE_INSN ("adr",  0x10000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_PCREL21), QL_ADRP, 0),
>>    CORE_INSN ("adrp", 0x90000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_ADRP), QL_ADRP, 0),
>>    /* TME Instructions.  */
>> -  _TME_INSN ("tstart", 0xd5233060, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
>> -  _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, 0, 0, OP0 (), QL_0, 0),
>> -  _TME_INSN ("ttest", 0xd5233160, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
>> -  _TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, 0, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0),
>> +  _TME_INSN ("tstart", 0xd5233060, 0xffffffe0, tme, 0, OP1 (Rd), QL_I1X, 0),
>> +  _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, tme, 0, OP0 (), QL_0, 0),
>> +  _TME_INSN ("ttest", 0xd5233160, 0xffffffe0, tme, 0, OP1 (Rd), QL_I1X, 0),
>> +  _TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, tme, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0),
>>    /* SME instructions (aliases for MSR <sysreg> operations.  */
>>    SME_INSN ("smstart", 0xd503477f, 0xffffffff, sme_start, 0, OP0 (), QL_0, F_SYS_WRITE, 0),
>>    SME_INSN ("smstop",  0xd503467f, 0xffffffff, sme_stop,  0, OP0 (), QL_0, F_SYS_WRITE, 0),
> 
> Couldn't _TME_INSN() take care of setting the (uniform) class?

Possibly, but I'm not sure it's worth it.

> 
> As per what the cover letter says, later you may mean to remove support
> altogether. Might it make sense to remove support only from the
> assembler, but keep the disassembler recognize the encodings (unless they
> are intended to be re-used for other purposes)?
> 

There never were any physical implementations of either of the features that have been dropped.  At most some software emulators might have supported it, but I'd be quite surprised if they did (and even more surpised if they still do).  There's no guarantee that the opcodes won't get re-allocated, but I don't know if there are any plans for that.

Whilst they are deprecated in the assembler, the instructions will continue to disassemble.  The sysregs (in the other patch) now disassemble as their raw encodings, without the special names - that seems to have been a deliberate choice when the F_DEPRECATED flag was implemented for sysregs.
> Jan

R.

From Richard.Earnshaw@arm.com  Thu Jun 25 16:14:25 2026
From: Richard.Earnshaw@arm.com (Richard Earnshaw)
Date: Thu, 25 Jun 2026 17:14:25 +0100
Subject: [PATCH 2/3] aarch64: warn if the TME feature is used during
 assembly.
In-Reply-To: <2591315c-7bd8-4c5c-a6ab-d4b653ebb28f@arm.com>
References: <20260625143639.3909071-1-rearnsha@arm.com>
 <20260625143639.3909071-3-rearnsha@arm.com>
 <bd5d99a4-8a6d-4f45-99c6-8268c28b21a6@suse.com>
 <2591315c-7bd8-4c5c-a6ab-d4b653ebb28f@arm.com>
Message-ID: <424a399b-f88e-4049-9e35-8ad72894f309@arm.com>

On 25/06/2026 17:12, Richard Earnshaw (foss) wrote:
> On 25/06/2026 15:58, Jan Beulich wrote:
>> On 25.06.2026 16:36, Richard Earnshaw wrote:
>>> --- a/gas/NEWS
>>> +++ b/gas/NEWS
>>> @@ -1,5 +1,9 @@
>>>  -*- text -*-
>>>  
>>> +* Arm has obsoleted the TME feature from the architecture because no
>>> +  implementations were ever produced.  The assembler will now warn if
>>> +  instructions from this extension are detected during assembly.
>>
>> The only reference to which targets are affected is "Arm" at the start of
>> the sentence. Yet it's not arm*-*-* that this talks about. May I ask for
>> clarifying this here?
>>
> 
> Fair point.  Will clarify.

In fact, I rewrote this section in patch 3, which handles this.

> 
>>> --- a/gas/config/tc-aarch64.c
>>> +++ b/gas/config/tc-aarch64.c
>>> @@ -8775,7 +8775,7 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
>>>      case ldstnapair_offs:
>>>      case ldstpair_indexed:
>>>        /* Loading/storing the base register is unpredictable if writeback.  */
>>> -      if ((aarch64_get_operand_class (opnds[0].type)
>>> +       if ((aarch64_get_operand_class (opnds[0].type)
>>>  	   == AARCH64_OPND_CLASS_INT_REG)
>>>  	  && (opnds[0].reg.regno == opnds[2].addr.base_regno
>>>  	    || opnds[1].reg.regno == opnds[2].addr.base_regno)
>>
>> Stray change?
> 
> Yep. Not sure how that happened, it certainly wasn't deliberate.
> 
>>
>>> @@ -8841,6 +8841,25 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
>>>      }
>>>  }
>>>  
>>> +static void
>>> +warn_deprecated (aarch64_instruction *instr, char *str)
>>
>> Mind me suggesting to use, in new code, proper pointer-to-const wherever
>> possible?
>>
> I was templating it on the function immediately above it, which is defined identically.
> 
> I'll have a look though.
> 
>>> +{
>>> +  aarch64_inst *base = &instr->base;
>>
>> I.e. also here then.
>>
>>> --- a/opcodes/aarch64-tbl.h
>>> +++ b/opcodes/aarch64-tbl.h
>>> @@ -3374,7 +3374,7 @@ static const aarch64_feature_set aarch64_feature_mpamv2 =
>>>  #define MEMTAG_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
>>>    { NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
>>>  #define _TME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
>>> -  { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
>>> +  { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1 | F_DEPRECATED_INSN, 0, 0, NULL }
>>>  #define SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
>>>    { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
>>>      FLAGS | F_INVALID_IMM_SYMS_2, 0, TIED, NULL }
>>> @@ -5154,10 +5154,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =
>>>    CORE_INSN ("adr",  0x10000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_PCREL21), QL_ADRP, 0),
>>>    CORE_INSN ("adrp", 0x90000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_ADRP), QL_ADRP, 0),
>>>    /* TME Instructions.  */
>>> -  _TME_INSN ("tstart", 0xd5233060, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
>>> -  _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, 0, 0, OP0 (), QL_0, 0),
>>> -  _TME_INSN ("ttest", 0xd5233160, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
>>> -  _TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, 0, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0),
>>> +  _TME_INSN ("tstart", 0xd5233060, 0xffffffe0, tme, 0, OP1 (Rd), QL_I1X, 0),
>>> +  _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, tme, 0, OP0 (), QL_0, 0),
>>> +  _TME_INSN ("ttest", 0xd5233160, 0xffffffe0, tme, 0, OP1 (Rd), QL_I1X, 0),
>>> +  _TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, tme, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0),
>>>    /* SME instructions (aliases for MSR <sysreg> operations.  */
>>>    SME_INSN ("smstart", 0xd503477f, 0xffffffff, sme_start, 0, OP0 (), QL_0, F_SYS_WRITE, 0),
>>>    SME_INSN ("smstop",  0xd503467f, 0xffffffff, sme_stop,  0, OP0 (), QL_0, F_SYS_WRITE, 0),
>>
>> Couldn't _TME_INSN() take care of setting the (uniform) class?
> 
> Possibly, but I'm not sure it's worth it.
> 
>>
>> As per what the cover letter says, later you may mean to remove support
>> altogether. Might it make sense to remove support only from the
>> assembler, but keep the disassembler recognize the encodings (unless they
>> are intended to be re-used for other purposes)?
>>
> 
> There never were any physical implementations of either of the features that have been dropped.  At most some software emulators might have supported it, but I'd be quite surprised if they did (and even more surpised if they still do).  There's no guarantee that the opcodes won't get re-allocated, but I don't know if there are any plans for that.
> 
> Whilst they are deprecated in the assembler, the instructions will continue to disassemble.  The sysregs (in the other patch) now disassemble as their raw encodings, without the special names - that seems to have been a deliberate choice when the F_DEPRECATED flag was implemented for sysregs.
>> Jan
> 
> R.


From macro@orcam.me.uk  Thu Jun 25 21:43:56 2026
From: macro@orcam.me.uk (Maciej W. Rozycki)
Date: Thu, 25 Jun 2026 22:43:56 +0100 (BST)
Subject: [PATCH v3] RISC-V: Fix build with GCC-8
In-Reply-To: <20260623133508.2896582-1-zhuangqiubin@linux.spacemit.com>
References: <f2abf263-4730-4ccd-af87-e3de2289b35c@suse.com>
 <20260623133508.2896582-1-zhuangqiubin@linux.spacemit.com>
Message-ID: <alpine.DEB.2.21.2606252232520.58268@angie.orcam.me.uk>

On Tue, 23 Jun 2026, Mark Zhuang wrote:

> From: Mark Zhuang <mark.zhuang@spacemit.com>
> 
> GCC 8.5.0 rejects a declaration right after a case label.
> Add braces to fix it.

 I think it would be more useful to the reader if the commit referred to 
the relevant C language standard and minimum compiler version as given by 
Andreas: <https://inbox.sourceware.org/binutils/mvmtsqtzgve.fsf@suse.de/>.

 FWIW it broke the build with GCC 10.2.1 here (production box, system
compiler).

  Maciej

From amodra@gmail.com  Thu Jun 25 23:44:08 2026
From: amodra@gmail.com (Alan Modra)
Date: Fri, 26 Jun 2026 09:14:08 +0930
Subject: aarch64: segv on aarch64_stub_erratum_843419_veneer
Message-ID: <aj29SHF5KAEEtbR1@squeak.grove.modra.org>

With a patch I've had in my tree for a while that makes use of the
stub bfd for linker generated sections, I saw segfaults in the
testsuite linking ld-aarch64/erratum843419-adr and
ld-aarch64/erratum843419-far-adr.  Without my changes (that result in
stub_file->the_bfd->sections non-NULL), elf64_aarch64_build_stubs is
not called.  See aarch64elf.em finish function.  However, I believe it
is possible to hit the segfault with a testcase that generates other
stub types besides the aarch64_stub_erratum_843419_veneer.

The segfault occurs on the aarch64_build_one_stub assert that
stub_sec->output_section != NULL.  That happens because
_bfd_aarch64_add_stub_entry_after creates a stub_entry with stub_sec
NULL when fix_erratum_843419 is ERRAT_ADR.  Clearly we shouldn't be
doing anything in aarch64_build_one_stub when stub_sec is NULL, and
inspecting aarch64_size_one_stub reveals that these stubs are not
sized.

I found the test in aarch64_size_one_stub to exclude these stubs a
little obscure, needing to verify the possible values of
htab->fix_erratum_843419 to convince myself it was correct.  (It is.)
So I changed the test in both places to stub_entry->stub_sec being
non-NULL.   Which is how _bfd_aarch64_erratum_843419_branch_to_stub
distinguishes the variants of the stub.

I'll commit this in a day or two if no one NAKs it, to make it into
the next release.

	* elfnn-aarch64.c (aarch64_build_one_stub): Don't segfault on
	NULL stub_sec.
	(aarch64_size_one_stub): Use the same condition here for
	aarch64_stub_erratum_843419_veneer.

diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c
index 96da6d790d9..ffca9048e65 100644
--- a/bfd/elfnn-aarch64.c
+++ b/bfd/elfnn-aarch64.c
@@ -3265,6 +3265,10 @@ aarch64_build_one_stub (struct bfd_hash_entry *gen_entry,
   info = (struct bfd_link_info *) in_arg;
   htab = elf_aarch64_hash_table (info);
 
+  if (stub_entry->stub_type == aarch64_stub_erratum_843419_veneer
+      && stub_entry->stub_sec == NULL)
+    return true;
+
   /* Fail if the target section could not be assigned to an output
      section.  The user should fix his linker script.  */
   if (stub_entry->target_section->output_section == NULL
@@ -3410,7 +3414,7 @@ static bool
 aarch64_size_one_stub (struct bfd_hash_entry *gen_entry, void *in_arg)
 {
   struct elf_aarch64_stub_hash_entry *stub_entry;
-  struct elf_aarch64_link_hash_table *htab;
+  struct elf_aarch64_link_hash_table *htab ATTRIBUTE_UNUSED;
   int size;
 
   /* Massage our args to the form they really have.  */
@@ -3433,7 +3437,7 @@ aarch64_size_one_stub (struct bfd_hash_entry *gen_entry, void *in_arg)
       break;
     case aarch64_stub_erratum_843419_veneer:
       {
-	if (htab->fix_erratum_843419 == ERRAT_ADR)
+	if (stub_entry->stub_sec == NULL)
 	  return true;
 	size = sizeof (aarch64_erratum_843419_stub);
       }

-- 
Alan Modra

From hjl.tools@gmail.com  Fri Jun 26 04:06:50 2026
From: hjl.tools@gmail.com (H.J. Lu)
Date: Fri, 26 Jun 2026 12:06:50 +0800
Subject: [PATCH v4] elf: Set image base address to the maximum page size
In-Reply-To: <CAMe9rOpmyweh-+Dp4F_K2H15C4x+aTSO__fLRFxCivMnA+oDKg@mail.gmail.com>
References: <05c74589-fa62-4673-bb6e-9154d37024ee@redhat.com>
 <CAMe9rOpmyweh-+Dp4F_K2H15C4x+aTSO__fLRFxCivMnA+oDKg@mail.gmail.com>
Message-ID: <CAMe9rOoW4dnsHBBLqAbHS_6fTaDwmSbjw=Ah2M0SaZVWei7i4Q@mail.gmail.com>

On Thu, Jun 25, 2026 at 11:46?PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Thu, Jun 25, 2026 at 10:42?PM Nick Clifton <nickc@redhat.com> wrote:
> >
> > Hi H.J.
> >
> > >       PR ld/34184
> > >       * ldexp.c (fold_binary): Set text-segment address to the maximum
> > >       page size for ELF PDE output with -z max-page-size=SIZE.
> > >       * testsuite/ld-elf/elf.exp: Add ld/34184 test.
> > >       * testsuite/ld-elf/pr34184.c: New file.
> >
> > I like this patch, but I do have a couple of comments:
> >
> > > +      /* When generating Position Dependent Executable for ELF with the
> > > +      maximum page size set on command-line, if text-segment address
> > > +      is lower than the maximum page size, set text-segment address
> > > +      to the maximum page size.  */
> > > +      if ((bfd_get_flavour (link_info.output_bfd)
> > > +        == bfd_target_elf_flavour)
> > > +       && bfd_link_pde (&link_info)
> > > +       && link_info.maxpagesize_is_set
> > > +       && link_info.maxpagesize > value
> > > +       && strcmp (segment_name, "text-segment") == 0)
> > > +     value = link_info.maxpagesize;
> >
> > I think that it would be helpful to inform the user that the text
> > segment address is being changed - *if* they have tried to set it
> > using --image-base or --Ttext-segment.  Otherwise they may wonder
> > why their command line option is being ignored.
>
> Will do.

Fixed in the v4 patch.

> >
> > > +    [list \
> > > +     "Run pr34184" \
> > > +     "-Wl,-z,max-page-size=0x800000" \
> > > +     "" \
> > > +     {pr34184.c} \
> > > +     "pr34184" \
> > > +     "pass.out" \
> > > +    ] \
> >
> > As far as I can tell, this test does not actually check that
> > the text segment's address is now a multiple of the max page
> > size...
>
> This is a run-time test.  Without the fix, we get segfault:
>
> [hjl@gnu-tgl-3 tmp]$ cat x.c
> int
> main ()
> {
>   return 0;
> }
> [hjl@gnu-tgl-3 tmp]$ gcc -Wl,-z,max-page-size=0x800000 x.c
> [hjl@gnu-tgl-3 tmp]$ ./a.out
> Segmentation fault         ./a.out
> [hjl@gnu-tgl-3 tmp]$
>
>
> --
> H.J.

Here is the v4 patch.

-- 
H.J.
---
When generating Position Dependent Executable for ELF with the maximum
page size set on command-line, set the default image base address to the
maximum page size to avoid segfault if it is lower than the maximum page
size and issue an warning if the image base address set on command-line
is lower than the maximum page size.

PR ld/34184
* ldexp.c (fold_binary): Set the default image base address to
the maximum page size for ELF PDE output if it is lower than
the maximum page size set on command-line and issue an warning
if the image base address set on command-line is lower than the
maximum page size.
* testsuite/ld-elf/elf.exp: Add ld/34184 tests for PDE, PIE
static PDE and static PIE.
* testsuite/ld-elf/pr34184.c: New file.
* testsuite/ld-elf/textaddr3.d: Change -Ttext-segment adddress
to 0x200100 so that it > the maximum page size.
* testsuite/ld-elf/textaddr5.d: Likewise.
* testsuite/ld-elf/textaddr8.d: New test.
* testsuite/ld-elf/textaddr9.d: Likewise.
-------------- next part --------------
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From builder@sourceware.org  Fri Jun 26 04:44:51 2026
From: builder@sourceware.org (builder@sourceware.org)
Date: Fri, 26 Jun 2026 04:44:51 +0000
Subject: =?utf-8?q?=E2=98=BA_Buildbot_=28Sourceware=29=3A_binutils-gdb_-_build_successful_=28master=29?=
Message-ID: <20260626044451.E28CD4BA2E07@sourceware.org>

A restored build has been detected on builder binutils-fedora-arm64 while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/176/builds/6034

Build state: build successful
Revision: 1901eb4aa2594c016d097b7818ce4230fb63fbd7
Worker: fedora-arm64
Build Reason: (unknown)
Blamelist: Claudiu Zissulescu <claudiu.zissulescu-ianculescu@amd.com>, GDB Administrator <gdbadmin@sourceware.org>, Georg-Johann Lay <avr@gjlay.de>, Simon Marchi <simon.marchi@polymtl.ca>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/3/logs/config_log

- 4: make ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/4/logs/stdio
        - warnings (47): https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/4/logs/warnings__47_

- 5: make check (no ld) ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/5/logs/stdio
        - gas.sum: https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/5/logs/gas_sum
        - gas.log: https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/5/logs/gas_log
        - binutils.sum: https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/5/logs/binutils_sum
        - binutils.log: https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/5/logs/binutils_log
        - libsframe.sum: https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/5/logs/libsframe_sum
        - libsframe.log: https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/5/logs/libsframe_log
        - libctf.sum: https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/5/logs/libctf_sum
        - libctf.log: https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/5/logs/libctf_log
        - warnings (12): https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/5/logs/warnings__12_

- 6: make check ld ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/6/logs/stdio
        - ld.sum: https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/6/logs/ld_sum
        - ld.log: https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/6/logs/ld_log
        - warnings (3): https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/6/logs/warnings__3_

- 7: prep ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/7/logs/stdio

- 8: collect system versions ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/8/logs/stdio

- 9: fetch .bunsen.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/9/logs/stdio

- 10: build bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/10/logs/stdio

- 11: fetch bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/11/logs/stdio

- 12: unpack bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/12/logs/stdio

- 13: pass .bunsen.source.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/13/logs/stdio

- 14: upload to bunsen ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/14/logs/stdio

- 15: clean up ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/15/logs/stdio

- 16: rm -rf binutils-build_1 ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/176/builds/6034/steps/16/logs/stdio


From nelson.chu@sifive.com  Fri Jun 26 05:15:36 2026
From: nelson.chu@sifive.com (Nelson Chu)
Date: Fri, 26 Jun 2026 13:15:36 +0800
Subject: [committed 1/2] MAINTAINERS: Update my email address
Message-ID: <20260626051537.79399-1-nelson.chu@sifive.com>

---
 binutils/MAINTAINERS | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/binutils/MAINTAINERS b/binutils/MAINTAINERS
index af60369b8ca..d5a286afa7f 100644
--- a/binutils/MAINTAINERS
+++ b/binutils/MAINTAINERS
@@ -123,7 +123,7 @@ responsibility among the other maintainers.
   RISC-V	   Palmer Dabbelt <palmer@dabbelt.com>
   RISC-V	   Andrew Waterman <andrew@sifive.com>
   RISC-V	   Jim Wilson <jim.wilson.gcc@gmail.com>
-  RISC-V	   Nelson Chu <nelson.chu1990@gmail.com>
+  RISC-V	   Nelson Chu <nelson.chu@sifive.com>
   RX               Nick Clifton <nickc@redhat.com>
   S12Z		   John Darrington <john@darrington.wattle.id.au>
   s390, s390x	   Andreas Krebbel <krebbel@linux.ibm.com>
-- 
2.50.1 (Apple Git-155)


From nelson.chu@sifive.com  Fri Jun 26 05:15:37 2026
From: nelson.chu@sifive.com (Nelson Chu)
Date: Fri, 26 Jun 2026 13:15:37 +0800
Subject: [committed 2/2] RISC-V: Minor fix the gas march-help.l testcase
In-Reply-To: <20260626051537.79399-1-nelson.chu@sifive.com>
References: <20260626051537.79399-1-nelson.chu@sifive.com>
Message-ID: <20260626051537.79399-2-nelson.chu@sifive.com>

---
 gas/testsuite/gas/riscv/march-help.l | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index a04d720d5b4..db6a86bc287 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -126,7 +126,7 @@ All available -march extensions for RISC-V:
 	smcntrpmf                               1.0
 	smctr                                   1.0
 	smepmp                                  1.0
-	smpmpmt                                 0.6
+	smpmpmt                                 1.0
 	smrnmi                                  1.0
 	smstateen                               1.0
 	smdbltrp                                1.0
-- 
2.50.1 (Apple Git-155)


From jbeulich@suse.com  Fri Jun 26 06:00:53 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 26 Jun 2026 08:00:53 +0200
Subject: [PATCH v3] RISC-V: Fix build with GCC-8
In-Reply-To: <alpine.DEB.2.21.2606252232520.58268@angie.orcam.me.uk>
References: <f2abf263-4730-4ccd-af87-e3de2289b35c@suse.com>
 <20260623133508.2896582-1-zhuangqiubin@linux.spacemit.com>
 <alpine.DEB.2.21.2606252232520.58268@angie.orcam.me.uk>
Message-ID: <7f84f26f-9f88-4690-8f61-e7e893831f65@suse.com>

On 25.06.2026 23:43, Maciej W. Rozycki wrote:
> On Tue, 23 Jun 2026, Mark Zhuang wrote:
> 
>> From: Mark Zhuang <mark.zhuang@spacemit.com>
>>
>> GCC 8.5.0 rejects a declaration right after a case label.
>> Add braces to fix it.
> 
>  I think it would be more useful to the reader if the commit referred to 
> the relevant C language standard and minimum compiler version as given by 
> Andreas: <https://inbox.sourceware.org/binutils/mvmtsqtzgve.fsf@suse.de/>.

To be honest, I think relatively basic standard C aspects should be known
to people, and "rejects a declaration right after a case label" is enough
of a pointer imo.

>  FWIW it broke the build with GCC 10.2.1 here (production box, system
> compiler).

At the risk of coming across blunt, but: You complain about too little
detail above, and then you report this issue without providing any detail?

Jan

From jbeulich@suse.com  Fri Jun 26 06:25:32 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 26 Jun 2026 08:25:32 +0200
Subject: [PATCH v3] RISC-V: Fix build with GCC-8
In-Reply-To: <20260623133508.2896582-1-zhuangqiubin@linux.spacemit.com>
References: <f2abf263-4730-4ccd-af87-e3de2289b35c@suse.com>
 <20260623133508.2896582-1-zhuangqiubin@linux.spacemit.com>
Message-ID: <6c0637ec-e589-4688-8d26-59e36632aaf8@suse.com>

On 23.06.2026 15:35, Mark Zhuang wrote:
> From: Mark Zhuang <mark.zhuang@spacemit.com>
> 
> GCC 8.5.0 rejects a declaration right after a case label.
> Add braces to fix it.

While I said I'd take care of getting this in, now I really can't seeing that
Maciej reported this breaks gcc10 (in a way unknown to me, as of yet).

As this made me look at the patch again (just to see if I can spot anything,
which I couldn't), ...

> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -1791,8 +1791,6 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
>  		}
>  		break;
>  	    case 'p': /* Vendor-specific (SpacemiT) operands.  */
> -	      size_t n;
> -	      size_t s;
>  	      switch (*++oparg)
>  		{
>  		case 'V':
> @@ -1815,13 +1813,15 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
>  		  break;
>  		case 'u': /* Integer immediate, 'XpuN@S' ...
>  			     N-bit unsigned immediate at bit S.  */
> -		  n = strtol (oparg + 1, (char **)&oparg, 10);
> -		  if (*oparg != '@')
> -		    goto unknown_validate_operand;
> -		  s = strtol (oparg + 1, (char **)&oparg, 10);
> -		  oparg--;
> -		  USE_IMM (n, s);
> -		  break;
> +		  {
> +		    size_t n = strtol (oparg + 1, (char **)&oparg, 10);
> +		    if (*oparg != '@')
> +		      goto unknown_validate_operand;
> +		    size_t s = strtol (oparg + 1, (char **)&oparg, 10);
> +		    oparg--;
> +		    USE_IMM (n, s);
> +		    break;
> +		  }

... I think the "break" here and ...

> @@ -4309,8 +4309,6 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
>  		  break;
>  
>  		case 'p': /* Vendor-specific (SpacemiT) operands.  */
> -		  size_t n;
> -		  size_t s;
>  		  switch (*++oparg)
>  		    {
>  		    case 'V':
> @@ -4358,20 +4356,22 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
>  		      break;
>  		    case 'u': /* Integer immediate, 'XpuN@S' ...
>  				 N-bit unsigned immediate at bit S.  */
> -		      n = strtol (oparg + 1, (char **)&oparg, 10);
> -		      if (*oparg != '@')
> -			goto unknown_riscv_ip_operand;
> -		      s = strtol (oparg + 1, (char **)&oparg, 10);
> -		      oparg--;
> -		      my_getExpression (imm_expr, asarg, force_reloc);
> -		      check_absolute_expr (ip, imm_expr, false);
> -		      if (!VALIDATE_U_IMM (imm_expr->X_add_number, n))
> -			as_bad (_("improper immediate value (%"PRIu64")"),
> -				imm_expr->X_add_number);
> -		      INSERT_IMM (n, s, *ip, imm_expr->X_add_number);
> -		      imm_expr->X_op = O_absent;
> -		      asarg = expr_parse_end;
> -		      continue;
> +		      {
> +			size_t n = strtol (oparg + 1, (char **)&oparg, 10);
> +			if (*oparg != '@')
> +			  goto unknown_riscv_ip_operand;
> +			size_t s = strtol (oparg + 1, (char **)&oparg, 10);
> +			oparg--;
> +			my_getExpression (imm_expr, asarg, force_reloc);
> +			check_absolute_expr (ip, imm_expr, false);
> +			if (!VALIDATE_U_IMM (imm_expr->X_add_number, n))
> +			  as_bad (_("improper immediate value (%"PRIu64")"),
> +				  imm_expr->X_add_number);
> +			INSERT_IMM (n, s, *ip, imm_expr->X_add_number);
> +			imm_expr->X_op = O_absent;
> +			asarg = expr_parse_end;
> +			continue;
> +		      }

... the "continue" here would be nice to keep in their original positions,
just like ...

> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -924,14 +924,18 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
>  		  switch (*++oparg)
>  		    {
>  		    case 'd':
> -		      unsigned vd = EXTRACT_OPERAND (SPACEMIT_IME_VD, l) * 2;
> -		      print (info->stream, dis_style_register, "%s",
> -			     riscv_vecr_names_numeric[vd]);
> +		      {
> +			unsigned vd = EXTRACT_OPERAND (SPACEMIT_IME_VD, l) * 2;
> +			print (info->stream, dis_style_register, "%s",
> +			       riscv_vecr_names_numeric[vd]);
> +		      }
>  		      break;
>  		    case 's':
> -		      unsigned vs = EXTRACT_OPERAND (SPACEMIT_IME_VS1, l) * 2;
> -		      print (info->stream, dis_style_register, "%s",
> -			     riscv_vecr_names_numeric[vs]);
> +		      {
> +			unsigned vs = EXTRACT_OPERAND (SPACEMIT_IME_VS1, l) * 2;
> +			print (info->stream, dis_style_register, "%s",
> +			       riscv_vecr_names_numeric[vs]);
> +		      }
>  		      break;

... you do here. Once again, I'm happy to adjust while committing, just that
first we need to understand and address the gcc10 issue. Maciej, please
provide details.

Jan

From jbeulich@suse.com  Fri Jun 26 06:59:52 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 26 Jun 2026 08:59:52 +0200
Subject: [PATCH v2] PE/COFF: auto-promote oversized objects to bigobj
In-Reply-To: <20260623213900.2000-2-oleg.tolmatcev@gmail.com>
References: <20260623213900.2000-2-oleg.tolmatcev@gmail.com>
Message-ID: <f17fa2b9-a855-4458-8676-bd4d74c193d4@suse.com>

On 23.06.2026 23:39, Oleg Tolmatcev wrote:
> @@ -3154,6 +3158,16 @@ coff_compute_section_file_positions (bfd * abfd)
>  
>    if (target_index >= bfd_coff_max_nscns (abfd))
>      {
> +#ifdef COFF_WITH_PE_BIGOBJ
> +      if (abfd->xvec != &TARGET_SYM_BIG)
> +	{
> +	  /* Regular PE/COFF uses 16-bit section numbers in symbols.
> +	     Promote oversized objects to the matching bigobj target
> +	     before any headers or symbols are finalized.  */
> +	  abfd->xvec = &TARGET_SYM_BIG;
> +	  return coff_compute_section_file_positions (abfd);
> +	}
> +#endif
>        bfd_set_error (bfd_error_file_too_big);
>        _bfd_error_handler
>  	/* xgettext:c-format */

It occurs to me only now that this new behavior affects not only COFF
objects, but also PE binaries. For the former the defaulting is imo okay
(as previously indicated), as you'll notice when linking that the linker
can't deal with the objects (and a newer linker needs using, or section
count needs bringing down). For the latter, however, an executable may
be produced which you have no way of knowing that it won't work with
certain loaders (because all you can ever test with is a limited set of
loaders). IOW I think the conditional may want to be

#if defined(COFF_WITH_PE_BIGOBJ) && !defined(COFF_IMAGE_WITH_PE)

Thoughts? I can certainly make that adjustment while committing, as
long as we can come to an agreement.

Jan

From jbeulich@suse.com  Fri Jun 26 07:06:51 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 26 Jun 2026 09:06:51 +0200
Subject: [PATCH] objdump: Fix private header ('-p') import table output
 for pe-aarch64
In-Reply-To: <20260619134339.73604-1-jon.turney@dronecode.org.uk>
References: <20260619134339.73604-1-jon.turney@dronecode.org.uk>
Message-ID: <aa44ecbb-b833-4776-aff5-92b79e3343fc@suse.com>

On 19.06.2026 15:43, Jon Turney wrote:
> The private header ('-p') import table output for pe-aarch64 (and
> probably all other 64-bit arches apart from x86_64) is truncated after the
> first import.
> 
> The distinction between the conditional branches here should be between
> PE32 (32-bit) and PE32+ (somewhat confusingly, the 64-bit version of the
> PE format).
> 
> PE file format specification [1] states under "Import Lookup Table":
> 
> "An import lookup table is an array of 32-bit numbers for PE32 or an
> array of 64-bit numbers for PE32+."
> 
> [1] https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#import-lookup-table
> 
> 2026-06-19  Jon Turney  <jon.turney@dronecode.org.uk>
> 
> 	* peXXigen.c (pe_print_idata): Fix conditional.

Okay, albeit preferably with ...

> --- a/bfd/peXXigen.c
> +++ b/bfd/peXXigen.c
> @@ -1462,7 +1462,7 @@ pe_print_idata (bfd * abfd, void * vfile)
>  	    }
>  
>  	  /* Print HintName vector entries.  */
> -#ifdef COFF_WITH_pex64
> +#if defined COFF_WITH_pep || defined COFF_WITH_pex64 || defined COFF_WITH_peAArch64 || defined COFF_WITH_peLoongArch64 || defined COFF_WITH_peRiscV64

... this line split for each part to remain within 80 columns (no matter
that other such long lines exist). Perhaps they all should be consolidated
into the checking of a single (new) manifest constant, such that mistakes
like the one being fixed here are easier to avoid. But that's for later.

Jan

Jan

From oleg.tolmatcev@gmail.com  Fri Jun 26 07:37:53 2026
From: oleg.tolmatcev@gmail.com (Oleg Tolmatcev)
Date: Fri, 26 Jun 2026 09:37:53 +0200
Subject: [PATCH v2] PE/COFF: auto-promote oversized objects to bigobj
In-Reply-To: <f17fa2b9-a855-4458-8676-bd4d74c193d4@suse.com>
References: <20260623213900.2000-2-oleg.tolmatcev@gmail.com>
 <f17fa2b9-a855-4458-8676-bd4d74c193d4@suse.com>
Message-ID: <CACcXsZgUOUwVhGHxA3fDdX68yQ=iemdm3D_=VAYgUxkzu+g=mg@mail.gmail.com>

Am Fr., 26. Juni 2026 um 08:59 Uhr schrieb Jan Beulich <jbeulich@suse.com>:
>
> On 23.06.2026 23:39, Oleg Tolmatcev wrote:
> > @@ -3154,6 +3158,16 @@ coff_compute_section_file_positions (bfd * abfd)
> >
> >    if (target_index >= bfd_coff_max_nscns (abfd))
> >      {
> > +#ifdef COFF_WITH_PE_BIGOBJ
> > +      if (abfd->xvec != &TARGET_SYM_BIG)
> > +     {
> > +       /* Regular PE/COFF uses 16-bit section numbers in symbols.
> > +          Promote oversized objects to the matching bigobj target
> > +          before any headers or symbols are finalized.  */
> > +       abfd->xvec = &TARGET_SYM_BIG;
> > +       return coff_compute_section_file_positions (abfd);
> > +     }
> > +#endif
> >        bfd_set_error (bfd_error_file_too_big);
> >        _bfd_error_handler
> >       /* xgettext:c-format */
>
> It occurs to me only now that this new behavior affects not only COFF
> objects, but also PE binaries. For the former the defaulting is imo okay
> (as previously indicated), as you'll notice when linking that the linker
> can't deal with the objects (and a newer linker needs using, or section
> count needs bringing down). For the latter, however, an executable may
> be produced which you have no way of knowing that it won't work with
> certain loaders (because all you can ever test with is a limited set of
> loaders). IOW I think the conditional may want to be
>
> #if defined(COFF_WITH_PE_BIGOBJ) && !defined(COFF_IMAGE_WITH_PE)
>
> Thoughts? I can certainly make that adjustment while committing, as
> long as we can come to an agreement.

I agree. The COFF objects case is the important one for me. Thanks.

Oleg.

From builder@sourceware.org  Fri Jun 26 07:42:50 2026
From: builder@sourceware.org (builder@sourceware.org)
Date: Fri, 26 Jun 2026 07:42:50 +0000
Subject: =?utf-8?q?=E2=98=BA_Buildbot_=28Sourceware=29=3A_binutils-gdb_-_build_successful_=28master=29?=
Message-ID: <20260626074250.2A7084BA2E17@sourceware.org>

A restored build has been detected on builder binutils-ubuntu-riscv while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/283/builds/3198

Build state: build successful
Revision: 5c88753f7b52e9bfbaf0e26239b179e4a8bb1142
Worker: starfive-4
Build Reason: (unknown)
Blamelist: Aditya Kamath <Aditya.Kamath1@ibm.com>, Andrew Burgess <aburgess@redhat.com>, Claudiu Zissulescu <claudiu.zissulescu-ianculescu@amd.com>, GDB Administrator <gdbadmin@sourceware.org>, Georg-Johann Lay <avr@gjlay.de>, Guinevere Larsen <guinevere@redhat.com>, H.J. Lu <hjl.tools@gmail.com>, Jerry Zhang Jian <jerry.zhangjian@sifive.com>, Nelson Chu <nelson.chu@sifive.com>, Simon Marchi <simon.marchi@polymtl.ca>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/3/logs/config_log

- 4: make ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/4/logs/stdio
        - warnings (12): https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/4/logs/warnings__12_

- 5: make check (no ld) ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/5/logs/stdio
        - gas.sum: https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/5/logs/gas_sum
        - gas.log: https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/5/logs/gas_log
        - binutils.sum: https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/5/logs/binutils_sum
        - binutils.log: https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/5/logs/binutils_log
        - libsframe.sum: https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/5/logs/libsframe_sum
        - libsframe.log: https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/5/logs/libsframe_log
        - libctf.sum: https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/5/logs/libctf_sum
        - libctf.log: https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/5/logs/libctf_log
        - warnings (8): https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/5/logs/warnings__8_

- 6: make check ld ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/6/logs/stdio
        - ld.sum: https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/6/logs/ld_sum
        - ld.log: https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/6/logs/ld_log
        - warnings (2): https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/6/logs/warnings__2_

- 7: prep ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/7/logs/stdio

- 8: collect system versions ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/8/logs/stdio

- 9: fetch .bunsen.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/9/logs/stdio

- 10: build bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/10/logs/stdio

- 11: fetch bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/11/logs/stdio

- 12: unpack bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/12/logs/stdio

- 13: pass .bunsen.source.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/13/logs/stdio

- 14: upload to bunsen ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/14/logs/stdio

- 15: clean up ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/15/logs/stdio

- 16: rm -rf binutils-build_1 ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3198/steps/16/logs/stdio


From macro@orcam.me.uk  Fri Jun 26 11:02:42 2026
From: macro@orcam.me.uk (Maciej W. Rozycki)
Date: Fri, 26 Jun 2026 12:02:42 +0100 (BST)
Subject: [PATCH v3] RISC-V: Fix build with GCC-8
In-Reply-To: <7f84f26f-9f88-4690-8f61-e7e893831f65@suse.com>
References: <f2abf263-4730-4ccd-af87-e3de2289b35c@suse.com>
 <20260623133508.2896582-1-zhuangqiubin@linux.spacemit.com>
 <alpine.DEB.2.21.2606252232520.58268@angie.orcam.me.uk>
 <7f84f26f-9f88-4690-8f61-e7e893831f65@suse.com>
Message-ID: <alpine.DEB.2.21.2606261151490.58268@angie.orcam.me.uk>

On Fri, 26 Jun 2026, Jan Beulich wrote:

> >  I think it would be more useful to the reader if the commit referred to 
> > the relevant C language standard and minimum compiler version as given by 
> > Andreas: <https://inbox.sourceware.org/binutils/mvmtsqtzgve.fsf@suse.de/>.
> 
> To be honest, I think relatively basic standard C aspects should be known
> to people, and "rejects a declaration right after a case label" is enough
> of a pointer imo.

 I don't expect everyone to track or remember all the individual features 
as they are added to standard revisions or compiler implementations, and 
details provided by Andreas are useful in determining the prerequsites.

 Indeed the breakage caused in the first place serves as a proof: you'd 
imply the code writer as well the approver should have known this feature 
isn't there in every compiler version supported for building binutils, and 
yet they missed it.

 Why do you think it would be preferable to require everyone to chase 
every time something that has been already determined?

> >  FWIW it broke the build with GCC 10.2.1 here (production box, system
> > compiler).
> 
> At the risk of coming across blunt, but: You complain about too little
> detail above, and then you report this issue without providing any detail?

 Why would I need to repeat the same exact details as with the original 
report?  This is just to confirm that the same issue triggers for versions 
other than 8.5.0 (just as Andreas has indicated).  I reckon Andrew Burgess 
also reported breakage with his environment.

  Maciej

From macro@orcam.me.uk  Fri Jun 26 11:04:10 2026
From: macro@orcam.me.uk (Maciej W. Rozycki)
Date: Fri, 26 Jun 2026 12:04:10 +0100 (BST)
Subject: [PATCH v3] RISC-V: Fix build with GCC-8
In-Reply-To: <6c0637ec-e589-4688-8d26-59e36632aaf8@suse.com>
References: <f2abf263-4730-4ccd-af87-e3de2289b35c@suse.com>
 <20260623133508.2896582-1-zhuangqiubin@linux.spacemit.com>
 <6c0637ec-e589-4688-8d26-59e36632aaf8@suse.com>
Message-ID: <alpine.DEB.2.21.2606261203340.58268@angie.orcam.me.uk>

On Fri, 26 Jun 2026, Jan Beulich wrote:

> > --- a/opcodes/riscv-dis.c
> > +++ b/opcodes/riscv-dis.c
> > @@ -924,14 +924,18 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
> >  		  switch (*++oparg)
> >  		    {
> >  		    case 'd':
> > -		      unsigned vd = EXTRACT_OPERAND (SPACEMIT_IME_VD, l) * 2;
> > -		      print (info->stream, dis_style_register, "%s",
> > -			     riscv_vecr_names_numeric[vd]);
> > +		      {
> > +			unsigned vd = EXTRACT_OPERAND (SPACEMIT_IME_VD, l) * 2;
> > +			print (info->stream, dis_style_register, "%s",
> > +			       riscv_vecr_names_numeric[vd]);
> > +		      }
> >  		      break;
> >  		    case 's':
> > -		      unsigned vs = EXTRACT_OPERAND (SPACEMIT_IME_VS1, l) * 2;
> > -		      print (info->stream, dis_style_register, "%s",
> > -			     riscv_vecr_names_numeric[vs]);
> > +		      {
> > +			unsigned vs = EXTRACT_OPERAND (SPACEMIT_IME_VS1, l) * 2;
> > +			print (info->stream, dis_style_register, "%s",
> > +			       riscv_vecr_names_numeric[vs]);
> > +		      }
> >  		      break;
> 
> ... you do here. Once again, I'm happy to adjust while committing, just that
> first we need to understand and address the gcc10 issue. Maciej, please
> provide details.

 The original report has them.

  Maciej

From claziss@gmail.com  Fri Jun 26 11:33:18 2026
From: claziss@gmail.com (Claudiu Zissulescu)
Date: Fri, 26 Jun 2026 14:33:18 +0300
Subject: [PATCH 0/4] gprofng: Improve HW counter markings and documentation
Message-ID: <20260626113840.44715-1-claziss@gmail.com>

Hi all,

Here is a patch series for gprofng that improves the display of
hardware counter precision information and adds related documentation.

These patches have neem tested on x86 architecture.

Any feedback is welcomed,
Claudiu


Claudiu Zissulescu (4):
  gprofng: group precise vs. non-precise HW counters in -h listing
  gprofng: mark non-precise HW counter columns and add report footnote
  gprofng: testsuite coverage for HW-counter precision markings
  gprofng: document HW-counter interface, precise events, and
    source-line metrics

 gprofng/common/hwctable.c                     | 78 +++++++++++++++----
 gprofng/doc/gprofng_ug.texi                   | 52 +++++++++++++
 gprofng/src/Hist_data.cc                      | 27 +++++++
 gprofng/src/Metric.cc                         | 16 +++-
 gprofng/src/Print.cc                          | 26 +++++++
 .../testsuite/gprofng.display/hwc_listing.exp | 60 ++++++++++++++
 .../gprofng.display/hwc_precision_marker.exp  | 72 +++++++++++++++++
 7 files changed, 315 insertions(+), 16 deletions(-)
 create mode 100644 gprofng/testsuite/gprofng.display/hwc_listing.exp
 create mode 100644 gprofng/testsuite/gprofng.display/hwc_precision_marker.exp

-- 
2.54.0


From claziss@gmail.com  Fri Jun 26 11:33:19 2026
From: claziss@gmail.com (Claudiu Zissulescu)
Date: Fri, 26 Jun 2026 14:33:19 +0300
Subject: [PATCH 1/4] gprofng: group precise vs. non-precise HW counters
In-Reply-To: <20260626113840.44715-1-claziss@gmail.com>
References: <20260626113840.44715-1-claziss@gmail.com>
Message-ID: <20260626113840.44715-2-claziss@gmail.com>

The -h listing prints all available HW counters in a single,
undifferentiated block. In that view, "type" column shows
"memoryspace" for PEBS/IBS events. Users can't tell from listing
alone that "memoryspace" means precise sample attribution, while
other event types may attribute samples slightly "late". This mismatch
is the most common source of confusion when reading source-view
reports.

To make this clearer, split the "std-ctrs" and "raw-ctrs" listings
into two sub-sections each ("Precise events" and "Standard events"),
and append "(precise)" to the type label for ABST_EXACT /
ABST_EXACT_PEBS_PLUS1 counters.

This change is only a reordering of existing entries?no counters are
added, removed, or renamed.

gprofng/
	* common/hwctable.c (hwc_memop_string): Tag ABST_EXACT and
	ABST_EXACT_PEBS_PLUS1 as precise.
	(hwc_usage_internal): Emit std and raw counter lists in two
	passes: precise events and standard events.
---
 gprofng/common/hwctable.c | 78 ++++++++++++++++++++++++++++++++-------
 1 file changed, 65 insertions(+), 13 deletions(-)

diff --git a/gprofng/common/hwctable.c b/gprofng/common/hwctable.c
index 52b28f21dc5..cb8a5e43763 100644
--- a/gprofng/common/hwctable.c
+++ b/gprofng/common/hwctable.c
@@ -2946,7 +2946,7 @@ hwc_memop_string (ABST_type memop)
       break;
     case ABST_EXACT_PEBS_PLUS1:
     case ABST_EXACT:
-      s = GTXT ("memoryspace ");
+      s = GTXT ("memoryspace (precise) ");
       break;
     case ABST_COUNT:
       s = GTXT ("count ");
@@ -3656,31 +3656,83 @@ hwc_usage_internal (int forKernel, FILE *f_usage, const char *cmd, const char *d
 
   /* long listings */
   char tmp[1024];
+  /* Counters whose memop is ABST_EXACT or ABST_EXACT_PEBS_PLUS1 deliver
+     precise PC attribution (IBS on AMD, PEBS on Intel).  All others can
+     skid forward by several instructions, which is the single most common
+     source of user confusion when reading source-view reports.  Group the
+     listing so the precise events are visible and labeled.  */
+#define HWC_IS_PRECISE(ctr) \
+  (HWCENTRY_USES_SAMPLING (ctr) || (ctr)->memop == ABST_EXACT)
+
   if (has_std_ctrs)
     {
-      fprintf (f_usage, GTXT ("\nAliases for most useful HW counters:\n\n"));
-      format_columns (tmp, 1024, "alias", "raw name", "type ", "units", "description");
-      fprintf (f_usage, NTXT ("    %s\n\n"), tmp);
+      int n_precise = 0;
       for (Hwcentry **pctr = std_ctrs; *pctr; pctr++)
+	if (HWC_IS_PRECISE (*pctr))
+	  n_precise++;
+
+      fprintf (f_usage, GTXT ("\nAliases for most useful HW counters:\n"));
+      if (n_precise)
 	{
-	  Hwcentry *ctr = *pctr;
-	  hwc_hwcentry_string_internal (tmp, sizeof (tmp), ctr, 0);
-	  fprintf (f_usage, NTXT ("    %s\n"), tmp);
+	  fprintf (f_usage, GTXT ("\n  Precise events (recommended for accurate"
+				  " instruction/line attribution):\n\n"));
+	  format_columns (tmp, 1024, "alias", "raw name", "type ", "units", "description");
+	  fprintf (f_usage, NTXT ("    %s\n\n"), tmp);
+	  for (Hwcentry **pctr = std_ctrs; *pctr; pctr++)
+	    if (HWC_IS_PRECISE (*pctr))
+	      {
+		hwc_hwcentry_string_internal (tmp, sizeof (tmp), *pctr, 0);
+		fprintf (f_usage, NTXT ("    %s\n"), tmp);
+	      }
 	}
+
+      fprintf (f_usage, GTXT ("\n  Standard events (sample location may"
+			      " skid forward several instructions):\n\n"));
+      format_columns (tmp, 1024, "alias", "raw name", "type ", "units", "description");
+      fprintf (f_usage, NTXT ("    %s\n\n"), tmp);
+      for (Hwcentry **pctr = std_ctrs; *pctr; pctr++)
+	if (!HWC_IS_PRECISE (*pctr))
+	  {
+	    hwc_hwcentry_string_internal (tmp, sizeof (tmp), *pctr, 0);
+	    fprintf (f_usage, NTXT ("    %s\n"), tmp);
+	  }
     }
   if (has_raw_ctrs)
     {
-      fprintf (f_usage, GTXT ("\nRaw HW counters:\n\n"));
+      int n_precise = 0;
+      for (Hwcentry **pctr = raw_ctrs; *pctr; pctr++)
+	if (HWC_IS_PRECISE (*pctr))
+	  n_precise++;
+
+      fprintf (f_usage, GTXT ("\nRaw HW counters:\n"));
       hwc_usage_raw_overview_sparc (f_usage, cpuver);
+
+      if (n_precise)
+	{
+	  fprintf (f_usage, GTXT ("\n  Precise events (recommended for accurate"
+				  " instruction/line attribution):\n\n"));
+	  format_columns (tmp, 1024, "name", NULL, "type ", "units", "description");
+	  fprintf (f_usage, NTXT ("    %s\n\n"), tmp);
+	  for (Hwcentry **pctr = raw_ctrs; *pctr; pctr++)
+	    if (HWC_IS_PRECISE (*pctr))
+	      {
+		hwc_hwcentry_string_internal (tmp, sizeof (tmp), *pctr, show_short_desc);
+		fprintf (f_usage, NTXT ("    %s\n"), tmp);
+	      }
+	}
+
+      fprintf (f_usage, GTXT ("\n  Standard events (sample location may"
+			      " skid forward several instructions):\n\n"));
       format_columns (tmp, 1024, "name", NULL, "type ", "units", "description");
       fprintf (f_usage, NTXT ("    %s\n\n"), tmp);
       for (Hwcentry **pctr = raw_ctrs; *pctr; pctr++)
-	{
-	  Hwcentry *ctr = *pctr;
-	  hwc_hwcentry_string_internal (tmp, sizeof (tmp), ctr, show_short_desc);
-	  fprintf (f_usage, NTXT ("    %s\n"), tmp);
-	}
+	if (!HWC_IS_PRECISE (*pctr))
+	  {
+	    hwc_hwcentry_string_internal (tmp, sizeof (tmp), *pctr, show_short_desc);
+	    fprintf (f_usage, NTXT ("    %s\n"), tmp);
+	  }
     }
+#undef HWC_IS_PRECISE
 
   /* documentation notice */
   hwc_get_docref (tmp, 1024);
-- 
2.54.0


From claziss@gmail.com  Fri Jun 26 11:33:20 2026
From: claziss@gmail.com (Claudiu Zissulescu)
Date: Fri, 26 Jun 2026 14:33:20 +0300
Subject: [PATCH 2/4] gprofng: mark non-precise HW counter columns
In-Reply-To: <20260626113840.44715-1-claziss@gmail.com>
References: <20260626113840.44715-1-claziss@gmail.com>
Message-ID: <20260626113840.44715-3-claziss@gmail.com>

Mark the column header of any non-precise HW counter metric with "(*)"
and emit a single explanatory footnote below the column header block
when at least one displayed metric is non-precise.  Precise PEBS/IBS
events (ABST_EXACT, ABST_EXACT_PEBS_PLUS1) are left unmarked. Also
point the user at the "Precise events" section of -h output.

gprofng/

	* src/Metric.cc (Metric::set_name): Append "*" marker.
	* src/Print.cc (print_label): Emit a footnote explaining the "*"
	marker.
	* src/Hist_data.cc (Hist_data::print_label): Likewise.
---
 gprofng/src/Hist_data.cc | 27 +++++++++++++++++++++++++++
 gprofng/src/Metric.cc    | 16 +++++++++++++---
 gprofng/src/Print.cc     | 26 ++++++++++++++++++++++++++
 3 files changed, 66 insertions(+), 3 deletions(-)

diff --git a/gprofng/src/Hist_data.cc b/gprofng/src/Hist_data.cc
index 41e3edf3ae4..8818e84f215 100644
--- a/gprofng/src/Hist_data.cc
+++ b/gprofng/src/Hist_data.cc
@@ -863,6 +863,33 @@ Hist_data::print_label (FILE *out_file, Metric::HistMetric *hist_metric,
   sb1.toFileLn (out_file);
   sb2.toFileLn (out_file);
   sb3.toFileLn (out_file);
+
+  /* Footnote for non-precise HW counters (marked with " (*)" by
+     Metric::set_name).  Emit once if any visible metric uses such a
+     counter, so users understand source-line attribution may skid.
+     Mirrors the equivalent block in the free print_label() in Print.cc.  */
+  bool any_non_precise = false;
+  for (int i = 0; i < nmetrics && !any_non_precise; i++)
+    {
+      Metric *m = metrics->get (i);
+      if (!m->is_any_visible ())
+	continue;
+      if (m->get_type () != Metric::HWCNTR)
+	continue;
+      Hwcentry *hwc = m->get_hw_ctr ();
+      if (hwc != NULL
+	  && !HWCENTRY_USES_SAMPLING (hwc)
+	  && hwc->memop != ABST_EXACT)
+	any_non_precise = true;
+    }
+  if (any_non_precise)
+    fprintf (out_file, GTXT (
+      "%*s(*) Non-precise HW event: sample location may skid forward by\n"
+      "%*s    several instructions, so cache/branch misses are often\n"
+      "%*s    attributed to the next basic block (e.g. a loop header).\n"
+      "%*s    For exact line attribution, prefer precise events\n"
+      "%*s    (see the \"Precise events\" section of `gprofng collect app -h`).\n"),
+      space, "", space, "", space, "", space, "", space, "");
   return name_offset;
 }
 
diff --git a/gprofng/src/Metric.cc b/gprofng/src/Metric.cc
index a72bdaef6a3..f4264277bf9 100644
--- a/gprofng/src/Metric.cc
+++ b/gprofng/src/Metric.cc
@@ -306,7 +306,8 @@ Metric::set_subtype (SubType st)
     case HWCNTR:
       {
 	char *sstr, *estr1, *estr2;
-	if (get_hw_ctr () == NULL)
+	Hwcentry *hwc = get_hw_ctr ();
+	if (hwc == NULL)
 	  abort ();
 	sstr = get_username ();
 	if (st == EXCLUSIVE)
@@ -335,8 +336,17 @@ Metric::set_subtype (SubType st)
 				 get_aux (), st);
 	    estr2 = dbe_strdup (NTXT ("??"));
 	  }
-	name = dbe_sprintf (NTXT ("%s%s"), estr1, sstr);
-	abbr = dbe_sprintf (NTXT ("%s%s"), estr2, sstr);
+	/* Mark non-precise counters so users don't over-trust source-line
+	   attribution.  Only PEBS/EXACT events tag the retiring instruction;
+	   everything else may skid forward by several instructions.  The (*)
+	   should be explained by a footnote at report-print time.  */
+	const char *mark = "";
+	if ((st == EXCLUSIVE || st == INCLUSIVE || st == DATASPACE)
+	    && !HWCENTRY_USES_SAMPLING (hwc)
+	    && hwc->memop != ABST_EXACT)
+	  mark = " (*)";
+	name = dbe_sprintf (NTXT ("%s%s%s"), estr1, sstr, mark);
+	abbr = dbe_sprintf (NTXT ("%s%s%s"), estr2, sstr, mark);
 	break;
       }
 
diff --git a/gprofng/src/Print.cc b/gprofng/src/Print.cc
index 564e3a638bc..8d3cef4ede4 100644
--- a/gprofng/src/Print.cc
+++ b/gprofng/src/Print.cc
@@ -306,6 +306,32 @@ print_label (FILE *out_file, MetricList *metrics_list,
   fprintf (out_file, NTXT ("%*s%s\n"), space, NTXT (""), delTrailingBlanks (line1));
   fprintf (out_file, NTXT ("%*s%s\n"), space, NTXT (""), delTrailingBlanks (line2));
   fprintf (out_file, NTXT ("%*s%s\n"), space, NTXT (""), delTrailingBlanks (line3));
+
+  /* Footnote for non-precise HW counters (marked with " (*)" by
+     Metric::set_name).  Emit once if any visible metric uses such a
+     counter, so users understand source-line attribution may skid.  */
+  bool any_non_precise = false;
+  for (int i = 0, n = mlist->size (); i < n && !any_non_precise; i++)
+    {
+      Metric *m = mlist->fetch (i);
+      if (!(m->is_visible () || m->is_tvisible () || m->is_pvisible ()))
+	continue;
+      if (m->get_type () != Metric::HWCNTR)
+	continue;
+      Hwcentry *hwc = m->get_hw_ctr ();
+      if (hwc != NULL
+	  && !HWCENTRY_USES_SAMPLING (hwc)
+	  && hwc->memop != ABST_EXACT)
+	any_non_precise = true;
+    }
+  if (any_non_precise)
+    fprintf (out_file, GTXT (
+      "%*s(*) Non-precise HW event: sample location may skid forward by\n"
+      "%*s    several instructions, so cache/branch misses are often\n"
+      "%*s    attributed to the next basic block (e.g. a loop header).\n"
+      "%*s    For exact line attribution, prefer precise events\n"
+      "%*s    (see the \"Precise events\" section of `gprofng collect app -h`).\n"),
+      space, "", space, "", space, "", space, "", space, "");
   return name_offset;
 }
 
-- 
2.54.0


From claziss@gmail.com  Fri Jun 26 11:33:22 2026
From: claziss@gmail.com (Claudiu Zissulescu)
Date: Fri, 26 Jun 2026 14:33:22 +0300
Subject: [PATCH 4/4] gprofng: document HW-counter interface
In-Reply-To: <20260626113840.44715-1-claziss@gmail.com>
References: <20260626113840.44715-1-claziss@gmail.com>
Message-ID: <20260626113840.44715-5-claziss@gmail.com>

The existing "Inclusive and Exclusive Metrics" section explains the
distinction at the function level but does not state that the same
reasoning applies in source/disassembly views, where a line without a
call necessarily has Excl == Incl.  The "Hardware Event Counters
Explained" appendix lists the limitations of HW counters but does not
mention sample skid nor the distinction between precise (PEBS/IBS)
and standard events.

gprofng/
	* doc/gprofng_ug.texi (Inclusive and Exclusive Metrics):
	Note that lines without function calls have identical
	inclusive and exclusive values in source/disassembly views.
	(Hardware Event Counters Explained): Add an note describing the
	precise/standard-event distinction.
	(Getting Information on the Counters Supported): Describe the
	Precise events/Standard events grouping.
---
 gprofng/doc/gprofng_ug.texi | 52 +++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/gprofng/doc/gprofng_ug.texi b/gprofng/doc/gprofng_ug.texi
index 97abcaec44d..88d83e77f9b 100644
--- a/gprofng/doc/gprofng_ug.texi
+++ b/gprofng/doc/gprofng_ug.texi
@@ -2595,6 +2595,27 @@ Raw HW counters:
 As can be seen, these names are not always easy to correlate to a specific
 event of interest.  The processor manual should provide more clarity on this.
 
+@cindex Precise event
+The alias listing and the raw-counter listing are each split into two
+subsections labeled ``Precise events'' and ``Standard events''.  Precise
+events (PEBS on Intel, IBS on AMD) tag the sample with the program counter
+of the retiring instruction, and should be preferred for source-line and
+instruction-level analysis.  Standard events are subject to skid: the
+reported program counter may be several instructions past the one that
+caused the event, which most commonly shows up as counts attributed to the
+control statement of a hot loop rather than to the instruction in the loop
+body that actually missed.  @xref{Hardware Event Counters Explained} for
+more on skid and the precise/standard distinction.  In the column labeled
+@code{type}, precise events are tagged @code{memoryspace (precise)}, while
+standard events show types such as @code{load}, @code{store}, or are left
+blank when no backtracking is supported.
+
+When the marker @code{(*)} appears in a column header of a
+@code{gprofng display text} report, it indicates that the counter feeding
+that column is a standard (non-precise) event and that source-line
+attribution for that column may skid.  A footnote below the column header
+block describes the marker and points back to this section.
+
 @c -- A new node --------------------------------------------------------------
 @node       Examples Using Hardware Event Counters
 @subsection Examples Using Hardware Event Counters
@@ -3940,6 +3961,13 @@ In case of a @emph{leaf function}, the inclusive and exclusive values for the
 metric are the same since by definition, it is not calling any other
 function(s).
 
+The same reasoning applies in the @emph{source} and @emph{disassembly} views,
+which attribute metrics to individual lines or instructions.  A line that
+contains no function call has no callees, so its inclusive and exclusive
+values are identical.  This is expected and not a defect of the report; the
+two columns only diverge for lines (such as a function-call statement) whose
+inclusive value rolls up the cost incurred inside the callee.
+
 Why do we use these two different values? The inclusive metric shows the most
 expensive path, in terms of this metric, in the application.  For example, if
 the metric is cache misses, the function with the highest inclusive metric
@@ -4273,6 +4301,30 @@ to cover all the events of interest.
 The names of the events may also not be easy to interpret.  In such cases,
 the description can be found in the architecture manual for the processor.
 
+@cindex Skid
+@cindex Precise event
+@item
+For most hardware events, the program counter (PC) sampled when the counter
+overflows is not the PC of the instruction that actually caused the event.
+The interrupt is delivered several instructions later, after the relevant
+instruction has already retired.  This delay is called @emph{skid} and
+typically pushes the sampled PC forward, often onto the next basic block.
+In a hot loop, for example, cache misses originating in the loop body may
+be reported against the loop's control statement (the @code{for} or
+@code{while} line at the top of the loop).  When the report shows
+unexpectedly high counts on a line that does little observable work, skid
+is the most likely explanation; consulting the @emph{disassembly} view
+will show on which individual instruction the samples actually landed.
+
+Some processors provide a second class of events, called @emph{precise}
+events, that do not skid.  On Intel processors this mechanism is called
+@emph{PEBS}, and on AMD processors it is called @emph{IBS}.  When precise
+events are available for the metric of interest, they should be preferred
+for source-line and instruction-level analysis.  @ToolName{} lists precise
+events in a dedicated subsection of the output of
+@code{gprofng collect app -h}, separately from the skid-prone standard
+events; @xref{Getting Information on the Counters Supported}.
+
 @end itemize
 
 Despite these drawbacks, hardware event counters are extremely useful and
-- 
2.54.0


From claziss@gmail.com  Fri Jun 26 11:33:21 2026
From: claziss@gmail.com (Claudiu Zissulescu)
Date: Fri, 26 Jun 2026 14:33:21 +0300
Subject: [PATCH 3/4] gprofng: testsuite coverage for HW-counter precision
 markings
In-Reply-To: <20260626113840.44715-1-claziss@gmail.com>
References: <20260626113840.44715-1-claziss@gmail.com>
Message-ID: <20260626113840.44715-4-claziss@gmail.com>

Add two DejaGnu tests that pin the user-facing output added by the
previous two commits.

hwc_listing.exp verifies that "gprofng collect app -h" groups counters
into "Precise events" and "Standard events" sections, and that precise
counters carry the "memoryspace (precise)" type tag.

hwc_precision_marker.exp records an HW-counter experiment with the
default counter set, runs "display text", and asserts that the column
header marker "(*)" and the explanatory footnote. A marker without a
footnote, or vice versa, is a regression.

gprofng/
	* testsuite/gprofng.display/hwc_listing.exp: New test.
	* testsuite/gprofng.display/hwc_precision_marker.exp: New test.
---
 .../testsuite/gprofng.display/hwc_listing.exp | 60 ++++++++++++++++
 .../gprofng.display/hwc_precision_marker.exp  | 72 +++++++++++++++++++
 2 files changed, 132 insertions(+)
 create mode 100644 gprofng/testsuite/gprofng.display/hwc_listing.exp
 create mode 100644 gprofng/testsuite/gprofng.display/hwc_precision_marker.exp

diff --git a/gprofng/testsuite/gprofng.display/hwc_listing.exp b/gprofng/testsuite/gprofng.display/hwc_listing.exp
new file mode 100644
index 00000000000..c70b7ea8695
--- /dev/null
+++ b/gprofng/testsuite/gprofng.display/hwc_listing.exp
@@ -0,0 +1,60 @@
+# Copyright (C) 2026 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+# Verify that "gprofng collect app -h" groups the available HW counters
+# into a "Precise events" section and a "Standard events" section, and
+# tags precise counters as "memoryspace (precise)" in the type column.
+# This pins the user-facing output added to gprofng/common/hwctable.c
+# so a future refactor cannot silently drop the section split.
+
+set gprofng $::env(GPROFNG)
+set testname "hwc_listing"
+
+set output [run_native_host_cmd "$gprofng collect app -h"]
+set out [lindex $output 1]
+
+if { [string first "not supported on this system" $out] >= 0 } then {
+    unsupported $testname
+    return
+}
+
+# Standard events block is always emitted when any counter is listed.
+if { [string first "Standard events" $out] < 0 } then {
+    send_log "missing 'Standard events' section in -h output:\n$out\n"
+    fail $testname
+    return
+}
+
+# If any precise counters are present (type column shows "memoryspace"),
+# the "(precise)" tag and the "Precise events" heading must both appear.
+if { [string first "memoryspace" $out] >= 0 } then {
+    if { [string first "memoryspace (precise)" $out] < 0 } then {
+	send_log "'memoryspace' type without '(precise)' tag:\n$out\n"
+	fail $testname
+	return
+    }
+    if { [string first "Precise events" $out] < 0 } then {
+	send_log "missing 'Precise events' heading despite memoryspace counters:\n$out\n"
+	fail $testname
+	return
+    }
+}
+
+pass $testname
diff --git a/gprofng/testsuite/gprofng.display/hwc_precision_marker.exp b/gprofng/testsuite/gprofng.display/hwc_precision_marker.exp
new file mode 100644
index 00000000000..0d38b7b3f83
--- /dev/null
+++ b/gprofng/testsuite/gprofng.display/hwc_precision_marker.exp
@@ -0,0 +1,72 @@
+# Copyright (C) 2026 Free Software Foundation, Inc.
+#
+# This file is part of the GNU Binutils.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+# MA 02110-1301, USA.
+#
+
+# Verify that "display text" on an HW-counter experiment marks
+# non-precise counter columns with " (*)" and emits the explanatory
+# footnote.  This pins the behavior introduced in gprofng/src/Metric.cc
+# and gprofng/src/Print.cc that addresses the most common user
+# confusion (cache misses attributed to a loop-header line because of
+# PMU skid).
+
+global srcdir CC CLOCK_GETTIME_LINK
+set gprofng $::env(GPROFNG)
+set testname "hwc_precision_marker"
+set tdir "tmpdir/hwc_precision_marker"
+
+run_native_host_cmd "mkdir -p $tdir"
+
+# Build and try to record with the default HW counter set.  If the
+# host has no PMU access the collect step will fail with a message
+# containing "not supported"; treat that as unsupported, not a fail.
+set output [run_native_host_cmd "cd $tdir && \
+  cp $srcdir/lib/smalltest.c t.c && \
+  $CC -g t.c $CLOCK_GETTIME_LINK && \
+  $gprofng collect app -p off -h on -a off -O exp.er ./a.out"]
+set status [lindex $output 0]
+set out [lindex $output 1]
+if { $status != 0 } then {
+    if { [string first "not supported" $out] >= 0 \
+	 || [string first "HW counter" $out] >= 0 \
+	 || [string first "perf_event" $out] >= 0 } then {
+	unsupported $testname
+	return
+    }
+    send_log "collect with -h on failed unexpectedly:\n$out\n"
+    fail $testname
+    return
+}
+
+set output [run_native_host_cmd "$gprofng display text -functions $tdir/exp.er"]
+set out [lindex $output 1]
+
+set have_mark	  [expr {[string first "(*)" $out] >= 0}]
+set have_footnote [expr {[string first "Non-precise HW event:" $out] >= 0}]
+
+# The marker and the footnote must be consistent.  Both present means a
+# non-precise counter was selected and explained; both absent means the
+# default set was entirely precise (rare but valid).  One without the
+# other is a regression.
+if { $have_mark != $have_footnote } then {
+    send_log "marker/footnote inconsistency (mark=$have_mark footnote=$have_footnote):\n$out\n"
+    fail $testname
+    return
+}
+
+pass $testname
-- 
2.54.0


From jbeulich@suse.com  Fri Jun 26 11:55:21 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Fri, 26 Jun 2026 13:55:21 +0200
Subject: [PATCH v3] RISC-V: Fix build with GCC-8
In-Reply-To: <alpine.DEB.2.21.2606261151490.58268@angie.orcam.me.uk>
References: <f2abf263-4730-4ccd-af87-e3de2289b35c@suse.com>
 <20260623133508.2896582-1-zhuangqiubin@linux.spacemit.com>
 <alpine.DEB.2.21.2606252232520.58268@angie.orcam.me.uk>
 <7f84f26f-9f88-4690-8f61-e7e893831f65@suse.com>
 <alpine.DEB.2.21.2606261151490.58268@angie.orcam.me.uk>
Message-ID: <dc6104a6-70d6-443a-9605-993bfb1c7851@suse.com>

On 26.06.2026 13:02, Maciej W. Rozycki wrote:
> On Fri, 26 Jun 2026, Jan Beulich wrote:
> 
>>>  I think it would be more useful to the reader if the commit referred to 
>>> the relevant C language standard and minimum compiler version as given by 
>>> Andreas: <https://inbox.sourceware.org/binutils/mvmtsqtzgve.fsf@suse.de/>.
>>
>> To be honest, I think relatively basic standard C aspects should be known
>> to people, and "rejects a declaration right after a case label" is enough
>> of a pointer imo.
> 
>  I don't expect everyone to track or remember all the individual features 
> as they are added to standard revisions or compiler implementations, and 
> details provided by Andreas are useful in determining the prerequsites.
> 
>  Indeed the breakage caused in the first place serves as a proof: you'd 
> imply the code writer as well the approver should have known this feature 
> isn't there in every compiler version supported for building binutils, and 
> yet they missed it.
> 
>  Why do you think it would be preferable to require everyone to chase 
> every time something that has been already determined?

Something needs saying, sure, but what you left me unclear with is why what
is being said in the description is insufficient.

>>>  FWIW it broke the build with GCC 10.2.1 here (production box, system
>>> compiler).
>>
>> At the risk of coming across blunt, but: You complain about too little
>> detail above, and then you report this issue without providing any detail?
> 
>  Why would I need to repeat the same exact details as with the original 
> report?  This is just to confirm that the same issue triggers for versions 
> other than 8.5.0 (just as Andreas has indicated).  I reckon Andrew Burgess 
> also reported breakage with his environment.

IOW "it" in your earlier reply referred to the original patch, not this fix?
In that case the fix could go in, but please confirm, as I fear I'm now
sufficiently confused.

Jan

From evgeny.karpov@arm.com  Fri Jun 26 13:30:12 2026
From: evgeny.karpov@arm.com (Evgeny Karpov)
Date: Fri, 26 Jun 2026 15:30:12 +0200
Subject: [PATCH v10 0/1] Implement Structured Exception Handling (SEH) on
 AArch64
Message-ID: <20260626133013.89140-1-evgeny.karpov@arm.com>

Hello,

Thank you for reviewing v9!
v10 adds an extra description for limitations and refactors the code to improve
readability. 

Changes in v10:
- Fix the indentations.
- Extend the description with limitations for the current implementation.
- Reorder aarch64_unwind_info.
- Use reg_pair to validate the correct register range.
- Rename offset_shift/reg_shift to offset_multiplier/reg_multiplier.
- Move some code to seh_aarch64_emit_xdata_record.
- Fix a typo for .seh_set_fp in the test's comment.
- Update the error message for offset.

Changes in v9 2026-06-17:
- Align backslashes only with tabs.
- Replace links with text that can help find proper resources.
- Replace binary literals with hex.
- Correct whitespace.
https://sourceware.org/pipermail/binutils/2026-June/149662.html

Changes in v8 2026-06-15:
- Refactor and simplify some conditions.
- Move .xdata record writing to a separate
  function (seh_aarch64_emit_xdata_record).
- Add documentation link to obj-coff-seh-aarch64.h.
- Add a minor change to the patch description.
- Use only prologue/epilogue.
- Add SEH tests.
- Use unsigned char instead of unsigned for aarch64_unwind_info.
- Rename offset/reg_offset to offset_addend/reg_addend.
- Remove shift direction from the names.
- Correct typos and comments locations.
- Add more comments and extend some of them.
- Reorder aarch64_unwind_code_data declarations.
- Remove AARCH64_UNOP_* and use code inside the declaration.
- Remove members that are NULL or 0.
- Rename unwind_code_pack_info to info.
- Rename aarch64_element to element and move 4 lines to the end of the function.
- Add validations for offset and reg.
- Drop the condition for code_bits.
- Inline some constants to the conditions.
- Check the register name for SEH directives.
- Modify style by changing line wrapping.
- Optimize some calculations.
- Remove some comments to avoid confusion.
- Add clarification for missing implementation.
- Move seh_aarch64_write_data under OBJ_COFF scope.
- Support .seh_code to simplify porting from x86_64.
https://sourceware.org/pipermail/binutils/2026-June/149639.html

Changes in v7 2026-03-19:
- Rename sort_x64_pdata to sort_pdata.
- Move obj_coff_seh_do_final implementation to a separate function.
- Merge patch 3/4 with 4/4.
https://sourceware.org/pipermail/binutils/2026-March/148657.html

Changes in v6 2026-03-11:
- Revert changes in frag_offset_ignore_align_p.
- Relax the code segment to be able to calculate the function sizes.
- Add seh_function_size that implements the calculation of the function size
  and replace frag_offset_ignore_align_p call with this implementation.
https://sourceware.org/pipermail/binutils/2026-March/148488.html

Changes in v5 2026-02-24:
- In many places int, uint32_t and int32_t have been replaced to unsigned.
- Refactor and move SEH aarch64 implementation to separate files.
- Replace uintptr_t with bfd_vma.
- Update comments.
- Add dedicated initializers.
- Move some variables inside loops.
- Fix the definition for packing some unwinding codes.
- Add description to seh commands.
- Rename prolog_instruction_count to prolog_insn_count.
- Relocate variable initilization closer to place of use.
- Add unwind_ prefix to unwind type enumerator.
https://sourceware.org/pipermail/binutils/2026-February/148332.html

Changes in v3(v4) 2025-08-14:
- Make the AArch64 implementation fully static.
- Fix ARM64_MAX_UNWIND_CODES and introduce AARCH64_MAX_UNWIND_CODES_SIZE.
- Add validation for the epilogue_scope array.
- Add an upper bound for the register number.
- Exclude changes in md_do_align.
- Refactor the AArch64 SEH implementation to emit .pdata/.xdata records at
  the end of assembly.
- Declare md_finish for AArch64 to trigger obj_coff_generate_pdata.
- Support different fragment ordering in frag_offset_ignore_align_p
- Change signed to unsigned.
- Replace Arm64 / arm64 with AArch64 / aarch64.
- Add references to the official documentation to clarify
  implementation.
- Add static and aarch64_ prefix.
- Rebase onto the current master.
- Fix comments.
- Correct code style and naming.
https://sourceware.org/pipermail/binutils/2025-August/143401.html

Changes in v2 2025-05-09:
- Add guards for different architectures
- Fix code style issues and typos
- Move Arm64-specific code to pdata/xdata functions
- Prefer unsigned int over uint32_t in some places
- Revert memory release to the original implementation
- Refactor long function fragmentation
- Fix the function size calculation issue related to code alignment
https://sourceware.org/pipermail/binutils/2025-May/140961.html

v1 2025-04-09:
This patch series supports the GCC patch series that implements SEH
support for the aarch64-w64-mingw32 target.
https://gcc.gnu.org/pipermail/gcc-patches/2024-November/669003.html
The patch series has been tested by applying internal tests and passing
all Boost library tests that involve exception handling.
https://sourceware.org/pipermail/binutils/2025-April/140495.html

Regards,
Evgeny

Evgeny Karpov (1):
  aarch64: Implement Structured Exception Handling (SEH) on AArch64

 gas/config/obj-coff-seh-aarch64.c             | 967 ++++++++++++++++++
 gas/config/obj-coff-seh-aarch64.h             | 254 +++++
 gas/config/obj-coff-seh-shared.c              |   8 +-
 gas/config/obj-coff.c                         |   4 +
 gas/config/tc-aarch64.c                       |  10 +
 gas/config/tc-aarch64.h                       |   6 +
 gas/testsuite/gas/pe/pe.exp                   |   3 +
 gas/testsuite/gas/pe/seh-aarch64-error.l      | 110 ++
 gas/testsuite/gas/pe/seh-aarch64-error.s      | 128 +++
 gas/testsuite/gas/pe/seh-aarch64-large-func.d |  53 +
 gas/testsuite/gas/pe/seh-aarch64-large-func.s |  13 +
 gas/testsuite/gas/pe/seh-aarch64.d            |  66 ++
 gas/testsuite/gas/pe/seh-aarch64.s            |  49 +
 gas/write.c                                   |   2 +-
 gas/write.h                                   |   1 +
 15 files changed, 1672 insertions(+), 2 deletions(-)
 create mode 100644 gas/config/obj-coff-seh-aarch64.c
 create mode 100644 gas/config/obj-coff-seh-aarch64.h
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64-error.l
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64-error.s
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64-large-func.d
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64-large-func.s
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64.d
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64.s


From evgeny.karpov@arm.com  Fri Jun 26 13:30:13 2026
From: evgeny.karpov@arm.com (Evgeny Karpov)
Date: Fri, 26 Jun 2026 15:30:13 +0200
Subject: [PATCH v10 1/1] aarch64: Implement Structured Exception Handling
 (SEH) on AArch64
In-Reply-To: <20260626133013.89140-1-evgeny.karpov@arm.com>
References: <20260626133013.89140-1-evgeny.karpov@arm.com>
Message-ID: <20260626133013.89140-2-evgeny.karpov@arm.com>

The patch reuses shared helpers for SEH and implements SEH on AArch64.
The implementation is based on
(https://learn.microsoft.com/en-us/cpp/build/arm64-exception-handling?view=msvc-170)
and pdata/xdata SEH records are emitted from md_finish.

When .pdata/.xdata is emitted, the function size is required.
Function sizes are calculated as late as possible, and the code segment needs
to be relaxed to be able to calculate the function sizes.

Initially, obj_coff_generate_pdata was called in write_object_file.
Before the change, obj_coff_generate_pdata was used only to validate
syntax, which was sufficient for that purpose. However, that location
seems incorrect, as it is too late to emit .pdata/.xdata records
in the AArch64 case.

md_finish has been declared for AArch64 and extended with
seh_aarch64_write_data to emit .pdata/.xdata records after all
assembly has been completed.

Signed-off-by: Evgeny Karpov <evgeny@kmaps.co>

gas/ChangeLog:
	* gas/config/obj-coff-seh-shared.c (defined): Update.
	(struct seh_seg_list): Use seh_context_t.
	* gas/config/obj-coff.c (defined): Update.
	* gas/config/tc-aarch64.c (defined): Add OBJ_COFF guard.
	(aarch64_md_finish): Add.
	* gas/config/tc-aarch64.h (defined): Add OBJ_COFF guard.
	(md_finish): Add.
	(aarch64_md_finish): Add.
	(seh_aarch64_write_data): Add.
	* testsuite/gas/pe/pe.exp: Add SEH tests.
	* write.c: Update.
	* write.h (subsegs_finish_section): Update.
	* config/obj-coff-seh-aarch64.c: New file.
	* config/obj-coff-seh-aarch64.h: New file.
	* testsuite/gas/pe/seh-aarch64-error.l: New test.
	* testsuite/gas/pe/seh-aarch64-error.s: New test.
	* testsuite/gas/pe/seh-aarch64-large-func.d: New test.
	* testsuite/gas/pe/seh-aarch64-large-func.s: New test.
	* testsuite/gas/pe/seh-aarch64.d: New test.
	* testsuite/gas/pe/seh-aarch64.s: New test.
---
 gas/config/obj-coff-seh-aarch64.c             | 967 ++++++++++++++++++
 gas/config/obj-coff-seh-aarch64.h             | 254 +++++
 gas/config/obj-coff-seh-shared.c              |   8 +-
 gas/config/obj-coff.c                         |   4 +
 gas/config/tc-aarch64.c                       |  10 +
 gas/config/tc-aarch64.h                       |   6 +
 gas/testsuite/gas/pe/pe.exp                   |   3 +
 gas/testsuite/gas/pe/seh-aarch64-error.l      | 110 ++
 gas/testsuite/gas/pe/seh-aarch64-error.s      | 128 +++
 gas/testsuite/gas/pe/seh-aarch64-large-func.d |  53 +
 gas/testsuite/gas/pe/seh-aarch64-large-func.s |  13 +
 gas/testsuite/gas/pe/seh-aarch64.d            |  66 ++
 gas/testsuite/gas/pe/seh-aarch64.s            |  49 +
 gas/write.c                                   |   2 +-
 gas/write.h                                   |   1 +
 15 files changed, 1672 insertions(+), 2 deletions(-)
 create mode 100644 gas/config/obj-coff-seh-aarch64.c
 create mode 100644 gas/config/obj-coff-seh-aarch64.h
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64-error.l
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64-error.s
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64-large-func.d
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64-large-func.s
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64.d
 create mode 100644 gas/testsuite/gas/pe/seh-aarch64.s

diff --git a/gas/config/obj-coff-seh-aarch64.c b/gas/config/obj-coff-seh-aarch64.c
new file mode 100644
index 00000000000..3b551d07673
--- /dev/null
+++ b/gas/config/obj-coff-seh-aarch64.c
@@ -0,0 +1,967 @@
+/* SEH .pdata/.xdata COFF object file format on AArch64
+   Copyright (C) 2026 Free Software Foundation, Inc.
+
+   This file is part of GAS.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+#include "obj-coff-seh-aarch64.h"
+
+static struct seh_aarch64_context *seh_ctx_root = NULL;
+static bool in_seh_proc = false;
+
+struct aarch64_unwind_info {
+  const char *directive;
+  unsigned char size;
+  unsigned char code_bits;
+  unsigned char code;
+  unsigned char offset_bits;
+  unsigned char offset_multiplier;
+  unsigned char offset_addend;
+  unsigned char reg_bits;
+  unsigned char reg_multiplier;
+  unsigned char reg_addend;
+  char reg_type;
+  bool reg_pair;
+};
+
+/* Unwind codes for AArch64 are described based on
+   "Microsoft ARM64 exception handling, unwind codes documentation"
+   and calculated in seh_aarch64_add_unwind_element function.
+   aarch64_unwind_code_data is indexed by the seh_aarch64_unwind_types enum.  */
+
+static const struct aarch64_unwind_info
+aarch64_unwind_code_data[] = {
+  {
+    .size = 1,
+    .code_bits = 3, .code = 0x0,
+    .offset_bits = 5, .offset_multiplier = 4
+  },
+  {
+    .size = 2,
+    .code_bits = 5, .code = 0x18,
+    .offset_bits = 11, .offset_multiplier = 4
+  },
+  {
+    .size = 4,
+    .code_bits = 8, .code = 0xe0,
+    .offset_bits = 24, .offset_multiplier = 4
+  },
+  {
+    .directive = ".seh_save_reg",
+    .size = 2,
+    .code_bits = 6, .code = 0x34,
+    .offset_bits = 6, .offset_multiplier = 3,
+    .reg_bits = 4, .reg_addend = 19, .reg_type = 'x'
+  },
+  {
+    .directive = ".seh_save_reg_x",
+    .size = 2,
+    .code_bits = 7, .code = 0x6a,
+    .offset_bits = 5, .offset_multiplier = 3, .offset_addend = 1,
+    .reg_bits = 4, .reg_addend = 19, .reg_type = 'x'
+  },
+  {
+    .directive = ".seh_save_regp",
+    .size = 2,
+    .code_bits = 6, .code = 0x32,
+    .offset_bits = 6, .offset_multiplier = 3,
+    .reg_bits = 4, .reg_addend = 19, .reg_type = 'x', .reg_pair = true
+  },
+  {
+    .directive = ".seh_save_regp_x",
+    .size = 2,
+    .code_bits = 6, .code = 0x33,
+    .offset_bits = 6, .offset_multiplier = 3, .offset_addend = 1,
+    .reg_bits = 4, .reg_addend = 19, .reg_type = 'x', .reg_pair = true
+  },
+  {
+    .directive = ".seh_save_fregp",
+    .size = 2,
+    .code_bits = 7, .code = 0x6c,
+    .offset_bits = 6, .offset_multiplier = 3,
+    .reg_bits = 3, .reg_addend = 8, .reg_type = 'd'
+  },
+  {
+    .directive = ".seh_save_fregp_x",
+    .size = 2,
+    .code_bits = 7, .code = 0x6d,
+    .offset_bits = 6, .offset_multiplier = 3, .offset_addend = 1,
+    .reg_bits = 3, .reg_addend = 8, .reg_type = 'd'
+  },
+  {
+    .directive = ".seh_save_freg",
+    .size = 2,
+    .code_bits = 7, .code = 0x6e,
+    .offset_bits = 6, .offset_multiplier = 3,
+    .reg_bits = 3, .reg_addend = 8, .reg_type = 'd'
+  },
+  {
+    .directive = ".seh_save_freg_x",
+    .size = 2,
+    .code_bits = 8, .code = 0xde,
+    .offset_bits = 5, .offset_multiplier = 3, .offset_addend = 1,
+    .reg_bits = 3, .reg_addend = 8, .reg_type = 'd'
+  },
+  {
+    .directive = ".seh_save_lrpair",
+    .size = 2,
+    .code_bits = 7, .code = 0x6b,
+    .offset_bits = 6, .offset_multiplier = 3,
+    .reg_bits = 3, .reg_multiplier = 1, .reg_addend = 19, .reg_type = 'x'
+  },
+  {
+    .directive = ".seh_save_fplr",
+    .size = 1,
+    .code_bits = 2, .code = 0x1,
+    .offset_bits = 6, .offset_multiplier = 3
+  },
+  {
+    .directive = ".seh_save_fplr_x",
+    .size = 1,
+    .code_bits = 2, .code = 0x2,
+    .offset_bits = 6, .offset_multiplier = 3, .offset_addend = 1
+  },
+  {
+    .directive = ".seh_save_r19r20_x",
+    .size = 1,
+    .code_bits = 3, .code = 0x1,
+    .offset_bits = 5, .offset_multiplier = 3
+  },
+  {
+    .directive = ".seh_add_fp",
+    .size = 2,
+    .code_bits = 8, .code = 0xe2,
+    .offset_bits = 8, .offset_multiplier = 3
+  },
+  {
+    .directive = ".seh_set_fp",
+    .size = 1,
+    .code_bits = 8, .code = 0xe1
+  },
+  {
+    .directive = ".seh_save_next",
+    .size = 1,
+    .code_bits = 8, .code = 0xe6
+  },
+  {
+    .directive = ".seh_nop",
+    .size = 1,
+    .code_bits = 8, .code = 0xe3
+  },
+  {
+    .directive = ".seh_pac_sign_lr",
+    .size = 1,
+    .code_bits = 8, .code = 0xfc
+  },
+  {
+    .size = 1,
+    .code_bits = 8, .code = 0xe4
+  },
+};
+
+/* Set for current context the default handler.  */
+static void
+obj_coff_seh_handler (const int what ATTRIBUTE_UNUSED)
+{
+  char *symbol_name;
+  char name_end;
+
+  if (!verify_context (".seh_handler"))
+    return;
+
+  if (*input_line_pointer == 0 || *input_line_pointer == '\n')
+    as_bad (_(".seh_handler requires a handler"));
+
+  SKIP_WHITESPACE ();
+
+  if (*input_line_pointer == '@')
+    {
+      name_end = get_symbol_name (&symbol_name);
+
+      seh_ctx_cur->handler.X_op = O_constant;
+      seh_ctx_cur->handler.X_add_number = 0;
+
+      if (strcasecmp (symbol_name, "@1") == 0)
+	seh_ctx_cur->handler.X_add_number = 1;
+      else if (strcasecmp (symbol_name, "@0")
+	       && strcasecmp (symbol_name, "@null"))
+	as_bad (_("unknown constant value '%s' for handler"), symbol_name);
+
+      (void) restore_line_pointer (name_end);
+    }
+  else
+    expression (&seh_ctx_cur->handler);
+
+  seh_ctx_cur->handler_data.X_op = O_constant;
+  seh_ctx_cur->handler_data.X_add_number = 0;
+  seh_ctx_cur->xdata_header.x = 1;
+
+  while (skip_whitespace_and_comma (0))
+    {
+      name_end = get_symbol_name (&symbol_name);
+      (void) restore_line_pointer (name_end);
+    }
+}
+
+/* Switch to subsection for handler data for exception region.  */
+static void
+obj_coff_seh_handlerdata (const int what ATTRIBUTE_UNUSED)
+{
+  demand_empty_rest_of_line ();
+
+  switch_xdata (seh_ctx_cur->subsection + 1, seh_ctx_cur->code_seg);
+  seh_ctx_cur->handler_data_xdata_addr = symbol_temp_new_now ();
+}
+
+/* Switch back to the code section.  */
+static void
+obj_coff_seh_code (int ignored ATTRIBUTE_UNUSED)
+{
+  subseg_set (seh_ctx_cur->code_seg, 0);
+}
+
+/* Obtain available unwind element.  */
+static void
+seh_aarch64_add_unwind_element (const seh_aarch64_unwind_types unwind_type,
+				unsigned offset, unsigned reg)
+{
+  const struct aarch64_unwind_info *info
+    = aarch64_unwind_code_data + unwind_type;
+  unsigned value_offset_bits = 0;
+
+  if ((seh_ctx_cur->unwind_codes_byte_count
+      + info->size) > AARCH64_MAX_UNWIND_CODES_SIZE)
+    as_bad (_("no unwind element available."));
+
+  unsigned value = 0;
+
+  if (info->offset_bits)
+    {
+      const unsigned multiplier = 1u << info->offset_multiplier;
+      if (offset & (multiplier - 1))
+	as_bad (_("offset should be a multiple of %u"), multiplier);
+      offset = (offset >> info->offset_multiplier) - info->offset_addend;
+      if (offset >= (1u << info->offset_bits))
+	as_bad (_("offset overflows expected range"));
+      value |= offset << value_offset_bits;
+      value_offset_bits += info->offset_bits;
+    }
+
+  if (info->reg_bits)
+    {
+      const unsigned regn_divided_by = 1u << info->reg_multiplier;
+      reg -= info->reg_addend;
+      if (reg & (regn_divided_by - 1))
+	as_bad (_("unexpected register number"));
+      reg >>= info->reg_multiplier;
+      if (reg >= (1u << info->reg_bits))
+	as_bad (_("unexpected register number"));
+      value |= reg << value_offset_bits;
+      value_offset_bits += info->reg_bits;
+    }
+
+  const unsigned code = info->code;
+  gas_assert (code < (1u << info->code_bits));
+  value |= code << value_offset_bits;
+
+  seh_aarch64_unwind_code *element;
+  element = seh_ctx_cur->unwind_codes + seh_ctx_cur->unwind_codes_count++;
+  element->type = unwind_type;
+  element->value = value;
+
+  seh_ctx_cur->unwind_codes_byte_count += info->size;
+}
+
+/* Mark begin of new context.  */
+static void
+obj_coff_seh_proc (const int what ATTRIBUTE_UNUSED)
+{
+  char *symbol_name;
+  char name_end;
+
+  if (in_seh_proc)
+    as_bad (_("previous SEH entry not closed (missing .seh_endproc)"));
+
+  if (*input_line_pointer == 0 || *input_line_pointer == '\n')
+    as_bad (_(".seh_proc requires function label name"));
+
+
+  if (!seh_ctx_root)
+    {
+      seh_ctx_root = XCNEW (seh_context);
+      seh_ctx_cur = seh_ctx_root;
+    }
+  else
+    {
+      seh_ctx_cur->next = XCNEW (seh_context);
+      seh_ctx_cur = seh_ctx_cur->next;
+    }
+
+  seh_ctx_cur->next = NULL;
+  seh_ctx_cur->code_seg = now_seg;
+
+  /* The current implementation always use a pair of .pdata and .xdata
+     records.  */
+  const bool use_xdata = true;
+
+  if (use_xdata)
+    {
+      x_segcur = seh_hash_find_or_make (seh_ctx_cur->code_seg, ".xdata");
+      seh_ctx_cur->subsection = x_segcur->subseg;
+      x_segcur->subseg += 2;
+
+      /* Initialize an empty .xdata record.  */
+      seh_ctx_cur->unwind_codes_count = 0;
+      seh_ctx_cur->unwind_codes_byte_count = 0;
+      seh_ctx_cur->epilogue_scopes_count = 0;
+      seh_ctx_cur->epilogue_scopes_capacity = 0;
+      seh_ctx_cur->epilogue_scopes = NULL;
+      seh_ctx_cur->xdata_header.x = 0;
+    }
+
+  SKIP_WHITESPACE ();
+
+  name_end = get_symbol_name (&symbol_name);
+  seh_ctx_cur->func_name = xstrdup (symbol_name);
+  (void) restore_line_pointer (name_end);
+
+  demand_empty_rest_of_line ();
+
+  seh_ctx_cur->start_addr = symbol_temp_new_now ();
+  in_seh_proc = true;
+}
+
+/* Mark end of prologue for current context.  */
+static void
+obj_coff_seh_endprologue (const int what ATTRIBUTE_UNUSED)
+{
+  if (!verify_context (".seh_endprologue")
+      || !seh_validate_seg (".seh_endprologue"))
+    return;
+  demand_empty_rest_of_line ();
+
+  if (seh_ctx_cur->endprologue_addr != NULL)
+    as_warn (_("duplicate .seh_endprologue in .seh_proc block"));
+  else
+    seh_ctx_cur->endprologue_addr = symbol_temp_new_now ();
+
+  /* Unwind codes need to be reversed.  */
+  for (unsigned i = 0, n = seh_ctx_cur->unwind_codes_count; i < n / 2; ++i)
+    {
+      seh_aarch64_unwind_code *unwind_codes = seh_ctx_cur->unwind_codes;
+      const seh_aarch64_unwind_code temp = unwind_codes[i];
+      unwind_codes[i] = unwind_codes[n-i-1];
+      unwind_codes[n-i-1] = temp;
+    }
+
+   seh_aarch64_add_unwind_element (unwind_end, 0, 0);
+}
+
+/* Mark end of current context.  */
+static void
+obj_coff_seh_endproc (const int what ATTRIBUTE_UNUSED)
+{
+  demand_empty_rest_of_line ();
+  if (!in_seh_proc)
+    {
+      as_bad (_(".seh_endproc used without .seh_proc"));
+      return;
+    }
+
+  seh_validate_seg (".seh_endproc");
+
+  seh_ctx_cur->end_addr = symbol_temp_new_now ();
+  in_seh_proc = false;
+}
+
+static void
+obj_coff_seh_startepilogue (const int what ATTRIBUTE_UNUSED)
+{
+  if (!verify_context (".seh_startepilogue")
+      || !seh_validate_seg (".seh_startepilogue"))
+    return;
+  demand_empty_rest_of_line ();
+
+  if (seh_ctx_cur->epilogue_scopes_count >= AARCH64_MAX_EPILOGUE_SCOPES)
+    as_bad (_("no epilogue scopes available."));
+
+  symbolS *epilogue_start_addr = symbol_temp_new_now ();
+  expressionS exp;
+  exp.X_op = O_subtract;
+  exp.X_add_symbol = epilogue_start_addr;
+  exp.X_op_symbol = seh_ctx_cur->start_addr;
+  exp.X_add_number = 0;
+
+  if (!resolve_expression (&exp) || exp.X_op != O_constant
+      || exp.X_add_number < 0)
+    as_bad (_(".seh_startepilogue offset expression for %s "
+	    "does not evaluate to a non-negative constant"),
+	    S_GET_NAME (epilogue_start_addr));
+
+  if (seh_ctx_cur->epilogue_scopes_count
+      >= seh_ctx_cur->epilogue_scopes_capacity)
+    {
+      const unsigned initial_capacity = 32;
+      if (seh_ctx_cur->epilogue_scopes_capacity)
+	seh_ctx_cur->epilogue_scopes_capacity *= 2;
+      else
+	seh_ctx_cur->epilogue_scopes_capacity = initial_capacity;
+
+      seh_ctx_cur->epilogue_scopes
+	= XRESIZEVEC (seh_aarch64_epilogue_scope, seh_ctx_cur->epilogue_scopes,
+		     seh_ctx_cur->epilogue_scopes_capacity);
+    }
+
+  seh_aarch64_epilogue_scope *epilogue_scope = seh_ctx_cur->epilogue_scopes
+    + seh_ctx_cur->epilogue_scopes_count;
+  epilogue_scope->epilogue_start_offset = exp.X_add_number / 4;
+  epilogue_scope->reserved = 0;
+  epilogue_scope->epilogue_start_index = 0;
+  seh_ctx_cur->epilogue_scopes_count++;
+}
+
+static void
+obj_coff_seh_endepilogue (const int what ATTRIBUTE_UNUSED)
+{
+  if (!verify_context (".seh_endepilogue")
+      || !seh_validate_seg (".seh_endepilogue"))
+    return;
+
+  demand_empty_rest_of_line ();
+
+  expressionS exp;
+  symbolS *epilogue_end_addr = symbol_temp_new_now ();
+  exp.X_op = O_subtract;
+  exp.X_add_symbol = epilogue_end_addr;
+  exp.X_op_symbol = seh_ctx_cur->start_addr;
+  exp.X_add_number = 0;
+
+  if (!resolve_expression (&exp) || exp.X_op != O_constant
+      || exp.X_add_number < 0)
+    as_bad (_(".seh_endepilogue offset expression for %s "
+	    "does not evaluate to a non-negative constant"),
+	    S_GET_NAME (epilogue_end_addr));
+
+   seh_aarch64_epilogue_scope *epilogue_scope = seh_ctx_cur->epilogue_scopes
+     + seh_ctx_cur->epilogue_scopes_count - 1;
+
+   epilogue_scope->epilogue_end_offset = exp.X_add_number;
+
+  /* End code.  */
+  seh_aarch64_add_unwind_element (unwind_end, 0, 0);
+}
+
+/* End-of-file hook.  */
+static void
+free_seh_ctx (struct seh_aarch64_context *seh_ctx)
+{
+  free (seh_ctx->func_name);
+  const seh_aarch64_func_fragment *fragment = seh_ctx->func_fragment.next;
+  while (fragment)
+    {
+      const seh_aarch64_func_fragment *next = fragment->next;
+      XDELETE (fragment);
+      fragment = next;
+    }
+  XDELETEVEC (seh_ctx->epilogue_scopes);
+  free (seh_ctx);
+}
+
+static void
+obj_coff_seh_save_reg (const int type)
+{
+  gas_assert (type >= 0 && type <= unwind_last_type);
+
+  const struct aarch64_unwind_info *info
+    = aarch64_unwind_code_data + type;
+
+  SKIP_WHITESPACE ();
+
+  char *symbol_name = NULL;
+  unsigned reg = -1;
+
+  if (info->reg_bits)
+    {
+      char name_end = get_symbol_name (&symbol_name);
+      if (info->reg_type != *symbol_name)
+	as_bad ("unexpected register name");
+
+      reg = atoi (symbol_name + 1);
+      (void) restore_line_pointer (name_end);
+
+      if (!skip_whitespace_and_comma (1))
+	return;
+
+      /* Check that reference registers are not higher than x30.  */
+      if (info->reg_type == 'x' && (reg + (info->reg_pair ? 1 : 0)) > 30)
+	as_bad (_("unexpected register number"));
+    }
+
+  offsetT off = -1;
+  if (info->offset_bits)
+    {
+      off = get_absolute_expression ();
+
+      if (off < 0)
+	as_bad (_("offset is negative"));
+    }
+
+  demand_empty_rest_of_line ();
+
+  if (!in_seh_proc)
+  {
+    as_bad (_("SEH entry has not been found (missing .seh_proc)"));
+    return;
+  }
+
+  if (!info->directive || !seh_validate_seg (info->directive))
+    return;
+
+  seh_aarch64_add_unwind_element (type, off, reg);
+}
+
+/* Add a stack-allocation token to current context.  */
+static void
+obj_coff_seh_stackalloc (const int what ATTRIBUTE_UNUSED)
+{
+  const offsetT off = get_absolute_expression ();
+  demand_empty_rest_of_line ();
+
+  if (!in_seh_proc)
+    {
+      as_bad (_("SEH entry has not been found (missing .seh_proc)"));
+      return;
+    }
+
+  if (off < 0x200)
+    seh_aarch64_add_unwind_element (unwind_alloc_s, off, 0);
+  else if (off < 0x8000)
+    seh_aarch64_add_unwind_element (unwind_alloc_m, off, 0);
+  else if (off < 0x10000000)
+    seh_aarch64_add_unwind_element (unwind_alloc_l, off, 0);
+  else
+    as_bad (_(".seh_stackalloc offset is out of range"));
+}
+
+/* Data writing routines.  */
+static void
+seh_aarch64_emit_epilogue_scopes (const seh_context *seh_ctx,
+				  const uint64_t fragment_offset,
+				  const unsigned prologue_size,
+				  const unsigned first_fragment_scope,
+				  const unsigned last_fragment_scope,
+				  const bool has_phantom_prologue)
+{
+  unsigned start_index_offset = 0;
+  const seh_aarch64_epilogue_scope *scopes = seh_ctx->epilogue_scopes;
+  if (first_fragment_scope < seh_ctx->epilogue_scopes_count)
+    start_index_offset = scopes[first_fragment_scope].epilogue_start_index
+			 - prologue_size;
+  if (has_phantom_prologue)
+    {
+      if (start_index_offset == 0)
+	as_bad (_("start index offset for the epilogue cannot be 0 when "
+		"phantom prologue is used"));
+      --start_index_offset;
+    }
+
+  for (unsigned i = first_fragment_scope; i < last_fragment_scope; ++i)
+    {
+      seh_aarch64_epilogue_scope scope = seh_ctx->epilogue_scopes[i];
+      scope.epilogue_start_offset_reduced = (scope.epilogue_start_offset
+					    - fragment_offset) >> 2;
+      scope.epilogue_start_index -= start_index_offset;
+      uint32_t scope_code;
+      memcpy (&scope_code, &scope, sizeof (scope_code));
+      md_number_to_chars (frag_more (4), scope_code, 4);
+    }
+}
+
+static void
+seh_aarch64_emit_unwind_codes (const seh_context *seh_ctx,
+			       const unsigned prologue_size,
+			       const unsigned first_epilogue_index,
+			       const unsigned last_epilogue_index,
+			       const bool has_phantom_prologue)
+{
+  unsigned total_byte_count = 0;
+
+  if (has_phantom_prologue)
+    {
+      ++total_byte_count;
+      const unsigned endc_code = 0xe5;
+      md_number_to_chars (frag_more (1), endc_code, 1);
+    }
+
+  unsigned unwind_bytes_offset = 0;
+  for (unsigned i = 0; i < seh_ctx->unwind_codes_count; ++i)
+    {
+      const seh_aarch64_unwind_code *code = seh_ctx->unwind_codes + i;
+      const unsigned byte_count
+	= aarch64_unwind_code_data[code->type].size;
+      unwind_bytes_offset += byte_count;
+
+      if (unwind_bytes_offset > last_epilogue_index)
+	break;
+
+      if (unwind_bytes_offset > prologue_size
+	  && unwind_bytes_offset <= first_epilogue_index)
+	continue;
+
+      /*  emit unwind code bytes in big endian.  */
+      number_to_chars_bigendian (frag_more (byte_count), code->value,
+				 byte_count);
+      total_byte_count += byte_count;
+    }
+
+    /* Handle word alignment.  */
+    const unsigned required_padding = (-total_byte_count) % 4;
+    if (required_padding)
+      {
+	/* Use the nop unwind code for alignment.  */
+	const uint32_t nop_chain = 0xe3e3e3e3;
+
+	md_number_to_chars (frag_more (required_padding), nop_chain,
+			    required_padding);
+      }
+}
+
+static void
+seh_aarch64_emit_xdata_record (struct seh_aarch64_context *seh_ctx,
+			       const bool is_fragmented_function,
+			       const bool is_last_frag,
+			       const uintptr_t frag_size,
+			       const uintptr_t fragment_offset,
+			       const unsigned prologue_size,
+			       const unsigned prologue_insn_count,
+			       const unsigned first_fragment_scope,
+			       const unsigned last_fragment_scope)
+{
+  seh_aarch64_xdata_header *header = &seh_ctx->xdata_header;
+  const seh_aarch64_epilogue_scope *scopes = seh_ctx->epilogue_scopes;
+
+  /* Initialize the .xdata record.  */
+  const uint32_t func_length_encoded = frag_size >> 2;
+  header->func_length = func_length_encoded;
+  header->vers = 0;
+  header->e = 0;
+  header->code_words = 0;
+  header->epilogue_count = 0;
+
+  header->ext_code_words = 0;
+  header->ext_epilogue_count = last_fragment_scope
+				- first_fragment_scope;
+  header->reserved = 0;
+
+  /* Calculate epilogue indexes for the current fragment.  */
+  unsigned first_epilogue_index = 0;
+  unsigned last_epilogue_index = 0;
+  if (!header->ext_epilogue_count)
+    {
+      first_epilogue_index = prologue_size;
+      last_epilogue_index = prologue_size;
+    }
+  else
+    {
+      const seh_aarch64_epilogue_scope *scope;
+      scope = scopes + first_fragment_scope;
+      first_epilogue_index = scope->epilogue_start_index;
+      last_epilogue_index = seh_ctx->unwind_codes_byte_count;
+    }
+
+  /* Calculate how many unwind bytes will be emitted in .xdata record.  */
+  unsigned unwind_bytes = prologue_size;
+
+  /* Check if current fragment has a phantom prologue.  If yes, then
+      the unwinding size should be adjusted.  */
+  const bool has_phantom_prologue = is_fragmented_function && is_last_frag;
+  if (has_phantom_prologue && unwind_bytes)
+    {
+      /* One more epilogue scope and unwind code are emitted with phantom
+	  prologue.  */
+      unwind_bytes += 1;
+      ++header->ext_epilogue_count;
+    }
+
+  /* Calculate the number of code words with 4-byte alignment.  */
+  header->ext_code_words = (unwind_bytes + 3) / 4;
+
+  /* Check if short or extended header for a .xdata record should be
+      used.  */
+  unsigned header_size = 8;
+  if ((header->ext_code_words != 0 || header->ext_epilogue_count != 0)
+      && header->ext_code_words < 32
+      && header->ext_epilogue_count < 32)
+    {
+      header_size = 4;
+      header->code_words = header->ext_code_words;
+      header->epilogue_count = header->ext_epilogue_count;
+      if (header->epilogue_count == 1)
+	{
+	  header->e = 1;
+	  if (has_phantom_prologue)
+	    header->ext_epilogue_count = 0;
+	  else
+	    {
+	      const seh_aarch64_epilogue_scope *scope;
+	      scope = scopes + first_fragment_scope;
+	      header->ext_epilogue_count = scope->epilogue_start_index;
+	    }
+	}
+    }
+
+  md_number_to_chars (frag_more (header_size), seh_ctx->xdata_header_value,
+		      header_size);
+
+  if (header->ext_epilogue_count && !header->e)
+    {
+      seh_aarch64_emit_epilogue_scopes (seh_ctx,
+					fragment_offset, prologue_size,
+					first_fragment_scope,
+					last_fragment_scope,
+					has_phantom_prologue);
+      if (has_phantom_prologue)
+	{
+	  const uint32_t epilogue_start_index_encoded = 1 << 22;
+	  const uint32_t epilogue_start_offset_encoded
+	    = (frag_size - prologue_insn_count * 4) >> 2;
+	  md_number_to_chars (frag_more (4),
+			      epilogue_start_index_encoded
+			      | epilogue_start_offset_encoded, 4);
+	}
+    }
+
+  if (header->ext_code_words)
+    seh_aarch64_emit_unwind_codes (seh_ctx, prologue_size, first_epilogue_index,
+				   last_epilogue_index, has_phantom_prologue);
+
+  if (header->x == 1)
+    {
+      if (seh_ctx->handler.X_op == O_symbol)
+	seh_ctx->handler.X_op = O_symbol_rva;
+
+      emit_expr (&seh_ctx->handler, 4);
+
+      /* Emit the fragment offset.  */
+      md_number_to_chars (frag_more (4), fragment_offset, 4);
+
+      /* Use the same SEH handler data for all fragments.
+	 The SEH handler data is emitted after the last fragment.  */
+      expressionS exp;
+      memset (&exp, 0, sizeof (expressionS));
+      exp.X_op = O_symbol_rva;
+      exp.X_add_symbol = seh_ctx->handler_data_xdata_addr;
+      emit_expr (&exp, 4);
+    }
+}
+
+static bool
+seh_function_size (const struct seh_aarch64_context *seh_ctx,
+		  uintptr_t *size)
+{
+  fragS *start_frag, *end_frag;
+  addressT start_offset, end_offset;
+  start_frag = symbol_get_frag_and_value (seh_ctx->start_addr, &start_offset);
+  end_frag = symbol_get_frag_and_value (seh_ctx->end_addr, &end_offset);
+
+  intptr_t func_size = end_frag->fr_address + end_offset
+		       - start_frag->fr_address - start_offset;
+  if (func_size < 0)
+    return false;
+
+  *size = func_size;
+  return true;
+}
+
+/* Write out the xdata information for one function.  */
+static void
+seh_aarch64_write_function_xdata (struct seh_aarch64_context *seh_ctx)
+{
+  if (!seh_ctx->unwind_codes_byte_count)
+    return;
+
+  const segT save_seg = now_seg;
+  const subsegT save_subseg = now_subseg;
+
+  switch_xdata (seh_ctx->subsection, seh_ctx->code_seg);
+
+  /* Set 4-byte alignment.  */
+  frag_align (2, 0, 0);
+
+  uintptr_t func_size = 0;
+  if (!seh_function_size (seh_ctx, &func_size))
+    {
+      as_bad (_("the function size for %s has not been evaluated"),
+	      seh_ctx->func_name);
+      return;
+    }
+
+  /* The large functions should be split into fragments smaller than 1MB with
+     4 bytes alignment, based on
+     "Microsoft ARM64 exception handling, large functions documentation".  */
+  const unsigned max_frag_size = (1 << 20) - 4;
+  const bool is_fragmented_function = func_size > max_frag_size;
+
+  unsigned prologue_insn_count = 0;
+  for (unsigned i = 0; i < seh_ctx->unwind_codes_count; ++i)
+    {
+      if (seh_ctx->unwind_codes[i].type == unwind_end)
+	{
+	  prologue_insn_count = i + 1;
+	  break;
+	}
+    }
+
+  unsigned prologue_size = seh_ctx->unwind_codes_byte_count;
+
+  seh_aarch64_func_fragment *fragment;
+  fragment = &seh_ctx->func_fragment;
+  uintptr_t fragment_offset = 0;
+  unsigned first_fragment_scope = 0;
+  unsigned last_fragment_scope = 0;
+
+  /* Large functions (>= 1MB) will be split into multiple fragments.
+     However, it is expected the most of the functions will have only one
+     fragment.  This loop iterates fragments and emit them.  */
+  while (true)
+    {
+      fragment->xdata_addr = symbol_temp_new_now ();
+      fragment->offset = fragment_offset;
+      fragment->next = NULL;
+
+      /* Calculate current fragment size.  */
+      uintptr_t frag_size = func_size - fragment_offset;
+      if (frag_size > max_frag_size)
+	frag_size = max_frag_size;
+
+      const bool is_last_frag = (fragment_offset + frag_size) == func_size;
+
+      /* If it is a fragmented function, the epilogue range should be calculated
+	 and will be emitted for the current fragment, otherwise all epilogues
+	 will be emitted.  */
+      if (!is_fragmented_function)
+	last_fragment_scope = seh_ctx->epilogue_scopes_count;
+      else
+	{
+	  first_fragment_scope = last_fragment_scope;
+	  for (unsigned i = first_fragment_scope;
+	       i < seh_ctx->epilogue_scopes_count; ++i)
+	    {
+	      const seh_aarch64_epilogue_scope *scope
+		= seh_ctx->epilogue_scopes;
+	      scope += i;
+	      if (scope->epilogue_start_offset >= (fragment_offset + frag_size))
+		break;
+
+	      if (scope->epilogue_end_offset >= (fragment_offset + frag_size))
+		{
+		  frag_size = scope->epilogue_start_offset - fragment_offset;
+		  break;
+		}
+
+	      if (scope->epilogue_start_offset >= fragment_offset)
+		last_fragment_scope = i + 1;
+	    }
+	}
+
+
+      /* Emit a .xdata record for the current fragment.  */
+      seh_aarch64_emit_xdata_record (seh_ctx, is_fragmented_function,
+				     is_last_frag, frag_size, fragment_offset,
+				     prologue_size, prologue_insn_count,
+				     first_fragment_scope, last_fragment_scope);
+
+      fragment_offset += frag_size;
+      /* Exit the loop if it is the latest fragment.  */
+      if (is_last_frag)
+	break;
+
+      /* Allocate a new fragment that will be used also for emitting a .pdata
+	 record.  */
+      fragment->next = XCNEW (seh_aarch64_func_fragment);
+      fragment = fragment->next;
+    }
+
+  subseg_set (save_seg, save_subseg);
+}
+
+/* Write out pdata for one function.  */
+static void
+seh_aarch64_write_function_pdata (const seh_context *seh_ctx)
+{
+  expressionS exp;
+  const segT save_seg = now_seg;
+  const subsegT save_subseg = now_subseg;
+  memset (&exp, 0, sizeof (expressionS));
+  switch_pdata (seh_ctx->code_seg);
+
+  if (seh_ctx->unwind_codes_byte_count)
+    {
+      const seh_aarch64_func_fragment *fragment = &seh_ctx->func_fragment;
+      while (fragment)
+	{
+	  exp.X_op = O_symbol_rva;
+	  exp.X_add_number = fragment->offset;
+	  exp.X_add_symbol = seh_ctx->start_addr;
+	  emit_expr (&exp, 4);
+
+	  exp.X_op = O_symbol_rva;
+	  /* TODO: Implementing packed unwind data.  */
+	  exp.X_add_number = 0;
+	  exp.X_add_symbol = fragment->xdata_addr;
+	  emit_expr (&exp, 4);
+	  fragment = fragment->next;
+	}
+    }
+
+  subseg_set (save_seg, save_subseg);
+}
+
+void
+seh_aarch64_write_data (void)
+{
+  if (in_seh_proc)
+  {
+    as_bad (_("open SEH entry at end of file (missing .seh_endproc)"));
+    return;
+  }
+
+  if (!seh_ctx_root)
+    return;
+
+  struct seh_aarch64_context *seh_ctx = seh_ctx_root;
+  seh_ctx_root = NULL;
+
+  /* Relax the segment to be able to calculate the function sizes.  */
+  subsegs_finish_section (seh_ctx->code_seg);
+  const segment_info_type *seginfo = seg_info (seh_ctx->code_seg);
+  relax_segment (seginfo->frchainP->frch_root, seh_ctx->code_seg, 0);
+
+  while (seh_ctx)
+  {
+    seh_aarch64_write_function_xdata (seh_ctx);
+    seh_aarch64_write_function_pdata (seh_ctx);
+    struct seh_aarch64_context *next = seh_ctx->next;
+    free_seh_ctx (seh_ctx);
+    seh_ctx = next;
+  }
+}
+
+void
+obj_coff_seh_do_final (void)
+{
+}
diff --git a/gas/config/obj-coff-seh-aarch64.h b/gas/config/obj-coff-seh-aarch64.h
new file mode 100644
index 00000000000..9f3b0922832
--- /dev/null
+++ b/gas/config/obj-coff-seh-aarch64.h
@@ -0,0 +1,254 @@
+/* SEH .pdata/.xdata COFF object file format on AArch64
+   Copyright (C) 2026 Free Software Foundation, Inc.
+
+   This file is part of GAS.
+
+   GAS is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   GAS is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with GAS; see the file COPYING.  If not, write to the Free
+   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
+   02110-1301, USA.  */
+
+/* SEH COFF AArch64 implementation partially intersects with the x64
+   version, however it has a different extension to the unwind codes.
+   It emits SEH data to pdata and xdata sections.  In some cases SEH
+   data could be emitted to a packed record in the pdata section
+   without the need for data in the xdata section.  However, the packed
+   pdata record is not implemented yet.
+
+   The current implementation does not include:
+   - Packed .pdata record.
+   - Support for AdvSIMD and SVE.
+   - Epilogue start index different than 0.
+   - Number of unwind codes and epilogue scopes limits are applied to the
+     entire function, without splitting it into fragments.
+   - Big endian host has not been validated yet and might be unsupported.  */
+
+#ifndef OBJ_COFF_SEH_AARCH64_H
+#define OBJ_COFF_SEH_AARCH64_H
+
+/* Unwind codes for AArch64 are based on
+   "Microsoft ARM64 exception handling, unwind codes documentation".  */
+
+typedef enum seh_aarch64_unwind_types
+{
+  unwind_alloc_s,
+  unwind_alloc_m,
+  unwind_alloc_l,
+  unwind_save_reg,
+  unwind_save_reg_x,
+  unwind_save_regp,
+  unwind_save_regp_x,
+  unwind_save_fregp,
+  unwind_save_fregp_x,
+  unwind_save_freg,
+  unwind_save_freg_x,
+  unwind_save_lrpair,
+  unwind_save_fplr,
+  unwind_save_fplr_x,
+  unwind_save_r19r20_x,
+  unwind_add_fp,
+  unwind_set_fp,
+  unwind_save_next,
+  unwind_nop,
+  unwind_pac_sign_lr,
+  unwind_end,
+  unwind_end_c,
+  unwind_last_type = unwind_end_c
+} seh_aarch64_unwind_types;
+
+#define SEH_CMDS							\
+  /* Start a function that contains SEH.  */				\
+  {"seh_proc", obj_coff_seh_proc, 0},					\
+									\
+  /* End a function that contains SEH.  */				\
+  {"seh_endproc", obj_coff_seh_endproc, 0},				\
+									\
+  /* End a SEH prologue with unwinding codes.  */			\
+  {"seh_endprologue", obj_coff_seh_endprologue, 0},			\
+									\
+  /* Allocate stack.  */						\
+  {"seh_stackalloc", obj_coff_seh_stackalloc, 0},			\
+									\
+  /* Set a SEH handler.  */						\
+  {"seh_handler", obj_coff_seh_handler, 0},				\
+									\
+  /* Set a SEH handler data.  */					\
+  {"seh_handlerdata", obj_coff_seh_handlerdata, 0},			\
+									\
+  /* Switch back to the code section.  */				\
+  {"seh_code", obj_coff_seh_code, 0},					\
+									\
+  /* Start a SEH epilogue.  */						\
+  {"seh_startepilogue", obj_coff_seh_startepilogue, 0},			\
+									\
+  /* End a SEH epilogue.  */						\
+  {"seh_endepilogue", obj_coff_seh_endepilogue, 0},			\
+									\
+  /* Save an 'x' register.  */						\
+  {"seh_save_reg", obj_coff_seh_save_reg, unwind_save_reg},		\
+									\
+  /* Save an 'x' register with a pre-indexed offset.  */		\
+  {"seh_save_reg_x", obj_coff_seh_save_reg, unwind_save_reg_x},		\
+									\
+  /* Save an 'x' register pair.  */					\
+  {"seh_save_regp", obj_coff_seh_save_reg, unwind_save_regp},		\
+									\
+  /* Save an 'x' register pair with a pre-indexed offset.  */		\
+  {"seh_save_regp_x", obj_coff_seh_save_reg, unwind_save_regp_x},	\
+									\
+  /* Save an 'x' register and lr.  */					\
+  {"seh_save_lrpair", obj_coff_seh_save_reg, unwind_save_lrpair},	\
+									\
+  /* Save a 'd' register pair.  */					\
+  {"seh_save_fregp", obj_coff_seh_save_reg, unwind_save_fregp},		\
+									\
+  /* Save a 'd' register pair with a pre-indexed offset.  */		\
+  {"seh_save_fregp_x", obj_coff_seh_save_reg, unwind_save_fregp_x},	\
+									\
+  /* Save a 'd' register.  */						\
+  {"seh_save_freg", obj_coff_seh_save_reg, unwind_save_freg},		\
+									\
+  /* Save a 'd' register with a pre-indexed offset.  */			\
+  {"seh_save_freg_x", obj_coff_seh_save_reg, unwind_save_freg_x},	\
+									\
+  /* Save fp and lr registers.  */					\
+  {"seh_save_fplr", obj_coff_seh_save_reg, unwind_save_fplr},		\
+									\
+  /* Save fp and lr registers with a pre-indexed offset.  */		\
+  {"seh_save_fplr_x", obj_coff_seh_save_reg, unwind_save_fplr_x},	\
+									\
+  /* Save x19 and x20 registers with a pre-indexed offset.  */		\
+  {"seh_save_r19r20_x", obj_coff_seh_save_reg, unwind_save_r19r20_x},	\
+									\
+  /* Set fp by sp + offset.  */						\
+  {"seh_add_fp", obj_coff_seh_save_reg, unwind_add_fp},			\
+									\
+  /* Unwind operation is not required.  */				\
+  {"seh_nop", obj_coff_seh_save_reg, unwind_nop},			\
+									\
+  /* Sign the return address in lr with pacibsp.  */			\
+  {"seh_pac_sign_lr", obj_coff_seh_save_reg, unwind_pac_sign_lr},	\
+									\
+  /* Set fp by sp.  */							\
+  {"seh_set_fp", obj_coff_seh_save_reg, unwind_set_fp},			\
+									\
+  /* Save next register pair.  */					\
+  {"seh_save_next", obj_coff_seh_save_reg, unwind_save_next},
+
+/* AArch64 exceptions handling and unwinding structures are based on
+   "Microsoft ARM64 exception handling, pdata records documentation".  */
+
+typedef struct seh_aarch64_unwind_code
+{
+  unsigned value;
+  seh_aarch64_unwind_types type;
+} seh_aarch64_unwind_code;
+
+typedef struct seh_aarch64_packed_unwind_data
+{
+  uint32_t flag : 2;
+  uint32_t func_length : 11;
+  uint32_t frame_size : 9;
+  uint32_t cr : 2;
+  uint32_t h : 1;
+  uint32_t regI : 4;
+  uint32_t regF : 3;
+} seh_aarch64_packed_unwind_data;
+
+typedef struct seh_aarch64_except_info
+{
+  uint32_t flag : 2;
+  uint32_t except_info_rva : 30;
+} seh_aarch64_except_info;
+
+typedef union seh_aarch64_unwind_info
+{
+  seh_aarch64_except_info except_info;
+  seh_aarch64_packed_unwind_data packed_unwind_data;
+} seh_aarch64_unwind_info;
+
+typedef struct seh_aarch64_xdata_header
+{
+  uint32_t func_length : 18;
+  uint32_t vers : 2;
+  uint32_t x : 1;
+  uint32_t e : 1;
+  uint32_t epilogue_count : 5;
+  uint32_t code_words : 5;
+  uint32_t ext_epilogue_count : 16;
+  uint32_t ext_code_words : 8;
+  uint32_t reserved : 8;
+} seh_aarch64_xdata_header;
+
+typedef struct seh_aarch64_epilogue_scope
+{
+  uint32_t epilogue_start_offset_reduced : 18;
+  uint32_t reserved : 4;
+  uint32_t epilogue_start_index : 10;
+  bfd_vma epilogue_start_offset;
+  bfd_vma epilogue_end_offset;
+} seh_aarch64_epilogue_scope;
+
+typedef struct seh_aarch64_func_fragment
+{
+  bfd_vma offset;
+  symbolS *xdata_addr;
+  struct seh_aarch64_func_fragment *next;
+} seh_aarch64_func_fragment;
+
+/* AARCH64_MAX_UNWIND_CODES is limited by
+   seh_aarch64_xdata_header::ext_code_words.  */
+#define AARCH64_MAX_UNWIND_CODES (255 * 4)
+#define AARCH64_MAX_UNWIND_CODES_SIZE (255 * 4)
+/* AARCH64_MAX_EPILOGUE_SCOPES is limited by
+   seh_aarch64_xdata_header::ext_epilogue_count.  */
+#define AARCH64_MAX_EPILOGUE_SCOPES 65535
+
+typedef struct seh_aarch64_context
+{
+  struct seh_aarch64_context *next;
+
+  /* Initial code-segment.  */
+  segT code_seg;
+  /* Function name.  */
+  char *func_name;
+  /* BeginAddress.  */
+  symbolS *start_addr;
+  /* EndAddress.  */
+  symbolS *end_addr;
+  /* PrologueEnd.  */
+  symbolS *endprologue_addr;
+
+  symbolS *handler_data_xdata_addr;
+  /* ExceptionHandler.  */
+  expressionS handler;
+  /* ExceptionHandlerData.  */
+  expressionS handler_data;
+
+  subsegT subsection;
+
+  union {
+    seh_aarch64_xdata_header xdata_header;
+    valueT xdata_header_value;
+  };
+  unsigned unwind_codes_count;
+  unsigned unwind_codes_byte_count;
+  seh_aarch64_unwind_code unwind_codes[AARCH64_MAX_UNWIND_CODES];
+  unsigned epilogue_scopes_count;
+  unsigned epilogue_scopes_capacity;
+  seh_aarch64_epilogue_scope *epilogue_scopes;
+  /* The function fragments.  */
+  seh_aarch64_func_fragment func_fragment;
+} seh_context;
+
+#endif /* OBJ_COFF_SEH_AARCH64_H.  */
diff --git a/gas/config/obj-coff-seh-shared.c b/gas/config/obj-coff-seh-shared.c
index 717a7d345ef..b99a6bb67ee 100644
--- a/gas/config/obj-coff-seh-shared.c
+++ b/gas/config/obj-coff-seh-shared.c
@@ -19,7 +19,13 @@
    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
    02110-1301, USA.  */
 
+#if defined (COFFAARCH64)
+#include "obj-coff-seh-aarch64.h"
+typedef struct seh_aarch64_context seh_context_t;
+#else
 #include "obj-coff-seh.h"
+typedef struct seh_context seh_context_t;
+#endif
 
 /* Private segment collection list.  */
 struct seh_seg_list {
@@ -28,7 +34,7 @@ struct seh_seg_list {
   char *seg_name;
 };
 
-static struct seh_context *seh_ctx_cur = NULL;
+static seh_context_t *seh_ctx_cur = NULL;
 
 static htab_t seh_hash;
 
diff --git a/gas/config/obj-coff.c b/gas/config/obj-coff.c
index 7732c0af911..b08295019d8 100644
--- a/gas/config/obj-coff.c
+++ b/gas/config/obj-coff.c
@@ -55,7 +55,11 @@ static const char weak_altprefix[] = ".weak.";
 #endif /* TE_PE */
 
 #include "obj-coff-seh-shared.c"
+#if defined (COFFAARCH64)
+#include "obj-coff-seh-aarch64.c"
+#else
 #include "obj-coff-seh.c"
+#endif
 
 typedef struct
   {
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 9632a5b2a01..9a18d624f0f 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10472,6 +10472,16 @@ aarch64_cleanup (void)
     }
 }
 
+#if defined (OBJ_COFF)
+/* Called after all assembly has been done.  */
+
+void
+aarch64_md_finish (void)
+{
+  seh_aarch64_write_data ();
+}
+#endif /* OBJ_COFF.  */
+
 #ifdef OBJ_ELF
 /* Remove any excess mapping symbols generated for alignment frags in
    SEC.  We may have created a mapping symbol before a zero byte
diff --git a/gas/config/tc-aarch64.h b/gas/config/tc-aarch64.h
index d1fb4c9058b..6446ac8efb8 100644
--- a/gas/config/tc-aarch64.h
+++ b/gas/config/tc-aarch64.h
@@ -82,6 +82,12 @@ struct aarch64_fix
 
 #define tc_frob_section(S) aarch64_frob_section (S)
 
+#if defined (OBJ_COFF)
+#define md_finish aarch64_md_finish
+extern void aarch64_md_finish (void);
+extern void seh_aarch64_write_data (void);
+#endif
+
 /* The key used to sign a function's return address.  */
 enum pointer_auth_key {
   AARCH64_PAUTH_KEY_A,
diff --git a/gas/testsuite/gas/pe/pe.exp b/gas/testsuite/gas/pe/pe.exp
index e25de3cfa9d..cc7701587ac 100644
--- a/gas/testsuite/gas/pe/pe.exp
+++ b/gas/testsuite/gas/pe/pe.exp
@@ -63,6 +63,9 @@ if ([istarget "x86_64-*-mingw*"]) then {
 # This test is only for AArch64
 if {[istarget "aarch64-*-pe*"] || [istarget "aarch64-*-mingw*"]} {
 	run_dump_test "pe-aarch64"
+	run_dump_test "seh-aarch64"
+	run_dump_test "seh-aarch64-large-func"
+	run_list_test "seh-aarch64-error" ""
 }
 
 # Big obj
diff --git a/gas/testsuite/gas/pe/seh-aarch64-error.l b/gas/testsuite/gas/pe/seh-aarch64-error.l
new file mode 100644
index 00000000000..c37beb932f0
--- /dev/null
+++ b/gas/testsuite/gas/pe/seh-aarch64-error.l
@@ -0,0 +1,110 @@
+.*: Assembler messages:
+.*:2: Error: .seh_endprologue used outside of .seh_proc block
+.*:3: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:4: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:5: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:6: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:7: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:8: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:9: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:10: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:11: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:12: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:13: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:14: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:15: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:16: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:17: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:18: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:19: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:20: Error: SEH entry has not been found \(missing .seh_proc\)
+.*:21: Error: .seh_endproc used without .seh_proc
+.*:23: Error: .seh_proc requires function label name
+.*:24: Error: previous SEH entry not closed \(missing .seh_endproc\)
+.*:29: Error: offset overflows expected range
+.*:30: Error: offset should be a multiple of 16
+.*:31: Error: .seh_stackalloc offset is out of range
+.*:33: Error: unexpected register number
+.*:34: Error: unexpected register number
+.*:35: Error: unexpected register name
+.*:36: Error: offset is negative
+.*:36: Error: offset overflows expected range
+.*:38: Error: offset should be a multiple of 8
+.*:39: Error: offset overflows expected range
+.*:41: Error: unexpected register number
+.*:42: Error: unexpected register number
+.*:43: Error: unexpected register name
+.*:44: Error: offset is negative
+.*:44: Error: offset overflows expected range
+.*:46: Error: offset should be a multiple of 8
+.*:47: Error: offset overflows expected range
+.*:49: Error: unexpected register number
+.*:50: Error: unexpected register number
+.*:51: Error: unexpected register name
+.*:52: Error: unexpected register number
+.*:53: Error: offset is negative
+.*:53: Error: offset overflows expected range
+.*:55: Error: offset should be a multiple of 8
+.*:56: Error: offset overflows expected range
+.*:58: Error: unexpected register number
+.*:59: Error: unexpected register number
+.*:60: Error: unexpected register name
+.*:61: Error: unexpected register number
+.*:62: Error: offset is negative
+.*:62: Error: offset overflows expected range
+.*:64: Error: offset should be a multiple of 8
+.*:65: Error: offset overflows expected range
+.*:67: Error: unexpected register number
+.*:67: Error: unexpected register number
+.*:68: Error: unexpected register number
+.*:69: Error: unexpected register name
+.*:70: Error: unexpected register number
+.*:71: Error: offset is negative
+.*:71: Error: offset overflows expected range
+.*:73: Error: offset should be a multiple of 8
+.*:74: Error: offset overflows expected range
+.*:76: Error: unexpected register number
+.*:77: Error: unexpected register number
+.*:78: Error: unexpected register name
+.*:79: Error: offset is negative
+.*:79: Error: offset overflows expected range
+.*:81: Error: offset should be a multiple of 8
+.*:82: Error: offset overflows expected range
+.*:84: Error: unexpected register number
+.*:85: Error: unexpected register number
+.*:86: Error: unexpected register name
+.*:87: Error: offset is negative
+.*:87: Error: offset overflows expected range
+.*:89: Error: offset should be a multiple of 8
+.*:90: Error: offset overflows expected range
+.*:92: Error: unexpected register number
+.*:93: Error: unexpected register number
+.*:94: Error: unexpected register name
+.*:95: Error: offset is negative
+.*:95: Error: offset overflows expected range
+.*:97: Error: offset should be a multiple of 8
+.*:98: Error: offset overflows expected range
+.*:100: Error: unexpected register number
+.*:101: Error: unexpected register number
+.*:102: Error: unexpected register name
+.*:103: Error: offset is negative
+.*:103: Error: offset overflows expected range
+.*:105: Error: offset should be a multiple of 8
+.*:106: Error: offset overflows expected range
+.*:108: Error: offset is negative
+.*:108: Error: offset overflows expected range
+.*:110: Error: offset should be a multiple of 8
+.*:111: Error: offset overflows expected range
+.*:113: Error: offset is negative
+.*:113: Error: offset overflows expected range
+.*:115: Error: offset should be a multiple of 8
+.*:116: Error: offset overflows expected range
+.*:118: Error: offset is negative
+.*:118: Error: offset overflows expected range
+.*:120: Error: offset should be a multiple of 8
+.*:121: Error: offset overflows expected range
+.*:123: Error: offset is negative
+.*:123: Error: offset overflows expected range
+.*:125: Error: offset should be a multiple of 8
+.*:126: Error: offset overflows expected range
+.*: Error: open SEH entry at end of file \(missing .seh_endproc\)
diff --git a/gas/testsuite/gas/pe/seh-aarch64-error.s b/gas/testsuite/gas/pe/seh-aarch64-error.s
new file mode 100644
index 00000000000..dc4118b7390
--- /dev/null
+++ b/gas/testsuite/gas/pe/seh-aarch64-error.s
@@ -0,0 +1,128 @@
+	.text
+	.seh_endprologue
+	.seh_stackalloc 16
+	.seh_save_reg x19, 0
+	.seh_save_reg_x x19, 16
+	.seh_save_regp x19, 32
+	.seh_save_regp_x x19, 48
+	.seh_save_lrpair x19, 64
+	.seh_save_fregp d8, 80
+	.seh_save_fregp_x d8, 96
+	.seh_save_freg d8, 112
+	.seh_save_freg_x d8, 128
+	.seh_save_fplr 144
+	.seh_save_fplr_x 160
+	.seh_save_r19r20_x 176
+	.seh_add_fp 192
+	.seh_nop
+	.seh_pac_sign_lr
+	.seh_set_fp
+	.seh_save_next
+	.seh_endproc
+
+	.seh_proc
+	.seh_proc foo
+	.seh_endproc
+
+	.seh_proc foo
+
+	.seh_stackalloc -16
+	.seh_stackalloc 268435455
+	.seh_stackalloc 268435456
+
+	.seh_save_reg x18, 0
+	.seh_save_reg x31, 0
+	.seh_save_reg d19, 0
+	.seh_save_reg x19, -8
+	.seh_save_reg x19, 504
+	.seh_save_reg x19, 511
+	.seh_save_reg x19, 512
+
+	.seh_save_reg_x x18, 16
+	.seh_save_reg_x x31, 16
+	.seh_save_reg_x d19, 16
+	.seh_save_reg_x x19, -8
+	.seh_save_reg_x x19, 256
+	.seh_save_reg_x x19, 263
+	.seh_save_reg_x x19, 264
+
+	.seh_save_regp x18, 32
+	.seh_save_regp x31, 32
+	.seh_save_regp d19, 32
+	.seh_save_regp x30, 32
+	.seh_save_regp x19, -8
+	.seh_save_regp x19, 504
+	.seh_save_regp x19, 511
+	.seh_save_regp x19, 512
+
+	.seh_save_regp_x x18, 48
+	.seh_save_regp_x x31, 48
+	.seh_save_regp_x d19, 48
+	.seh_save_regp_x x30, 48
+	.seh_save_regp_x x19, -8
+	.seh_save_regp_x x19, 512
+	.seh_save_regp_x x19, 519
+	.seh_save_regp_x x19, 520
+
+	.seh_save_lrpair x18, 64
+	.seh_save_lrpair x31, 64
+	.seh_save_lrpair d19, 64
+	.seh_save_lrpair x20, 64
+	.seh_save_lrpair x19, -8
+	.seh_save_lrpair x19, 504
+	.seh_save_lrpair x19, 511
+	.seh_save_lrpair x19, 512
+
+	.seh_save_fregp d7, 80
+	.seh_save_fregp d16, 80
+	.seh_save_fregp x8, 80
+	.seh_save_fregp d8, -8
+	.seh_save_fregp d8, 504
+	.seh_save_fregp d8, 511
+	.seh_save_fregp d8, 512
+
+	.seh_save_fregp_x d7, 96
+	.seh_save_fregp_x d16, 96
+	.seh_save_fregp_x x8, 96
+	.seh_save_fregp_x d8, -8
+	.seh_save_fregp_x d8, 512
+	.seh_save_fregp_x d8, 519
+	.seh_save_fregp_x d8, 520
+
+	.seh_save_freg d7, 112
+	.seh_save_freg d16, 112
+	.seh_save_freg x8, 112
+	.seh_save_freg d8, -8
+	.seh_save_freg d8, 504
+	.seh_save_freg d8, 511
+	.seh_save_freg d8, 512
+
+	.seh_save_freg_x d7, 128
+	.seh_save_freg_x d16, 128
+	.seh_save_freg_x x8, 128
+	.seh_save_freg_x d8, -8
+	.seh_save_freg_x d8, 256
+	.seh_save_freg_x d8, 263
+	.seh_save_freg_x d8, 264
+
+	.seh_save_fplr -8
+	.seh_save_fplr 504
+	.seh_save_fplr 511
+	.seh_save_fplr 512
+
+	.seh_save_fplr_x -8
+	.seh_save_fplr_x 512
+	.seh_save_fplr_x 519
+	.seh_save_fplr_x 520
+
+	.seh_save_r19r20_x -8
+	.seh_save_r19r20_x 248
+	.seh_save_r19r20_x 255
+	.seh_save_r19r20_x 256
+
+	.seh_add_fp -8
+	.seh_add_fp 2040
+	.seh_add_fp 2047
+	.seh_add_fp 2048
+
+	.seh_endprologue
diff --git a/gas/testsuite/gas/pe/seh-aarch64-large-func.d b/gas/testsuite/gas/pe/seh-aarch64-large-func.d
new file mode 100644
index 00000000000..61338de5145
--- /dev/null
+++ b/gas/testsuite/gas/pe/seh-aarch64-large-func.d
@@ -0,0 +1,53 @@
+#objdump: -s -j .xdata
+#name: PEP aarch64 SEH large function
+
+.*:     file format pe-aarch64-little
+
+Contents of section .xdata:
+
+# .xdata SEH record
+# 0x0813ffff  code-words: 1
+#             epilogue-count: 0
+#             single-epilogue-in-header: 0
+#             exception-data: 1
+#             version: 0
+#             function-size: 1048572
+# 0x01         .seh_stackalloc 16
+# 0xe4        end
+# 0xe3        nop
+# 0xe3        nop
+# 0x00000000  seh-handler
+# 0x00000000  fragment-offset
+# 0x0000003c  seh-handle-data-address
+# 0x0813ffff  code-words: 1
+#             epilogue-count: 0
+#             single-epilogue-in-header: 0
+#             exception-data: 1
+#             version: 0
+#             function-size: 1048572
+# 0x01        .seh_stackalloc 16
+# 0xe4        end
+# 0xe3        nop
+# 0xe3        nop
+# 0x00000000  seh-handler
+# 0x000ffffc  fragment-offset
+# 0x0000003c  seh-handle-data-address
+# 0x087002ca  code-words: 1
+#             epilogue-count: 0
+#             single-epilogue-in-header: 0
+#             exception-data: 1
+#             version: 0
+#             function-size: 2856
+# 0xe5        end_c
+# 0x01         .seh_stackalloc 16
+# 0xe4        end
+# 0xe3        nop
+# 0x00000000  seh-handler
+# 0x001ffff8  fragment-offset
+# 0x0000003c  seh-handle-data-address
+# 0x00000001  long 1 (seh_handlerdata)
+
+ 0000 ffff1308 01e4e3e3 00000000 00000000  .*
+ 0010 3c000000 ffff1308 01e4e3e3 00000000  .*
+ 0020 fcff0f00 3c000000 ca027008 e501e4e3  .*
+ 0030 00000000 f8ff1f00 3c000000 01000000  .*
\ No newline at end of file
diff --git a/gas/testsuite/gas/pe/seh-aarch64-large-func.s b/gas/testsuite/gas/pe/seh-aarch64-large-func.s
new file mode 100644
index 00000000000..4e7d4772b65
--- /dev/null
+++ b/gas/testsuite/gas/pe/seh-aarch64-large-func.s
@@ -0,0 +1,13 @@
+	.text
+	.seh_proc	foo
+foo:
+	.seh_stackalloc 16
+	.seh_endprologue
+	.rept 2100000 / 4
+	nop
+	.endr
+	.seh_handler _ZN9exception6handleEPvS0_S0_S0_, @except
+	.seh_handlerdata
+	.long 1
+	.seh_code
+	.seh_endproc
diff --git a/gas/testsuite/gas/pe/seh-aarch64.d b/gas/testsuite/gas/pe/seh-aarch64.d
new file mode 100644
index 00000000000..829e7bc362e
--- /dev/null
+++ b/gas/testsuite/gas/pe/seh-aarch64.d
@@ -0,0 +1,66 @@
+#objdump: -s -j .xdata
+#name: PEP aarch64 SEH
+
+.*:     file format pe-aarch64-little
+
+Contents of section .xdata:
+
+# .xdata SEH record
+# 0x98700000  code-words: 19
+#             epilogue-count: 1
+#             single-epilogue-in-header: 1
+#             exception-data: 1
+#             version: 0
+#             function-size: 0
+# 0xe6        .seh_save_next
+# 0xe1        .seh_set_fp
+# 0xfc        .seh_pac_sign_lr
+# 0xe3        .seh_nop
+# 0xe218      .seh_add_fp 192
+# 0x36        .seh_save_r19r20_x 176
+# 0x93        .seh_save_fplr_x 160
+# 0x52        .seh_save_fplr 144
+# 0xdeef      .seh_save_freg_x d15, 128
+# 0xde2f      .seh_save_freg_x d9, 128
+# 0xde0f      .seh_save_freg_x d8, 128
+# 0xddce      .seh_save_freg d15, 112
+# 0xdc4e      .seh_save_freg d9, 112
+# 0xdc0e      .seh_save_freg d8, 112
+# 0xdbcb      .seh_save_fregp_x d15, 96
+# 0xda4b      .seh_save_fregp_x d9, 96
+# 0xda0b      .seh_save_fregp_x d8, 96
+# 0xd9ca      .seh_save_fregp d15, 80
+# 0xd84a      .seh_save_fregp d9, 80
+# 0xd80a      .seh_save_fregp d8, 80
+# 0xd748      .seh_save_lrpair x29, 64
+# 0xd648      .seh_save_lrpair x21, 64
+# 0xd608      .seh_save_lrpair x19, 64
+# 0xce85      .seh_save_regp_x x29, 48
+# 0xcc45      .seh_save_regp_x x20, 48
+# 0xcc05      .seh_save_regp_x x19, 48
+# 0xca84      .seh_save_regp x29, 32
+# 0xc844      .seh_save_regp x20, 32
+# 0xc804      .seh_save_regp x19, 32
+# 0xd561      .seh_save_reg_x x30, 16
+# 0xd421      .seh_save_reg_x x20, 16
+# 0xd401      .seh_save_reg_x x19, 16
+# 0xd2c0      .seh_save_reg x30, 0
+# 0xd040      .seh_save_reg x20, 0
+# 0xd000      .seh_save_reg x19, 0
+# 0xe0ffffff  .seh_stackalloc 268435440
+# 0xe0000800  .seh_stackalloc 32768
+# 0xc020      .seh_stackalloc 512
+# 0x01        .seh_stackalloc 16
+# 0xe4        nop
+# 0xe4        nop
+# 0x00000000  seh-handler
+# 0x00000000  fragment-offset
+# 0x0000005c  seh-handle-data-address
+# 0x00000001  long 1 (seh_handlerdata)
+
+ 0000 00007098 e6e1fce3 e2183693 52deefde  .*
+ 0010 2fde0fdd cedc4edc 0edbcbda 4bda0bd9  .*
+ 0020 cad84ad8 0ad748d6 48d608ce 85cc45cc  .*
+ 0030 05ca84c8 44c804d5 61d421d4 01d2c0d0  .*
+ 0040 40d000e0 ffffffe0 000800c0 2001e4e4  .*
+ 0050 00000000 00000000 5c000000 01000000  .*
\ No newline at end of file
diff --git a/gas/testsuite/gas/pe/seh-aarch64.s b/gas/testsuite/gas/pe/seh-aarch64.s
new file mode 100644
index 00000000000..5868a7f57dc
--- /dev/null
+++ b/gas/testsuite/gas/pe/seh-aarch64.s
@@ -0,0 +1,49 @@
+	.text
+	.seh_proc	foo
+	.seh_stackalloc 16
+	.seh_stackalloc 512
+	.seh_stackalloc 32768
+	.seh_stackalloc 268435440
+	.seh_save_reg x19, 0
+	.seh_save_reg x20, 0
+	.seh_save_reg x30, 0
+	.seh_save_reg_x x19, 16
+	.seh_save_reg_x x20, 16
+	.seh_save_reg_x x30, 16
+	.seh_save_regp x19, 32
+	.seh_save_regp x20, 32
+	.seh_save_regp x29, 32
+	.seh_save_regp_x x19, 48
+	.seh_save_regp_x x20, 48
+	.seh_save_regp_x x29, 48
+	.seh_save_lrpair x19, 64
+	.seh_save_lrpair x21, 64
+	.seh_save_lrpair x29, 64
+	.seh_save_fregp d8, 80
+	.seh_save_fregp d9, 80
+	.seh_save_fregp d15, 80
+	.seh_save_fregp_x d8, 96
+	.seh_save_fregp_x d9, 96
+	.seh_save_fregp_x d15, 96
+	.seh_save_freg d8, 112
+	.seh_save_freg d9, 112
+	.seh_save_freg d15, 112
+	.seh_save_freg_x d8, 128
+	.seh_save_freg_x d9, 128
+	.seh_save_freg_x d15, 128
+	.seh_save_fplr 144
+	.seh_save_fplr_x 160
+	.seh_save_r19r20_x 176
+	.seh_add_fp 192
+	.seh_nop
+	.seh_pac_sign_lr
+	.seh_set_fp
+	.seh_save_next
+	.seh_endprologue
+	.seh_handler _ZN9exception6handleEPvS0_S0_S0_, @except
+	.seh_handlerdata
+	.long 1
+	.seh_code
+	.seh_startepilogue
+	.seh_endepilogue
+	.seh_endproc
diff --git a/gas/write.c b/gas/write.c
index 9514c3df42e..b1a0d00a275 100644
--- a/gas/write.c
+++ b/gas/write.c
@@ -1839,7 +1839,7 @@ set_symtab (void)
 #endif
 #endif
 
-static void
+void
 subsegs_finish_section (asection *s)
 {
   struct frchain *frchainP;
diff --git a/gas/write.h b/gas/write.h
index bc5260a2efd..69072cd57e2 100644
--- a/gas/write.h
+++ b/gas/write.h
@@ -191,5 +191,6 @@ extern void as_bad_subtract (fixS *);
 struct segment_info_struct;
 extern fragS *get_frag_for_address (fragS *, const struct segment_info_struct *,
 				    addressT);
+extern void subsegs_finish_section (asection *);
 
 #endif /* __write_h__ */

From rearnsha@arm.com  Fri Jun 26 13:35:13 2026
From: rearnsha@arm.com (Richard Earnshaw)
Date: Fri, 26 Jun 2026 14:35:13 +0100
Subject: [PATCH v2 0/3] aarch64: deprecate some ISA features
Message-ID: <20260626133516.1904430-1-rearnsha@arm.com>

A couple of features which were specified in the architecture, but
never implemented in products have been withdrawn.  This short series
adjusts the assembler to warn if they are used in real code.  The
intent is to ultimately remove support entirely from the tools, but
we'll do that in stages and deprecation is the first step.

I'd like to get this committed some time next week, so that it's in
with plenty of time before for the upcoming branch.

Changes since v1:

 - Incorporate most of the feedback from Jan

Richard Earnshaw (3):
  aarch64: Remove a stray comment from opcode/aarch64.h
  aarch64: warn if the TME feature is used during assembly.
  aarch64: deprecate mpamv2_vid sysregs

 gas/NEWS                                      |  5 ++++
 gas/config/tc-aarch64.c                       | 24 +++++++++++++++++--
 .../gas/aarch64/sysreg/mpamv2_vid-bad.l       | 12 ++++++++++
 .../gas/aarch64/sysreg/mpamv2_vid-depr.l      |  7 ++++++
 gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.d | 15 ++++++------
 gas/testsuite/gas/aarch64/tme-warn.l          | 15 ++++++++++++
 gas/testsuite/gas/aarch64/tme.d               |  1 +
 include/opcode/aarch64.h                      |  6 +++--
 opcodes/aarch64-sys-regs.def                  |  6 ++---
 opcodes/aarch64-tbl.h                         | 10 ++++----
 10 files changed, 82 insertions(+), 19 deletions(-)
 create mode 100644 gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-depr.l
 create mode 100644 gas/testsuite/gas/aarch64/tme-warn.l

-- 
2.43.0


From rearnsha@arm.com  Fri Jun 26 13:35:14 2026
From: rearnsha@arm.com (Richard Earnshaw)
Date: Fri, 26 Jun 2026 14:35:14 +0100
Subject: [PATCH v2 1/3] aarch64: Remove a stray comment from opcode/aarch64.h
In-Reply-To: <20260626133516.1904430-1-rearnsha@arm.com>
References: <20260626133516.1904430-1-rearnsha@arm.com>
Message-ID: <20260626133516.1904430-2-rearnsha@arm.com>

When flag bit 28 was removed in an earlier patch, the comment describing
it was left behind.  This just cleans that up.
---
 include/opcode/aarch64.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 6d1b414444a..f51045210c9 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1479,7 +1479,7 @@ extern const aarch64_opcode aarch64_opcode_table[];
 #define F_OD(X) (((X) & 0x7) << 24)
 /* Instruction has the field of 'sz'.  */
 #define F_LSE_SZ (1 << 27)
-/* Require an exact qualifier match, even for NIL qualifiers.  */
+
 
 #define F_SYS_READ (1ULL << 29)
 /* This system instruction is used to write system registers.  */
-- 
2.43.0


From rearnsha@arm.com  Fri Jun 26 13:35:15 2026
From: rearnsha@arm.com (Richard Earnshaw)
Date: Fri, 26 Jun 2026 14:35:15 +0100
Subject: [PATCH v2 2/3] aarch64: warn if the TME feature is used during
 assembly.
In-Reply-To: <20260626133516.1904430-1-rearnsha@arm.com>
References: <20260626133516.1904430-1-rearnsha@arm.com>
Message-ID: <20260626133516.1904430-3-rearnsha@arm.com>

Arm has obsoleted the unimplemented TME feature.  Warn if instructions
from this feature are encountered.

Also tweak warn_unpredictable_ldst to use const more often, since the
arguments are the same as for the new warn_deprecated function.
---
 gas/NEWS                             |  4 ++++
 gas/config/tc-aarch64.c              | 24 ++++++++++++++++++++++--
 gas/testsuite/gas/aarch64/tme-warn.l | 15 +++++++++++++++
 gas/testsuite/gas/aarch64/tme.d      |  1 +
 include/opcode/aarch64.h             |  6 ++++--
 opcodes/aarch64-tbl.h                | 10 +++++-----
 6 files changed, 51 insertions(+), 9 deletions(-)
 create mode 100644 gas/testsuite/gas/aarch64/tme-warn.l

diff --git a/gas/NEWS b/gas/NEWS
index 4c55a544f25..116d5e62be6 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,9 @@
 -*- text -*-
 
+* The aarch64 TME extension has never been implemented in any products.  Arm
+  has withdrawn it from the architecture.  The assembler will now warn if
+  instructions from the extension are detected during assembly.
+
 * The legacy .vtable_entry and .vtable_inherit directives that were
   needed for versions of GCC prior to gcc-3.0 (when the generic C++
   ABI was adopted) are now considered obsolete.  They are now deprecated
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 9632a5b2a01..587c3588b09 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -8743,9 +8743,9 @@ programmer_friendly_fixup (aarch64_instruction *instr)
 /* Check for loads and stores that will cause unpredictable behavior.  */
 
 static void
-warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
+warn_unpredictable_ldst (const aarch64_instruction *instr, const char *str)
 {
-  aarch64_inst *base = &instr->base;
+  const aarch64_inst *base = &instr->base;
   const aarch64_opcode *opcode = base->opcode;
   const aarch64_opnd_info *opnds = base->operands;
   switch (opcode->iclass)
@@ -8841,6 +8841,25 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
     }
 }
 
+static void
+warn_deprecated (const aarch64_instruction *instr, const char *str)
+{
+  const aarch64_inst *base = &instr->base;
+  const aarch64_opcode *opcode = base->opcode;
+  if (!(opcode->flags & F_DEPRECATED_INSN))
+    return;
+  switch (opcode->iclass)
+    {
+    case tme:
+      as_warn (_("the TME feature has been deprecated -- `%s'"), str);
+      break;
+    default:
+      /* Instruction marked as deprecated, but a suitable warning not
+	 added above.  */
+      abort();
+    }
+}
+
 static void
 force_automatic_sequence_close (void)
 {
@@ -9019,6 +9038,7 @@ md_assemble (char *str)
 	    }
 
 	  warn_unpredictable_ldst (&inst, str);
+	  warn_deprecated (&inst, str);
 
 	  if (inst.reloc.type == BFD_RELOC_UNUSED
 	      || !inst.reloc.need_libopcodes_p)
diff --git a/gas/testsuite/gas/aarch64/tme-warn.l b/gas/testsuite/gas/aarch64/tme-warn.l
new file mode 100644
index 00000000000..ed26e4ed95c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tme-warn.l
@@ -0,0 +1,15 @@
+[^:]*: Assembler messages:
+.*: Warning: the TME feature has been deprecated -- `tstart x0'
+.*: Warning: the TME feature has been deprecated -- `tstart X0'
+.*: Warning: the TME feature has been deprecated -- `tstart x15'
+.*: Warning: the TME feature has been deprecated -- `tstart X15'
+.*: Warning: the TME feature has been deprecated -- `tstart x30'
+.*: Warning: the TME feature has been deprecated -- `tstart X30'
+.*: Warning: the TME feature has been deprecated -- `tcommit'
+.*: Warning: the TME feature has been deprecated -- `tcommit'
+.*: Warning: the TME feature has been deprecated -- `ttest x0'
+.*: Warning: the TME feature has been deprecated -- `ttest X30'
+.*: Warning: the TME feature has been deprecated -- `tcancel 0'
+.*: Warning: the TME feature has been deprecated -- `tcancel 65535'
+.*: Warning: the TME feature has been deprecated -- `tcancel 0xffff'
+.*: Warning: the TME feature has been deprecated -- `tcancel 0XA'
diff --git a/gas/testsuite/gas/aarch64/tme.d b/gas/testsuite/gas/aarch64/tme.d
index 24d34ea9561..66527b03921 100644
--- a/gas/testsuite/gas/aarch64/tme.d
+++ b/gas/testsuite/gas/aarch64/tme.d
@@ -1,4 +1,5 @@
 #as: -march=armv8-a+tme
+#warning_output: tme-warn.l
 #objdump: -dr
 
 .* file format .*
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index f51045210c9..2d8514b8e7d 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1219,6 +1219,7 @@ enum aarch64_insn_class
   sve_shift_tsz_bhsd,
   sve_size_tsz_bhs,
   testbranch,
+  tme,
   cryptosm3,
   cryptosm4,
   dotproduct,
@@ -1479,7 +1480,8 @@ extern const aarch64_opcode aarch64_opcode_table[];
 #define F_OD(X) (((X) & 0x7) << 24)
 /* Instruction has the field of 'sz'.  */
 #define F_LSE_SZ (1 << 27)
-
+/* The instruction has been deprecated.  */
+#define F_DEPRECATED_INSN (1 << 28)
 
 #define F_SYS_READ (1ULL << 29)
 /* This system instruction is used to write system registers.  */
@@ -1542,7 +1544,7 @@ extern const aarch64_opcode aarch64_opcode_table[];
 /* As above, plus PN registers.  */
 #define F_INVALID_IMM_SYMS_3 (3ULL << 42)
 
-/* Next bit is 44, and 28 is also unused.  */
+/* Next bit is 44.  */
 
 /* Instruction constraints.  */
 /* This instruction has a predication constraint on the instruction at PC+4.  */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 518109ecfd6..c6cb5257008 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -3374,7 +3374,7 @@ static const aarch64_feature_set aarch64_feature_mpamv2 =
 #define MEMTAG_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
 #define _TME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
-  { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
+  { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1 | F_DEPRECATED_INSN, 0, 0, NULL }
 #define SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
   { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
     FLAGS | F_INVALID_IMM_SYMS_2, 0, TIED, NULL }
@@ -5154,10 +5154,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   CORE_INSN ("adr",  0x10000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_PCREL21), QL_ADRP, 0),
   CORE_INSN ("adrp", 0x90000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_ADRP), QL_ADRP, 0),
   /* TME Instructions.  */
-  _TME_INSN ("tstart", 0xd5233060, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
-  _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, 0, 0, OP0 (), QL_0, 0),
-  _TME_INSN ("ttest", 0xd5233160, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
-  _TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, 0, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0),
+  _TME_INSN ("tstart", 0xd5233060, 0xffffffe0, tme, 0, OP1 (Rd), QL_I1X, 0),
+  _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, tme, 0, OP0 (), QL_0, 0),
+  _TME_INSN ("ttest", 0xd5233160, 0xffffffe0, tme, 0, OP1 (Rd), QL_I1X, 0),
+  _TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, tme, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0),
   /* SME instructions (aliases for MSR <sysreg> operations.  */
   SME_INSN ("smstart", 0xd503477f, 0xffffffff, sme_start, 0, OP0 (), QL_0, F_SYS_WRITE, 0),
   SME_INSN ("smstop",  0xd503467f, 0xffffffff, sme_stop,  0, OP0 (), QL_0, F_SYS_WRITE, 0),
-- 
2.43.0


From rearnsha@arm.com  Fri Jun 26 13:35:16 2026
From: rearnsha@arm.com (Richard Earnshaw)
Date: Fri, 26 Jun 2026 14:35:16 +0100
Subject: [PATCH v2 3/3] aarch64: deprecate mpamv2_vid sysregs
In-Reply-To: <20260626133516.1904430-1-rearnsha@arm.com>
References: <20260626133516.1904430-1-rearnsha@arm.com>
Message-ID: <20260626133516.1904430-4-rearnsha@arm.com>

These registers were never implemented in any products and have been
withdrawn from the architecture.  Mark the registers as deprecated
and update the testsuite accordingly.
---
 gas/NEWS                                          |  7 ++++---
 gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.l | 12 ++++++++++++
 .../gas/aarch64/sysreg/mpamv2_vid-depr.l          |  7 +++++++
 gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.d     | 15 ++++++++-------
 opcodes/aarch64-sys-regs.def                      |  6 +++---
 5 files changed, 34 insertions(+), 13 deletions(-)
 create mode 100644 gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-depr.l

diff --git a/gas/NEWS b/gas/NEWS
index 116d5e62be6..62c28932189 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,8 +1,9 @@
 -*- text -*-
 
-* The aarch64 TME extension has never been implemented in any products.  Arm
-  has withdrawn it from the architecture.  The assembler will now warn if
-  instructions from the extension are detected during assembly.
+* The aarch64 extensions TME and MPAMv2_VID have never been implemented in any
+  products.  Arm has withdrawn them from the architecture.  The assembler will
+  now warn if instructions or system registers from either extension are
+  detected during assembly.
 
 * The legacy .vtable_entry and .vtable_inherit directives that were
   needed for versions of GCC prior to gcc-3.0 (when the generic C++
diff --git a/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.l b/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.l
index 6ab3d16fba0..a61ec858e73 100644
--- a/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.l
+++ b/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.l
@@ -1,13 +1,25 @@
 .*: Assembler messages:
 .*: Error: selected processor does not support system register name 'mpamvidcr_el2'
 .*:  Info: macro invoked from here
+.*: Warning: system register name 'mpamvidcr_el2' is deprecated and may be removed in a future release
+.*:  Info: macro invoked from here
 .*: Error: selected processor does not support system register name 'mpamvidcr_el2'
 .*:  Info: macro invoked from here
+.*: Warning: system register name 'mpamvidcr_el2' is deprecated and may be removed in a future release
+.*:  Info: macro invoked from here
 .*: Error: selected processor does not support system register name 'mpamvidsr_el2'
 .*:  Info: macro invoked from here
+.*: Warning: system register name 'mpamvidsr_el2' is deprecated and may be removed in a future release
+.*:  Info: macro invoked from here
 .*: Error: selected processor does not support system register name 'mpamvidsr_el2'
 .*:  Info: macro invoked from here
+.*: Warning: system register name 'mpamvidsr_el2' is deprecated and may be removed in a future release
+.*:  Info: macro invoked from here
 .*: Error: selected processor does not support system register name 'mpamvidsr_el3'
 .*:  Info: macro invoked from here
+.*: Warning: system register name 'mpamvidsr_el3' is deprecated and may be removed in a future release
+.*:  Info: macro invoked from here
 .*: Error: selected processor does not support system register name 'mpamvidsr_el3'
 .*:  Info: macro invoked from here
+.*: Warning: system register name 'mpamvidsr_el3' is deprecated and may be removed in a future release
+.*:  Info: macro invoked from here
diff --git a/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-depr.l b/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-depr.l
new file mode 100644
index 00000000000..6fc9b23b70b
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-depr.l
@@ -0,0 +1,7 @@
+.*: Assembler messages:
+.*: Warning: system register name 'mpamvidcr_el2' is deprecated and may be removed in a future release
+.*: Warning: system register name 'mpamvidcr_el2' is deprecated and may be removed in a future release
+.*: Warning: system register name 'mpamvidsr_el2' is deprecated and may be removed in a future release
+.*: Warning: system register name 'mpamvidsr_el2' is deprecated and may be removed in a future release
+.*: Warning: system register name 'mpamvidsr_el3' is deprecated and may be removed in a future release
+.*: Warning: system register name 'mpamvidsr_el3' is deprecated and may be removed in a future release
diff --git a/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.d b/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.d
index 88c0c1883d8..1399d095d54 100644
--- a/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.d
+++ b/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.d
@@ -1,4 +1,5 @@
-#as: -menable-sysreg-checking -march=armv8-a+mpamv2 -I$srcdir/$subdir
+#as: -menable-sysreg-checking -march=armv8-a+mpamv2 -I$srcdir/$subdir --no-info
+#warning_output: mpamv2_vid-depr.l
 #objdump: -dr
 
 .*:     file format .*
@@ -6,9 +7,9 @@
 Disassembly of section \.text:
 
 0+ <.*>:
-.*:	d51ca700 	msr	mpamvidcr_el2, x0
-.*:	d53ca700 	mrs	x0, mpamvidcr_el2
-.*:	d51ca720 	msr	mpamvidsr_el2, x0
-.*:	d53ca720 	mrs	x0, mpamvidsr_el2
-.*:	d51ea720 	msr	mpamvidsr_el3, x0
-.*:	d53ea720 	mrs	x0, mpamvidsr_el3
+.*:	d51ca700 	msr	s3_4_c10_c7_0, x0
+.*:	d53ca700 	mrs	x0, s3_4_c10_c7_0
+.*:	d51ca720 	msr	s3_4_c10_c7_1, x0
+.*:	d53ca720 	mrs	x0, s3_4_c10_c7_1
+.*:	d51ea720 	msr	s3_6_c10_c7_1, x0
+.*:	d53ea720 	mrs	x0, s3_6_c10_c7_1
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index 9daa178ed7b..e8eee8a7c66 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -929,9 +929,9 @@
   SYSREG ("mpamhcr_el2",	CPENC (3,4,10,4,0),	0,		AARCH64_FEATURE (V8_2A)) /* MPAM */
   SYSREG ("mpamidr_el1",	CPENC (3,0,10,4,4),	F_REG_READ,	AARCH64_FEATURE (V8_2A)) /* MPAM */
   SYSREG ("mpamsm_el1",		CPENC (3,0,10,5,3),	0,		AARCH64_FEATURES (2, SME, V8_2A)) /* SME && MPAM */
-  SYSREG ("mpamvidcr_el2",	CPENC (3,4,10,7,0),	0,		AARCH64_FEATURE (MPAMv2))
-  SYSREG ("mpamvidsr_el2",	CPENC (3,4,10,7,1),	0,		AARCH64_FEATURE (MPAMv2))
-  SYSREG ("mpamvidsr_el3",	CPENC (3,6,10,7,1),	0,		AARCH64_FEATURE (MPAMv2))
+  SYSREG ("mpamvidcr_el2",	CPENC (3,4,10,7,0),	F_DEPRECATED,	AARCH64_FEATURE (MPAMv2))
+  SYSREG ("mpamvidsr_el2",	CPENC (3,4,10,7,1),	F_DEPRECATED,	AARCH64_FEATURE (MPAMv2))
+  SYSREG ("mpamvidsr_el3",	CPENC (3,6,10,7,1),	F_DEPRECATED,	AARCH64_FEATURE (MPAMv2))
   SYSREG ("mpamvpm0_el2",	CPENC (3,4,10,6,0),	0,		AARCH64_FEATURE (V8_2A)) /* MPAM */
   SYSREG ("mpamvpm1_el2",	CPENC (3,4,10,6,1),	0,		AARCH64_FEATURE (V8_2A)) /* MPAM */
   SYSREG ("mpamvpm2_el2",	CPENC (3,4,10,6,2),	0,		AARCH64_FEATURE (V8_2A)) /* MPAM */
-- 
2.43.0


From alice.carlotti@arm.com  Fri Jun 26 15:41:09 2026
From: alice.carlotti@arm.com (Alice Carlotti)
Date: Fri, 26 Jun 2026 16:41:09 +0100
Subject: [PATCH v2 1/3] aarch64: Remove a stray comment from
 opcode/aarch64.h
In-Reply-To: <20260626133516.1904430-2-rearnsha@arm.com>
References: <20260626133516.1904430-1-rearnsha@arm.com>
 <20260626133516.1904430-2-rearnsha@arm.com>
Message-ID: <0f58bb35-352f-99bd-5dad-0ab24510a16b@e124511.cambridge.arm.com>

On Fri, Jun 26, 2026 at 02:35:14PM +0100, Richard Earnshaw wrote:
> When flag bit 28 was removed in an earlier patch, the comment describing
> it was left behind.  This just cleans that up.
> ---
>  include/opcode/aarch64.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
> index 6d1b414444a..f51045210c9 100644
> --- a/include/opcode/aarch64.h
> +++ b/include/opcode/aarch64.h
> @@ -1479,7 +1479,7 @@ extern const aarch64_opcode aarch64_opcode_table[];
>  #define F_OD(X) (((X) & 0x7) << 24)
>  /* Instruction has the field of 'sz'.  */
>  #define F_LSE_SZ (1 << 27)
> -/* Require an exact qualifier match, even for NIL qualifiers.  */
> +
>  
>  #define F_SYS_READ (1ULL << 29)
>  /* This system instruction is used to write system registers.  */
> -- 
> 2.43.0
> 

The extra blank line looks unnecessary to me, but you'll be touching this again
in the next patch anyway.  Ignoring that nit, this patch is obviously ok -
thanks for fixing my earlier mistake.

Alice

From alice.carlotti@arm.com  Fri Jun 26 15:45:54 2026
From: alice.carlotti@arm.com (Alice Carlotti)
Date: Fri, 26 Jun 2026 16:45:54 +0100
Subject: [PATCH v2 3/3] aarch64: deprecate mpamv2_vid sysregs
In-Reply-To: <20260626133516.1904430-4-rearnsha@arm.com>
References: <20260626133516.1904430-1-rearnsha@arm.com>
 <20260626133516.1904430-4-rearnsha@arm.com>
Message-ID: <45c2510b-ef0a-e521-aa81-ef0628c5fc87@e124511.cambridge.arm.com>

On Fri, Jun 26, 2026 at 02:35:16PM +0100, Richard Earnshaw wrote:
> These registers were never implemented in any products and have been
> withdrawn from the architecture.  Mark the registers as deprecated
> and update the testsuite accordingly.

This was only added in the previous Binutils release, so I think we can avoid
marking stuff as deprecated and just delete it.  I also discussed with the LLVM
team that we wouldn't have created the +mpamv2 flag without the presence of the
corresponding system instructions (which this patch doesn't address at all),
and we agreed that we should remove that flag as well.

Alice

> ---
>  gas/NEWS                                          |  7 ++++---
>  gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.l | 12 ++++++++++++
>  .../gas/aarch64/sysreg/mpamv2_vid-depr.l          |  7 +++++++
>  gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.d     | 15 ++++++++-------
>  opcodes/aarch64-sys-regs.def                      |  6 +++---
>  5 files changed, 34 insertions(+), 13 deletions(-)
>  create mode 100644 gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-depr.l
> 
> diff --git a/gas/NEWS b/gas/NEWS
> index 116d5e62be6..62c28932189 100644
> --- a/gas/NEWS
> +++ b/gas/NEWS
> @@ -1,8 +1,9 @@
>  -*- text -*-
>  
> -* The aarch64 TME extension has never been implemented in any products.  Arm
> -  has withdrawn it from the architecture.  The assembler will now warn if
> -  instructions from the extension are detected during assembly.
> +* The aarch64 extensions TME and MPAMv2_VID have never been implemented in any
> +  products.  Arm has withdrawn them from the architecture.  The assembler will
> +  now warn if instructions or system registers from either extension are
> +  detected during assembly.
>  
>  * The legacy .vtable_entry and .vtable_inherit directives that were
>    needed for versions of GCC prior to gcc-3.0 (when the generic C++
> diff --git a/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.l b/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.l
> index 6ab3d16fba0..a61ec858e73 100644
> --- a/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.l
> +++ b/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.l
> @@ -1,13 +1,25 @@
>  .*: Assembler messages:
>  .*: Error: selected processor does not support system register name 'mpamvidcr_el2'
>  .*:  Info: macro invoked from here
> +.*: Warning: system register name 'mpamvidcr_el2' is deprecated and may be removed in a future release
> +.*:  Info: macro invoked from here
>  .*: Error: selected processor does not support system register name 'mpamvidcr_el2'
>  .*:  Info: macro invoked from here
> +.*: Warning: system register name 'mpamvidcr_el2' is deprecated and may be removed in a future release
> +.*:  Info: macro invoked from here
>  .*: Error: selected processor does not support system register name 'mpamvidsr_el2'
>  .*:  Info: macro invoked from here
> +.*: Warning: system register name 'mpamvidsr_el2' is deprecated and may be removed in a future release
> +.*:  Info: macro invoked from here
>  .*: Error: selected processor does not support system register name 'mpamvidsr_el2'
>  .*:  Info: macro invoked from here
> +.*: Warning: system register name 'mpamvidsr_el2' is deprecated and may be removed in a future release
> +.*:  Info: macro invoked from here
>  .*: Error: selected processor does not support system register name 'mpamvidsr_el3'
>  .*:  Info: macro invoked from here
> +.*: Warning: system register name 'mpamvidsr_el3' is deprecated and may be removed in a future release
> +.*:  Info: macro invoked from here
>  .*: Error: selected processor does not support system register name 'mpamvidsr_el3'
>  .*:  Info: macro invoked from here
> +.*: Warning: system register name 'mpamvidsr_el3' is deprecated and may be removed in a future release
> +.*:  Info: macro invoked from here
> diff --git a/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-depr.l b/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-depr.l
> new file mode 100644
> index 00000000000..6fc9b23b70b
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-depr.l
> @@ -0,0 +1,7 @@
> +.*: Assembler messages:
> +.*: Warning: system register name 'mpamvidcr_el2' is deprecated and may be removed in a future release
> +.*: Warning: system register name 'mpamvidcr_el2' is deprecated and may be removed in a future release
> +.*: Warning: system register name 'mpamvidsr_el2' is deprecated and may be removed in a future release
> +.*: Warning: system register name 'mpamvidsr_el2' is deprecated and may be removed in a future release
> +.*: Warning: system register name 'mpamvidsr_el3' is deprecated and may be removed in a future release
> +.*: Warning: system register name 'mpamvidsr_el3' is deprecated and may be removed in a future release
> diff --git a/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.d b/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.d
> index 88c0c1883d8..1399d095d54 100644
> --- a/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.d
> +++ b/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.d
> @@ -1,4 +1,5 @@
> -#as: -menable-sysreg-checking -march=armv8-a+mpamv2 -I$srcdir/$subdir
> +#as: -menable-sysreg-checking -march=armv8-a+mpamv2 -I$srcdir/$subdir --no-info
> +#warning_output: mpamv2_vid-depr.l
>  #objdump: -dr
>  
>  .*:     file format .*
> @@ -6,9 +7,9 @@
>  Disassembly of section \.text:
>  
>  0+ <.*>:
> -.*:	d51ca700 	msr	mpamvidcr_el2, x0
> -.*:	d53ca700 	mrs	x0, mpamvidcr_el2
> -.*:	d51ca720 	msr	mpamvidsr_el2, x0
> -.*:	d53ca720 	mrs	x0, mpamvidsr_el2
> -.*:	d51ea720 	msr	mpamvidsr_el3, x0
> -.*:	d53ea720 	mrs	x0, mpamvidsr_el3
> +.*:	d51ca700 	msr	s3_4_c10_c7_0, x0
> +.*:	d53ca700 	mrs	x0, s3_4_c10_c7_0
> +.*:	d51ca720 	msr	s3_4_c10_c7_1, x0
> +.*:	d53ca720 	mrs	x0, s3_4_c10_c7_1
> +.*:	d51ea720 	msr	s3_6_c10_c7_1, x0
> +.*:	d53ea720 	mrs	x0, s3_6_c10_c7_1
> diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
> index 9daa178ed7b..e8eee8a7c66 100644
> --- a/opcodes/aarch64-sys-regs.def
> +++ b/opcodes/aarch64-sys-regs.def
> @@ -929,9 +929,9 @@
>    SYSREG ("mpamhcr_el2",	CPENC (3,4,10,4,0),	0,		AARCH64_FEATURE (V8_2A)) /* MPAM */
>    SYSREG ("mpamidr_el1",	CPENC (3,0,10,4,4),	F_REG_READ,	AARCH64_FEATURE (V8_2A)) /* MPAM */
>    SYSREG ("mpamsm_el1",		CPENC (3,0,10,5,3),	0,		AARCH64_FEATURES (2, SME, V8_2A)) /* SME && MPAM */
> -  SYSREG ("mpamvidcr_el2",	CPENC (3,4,10,7,0),	0,		AARCH64_FEATURE (MPAMv2))
> -  SYSREG ("mpamvidsr_el2",	CPENC (3,4,10,7,1),	0,		AARCH64_FEATURE (MPAMv2))
> -  SYSREG ("mpamvidsr_el3",	CPENC (3,6,10,7,1),	0,		AARCH64_FEATURE (MPAMv2))
> +  SYSREG ("mpamvidcr_el2",	CPENC (3,4,10,7,0),	F_DEPRECATED,	AARCH64_FEATURE (MPAMv2))
> +  SYSREG ("mpamvidsr_el2",	CPENC (3,4,10,7,1),	F_DEPRECATED,	AARCH64_FEATURE (MPAMv2))
> +  SYSREG ("mpamvidsr_el3",	CPENC (3,6,10,7,1),	F_DEPRECATED,	AARCH64_FEATURE (MPAMv2))
>    SYSREG ("mpamvpm0_el2",	CPENC (3,4,10,6,0),	0,		AARCH64_FEATURE (V8_2A)) /* MPAM */
>    SYSREG ("mpamvpm1_el2",	CPENC (3,4,10,6,1),	0,		AARCH64_FEATURE (V8_2A)) /* MPAM */
>    SYSREG ("mpamvpm2_el2",	CPENC (3,4,10,6,2),	0,		AARCH64_FEATURE (V8_2A)) /* MPAM */
> -- 
> 2.43.0
> 

From alice.carlotti@arm.com  Fri Jun 26 15:54:28 2026
From: alice.carlotti@arm.com (Alice Carlotti)
Date: Fri, 26 Jun 2026 16:54:28 +0100
Subject: [PATCH v2 2/3] aarch64: warn if the TME feature is used during
 assembly.
In-Reply-To: <20260626133516.1904430-3-rearnsha@arm.com>
References: <20260626133516.1904430-1-rearnsha@arm.com>
 <20260626133516.1904430-3-rearnsha@arm.com>
Message-ID: <15d29e84-0c9b-c2d6-bb8c-feef3be9aa0c@e124511.cambridge.arm.com>

On Fri, Jun 26, 2026 at 02:35:15PM +0100, Richard Earnshaw wrote:
> Arm has obsoleted the unimplemented TME feature.  Warn if instructions
> from this feature are encountered.

We could only use these instruction in assembly if we specify the +tme
extension, and if we're deprecating the instructions then we should deprecate
the flag as well.  So I think it would be better to emit the deprecation
warning when parsing the "+tme" extension (and we need only warn about this
once).

Alice

> 
> Also tweak warn_unpredictable_ldst to use const more often, since the
> arguments are the same as for the new warn_deprecated function.
> ---
>  gas/NEWS                             |  4 ++++
>  gas/config/tc-aarch64.c              | 24 ++++++++++++++++++++++--
>  gas/testsuite/gas/aarch64/tme-warn.l | 15 +++++++++++++++
>  gas/testsuite/gas/aarch64/tme.d      |  1 +
>  include/opcode/aarch64.h             |  6 ++++--
>  opcodes/aarch64-tbl.h                | 10 +++++-----
>  6 files changed, 51 insertions(+), 9 deletions(-)
>  create mode 100644 gas/testsuite/gas/aarch64/tme-warn.l
> 
> diff --git a/gas/NEWS b/gas/NEWS
> index 4c55a544f25..116d5e62be6 100644
> --- a/gas/NEWS
> +++ b/gas/NEWS
> @@ -1,5 +1,9 @@
>  -*- text -*-
>  
> +* The aarch64 TME extension has never been implemented in any products.  Arm
> +  has withdrawn it from the architecture.  The assembler will now warn if
> +  instructions from the extension are detected during assembly.
> +
>  * The legacy .vtable_entry and .vtable_inherit directives that were
>    needed for versions of GCC prior to gcc-3.0 (when the generic C++
>    ABI was adopted) are now considered obsolete.  They are now deprecated
> diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
> index 9632a5b2a01..587c3588b09 100644
> --- a/gas/config/tc-aarch64.c
> +++ b/gas/config/tc-aarch64.c
> @@ -8743,9 +8743,9 @@ programmer_friendly_fixup (aarch64_instruction *instr)
>  /* Check for loads and stores that will cause unpredictable behavior.  */
>  
>  static void
> -warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
> +warn_unpredictable_ldst (const aarch64_instruction *instr, const char *str)
>  {
> -  aarch64_inst *base = &instr->base;
> +  const aarch64_inst *base = &instr->base;
>    const aarch64_opcode *opcode = base->opcode;
>    const aarch64_opnd_info *opnds = base->operands;
>    switch (opcode->iclass)
> @@ -8841,6 +8841,25 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
>      }
>  }
>  
> +static void
> +warn_deprecated (const aarch64_instruction *instr, const char *str)
> +{
> +  const aarch64_inst *base = &instr->base;
> +  const aarch64_opcode *opcode = base->opcode;
> +  if (!(opcode->flags & F_DEPRECATED_INSN))
> +    return;
> +  switch (opcode->iclass)
> +    {
> +    case tme:
> +      as_warn (_("the TME feature has been deprecated -- `%s'"), str);
> +      break;
> +    default:
> +      /* Instruction marked as deprecated, but a suitable warning not
> +	 added above.  */
> +      abort();
> +    }
> +}
> +
>  static void
>  force_automatic_sequence_close (void)
>  {
> @@ -9019,6 +9038,7 @@ md_assemble (char *str)
>  	    }
>  
>  	  warn_unpredictable_ldst (&inst, str);
> +	  warn_deprecated (&inst, str);
>  
>  	  if (inst.reloc.type == BFD_RELOC_UNUSED
>  	      || !inst.reloc.need_libopcodes_p)
> diff --git a/gas/testsuite/gas/aarch64/tme-warn.l b/gas/testsuite/gas/aarch64/tme-warn.l
> new file mode 100644
> index 00000000000..ed26e4ed95c
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/tme-warn.l
> @@ -0,0 +1,15 @@
> +[^:]*: Assembler messages:
> +.*: Warning: the TME feature has been deprecated -- `tstart x0'
> +.*: Warning: the TME feature has been deprecated -- `tstart X0'
> +.*: Warning: the TME feature has been deprecated -- `tstart x15'
> +.*: Warning: the TME feature has been deprecated -- `tstart X15'
> +.*: Warning: the TME feature has been deprecated -- `tstart x30'
> +.*: Warning: the TME feature has been deprecated -- `tstart X30'
> +.*: Warning: the TME feature has been deprecated -- `tcommit'
> +.*: Warning: the TME feature has been deprecated -- `tcommit'
> +.*: Warning: the TME feature has been deprecated -- `ttest x0'
> +.*: Warning: the TME feature has been deprecated -- `ttest X30'
> +.*: Warning: the TME feature has been deprecated -- `tcancel 0'
> +.*: Warning: the TME feature has been deprecated -- `tcancel 65535'
> +.*: Warning: the TME feature has been deprecated -- `tcancel 0xffff'
> +.*: Warning: the TME feature has been deprecated -- `tcancel 0XA'
> diff --git a/gas/testsuite/gas/aarch64/tme.d b/gas/testsuite/gas/aarch64/tme.d
> index 24d34ea9561..66527b03921 100644
> --- a/gas/testsuite/gas/aarch64/tme.d
> +++ b/gas/testsuite/gas/aarch64/tme.d
> @@ -1,4 +1,5 @@
>  #as: -march=armv8-a+tme
> +#warning_output: tme-warn.l
>  #objdump: -dr
>  
>  .* file format .*
> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
> index f51045210c9..2d8514b8e7d 100644
> --- a/include/opcode/aarch64.h
> +++ b/include/opcode/aarch64.h
> @@ -1219,6 +1219,7 @@ enum aarch64_insn_class
>    sve_shift_tsz_bhsd,
>    sve_size_tsz_bhs,
>    testbranch,
> +  tme,
>    cryptosm3,
>    cryptosm4,
>    dotproduct,
> @@ -1479,7 +1480,8 @@ extern const aarch64_opcode aarch64_opcode_table[];
>  #define F_OD(X) (((X) & 0x7) << 24)
>  /* Instruction has the field of 'sz'.  */
>  #define F_LSE_SZ (1 << 27)
> -
> +/* The instruction has been deprecated.  */
> +#define F_DEPRECATED_INSN (1 << 28)
>  
>  #define F_SYS_READ (1ULL << 29)
>  /* This system instruction is used to write system registers.  */
> @@ -1542,7 +1544,7 @@ extern const aarch64_opcode aarch64_opcode_table[];
>  /* As above, plus PN registers.  */
>  #define F_INVALID_IMM_SYMS_3 (3ULL << 42)
>  
> -/* Next bit is 44, and 28 is also unused.  */
> +/* Next bit is 44.  */
>  
>  /* Instruction constraints.  */
>  /* This instruction has a predication constraint on the instruction at PC+4.  */
> diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
> index 518109ecfd6..c6cb5257008 100644
> --- a/opcodes/aarch64-tbl.h
> +++ b/opcodes/aarch64-tbl.h
> @@ -3374,7 +3374,7 @@ static const aarch64_feature_set aarch64_feature_mpamv2 =
>  #define MEMTAG_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
>    { NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
>  #define _TME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
> -  { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
> +  { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1 | F_DEPRECATED_INSN, 0, 0, NULL }
>  #define SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
>    { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
>      FLAGS | F_INVALID_IMM_SYMS_2, 0, TIED, NULL }
> @@ -5154,10 +5154,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =
>    CORE_INSN ("adr",  0x10000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_PCREL21), QL_ADRP, 0),
>    CORE_INSN ("adrp", 0x90000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_ADRP), QL_ADRP, 0),
>    /* TME Instructions.  */
> -  _TME_INSN ("tstart", 0xd5233060, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
> -  _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, 0, 0, OP0 (), QL_0, 0),
> -  _TME_INSN ("ttest", 0xd5233160, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
> -  _TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, 0, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0),
> +  _TME_INSN ("tstart", 0xd5233060, 0xffffffe0, tme, 0, OP1 (Rd), QL_I1X, 0),
> +  _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, tme, 0, OP0 (), QL_0, 0),
> +  _TME_INSN ("ttest", 0xd5233160, 0xffffffe0, tme, 0, OP1 (Rd), QL_I1X, 0),
> +  _TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, tme, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0),
>    /* SME instructions (aliases for MSR <sysreg> operations.  */
>    SME_INSN ("smstart", 0xd503477f, 0xffffffff, sme_start, 0, OP0 (), QL_0, F_SYS_WRITE, 0),
>    SME_INSN ("smstop",  0xd503467f, 0xffffffff, sme_stop,  0, OP0 (), QL_0, F_SYS_WRITE, 0),
> -- 
> 2.43.0
> 

From alice.carlotti@arm.com  Fri Jun 26 19:17:53 2026
From: alice.carlotti@arm.com (Alice Carlotti)
Date: Fri, 26 Jun 2026 20:17:53 +0100
Subject: [PATCH v10 1/1] aarch64: Implement Structured Exception Handling
 (SEH) on AArch64
In-Reply-To: <20260626133013.89140-2-evgeny.karpov@arm.com>
References: <20260626133013.89140-1-evgeny.karpov@arm.com>
 <20260626133013.89140-2-evgeny.karpov@arm.com>
Message-ID: <5333dbca-8260-4a32-f560-f700aaf1100c@e124511.cambridge.arm.com>

On Fri, Jun 26, 2026 at 03:30:13PM +0200, Evgeny Karpov wrote:
> The patch reuses shared helpers for SEH and implements SEH on AArch64.
> The implementation is based on
> (https://learn.microsoft.com/en-us/cpp/build/arm64-exception-handling?view=msvc-170)
> and pdata/xdata SEH records are emitted from md_finish.
> 
> When .pdata/.xdata is emitted, the function size is required.
> Function sizes are calculated as late as possible, and the code segment needs
> to be relaxed to be able to calculate the function sizes.
> 
> Initially, obj_coff_generate_pdata was called in write_object_file.
> Before the change, obj_coff_generate_pdata was used only to validate
> syntax, which was sufficient for that purpose. However, that location
> seems incorrect, as it is too late to emit .pdata/.xdata records
> in the AArch64 case.
> 
> md_finish has been declared for AArch64 and extended with
> seh_aarch64_write_data to emit .pdata/.xdata records after all
> assembly has been completed.
> 
> Signed-off-by: Evgeny Karpov <evgeny@kmaps.co>



> Changes in v10:
> - Rename offset_shift/reg_shift to offset_multiplier/reg_multiplier.
I think you misinterpreted my review - I wanted you to rename the local
variables in seh_aarch64_add_unwind_element:
divided_by -> offset_multipler
regn_divided_by -> reg_multiplier

The offset_shift and reg_shift field names were fine, and the new names are
wrong (because the values are shift amounts, not multipliers).  Please change
the field names back to offset_shift and reg_shift.


>From previous review:
> > > Yes, it makes sense to stop compilation when function size cannot be properly calculated.
> > > It means the assembler has an internal issue and should be fixed.
> > 
> > I think you missed my point - I'm asking whether "the function size has not
> > been evaluated" only happens when func_size < 0, or can it happen with
> > func_size >= 0 as well?
> 
> Yes, something should be wrong if func_size < 0, no need to check if func_size >= 0.

Can you explain why there's no need to check when func_size >= 0?  It looks to
me like we could end up in that case without the function size being fully
evaluated, but I don't really understand what this is checking.


> > > The big endian host should be supported properly by md_number_to_chars that is used
> > > for emitting pdata/xdata records.
> > 
> > That only ensures that the conversion from valueT to bytes-on-disk is handled
> > correctly.  The issue is with the bit-field to valueT conversion - on a
> > big-endian host I think this would pack the bitfields in the wrong order. 
> 
> The description will be extended with text that big endian host has not been validated.
> It will be validated, and a separate patch will be submitted if needed. 

I think deliberately committing code that is broken for a big endian host, and
then testing and fixing it later, is the wrong approach when doing it correctly
is no more complex (and, in my opinion, might be a bit clearer).

> > It would be clearer to use separate variables here, and only combine them into
> > a single header value within seh_aarch64_emit_xdata_record.   We can't do the
> > type-punning anyway, so there's no benefit to putting the values into a struct.
> > This also avoids any ambiguity about whether the short or extended fields
> > should be used for computations in this function.
> 
> This can be done after validating big endian host if needed.

Or just do it now - see below.


>From patch:
> +static void
> +obj_coff_seh_save_reg (const int type)
> +{
> +  gas_assert (type >= 0 && type <= unwind_last_type);
> +
> +  const struct aarch64_unwind_info *info
> +    = aarch64_unwind_code_data + type;
> +
> +  SKIP_WHITESPACE ();
> +
> +  char *symbol_name = NULL;
> +  unsigned reg = -1;
> +
> +  if (info->reg_bits)
> +    {
> +      char name_end = get_symbol_name (&symbol_name);
> +      if (info->reg_type != *symbol_name)
> +	as_bad ("unexpected register name");
> +
> +      reg = atoi (symbol_name + 1);
> +      (void) restore_line_pointer (name_end);
> +
> +      if (!skip_whitespace_and_comma (1))
> +	return;
> +
> +      /* Check that reference registers are not higher than x30.  */

Nit: s/reference/referenced/

> +      if (info->reg_type == 'x' && (reg + (info->reg_pair ? 1 : 0)) > 30)
> +	as_bad (_("unexpected register number"));
> +    }
> +

...
> +static void
> +seh_aarch64_emit_xdata_record (struct seh_aarch64_context *seh_ctx,
> +			       const bool is_fragmented_function,
> +			       const bool is_last_frag,
> +			       const uintptr_t frag_size,
> +			       const uintptr_t fragment_offset,
> +			       const unsigned prologue_size,
> +			       const unsigned prologue_insn_count,
> +			       const unsigned first_fragment_scope,
> +			       const unsigned last_fragment_scope)
> +{
> +  seh_aarch64_xdata_header *header = &seh_ctx->xdata_header;
> +  const seh_aarch64_epilogue_scope *scopes = seh_ctx->epilogue_scopes;
> +
> +  /* Initialize the .xdata record.  */
> +  const uint32_t func_length_encoded = frag_size >> 2;
> +  header->func_length = func_length_encoded;
> +  header->vers = 0;
> +  header->e = 0;
> +  header->code_words = 0;
> +  header->epilogue_count = 0;
> +
> +  header->ext_code_words = 0;
> +  header->ext_epilogue_count = last_fragment_scope
> +				- first_fragment_scope;
> +  header->reserved = 0;
> +
> +  /* Calculate epilogue indexes for the current fragment.  */
> +  unsigned first_epilogue_index = 0;
> +  unsigned last_epilogue_index = 0;
> +  if (!header->ext_epilogue_count)
> +    {
> +      first_epilogue_index = prologue_size;
> +      last_epilogue_index = prologue_size;
> +    }
> +  else
> +    {
> +      const seh_aarch64_epilogue_scope *scope;
> +      scope = scopes + first_fragment_scope;
> +      first_epilogue_index = scope->epilogue_start_index;
> +      last_epilogue_index = seh_ctx->unwind_codes_byte_count;
> +    }
> +
> +  /* Calculate how many unwind bytes will be emitted in .xdata record.  */
> +  unsigned unwind_bytes = prologue_size;
> +
> +  /* Check if current fragment has a phantom prologue.  If yes, then
> +      the unwinding size should be adjusted.  */
> +  const bool has_phantom_prologue = is_fragmented_function && is_last_frag;
This condition is still wrong.


> +  if (has_phantom_prologue && unwind_bytes)
> +    {
> +      /* One more epilogue scope and unwind code are emitted with phantom
> +	  prologue.  */
> +      unwind_bytes += 1;
> +      ++header->ext_epilogue_count;
> +    }
> +
> +  /* Calculate the number of code words with 4-byte alignment.  */
> +  header->ext_code_words = (unwind_bytes + 3) / 4;
> +
> +  /* Check if short or extended header for a .xdata record should be
> +      used.  */
> +  unsigned header_size = 8;
> +  if ((header->ext_code_words != 0 || header->ext_epilogue_count != 0)
> +      && header->ext_code_words < 32
> +      && header->ext_epilogue_count < 32)
> +    {
> +      header_size = 4;
> +      header->code_words = header->ext_code_words;
> +      header->epilogue_count = header->ext_epilogue_count;
> +      if (header->epilogue_count == 1)
> +	{
> +	  header->e = 1;
> +	  if (has_phantom_prologue)
> +	    header->ext_epilogue_count = 0;
This looks wrong - surely the start index is 1 in this case (with unwind code
index 0 being end_c, to indicate the phantom prologue).

> +	  else
> +	    {
> +	      const seh_aarch64_epilogue_scope *scope;
> +	      scope = scopes + first_fragment_scope;
> +	      header->ext_epilogue_count = scope->epilogue_start_index;
> +	    }
> +	}
> +    }
> +
> +  md_number_to_chars (frag_more (header_size), seh_ctx->xdata_header_value,
> +		      header_size);

I think we should just build up the headers manually - this avoids endianess or
other platform-specific issues, and simplifies the code a bit.  So something
like:

+  unsigned code_words = ((unwind_bytes + 3) >> 2);
+
+  /* Compute and emit the xdata record header.  */
+  uint32_t header = frag_size >> 2;
+  if (seh_ctx->has_exception_data)
+    header |= 1 << 20;
+  if (epilogue_count <= 31 && code_words <= 31)
+    {
+      header |= epilogue_count << 22;
+      header |= code_words << 27;
+      md_number_to_chars (frag_more (4), header, 4));
+    }
+  else
+    {
+      md_number_to_chars (frag_more (4), header, 4));
+      uint32_t header2 = epilogue_count | (code_words << 16)
+      md_number_to_chars (frag_more (4), header2, 4));
+    }

This doesn't use the E=1 format (which only saves 4 bytes) - if we wanted to
include that then we'd need to add an initial check for:
+  if (epilogue_count == 1 && code_words <= 31
+      && /* Check epilogue start index <= 31.  */
+      && /* Check epilogue is at the end of the function - this doesn't seem
to be documented, but it's the only sensible way I can see to specify the
offset in this case.  */)

However, I can't see clear documentation for how this works, so it might be
better to ignore the E=1 format for now, and seek clarification before
implementing it.

> +
> +  if (header->ext_epilogue_count && !header->e)
> +    {
> +      seh_aarch64_emit_epilogue_scopes (seh_ctx,
> +					fragment_offset, prologue_size,
> +					first_fragment_scope,
> +					last_fragment_scope,
> +					has_phantom_prologue);
> +      if (has_phantom_prologue)
> +	{
> +	  const uint32_t epilogue_start_index_encoded = 1 << 22;
> +	  const uint32_t epilogue_start_offset_encoded
> +	    = (frag_size - prologue_insn_count * 4) >> 2;
> +	  md_number_to_chars (frag_more (4),
> +			      epilogue_start_index_encoded
> +			      | epilogue_start_offset_encoded, 4);
> +	}
> +    }
> +
> +  if (header->ext_code_words)
> +    seh_aarch64_emit_unwind_codes (seh_ctx, prologue_size, first_epilogue_index,
> +				   last_epilogue_index, has_phantom_prologue);
> +
> +  if (header->x == 1)
> +    {
> +      if (seh_ctx->handler.X_op == O_symbol)
> +	seh_ctx->handler.X_op = O_symbol_rva;
> +
> +      emit_expr (&seh_ctx->handler, 4);
> +
> +      /* Emit the fragment offset.  */
> +      md_number_to_chars (frag_more (4), fragment_offset, 4);
> +
> +      /* Use the same SEH handler data for all fragments.
> +	 The SEH handler data is emitted after the last fragment.  */
> +      expressionS exp;
> +      memset (&exp, 0, sizeof (expressionS));
> +      exp.X_op = O_symbol_rva;
> +      exp.X_add_symbol = seh_ctx->handler_data_xdata_addr;
> +      emit_expr (&exp, 4);
> +    }
> +}
> +
> +static bool
> +seh_function_size (const struct seh_aarch64_context *seh_ctx,
> +		  uintptr_t *size)
> +{
> +  fragS *start_frag, *end_frag;
> +  addressT start_offset, end_offset;
> +  start_frag = symbol_get_frag_and_value (seh_ctx->start_addr, &start_offset);
> +  end_frag = symbol_get_frag_and_value (seh_ctx->end_addr, &end_offset);
> +
> +  intptr_t func_size = end_frag->fr_address + end_offset
> +		       - start_frag->fr_address - start_offset;
> +  if (func_size < 0)
> +    return false;
> +
> +  *size = func_size;
> +  return true;
> +}
> +
> +/* Write out the xdata information for one function.  */
> +static void
> +seh_aarch64_write_function_xdata (struct seh_aarch64_context *seh_ctx)
> +{
> +  if (!seh_ctx->unwind_codes_byte_count)
> +    return;
> +
> +  const segT save_seg = now_seg;
> +  const subsegT save_subseg = now_subseg;
> +
> +  switch_xdata (seh_ctx->subsection, seh_ctx->code_seg);
> +
> +  /* Set 4-byte alignment.  */
> +  frag_align (2, 0, 0);
> +
> +  uintptr_t func_size = 0;
> +  if (!seh_function_size (seh_ctx, &func_size))
> +    {
> +      as_bad (_("the function size for %s has not been evaluated"),
> +	      seh_ctx->func_name);
> +      return;
> +    }
> +
> +  /* The large functions should be split into fragments smaller than 1MB with
> +     4 bytes alignment, based on
> +     "Microsoft ARM64 exception handling, large functions documentation".  */
> +  const unsigned max_frag_size = (1 << 20) - 4;
> +  const bool is_fragmented_function = func_size > max_frag_size;
> +
> +  unsigned prologue_insn_count = 0;
> +  for (unsigned i = 0; i < seh_ctx->unwind_codes_count; ++i)
> +    {
> +      if (seh_ctx->unwind_codes[i].type == unwind_end)
> +	{
> +	  prologue_insn_count = i + 1;
> +	  break;
> +	}
> +    }
> +
> +  unsigned prologue_size = seh_ctx->unwind_codes_byte_count;
> +
> +  seh_aarch64_func_fragment *fragment;
> +  fragment = &seh_ctx->func_fragment;
> +  uintptr_t fragment_offset = 0;
> +  unsigned first_fragment_scope = 0;
> +  unsigned last_fragment_scope = 0;
> +
> +  /* Large functions (>= 1MB) will be split into multiple fragments.
> +     However, it is expected the most of the functions will have only one
> +     fragment.  This loop iterates fragments and emit them.  */
> +  while (true)
> +    {
> +      fragment->xdata_addr = symbol_temp_new_now ();
> +      fragment->offset = fragment_offset;
> +      fragment->next = NULL;
> +
> +      /* Calculate current fragment size.  */
> +      uintptr_t frag_size = func_size - fragment_offset;
> +      if (frag_size > max_frag_size)
> +	frag_size = max_frag_size;
> +
> +      const bool is_last_frag = (fragment_offset + frag_size) == func_size;
This value shouldn't be needed in the function call, so we can just inline this
condition into the loop termination check.

> +
> +      /* If it is a fragmented function, the epilogue range should be calculated
> +	 and will be emitted for the current fragment, otherwise all epilogues
> +	 will be emitted.  */
> +      if (!is_fragmented_function)
> +	last_fragment_scope = seh_ctx->epilogue_scopes_count;
> +      else
> +	{
> +	  first_fragment_scope = last_fragment_scope;
> +	  for (unsigned i = first_fragment_scope;
> +	       i < seh_ctx->epilogue_scopes_count; ++i)
> +	    {
> +	      const seh_aarch64_epilogue_scope *scope
> +		= seh_ctx->epilogue_scopes;
> +	      scope += i;
> +	      if (scope->epilogue_start_offset >= (fragment_offset + frag_size))
> +		break;
> +
> +	      if (scope->epilogue_end_offset >= (fragment_offset + frag_size))
> +		{
> +		  frag_size = scope->epilogue_start_offset - fragment_offset;
> +		  break;
> +		}
> +
> +	      if (scope->epilogue_start_offset >= fragment_offset)
> +		last_fragment_scope = i + 1;
> +	    }
> +	}
> +
> +
> +      /* Emit a .xdata record for the current fragment.  */
> +      seh_aarch64_emit_xdata_record (seh_ctx, is_fragmented_function,
> +				     is_last_frag, frag_size, fragment_offset,
> +				     prologue_size, prologue_insn_count,
> +				     first_fragment_scope, last_fragment_scope);
> +
> +      fragment_offset += frag_size;
> +      /* Exit the loop if it is the latest fragment.  */
> +      if (is_last_frag)
> +	break;
> +
> +      /* Allocate a new fragment that will be used also for emitting a .pdata
> +	 record.  */
> +      fragment->next = XCNEW (seh_aarch64_func_fragment);
> +      fragment = fragment->next;
> +    }
> +
> +  subseg_set (save_seg, save_subseg);
> +}

...

> +typedef struct seh_aarch64_context
> +{
> +  struct seh_aarch64_context *next;
> +
> +  /* Initial code-segment.  */
> +  segT code_seg;
> +  /* Function name.  */
> +  char *func_name;
> +  /* BeginAddress.  */
> +  symbolS *start_addr;
> +  /* EndAddress.  */
> +  symbolS *end_addr;
> +  /* PrologueEnd.  */
> +  symbolS *endprologue_addr;
> +
> +  symbolS *handler_data_xdata_addr;
> +  /* ExceptionHandler.  */
> +  expressionS handler;
> +  /* ExceptionHandlerData.  */
> +  expressionS handler_data;
> +
> +  subsegT subsection;
> +
> +  union {
> +    seh_aarch64_xdata_header xdata_header;
> +    valueT xdata_header_value;
> +  };
The only header field that is now used outside of seh_aarch64_emit_xdata_record
is xdata_header->x.  Please replace this union with a single boolean value
seh_ctx_cur->has_exception_data (or some similar name).  We can keep details
of the header layout contained to the single function that writes those other
fields.

> +  unsigned unwind_codes_count;
> +  unsigned unwind_codes_byte_count;
> +  seh_aarch64_unwind_code unwind_codes[AARCH64_MAX_UNWIND_CODES];
> +  unsigned epilogue_scopes_count;
> +  unsigned epilogue_scopes_capacity;
> +  seh_aarch64_epilogue_scope *epilogue_scopes;
> +  /* The function fragments.  */
> +  seh_aarch64_func_fragment func_fragment;
> +} seh_context;


From Ganesh.Gopalasubramanian@amd.com  Sat Jun 27 09:55:40 2026
From: Ganesh.Gopalasubramanian@amd.com (Ganesh Gopalasubramanian)
Date: Sat, 27 Jun 2026 15:25:40 +0530
Subject: [PATCH v1 0/2] Support AVX10_V2_AUX and x86 ACE ISA
Message-ID: <20260627095543.1627012-1-Ganesh.Gopalasubramanian@amd.com>

This series adds assembler and disassembler support for two new x86
instruction set extensions described in the AI Compute Extensions (ACE)
Specification, v1.15:

  https://x86ecosystem.org/wp-content/uploads/2026/06/ACE_v1_Specification_public_1_15.pdf

Patch 1 adds the AVX10_V2_AUX instructions.  The AVX10_V1_AUX subset is
already present as part of AVX10.2 and is simply re-exposed under a new
CPUID bit, while AVX10_V2_AUX introduces genuinely new instructions.

Patch 2 adds the x86 ACE ISA: tile, block scale register, outer product,
and MX FP8/INT8/BF16 instructions, all enumerated under a single ACE
feature flag (CPUID.(EAX=07H,ECX=1):ECX[11]).

Both patches include NEWS entries, documentation updates, regenerated
opcode tables, and gas testsuite coverage in both AT&T and Intel syntax.

Ganesh Gopalasubramanian (2):
  Support AVX10_V2_AUX instructions
  Support x86 ACE ISA

 gas/NEWS                                      |     7 +
 gas/config/tc-i386.c                          |    53 +-
 gas/doc/c-i386.texi                           |     6 +-
 gas/testsuite/gas/i386/x86-64-ace-intel.d     |    43 +
 gas/testsuite/gas/i386/x86-64-ace.d           |    43 +
 gas/testsuite/gas/i386/x86-64-ace.s           |    45 +
 .../gas/i386/x86-64-avx10_v2_aux-intel.d      |   116 +
 gas/testsuite/gas/i386/x86-64-avx10_v2_aux.d  |   116 +
 gas/testsuite/gas/i386/x86-64-avx10_v2_aux.s  |   149 +
 gas/testsuite/gas/i386/x86-64.exp             |     4 +
 opcodes/i386-dis-evex-len.h                   |    13 +
 opcodes/i386-dis-evex-prefix.h                |   109 +
 opcodes/i386-dis-evex-w.h                     |    39 +-
 opcodes/i386-dis-evex.h                       |    36 +-
 opcodes/i386-dis.c                            |   129 +-
 opcodes/i386-gen.c                            |     7 +
 opcodes/i386-init.h                           |   834 +-
 opcodes/i386-mnem.h                           |  4194 ++--
 opcodes/i386-opc.h                            |     7 +
 opcodes/i386-opc.tbl                          |   157 +-
 opcodes/i386-reg.tbl                          |     4 +-
 opcodes/i386-tbl.h                            | 19347 ++++++++--------
 22 files changed, 13733 insertions(+), 11725 deletions(-)
 create mode 100644 gas/testsuite/gas/i386/x86-64-ace-intel.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-ace.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-ace.s
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx10_v2_aux-intel.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx10_v2_aux.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx10_v2_aux.s

-- 
2.53.0


From Ganesh.Gopalasubramanian@amd.com  Sat Jun 27 09:55:41 2026
From: Ganesh.Gopalasubramanian@amd.com (Ganesh Gopalasubramanian)
Date: Sat, 27 Jun 2026 15:25:41 +0530
Subject: [PATCH v1 1/2] Support AVX10_V2_AUX instructions
In-Reply-To: <20260627095543.1627012-1-Ganesh.Gopalasubramanian@amd.com>
References: <20260627095543.1627012-1-Ganesh.Gopalasubramanian@amd.com>
Message-ID: <20260627095543.1627012-2-Ganesh.Gopalasubramanian@amd.com>

- AVX10_V1_AUX instructions are already present as part of AVX10.2
instructions. They are just available under new cpuid bit.
- AVX10_V2_AUX are new x86 instructions.

Reference: AI Compute Extensions (ACE) Specification, v1.15
https://x86ecosystem.org/wp-content/uploads/2026/06/ACE_v1_Specification_public_1_15.pdf

Co-authored-by: Umesh Kalvakuntla
---
 gas/NEWS                                      |    3 +
 gas/config/tc-i386.c                          |    1 +
 gas/doc/c-i386.texi                           |    3 +-
 .../gas/i386/x86-64-avx10_v2_aux-intel.d      |  116 +
 gas/testsuite/gas/i386/x86-64-avx10_v2_aux.d  |  116 +
 gas/testsuite/gas/i386/x86-64-avx10_v2_aux.s  |  149 +
 gas/testsuite/gas/i386/x86-64.exp             |    2 +
 opcodes/i386-dis-evex-prefix.h                |   52 +
 opcodes/i386-dis-evex-w.h                     |   20 +
 opcodes/i386-dis-evex.h                       |   22 +-
 opcodes/i386-dis.c                            |   14 +
 opcodes/i386-gen.c                            |    3 +
 opcodes/i386-init.h                           |  812 ++--
 opcodes/i386-mnem.h                           | 4179 +++++++++--------
 opcodes/i386-opc.h                            |    3 +
 opcodes/i386-opc.tbl                          |   89 +
 opcodes/i386-tbl.h                            |  622 ++-
 17 files changed, 3719 insertions(+), 2487 deletions(-)
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx10_v2_aux-intel.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx10_v2_aux.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-avx10_v2_aux.s

diff --git a/gas/NEWS b/gas/NEWS
index 4c55a544f25..ef4bd048e4b 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,8 @@
 -*- text -*-
 
+* Add support for the x86 AVX10_V2_AUX instructions, providing FP8, FP4
+  and FP6 format conversion instructions.
+
 * The legacy .vtable_entry and .vtable_inherit directives that were
   needed for versions of GCC prior to gcc-3.0 (when the generic C++
   ABI was adopted) are now considered obsolete.  They are now deprecated
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 9b3f527d2c1..d82ed061a78 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1253,6 +1253,7 @@ static const arch_entry cpu_arch[] =
   SUBARCH (apx_nf, APX_NF, ANY_APX_NF, false),
   SUBARCH (apx_nci_ndd_nf, APX_NCI_NDD_NF, ANY_APX_NCI_NDD_NF, false),
   VECARCH (avx10.2, AVX10_2, ANY_AVX10_2, set),
+  VECARCH (avx10_v2_aux, AVX10_V2_AUX, ANY_AVX10_V2_AUX, set),
   SUBARCH (gmism2, GMISM2, GMISM2, false),
   SUBARCH (gmiccs, GMICCS, GMICCS, false),
   SUBARCH (msr_imm, MSR_IMM, MSR_IMM, false),
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index b25a4fbc70e..9f6e8da443d 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -230,6 +230,7 @@ accept various extension mnemonics.  For example,
 @code{avx10.2/512},
 @code{avx10.2/256},
 @code{avx10.2/128},
+@code{avx10_v2_aux},
 @code{movrs},
 @code{amx_int8},
 @code{amx_bf16},
@@ -1723,7 +1724,7 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs}
 @item @samp{.avx_vnni_int16} @tab @samp{.sha512} @tab @samp{.sm3} @tab @samp{.sm4}
 @item @samp{.pbndkb} @tab @samp{.user_msr} @tab @samp{.msr_imm} @tab @samp{.avx10.2}
-@item @samp{.movrs}
+@item @samp{.avx10_v2_aux} @tab @samp{.movrs}
 @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
 @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
diff --git a/gas/testsuite/gas/i386/x86-64-avx10_v2_aux-intel.d b/gas/testsuite/gas/i386/x86-64-avx10_v2_aux-intel.d
new file mode 100644
index 00000000000..bd80ca77107
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx10_v2_aux-intel.d
@@ -0,0 +1,116 @@
+#as: -march=+avx10_v2_aux
+#objdump: -dw -Mintel
+#name: x86-64 AVX10_V2_AUX (Intel disassembly)
+#source: x86-64-avx10_v2_aux.s
+
+.*: +file format .*
+
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 08 39 c1[ 	]*vcvtps2bf8 xmm0,xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 28 39 c1[ 	]*vcvtps2bf8 xmm0,ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 48 39 c1[ 	]*vcvtps2bf8 xmm0,zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 08 39 01[ 	]*vcvtps2bf8 xmm0,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 08 39 41 01[ 	]*vcvtps2bf8 xmm0,XMMWORD PTR \[rcx\+0x10\]
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 09 39 c1[ 	]*vcvtps2bf8 xmm0\{k1\},xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 89 39 c1[ 	]*vcvtps2bf8 xmm0\{k1\}\{z\},xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 08 3b c1[ 	]*vcvtps2bf8s xmm0,xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 28 3b c1[ 	]*vcvtps2bf8s xmm0,ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 48 3b c1[ 	]*vcvtps2bf8s xmm0,zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 08 3b 01[ 	]*vcvtps2bf8s xmm0,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 09 3b c1[ 	]*vcvtps2bf8s xmm0\{k1\},xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 08 38 c1[ 	]*vcvtps2hf8 xmm0,xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 28 38 c1[ 	]*vcvtps2hf8 xmm0,ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 48 38 c1[ 	]*vcvtps2hf8 xmm0,zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 08 38 01[ 	]*vcvtps2hf8 xmm0,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 09 38 c1[ 	]*vcvtps2hf8 xmm0\{k1\},xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 08 3a c1[ 	]*vcvtps2hf8s xmm0,xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 28 3a c1[ 	]*vcvtps2hf8s xmm0,ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 48 3a c1[ 	]*vcvtps2hf8s xmm0,zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 08 3a 01[ 	]*vcvtps2hf8s xmm0,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 09 3a c1[ 	]*vcvtps2hf8s xmm0\{k1\},xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 08 38 c1[ 	]*vcvtrops2hf8 xmm0,xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 28 38 c1[ 	]*vcvtrops2hf8 xmm0,ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 48 38 c1[ 	]*vcvtrops2hf8 xmm0,zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 08 38 01[ 	]*vcvtrops2hf8 xmm0,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 09 38 c1[ 	]*vcvtrops2hf8 xmm0\{k1\},xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 08 3a c1[ 	]*vcvtrops2hf8s xmm0,xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 28 3a c1[ 	]*vcvtrops2hf8s xmm0,ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 48 3a c1[ 	]*vcvtrops2hf8s xmm0,zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 08 3a 01[ 	]*vcvtrops2hf8s xmm0,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 09 3a c1[ 	]*vcvtrops2hf8s xmm0\{k1\},xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 08 39 c2[ 	]*vcvtbiasps2bf8 xmm0,xmm1,xmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 28 39 c2[ 	]*vcvtbiasps2bf8 xmm0,ymm1,ymm2
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 48 39 c2[ 	]*vcvtbiasps2bf8 xmm0,zmm1,zmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 08 39 01[ 	]*vcvtbiasps2bf8 xmm0,xmm1,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 09 39 c2[ 	]*vcvtbiasps2bf8 xmm0\{k1\},xmm1,xmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 89 39 c2[ 	]*vcvtbiasps2bf8 xmm0\{k1\}\{z\},xmm1,xmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 08 3b c2[ 	]*vcvtbiasps2bf8s xmm0,xmm1,xmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 28 3b c2[ 	]*vcvtbiasps2bf8s xmm0,ymm1,ymm2
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 48 3b c2[ 	]*vcvtbiasps2bf8s xmm0,zmm1,zmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 08 3b 01[ 	]*vcvtbiasps2bf8s xmm0,xmm1,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 09 3b c2[ 	]*vcvtbiasps2bf8s xmm0\{k1\},xmm1,xmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 08 38 c2[ 	]*vcvtbiasps2hf8 xmm0,xmm1,xmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 28 38 c2[ 	]*vcvtbiasps2hf8 xmm0,ymm1,ymm2
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 48 38 c2[ 	]*vcvtbiasps2hf8 xmm0,zmm1,zmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 08 38 01[ 	]*vcvtbiasps2hf8 xmm0,xmm1,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 09 38 c2[ 	]*vcvtbiasps2hf8 xmm0\{k1\},xmm1,xmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 08 3a c2[ 	]*vcvtbiasps2hf8s xmm0,xmm1,xmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 28 3a c2[ 	]*vcvtbiasps2hf8s xmm0,ymm1,ymm2
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 48 3a c2[ 	]*vcvtbiasps2hf8s xmm0,zmm1,zmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 08 3a 01[ 	]*vcvtbiasps2hf8s xmm0,xmm1,XMMWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 09 3a c2[ 	]*vcvtbiasps2hf8s xmm0\{k1\},xmm1,xmm2
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fc 08 36 c1[ 	]*vcvtbf82ps xmm0,xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fc 28 36 c1[ 	]*vcvtbf82ps ymm0,xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fc 48 36 c1[ 	]*vcvtbf82ps zmm0,xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fc 08 36 01[ 	]*vcvtbf82ps xmm0,DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fc 09 36 c1[ 	]*vcvtbf82ps xmm0\{k1\},xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fc 89 36 c1[ 	]*vcvtbf82ps xmm0\{k1\}\{z\},xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7c 08 36 c1[ 	]*vcvthf82ps xmm0,xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7c 28 36 c1[ 	]*vcvthf82ps ymm0,xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7c 48 36 c1[ 	]*vcvthf82ps zmm0,xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7c 08 36 01[ 	]*vcvthf82ps xmm0,DWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7c 09 36 c1[ 	]*vcvthf82ps xmm0\{k1\},xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fe 08 3d c8[ 	]*vcvtbf82bf4s xmm0,xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fe 28 3d c8[ 	]*vcvtbf82bf4s xmm0,ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fe 48 3d c8[ 	]*vcvtbf82bf4s ymm0,zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fe 08 3d 09[ 	]*vcvtbf82bf4s QWORD PTR \[rcx\],xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 08 3d c8[ 	]*vcvthf82bf4s xmm0,xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 28 3d c8[ 	]*vcvthf82bf4s xmm0,ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 48 3d c8[ 	]*vcvthf82bf4s ymm0,zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 08 3d 09[ 	]*vcvthf82bf4s QWORD PTR \[rcx\],xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fe 08 3e c1[ 	]*vcvtbf82bf6s xmm0,xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fe 28 3e c1[ 	]*vcvtbf82bf6s ymm0,ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fe 48 3e c1[ 	]*vcvtbf82bf6s zmm0,zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 08 3c c1[ 	]*vcvthf82hf6s xmm0,xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 28 3c c1[ 	]*vcvthf82hf6s ymm0,ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 48 3c c1[ 	]*vcvthf82hf6s zmm0,zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7c 08 37 c1[ 	]*vcvtbf42hf8 xmm0,xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7c 28 37 c1[ 	]*vcvtbf42hf8 ymm0,xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7c 48 37 c1[ 	]*vcvtbf42hf8 zmm0,ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7c 08 37 01[ 	]*vcvtbf42hf8 xmm0,QWORD PTR \[rcx\]
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7c 09 37 c1[ 	]*vcvtbf42hf8 xmm0\{k1\},xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7c 89 37 c1[ 	]*vcvtbf42hf8 xmm0\{k1\}\{z\},xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fd 08 37 c1[ 	]*vcvtbf62hf8 xmm0,xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fd 28 37 c1[ 	]*vcvtbf62hf8 ymm0,ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fd 48 37 c1[ 	]*vcvtbf62hf8 zmm0,zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fd 09 37 c1[ 	]*vcvtbf62hf8 xmm0\{k1\},xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fd 89 37 c1[ 	]*vcvtbf62hf8 xmm0\{k1\}\{z\},xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 08 37 c1[ 	]*vcvthf62hf8 xmm0,xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 28 37 c1[ 	]*vcvthf62hf8 ymm0,ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 48 37 c1[ 	]*vcvthf62hf8 zmm0,zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 09 37 c1[ 	]*vcvthf62hf8 xmm0\{k1\},xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7e 08 41 c8[ 	]*vpmovssdb xmm0,xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7e 28 41 c8[ 	]*vpmovssdb xmm0,ymm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7e 48 41 c8[ 	]*vpmovssdb xmm0,zmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7e 08 41 09[ 	]*vpmovssdb DWORD PTR \[rcx\],xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7e 09 41 c8[ 	]*vpmovssdb xmm0\{k1\},xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7e 89 41 c8[ 	]*vpmovssdb xmm0\{k1\}\{z\},xmm1
+[ 	]*[a-f0-9]+:[ 	]*62 f3 7c 08 3d c1 01[ 	]*vunpackb xmm0,xmm1,0x1
+[ 	]*[a-f0-9]+:[ 	]*62 f3 7c 28 3d c1 01[ 	]*vunpackb ymm0,ymm1,0x1
+[ 	]*[a-f0-9]+:[ 	]*62 f3 7c 48 3d c1 01[ 	]*vunpackb zmm0,zmm1,0x1
+[ 	]*[a-f0-9]+:[ 	]*62 f3 7c 08 3d 01 01[ 	]*vunpackb xmm0,XMMWORD PTR \[rcx\],0x1
+[ 	]*[a-f0-9]+:[ 	]*62 f3 7c 09 3d c1 01[ 	]*vunpackb xmm0\{k1\},xmm1,0x1
+[ 	]*[a-f0-9]+:[ 	]*62 f3 7c 89 3d c1 01[ 	]*vunpackb xmm0\{k1\}\{z\},xmm1,0x1
diff --git a/gas/testsuite/gas/i386/x86-64-avx10_v2_aux.d b/gas/testsuite/gas/i386/x86-64-avx10_v2_aux.d
new file mode 100644
index 00000000000..5b78457045d
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx10_v2_aux.d
@@ -0,0 +1,116 @@
+#as: -march=+avx10_v2_aux
+#objdump: -dw -Mx86-64
+#name: x86-64 AVX10_V2_AUX
+
+.*: +file format .*
+
+
+Disassembly of section .text:
+
+0+ <_start>:
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 08 39 c1[ 	]*vcvtps2bf8 %xmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 28 39 c1[ 	]*vcvtps2bf8 %ymm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 48 39 c1[ 	]*vcvtps2bf8 %zmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 08 39 01[ 	]*vcvtps2bf8 \(%rcx\),%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 08 39 41 01[ 	]*vcvtps2bf8 0x10\(%rcx\),%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 09 39 c1[ 	]*vcvtps2bf8 %xmm1,%xmm0\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 89 39 c1[ 	]*vcvtps2bf8 %xmm1,%xmm0\{%k1\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 08 3b c1[ 	]*vcvtps2bf8s %xmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 28 3b c1[ 	]*vcvtps2bf8s %ymm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 48 3b c1[ 	]*vcvtps2bf8s %zmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 08 3b 01[ 	]*vcvtps2bf8s \(%rcx\),%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 09 3b c1[ 	]*vcvtps2bf8s %xmm1,%xmm0\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 08 38 c1[ 	]*vcvtps2hf8 %xmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 28 38 c1[ 	]*vcvtps2hf8 %ymm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 48 38 c1[ 	]*vcvtps2hf8 %zmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 08 38 01[ 	]*vcvtps2hf8 \(%rcx\),%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 09 38 c1[ 	]*vcvtps2hf8 %xmm1,%xmm0\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 08 3a c1[ 	]*vcvtps2hf8s %xmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 28 3a c1[ 	]*vcvtps2hf8s %ymm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 48 3a c1[ 	]*vcvtps2hf8s %zmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 08 3a 01[ 	]*vcvtps2hf8s \(%rcx\),%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 09 3a c1[ 	]*vcvtps2hf8s %xmm1,%xmm0\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 08 38 c1[ 	]*vcvtrops2hf8 %xmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 28 38 c1[ 	]*vcvtrops2hf8 %ymm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 48 38 c1[ 	]*vcvtrops2hf8 %zmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 08 38 01[ 	]*vcvtrops2hf8 \(%rcx\),%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 09 38 c1[ 	]*vcvtrops2hf8 %xmm1,%xmm0\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 08 3a c1[ 	]*vcvtrops2hf8s %xmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 28 3a c1[ 	]*vcvtrops2hf8s %ymm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 48 3a c1[ 	]*vcvtrops2hf8s %zmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 08 3a 01[ 	]*vcvtrops2hf8s \(%rcx\),%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 09 3a c1[ 	]*vcvtrops2hf8s %xmm1,%xmm0\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 08 39 c2[ 	]*vcvtbiasps2bf8 %xmm2,%xmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 28 39 c2[ 	]*vcvtbiasps2bf8 %ymm2,%ymm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 48 39 c2[ 	]*vcvtbiasps2bf8 %zmm2,%zmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 08 39 01[ 	]*vcvtbiasps2bf8 \(%rcx\),%xmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 09 39 c2[ 	]*vcvtbiasps2bf8 %xmm2,%xmm1,%xmm0\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 89 39 c2[ 	]*vcvtbiasps2bf8 %xmm2,%xmm1,%xmm0\{%k1\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 08 3b c2[ 	]*vcvtbiasps2bf8s %xmm2,%xmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 28 3b c2[ 	]*vcvtbiasps2bf8s %ymm2,%ymm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 48 3b c2[ 	]*vcvtbiasps2bf8s %zmm2,%zmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 08 3b 01[ 	]*vcvtbiasps2bf8s \(%rcx\),%xmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 09 3b c2[ 	]*vcvtbiasps2bf8s %xmm2,%xmm1,%xmm0\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 08 38 c2[ 	]*vcvtbiasps2hf8 %xmm2,%xmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 28 38 c2[ 	]*vcvtbiasps2hf8 %ymm2,%ymm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 48 38 c2[ 	]*vcvtbiasps2hf8 %zmm2,%zmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 08 38 01[ 	]*vcvtbiasps2hf8 \(%rcx\),%xmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 09 38 c2[ 	]*vcvtbiasps2hf8 %xmm2,%xmm1,%xmm0\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 08 3a c2[ 	]*vcvtbiasps2hf8s %xmm2,%xmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 28 3a c2[ 	]*vcvtbiasps2hf8s %ymm2,%ymm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 48 3a c2[ 	]*vcvtbiasps2hf8s %zmm2,%zmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 08 3a 01[ 	]*vcvtbiasps2hf8s \(%rcx\),%xmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 74 09 3a c2[ 	]*vcvtbiasps2hf8s %xmm2,%xmm1,%xmm0\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fc 08 36 c1[ 	]*vcvtbf82ps %xmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fc 28 36 c1[ 	]*vcvtbf82ps %xmm1,%ymm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fc 48 36 c1[ 	]*vcvtbf82ps %xmm1,%zmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fc 08 36 01[ 	]*vcvtbf82ps \(%rcx\),%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fc 09 36 c1[ 	]*vcvtbf82ps %xmm1,%xmm0\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fc 89 36 c1[ 	]*vcvtbf82ps %xmm1,%xmm0\{%k1\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7c 08 36 c1[ 	]*vcvthf82ps %xmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7c 28 36 c1[ 	]*vcvthf82ps %xmm1,%ymm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7c 48 36 c1[ 	]*vcvthf82ps %xmm1,%zmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7c 08 36 01[ 	]*vcvthf82ps \(%rcx\),%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7c 09 36 c1[ 	]*vcvthf82ps %xmm1,%xmm0\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fe 08 3d c8[ 	]*vcvtbf82bf4s %xmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fe 28 3d c8[ 	]*vcvtbf82bf4s %ymm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fe 48 3d c8[ 	]*vcvtbf82bf4s %zmm1,%ymm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fe 08 3d 09[ 	]*vcvtbf82bf4s %xmm1,\(%rcx\)
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 08 3d c8[ 	]*vcvthf82bf4s %xmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 28 3d c8[ 	]*vcvthf82bf4s %ymm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 48 3d c8[ 	]*vcvthf82bf4s %zmm1,%ymm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 08 3d 09[ 	]*vcvthf82bf4s %xmm1,\(%rcx\)
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fe 08 3e c1[ 	]*vcvtbf82bf6s %xmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fe 28 3e c1[ 	]*vcvtbf82bf6s %ymm1,%ymm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fe 48 3e c1[ 	]*vcvtbf82bf6s %zmm1,%zmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 08 3c c1[ 	]*vcvthf82hf6s %xmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 28 3c c1[ 	]*vcvthf82hf6s %ymm1,%ymm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7e 48 3c c1[ 	]*vcvthf82hf6s %zmm1,%zmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7c 08 37 c1[ 	]*vcvtbf42hf8 %xmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7c 28 37 c1[ 	]*vcvtbf42hf8 %xmm1,%ymm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7c 48 37 c1[ 	]*vcvtbf42hf8 %ymm1,%zmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7c 08 37 01[ 	]*vcvtbf42hf8 \(%rcx\),%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7c 09 37 c1[ 	]*vcvtbf42hf8 %xmm1,%xmm0\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7c 89 37 c1[ 	]*vcvtbf42hf8 %xmm1,%xmm0\{%k1\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fd 08 37 c1[ 	]*vcvtbf62hf8 %xmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fd 28 37 c1[ 	]*vcvtbf62hf8 %ymm1,%ymm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fd 48 37 c1[ 	]*vcvtbf62hf8 %zmm1,%zmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fd 09 37 c1[ 	]*vcvtbf62hf8 %xmm1,%xmm0\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f5 fd 89 37 c1[ 	]*vcvtbf62hf8 %xmm1,%xmm0\{%k1\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 08 37 c1[ 	]*vcvthf62hf8 %xmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 28 37 c1[ 	]*vcvthf62hf8 %ymm1,%ymm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 48 37 c1[ 	]*vcvthf62hf8 %zmm1,%zmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 09 37 c1[ 	]*vcvthf62hf8 %xmm1,%xmm0\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7e 08 41 c8[ 	]*vpmovssdb %xmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7e 28 41 c8[ 	]*vpmovssdb %ymm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7e 48 41 c8[ 	]*vpmovssdb %zmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7e 08 41 09[ 	]*vpmovssdb %xmm1,\(%rcx\)
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7e 09 41 c8[ 	]*vpmovssdb %xmm1,%xmm0\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f2 7e 89 41 c8[ 	]*vpmovssdb %xmm1,%xmm0\{%k1\}\{z\}
+[ 	]*[a-f0-9]+:[ 	]*62 f3 7c 08 3d c1 01[ 	]*vunpackb \$0x1,%xmm1,%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f3 7c 28 3d c1 01[ 	]*vunpackb \$0x1,%ymm1,%ymm0
+[ 	]*[a-f0-9]+:[ 	]*62 f3 7c 48 3d c1 01[ 	]*vunpackb \$0x1,%zmm1,%zmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f3 7c 08 3d 01 01[ 	]*vunpackb \$0x1,\(%rcx\),%xmm0
+[ 	]*[a-f0-9]+:[ 	]*62 f3 7c 09 3d c1 01[ 	]*vunpackb \$0x1,%xmm1,%xmm0\{%k1\}
+[ 	]*[a-f0-9]+:[ 	]*62 f3 7c 89 3d c1 01[ 	]*vunpackb \$0x1,%xmm1,%xmm0\{%k1\}\{z\}
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-avx10_v2_aux.s b/gas/testsuite/gas/i386/x86-64-avx10_v2_aux.s
new file mode 100644
index 00000000000..24c2901f599
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-avx10_v2_aux.s
@@ -0,0 +1,149 @@
+	.text
+	.arch .avx10_v2_aux
+_start:
+	# VCVTPS2BF8 - F3.MAP5.W0 opcode 39
+	vcvtps2bf8	%xmm1, %xmm0
+	vcvtps2bf8	%ymm1, %xmm0
+	vcvtps2bf8	%zmm1, %xmm0
+	vcvtps2bf8	(%rcx), %xmm0
+	vcvtps2bf8	0x10(%rcx), %xmm0
+	vcvtps2bf8	%xmm1, %xmm0{%k1}
+	vcvtps2bf8	%xmm1, %xmm0{%k1}{z}
+
+	# VCVTPS2BF8S - F3.MAP5.W0 opcode 3B
+	vcvtps2bf8s	%xmm1, %xmm0
+	vcvtps2bf8s	%ymm1, %xmm0
+	vcvtps2bf8s	%zmm1, %xmm0
+	vcvtps2bf8s	(%rcx), %xmm0
+	vcvtps2bf8s	%xmm1, %xmm0{%k1}
+
+	# VCVTPS2HF8 - F3.MAP5.W0 opcode 38
+	vcvtps2hf8	%xmm1, %xmm0
+	vcvtps2hf8	%ymm1, %xmm0
+	vcvtps2hf8	%zmm1, %xmm0
+	vcvtps2hf8	(%rcx), %xmm0
+	vcvtps2hf8	%xmm1, %xmm0{%k1}
+
+	# VCVTPS2HF8S - F3.MAP5.W0 opcode 3A
+	vcvtps2hf8s	%xmm1, %xmm0
+	vcvtps2hf8s	%ymm1, %xmm0
+	vcvtps2hf8s	%zmm1, %xmm0
+	vcvtps2hf8s	(%rcx), %xmm0
+	vcvtps2hf8s	%xmm1, %xmm0{%k1}
+
+	# VCVTROPS2HF8 - 66.MAP5.W0 opcode 38
+	vcvtrops2hf8	%xmm1, %xmm0
+	vcvtrops2hf8	%ymm1, %xmm0
+	vcvtrops2hf8	%zmm1, %xmm0
+	vcvtrops2hf8	(%rcx), %xmm0
+	vcvtrops2hf8	%xmm1, %xmm0{%k1}
+
+	# VCVTROPS2HF8S - 66.MAP5.W0 opcode 3A
+	vcvtrops2hf8s	%xmm1, %xmm0
+	vcvtrops2hf8s	%ymm1, %xmm0
+	vcvtrops2hf8s	%zmm1, %xmm0
+	vcvtrops2hf8s	(%rcx), %xmm0
+	vcvtrops2hf8s	%xmm1, %xmm0{%k1}
+
+	# VCVTBIASPS2BF8 - NP.MAP5.W0 opcode 39
+	vcvtbiasps2bf8	%xmm2, %xmm1, %xmm0
+	vcvtbiasps2bf8	%ymm2, %ymm1, %xmm0
+	vcvtbiasps2bf8	%zmm2, %zmm1, %xmm0
+	vcvtbiasps2bf8	(%rcx), %xmm1, %xmm0
+	vcvtbiasps2bf8	%xmm2, %xmm1, %xmm0{%k1}
+	vcvtbiasps2bf8	%xmm2, %xmm1, %xmm0{%k1}{z}
+
+	# VCVTBIASPS2BF8S - NP.MAP5.W0 opcode 3B
+	vcvtbiasps2bf8s	%xmm2, %xmm1, %xmm0
+	vcvtbiasps2bf8s	%ymm2, %ymm1, %xmm0
+	vcvtbiasps2bf8s	%zmm2, %zmm1, %xmm0
+	vcvtbiasps2bf8s	(%rcx), %xmm1, %xmm0
+	vcvtbiasps2bf8s	%xmm2, %xmm1, %xmm0{%k1}
+
+	# VCVTBIASPS2HF8 - NP.MAP5.W0 opcode 38
+	vcvtbiasps2hf8	%xmm2, %xmm1, %xmm0
+	vcvtbiasps2hf8	%ymm2, %ymm1, %xmm0
+	vcvtbiasps2hf8	%zmm2, %zmm1, %xmm0
+	vcvtbiasps2hf8	(%rcx), %xmm1, %xmm0
+	vcvtbiasps2hf8	%xmm2, %xmm1, %xmm0{%k1}
+
+	# VCVTBIASPS2HF8S - NP.MAP5.W0 opcode 3A
+	vcvtbiasps2hf8s	%xmm2, %xmm1, %xmm0
+	vcvtbiasps2hf8s	%ymm2, %ymm1, %xmm0
+	vcvtbiasps2hf8s	%zmm2, %zmm1, %xmm0
+	vcvtbiasps2hf8s	(%rcx), %xmm1, %xmm0
+	vcvtbiasps2hf8s	%xmm2, %xmm1, %xmm0{%k1}
+
+	# VCVTBF82PS - NP.MAP5.W1 opcode 36
+	vcvtbf82ps	%xmm1, %xmm0
+	vcvtbf82ps	%xmm1, %ymm0
+	vcvtbf82ps	%xmm1, %zmm0
+	vcvtbf82ps	(%rcx), %xmm0
+	vcvtbf82ps	%xmm1, %xmm0{%k1}
+	vcvtbf82ps	%xmm1, %xmm0{%k1}{z}
+
+	# VCVTHF82PS - NP.MAP5.W0 opcode 36
+	vcvthf82ps	%xmm1, %xmm0
+	vcvthf82ps	%xmm1, %ymm0
+	vcvthf82ps	%xmm1, %zmm0
+	vcvthf82ps	(%rcx), %xmm0
+	vcvthf82ps	%xmm1, %xmm0{%k1}
+
+	# VCVTBF82BF4S - F3.MAP5.W1 opcode 3D (no masking)
+	vcvtbf82bf4s	%xmm1, %xmm0
+	vcvtbf82bf4s	%ymm1, %xmm0
+	vcvtbf82bf4s	%zmm1, %ymm0
+	vcvtbf82bf4s	%xmm1, (%rcx)
+
+	# VCVTHF82BF4S - F3.MAP5.W0 opcode 3D (no masking)
+	vcvthf82bf4s	%xmm1, %xmm0
+	vcvthf82bf4s	%ymm1, %xmm0
+	vcvthf82bf4s	%zmm1, %ymm0
+	vcvthf82bf4s	%xmm1, (%rcx)
+
+	# VCVTBF82BF6S - F3.MAP5.W1 opcode 3E (reg-reg only, no masking)
+	vcvtbf82bf6s	%xmm1, %xmm0
+	vcvtbf82bf6s	%ymm1, %ymm0
+	vcvtbf82bf6s	%zmm1, %zmm0
+
+	# VCVTHF82HF6S - F3.MAP5.W0 opcode 3C (reg-reg only, no masking)
+	vcvthf82hf6s	%xmm1, %xmm0
+	vcvthf82hf6s	%ymm1, %ymm0
+	vcvthf82hf6s	%zmm1, %zmm0
+
+	# VCVTBF42HF8 - NP.MAP5.W0 opcode 37
+	vcvtbf42hf8	%xmm1, %xmm0
+	vcvtbf42hf8	%xmm1, %ymm0
+	vcvtbf42hf8	%ymm1, %zmm0
+	vcvtbf42hf8	(%rcx), %xmm0
+	vcvtbf42hf8	%xmm1, %xmm0{%k1}
+	vcvtbf42hf8	%xmm1, %xmm0{%k1}{z}
+
+	# VCVTBF62HF8 - 66.MAP5.W1 opcode 37 (reg-reg only)
+	vcvtbf62hf8	%xmm1, %xmm0
+	vcvtbf62hf8	%ymm1, %ymm0
+	vcvtbf62hf8	%zmm1, %zmm0
+	vcvtbf62hf8	%xmm1, %xmm0{%k1}
+	vcvtbf62hf8	%xmm1, %xmm0{%k1}{z}
+
+	# VCVTHF62HF8 - 66.MAP5.W0 opcode 37 (reg-reg only)
+	vcvthf62hf8	%xmm1, %xmm0
+	vcvthf62hf8	%ymm1, %ymm0
+	vcvthf62hf8	%zmm1, %zmm0
+	vcvthf62hf8	%xmm1, %xmm0{%k1}
+
+	# VPMOVSSDB - F3.0F38.W0 opcode 41
+	vpmovssdb	%xmm1, %xmm0
+	vpmovssdb	%ymm1, %xmm0
+	vpmovssdb	%zmm1, %xmm0
+	vpmovssdb	%xmm1, (%rcx)
+	vpmovssdb	%xmm1, %xmm0{%k1}
+	vpmovssdb	%xmm1, %xmm0{%k1}{z}
+
+	# VUNPACKB - NP.0F3A.W0 opcode 3D
+	vunpackb	$1, %xmm1, %xmm0
+	vunpackb	$1, %ymm1, %ymm0
+	vunpackb	$1, %zmm1, %zmm0
+	vunpackb	$1, (%rcx), %xmm0
+	vunpackb	$1, %xmm1, %xmm0{%k1}
+	vunpackb	$1, %xmm1, %xmm0{%k1}{z}
diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp
index 8ddf05481a5..d0d3cb47117 100644
--- a/gas/testsuite/gas/i386/x86-64.exp
+++ b/gas/testsuite/gas/i386/x86-64.exp
@@ -527,6 +527,8 @@ run_dump_test "x86-64-avx10_2-256-sm4-intel"
 run_dump_test "x86-64-avx10_2-512-sm4"
 run_dump_test "x86-64-avx10_2-512-sm4-intel"
 run_list_test "x86-64-avx10_2-sm4-inval"
+run_dump_test "x86-64-avx10_v2_aux"
+run_dump_test "x86-64-avx10_v2_aux-intel"
 run_dump_test "x86-64-amx-transpose"
 run_dump_test "x86-64-amx-transpose-intel"
 run_list_test "x86-64-amx-transpose-inval"
diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h
index 1aeac210c5d..ffecef5e796 100644
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -243,6 +243,11 @@
     { VEX_W_TABLE (EVEX_W_0F383A_P_1) },
     { "%XEvpminuw",	{ XM, Vex, EXx }, 0 },
   },
+  /* PREFIX_EVEX_0F3841 */
+  {
+    { Bad_Opcode },
+    { "vpmovssdb",	{ EXxmmqd, XM }, 0 },
+  },
   /* PREFIX_EVEX_0F384A_W_0_L_2 */
   {
     { Bad_Opcode },
@@ -614,6 +619,53 @@
     { Bad_Opcode },
     { "vmovrs%BW",	{ XM, Mx }, 0 },
   },
+  /* PREFIX_EVEX_MAP5_36 */
+  {
+    { VEX_W_TABLE (EVEX_W_MAP5_36_P_0) },
+  },
+  /* PREFIX_EVEX_MAP5_37 */
+  {
+    { "vcvtbf42hf8",	{ XM, EXxmmq }, 0 },
+    { Bad_Opcode },
+    { VEX_W_TABLE (EVEX_W_MAP5_37_P_2) },
+  },
+  /* PREFIX_EVEX_MAP5_38 */
+  {
+    { "vcvtbiasps2hf8",	{ XMM, Vex, EXx }, 0 },
+    { "vcvtps2hf8",	{ XMM, EXx }, 0 },
+    { "vcvtrops2hf8",	{ XMM, EXx }, 0 },
+  },
+  /* PREFIX_EVEX_MAP5_39 */
+  {
+    { "vcvtbiasps2bf8",	{ XMM, Vex, EXx }, 0 },
+    { "vcvtps2bf8",	{ XMM, EXx }, 0 },
+  },
+  /* PREFIX_EVEX_MAP5_3A */
+  {
+    { "vcvtbiasps2hf8s",	{ XMM, Vex, EXx }, 0 },
+    { "vcvtps2hf8s",	{ XMM, EXx }, 0 },
+    { "vcvtrops2hf8s",	{ XMM, EXx }, 0 },
+  },
+  /* PREFIX_EVEX_MAP5_3B */
+  {
+    { "vcvtbiasps2bf8s",	{ XMM, Vex, EXx }, 0 },
+    { "vcvtps2bf8s",	{ XMM, EXx }, 0 },
+  },
+  /* PREFIX_EVEX_MAP5_3C */
+  {
+    { Bad_Opcode },
+    { "vcvthf82hf6s",	{ XM, EXx }, 0 },
+  },
+  /* PREFIX_EVEX_MAP5_3D */
+  {
+    { Bad_Opcode },
+    { VEX_W_TABLE (EVEX_W_MAP5_3D_P_1) },
+  },
+  /* PREFIX_EVEX_MAP5_3E */
+  {
+    { Bad_Opcode },
+    { VEX_W_TABLE (EVEX_W_MAP5_3E_P_1) },
+  },
   /* PREFIX_EVEX_MAP5_74 */
   {
     { "vcvtbiasp%XH2bf8s",	{ XMxmmq, Vex, EXxh }, 0 },
diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h
index 310f121f499..6e94bc45fe1 100644
--- a/opcodes/i386-dis-evex-w.h
+++ b/opcodes/i386-dis-evex-w.h
@@ -486,6 +486,26 @@
     { "push2", { { PUSH2_POP2_Fixup, q_mode}, Eq }, 0 },
     { "push2p", { { PUSH2_POP2_Fixup, q_mode}, Eq }, 0 },
   },
+  /* EVEX_W_MAP5_36_P_0 */
+  {
+    { "vcvthf82ps",	{ XM, EXxmmqd }, 0 },
+    { "vcvtbf82ps",	{ XM, EXxmmqd }, 0 },
+  },
+  /* EVEX_W_MAP5_37_P_2 */
+  {
+    { "vcvthf62hf8",	{ XM, EXx }, 0 },
+    { "vcvtbf62hf8",	{ XM, EXx }, 0 },
+  },
+  /* EVEX_W_MAP5_3D_P_1 */
+  {
+    { "vcvthf82bf4s",	{ EXxmmq, XM }, 0 },
+    { "vcvtbf82bf4s",	{ EXxmmq, XM }, 0 },
+  },
+  /* EVEX_W_MAP5_3E_P_1 */
+  {
+    { Bad_Opcode },
+    { "vcvtbf82bf6s",	{ XM, EXx }, 0 },
+  },
   /* EVEX_W_MAP5_5B_P_0 */
   {
     { "vcvtdq2ph%XY",	{ XMxmmq, EXx, EXxEVexR }, 0 },
diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
index b2f02e494f9..7d555aa9e11 100644
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -366,7 +366,7 @@ static const struct dis386 evex_table[][256] = {
     { "%XEvpmaxu%DQ",	{ XM, Vex, EXx }, PREFIX_DATA },
     /* 40 */
     { "%XEvpmull%DQ",	{ XM, Vex, EXx }, PREFIX_DATA },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_EVEX_0F3841) },
     { "vgetexpp%XW",	{ XM, EXx, EXxEVexS }, PREFIX_DATA },
     { "vgetexps%XW",	{ XMScalar, VexScalar, EXdq, EXxEVexS }, PREFIX_DATA },
     { "vplzcnt%DQ",	{ XM, EXx }, PREFIX_DATA },
@@ -652,7 +652,7 @@ static const struct dis386 evex_table[][256] = {
     { EVEX_LEN_TABLE (EVEX_LEN_0F3A3A) },
     { EVEX_LEN_TABLE (EVEX_LEN_0F3A3B) },
     { Bad_Opcode },
-    { Bad_Opcode },
+    { "vunpackb",	{ XM, EXx, Ib }, 0 },
     { "vpcmpu%BW",	{ MaskG, Vex, EXx, VPCMP }, PREFIX_DATA },
     { "vpcmp%BW",	{ MaskG, Vex, EXx, VPCMP }, PREFIX_DATA },
     /* 40 */
@@ -1226,16 +1226,16 @@ static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_EVEX_MAP5_36) },
+    { PREFIX_TABLE (PREFIX_EVEX_MAP5_37) },
     /* 38 */
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_EVEX_MAP5_38) },
+    { PREFIX_TABLE (PREFIX_EVEX_MAP5_39) },
+    { PREFIX_TABLE (PREFIX_EVEX_MAP5_3A) },
+    { PREFIX_TABLE (PREFIX_EVEX_MAP5_3B) },
+    { PREFIX_TABLE (PREFIX_EVEX_MAP5_3C) },
+    { PREFIX_TABLE (PREFIX_EVEX_MAP5_3D) },
+    { PREFIX_TABLE (PREFIX_EVEX_MAP5_3E) },
     { Bad_Opcode },
     /* 40 */
     { Bad_Opcode },
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 749c37e06e6..5643cfe55d5 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1211,6 +1211,7 @@ enum
   PREFIX_EVEX_0F3838,
   PREFIX_EVEX_0F3839,
   PREFIX_EVEX_0F383A,
+  PREFIX_EVEX_0F3841,
   PREFIX_EVEX_0F384A_X86_64_W_0_L_2,
   PREFIX_EVEX_0F3852,
   PREFIX_EVEX_0F3853,
@@ -1272,6 +1273,15 @@ enum
   PREFIX_EVEX_MAP5_6D,
   PREFIX_EVEX_MAP5_6E_L_0,
   PREFIX_EVEX_MAP5_6F_X86_64,
+  PREFIX_EVEX_MAP5_36,
+  PREFIX_EVEX_MAP5_37,
+  PREFIX_EVEX_MAP5_38,
+  PREFIX_EVEX_MAP5_39,
+  PREFIX_EVEX_MAP5_3A,
+  PREFIX_EVEX_MAP5_3B,
+  PREFIX_EVEX_MAP5_3C,
+  PREFIX_EVEX_MAP5_3D,
+  PREFIX_EVEX_MAP5_3E,
   PREFIX_EVEX_MAP5_74,
   PREFIX_EVEX_MAP5_78,
   PREFIX_EVEX_MAP5_79,
@@ -1860,6 +1870,10 @@ enum
   EVEX_W_MAP4_F8_P3_M_1,
   EVEX_W_MAP4_FF_R_6,
 
+  EVEX_W_MAP5_36_P_0,
+  EVEX_W_MAP5_37_P_2,
+  EVEX_W_MAP5_3D_P_1,
+  EVEX_W_MAP5_3E_P_1,
   EVEX_W_MAP5_5B_P_0,
   EVEX_W_MAP5_6C_P_0,
   EVEX_W_MAP5_6C_P_2,
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index be580d48a18..11cc4ff19dc 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -249,6 +249,8 @@ static const dependency isa_dependencies[] =
     "|AVX512_VNNI|AVX512_BF16|AVX512_FP16|AVX512_VPOPCNTDQ|AVX512_BITALG" },
   { "AVX10_2",
     "AVX10_1" },
+  { "AVX10_V2_AUX",
+    "AVX10_2" },
   { "SEV_ES",
     "SVME" },
   { "SNP",
@@ -450,6 +452,7 @@ static bitfield cpu_flags[] =
   BITFIELD (MSR_IMM),
   BITFIELD (APX_F),
   BITFIELD (AVX10_2),
+  BITFIELD (AVX10_V2_AUX),
   BITFIELD (MOVRS),
   BITFIELD (MWAITX),
   BITFIELD (CLZERO),
diff --git a/opcodes/i386-init.h b/opcodes/i386-init.h
index c10928125a7..eb2cc271bb3 100644
--- a/opcodes/i386-init.h
+++ b/opcodes/i386-init.h
@@ -27,7 +27,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_286_FLAGS \
   { { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -38,7 +38,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_386_FLAGS \
   { { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -49,7 +49,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_486_FLAGS \
   { { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -60,7 +60,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_586_FLAGS \
   { { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -70,8 +70,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_686_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
@@ -81,8 +81,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_CMOV_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -93,7 +93,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_FXSR_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -104,7 +104,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_CLFLUSH_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -115,7 +115,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_NOP_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -126,7 +126,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_SYSCALL_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -137,7 +137,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_8087_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -148,7 +148,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_687_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
@@ -158,8 +158,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_FISTTP_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \
@@ -169,8 +169,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_MMX_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
@@ -181,7 +181,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_SSE_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
@@ -192,7 +192,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_SSE2_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \
@@ -203,7 +203,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_SSE3_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -214,7 +214,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_PADLOCK_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
@@ -225,7 +225,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_PADLOCKRNG2_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
@@ -236,7 +236,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_PADLOCKPHE2_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
@@ -247,7 +247,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_PADLOCKXMODX_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
@@ -258,7 +258,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_GMISM2_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -269,7 +269,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_GMICCS_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -280,7 +280,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_SVME_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -291,7 +291,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_VMX_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -302,7 +302,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_SMX_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -313,7 +313,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_SSSE3_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -324,7 +324,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_SSE4A_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -335,7 +335,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_LZCNT_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -346,7 +346,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_POPCNT_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -357,7 +357,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_MONITOR_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -368,7 +368,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_SSE4_1_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -379,7 +379,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_SSE4_2_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -390,7 +390,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AVX2_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -400,8 +400,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AVX512CD_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -411,8 +411,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AVX512ER_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -422,8 +422,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AVX512PF_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -433,8 +433,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AVX512DQ_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -444,8 +444,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AVX512BW_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -455,8 +455,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_IAMCU_FLAGS \
   { { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -467,7 +467,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_XSAVE_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -478,7 +478,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_XSAVEOPT_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -489,7 +489,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AES_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \
@@ -500,7 +500,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_PCLMULQDQ_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \
@@ -511,7 +511,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_FMA_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -521,8 +521,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_FMA4_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -532,8 +532,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_XOP_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -543,8 +543,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_LWP_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -555,7 +555,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_BMI_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -566,7 +566,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_TBM_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -577,7 +577,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_MOVBE_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -588,7 +588,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_CX16_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -599,7 +599,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_LAHF_SAHF_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -610,7 +610,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_EPT_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -621,7 +621,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_RDTSCP_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -632,7 +632,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_FSGSBASE_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -643,7 +643,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_RDRND_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -654,7 +654,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_F16C_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -664,8 +664,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_BMI2_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -676,7 +676,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_RTM_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -687,7 +687,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_INVPCID_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -698,7 +698,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_VMFUNC_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -709,7 +709,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_MPX_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -720,7 +720,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_RDSEED_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -731,7 +731,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ADX_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -742,7 +742,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_PRFCHW_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -753,7 +753,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_SMAP_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -764,7 +764,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_SHA_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \
@@ -775,7 +775,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_SHA512_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -785,8 +785,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_SM3_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -796,8 +796,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_SM4_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -807,8 +807,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_CLFLUSHOPT_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -819,7 +819,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_XSAVES_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -830,7 +830,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_XSAVEC_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -841,7 +841,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_PREFETCHWT1_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -852,7 +852,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_SE1_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -863,7 +863,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_CLWB_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -874,7 +874,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AVX512IFMA_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -884,8 +884,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AVX512VBMI_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -895,8 +895,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AVX512_4FMAPS_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -906,8 +906,8 @@
       1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AVX512_4VNNIW_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -917,8 +917,8 @@
       0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AVX512_VPOPCNTDQ_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -928,8 +928,8 @@
       0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AVX512_VBMI2_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -939,8 +939,8 @@
       0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AVX512_VNNI_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -950,8 +950,8 @@
       0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AVX512_BITALG_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -961,8 +961,8 @@
       0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AVX512_BF16_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -972,8 +972,8 @@
       0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AVX512_VP2INTERSECT_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -983,8 +983,8 @@
       0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AVX512_BMM_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -994,8 +994,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_TDX_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1006,7 +1006,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AVX_VNNI_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -1016,8 +1016,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AVX512_FP16_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -1027,8 +1027,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_PREFETCHI_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1039,7 +1039,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AVX_IFMA_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -1049,8 +1049,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AVX_VNNI_INT8_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -1060,8 +1060,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AVX_VNNI_INT16_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -1071,8 +1071,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_CMPCCXADD_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1083,7 +1083,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_WRMSRNS_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1094,7 +1094,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_MSRLIST_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1105,7 +1105,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AVX_NE_CONVERT_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -1115,8 +1115,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_RAO_INT_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1127,7 +1127,7 @@
       1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_FRED_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1138,7 +1138,7 @@
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_LKGS_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1149,7 +1149,7 @@
       0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_USER_MSR_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1160,7 +1160,7 @@
       0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_MSR_IMM_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1171,7 +1171,7 @@
       0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_MOVRS_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1182,7 +1182,7 @@
       0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_MWAITX_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1193,7 +1193,7 @@
       0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_CLZERO_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1204,7 +1204,7 @@
       0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_OSPKE_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1215,7 +1215,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_RDPID_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1226,7 +1226,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_PTWRITE_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1237,7 +1237,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_IBT_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1248,7 +1248,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_SHSTK_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1259,7 +1259,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AMX_INT8_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1270,7 +1270,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
       0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AMX_BF16_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1281,7 +1281,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
       0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AMX_FP16_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1292,7 +1292,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
       0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AMX_COMPLEX_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1303,7 +1303,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
       0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AMX_TF32_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1314,7 +1314,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
       0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AMX_FP8_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1325,7 +1325,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
       0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AMX_MOVRS_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1336,7 +1336,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
       0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AMX_AVX512_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -1346,8 +1346,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AMX_TILE_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1358,7 +1358,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_GFNI_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \
@@ -1369,7 +1369,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_VAES_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -1379,8 +1379,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_VPCLMULQDQ_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -1390,8 +1390,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_WBNOINVD_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1402,7 +1402,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_PCONFIG_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1413,7 +1413,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_PBNDKB_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1424,7 +1424,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_WAITPKG_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1435,7 +1435,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_UINTR_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1446,7 +1446,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_CLDEMOTE_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1457,7 +1457,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_MOVDIRI_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1468,7 +1468,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_MOVDIR64B_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1479,7 +1479,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ENQCMD_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1490,7 +1490,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_SERIALIZE_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1501,7 +1501,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_RDPRU_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1512,7 +1512,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_MCOMMIT_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1523,7 +1523,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_SEV_ES_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1534,7 +1534,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_TSXLDTRK_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1545,7 +1545,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_KL_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \
@@ -1556,7 +1556,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_WIDEKL_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \
@@ -1567,7 +1567,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
       1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_HRESET_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1578,7 +1578,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_INVLPGB_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1589,7 +1589,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_TLBSYNC_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1600,7 +1600,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_SNP_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1611,7 +1611,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
       0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_RMPQUERY_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1622,7 +1622,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
       0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_RMPREAD_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1633,7 +1633,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
       0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_APX_NCI_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1643,8 +1643,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      1, 0, 0, 0, 0 } }
 
 #define CPU_APX_NDD_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1654,8 +1654,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      1, 0, 0, 0, 0 } }
 
 #define CPU_APX_NF_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1665,8 +1665,19 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      1, 0, 0, 0, 0 } }
+
+#define CPU_AVX10_V2_AUX_FLAGS \
+  { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
+      0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 1, 1, 1, 1, 0, 0, 1, 1, \
+      0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
+      0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, \
+      0, 1, 0, 0, 0 } }
 
 #define CPU_287_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1676,8 +1687,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_387_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1687,8 +1698,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_3DNOW_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
@@ -1698,8 +1709,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_3DNOWA_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
@@ -1709,8 +1720,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AVX_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -1720,8 +1731,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_HLE_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1731,8 +1742,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AVX512F_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -1742,8 +1753,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AVX512VL_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -1753,8 +1764,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_APX_F_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1764,8 +1775,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      1, 0, 0, 0, 0 } }
 
 #define CPU_AVX10_2_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -1775,8 +1786,8 @@
       0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, \
-      1, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, \
+      0, 1, 0, 0, 0 } }
 
 #define CPU_AMX_TRANSPOSE_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1787,7 +1798,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 1, 0, 0 } }
+      0, 0, 1, 0, 0 } }
 
 #define CPU_UNKNOWN_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
@@ -1798,7 +1809,7 @@
       1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
       1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
       1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
-      1, 0, 0, 0 } }
+      1, 1, 0, 0, 0 } }
 
 #define CPU_GENERIC32_FLAGS \
   { { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1809,7 +1820,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_GENERIC64_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 1, 0, 0, 0, \
@@ -1819,8 +1830,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_NONE_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -1831,7 +1842,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_PENTIUMPRO_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
@@ -1841,8 +1852,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_P2_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, \
@@ -1852,8 +1863,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_P3_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 0, 0, \
@@ -1863,8 +1874,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_P4_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 0, 0, 0, \
@@ -1874,8 +1885,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_NOCONA_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
@@ -1885,8 +1896,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_CORE_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
@@ -1896,8 +1907,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_CORE2_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
@@ -1907,8 +1918,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_COREI7_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
@@ -1918,8 +1929,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_K6_FLAGS \
   { { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
@@ -1929,8 +1940,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_K6_2_FLAGS \
   { { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
@@ -1940,8 +1951,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ATHLON_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, \
@@ -1951,8 +1962,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_K8_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, 0, 1, 1, 1, 0, 0, 0, \
@@ -1962,8 +1973,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AMDFAM10_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
@@ -1973,8 +1984,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_BDVER1_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
@@ -1984,8 +1995,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_BDVER2_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
@@ -1995,8 +2006,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_BDVER3_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
@@ -2006,8 +2017,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_BDVER4_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
@@ -2017,8 +2028,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ZNVER1_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
@@ -2028,8 +2039,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ZNVER2_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
@@ -2039,8 +2050,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ZNVER3_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
@@ -2050,8 +2061,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
-      0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ZNVER4_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
@@ -2061,8 +2072,8 @@
       0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
-      0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 1, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 1, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ZNVER5_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
@@ -2072,8 +2083,8 @@
       0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 1, 0, 0, \
-      0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 1, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 1, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ZNVER6_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
@@ -2083,8 +2094,8 @@
       0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, \
       0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 1, 0, 0, \
-      0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 1, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 1, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_BTVER1_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
@@ -2094,8 +2105,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_BTVER2_FLAGS \
   { { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
@@ -2105,8 +2116,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ABM_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2117,7 +2128,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_AVX10_1_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -2127,8 +2138,8 @@
       0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_TSX_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2138,8 +2149,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_APX_NCI_NDD_NF_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2149,8 +2160,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
+      1, 0, 0, 0, 0 } }
 
 #define CPU_ANY_FXSR_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
@@ -2161,7 +2172,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
       1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_8087_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
@@ -2171,8 +2182,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_687_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \
@@ -2183,7 +2194,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_FISTTP_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
@@ -2194,7 +2205,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_MMX_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
@@ -2204,8 +2215,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_SSE_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, \
@@ -2216,7 +2227,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
       1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_SSE2_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \
@@ -2227,7 +2238,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
       1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_SSE3_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
@@ -2238,7 +2249,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_PADLOCK_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
@@ -2249,7 +2260,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_PADLOCKRNG2_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
@@ -2260,7 +2271,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_PADLOCKPHE2_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2271,7 +2282,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_PADLOCKXMODX_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2282,7 +2293,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_SVME_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2293,7 +2304,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
       0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_VMX_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2304,7 +2315,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_SSSE3_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2315,7 +2326,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_SSE4A_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2326,7 +2337,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_SSE4_1_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2337,7 +2348,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_SSE4_2_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2348,7 +2359,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_AVX2_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2358,8 +2369,8 @@
       1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 1, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
-      1, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
+      0, 1, 0, 0, 0 } }
 
 #define CPU_ANY_AVX512CD_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2369,8 +2380,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      1, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      0, 1, 0, 0, 0 } }
 
 #define CPU_ANY_AVX512ER_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2381,7 +2392,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_AVX512PF_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2392,7 +2403,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_AVX512DQ_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2402,8 +2413,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      1, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      0, 1, 0, 0, 0 } }
 
 #define CPU_ANY_AVX512BW_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2413,8 +2424,8 @@
       0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      1, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      0, 1, 0, 0, 0 } }
 
 #define CPU_ANY_IAMCU_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2425,7 +2436,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_XSAVE_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2435,8 +2446,8 @@
       1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 1, \
       0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, \
       1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, \
-      1, 1, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, \
+      1, 1, 1, 0, 0 } }
 
 #define CPU_ANY_XSAVEOPT_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2447,7 +2458,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_AES_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2458,7 +2469,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_PCLMULQDQ_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2469,7 +2480,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_FMA_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2480,7 +2491,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_FMA4_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2491,7 +2502,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_XOP_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2502,7 +2513,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_LWP_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2513,7 +2524,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_EPT_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2524,7 +2535,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_F16C_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2535,7 +2546,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_RTM_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2546,7 +2557,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_VMFUNC_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2557,7 +2568,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_MPX_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2568,7 +2579,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_SHA_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2579,7 +2590,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_SHA512_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2590,7 +2601,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_SM3_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2601,7 +2612,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_SM4_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2612,7 +2623,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_XSAVES_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2623,7 +2634,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_XSAVEC_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2634,7 +2645,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_AVX512IFMA_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2644,8 +2655,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      1, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      0, 1, 0, 0, 0 } }
 
 #define CPU_ANY_AVX512VBMI_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2655,8 +2666,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      1, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      0, 1, 0, 0, 0 } }
 
 #define CPU_ANY_AVX512_4FMAPS_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2667,7 +2678,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_AVX512_4VNNIW_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2678,7 +2689,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_AVX512_VPOPCNTDQ_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2688,8 +2699,8 @@
       0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      1, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      0, 1, 0, 0, 0 } }
 
 #define CPU_ANY_AVX512_VBMI2_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2699,8 +2710,8 @@
       0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      1, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      0, 1, 0, 0, 0 } }
 
 #define CPU_ANY_AVX512_VNNI_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2710,8 +2721,8 @@
       0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      1, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      0, 1, 0, 0, 0 } }
 
 #define CPU_ANY_AVX512_BITALG_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2721,8 +2732,8 @@
       0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      1, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      0, 1, 0, 0, 0 } }
 
 #define CPU_ANY_AVX512_BF16_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2732,8 +2743,8 @@
       0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      1, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      0, 1, 0, 0, 0 } }
 
 #define CPU_ANY_AVX512_VP2INTERSECT_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2744,7 +2755,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_AVX512_BMM_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2755,7 +2766,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_AVX_VNNI_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2766,7 +2777,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_AVX512_FP16_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2776,8 +2787,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      1, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      0, 1, 0, 0, 0 } }
 
 #define CPU_ANY_AVX_IFMA_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2788,7 +2799,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_AVX_VNNI_INT8_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2799,7 +2810,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_AVX_VNNI_INT16_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2810,7 +2821,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_AVX_NE_CONVERT_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2821,7 +2832,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_FRED_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2832,7 +2843,7 @@
       0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_LKGS_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2843,7 +2854,7 @@
       0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_OSPKE_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2854,7 +2865,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_AMX_INT8_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2865,7 +2876,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_AMX_BF16_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2876,7 +2887,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_AMX_FP16_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2887,7 +2898,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_AMX_COMPLEX_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2898,7 +2909,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_AMX_TF32_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2909,7 +2920,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_AMX_FP8_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2920,7 +2931,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_AMX_MOVRS_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2931,7 +2942,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_AMX_AVX512_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2942,7 +2953,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_AMX_TILE_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2953,7 +2964,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, \
       1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 1, 0, 0 } }
+      0, 0, 1, 0, 0 } }
 
 #define CPU_ANY_GFNI_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2964,7 +2975,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_VAES_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2975,7 +2986,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_VPCLMULQDQ_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2986,7 +2997,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_SEV_ES_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -2997,7 +3008,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
       0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_TSXLDTRK_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -3008,7 +3019,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_KL_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -3019,7 +3030,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
       1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_WIDEKL_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -3030,7 +3041,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_SNP_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -3041,7 +3052,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_RMPQUERY_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -3052,7 +3063,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_RMPREAD_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -3063,7 +3074,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_APX_NCI_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -3074,7 +3085,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_APX_NDD_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -3085,7 +3096,7 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_APX_NF_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -3096,7 +3107,18 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0 } }
+
+#define CPU_ANY_AVX10_V2_AUX_FLAGS \
+  { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_287_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \
@@ -3106,8 +3128,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_387_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \
@@ -3117,8 +3139,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_3DNOW_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -3128,8 +3150,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_3DNOWA_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -3139,8 +3161,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
+      0, 0, 0, 0, 0 } }
 
 #define CPU_ANY_64_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -3150,8 +3172,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, \
       0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, \
       1, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
-      0, 1, 0, 0 } }
+      0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      1, 0, 1, 0, 0 } }
 
 #define CPU_ANY_AVX_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -3161,8 +3183,8 @@
       1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 1, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, \
-      1, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, \
+      0, 1, 0, 0, 0 } }
 
 #define CPU_ANY_AVX512F_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -3172,8 +3194,8 @@
       1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
-      1, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
+      0, 1, 0, 0, 0 } }
 
 #define CPU_ANY_AVX512VL_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -3183,8 +3205,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
-      1, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
+      0, 1, 0, 0, 0 } }
 
 #define CPU_ANY_APX_F_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -3194,8 +3216,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
-      0, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      1, 0, 0, 0, 0 } }
 
 #define CPU_ANY_AVX10_2_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -3205,8 +3227,8 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      1, 0, 0, 0 } }
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+      0, 1, 0, 0, 0 } }
 
 #define CPU_ANY_AMX_TRANSPOSE_FLAGS \
   { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
@@ -3217,5 +3239,5 @@
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
-      0, 1, 0, 0 } }
+      0, 0, 1, 0, 0 } }
 
diff --git a/opcodes/i386-mnem.h b/opcodes/i386-mnem.h
index c44849c9984..764928a74a2 100644
--- a/opcodes/i386-mnem.h
+++ b/opcodes/i386-mnem.h
@@ -167,2470 +167,2491 @@ static const char i386_mnemonics[];
 #define MN_vcvt2ph2bf8 0x619
 #define MN_vcvtbiasph2bf8 0x625
 #define MN_vcvtph2bf8 0x634
-#define MN_vcvt2ph2hf8 0x63f
-#define MN_vcvtbiasph2hf8 0x64b
-#define MN_vcvtph2hf8 0x65a
-#define MN_vmovdqu8 0x665
-#define MN_vextractf32x8 0x66e
-#define MN_vinsertf32x8 0x67c
-#define MN_vbroadcastf32x8 0x689
-#define MN_vextracti32x8 0x699
-#define MN_vinserti32x8 0x6a7
-#define MN_vbroadcasti32x8 0x6b4
-#define MN_ud2a 0x6c4
-#define MN_aaa 0x6c9
-#define MN_daa 0x6cd
-#define MN_ssca 0x6d1
-#define MN_lea 0x6d6
-#define MN_invlpga 0x6da
-#define MN_pusha 0x6e2
-#define MN_ja 0x6e8
-#define MN_jna 0x6eb
-#define MN_ccmpna 0x6ef
-#define MN_setna 0x6f6
-#define MN_ctestna 0x6fc
-#define MN_setzuna 0x704
+#define MN_vcvtbiasps2bf8 0x63f
+#define MN_vcvtps2bf8 0x64e
+#define MN_vcvtbf42hf8 0x659
+#define MN_vcvtbf62hf8 0x665
+#define MN_vcvthf62hf8 0x671
+#define MN_vcvt2ph2hf8 0x67d
+#define MN_vcvtbiasph2hf8 0x689
+#define MN_vcvtph2hf8 0x698
+#define MN_vcvtrops2hf8 0x6a3
+#define MN_vcvtbiasps2hf8 0x6b0
+#define MN_vcvtps2hf8 0x6bf
+#define MN_vmovdqu8 0x6ca
+#define MN_vextractf32x8 0x6d3
+#define MN_vinsertf32x8 0x6e1
+#define MN_vbroadcastf32x8 0x6ee
+#define MN_vextracti32x8 0x6fe
+#define MN_vinserti32x8 0x70c
+#define MN_vbroadcasti32x8 0x719
+#define MN_ud2a 0x729
+#define MN_aaa 0x72e
+#define MN_daa 0x732
+#define MN_ssca 0x736
+#define MN_lea 0x73b
+#define MN_invlpga 0x73f
+#define MN_pusha 0x747
+#define MN_ja 0x74d
+#define MN_jna 0x750
+#define MN_ccmpna 0x754
+#define MN_setna 0x75b
+#define MN_ctestna 0x761
+#define MN_setzuna 0x769
 #define MN_cmovna (MN_fcmovna + 1)
 #define MN_fcmovna (MN_cfcmovna + 1)
-#define MN_cfcmovna 0x70c
-#define MN_ccmpa 0x715
-#define MN_popa 0x71b
+#define MN_cfcmovna 0x771
+#define MN_ccmpa 0x77a
+#define MN_popa 0x780
 #define MN_movntdqa (MN_vmovntdqa + 1)
-#define MN_vmovntdqa 0x720
+#define MN_vmovntdqa 0x785
 #define MN_movdqa (MN_vmovdqa + 1)
-#define MN_vmovdqa 0x72a
-#define MN_seta 0x732
-#define MN_prefetchnta 0x737
-#define MN_ctesta 0x743
-#define MN_setzua 0x74a
+#define MN_vmovdqa 0x78f
+#define MN_seta 0x797
+#define MN_prefetchnta 0x79c
+#define MN_ctesta 0x7a8
+#define MN_setzua 0x7af
 #define MN_cmova (MN_fcmova + 1)
 #define MN_fcmova (MN_cfcmova + 1)
-#define MN_cfcmova 0x751
-#define MN_rex_b 0x759
-#define MN_ud2b 0x75f
-#define MN_vpermi2b 0x764
-#define MN_vpmovm2b 0x76d
-#define MN_vpermt2b 0x776
-#define MN_movdir64b 0x77f
-#define MN_cmpxchg16b 0x789
-#define MN_cmpxchg8b 0x794
-#define MN_vpshab 0x79e
-#define MN_sbb 0x7a5
+#define MN_cfcmova 0x7b6
+#define MN_rex_b 0x7be
+#define MN_ud2b 0x7c4
+#define MN_vpermi2b 0x7c9
+#define MN_vpmovm2b 0x7d2
+#define MN_vpermt2b 0x7db
+#define MN_movdir64b 0x7e4
+#define MN_cmpxchg16b 0x7ee
+#define MN_cmpxchg8b 0x7f9
+#define MN_vpshab 0x803
+#define MN_sbb 0x80a
 #define MN_psubb (MN_vpsubb + 1)
-#define MN_vpsubb 0x7a9
-#define MN_xcrypt_ecb 0x7b0
-#define MN_xcryptecb 0x7bb
-#define MN_llwpcb 0x7c5
-#define MN_slwpcb 0x7cc
-#define MN_kaddb 0x7d3
+#define MN_vpsubb 0x80e
+#define MN_xcrypt_ecb 0x815
+#define MN_xcryptecb 0x820
+#define MN_llwpcb 0x82a
+#define MN_slwpcb 0x831
+#define MN_kaddb 0x838
 #define MN_paddb (MN_vpaddb + 1)
-#define MN_vpaddb 0x7d9
-#define MN_kandb 0x7e0
-#define MN_vpexpandb 0x7e6
-#define MN_vpmovusdb 0x7f0
-#define MN_vpmovsdb 0x7fa
-#define MN_udb 0x803
-#define MN_vpmovdb 0x807
-#define MN_vpcomgeb 0x80f
-#define MN_vpcomleb 0x818
-#define MN_vpcmpnleb 0x821
-#define MN_vpcmpleb 0x82b
-#define MN_vpcomfalseb 0x834
-#define MN_vpcomtrueb 0x840
-#define MN_xcrypt_cfb 0x84b
-#define MN_xcryptcfb 0x856
-#define MN_xcrypt_ofb 0x860
-#define MN_xcryptofb 0x86b
+#define MN_vpaddb 0x83e
+#define MN_kandb 0x845
+#define MN_vpexpandb 0x84b
+#define MN_vpmovssdb 0x855
+#define MN_vpmovusdb 0x85f
+#define MN_vpmovsdb 0x869
+#define MN_udb 0x872
+#define MN_vpmovdb 0x876
+#define MN_vpcomgeb 0x87e
+#define MN_vpcomleb 0x887
+#define MN_vpcmpnleb 0x890
+#define MN_vpcmpleb 0x89a
+#define MN_vpcomfalseb 0x8a3
+#define MN_vpcomtrueb 0x8af
+#define MN_xcrypt_cfb 0x8ba
+#define MN_xcryptcfb 0x8c5
+#define MN_xcrypt_ofb 0x8cf
+#define MN_xcryptofb 0x8da
 #define MN_pshufb (MN_vpshufb + 1)
-#define MN_vpshufb 0x875
-#define MN_invlpgb 0x87d
+#define MN_vpshufb 0x8e4
+#define MN_invlpgb 0x8ec
 #define MN_pavgb (MN_vpavgb + 1)
-#define MN_vpavgb 0x885
-#define MN_jb 0x88c
-#define MN_pbndkb 0x88f
+#define MN_vpavgb 0x8f4
+#define MN_jb 0x8fb
+#define MN_vunpackb 0x8fe
+#define MN_pbndkb 0x907
 #define MN_pmovmskb (MN_vpmovmskb + 1)
-#define MN_vpmovmskb 0x896
-#define MN_vpshlb 0x8a0
-#define MN_kshiftlb 0x8a7
+#define MN_vpmovmskb 0x90e
+#define MN_vpshlb 0x918
+#define MN_kshiftlb 0x91f
 #define MN_gf2p8mulb (MN_vgf2p8mulb + 1)
-#define MN_vgf2p8mulb 0x8b0
-#define MN_vpblendmb 0x8bb
-#define MN_vptestnmb 0x8c5
-#define MN_vpcomb 0x8cf
-#define MN_vpshufbitqmb 0x8d6
-#define MN_vpermb 0x8e3
-#define MN_vptestmb 0x8ea
-#define MN_kandnb 0x8f3
+#define MN_vgf2p8mulb 0x928
+#define MN_vpblendmb 0x933
+#define MN_vptestnmb 0x93d
+#define MN_vpcomb 0x947
+#define MN_vpshufbitqmb 0x94e
+#define MN_vpermb 0x95b
+#define MN_vptestmb 0x962
+#define MN_kandnb 0x96b
 #define MN_psignb (MN_vpsignb + 1)
-#define MN_vpsignb 0x8fa
-#define MN_jnb 0x902
-#define MN_ccmpnb 0x906
-#define MN_setnb 0x90d
-#define MN_ctestnb 0x913
-#define MN_setzunb 0x91b
+#define MN_vpsignb 0x972
+#define MN_jnb 0x97a
+#define MN_ccmpnb 0x97e
+#define MN_setnb 0x985
+#define MN_ctestnb 0x98b
+#define MN_setzunb 0x993
 #define MN_cmovnb (MN_fcmovnb + 1)
 #define MN_fcmovnb (MN_cfcmovnb + 1)
-#define MN_cfcmovnb 0x923
-#define MN_ccmpb 0x92c
-#define MN_vpcmpb 0x932
-#define MN_vpcomeqb 0x939
+#define MN_cfcmovnb 0x99b
+#define MN_ccmpb 0x9a4
+#define MN_vpcmpb 0x9aa
+#define MN_vpcomeqb 0x9b1
 #define MN_gf2p8affineqb (MN_vgf2p8affineqb + 1)
-#define MN_vgf2p8affineqb 0x942
-#define MN_vpcomneqb 0x951
-#define MN_vpcmpneqb 0x95b
+#define MN_vgf2p8affineqb 0x9ba
+#define MN_vpcomneqb 0x9c9
+#define MN_vpcmpneqb 0x9d3
 #define MN_pcmpeqb (MN_vpcmpeqb + 1)
-#define MN_vpcmpeqb 0x965
-#define MN_vpmovusqb 0x96e
-#define MN_vpmovsqb 0x978
-#define MN_vpmultishiftqb 0x981
+#define MN_vpcmpeqb 0x9dd
+#define MN_vpmovusqb 0x9e6
+#define MN_vpmovsqb 0x9f0
+#define MN_vpmultishiftqb 0x9f9
 #define MN_gf2p8affineinvqb (MN_vgf2p8affineinvqb + 1)
-#define MN_vgf2p8affineinvqb 0x990
-#define MN_vpmovqb 0x9a2
-#define MN_rex_rb 0x9aa
-#define MN_korb 0x9b1
-#define MN_kxnorb 0x9b6
-#define MN_kxorb 0x9bd
+#define MN_vgf2p8affineinvqb 0xa08
+#define MN_vpmovqb 0xa1a
+#define MN_rex_rb 0xa22
+#define MN_korb 0xa29
+#define MN_kxnorb 0xa2e
+#define MN_kxorb 0xa35
 #define MN_pinsrb (MN_vpinsrb + 1)
-#define MN_vpinsrb 0x9c3
-#define MN_kshiftrb 0x9cb
+#define MN_vpinsrb 0xa3b
+#define MN_kshiftrb 0xa43
 #define MN_pextrb (MN_vpextrb + 1)
-#define MN_vpextrb 0x9d4
-#define MN_rex_wrb 0x9dc
+#define MN_vpextrb 0xa4c
+#define MN_rex_wrb 0xa54
 #define MN_pabsb (MN_vpabsb + 1)
-#define MN_vpabsb 0x9e4
+#define MN_vpabsb 0xa5c
 #define MN_psubsb (MN_vpsubsb + 1)
-#define MN_vpsubsb 0x9eb
+#define MN_vpsubsb 0xa63
 #define MN_paddsb (MN_vpaddsb + 1)
-#define MN_vpaddsb 0x9f3
+#define MN_vpaddsb 0xa6b
 #define MN_pminsb (MN_vpminsb + 1)
-#define MN_vpminsb 0x9fb
-#define MN_vmovrsb 0xa03
-#define MN_vpcompressb 0xa0b
+#define MN_vpminsb 0xa73
+#define MN_vmovrsb 0xa7b
+#define MN_vpcompressb 0xa83
 #define MN_psubusb (MN_vpsubusb + 1)
-#define MN_vpsubusb 0xa17
+#define MN_vpsubusb 0xa8f
 #define MN_paddusb (MN_vpaddusb + 1)
-#define MN_vpaddusb 0xa20
-#define MN_pavgusb 0xa29
-#define MN_movsb 0xa31
+#define MN_vpaddusb 0xa98
+#define MN_pavgusb 0xaa1
+#define MN_movsb 0xaa9
 #define MN_pmaxsb (MN_vpmaxsb + 1)
-#define MN_vpmaxsb 0xa37
-#define MN_setb 0xa3f
-#define MN_vpcomgtb 0xa44
+#define MN_vpmaxsb 0xaaf
+#define MN_setb 0xab7
+#define MN_vpcomgtb 0xabc
 #define MN_pcmpgtb (MN_vpcmpgtb + 1)
-#define MN_vpcmpgtb 0xa4d
-#define MN_vpcomltb 0xa56
-#define MN_vpcmpnltb 0xa5f
-#define MN_vpcmpltb 0xa69
-#define MN_vpopcntb 0xa72
-#define MN_knotb 0xa7b
-#define MN_vprotb 0xa81
-#define MN_vpbroadcastb 0xa88
-#define MN_ctestb 0xa95
-#define MN_ktestb 0xa9c
-#define MN_kortestb 0xaa3
-#define MN_vpcomgeub 0xaac
-#define MN_vpcomleub 0xab6
-#define MN_vpcmpnleub 0xac0
-#define MN_vpcmpleub 0xacb
-#define MN_vpcomfalseub 0xad5
-#define MN_vpcomtrueub 0xae2
-#define MN_vpcomub 0xaee
+#define MN_vpcmpgtb 0xac5
+#define MN_vpcomltb 0xace
+#define MN_vpcmpnltb 0xad7
+#define MN_vpcmpltb 0xae1
+#define MN_vpopcntb 0xaea
+#define MN_knotb 0xaf3
+#define MN_vprotb 0xaf9
+#define MN_vpbroadcastb 0xb00
+#define MN_ctestb 0xb0d
+#define MN_ktestb 0xb14
+#define MN_kortestb 0xb1b
+#define MN_vpcomgeub 0xb24
+#define MN_vpcomleub 0xb2e
+#define MN_vpcmpnleub 0xb38
+#define MN_vpcmpleub 0xb43
+#define MN_vpcomfalseub 0xb4d
+#define MN_vpcomtrueub 0xb5a
+#define MN_vpcomub 0xb66
 #define MN_pminub (MN_vpminub + 1)
-#define MN_vpminub 0xaf6
-#define MN_vpcmpub 0xafe
-#define MN_vpcomequb 0xb06
-#define MN_vpcomnequb 0xb10
-#define MN_vpcmpnequb 0xb1b
-#define MN_vpcmpequb 0xb26
+#define MN_vpminub 0xb6e
+#define MN_vpcmpub 0xb76
+#define MN_vpcomequb 0xb7e
+#define MN_vpcomnequb 0xb88
+#define MN_vpcmpnequb 0xb93
+#define MN_vpcmpequb 0xb9e
 #define MN_sub (MN_fsub + 1)
 #define MN_fsub (MN_pfsub + 1)
-#define MN_pfsub 0xb30
-#define MN_fisub 0xb36
-#define MN_vpcomgtub 0xb3c
-#define MN_vpcomltub 0xb46
-#define MN_vpcmpnltub 0xb50
-#define MN_vpcmpltub 0xb5b
+#define MN_pfsub 0xba8
+#define MN_fisub 0xbae
+#define MN_vpcomgtub 0xbb4
+#define MN_vpcomltub 0xbbe
+#define MN_vpcmpnltub 0xbc8
+#define MN_vpcmpltub 0xbd3
 #define MN_pmaxub (MN_vpmaxub + 1)
-#define MN_vpmaxub 0xb65
-#define MN_setzub 0xb6d
+#define MN_vpmaxub 0xbdd
+#define MN_setzub 0xbe5
 #define MN_pblendvb (MN_vpblendvb + 1)
-#define MN_vpblendvb 0xb74
-#define MN_vbitrevb 0xb7e
+#define MN_vpblendvb 0xbec
+#define MN_vbitrevb 0xbf6
 #define MN_cmovb (MN_fcmovb + 1)
 #define MN_fcmovb (MN_cfcmovb + 1)
-#define MN_cfcmovb 0xb87
-#define MN_kmovb 0xb8f
-#define MN_rex_wb 0xb95
-#define MN_clwb 0xb9c
+#define MN_cfcmovb 0xbff
+#define MN_kmovb 0xc07
+#define MN_rex_wb 0xc0d
+#define MN_clwb 0xc14
 #define MN_packsswb (MN_vpacksswb + 1)
-#define MN_vpacksswb 0xba1
+#define MN_vpacksswb 0xc19
 #define MN_packuswb (MN_vpackuswb + 1)
-#define MN_vpackuswb 0xbab
-#define MN_vpmovuswb 0xbb5
-#define MN_vpmovswb 0xbbf
-#define MN_vpmovwb 0xbc8
-#define MN_rex_xb 0xbd0
-#define MN_rex_rxb 0xbd7
-#define MN_rex_wrxb 0xbdf
-#define MN_rex_wxb 0xbe8
-#define MN_movzb 0xbf0
-#define MN_clac 0xbf6
-#define MN_stac 0xbfb
-#define MN_xcrypt_cbc 0xc00
-#define MN_xcryptcbc 0xc0b
-#define MN_pfacc 0xc15
-#define MN_pfnacc 0xc1b
-#define MN_pfpnacc 0xc22
-#define MN_adc 0xc2a
+#define MN_vpackuswb 0xc23
+#define MN_vpmovuswb 0xc2d
+#define MN_vpmovswb 0xc37
+#define MN_vpmovwb 0xc40
+#define MN_rex_xb 0xc48
+#define MN_rex_rxb 0xc4f
+#define MN_rex_wrxb 0xc57
+#define MN_rex_wxb 0xc60
+#define MN_movzb 0xc68
+#define MN_clac 0xc6e
+#define MN_stac 0xc73
+#define MN_xcrypt_cbc 0xc78
+#define MN_xcryptcbc 0xc83
+#define MN_pfacc 0xc8d
+#define MN_pfnacc 0xc93
+#define MN_pfpnacc 0xc9a
+#define MN_adc 0xca2
 #define MN_dec (MN_aesdec + 3)
 #define MN_aesdec (MN_vaesdec + 1)
-#define MN_vaesdec 0xc2e
-#define MN_getsec 0xc36
-#define MN_xsavec 0xc3d
-#define MN_blcic 0xc44
-#define MN_blsic 0xc4a
-#define MN_jc 0xc50
-#define MN_t1mskc 0xc53
-#define MN_salc 0xc5a
-#define MN_clc 0xc5f
-#define MN_cmc 0xc63
+#define MN_vaesdec 0xca6
+#define MN_getsec 0xcae
+#define MN_xsavec 0xcb5
+#define MN_blcic 0xcbc
+#define MN_blsic 0xcc2
+#define MN_jc 0xcc8
+#define MN_t1mskc 0xccb
+#define MN_salc 0xcd2
+#define MN_clc 0xcd7
+#define MN_cmc 0xcdb
 #define MN_aesimc (MN_vaesimc + 1)
-#define MN_vaesimc 0xc67
-#define MN_rdpmc 0xc6f
+#define MN_vaesimc 0xcdf
+#define MN_rdpmc 0xce7
 #define MN_aesenc (MN_vaesenc + 1)
-#define MN_vaesenc 0xc75
-#define MN_inc 0xc7d
-#define MN_jnc 0xc81
-#define MN_ccmpnc 0xc85
-#define MN_setnc 0xc8c
-#define MN_ctestnc 0xc92
-#define MN_vmfunc 0xc9a
-#define MN_setzunc 0xca1
+#define MN_vaesenc 0xced
+#define MN_inc 0xcf5
+#define MN_jnc 0xcf9
+#define MN_ccmpnc 0xcfd
+#define MN_setnc 0xd04
+#define MN_ctestnc 0xd0a
+#define MN_vmfunc 0xd12
+#define MN_setzunc 0xd19
 #define MN_cmovnc (MN_cfcmovnc + 2)
-#define MN_cfcmovnc 0xca9
-#define MN_tlbsync 0xcb2
-#define MN_ccmpc 0xcba
-#define MN_rdtsc 0xcc0
-#define MN_btc 0xcc6
-#define MN_setc 0xcca
+#define MN_cfcmovnc 0xd21
+#define MN_tlbsync 0xd2a
+#define MN_ccmpc 0xd32
+#define MN_rdtsc 0xd38
+#define MN_btc 0xd3e
+#define MN_setc 0xd42
 #define MN_stc (MN_ctestc + 3)
-#define MN_ctestc 0xccf
-#define MN_setzuc 0xcd6
+#define MN_ctestc 0xd47
+#define MN_setzuc 0xd4e
 #define MN_cmovc (MN_cfcmovc + 2)
-#define MN_cfcmovc 0xcdd
-#define MN_vpermi2d 0xce5
-#define MN_vpmovm2d 0xcee
-#define MN_vpermt2d 0xcf7
-#define MN_vpbroadcastmw2d 0xd00
-#define MN_aad 0xd10
-#define MN_vmread 0xd14
-#define MN_rmpread 0xd1b
-#define MN_vpshad 0xd23
-#define MN_vmload 0xd2a
+#define MN_cfcmovc 0xd55
+#define MN_vpermi2d 0xd5d
+#define MN_vpmovm2d 0xd66
+#define MN_vpermt2d 0xd6f
+#define MN_vpbroadcastmw2d 0xd78
+#define MN_aad 0xd88
+#define MN_vmread 0xd8c
+#define MN_rmpread 0xd93
+#define MN_vpshad 0xd9b
+#define MN_vmload 0xda2
 #define MN_psrad (MN_vpsrad + 1)
-#define MN_vpsrad 0xd31
-#define MN_vphaddbd 0xd38
-#define MN_vphaddubd 0xd41
+#define MN_vpsrad 0xda9
+#define MN_vphaddbd 0xdb0
+#define MN_vphaddubd 0xdb9
 #define MN_phsubd (MN_vphsubd + 1)
-#define MN_vphsubd 0xd4b
+#define MN_vphsubd 0xdc3
 #define MN_psubd (MN_vpsubd + 1)
-#define MN_vpsubd 0xd53
+#define MN_vpsubd 0xdcb
 #define MN_pmovsxbd (MN_vpmovsxbd + 1)
-#define MN_vpmovsxbd 0xd5a
+#define MN_vpmovsxbd 0xdd2
 #define MN_pmovzxbd (MN_vpmovzxbd + 1)
-#define MN_vpmovzxbd 0xd64
+#define MN_vpmovzxbd 0xddc
 #define MN_add (MN_aadd + 1)
-#define MN_aadd 0xd6e
+#define MN_aadd 0xde6
 #define MN_fadd (MN_pfadd + 1)
-#define MN_pfadd 0xd73
-#define MN_fiadd 0xd79
-#define MN_tileloadd 0xd7f
+#define MN_pfadd 0xdeb
+#define MN_fiadd 0xdf1
+#define MN_tileloadd 0xdf7
 #define MN_xadd (MN_cmpnaxadd + 5)
-#define MN_cmpnaxadd 0xd89
-#define MN_cmpaxadd 0xd93
-#define MN_cmpnbxadd 0xd9c
-#define MN_cmpbxadd 0xda6
-#define MN_cmpncxadd 0xdaf
-#define MN_cmpcxadd 0xdb9
-#define MN_cmpnaexadd 0xdc2
-#define MN_cmpaexadd 0xdcd
-#define MN_cmpnbexadd 0xdd7
-#define MN_cmpbexadd 0xde2
-#define MN_cmpngexadd 0xdec
-#define MN_cmpgexadd 0xdf7
-#define MN_cmpnlexadd 0xe01
-#define MN_cmplexadd 0xe0c
-#define MN_cmpnexadd 0xe16
-#define MN_cmpexadd 0xe20
-#define MN_cmppexadd 0xe29
-#define MN_cmpngxadd 0xe33
-#define MN_cmpgxadd 0xe3d
-#define MN_cmpnlxadd 0xe46
-#define MN_cmplxadd 0xe50
-#define MN_cmpnoxadd 0xe59
-#define MN_cmpoxadd 0xe63
-#define MN_cmppoxadd 0xe6c
-#define MN_cmpnpxadd 0xe76
-#define MN_cmppxadd 0xe80
-#define MN_cmpnsxadd 0xe89
-#define MN_cmpsxadd 0xe93
-#define MN_cmpnzxadd 0xe9c
-#define MN_cmpzxadd 0xea6
+#define MN_cmpnaxadd 0xe01
+#define MN_cmpaxadd 0xe0b
+#define MN_cmpnbxadd 0xe14
+#define MN_cmpbxadd 0xe1e
+#define MN_cmpncxadd 0xe27
+#define MN_cmpcxadd 0xe31
+#define MN_cmpnaexadd 0xe3a
+#define MN_cmpaexadd 0xe45
+#define MN_cmpnbexadd 0xe4f
+#define MN_cmpbexadd 0xe5a
+#define MN_cmpngexadd 0xe64
+#define MN_cmpgexadd 0xe6f
+#define MN_cmpnlexadd 0xe79
+#define MN_cmplexadd 0xe84
+#define MN_cmpnexadd 0xe8e
+#define MN_cmpexadd 0xe98
+#define MN_cmppexadd 0xea1
+#define MN_cmpngxadd 0xeab
+#define MN_cmpgxadd 0xeb5
+#define MN_cmpnlxadd 0xebe
+#define MN_cmplxadd 0xec8
+#define MN_cmpnoxadd 0xed1
+#define MN_cmpoxadd 0xedb
+#define MN_cmppoxadd 0xee4
+#define MN_cmpnpxadd 0xeee
+#define MN_cmppxadd 0xef8
+#define MN_cmpnsxadd 0xf01
+#define MN_cmpsxadd 0xf0b
+#define MN_cmpnzxadd 0xf14
+#define MN_cmpzxadd 0xf1e
 #define MN_phaddd (MN_vphaddd + 1)
-#define MN_vphaddd 0xeaf
-#define MN_kaddd 0xeb7
+#define MN_vphaddd 0xf27
+#define MN_kaddd 0xf2f
 #define MN_paddd (MN_vpaddd + 1)
-#define MN_vpaddd 0xebd
-#define MN_vpshldd 0xec4
-#define MN_kandd 0xecc
-#define MN_vpandd 0xed2
-#define MN_vpexpandd 0xed9
-#define MN_vpblendd 0xee3
-#define MN_vpgatherdd 0xeec
-#define MN_vpscatterdd 0xef7
-#define MN_vpshrdd 0xf03
-#define MN_vpmacsdd 0xf0b
-#define MN_vpmacssdd 0xf14
-#define MN_rdseed 0xf1e
-#define MN_vpcomged 0xf25
-#define MN_vpcomled 0xf2e
-#define MN_vpcmpnled 0xf37
-#define MN_vpcmpled 0xf41
-#define MN_tilestored 0xf4a
-#define MN_vpcomfalsed 0xf55
-#define MN_ttransposed 0xf61
-#define MN_vpcomtrued 0xf6d
-#define MN_pi2fd 0xf78
+#define MN_vpaddd 0xf35
+#define MN_vpshldd 0xf3c
+#define MN_kandd 0xf44
+#define MN_vpandd 0xf4a
+#define MN_vpexpandd 0xf51
+#define MN_vpblendd 0xf5b
+#define MN_vpgatherdd 0xf64
+#define MN_vpscatterdd 0xf6f
+#define MN_vpshrdd 0xf7b
+#define MN_vpmacsdd 0xf83
+#define MN_vpmacssdd 0xf8c
+#define MN_rdseed 0xf96
+#define MN_vpcomged 0xf9d
+#define MN_vpcomled 0xfa6
+#define MN_vpcmpnled 0xfaf
+#define MN_vpcmpled 0xfb9
+#define MN_tilestored 0xfc2
+#define MN_vpcomfalsed 0xfcd
+#define MN_ttransposed 0xfd9
+#define MN_vpcomtrued 0xfe5
+#define MN_pi2fd 0xff0
 #define MN_pshufd (MN_vpshufd + 1)
-#define MN_vpshufd 0xf7e
-#define MN_vpternlogd 0xf86
-#define MN_pf2id 0xf91
-#define MN_invpcid 0xf97
-#define MN_rdpid 0xf9f
-#define MN_invvpid 0xfa5
-#define MN_cpuid 0xfad
-#define MN_fbld 0xfb3
-#define MN_cld 0xfb8
-#define MN_fld 0xfbc
+#define MN_vpshufd 0xff6
+#define MN_vpternlogd 0xffe
+#define MN_pf2id 0x1009
+#define MN_invpcid 0x100f
+#define MN_rdpid 0x1017
+#define MN_invvpid 0x101d
+#define MN_cpuid 0x1025
+#define MN_fbld 0x102b
+#define MN_cld 0x1030
+#define MN_fld 0x1034
 #define MN_shld (MN_vpshld + 2)
-#define MN_vpshld 0xfc0
-#define MN_fild 0xfc7
+#define MN_vpshld 0x1038
+#define MN_fild 0x103f
 #define MN_pslld (MN_vpslld + 1)
-#define MN_vpslld 0xfcc
+#define MN_vpslld 0x1044
 #define MN_pmulld (MN_vpmulld + 1)
-#define MN_vpmulld 0xfd3
-#define MN_vprold 0xfdb
+#define MN_vpmulld 0x104b
+#define MN_vprold 0x1053
 #define MN_psrld (MN_vpsrld + 1)
-#define MN_vpsrld 0xfe2
-#define MN_vmptrld 0xfe9
-#define MN_kshiftld 0xff1
-#define MN_enqcmd 0xffa
-#define MN_vpblendmd 0x1001
-#define MN_vptestnmd 0x100b
-#define MN_vpcomd 0x1015
-#define MN_vpermd 0x101c
-#define MN_vptestmd 0x1023
+#define MN_vpsrld 0x105a
+#define MN_vmptrld 0x1061
+#define MN_kshiftld 0x1069
+#define MN_enqcmd 0x1072
+#define MN_vpblendmd 0x1079
+#define MN_vptestnmd 0x1083
+#define MN_vpcomd 0x108d
+#define MN_vpermd 0x1094
+#define MN_vptestmd 0x109b
 #define MN_and (MN_aand + 1)
-#define MN_aand 0x102c
+#define MN_aand 0x10a4
 #define MN_pand (MN_vpand + 1)
-#define MN_vpand 0x1031
-#define MN_rdrand 0x1037
-#define MN_bnd 0x103e
-#define MN_kandnd 0x1042
-#define MN_vpandnd 0x1049
-#define MN_xend 0x1051
-#define MN_valignd 0x1056
+#define MN_vpand 0x10a9
+#define MN_rdrand 0x10af
+#define MN_bnd 0x10b6
+#define MN_kandnd 0x10ba
+#define MN_vpandnd 0x10c1
+#define MN_xend 0x10c9
+#define MN_valignd 0x10ce
 #define MN_psignd (MN_vpsignd + 1)
-#define MN_vpsignd 0x105e
-#define MN_bound 0x1066
-#define MN_slod 0x106c
-#define MN_vfmaddsub231pd 0x1071
-#define MN_vfmsub231pd 0x1080
-#define MN_vfnmsub231pd 0x108c
-#define MN_vfmsubadd231pd 0x1099
-#define MN_vfmadd231pd 0x10a8
-#define MN_vfnmadd231pd 0x10b4
-#define MN_vfmaddsub132pd 0x10c1
-#define MN_vfmsub132pd 0x10d0
-#define MN_vfnmsub132pd 0x10dc
-#define MN_vfmsubadd132pd 0x10e9
-#define MN_vfmadd132pd 0x10f8
-#define MN_vfnmadd132pd 0x1104
-#define MN_vcvtph2pd 0x1111
-#define MN_vpermi2pd 0x111b
-#define MN_cvtpi2pd 0x1125
-#define MN_vpermil2pd 0x112e
-#define MN_vexp2pd 0x1139
+#define MN_vpsignd 0x10d6
+#define MN_bound 0x10de
+#define MN_slod 0x10e4
+#define MN_vfmaddsub231pd 0x10e9
+#define MN_vfmsub231pd 0x10f8
+#define MN_vfnmsub231pd 0x1104
+#define MN_vfmsubadd231pd 0x1111
+#define MN_vfmadd231pd 0x1120
+#define MN_vfnmadd231pd 0x112c
+#define MN_vfmaddsub132pd 0x1139
+#define MN_vfmsub132pd 0x1148
+#define MN_vfnmsub132pd 0x1154
+#define MN_vfmsubadd132pd 0x1161
+#define MN_vfmadd132pd 0x1170
+#define MN_vfnmadd132pd 0x117c
+#define MN_vcvtph2pd 0x1189
+#define MN_vpermi2pd 0x1193
+#define MN_cvtpi2pd 0x119d
+#define MN_vpermil2pd 0x11a6
+#define MN_vexp2pd 0x11b1
 #define MN_cvtdq2pd (MN_vcvtdq2pd + 1)
-#define MN_vcvtdq2pd 0x1141
-#define MN_vcvtudq2pd 0x114b
-#define MN_vcvtqq2pd 0x1156
-#define MN_vcvtuqq2pd 0x1160
+#define MN_vcvtdq2pd 0x11b9
+#define MN_vcvtudq2pd 0x11c3
+#define MN_vcvtqq2pd 0x11ce
+#define MN_vcvtuqq2pd 0x11d8
 #define MN_cvtps2pd (MN_vcvtps2pd + 1)
-#define MN_vcvtps2pd 0x116b
-#define MN_vpermt2pd 0x1175
-#define MN_vfmaddsub213pd 0x117f
-#define MN_vfmsub213pd 0x118e
-#define MN_vfnmsub213pd 0x119a
-#define MN_vfmsubadd213pd 0x11a7
-#define MN_vfmadd213pd 0x11b6
-#define MN_vfnmadd213pd 0x11c2
-#define MN_vrcp14pd 0x11cf
-#define MN_vrsqrt14pd 0x11d8
-#define MN_vrcp28pd 0x11e3
-#define MN_vrsqrt28pd 0x11ec
+#define MN_vcvtps2pd 0x11e3
+#define MN_vpermt2pd 0x11ed
+#define MN_vfmaddsub213pd 0x11f7
+#define MN_vfmsub213pd 0x1206
+#define MN_vfnmsub213pd 0x1212
+#define MN_vfmsubadd213pd 0x121f
+#define MN_vfmadd213pd 0x122e
+#define MN_vfnmadd213pd 0x123a
+#define MN_vrcp14pd 0x1247
+#define MN_vrsqrt14pd 0x1250
+#define MN_vrcp28pd 0x125b
+#define MN_vrsqrt28pd 0x1264
 #define MN_movapd (MN_vmovapd + 1)
-#define MN_vmovapd 0x11f7
-#define MN_pswapd 0x11ff
+#define MN_vmovapd 0x126f
+#define MN_pswapd 0x1277
 #define MN_subpd (MN_addsubpd + 3)
 #define MN_addsubpd (MN_vfmaddsubpd + 3)
-#define MN_vfmaddsubpd 0x1206
-#define MN_vaddsubpd 0x1212
+#define MN_vfmaddsubpd 0x127e
+#define MN_vaddsubpd 0x128a
 #define MN_hsubpd (MN_vhsubpd + 1)
-#define MN_vhsubpd 0x121c
-#define MN_vfmsubpd 0x1224
-#define MN_vfnmsubpd 0x122d
-#define MN_vsubpd 0x1237
-#define MN_vgatherpf0dpd 0x123e
-#define MN_vscatterpf0dpd 0x124c
-#define MN_vgatherpf1dpd 0x125b
-#define MN_vscatterpf1dpd 0x1269
+#define MN_vhsubpd 0x1294
+#define MN_vfmsubpd 0x129c
+#define MN_vfnmsubpd 0x12a5
+#define MN_vsubpd 0x12af
+#define MN_vgatherpf0dpd 0x12b6
+#define MN_vscatterpf0dpd 0x12c4
+#define MN_vgatherpf1dpd 0x12d3
+#define MN_vscatterpf1dpd 0x12e1
 #define MN_addpd (MN_vfmsubaddpd + 6)
-#define MN_vfmsubaddpd 0x1278
+#define MN_vfmsubaddpd 0x12f0
 #define MN_haddpd (MN_vhaddpd + 1)
-#define MN_vhaddpd 0x1284
-#define MN_vfmaddpd 0x128c
-#define MN_vfnmaddpd 0x1295
-#define MN_vaddpd 0x129f
+#define MN_vhaddpd 0x12fc
+#define MN_vfmaddpd 0x1304
+#define MN_vfnmaddpd 0x130d
+#define MN_vaddpd 0x1317
 #define MN_andpd (MN_vexpandpd + 4)
-#define MN_vexpandpd 0x12a6
-#define MN_vandpd 0x12b0
+#define MN_vexpandpd 0x131e
+#define MN_vandpd 0x1328
 #define MN_blendpd (MN_vblendpd + 1)
-#define MN_vblendpd 0x12b7
+#define MN_vblendpd 0x132f
 #define MN_roundpd (MN_vroundpd + 1)
-#define MN_vroundpd 0x12c0
-#define MN_vgatherdpd 0x12c9
-#define MN_vscatterdpd 0x12d4
+#define MN_vroundpd 0x1338
+#define MN_vgatherdpd 0x1341
+#define MN_vscatterdpd 0x134c
 #define MN_cmpunordpd (MN_vcmpunordpd + 1)
-#define MN_vcmpunordpd 0x12e0
+#define MN_vcmpunordpd 0x1358
 #define MN_cmpordpd (MN_vcmpordpd + 1)
-#define MN_vcmpordpd 0x12ec
-#define MN_vreducepd 0x12f6
-#define MN_vrangepd 0x1300
-#define MN_vcmpngepd 0x1309
-#define MN_vcmpgepd 0x1313
-#define MN_vrndscalepd 0x131c
+#define MN_vcmpordpd 0x1364
+#define MN_vreducepd 0x136e
+#define MN_vrangepd 0x1378
+#define MN_vcmpngepd 0x1381
+#define MN_vcmpgepd 0x138b
+#define MN_vrndscalepd 0x1394
 #define MN_cmpnlepd (MN_vcmpnlepd + 1)
-#define MN_vcmpnlepd 0x1328
+#define MN_vcmpnlepd 0x13a0
 #define MN_cmplepd (MN_vcmplepd + 1)
-#define MN_vcmplepd 0x1332
-#define MN_vcmpfalsepd 0x133b
-#define MN_vcmptruepd 0x1347
-#define MN_vscalefpd 0x1352
+#define MN_vcmplepd 0x13aa
+#define MN_vcmpfalsepd 0x13b3
+#define MN_vcmptruepd 0x13bf
+#define MN_vscalefpd 0x13ca
 #define MN_shufpd (MN_vshufpd + 1)
-#define MN_vshufpd 0x135c
+#define MN_vshufpd 0x13d4
 #define MN_unpckhpd (MN_vunpckhpd + 1)
-#define MN_vunpckhpd 0x1364
+#define MN_vunpckhpd 0x13dc
 #define MN_movhpd (MN_vmovhpd + 1)
-#define MN_vmovhpd 0x136e
+#define MN_vmovhpd 0x13e6
 #define MN_movmskpd (MN_vmovmskpd + 1)
-#define MN_vmovmskpd 0x1376
-#define MN_vpermilpd 0x1380
+#define MN_vmovmskpd 0x13ee
+#define MN_vpermilpd 0x13f8
 #define MN_unpcklpd (MN_vunpcklpd + 1)
-#define MN_vunpcklpd 0x138a
+#define MN_vunpcklpd 0x1402
 #define MN_mulpd (MN_vmulpd + 1)
-#define MN_vmulpd 0x1394
+#define MN_vmulpd 0x140c
 #define MN_movlpd (MN_vmovlpd + 1)
-#define MN_vmovlpd 0x139b
-#define MN_vpcmpd 0x13a3
-#define MN_vblendmpd 0x13aa
-#define MN_vfixupimmpd 0x13b4
-#define MN_vpermpd 0x13c0
+#define MN_vmovlpd 0x1413
+#define MN_vpcmpd 0x141b
+#define MN_vblendmpd 0x1422
+#define MN_vfixupimmpd 0x142c
+#define MN_vpermpd 0x1438
 #define MN_andnpd (MN_vandnpd + 1)
-#define MN_vandnpd 0x13c8
+#define MN_vandnpd 0x1440
 #define MN_minpd (MN_vminpd + 1)
-#define MN_vminpd 0x13d0
+#define MN_vminpd 0x1448
 #define MN_dppd (MN_vdppd + 1)
-#define MN_vdppd 0x13d7
+#define MN_vdppd 0x144f
 #define MN_cmppd (MN_vcmppd + 1)
-#define MN_vcmppd 0x13dd
-#define MN_vgetexppd 0x13e4
-#define MN_vgatherpf0qpd 0x13ee
-#define MN_vscatterpf0qpd 0x13fc
-#define MN_vgatherpf1qpd 0x140b
-#define MN_vscatterpf1qpd 0x1419
-#define MN_vcmpunord_qpd 0x1428
-#define MN_vcmpord_qpd 0x1436
+#define MN_vcmppd 0x1455
+#define MN_vgetexppd 0x145c
+#define MN_vgatherpf0qpd 0x1466
+#define MN_vscatterpf0qpd 0x1474
+#define MN_vgatherpf1qpd 0x1483
+#define MN_vscatterpf1qpd 0x1491
+#define MN_vcmpunord_qpd 0x14a0
+#define MN_vcmpord_qpd 0x14ae
 #define MN_cmpneqpd (MN_vcmpneqpd + 1)
-#define MN_vcmpneqpd 0x1442
+#define MN_vcmpneqpd 0x14ba
 #define MN_cmpeqpd (MN_vcmpeqpd + 1)
-#define MN_vcmpeqpd 0x144c
-#define MN_vcmpge_oqpd 0x1455
-#define MN_vcmple_oqpd 0x1461
-#define MN_vcmpfalse_oqpd 0x146d
-#define MN_vcmpneq_oqpd 0x147c
-#define MN_vcmpeq_oqpd 0x1489
-#define MN_vcmpgt_oqpd 0x1495
-#define MN_vcmplt_oqpd 0x14a1
-#define MN_vgatherqpd 0x14ad
-#define MN_vscatterqpd 0x14b8
-#define MN_vcmpnge_uqpd 0x14c4
-#define MN_vcmpnle_uqpd 0x14d1
-#define MN_vcmptrue_uqpd 0x14de
-#define MN_vcmpneq_uqpd 0x14ec
-#define MN_vcmpeq_uqpd 0x14f9
-#define MN_vcmpngt_uqpd 0x1505
-#define MN_vcmpnlt_uqpd 0x1512
+#define MN_vcmpeqpd 0x14c4
+#define MN_vcmpge_oqpd 0x14cd
+#define MN_vcmple_oqpd 0x14d9
+#define MN_vcmpfalse_oqpd 0x14e5
+#define MN_vcmpneq_oqpd 0x14f4
+#define MN_vcmpeq_oqpd 0x1501
+#define MN_vcmpgt_oqpd 0x150d
+#define MN_vcmplt_oqpd 0x1519
+#define MN_vgatherqpd 0x1525
+#define MN_vscatterqpd 0x1530
+#define MN_vcmpnge_uqpd 0x153c
+#define MN_vcmpnle_uqpd 0x1549
+#define MN_vcmptrue_uqpd 0x1556
+#define MN_vcmpneq_uqpd 0x1564
+#define MN_vcmpeq_uqpd 0x1571
+#define MN_vcmpngt_uqpd 0x157d
+#define MN_vcmpnlt_uqpd 0x158a
 #define MN_orpd (MN_vorpd + 1)
-#define MN_vorpd 0x151f
+#define MN_vorpd 0x1597
 #define MN_xorpd (MN_vxorpd + 1)
-#define MN_vxorpd 0x1525
-#define MN_vcmpunord_spd 0x152c
-#define MN_vcmpord_spd 0x153a
-#define MN_vcmpge_ospd 0x1546
-#define MN_vcmple_ospd 0x1552
-#define MN_vcmpfalse_ospd 0x155e
-#define MN_vcmpneq_ospd 0x156d
-#define MN_vcmpeq_ospd 0x157a
-#define MN_vcmpgt_ospd 0x1586
-#define MN_vcmplt_ospd 0x1592
-#define MN_vfpclasspd 0x159e
-#define MN_incsspd 0x15a9
-#define MN_rdsspd 0x15b1
-#define MN_vcompresspd 0x15b8
-#define MN_vcmpnge_uspd 0x15c4
-#define MN_vcmpnle_uspd 0x15d1
-#define MN_vcmptrue_uspd 0x15de
-#define MN_vcmpneq_uspd 0x15ec
-#define MN_vcmpeq_uspd 0x15f9
-#define MN_vcmpngt_uspd 0x1605
-#define MN_vcmpnlt_uspd 0x1612
-#define MN_vcmpngtpd 0x161f
-#define MN_vcmpgtpd 0x1629
+#define MN_vxorpd 0x159d
+#define MN_vcmpunord_spd 0x15a4
+#define MN_vcmpord_spd 0x15b2
+#define MN_vcmpge_ospd 0x15be
+#define MN_vcmple_ospd 0x15ca
+#define MN_vcmpfalse_ospd 0x15d6
+#define MN_vcmpneq_ospd 0x15e5
+#define MN_vcmpeq_ospd 0x15f2
+#define MN_vcmpgt_ospd 0x15fe
+#define MN_vcmplt_ospd 0x160a
+#define MN_vfpclasspd 0x1616
+#define MN_incsspd 0x1621
+#define MN_rdsspd 0x1629
+#define MN_vcompresspd 0x1630
+#define MN_vcmpnge_uspd 0x163c
+#define MN_vcmpnle_uspd 0x1649
+#define MN_vcmptrue_uspd 0x1656
+#define MN_vcmpneq_uspd 0x1664
+#define MN_vcmpeq_uspd 0x1671
+#define MN_vcmpngt_uspd 0x167d
+#define MN_vcmpnlt_uspd 0x168a
+#define MN_vcmpngtpd 0x1697
+#define MN_vcmpgtpd 0x16a1
 #define MN_cmpnltpd (MN_vcmpnltpd + 1)
-#define MN_vcmpnltpd 0x1632
+#define MN_vcmpnltpd 0x16aa
 #define MN_cmpltpd (MN_vcmpltpd + 1)
-#define MN_vcmpltpd 0x163c
-#define MN_vgetmantpd 0x1645
+#define MN_vcmpltpd 0x16b4
+#define MN_vgetmantpd 0x16bd
 #define MN_movntpd (MN_vmovntpd + 1)
-#define MN_vmovntpd 0x1650
+#define MN_vmovntpd 0x16c8
 #define MN_sqrtpd (MN_vsqrtpd + 1)
-#define MN_vsqrtpd 0x1659
-#define MN_vtestpd 0x1661
+#define MN_vsqrtpd 0x16d1
+#define MN_vtestpd 0x16d9
 #define MN_movupd (MN_vmovupd + 1)
-#define MN_vmovupd 0x1669
+#define MN_vmovupd 0x16e1
 #define MN_blendvpd (MN_vblendvpd + 1)
-#define MN_vblendvpd 0x1671
+#define MN_vblendvpd 0x16e9
 #define MN_divpd (MN_vdivpd + 1)
-#define MN_vdivpd 0x167b
-#define MN_vmaskmovpd 0x1682
+#define MN_vdivpd 0x16f3
+#define MN_vmaskmovpd 0x16fa
 #define MN_maxpd (MN_vminmaxpd + 4)
-#define MN_vminmaxpd 0x168d
-#define MN_vmaxpd 0x1697
-#define MN_vfrczpd 0x169e
-#define MN_vpcomeqd 0x16a6
-#define MN_vpcomneqd 0x16af
-#define MN_vpcmpneqd 0x16b9
+#define MN_vminmaxpd 0x1705
+#define MN_vmaxpd 0x170f
+#define MN_vfrczpd 0x1716
+#define MN_vpcomeqd 0x171e
+#define MN_vpcomneqd 0x1727
+#define MN_vpcmpneqd 0x1731
 #define MN_pcmpeqd (MN_vpcmpeqd + 1)
-#define MN_vpcmpeqd 0x16c3
-#define MN_vpgatherqd 0x16cc
-#define MN_vpscatterqd 0x16d7
-#define MN_vpmovusqd 0x16e3
-#define MN_vpmovsqd 0x16ed
-#define MN_vpmovqd 0x16f6
-#define MN_shrd 0x16fe
-#define MN_kord 0x1703
-#define MN_kxnord 0x1708
-#define MN_vpord 0x170f
-#define MN_vprord 0x1715
+#define MN_vpcmpeqd 0x173b
+#define MN_vpgatherqd 0x1744
+#define MN_vpscatterqd 0x174f
+#define MN_vpmovusqd 0x175b
+#define MN_vpmovsqd 0x1765
+#define MN_vpmovqd 0x176e
+#define MN_shrd 0x1776
+#define MN_kord 0x177b
+#define MN_kxnord 0x1780
+#define MN_vpord 0x1787
+#define MN_vprord 0x178d
 #define MN_word (MN_aword + 1)
-#define MN_aword 0x171c
+#define MN_aword 0x1794
 #define MN_dword (MN_adword + 1)
-#define MN_adword 0x1722
-#define MN_kxord 0x1729
-#define MN_vpxord 0x172f
+#define MN_adword 0x179a
+#define MN_kxord 0x17a1
+#define MN_vpxord 0x17a7
 #define MN_pinsrd (MN_vpinsrd + 1)
-#define MN_vpinsrd 0x1736
-#define MN_kshiftrd 0x173e
+#define MN_vpinsrd 0x17ae
+#define MN_kshiftrd 0x17b6
 #define MN_pextrd (MN_vpextrd + 1)
-#define MN_vpextrd 0x1747
-#define MN_vfmsub231sd 0x174f
-#define MN_vfnmsub231sd 0x175b
-#define MN_vfmadd231sd 0x1768
-#define MN_vfnmadd231sd 0x1774
-#define MN_vfmsub132sd 0x1781
-#define MN_vfnmsub132sd 0x178d
-#define MN_vfmadd132sd 0x179a
-#define MN_vfnmadd132sd 0x17a6
-#define MN_vcvtsh2sd 0x17b3
+#define MN_vpextrd 0x17bf
+#define MN_vfmsub231sd 0x17c7
+#define MN_vfnmsub231sd 0x17d3
+#define MN_vfmadd231sd 0x17e0
+#define MN_vfnmadd231sd 0x17ec
+#define MN_vfmsub132sd 0x17f9
+#define MN_vfnmsub132sd 0x1805
+#define MN_vfmadd132sd 0x1812
+#define MN_vfnmadd132sd 0x181e
+#define MN_vcvtsh2sd 0x182b
 #define MN_cvtsi2sd (MN_vcvtsi2sd + 1)
-#define MN_vcvtsi2sd 0x17bd
-#define MN_vcvtusi2sd 0x17c7
+#define MN_vcvtsi2sd 0x1835
+#define MN_vcvtusi2sd 0x183f
 #define MN_cvtss2sd (MN_vcvtss2sd + 1)
-#define MN_vcvtss2sd 0x17d2
-#define MN_vfmsub213sd 0x17dc
-#define MN_vfnmsub213sd 0x17e8
-#define MN_vfmadd213sd 0x17f5
-#define MN_vfnmadd213sd 0x1801
-#define MN_vrcp14sd 0x180e
-#define MN_vrsqrt14sd 0x1817
-#define MN_vrcp28sd 0x1822
-#define MN_vrsqrt28sd 0x182b
+#define MN_vcvtss2sd 0x184a
+#define MN_vfmsub213sd 0x1854
+#define MN_vfnmsub213sd 0x1860
+#define MN_vfmadd213sd 0x186d
+#define MN_vfnmadd213sd 0x1879
+#define MN_vrcp14sd 0x1886
+#define MN_vrsqrt14sd 0x188f
+#define MN_vrcp28sd 0x189a
+#define MN_vrsqrt28sd 0x18a3
 #define MN_pabsd (MN_vpabsd + 1)
-#define MN_vpabsd 0x1836
+#define MN_vpabsd 0x18ae
 #define MN_subsd (MN_vfmsubsd + 3)
-#define MN_vfmsubsd 0x183d
-#define MN_vfnmsubsd 0x1846
-#define MN_vsubsd 0x1850
+#define MN_vfmsubsd 0x18b5
+#define MN_vfnmsubsd 0x18be
+#define MN_vsubsd 0x18c8
 #define MN_addsd (MN_vfmaddsd + 3)
-#define MN_vfmaddsd 0x1857
-#define MN_vfnmaddsd 0x1860
-#define MN_vaddsd 0x186a
+#define MN_vfmaddsd 0x18cf
+#define MN_vfnmaddsd 0x18d8
+#define MN_vaddsd 0x18e2
 #define MN_roundsd (MN_vroundsd + 1)
-#define MN_vroundsd 0x1871
+#define MN_vroundsd 0x18e9
 #define MN_cmpunordsd (MN_vcmpunordsd + 1)
-#define MN_vcmpunordsd 0x187a
+#define MN_vcmpunordsd 0x18f2
 #define MN_cmpordsd (MN_vcmpordsd + 1)
-#define MN_vcmpordsd 0x1886
-#define MN_vreducesd 0x1890
-#define MN_vrangesd 0x189a
-#define MN_vcmpngesd 0x18a3
-#define MN_vcmpgesd 0x18ad
-#define MN_vrndscalesd 0x18b6
+#define MN_vcmpordsd 0x18fe
+#define MN_vreducesd 0x1908
+#define MN_vrangesd 0x1912
+#define MN_vcmpngesd 0x191b
+#define MN_vcmpgesd 0x1925
+#define MN_vrndscalesd 0x192e
 #define MN_cmpnlesd (MN_vcmpnlesd + 1)
-#define MN_vcmpnlesd 0x18c2
+#define MN_vcmpnlesd 0x193a
 #define MN_cmplesd (MN_vcmplesd + 1)
-#define MN_vcmplesd 0x18cc
-#define MN_vcmpfalsesd 0x18d5
-#define MN_vcmptruesd 0x18e1
-#define MN_vscalefsd 0x18ec
+#define MN_vcmplesd 0x1944
+#define MN_vcmpfalsesd 0x194d
+#define MN_vcmptruesd 0x1959
+#define MN_vscalefsd 0x1964
 #define MN_comisd (MN_ucomisd + 1)
 #define MN_ucomisd (MN_vucomisd + 1)
-#define MN_vucomisd 0x18f6
-#define MN_vcomisd 0x18ff
+#define MN_vucomisd 0x196e
+#define MN_vcomisd 0x1977
 #define MN_mulsd (MN_vmulsd + 1)
-#define MN_vmulsd 0x1907
-#define MN_vfixupimmsd 0x190e
+#define MN_vmulsd 0x197f
+#define MN_vfixupimmsd 0x1986
 #define MN_minsd (MN_pminsd + 1)
 #define MN_pminsd (MN_vpminsd + 1)
-#define MN_vpminsd 0x191a
-#define MN_vminsd 0x1922
+#define MN_vpminsd 0x1992
+#define MN_vminsd 0x199a
 #define MN_cmpsd (MN_vcmpsd + 1)
-#define MN_vcmpsd 0x1929
-#define MN_vgetexpsd 0x1930
-#define MN_vcmpunord_qsd 0x193a
-#define MN_vcmpord_qsd 0x1948
+#define MN_vcmpsd 0x19a1
+#define MN_vgetexpsd 0x19a8
+#define MN_vcmpunord_qsd 0x19b2
+#define MN_vcmpord_qsd 0x19c0
 #define MN_cmpneqsd (MN_vcmpneqsd + 1)
-#define MN_vcmpneqsd 0x1954
+#define MN_vcmpneqsd 0x19cc
 #define MN_cmpeqsd (MN_vcmpeqsd + 1)
-#define MN_vcmpeqsd 0x195e
-#define MN_vcmpge_oqsd 0x1967
-#define MN_vcmple_oqsd 0x1973
-#define MN_vcmpfalse_oqsd 0x197f
-#define MN_vcmpneq_oqsd 0x198e
-#define MN_vcmpeq_oqsd 0x199b
-#define MN_vcmpgt_oqsd 0x19a7
-#define MN_vcmplt_oqsd 0x19b3
-#define MN_vcmpnge_uqsd 0x19bf
-#define MN_vcmpnle_uqsd 0x19cc
-#define MN_vcmptrue_uqsd 0x19d9
-#define MN_vcmpneq_uqsd 0x19e7
-#define MN_vcmpeq_uqsd 0x19f4
-#define MN_vcmpngt_uqsd 0x1a00
-#define MN_vcmpnlt_uqsd 0x1a0d
-#define MN_vmovrsd 0x1a1a
-#define MN_vcmpunord_ssd 0x1a22
-#define MN_vcmpord_ssd 0x1a30
-#define MN_vpdpbssd 0x1a3c
-#define MN_tdpbssd 0x1a45
-#define MN_vpcompressd 0x1a4d
-#define MN_vcmpge_ossd 0x1a59
-#define MN_vcmple_ossd 0x1a65
-#define MN_vcmpfalse_ossd 0x1a71
-#define MN_vcmpneq_ossd 0x1a80
-#define MN_vcmpeq_ossd 0x1a8d
-#define MN_vcmpgt_ossd 0x1a99
-#define MN_vcmplt_ossd 0x1aa5
-#define MN_wrssd 0x1ab1
-#define MN_vfpclasssd 0x1ab7
-#define MN_vcmpnge_ussd 0x1ac2
-#define MN_vcmpnle_ussd 0x1acf
-#define MN_vcmptrue_ussd 0x1adc
-#define MN_vcmpneq_ussd 0x1aea
-#define MN_vcmpeq_ussd 0x1af7
-#define MN_vcmpngt_ussd 0x1b03
-#define MN_vcmpnlt_ussd 0x1b10
-#define MN_wrussd 0x1b1d
-#define MN_vp4dpwssd 0x1b24
-#define MN_vpdpwssd 0x1b2e
-#define MN_vcmpngtsd 0x1b37
-#define MN_vcmpgtsd 0x1b41
+#define MN_vcmpeqsd 0x19d6
+#define MN_vcmpge_oqsd 0x19df
+#define MN_vcmple_oqsd 0x19eb
+#define MN_vcmpfalse_oqsd 0x19f7
+#define MN_vcmpneq_oqsd 0x1a06
+#define MN_vcmpeq_oqsd 0x1a13
+#define MN_vcmpgt_oqsd 0x1a1f
+#define MN_vcmplt_oqsd 0x1a2b
+#define MN_vcmpnge_uqsd 0x1a37
+#define MN_vcmpnle_uqsd 0x1a44
+#define MN_vcmptrue_uqsd 0x1a51
+#define MN_vcmpneq_uqsd 0x1a5f
+#define MN_vcmpeq_uqsd 0x1a6c
+#define MN_vcmpngt_uqsd 0x1a78
+#define MN_vcmpnlt_uqsd 0x1a85
+#define MN_vmovrsd 0x1a92
+#define MN_vcmpunord_ssd 0x1a9a
+#define MN_vcmpord_ssd 0x1aa8
+#define MN_vpdpbssd 0x1ab4
+#define MN_tdpbssd 0x1abd
+#define MN_vpcompressd 0x1ac5
+#define MN_vcmpge_ossd 0x1ad1
+#define MN_vcmple_ossd 0x1add
+#define MN_vcmpfalse_ossd 0x1ae9
+#define MN_vcmpneq_ossd 0x1af8
+#define MN_vcmpeq_ossd 0x1b05
+#define MN_vcmpgt_ossd 0x1b11
+#define MN_vcmplt_ossd 0x1b1d
+#define MN_wrssd 0x1b29
+#define MN_vfpclasssd 0x1b2f
+#define MN_vcmpnge_ussd 0x1b3a
+#define MN_vcmpnle_ussd 0x1b47
+#define MN_vcmptrue_ussd 0x1b54
+#define MN_vcmpneq_ussd 0x1b62
+#define MN_vcmpeq_ussd 0x1b6f
+#define MN_vcmpngt_ussd 0x1b7b
+#define MN_vcmpnlt_ussd 0x1b88
+#define MN_wrussd 0x1b95
+#define MN_vp4dpwssd 0x1b9c
+#define MN_vpdpwssd 0x1ba6
+#define MN_vcmpngtsd 0x1baf
+#define MN_vcmpgtsd 0x1bb9
 #define MN_cmpnltsd (MN_vcmpnltsd + 1)
-#define MN_vcmpnltsd 0x1b4a
+#define MN_vcmpnltsd 0x1bc2
 #define MN_cmpltsd (MN_vcmpltsd + 1)
-#define MN_vcmpltsd 0x1b54
-#define MN_vgetmantsd 0x1b5d
-#define MN_movntsd 0x1b68
+#define MN_vcmpltsd 0x1bcc
+#define MN_vgetmantsd 0x1bd5
+#define MN_movntsd 0x1be0
 #define MN_sqrtsd (MN_vsqrtsd + 1)
-#define MN_vsqrtsd 0x1b70
-#define MN_vbroadcastsd 0x1b78
-#define MN_vpdpbusd 0x1b85
-#define MN_tdpbusd 0x1b8e
-#define MN_vpdpwusd 0x1b96
+#define MN_vsqrtsd 0x1be8
+#define MN_vbroadcastsd 0x1bf0
+#define MN_vpdpbusd 0x1bfd
+#define MN_tdpbusd 0x1c06
+#define MN_vpdpwusd 0x1c0e
 #define MN_divsd (MN_vdivsd + 1)
-#define MN_vdivsd 0x1b9f
+#define MN_vdivsd 0x1c17
 #define MN_movsd (MN_vmovsd + 1)
-#define MN_vmovsd 0x1ba6
+#define MN_vmovsd 0x1c1e
 #define MN_maxsd (MN_vminmaxsd + 4)
-#define MN_vminmaxsd 0x1bad
+#define MN_vminmaxsd 0x1c25
 #define MN_pmaxsd (MN_vpmaxsd + 1)
-#define MN_vpmaxsd 0x1bb7
-#define MN_vmaxsd 0x1bbf
-#define MN_vucomxsd 0x1bc6
-#define MN_vcomxsd 0x1bcf
-#define MN_vfrczsd 0x1bd7
-#define MN_vp2intersectd 0x1bdf
-#define MN_vpconflictd 0x1bed
-#define MN_vpcomgtd 0x1bf9
+#define MN_vpmaxsd 0x1c2f
+#define MN_vmaxsd 0x1c37
+#define MN_vucomxsd 0x1c3e
+#define MN_vcomxsd 0x1c47
+#define MN_vfrczsd 0x1c4f
+#define MN_vp2intersectd 0x1c57
+#define MN_vpconflictd 0x1c65
+#define MN_vpcomgtd 0x1c71
 #define MN_pcmpgtd (MN_vpcmpgtd + 1)
-#define MN_vpcmpgtd 0x1c02
-#define MN_cltd 0x1c0b
-#define MN_vpcomltd 0x1c10
-#define MN_vpcmpnltd 0x1c19
-#define MN_vpcmpltd 0x1c23
-#define MN_vpopcntd 0x1c2c
-#define MN_vplzcntd 0x1c35
-#define MN_knotd 0x1c3e
-#define MN_vprotd 0x1c44
+#define MN_vpcmpgtd 0x1c7a
+#define MN_cltd 0x1c83
+#define MN_vpcomltd 0x1c88
+#define MN_vpcmpnltd 0x1c91
+#define MN_vpcmpltd 0x1c9b
+#define MN_vpopcntd 0x1ca4
+#define MN_vplzcntd 0x1cad
+#define MN_knotd 0x1cb6
+#define MN_vprotd 0x1cbc
 #define MN_std (MN_vpbroadcastd + 9)
-#define MN_vpbroadcastd 0x1c4b
-#define MN_ktestd 0x1c58
-#define MN_kortestd 0x1c5f
-#define MN_cwtd 0x1c68
-#define MN_vpcomgeud 0x1c6d
-#define MN_vpcomleud 0x1c77
-#define MN_vpcmpnleud 0x1c81
-#define MN_vpcmpleud 0x1c8c
-#define MN_vpcomfalseud 0x1c96
-#define MN_vpcomtrueud 0x1ca3
-#define MN_vpcomud 0x1caf
+#define MN_vpbroadcastd 0x1cc3
+#define MN_ktestd 0x1cd0
+#define MN_kortestd 0x1cd7
+#define MN_cwtd 0x1ce0
+#define MN_vpcomgeud 0x1ce5
+#define MN_vpcomleud 0x1cef
+#define MN_vpcmpnleud 0x1cf9
+#define MN_vpcmpleud 0x1d04
+#define MN_vpcomfalseud 0x1d0e
+#define MN_vpcomtrueud 0x1d1b
+#define MN_vpcomud 0x1d27
 #define MN_pminud (MN_vpminud + 1)
-#define MN_vpminud 0x1cb7
-#define MN_vpcmpud 0x1cbf
-#define MN_vpcomequd 0x1cc7
-#define MN_vpcomnequd 0x1cd1
-#define MN_vpcmpnequd 0x1cdc
-#define MN_vpcmpequd 0x1ce7
-#define MN_vpdpbsud 0x1cf1
-#define MN_tdpbsud 0x1cfa
-#define MN_vpdpwsud 0x1d02
-#define MN_vpcomgtud 0x1d0b
-#define MN_vpcomltud 0x1d15
-#define MN_vpcmpnltud 0x1d1f
-#define MN_vpcmpltud 0x1d2a
-#define MN_vpdpbuud 0x1d34
-#define MN_tdpbuud 0x1d3d
-#define MN_vpdpwuud 0x1d45
+#define MN_vpminud 0x1d2f
+#define MN_vpcmpud 0x1d37
+#define MN_vpcomequd 0x1d3f
+#define MN_vpcomnequd 0x1d49
+#define MN_vpcmpnequd 0x1d54
+#define MN_vpcmpequd 0x1d5f
+#define MN_vpdpbsud 0x1d69
+#define MN_tdpbsud 0x1d72
+#define MN_vpdpwsud 0x1d7a
+#define MN_vpcomgtud 0x1d83
+#define MN_vpcomltud 0x1d8d
+#define MN_vpcmpnltud 0x1d97
+#define MN_vpcmpltud 0x1da2
+#define MN_vpdpbuud 0x1dac
+#define MN_tdpbuud 0x1db5
+#define MN_vpdpwuud 0x1dbd
 #define MN_pmaxud (MN_vpmaxud + 1)
-#define MN_vpmaxud 0x1d4e
-#define MN_vpsravd 0x1d56
-#define MN_vpshldvd 0x1d5e
-#define MN_vpshrdvd 0x1d67
-#define MN_vpsllvd 0x1d70
-#define MN_vprolvd 0x1d78
-#define MN_vpsrlvd 0x1d80
+#define MN_vpmaxud 0x1dc6
+#define MN_vpsravd 0x1dce
+#define MN_vpshldvd 0x1dd6
+#define MN_vpshrdvd 0x1ddf
+#define MN_vpsllvd 0x1de8
+#define MN_vprolvd 0x1df0
+#define MN_vpsrlvd 0x1df8
 #define MN_invd (MN_wbinvd + 2)
-#define MN_wbinvd 0x1d88
-#define MN_wbnoinvd 0x1d8f
+#define MN_wbinvd 0x1e00
+#define MN_wbnoinvd 0x1e07
 #define MN_movd (MN_kmovd + 1)
 #define MN_kmovd (MN_vpmaskmovd + 5)
-#define MN_vpmaskmovd 0x1d98
-#define MN_vmovd 0x1da3
-#define MN_vprorvd 0x1da9
-#define MN_vphsubwd 0x1db1
-#define MN_cwd 0x1dba
-#define MN_vphaddwd 0x1dbe
+#define MN_vpmaskmovd 0x1e10
+#define MN_vmovd 0x1e1b
+#define MN_vprorvd 0x1e21
+#define MN_vphsubwd 0x1e29
+#define MN_cwd 0x1e32
+#define MN_vphaddwd 0x1e36
 #define MN_pmaddwd (MN_vpmaddwd + 1)
-#define MN_vpmaddwd 0x1dc7
+#define MN_vpmaddwd 0x1e3f
 #define MN_punpckhwd (MN_vpunpckhwd + 1)
-#define MN_vpunpckhwd 0x1dd0
-#define MN_kunpckwd 0x1ddb
+#define MN_vpunpckhwd 0x1e48
+#define MN_kunpckwd 0x1e53
 #define MN_punpcklwd (MN_vpunpcklwd + 1)
-#define MN_vpunpcklwd 0x1de4
-#define MN_vpmacswd 0x1def
-#define MN_vpmadcswd 0x1df8
-#define MN_vpmacsswd 0x1e02
-#define MN_vpmadcsswd 0x1e0c
-#define MN_vphadduwd 0x1e17
+#define MN_vpunpcklwd 0x1e5c
+#define MN_vpmacswd 0x1e67
+#define MN_vpmadcswd 0x1e70
+#define MN_vpmacsswd 0x1e7a
+#define MN_vpmadcsswd 0x1e84
+#define MN_vphadduwd 0x1e8f
 #define MN_pmovsxwd (MN_vpmovsxwd + 1)
-#define MN_vpmovsxwd 0x1e21
+#define MN_vpmovsxwd 0x1e99
 #define MN_pmovzxwd (MN_vpmovzxwd + 1)
-#define MN_vpmovzxwd 0x1e2b
-#define MN_movsxd 0x1e35
-#define MN_fldl2e 0x1e3c
-#define MN_jae 0x1e43
-#define MN_jnae 0x1e47
-#define MN_ccmpnae 0x1e4c
-#define MN_setnae 0x1e54
-#define MN_ctestnae 0x1e5b
-#define MN_setzunae 0x1e64
+#define MN_vpmovzxwd 0x1ea3
+#define MN_movsxd 0x1ead
+#define MN_fldl2e 0x1eb4
+#define MN_jae 0x1ebb
+#define MN_jnae 0x1ebf
+#define MN_ccmpnae 0x1ec4
+#define MN_setnae 0x1ecc
+#define MN_ctestnae 0x1ed3
+#define MN_setzunae 0x1edc
 #define MN_cmovnae (MN_fcmovnae + 1)
 #define MN_fcmovnae (MN_cfcmovnae + 1)
-#define MN_cfcmovnae 0x1e6d
-#define MN_ccmpae 0x1e77
-#define MN_setae 0x1e7e
-#define MN_ctestae 0x1e84
-#define MN_setzuae 0x1e8c
+#define MN_cfcmovnae 0x1ee5
+#define MN_ccmpae 0x1eef
+#define MN_setae 0x1ef6
+#define MN_ctestae 0x1efc
+#define MN_setzuae 0x1f04
 #define MN_cmovae (MN_fcmovae + 1)
 #define MN_fcmovae (MN_cfcmovae + 1)
-#define MN_cfcmovae 0x1e94
-#define MN_jbe 0x1e9d
-#define MN_jnbe 0x1ea1
-#define MN_ccmpnbe 0x1ea6
-#define MN_setnbe 0x1eae
-#define MN_ctestnbe 0x1eb5
-#define MN_setzunbe 0x1ebe
+#define MN_cfcmovae 0x1f0c
+#define MN_jbe 0x1f15
+#define MN_jnbe 0x1f19
+#define MN_ccmpnbe 0x1f1e
+#define MN_setnbe 0x1f26
+#define MN_ctestnbe 0x1f2d
+#define MN_setzunbe 0x1f36
 #define MN_cmovnbe (MN_fcmovnbe + 1)
 #define MN_fcmovnbe (MN_cfcmovnbe + 1)
-#define MN_cfcmovnbe 0x1ec7
-#define MN_ccmpbe 0x1ed1
-#define MN_setbe 0x1ed8
-#define MN_ctestbe 0x1ede
-#define MN_setzube 0x1ee6
+#define MN_cfcmovnbe 0x1f3f
+#define MN_ccmpbe 0x1f49
+#define MN_setbe 0x1f50
+#define MN_ctestbe 0x1f56
+#define MN_setzube 0x1f5e
 #define MN_movbe (MN_cmovbe + 1)
 #define MN_cmovbe (MN_fcmovbe + 1)
 #define MN_fcmovbe (MN_cfcmovbe + 1)
-#define MN_cfcmovbe 0x1eee
-#define MN_lfence 0x1ef7
-#define MN_mfence 0x1efe
-#define MN_sfence 0x1f05
-#define MN_cwde 0x1f0c
-#define MN_ffree 0x1f11
-#define MN_jge 0x1f17
-#define MN_jnge 0x1f1b
-#define MN_ccmpnge 0x1f20
-#define MN_setnge 0x1f28
-#define MN_ctestnge 0x1f2f
-#define MN_setzunge 0x1f38
+#define MN_cfcmovbe 0x1f66
+#define MN_lfence 0x1f6f
+#define MN_mfence 0x1f76
+#define MN_sfence 0x1f7d
+#define MN_cwde 0x1f84
+#define MN_ffree 0x1f89
+#define MN_jge 0x1f8f
+#define MN_jnge 0x1f93
+#define MN_ccmpnge 0x1f98
+#define MN_setnge 0x1fa0
+#define MN_ctestnge 0x1fa7
+#define MN_setzunge 0x1fb0
 #define MN_cmovnge (MN_cfcmovnge + 2)
-#define MN_cfcmovnge 0x1f41
-#define MN_ccmpge 0x1f4b
-#define MN_pfcmpge 0x1f52
-#define MN_setge 0x1f5a
-#define MN_ctestge 0x1f60
-#define MN_setzuge 0x1f68
+#define MN_cfcmovnge 0x1fb9
+#define MN_ccmpge 0x1fc3
+#define MN_pfcmpge 0x1fca
+#define MN_setge 0x1fd2
+#define MN_ctestge 0x1fd8
+#define MN_setzuge 0x1fe0
 #define MN_cmovge (MN_cfcmovge + 2)
-#define MN_cfcmovge 0x1f70
-#define MN_je 0x1f79
-#define MN_fscale 0x1f7c
-#define MN_jle 0x1f83
-#define MN_jnle 0x1f87
-#define MN_ccmpnle 0x1f8c
-#define MN_setnle 0x1f94
-#define MN_ctestnle 0x1f9b
-#define MN_setzunle 0x1fa4
+#define MN_cfcmovge 0x1fe8
+#define MN_je 0x1ff1
+#define MN_fscale 0x1ff4
+#define MN_jle 0x1ffb
+#define MN_jnle 0x1fff
+#define MN_ccmpnle 0x2004
+#define MN_setnle 0x200c
+#define MN_ctestnle 0x2013
+#define MN_setzunle 0x201c
 #define MN_cmovnle (MN_cfcmovnle + 2)
-#define MN_cfcmovnle 0x1fad
-#define MN_ccmple 0x1fb7
-#define MN_setle 0x1fbe
-#define MN_ctestle 0x1fc4
-#define MN_setzule 0x1fcc
+#define MN_cfcmovnle 0x2025
+#define MN_ccmple 0x202f
+#define MN_setle 0x2036
+#define MN_ctestle 0x203c
+#define MN_setzule 0x2044
 #define MN_cmovle (MN_cfcmovle + 2)
-#define MN_cfcmovle 0x1fd4
-#define MN_vmresume 0x1fdd
-#define MN_jne 0x1fe6
-#define MN_repne 0x1fea
-#define MN_ccmpne 0x1ff0
-#define MN_loopne 0x1ff7
-#define MN_setne 0x1ffe
-#define MN_ctestne 0x2004
-#define MN_setzune 0x200c
+#define MN_cfcmovle 0x204c
+#define MN_vmresume 0x2055
+#define MN_jne 0x205e
+#define MN_repne 0x2062
+#define MN_ccmpne 0x2068
+#define MN_loopne 0x206f
+#define MN_setne 0x2076
+#define MN_ctestne 0x207c
+#define MN_setzune 0x2084
 #define MN_cmovne (MN_fcmovne + 1)
 #define MN_fcmovne (MN_cfcmovne + 1)
-#define MN_cfcmovne 0x2014
-#define MN_repe 0x201d
-#define MN_jpe 0x2022
-#define MN_ccmpe 0x2026
-#define MN_loope 0x202c
-#define MN_setpe 0x2032
-#define MN_setzupe 0x2038
+#define MN_cfcmovne 0x208c
+#define MN_repe 0x2095
+#define MN_jpe 0x209a
+#define MN_ccmpe 0x209e
+#define MN_loope 0x20a4
+#define MN_setpe 0x20aa
+#define MN_setzupe 0x20b0
 #define MN_cmovpe (MN_cfcmovpe + 2)
-#define MN_cfcmovpe 0x2040
-#define MN_cdqe 0x2049
-#define MN_xacquire 0x204e
-#define MN_xstore 0x2057
-#define MN_rdfsbase 0x205e
-#define MN_wrfsbase 0x2067
-#define MN_rdgsbase 0x2070
-#define MN_wrgsbase 0x2079
-#define MN_tilerelease 0x2082
-#define MN_xrelease 0x208e
+#define MN_cfcmovpe 0x20b8
+#define MN_cdqe 0x20c1
+#define MN_xacquire 0x20c6
+#define MN_xstore 0x20cf
+#define MN_rdfsbase 0x20d6
+#define MN_wrfsbase 0x20df
+#define MN_rdgsbase 0x20e8
+#define MN_wrgsbase 0x20f1
+#define MN_tilerelease 0x20fa
+#define MN_xrelease 0x2106
 #define MN_pause (MN_tpause + 1)
-#define MN_tpause 0x2097
-#define MN_pvalidate 0x209e
-#define MN_rmpupdate 0x20a8
-#define MN_sete 0x20b2
-#define MN_vmwrite 0x20b7
-#define MN_ptwrite 0x20bf
-#define MN_cldemote 0x20c7
-#define MN_cteste 0x20d0
-#define MN_sha1nexte 0x20d7
-#define MN_setzue 0x20e1
-#define MN_leave 0x20e8
-#define MN_fsave 0x20ee
-#define MN_vmsave 0x20f4
-#define MN_fnsave 0x20fb
+#define MN_tpause 0x210f
+#define MN_pvalidate 0x2116
+#define MN_rmpupdate 0x2120
+#define MN_sete 0x212a
+#define MN_vmwrite 0x212f
+#define MN_ptwrite 0x2137
+#define MN_cldemote 0x213f
+#define MN_cteste 0x2148
+#define MN_sha1nexte 0x214f
+#define MN_setzue 0x2159
+#define MN_leave 0x2160
+#define MN_fsave 0x2166
+#define MN_vmsave 0x216c
+#define MN_fnsave 0x2173
 #define MN_xsave (MN_fxsave + 1)
-#define MN_fxsave 0x2102
+#define MN_fxsave 0x217a
 #define MN_cmove (MN_fcmove + 1)
 #define MN_fcmove (MN_cfcmove + 1)
-#define MN_cfcmove 0x2109
-#define MN_serialize 0x2111
-#define MN_vmxoff 0x211b
-#define MN_lahf 0x2122
-#define MN_sahf 0x2127
-#define MN_pushf 0x212c
-#define MN_ccmpf 0x2132
-#define MN_popf 0x2138
-#define MN_bsf 0x213d
-#define MN_retf 0x2141
-#define MN_ctestf 0x2146
-#define MN_neg 0x214d
-#define MN_ldtilecfg 0x2151
-#define MN_sttilecfg 0x215b
+#define MN_cfcmove 0x2181
+#define MN_serialize 0x2189
+#define MN_vmxoff 0x2193
+#define MN_lahf 0x219a
+#define MN_sahf 0x219f
+#define MN_pushf 0x21a4
+#define MN_ccmpf 0x21aa
+#define MN_popf 0x21b0
+#define MN_bsf 0x21b5
+#define MN_retf 0x21b9
+#define MN_ctestf 0x21be
+#define MN_neg 0x21c5
+#define MN_ldtilecfg 0x21c9
+#define MN_sttilecfg 0x21d3
 #define MN_xchg (MN_cmpxchg + 3)
-#define MN_cmpxchg 0x2165
-#define MN_pconfig 0x216d
-#define MN_jg 0x2175
-#define MN_jng 0x2178
-#define MN_ccmpng 0x217c
-#define MN_xstore_rng 0x2183
-#define MN_xstorerng 0x218e
-#define MN_setng 0x2198
-#define MN_ctestng 0x219e
-#define MN_setzung 0x21a6
+#define MN_cmpxchg 0x21dd
+#define MN_pconfig 0x21e5
+#define MN_jg 0x21ed
+#define MN_jng 0x21f0
+#define MN_ccmpng 0x21f4
+#define MN_xstore_rng 0x21fb
+#define MN_xstorerng 0x2206
+#define MN_setng 0x2210
+#define MN_ctestng 0x2216
+#define MN_setzung 0x221e
 #define MN_cmovng (MN_cfcmovng + 2)
-#define MN_cfcmovng 0x21ae
-#define MN_invlpg 0x21b7
-#define MN_ccmpg 0x21be
-#define MN_setg 0x21c4
-#define MN_ctestg 0x21c9
-#define MN_setzug 0x21d0
+#define MN_cfcmovng 0x2226
+#define MN_invlpg 0x222f
+#define MN_ccmpg 0x2236
+#define MN_setg 0x223c
+#define MN_ctestg 0x2241
+#define MN_setzug 0x2248
 #define MN_cmovg (MN_cfcmovg + 2)
-#define MN_cfcmovg 0x21d7
-#define MN_tcvtrowps2bf16h 0x21df
-#define MN_vmlaunch 0x21ef
-#define MN_prefetch 0x21f8
-#define MN_fxch 0x2201
-#define MN_tcvtrowps2phh 0x2206
-#define MN_vfmaddsub231ph 0x2214
-#define MN_vfmsub231ph 0x2223
-#define MN_vfnmsub231ph 0x222f
-#define MN_vfmsubadd231ph 0x223c
-#define MN_vfmadd231ph 0x224b
-#define MN_vfnmadd231ph 0x2257
-#define MN_vfmaddsub132ph 0x2264
-#define MN_vfmsub132ph 0x2273
-#define MN_vfnmsub132ph 0x227f
-#define MN_vfmsubadd132ph 0x228c
-#define MN_vfmadd132ph 0x229b
-#define MN_vfnmadd132ph 0x22a7
-#define MN_vcvthf82ph 0x22b4
-#define MN_vcvtpd2ph 0x22bf
-#define MN_vcvtdq2ph 0x22c9
-#define MN_vcvtudq2ph 0x22d3
-#define MN_vcvtqq2ph 0x22de
-#define MN_vcvtuqq2ph 0x22e8
-#define MN_vcvtps2ph 0x22f3
-#define MN_vcvtw2ph 0x22fd
-#define MN_vcvtuw2ph 0x2306
-#define MN_vfmaddsub213ph 0x2310
-#define MN_vfmsub213ph 0x231f
-#define MN_vfnmsub213ph 0x232b
-#define MN_vfmsubadd213ph 0x2338
-#define MN_vfmadd213ph 0x2347
-#define MN_vfnmadd213ph 0x2353
-#define MN_vsubph 0x2360
-#define MN_vfcmaddcph 0x2367
-#define MN_vfmaddcph 0x2372
-#define MN_vfcmulcph 0x237c
-#define MN_vfmulcph 0x2386
-#define MN_vaddph 0x238f
-#define MN_vcmpunordph 0x2396
-#define MN_vcmpordph 0x23a2
-#define MN_vreduceph 0x23ac
-#define MN_vcmpngeph 0x23b6
-#define MN_vcmpgeph 0x23c0
-#define MN_vrndscaleph 0x23c9
-#define MN_vcmpnleph 0x23d5
-#define MN_vcmpleph 0x23df
-#define MN_vcmpfalseph 0x23e8
-#define MN_vcmptrueph 0x23f4
-#define MN_vscalefph 0x23ff
-#define MN_vmulph 0x2409
-#define MN_vminph 0x2410
-#define MN_vrcpph 0x2417
-#define MN_vcmpph 0x241e
-#define MN_vgetexpph 0x2425
-#define MN_vcmpunord_qph 0x242f
-#define MN_vcmpord_qph 0x243d
-#define MN_vcmpneqph 0x2449
-#define MN_vcmpeqph 0x2453
-#define MN_vcmpge_oqph 0x245c
-#define MN_vcmple_oqph 0x2468
-#define MN_vcmpfalse_oqph 0x2474
-#define MN_vcmpneq_oqph 0x2483
-#define MN_vcmpeq_oqph 0x2490
-#define MN_vcmpgt_oqph 0x249c
-#define MN_vcmplt_oqph 0x24a8
-#define MN_vcmpnge_uqph 0x24b4
-#define MN_vcmpnle_uqph 0x24c1
-#define MN_vcmptrue_uqph 0x24ce
-#define MN_vcmpneq_uqph 0x24dc
-#define MN_vcmpeq_uqph 0x24e9
-#define MN_vcmpngt_uqph 0x24f5
-#define MN_vcmpnlt_uqph 0x2502
-#define MN_vcmpunord_sph 0x250f
-#define MN_vcmpord_sph 0x251d
-#define MN_vcmpge_osph 0x2529
-#define MN_vcmple_osph 0x2535
-#define MN_vcmpfalse_osph 0x2541
-#define MN_vcmpneq_osph 0x2550
-#define MN_vcmpeq_osph 0x255d
-#define MN_vcmpgt_osph 0x2569
-#define MN_vcmplt_osph 0x2575
-#define MN_vfpclassph 0x2581
-#define MN_vcmpnge_usph 0x258c
-#define MN_vcmpnle_usph 0x2599
-#define MN_vcmptrue_usph 0x25a6
-#define MN_vcmpneq_usph 0x25b4
-#define MN_vcmpeq_usph 0x25c1
-#define MN_vcmpngt_usph 0x25cd
-#define MN_vcmpnlt_usph 0x25da
-#define MN_vcmpngtph 0x25e7
-#define MN_vcmpgtph 0x25f1
-#define MN_vcmpnltph 0x25fa
-#define MN_vcmpltph 0x2604
-#define MN_vgetmantph 0x260d
-#define MN_vrsqrtph 0x2618
-#define MN_vsqrtph 0x2621
-#define MN_vdivph 0x2629
-#define MN_vminmaxph 0x2630
-#define MN_vmaxph 0x263a
-#define MN_vpmacsdqh 0x2641
-#define MN_vpmacssdqh 0x264b
-#define MN_vfmsub231sh 0x2656
-#define MN_vfnmsub231sh 0x2662
-#define MN_vfmadd231sh 0x266f
-#define MN_vfnmadd231sh 0x267b
-#define MN_vfmsub132sh 0x2688
-#define MN_vfnmsub132sh 0x2694
-#define MN_vfmadd132sh 0x26a1
-#define MN_vfnmadd132sh 0x26ad
-#define MN_vcvtsd2sh 0x26ba
-#define MN_vcvtsi2sh 0x26c4
-#define MN_vcvtusi2sh 0x26ce
-#define MN_vcvtss2sh 0x26d9
-#define MN_vfmsub213sh 0x26e3
-#define MN_vfnmsub213sh 0x26ef
-#define MN_vfmadd213sh 0x26fc
-#define MN_vfnmadd213sh 0x2708
-#define MN_psmash 0x2715
-#define MN_vsubsh 0x271c
-#define MN_vfcmaddcsh 0x2723
-#define MN_vfmaddcsh 0x272e
-#define MN_vfcmulcsh 0x2738
-#define MN_vfmulcsh 0x2742
-#define MN_vaddsh 0x274b
-#define MN_vcmpunordsh 0x2752
-#define MN_vcmpordsh 0x275e
-#define MN_vreducesh 0x2768
-#define MN_vcmpngesh 0x2772
-#define MN_vcmpgesh 0x277c
-#define MN_vrndscalesh 0x2785
-#define MN_vcmpnlesh 0x2791
-#define MN_vcmplesh 0x279b
-#define MN_vcmpfalsesh 0x27a4
-#define MN_vcmptruesh 0x27b0
-#define MN_vscalefsh 0x27bb
-#define MN_vucomish 0x27c5
-#define MN_vcomish 0x27ce
-#define MN_vmulsh 0x27d6
-#define MN_vminsh 0x27dd
-#define MN_vrcpsh 0x27e4
-#define MN_vcmpsh 0x27eb
-#define MN_vgetexpsh 0x27f2
-#define MN_vcmpunord_qsh 0x27fc
-#define MN_vcmpord_qsh 0x280a
-#define MN_vcmpneqsh 0x2816
-#define MN_vcmpeqsh 0x2820
-#define MN_vcmpge_oqsh 0x2829
-#define MN_vcmple_oqsh 0x2835
-#define MN_vcmpfalse_oqsh 0x2841
-#define MN_vcmpneq_oqsh 0x2850
-#define MN_vcmpeq_oqsh 0x285d
-#define MN_vcmpgt_oqsh 0x2869
-#define MN_vcmplt_oqsh 0x2875
-#define MN_vcmpnge_uqsh 0x2881
-#define MN_vcmpnle_uqsh 0x288e
-#define MN_vcmptrue_uqsh 0x289b
-#define MN_vcmpneq_uqsh 0x28a9
-#define MN_vcmpeq_uqsh 0x28b6
-#define MN_vcmpngt_uqsh 0x28c2
-#define MN_vcmpnlt_uqsh 0x28cf
-#define MN_vcmpunord_ssh 0x28dc
-#define MN_vcmpord_ssh 0x28ea
-#define MN_vcmpge_ossh 0x28f6
-#define MN_vcmple_ossh 0x2902
-#define MN_vcmpfalse_ossh 0x290e
-#define MN_vcmpneq_ossh 0x291d
-#define MN_vcmpeq_ossh 0x292a
-#define MN_vcmpgt_ossh 0x2936
-#define MN_vcmplt_ossh 0x2942
-#define MN_vfpclasssh 0x294e
-#define MN_vcmpnge_ussh 0x2959
-#define MN_vcmpnle_ussh 0x2966
-#define MN_vcmptrue_ussh 0x2973
-#define MN_vcmpneq_ussh 0x2981
-#define MN_vcmpeq_ussh 0x298e
-#define MN_vcmpngt_ussh 0x299a
-#define MN_vcmpnlt_ussh 0x29a7
-#define MN_vcmpngtsh 0x29b4
-#define MN_vcmpgtsh 0x29be
-#define MN_vcmpnltsh 0x29c7
-#define MN_vcmpltsh 0x29d1
-#define MN_vgetmantsh 0x29da
-#define MN_vrsqrtsh 0x29e5
-#define MN_vsqrtsh 0x29ee
-#define MN_clflush 0x29f6
-#define MN_push 0x29fe
-#define MN_vdivsh 0x2a03
-#define MN_vmovsh 0x2a0a
-#define MN_vminmaxsh 0x2a11
-#define MN_vmaxsh 0x2a1b
-#define MN_vucomxsh 0x2a22
-#define MN_vcomxsh 0x2a2b
-#define MN_blci 0x2a33
-#define MN_clgi 0x2a38
-#define MN_stgi 0x2a3d
-#define MN_bzhi 0x2a42
-#define MN_cli 0x2a47
-#define MN_fcomi 0x2a4b
-#define MN_fucomi 0x2a51
-#define MN_feni 0x2a58
-#define MN_fneni 0x2a5d
-#define MN_cvttpd2pi 0x2a63
-#define MN_cvtpd2pi 0x2a6d
-#define MN_cvttps2pi 0x2a76
-#define MN_cvtps2pi 0x2a80
-#define MN_fldpi 0x2a89
-#define MN_senduipi 0x2a8f
-#define MN_fcompi 0x2a98
-#define MN_fucompi 0x2a9f
-#define MN_movdiri 0x2aa7
+#define MN_cfcmovg 0x224f
+#define MN_tcvtrowps2bf16h 0x2257
+#define MN_vmlaunch 0x2267
+#define MN_prefetch 0x2270
+#define MN_fxch 0x2279
+#define MN_tcvtrowps2phh 0x227e
+#define MN_vfmaddsub231ph 0x228c
+#define MN_vfmsub231ph 0x229b
+#define MN_vfnmsub231ph 0x22a7
+#define MN_vfmsubadd231ph 0x22b4
+#define MN_vfmadd231ph 0x22c3
+#define MN_vfnmadd231ph 0x22cf
+#define MN_vfmaddsub132ph 0x22dc
+#define MN_vfmsub132ph 0x22eb
+#define MN_vfnmsub132ph 0x22f7
+#define MN_vfmsubadd132ph 0x2304
+#define MN_vfmadd132ph 0x2313
+#define MN_vfnmadd132ph 0x231f
+#define MN_vcvthf82ph 0x232c
+#define MN_vcvtpd2ph 0x2337
+#define MN_vcvtdq2ph 0x2341
+#define MN_vcvtudq2ph 0x234b
+#define MN_vcvtqq2ph 0x2356
+#define MN_vcvtuqq2ph 0x2360
+#define MN_vcvtps2ph 0x236b
+#define MN_vcvtw2ph 0x2375
+#define MN_vcvtuw2ph 0x237e
+#define MN_vfmaddsub213ph 0x2388
+#define MN_vfmsub213ph 0x2397
+#define MN_vfnmsub213ph 0x23a3
+#define MN_vfmsubadd213ph 0x23b0
+#define MN_vfmadd213ph 0x23bf
+#define MN_vfnmadd213ph 0x23cb
+#define MN_vsubph 0x23d8
+#define MN_vfcmaddcph 0x23df
+#define MN_vfmaddcph 0x23ea
+#define MN_vfcmulcph 0x23f4
+#define MN_vfmulcph 0x23fe
+#define MN_vaddph 0x2407
+#define MN_vcmpunordph 0x240e
+#define MN_vcmpordph 0x241a
+#define MN_vreduceph 0x2424
+#define MN_vcmpngeph 0x242e
+#define MN_vcmpgeph 0x2438
+#define MN_vrndscaleph 0x2441
+#define MN_vcmpnleph 0x244d
+#define MN_vcmpleph 0x2457
+#define MN_vcmpfalseph 0x2460
+#define MN_vcmptrueph 0x246c
+#define MN_vscalefph 0x2477
+#define MN_vmulph 0x2481
+#define MN_vminph 0x2488
+#define MN_vrcpph 0x248f
+#define MN_vcmpph 0x2496
+#define MN_vgetexpph 0x249d
+#define MN_vcmpunord_qph 0x24a7
+#define MN_vcmpord_qph 0x24b5
+#define MN_vcmpneqph 0x24c1
+#define MN_vcmpeqph 0x24cb
+#define MN_vcmpge_oqph 0x24d4
+#define MN_vcmple_oqph 0x24e0
+#define MN_vcmpfalse_oqph 0x24ec
+#define MN_vcmpneq_oqph 0x24fb
+#define MN_vcmpeq_oqph 0x2508
+#define MN_vcmpgt_oqph 0x2514
+#define MN_vcmplt_oqph 0x2520
+#define MN_vcmpnge_uqph 0x252c
+#define MN_vcmpnle_uqph 0x2539
+#define MN_vcmptrue_uqph 0x2546
+#define MN_vcmpneq_uqph 0x2554
+#define MN_vcmpeq_uqph 0x2561
+#define MN_vcmpngt_uqph 0x256d
+#define MN_vcmpnlt_uqph 0x257a
+#define MN_vcmpunord_sph 0x2587
+#define MN_vcmpord_sph 0x2595
+#define MN_vcmpge_osph 0x25a1
+#define MN_vcmple_osph 0x25ad
+#define MN_vcmpfalse_osph 0x25b9
+#define MN_vcmpneq_osph 0x25c8
+#define MN_vcmpeq_osph 0x25d5
+#define MN_vcmpgt_osph 0x25e1
+#define MN_vcmplt_osph 0x25ed
+#define MN_vfpclassph 0x25f9
+#define MN_vcmpnge_usph 0x2604
+#define MN_vcmpnle_usph 0x2611
+#define MN_vcmptrue_usph 0x261e
+#define MN_vcmpneq_usph 0x262c
+#define MN_vcmpeq_usph 0x2639
+#define MN_vcmpngt_usph 0x2645
+#define MN_vcmpnlt_usph 0x2652
+#define MN_vcmpngtph 0x265f
+#define MN_vcmpgtph 0x2669
+#define MN_vcmpnltph 0x2672
+#define MN_vcmpltph 0x267c
+#define MN_vgetmantph 0x2685
+#define MN_vrsqrtph 0x2690
+#define MN_vsqrtph 0x2699
+#define MN_vdivph 0x26a1
+#define MN_vminmaxph 0x26a8
+#define MN_vmaxph 0x26b2
+#define MN_vpmacsdqh 0x26b9
+#define MN_vpmacssdqh 0x26c3
+#define MN_vfmsub231sh 0x26ce
+#define MN_vfnmsub231sh 0x26da
+#define MN_vfmadd231sh 0x26e7
+#define MN_vfnmadd231sh 0x26f3
+#define MN_vfmsub132sh 0x2700
+#define MN_vfnmsub132sh 0x270c
+#define MN_vfmadd132sh 0x2719
+#define MN_vfnmadd132sh 0x2725
+#define MN_vcvtsd2sh 0x2732
+#define MN_vcvtsi2sh 0x273c
+#define MN_vcvtusi2sh 0x2746
+#define MN_vcvtss2sh 0x2751
+#define MN_vfmsub213sh 0x275b
+#define MN_vfnmsub213sh 0x2767
+#define MN_vfmadd213sh 0x2774
+#define MN_vfnmadd213sh 0x2780
+#define MN_psmash 0x278d
+#define MN_vsubsh 0x2794
+#define MN_vfcmaddcsh 0x279b
+#define MN_vfmaddcsh 0x27a6
+#define MN_vfcmulcsh 0x27b0
+#define MN_vfmulcsh 0x27ba
+#define MN_vaddsh 0x27c3
+#define MN_vcmpunordsh 0x27ca
+#define MN_vcmpordsh 0x27d6
+#define MN_vreducesh 0x27e0
+#define MN_vcmpngesh 0x27ea
+#define MN_vcmpgesh 0x27f4
+#define MN_vrndscalesh 0x27fd
+#define MN_vcmpnlesh 0x2809
+#define MN_vcmplesh 0x2813
+#define MN_vcmpfalsesh 0x281c
+#define MN_vcmptruesh 0x2828
+#define MN_vscalefsh 0x2833
+#define MN_vucomish 0x283d
+#define MN_vcomish 0x2846
+#define MN_vmulsh 0x284e
+#define MN_vminsh 0x2855
+#define MN_vrcpsh 0x285c
+#define MN_vcmpsh 0x2863
+#define MN_vgetexpsh 0x286a
+#define MN_vcmpunord_qsh 0x2874
+#define MN_vcmpord_qsh 0x2882
+#define MN_vcmpneqsh 0x288e
+#define MN_vcmpeqsh 0x2898
+#define MN_vcmpge_oqsh 0x28a1
+#define MN_vcmple_oqsh 0x28ad
+#define MN_vcmpfalse_oqsh 0x28b9
+#define MN_vcmpneq_oqsh 0x28c8
+#define MN_vcmpeq_oqsh 0x28d5
+#define MN_vcmpgt_oqsh 0x28e1
+#define MN_vcmplt_oqsh 0x28ed
+#define MN_vcmpnge_uqsh 0x28f9
+#define MN_vcmpnle_uqsh 0x2906
+#define MN_vcmptrue_uqsh 0x2913
+#define MN_vcmpneq_uqsh 0x2921
+#define MN_vcmpeq_uqsh 0x292e
+#define MN_vcmpngt_uqsh 0x293a
+#define MN_vcmpnlt_uqsh 0x2947
+#define MN_vcmpunord_ssh 0x2954
+#define MN_vcmpord_ssh 0x2962
+#define MN_vcmpge_ossh 0x296e
+#define MN_vcmple_ossh 0x297a
+#define MN_vcmpfalse_ossh 0x2986
+#define MN_vcmpneq_ossh 0x2995
+#define MN_vcmpeq_ossh 0x29a2
+#define MN_vcmpgt_ossh 0x29ae
+#define MN_vcmplt_ossh 0x29ba
+#define MN_vfpclasssh 0x29c6
+#define MN_vcmpnge_ussh 0x29d1
+#define MN_vcmpnle_ussh 0x29de
+#define MN_vcmptrue_ussh 0x29eb
+#define MN_vcmpneq_ussh 0x29f9
+#define MN_vcmpeq_ussh 0x2a06
+#define MN_vcmpngt_ussh 0x2a12
+#define MN_vcmpnlt_ussh 0x2a1f
+#define MN_vcmpngtsh 0x2a2c
+#define MN_vcmpgtsh 0x2a36
+#define MN_vcmpnltsh 0x2a3f
+#define MN_vcmpltsh 0x2a49
+#define MN_vgetmantsh 0x2a52
+#define MN_vrsqrtsh 0x2a5d
+#define MN_vsqrtsh 0x2a66
+#define MN_clflush 0x2a6e
+#define MN_push 0x2a76
+#define MN_vdivsh 0x2a7b
+#define MN_vmovsh 0x2a82
+#define MN_vminmaxsh 0x2a89
+#define MN_vmaxsh 0x2a93
+#define MN_vucomxsh 0x2a9a
+#define MN_vcomxsh 0x2aa3
+#define MN_blci 0x2aab
+#define MN_clgi 0x2ab0
+#define MN_stgi 0x2ab5
+#define MN_bzhi 0x2aba
+#define MN_cli 0x2abf
+#define MN_fcomi 0x2ac3
+#define MN_fucomi 0x2ac9
+#define MN_feni 0x2ad0
+#define MN_fneni 0x2ad5
+#define MN_cvttpd2pi 0x2adb
+#define MN_cvtpd2pi 0x2ae5
+#define MN_cvttps2pi 0x2aee
+#define MN_cvtps2pi 0x2af8
+#define MN_fldpi 0x2b01
+#define MN_senduipi 0x2b07
+#define MN_fcompi 0x2b10
+#define MN_fucompi 0x2b17
+#define MN_movdiri 0x2b1f
 #define MN_pcmpestri (MN_vpcmpestri + 1)
-#define MN_vpcmpestri 0x2aaf
+#define MN_vpcmpestri 0x2b27
 #define MN_pcmpistri (MN_vpcmpistri + 1)
-#define MN_vpcmpistri 0x2aba
+#define MN_vpcmpistri 0x2b32
 #define MN_cvttsd2si (MN_vcvttsd2si + 1)
-#define MN_vcvttsd2si 0x2ac5
+#define MN_vcvttsd2si 0x2b3d
 #define MN_cvtsd2si (MN_vcvtsd2si + 1)
-#define MN_vcvtsd2si 0x2ad0
-#define MN_vcvttsh2si 0x2ada
-#define MN_vcvtsh2si 0x2ae5
+#define MN_vcvtsd2si 0x2b48
+#define MN_vcvttsh2si 0x2b52
+#define MN_vcvtsh2si 0x2b5d
 #define MN_cvttss2si (MN_vcvttss2si + 1)
-#define MN_vcvttss2si 0x2aef
+#define MN_vcvttss2si 0x2b67
 #define MN_cvtss2si (MN_vcvtss2si + 1)
-#define MN_vcvtss2si 0x2afa
-#define MN_fdisi 0x2b04
-#define MN_fndisi 0x2b0a
-#define MN_blsi 0x2b11
-#define MN_vcvttsd2usi 0x2b16
-#define MN_vcvtsd2usi 0x2b22
-#define MN_vcvttsh2usi 0x2b2d
-#define MN_vcvtsh2usi 0x2b39
-#define MN_vcvttss2usi 0x2b44
-#define MN_vcvtss2usi 0x2b50
-#define MN_movnti 0x2b5b
-#define MN_sti 0x2b62
-#define MN_clui 0x2b66
+#define MN_vcvtss2si 0x2b72
+#define MN_fdisi 0x2b7c
+#define MN_fndisi 0x2b82
+#define MN_blsi 0x2b89
+#define MN_vcvttsd2usi 0x2b8e
+#define MN_vcvtsd2usi 0x2b9a
+#define MN_vcvttsh2usi 0x2ba5
+#define MN_vcvtsh2usi 0x2bb1
+#define MN_vcvttss2usi 0x2bbc
+#define MN_vcvtss2usi 0x2bc8
+#define MN_movnti 0x2bd3
+#define MN_sti 0x2bda
+#define MN_clui 0x2bde
 #define MN_stui (MN_testui + 2)
-#define MN_testui 0x2b6b
-#define MN_notrack 0x2b72
-#define MN_lock 0x2b7a
-#define MN_bndmk 0x2b7f
-#define MN_xresldtrk 0x2b85
-#define MN_xsusldtrk 0x2b8f
-#define MN_blcmsk 0x2b99
-#define MN_blsmsk 0x2ba0
-#define MN_tzmsk 0x2ba7
-#define MN_tcvtrowps2bf16l 0x2bad
-#define MN_sal 0x2bbd
-#define MN_lwpval 0x2bc1
-#define MN_bndcl 0x2bc8
-#define MN_rcl 0x2bce
-#define MN_tcvtrowps2phl 0x2bd2
-#define MN_shl 0x2be0
-#define MN_jl 0x2be4
-#define MN_aesdec256kl 0x2be7
-#define MN_aesenc256kl 0x2bf3
-#define MN_aesdecwide256kl 0x2bff
-#define MN_aesencwide256kl 0x2c0f
-#define MN_aesdec128kl 0x2c1f
-#define MN_aesenc128kl 0x2c2b
-#define MN_aesdecwide128kl 0x2c37
-#define MN_aesencwide128kl 0x2c47
+#define MN_testui 0x2be3
+#define MN_notrack 0x2bea
+#define MN_lock 0x2bf2
+#define MN_bndmk 0x2bf7
+#define MN_xresldtrk 0x2bfd
+#define MN_xsusldtrk 0x2c07
+#define MN_blcmsk 0x2c11
+#define MN_blsmsk 0x2c18
+#define MN_tzmsk 0x2c1f
+#define MN_tcvtrowps2bf16l 0x2c25
+#define MN_sal 0x2c35
+#define MN_lwpval 0x2c39
+#define MN_bndcl 0x2c40
+#define MN_rcl 0x2c46
+#define MN_tcvtrowps2phl 0x2c4a
+#define MN_shl 0x2c58
+#define MN_jl 0x2c5c
+#define MN_aesdec256kl 0x2c5f
+#define MN_aesenc256kl 0x2c6b
+#define MN_aesdecwide256kl 0x2c77
+#define MN_aesencwide256kl 0x2c87
+#define MN_aesdec128kl 0x2c97
+#define MN_aesenc128kl 0x2ca3
+#define MN_aesdecwide128kl 0x2caf
+#define MN_aesencwide128kl 0x2cbf
 #define MN_call (MN_tdcall + 2)
-#define MN_tdcall 0x2c57
-#define MN_lcall 0x2c5e
-#define MN_seamcall 0x2c64
-#define MN_vmmcall 0x2c6d
-#define MN_vmcall 0x2c75
-#define MN_syscall 0x2c7c
-#define MN_vzeroall 0x2c84
-#define MN_fildll 0x2c8d
-#define MN_blcfill 0x2c94
-#define MN_blsfill 0x2c9c
-#define MN_fistpll 0x2ca4
-#define MN_fisttpll 0x2cac
-#define MN_jnl 0x2cb5
-#define MN_ccmpnl 0x2cb9
-#define MN_setnl 0x2cc0
-#define MN_ctestnl 0x2cc6
-#define MN_setzunl 0x2cce
+#define MN_tdcall 0x2ccf
+#define MN_lcall 0x2cd6
+#define MN_seamcall 0x2cdc
+#define MN_vmmcall 0x2ce5
+#define MN_vmcall 0x2ced
+#define MN_syscall 0x2cf4
+#define MN_vzeroall 0x2cfc
+#define MN_fildll 0x2d05
+#define MN_blcfill 0x2d0c
+#define MN_blsfill 0x2d14
+#define MN_fistpll 0x2d1c
+#define MN_fisttpll 0x2d24
+#define MN_jnl 0x2d2d
+#define MN_ccmpnl 0x2d31
+#define MN_setnl 0x2d38
+#define MN_ctestnl 0x2d3e
+#define MN_setzunl 0x2d46
 #define MN_cmovnl (MN_cfcmovnl + 2)
-#define MN_cfcmovnl 0x2cd6
-#define MN_rol 0x2cdf
-#define MN_ccmpl 0x2ce3
-#define MN_arpl 0x2ce9
-#define MN_vpmacsdql 0x2cee
-#define MN_vpmacssdql 0x2cf8
-#define MN_lsl 0x2d03
-#define MN_movsl 0x2d07
-#define MN_setl 0x2d0d
-#define MN_ctestl 0x2d12
-#define MN_cwtl 0x2d19
+#define MN_cfcmovnl 0x2d4e
+#define MN_rol 0x2d57
+#define MN_ccmpl 0x2d5b
+#define MN_arpl 0x2d61
+#define MN_vpmacsdql 0x2d66
+#define MN_vpmacssdql 0x2d70
+#define MN_lsl 0x2d7b
+#define MN_movsl 0x2d7f
+#define MN_setl 0x2d85
+#define MN_ctestl 0x2d8a
+#define MN_cwtl 0x2d91
 #define MN_mul (MN_fmul + 1)
 #define MN_fmul (MN_pfmul + 1)
-#define MN_pfmul 0x2d1e
+#define MN_pfmul 0x2d96
 #define MN_imul (MN_fimul + 1)
-#define MN_fimul 0x2d24
-#define MN_montmul 0x2d2a
-#define MN_setzul 0x2d32
+#define MN_fimul 0x2d9c
+#define MN_montmul 0x2da2
+#define MN_setzul 0x2daa
 #define MN_cmovl (MN_cfcmovl + 2)
-#define MN_cfcmovl 0x2d39
-#define MN_vpmovb2m 0x2d41
-#define MN_vpmovd2m 0x2d4a
-#define MN_vpmovq2m 0x2d53
-#define MN_vpmovw2m 0x2d5c
-#define MN_aam 0x2d65
-#define MN_fxam 0x2d69
-#define MN_fprem 0x2d6e
-#define MN_fcom 0x2d74
-#define MN_ficom 0x2d79
-#define MN_fucom 0x2d7f
-#define MN_fsetpm 0x2d85
-#define MN_fnsetpm 0x2d8c
-#define MN_frstpm 0x2d94
-#define MN_vpperm 0x2d9b
+#define MN_cfcmovl 0x2db1
+#define MN_vpmovb2m 0x2db9
+#define MN_vpmovd2m 0x2dc2
+#define MN_vpmovq2m 0x2dcb
+#define MN_vpmovw2m 0x2dd4
+#define MN_aam 0x2ddd
+#define MN_fxam 0x2de1
+#define MN_fprem 0x2de6
+#define MN_fcom 0x2dec
+#define MN_ficom 0x2df1
+#define MN_fucom 0x2df7
+#define MN_fsetpm 0x2dfd
+#define MN_fnsetpm 0x2e04
+#define MN_frstpm 0x2e0c
+#define MN_vpperm 0x2e13
 #define MN_pcmpestrm (MN_vpcmpestrm + 1)
-#define MN_vpcmpestrm 0x2da2
+#define MN_vpcmpestrm 0x2e1a
 #define MN_pcmpistrm (MN_vpcmpistrm + 1)
-#define MN_vpcmpistrm 0x2dad
-#define MN_rsm 0x2db8
-#define MN_fpatan 0x2dbc
-#define MN_fptan 0x2dc3
-#define MN_bndcn 0x2dc9
+#define MN_vpcmpistrm 0x2e25
+#define MN_rsm 0x2e30
+#define MN_fpatan 0x2e34
+#define MN_fptan 0x2e3b
+#define MN_bndcn 0x2e41
 #define MN_andn (MN_pandn + 1)
 #define MN_pandn (MN_vpandn + 1)
-#define MN_vpandn 0x2dcf
+#define MN_vpandn 0x2e47
 #define MN_in (MN_xbegin + 4)
-#define MN_xbegin 0x2dd6
-#define MN_pfmin 0x2ddd
-#define MN_fsin 0x2de3
-#define MN_vmxon 0x2de8
-#define MN_vmrun 0x2dee
-#define MN_jo 0x2df4
-#define MN_jno 0x2df7
-#define MN_ccmpno 0x2dfb
-#define MN_setno 0x2e02
-#define MN_ctestno 0x2e08
-#define MN_setzuno 0x2e10
+#define MN_xbegin 0x2e4e
+#define MN_pfmin 0x2e55
+#define MN_fsin 0x2e5b
+#define MN_vmxon 0x2e60
+#define MN_vmrun 0x2e66
+#define MN_jo 0x2e6c
+#define MN_jno 0x2e6f
+#define MN_ccmpno 0x2e73
+#define MN_setno 0x2e7a
+#define MN_ctestno 0x2e80
+#define MN_setzuno 0x2e88
 #define MN_cmovno (MN_cfcmovno + 2)
-#define MN_cfcmovno 0x2e18
-#define MN_jpo 0x2e21
-#define MN_ccmpo 0x2e25
-#define MN_setpo 0x2e2b
-#define MN_setzupo 0x2e31
+#define MN_cfcmovno 0x2e90
+#define MN_jpo 0x2e99
+#define MN_ccmpo 0x2e9d
+#define MN_setpo 0x2ea3
+#define MN_setzupo 0x2ea9
 #define MN_cmovpo (MN_cfcmovpo + 2)
-#define MN_cfcmovpo 0x2e39
-#define MN_cqo 0x2e42
-#define MN_tilezero 0x2e46
-#define MN_clzero 0x2e4f
-#define MN_seto 0x2e56
-#define MN_into 0x2e5b
-#define MN_cqto 0x2e60
-#define MN_ctesto 0x2e65
-#define MN_ssto 0x2e6c
-#define MN_setzuo 0x2e71
+#define MN_cfcmovpo 0x2eb1
+#define MN_cqo 0x2eba
+#define MN_tilezero 0x2ebe
+#define MN_clzero 0x2ec7
+#define MN_seto 0x2ece
+#define MN_into 0x2ed3
+#define MN_cqto 0x2ed8
+#define MN_ctesto 0x2edd
+#define MN_ssto 0x2ee4
+#define MN_setzuo 0x2ee9
 #define MN_cmovo (MN_cfcmovo + 2)
-#define MN_cfcmovo 0x2e78
-#define MN_push2p 0x2e80
-#define MN_pop2p 0x2e87
-#define MN_bswap 0x2e8d
-#define MN_fsubp 0x2e93
-#define MN_pfrcp 0x2e99
-#define MN_rdtscp 0x2e9f
-#define MN_faddp 0x2ea6
-#define MN_pdep 0x2eac
-#define MN_ffreep 0x2eb1
-#define MN_rep 0x2eb8
-#define MN_pushp 0x2ebc
-#define MN_fcomip 0x2ec2
-#define MN_fucomip 0x2ec9
-#define MN_jp 0x2ed1
-#define MN_fmulp 0x2ed4
+#define MN_cfcmovo 0x2ef0
+#define MN_push2p 0x2ef8
+#define MN_pop2p 0x2eff
+#define MN_bswap 0x2f05
+#define MN_fsubp 0x2f0b
+#define MN_pfrcp 0x2f11
+#define MN_rdtscp 0x2f17
+#define MN_faddp 0x2f1e
+#define MN_pdep 0x2f24
+#define MN_ffreep 0x2f29
+#define MN_rep 0x2f30
+#define MN_pushp 0x2f34
+#define MN_fcomip 0x2f3a
+#define MN_fucomip 0x2f41
+#define MN_jp 0x2f49
+#define MN_fmulp 0x2f4c
 #define MN_cmp (MN_scmp + 1)
-#define MN_scmp 0x2eda
+#define MN_scmp 0x2f52
 #define MN_jmp (MN_ljmp + 1)
-#define MN_ljmp 0x2edf
-#define MN_fcomp 0x2ee4
-#define MN_ficomp 0x2eea
-#define MN_fucomp 0x2ef1
-#define MN_jnp 0x2ef8
-#define MN_setnp 0x2efc
-#define MN_setzunp 0x2f02
+#define MN_ljmp 0x2f57
+#define MN_fcomp 0x2f5c
+#define MN_ficomp 0x2f62
+#define MN_fucomp 0x2f69
+#define MN_jnp 0x2f70
+#define MN_setnp 0x2f74
+#define MN_setzunp 0x2f7a
 #define MN_cmovnp (MN_cfcmovnp + 2)
-#define MN_cfcmovnp 0x2f0a
+#define MN_cfcmovnp 0x2f82
 #define MN_nop (MN_fnop + 1)
-#define MN_fnop 0x2f13
-#define MN_loop 0x2f18
-#define MN_pop 0x2f1d
-#define MN_fcompp 0x2f21
-#define MN_fucompp 0x2f28
-#define MN_popp 0x2f30
-#define MN_fsubrp 0x2f35
-#define MN_fdivrp 0x2f3c
-#define MN_rstorssp 0x2f43
-#define MN_saveprevssp 0x2f4c
-#define MN_setp 0x2f58
-#define MN_fbstp 0x2f5d
-#define MN_fdecstp 0x2f63
-#define MN_fincstp 0x2f6b
-#define MN_fstp 0x2f73
-#define MN_fistp 0x2f78
-#define MN_fisttp 0x2f7e
+#define MN_fnop 0x2f8b
+#define MN_loop 0x2f90
+#define MN_pop 0x2f95
+#define MN_fcompp 0x2f99
+#define MN_fucompp 0x2fa0
+#define MN_popp 0x2fa8
+#define MN_fsubrp 0x2fad
+#define MN_fdivrp 0x2fb4
+#define MN_rstorssp 0x2fbb
+#define MN_saveprevssp 0x2fc4
+#define MN_setp 0x2fd0
+#define MN_fbstp 0x2fd5
+#define MN_fdecstp 0x2fdb
+#define MN_fincstp 0x2fe3
+#define MN_fstp 0x2feb
+#define MN_fistp 0x2ff0
+#define MN_fisttp 0x2ff6
 #define MN_movddup (MN_vmovddup + 1)
-#define MN_vmovddup 0x2f85
+#define MN_vmovddup 0x2ffd
 #define MN_movshdup (MN_vmovshdup + 1)
-#define MN_vmovshdup 0x2f8e
+#define MN_vmovshdup 0x3006
 #define MN_movsldup (MN_vmovsldup + 1)
-#define MN_vmovsldup 0x2f98
-#define MN_setzup 0x2fa2
-#define MN_fdivp 0x2fa9
+#define MN_vmovsldup 0x3010
+#define MN_setzup 0x301a
+#define MN_fdivp 0x3021
 #define MN_cmovp (MN_cfcmovp + 2)
-#define MN_cfcmovp 0x2faf
-#define MN_xmodexp 0x2fb7
-#define MN_vpbroadcastmb2q 0x2fbf
-#define MN_vpermi2q 0x2fcf
-#define MN_vpmovm2q 0x2fd8
-#define MN_movdq2q 0x2fe1
-#define MN_vpermt2q 0x2fe9
-#define MN_vpshaq 0x2ff2
-#define MN_vpsraq 0x2ff9
-#define MN_vphaddbq 0x3000
-#define MN_vphaddubq 0x3009
+#define MN_cfcmovp 0x3027
+#define MN_xmodexp 0x302f
+#define MN_vpbroadcastmb2q 0x3037
+#define MN_vpermi2q 0x3047
+#define MN_vpmovm2q 0x3050
+#define MN_movdq2q 0x3059
+#define MN_vpermt2q 0x3061
+#define MN_vpshaq 0x306a
+#define MN_vpsraq 0x3071
+#define MN_vphaddbq 0x3078
+#define MN_vphaddubq 0x3081
 #define MN_psubq (MN_vpsubq + 1)
-#define MN_vpsubq 0x3013
+#define MN_vpsubq 0x308b
 #define MN_pmovsxbq (MN_vpmovsxbq + 1)
-#define MN_vpmovsxbq 0x301a
+#define MN_vpmovsxbq 0x3092
 #define MN_pmovzxbq (MN_vpmovzxbq + 1)
-#define MN_vpmovzxbq 0x3024
+#define MN_vpmovzxbq 0x309c
 #define MN_cvttpd2dq (MN_vcvttpd2dq + 1)
-#define MN_vcvttpd2dq 0x302e
+#define MN_vcvttpd2dq 0x30a6
 #define MN_cvtpd2dq (MN_vcvtpd2dq + 1)
-#define MN_vcvtpd2dq 0x3039
-#define MN_vcvttph2dq 0x3043
-#define MN_vcvtph2dq 0x304e
-#define MN_movq2dq 0x3058
+#define MN_vcvtpd2dq 0x30b1
+#define MN_vcvttph2dq 0x30bb
+#define MN_vcvtph2dq 0x30c6
+#define MN_movq2dq 0x30d0
 #define MN_cvttps2dq (MN_vcvttps2dq + 1)
-#define MN_vcvttps2dq 0x3060
+#define MN_vcvttps2dq 0x30d8
 #define MN_cvtps2dq (MN_vcvtps2dq + 1)
-#define MN_vcvtps2dq 0x306b
-#define MN_vphsubdq 0x3075
-#define MN_cdq 0x307e
-#define MN_kaddq 0x3082
+#define MN_vcvtps2dq 0x30e3
+#define MN_vphsubdq 0x30ed
+#define MN_cdq 0x30f6
+#define MN_kaddq 0x30fa
 #define MN_paddq (MN_vpaddq + 1)
-#define MN_vpaddq 0x3088
-#define MN_vphadddq 0x308f
+#define MN_vpaddq 0x3100
+#define MN_vphadddq 0x3107
 #define MN_punpckhdq (MN_vpunpckhdq + 1)
-#define MN_vpunpckhdq 0x3098
-#define MN_kunpckdq 0x30a3
-#define MN_vpshldq 0x30ac
+#define MN_vpunpckhdq 0x3110
+#define MN_kunpckdq 0x311b
+#define MN_vpshldq 0x3124
 #define MN_punpckldq (MN_vpunpckldq + 1)
-#define MN_vpunpckldq 0x30b4
+#define MN_vpunpckldq 0x312c
 #define MN_pslldq (MN_vpslldq + 1)
-#define MN_vpslldq 0x30bf
+#define MN_vpslldq 0x3137
 #define MN_psrldq (MN_vpsrldq + 1)
-#define MN_vpsrldq 0x30c7
+#define MN_vpsrldq 0x313f
 #define MN_pmuldq (MN_vpmuldq + 1)
-#define MN_vpmuldq 0x30cf
-#define MN_kandq 0x30d7
-#define MN_vpandq 0x30dd
-#define MN_vpexpandq 0x30e4
+#define MN_vpmuldq 0x3147
+#define MN_kandq 0x314f
+#define MN_vpandq 0x3155
+#define MN_vpexpandq 0x315c
 #define MN_punpckhqdq (MN_vpunpckhqdq + 1)
-#define MN_vpunpckhqdq 0x30ee
+#define MN_vpunpckhqdq 0x3166
 #define MN_pclmulhqhqdq (MN_vpclmulhqhqdq + 1)
-#define MN_vpclmulhqhqdq 0x30fa
+#define MN_vpclmulhqhqdq 0x3172
 #define MN_pclmullqhqdq (MN_vpclmullqhqdq + 1)
-#define MN_vpclmullqhqdq 0x3108
+#define MN_vpclmullqhqdq 0x3180
 #define MN_punpcklqdq (MN_vpunpcklqdq + 1)
-#define MN_vpunpcklqdq 0x3116
+#define MN_vpunpcklqdq 0x318e
 #define MN_pclmulhqlqdq (MN_vpclmulhqlqdq + 1)
-#define MN_vpclmulhqlqdq 0x3122
+#define MN_vpclmulhqlqdq 0x319a
 #define MN_pclmullqlqdq (MN_vpclmullqlqdq + 1)
-#define MN_vpclmullqlqdq 0x3130
+#define MN_vpclmullqlqdq 0x31a8
 #define MN_pclmulqdq (MN_vpclmulqdq + 1)
-#define MN_vpclmulqdq 0x313e
-#define MN_vpgatherdq 0x3149
-#define MN_vpscatterdq 0x3154
-#define MN_vpshrdq 0x3160
+#define MN_vpclmulqdq 0x31b6
+#define MN_vpgatherdq 0x31c1
+#define MN_vpscatterdq 0x31cc
+#define MN_vpshrdq 0x31d8
 #define MN_movntdq (MN_vmovntdq + 1)
-#define MN_vmovntdq 0x3168
-#define MN_vcvttpd2udq 0x3171
-#define MN_vcvtpd2udq 0x317d
-#define MN_vcvttph2udq 0x3188
-#define MN_vcvtph2udq 0x3194
-#define MN_vcvttps2udq 0x319f
-#define MN_vcvtps2udq 0x31ab
-#define MN_vphaddudq 0x31b6
+#define MN_vmovntdq 0x31e0
+#define MN_vcvttpd2udq 0x31e9
+#define MN_vcvtpd2udq 0x31f5
+#define MN_vcvttph2udq 0x3200
+#define MN_vcvtph2udq 0x320c
+#define MN_vcvttps2udq 0x3217
+#define MN_vcvtps2udq 0x3223
+#define MN_vphaddudq 0x322e
 #define MN_pmuludq (MN_vpmuludq + 1)
-#define MN_vpmuludq 0x31c0
+#define MN_vpmuludq 0x3238
 #define MN_pmovsxdq (MN_vpmovsxdq + 1)
-#define MN_vpmovsxdq 0x31c9
+#define MN_vpmovsxdq 0x3241
 #define MN_pmovzxdq (MN_vpmovzxdq + 1)
-#define MN_vpmovzxdq 0x31d3
-#define MN_vpcomgeq 0x31dd
-#define MN_vpcomleq 0x31e6
-#define MN_vpcmpnleq 0x31ef
-#define MN_vpcmpleq 0x31f9
-#define MN_pfcmpeq 0x3202
-#define MN_vpcomfalseq 0x320a
-#define MN_vpcomtrueq 0x3216
-#define MN_vpternlogq 0x3221
-#define MN_vpshlq 0x322c
+#define MN_vpmovzxdq 0x324b
+#define MN_vpcomgeq 0x3255
+#define MN_vpcomleq 0x325e
+#define MN_vpcmpnleq 0x3267
+#define MN_vpcmpleq 0x3271
+#define MN_pfcmpeq 0x327a
+#define MN_vpcomfalseq 0x3282
+#define MN_vpcomtrueq 0x328e
+#define MN_vpternlogq 0x3299
+#define MN_vpshlq 0x32a4
 #define MN_psllq (MN_vpsllq + 1)
-#define MN_vpsllq 0x3233
-#define MN_vpmullq 0x323a
-#define MN_vprolq 0x3242
+#define MN_vpsllq 0x32ab
+#define MN_vpmullq 0x32b2
+#define MN_vprolq 0x32ba
 #define MN_psrlq (MN_vpsrlq + 1)
-#define MN_vpsrlq 0x3249
-#define MN_kshiftlq 0x3250
-#define MN_vpblendmq 0x3259
-#define MN_vptestnmq 0x3263
-#define MN_vpcomq 0x326d
-#define MN_vpermq 0x3274
-#define MN_vptestmq 0x327b
-#define MN_kandnq 0x3284
-#define MN_vpandnq 0x328b
-#define MN_valignq 0x3293
-#define MN_vpcmpq 0x329b
-#define MN_incsspq 0x32a2
-#define MN_rdsspq 0x32aa
-#define MN_vcvttpd2qq 0x32b1
-#define MN_vcvtpd2qq 0x32bc
-#define MN_vcvttph2qq 0x32c6
-#define MN_vcvtph2qq 0x32d1
-#define MN_vcvttps2qq 0x32db
-#define MN_vcvtps2qq 0x32e6
-#define MN_vpcomeqq 0x32f0
-#define MN_vpcomneqq 0x32f9
-#define MN_vpcmpneqq 0x3303
+#define MN_vpsrlq 0x32c1
+#define MN_kshiftlq 0x32c8
+#define MN_vpblendmq 0x32d1
+#define MN_vptestnmq 0x32db
+#define MN_vpcomq 0x32e5
+#define MN_vpermq 0x32ec
+#define MN_vptestmq 0x32f3
+#define MN_kandnq 0x32fc
+#define MN_vpandnq 0x3303
+#define MN_valignq 0x330b
+#define MN_vpcmpq 0x3313
+#define MN_incsspq 0x331a
+#define MN_rdsspq 0x3322
+#define MN_vcvttpd2qq 0x3329
+#define MN_vcvtpd2qq 0x3334
+#define MN_vcvttph2qq 0x333e
+#define MN_vcvtph2qq 0x3349
+#define MN_vcvttps2qq 0x3353
+#define MN_vcvtps2qq 0x335e
+#define MN_vpcomeqq 0x3368
+#define MN_vpcomneqq 0x3371
+#define MN_vpcmpneqq 0x337b
 #define MN_pcmpeqq (MN_vpcmpeqq + 1)
-#define MN_vpcmpeqq 0x330d
-#define MN_vpgatherqq 0x3316
-#define MN_vpscatterqq 0x3321
-#define MN_vcvttpd2uqq 0x332d
-#define MN_vcvtpd2uqq 0x3339
-#define MN_vcvttph2uqq 0x3344
-#define MN_vcvtph2uqq 0x3350
-#define MN_vcvttps2uqq 0x335b
-#define MN_vcvtps2uqq 0x3367
-#define MN_korq 0x3372
-#define MN_kxnorq 0x3377
-#define MN_vporq 0x337e
-#define MN_vprorq 0x3384
-#define MN_kxorq 0x338b
-#define MN_vpxorq 0x3391
+#define MN_vpcmpeqq 0x3385
+#define MN_vpgatherqq 0x338e
+#define MN_vpscatterqq 0x3399
+#define MN_vcvttpd2uqq 0x33a5
+#define MN_vcvtpd2uqq 0x33b1
+#define MN_vcvttph2uqq 0x33bc
+#define MN_vcvtph2uqq 0x33c8
+#define MN_vcvttps2uqq 0x33d3
+#define MN_vcvtps2uqq 0x33df
+#define MN_korq 0x33ea
+#define MN_kxnorq 0x33ef
+#define MN_vporq 0x33f6
+#define MN_vprorq 0x33fc
+#define MN_kxorq 0x3403
+#define MN_vpxorq 0x3409
 #define MN_pinsrq (MN_vpinsrq + 1)
-#define MN_vpinsrq 0x3398
-#define MN_kshiftrq 0x33a0
+#define MN_vpinsrq 0x3410
+#define MN_kshiftrq 0x3418
 #define MN_extrq (MN_pextrq + 1)
 #define MN_pextrq (MN_vpextrq + 1)
-#define MN_vpextrq 0x33a9
-#define MN_vpabsq 0x33b1
-#define MN_vpminsq 0x33b8
-#define MN_vmovrsq 0x33c0
-#define MN_vpcompressq 0x33c8
-#define MN_wrssq 0x33d4
-#define MN_wrussq 0x33da
-#define MN_vpmaxsq 0x33e1
-#define MN_vp2intersectq 0x33e9
-#define MN_vpconflictq 0x33f7
-#define MN_vpcomgtq 0x3403
+#define MN_vpextrq 0x3421
+#define MN_vpabsq 0x3429
+#define MN_vpminsq 0x3430
+#define MN_vmovrsq 0x3438
+#define MN_vpcompressq 0x3440
+#define MN_wrssq 0x344c
+#define MN_wrussq 0x3452
+#define MN_vpmaxsq 0x3459
+#define MN_vp2intersectq 0x3461
+#define MN_vpconflictq 0x346f
+#define MN_vpcomgtq 0x347b
 #define MN_pcmpgtq (MN_vpcmpgtq + 1)
-#define MN_vpcmpgtq 0x340c
-#define MN_cltq 0x3415
-#define MN_vpcomltq 0x341a
-#define MN_vpcmpnltq 0x3423
-#define MN_vpcmpltq 0x342d
-#define MN_vpopcntq 0x3436
-#define MN_vplzcntq 0x343f
-#define MN_movntq 0x3448
-#define MN_knotq 0x344f
-#define MN_vprotq 0x3455
-#define MN_insertq 0x345c
-#define MN_vpbroadcastq 0x3464
-#define MN_ktestq 0x3471
-#define MN_kortestq 0x3478
-#define MN_vpcomgeuq 0x3481
-#define MN_vpcomleuq 0x348b
-#define MN_vpcmpnleuq 0x3495
-#define MN_vpcmpleuq 0x34a0
-#define MN_vpcomfalseuq 0x34aa
-#define MN_vpcomtrueuq 0x34b7
-#define MN_vpmadd52huq 0x34c3
-#define MN_vpmadd52luq 0x34cf
-#define MN_vpcomuq 0x34db
-#define MN_vpminuq 0x34e3
-#define MN_vpcmpuq 0x34eb
-#define MN_vpcomequq 0x34f3
-#define MN_vpcomnequq 0x34fd
-#define MN_vpcmpnequq 0x3508
-#define MN_vpcmpequq 0x3513
-#define MN_vpcomgtuq 0x351d
-#define MN_vpcomltuq 0x3527
-#define MN_vpcmpnltuq 0x3531
-#define MN_vpcmpltuq 0x353c
-#define MN_vpmaxuq 0x3546
-#define MN_vpsravq 0x354e
-#define MN_vpshldvq 0x3556
-#define MN_vpshrdvq 0x355f
-#define MN_vpsllvq 0x3568
-#define MN_vprolvq 0x3570
-#define MN_vpsrlvq 0x3578
+#define MN_vpcmpgtq 0x3484
+#define MN_cltq 0x348d
+#define MN_vpcomltq 0x3492
+#define MN_vpcmpnltq 0x349b
+#define MN_vpcmpltq 0x34a5
+#define MN_vpopcntq 0x34ae
+#define MN_vplzcntq 0x34b7
+#define MN_movntq 0x34c0
+#define MN_knotq 0x34c7
+#define MN_vprotq 0x34cd
+#define MN_insertq 0x34d4
+#define MN_vpbroadcastq 0x34dc
+#define MN_ktestq 0x34e9
+#define MN_kortestq 0x34f0
+#define MN_vpcomgeuq 0x34f9
+#define MN_vpcomleuq 0x3503
+#define MN_vpcmpnleuq 0x350d
+#define MN_vpcmpleuq 0x3518
+#define MN_vpcomfalseuq 0x3522
+#define MN_vpcomtrueuq 0x352f
+#define MN_vpmadd52huq 0x353b
+#define MN_vpmadd52luq 0x3547
+#define MN_vpcomuq 0x3553
+#define MN_vpminuq 0x355b
+#define MN_vpcmpuq 0x3563
+#define MN_vpcomequq 0x356b
+#define MN_vpcomnequq 0x3575
+#define MN_vpcmpnequq 0x3580
+#define MN_vpcmpequq 0x358b
+#define MN_vpcomgtuq 0x3595
+#define MN_vpcomltuq 0x359f
+#define MN_vpcmpnltuq 0x35a9
+#define MN_vpcmpltuq 0x35b4
+#define MN_vpmaxuq 0x35be
+#define MN_vpsravq 0x35c6
+#define MN_vpshldvq 0x35ce
+#define MN_vpshrdvq 0x35d7
+#define MN_vpsllvq 0x35e0
+#define MN_vprolvq 0x35e8
+#define MN_vpsrlvq 0x35f0
 #define MN_movq (MN_kmovq + 1)
 #define MN_kmovq (MN_maskmovq + 3)
 #define MN_maskmovq (MN_vpmaskmovq + 2)
-#define MN_vpmaskmovq 0x3580
-#define MN_vmovq 0x358b
-#define MN_vprorvq 0x3591
-#define MN_vphaddwq 0x3599
-#define MN_vphadduwq 0x35a2
+#define MN_vpmaskmovq 0x35f8
+#define MN_vmovq 0x3603
+#define MN_vprorvq 0x3609
+#define MN_vphaddwq 0x3611
+#define MN_vphadduwq 0x361a
 #define MN_pmovsxwq (MN_vpmovsxwq + 1)
-#define MN_vpmovsxwq 0x35ac
+#define MN_vpmovsxwq 0x3624
 #define MN_pmovzxwq (MN_vpmovzxwq + 1)
-#define MN_vpmovzxwq 0x35b6
-#define MN_rex_r 0x35c0
-#define MN_vmclear 0x35c6
-#define MN_lar 0x35ce
-#define MN_sar 0x35d2
+#define MN_vpmovzxwq 0x362e
+#define MN_rex_r 0x3638
+#define MN_vmclear 0x363e
+#define MN_lar 0x3646
+#define MN_sar 0x364a
 #define MN_fsubr (MN_pfsubr + 1)
-#define MN_pfsubr 0x35d6
-#define MN_fisubr 0x35dd
-#define MN_rcr 0x35e4
-#define MN_vzeroupper 0x35e8
+#define MN_pfsubr 0x364e
+#define MN_fisubr 0x3655
+#define MN_rcr 0x365c
+#define MN_vzeroupper 0x3660
 #define MN_enter (MN_sysenter + 3)
-#define MN_sysenter 0x35f3
-#define MN_shr 0x35fc
-#define MN_clr 0x3600
+#define MN_sysenter 0x366b
+#define MN_shr 0x3674
+#define MN_clr 0x3678
 #define MN_palignr (MN_vpalignr + 1)
-#define MN_vpalignr 0x3604
+#define MN_vpalignr 0x367c
 #define MN_or (MN_aor + 1)
-#define MN_aor 0x360d
+#define MN_aor 0x3685
 #define MN_por (MN_vpor + 1)
-#define MN_vpor 0x3611
-#define MN_ror 0x3616
+#define MN_vpor 0x3689
+#define MN_ror 0x368e
 #define MN_monitor (MN_umonitor + 1)
-#define MN_umonitor 0x361a
-#define MN_frstor 0x3623
+#define MN_umonitor 0x3692
+#define MN_frstor 0x369b
 #define MN_xrstor (MN_fxrstor + 1)
-#define MN_fxrstor 0x362a
+#define MN_fxrstor 0x36a2
 #define MN_xor (MN_axor + 1)
-#define MN_axor 0x3632
+#define MN_axor 0x36aa
 #define MN_pxor (MN_vpxor + 1)
-#define MN_vpxor 0x3637
-#define MN_verr 0x363d
-#define MN_bsr 0x3642
+#define MN_vpxor 0x36af
+#define MN_verr 0x36b5
+#define MN_bsr 0x36ba
 #define MN_ldmxcsr (MN_vldmxcsr + 1)
-#define MN_vldmxcsr 0x3646
+#define MN_vldmxcsr 0x36be
 #define MN_stmxcsr (MN_vstmxcsr + 1)
-#define MN_vstmxcsr 0x364f
-#define MN_blsr 0x3658
+#define MN_vstmxcsr 0x36c7
+#define MN_blsr 0x36d0
 #define MN_rdmsr (MN_urdmsr + 1)
-#define MN_urdmsr 0x365d
+#define MN_urdmsr 0x36d5
 #define MN_wrmsr (MN_uwrmsr + 1)
-#define MN_uwrmsr 0x3664
-#define MN_btr 0x366b
-#define MN_xcrypt_ctr 0x366f
-#define MN_xcryptctr 0x367a
-#define MN_ltr 0x3684
-#define MN_str 0x3688
-#define MN_bextr 0x368c
-#define MN_fdivr 0x3692
-#define MN_fidivr 0x3698
-#define MN_rex_wr 0x369f
-#define MN_vcvt2ph2bf8s 0x36a6
-#define MN_vcvtbiasph2bf8s 0x36b3
-#define MN_vcvtph2bf8s 0x36c3
-#define MN_vcvt2ph2hf8s 0x36cf
-#define MN_vcvtbiasph2hf8s 0x36dc
-#define MN_vcvtph2hf8s 0x36ec
-#define MN_aas 0x36f8
-#define MN_scas 0x36fc
-#define MN_das 0x3701
-#define MN_fabs 0x3705
-#define MN_jmpabs 0x370a
-#define MN_movabs 0x3711
-#define MN_vcvttbf162ibs 0x3718
-#define MN_vcvtbf162ibs 0x3726
-#define MN_vcvttph2ibs 0x3733
-#define MN_vcvtph2ibs 0x373f
-#define MN_vcvttps2ibs 0x374a
-#define MN_vcvtps2ibs 0x3756
-#define MN_vcvttbf162iubs 0x3761
-#define MN_vcvtbf162iubs 0x3770
-#define MN_vcvttph2iubs 0x377e
-#define MN_vcvtph2iubs 0x378b
-#define MN_vcvttps2iubs 0x3797
-#define MN_vcvtps2iubs 0x37a4
+#define MN_uwrmsr 0x36dc
+#define MN_btr 0x36e3
+#define MN_xcrypt_ctr 0x36e7
+#define MN_xcryptctr 0x36f2
+#define MN_ltr 0x36fc
+#define MN_str 0x3700
+#define MN_bextr 0x3704
+#define MN_fdivr 0x370a
+#define MN_fidivr 0x3710
+#define MN_rex_wr 0x3717
+#define MN_vcvtbf82bf4s 0x371e
+#define MN_vcvthf82bf4s 0x372b
+#define MN_vcvtbf82bf6s 0x3738
+#define MN_vcvthf82hf6s 0x3745
+#define MN_vcvt2ph2bf8s 0x3752
+#define MN_vcvtbiasph2bf8s 0x375f
+#define MN_vcvtph2bf8s 0x376f
+#define MN_vcvtbiasps2bf8s 0x377b
+#define MN_vcvtps2bf8s 0x378b
+#define MN_vcvt2ph2hf8s 0x3797
+#define MN_vcvtbiasph2hf8s 0x37a4
+#define MN_vcvtph2hf8s 0x37b4
+#define MN_vcvtrops2hf8s 0x37c0
+#define MN_vcvtbiasps2hf8s 0x37ce
+#define MN_vcvtps2hf8s 0x37de
+#define MN_aas 0x37ea
+#define MN_scas 0x37ee
+#define MN_das 0x37f3
+#define MN_fabs 0x37f7
+#define MN_jmpabs 0x37fc
+#define MN_movabs 0x3803
+#define MN_vcvttbf162ibs 0x380a
+#define MN_vcvtbf162ibs 0x3818
+#define MN_vcvttph2ibs 0x3825
+#define MN_vcvtph2ibs 0x3831
+#define MN_vcvttps2ibs 0x383c
+#define MN_vcvtps2ibs 0x3848
+#define MN_vcvttbf162iubs 0x3853
+#define MN_vcvtbf162iubs 0x3862
+#define MN_vcvttph2iubs 0x3870
+#define MN_vcvtph2iubs 0x387d
+#define MN_vcvttps2iubs 0x3889
+#define MN_vcvtps2iubs 0x3896
 #define MN_cs (MN_blcs + 2)
-#define MN_blcs 0x37b0
+#define MN_blcs 0x38a2
 #define MN_ds (MN_lds + 1)
-#define MN_lds 0x37b5
-#define MN_enqcmds 0x37b9
-#define MN_lods 0x37c1
-#define MN_vpdpbssds 0x37c6
-#define MN_vp4dpwssds 0x37d0
-#define MN_vpdpwssds 0x37db
-#define MN_vpdpbusds 0x37e5
-#define MN_vpdpwusds 0x37ef
-#define MN_vpdpbsuds 0x37f9
-#define MN_vpdpwsuds 0x3803
-#define MN_vpdpbuuds 0x380d
-#define MN_vpdpwuuds 0x3817
+#define MN_lds 0x38a7
+#define MN_enqcmds 0x38ab
+#define MN_lods 0x38b3
+#define MN_vpdpbssds 0x38b8
+#define MN_vp4dpwssds 0x38c2
+#define MN_vpdpwssds 0x38cd
+#define MN_vpdpbusds 0x38d7
+#define MN_vpdpwusds 0x38e1
+#define MN_vpdpbsuds 0x38eb
+#define MN_vpdpwsuds 0x38f5
+#define MN_vpdpbuuds 0x38ff
+#define MN_vpdpwuuds 0x3909
 #define MN_es (MN_les + 1)
-#define MN_les 0x3821
-#define MN_xsaves 0x3825
+#define MN_les 0x3913
+#define MN_xsaves 0x3917
 #define MN_fs (MN_lfs + 1)
-#define MN_lfs 0x382c
+#define MN_lfs 0x391e
 #define MN_gs (MN_lkgs + 2)
-#define MN_lkgs 0x3830
-#define MN_lgs 0x3835
-#define MN_swapgs 0x3839
-#define MN_fchs 0x3840
-#define MN_vcvttsd2sis 0x3845
-#define MN_vcvttss2sis 0x3851
-#define MN_vcvttsd2usis 0x385d
-#define MN_vcvttss2usis 0x386a
-#define MN_js 0x3877
-#define MN_encls 0x387a
+#define MN_lkgs 0x3922
+#define MN_lgs 0x3927
+#define MN_swapgs 0x392b
+#define MN_fchs 0x3932
+#define MN_vcvttsd2sis 0x3937
+#define MN_vcvttss2sis 0x3943
+#define MN_vcvttsd2usis 0x394f
+#define MN_vcvttss2usis 0x395c
+#define MN_js 0x3969
+#define MN_encls 0x396c
 #define MN_emms (MN_femms + 1)
-#define MN_femms 0x3880
+#define MN_femms 0x3972
 #define MN_ins (MN_lwpins + 3)
-#define MN_lwpins 0x3886
-#define MN_jns 0x388d
-#define MN_ccmpns 0x3891
-#define MN_wrmsrns 0x3898
-#define MN_setns 0x38a0
-#define MN_ctestns 0x38a6
-#define MN_setzuns 0x38ae
+#define MN_lwpins 0x3978
+#define MN_jns 0x397f
+#define MN_ccmpns 0x3983
+#define MN_wrmsrns 0x398a
+#define MN_setns 0x3992
+#define MN_ctestns 0x3998
+#define MN_setzuns 0x39a0
 #define MN_cmovns (MN_cfcmovns + 2)
-#define MN_cfcmovns 0x38b6
-#define MN_fcos 0x38bf
-#define MN_fsincos 0x38c4
-#define MN_stos 0x38cc
-#define MN_vfmaddsub231ps 0x38d1
-#define MN_vfmsub231ps 0x38e0
-#define MN_vfnmsub231ps 0x38ec
-#define MN_vfmsubadd231ps 0x38f9
-#define MN_vfmadd231ps 0x3908
-#define MN_vfnmadd231ps 0x3914
-#define MN_vfmaddsub132ps 0x3921
-#define MN_vfmsub132ps 0x3930
-#define MN_vfnmsub132ps 0x393c
-#define MN_vfmsubadd132ps 0x3949
-#define MN_vfmadd132ps 0x3958
-#define MN_vfnmadd132ps 0x3964
+#define MN_cfcmovns 0x39a8
+#define MN_fcos 0x39b1
+#define MN_fsincos 0x39b6
+#define MN_stos 0x39be
+#define MN_vfmaddsub231ps 0x39c3
+#define MN_vfmsub231ps 0x39d2
+#define MN_vfnmsub231ps 0x39de
+#define MN_vfmsubadd231ps 0x39eb
+#define MN_vfmadd231ps 0x39fa
+#define MN_vfnmadd231ps 0x3a06
+#define MN_vfmaddsub132ps 0x3a13
+#define MN_vfmsub132ps 0x3a22
+#define MN_vfnmsub132ps 0x3a2e
+#define MN_vfmsubadd132ps 0x3a3b
+#define MN_vfmadd132ps 0x3a4a
+#define MN_vfnmadd132ps 0x3a56
 #define MN_tmmultf32ps (MN_ttmmultf32ps + 1)
-#define MN_ttmmultf32ps 0x3971
-#define MN_vcvtneebf162ps 0x397e
-#define MN_vbcstnebf162ps 0x398d
-#define MN_vcvtneobf162ps 0x399c
+#define MN_ttmmultf32ps 0x3a63
+#define MN_vcvtneebf162ps 0x3a70
+#define MN_vbcstnebf162ps 0x3a7f
+#define MN_vcvtneobf162ps 0x3a8e
+#define MN_vcvtbf82ps 0x3a9d
+#define MN_vcvthf82ps 0x3aa8
 #define MN_cvtpd2ps (MN_vcvtpd2ps + 1)
-#define MN_vcvtpd2ps 0x39ab
-#define MN_tcvtrowd2ps 0x39b5
-#define MN_vcvtneeph2ps 0x39c1
-#define MN_vcvtneoph2ps 0x39ce
-#define MN_vcvtph2ps 0x39db
-#define MN_vbcstnesh2ps 0x39e5
-#define MN_vpermi2ps 0x39f2
-#define MN_cvtpi2ps 0x39fc
-#define MN_vpermil2ps 0x3a05
-#define MN_vexp2ps 0x3a10
+#define MN_vcvtpd2ps 0x3ab3
+#define MN_tcvtrowd2ps 0x3abd
+#define MN_vcvtneeph2ps 0x3ac9
+#define MN_vcvtneoph2ps 0x3ad6
+#define MN_vcvtph2ps 0x3ae3
+#define MN_vbcstnesh2ps 0x3aed
+#define MN_vpermi2ps 0x3afa
+#define MN_cvtpi2ps 0x3b04
+#define MN_vpermil2ps 0x3b0d
+#define MN_vexp2ps 0x3b18
 #define MN_cvtdq2ps (MN_vcvtdq2ps + 1)
-#define MN_vcvtdq2ps 0x3a18
-#define MN_vcvtudq2ps 0x3a22
-#define MN_vcvtqq2ps 0x3a2d
-#define MN_vcvtuqq2ps 0x3a37
-#define MN_vpermt2ps 0x3a42
-#define MN_vfmaddsub213ps 0x3a4c
-#define MN_vfmsub213ps 0x3a5b
-#define MN_vfnmsub213ps 0x3a67
-#define MN_vfmsubadd213ps 0x3a74
-#define MN_vfmadd213ps 0x3a83
-#define MN_vfnmadd213ps 0x3a8f
-#define MN_vrcp14ps 0x3a9c
-#define MN_vrsqrt14ps 0x3aa5
+#define MN_vcvtdq2ps 0x3b20
+#define MN_vcvtudq2ps 0x3b2a
+#define MN_vcvtqq2ps 0x3b35
+#define MN_vcvtuqq2ps 0x3b3f
+#define MN_vpermt2ps 0x3b4a
+#define MN_vfmaddsub213ps 0x3b54
+#define MN_vfmsub213ps 0x3b63
+#define MN_vfnmsub213ps 0x3b6f
+#define MN_vfmsubadd213ps 0x3b7c
+#define MN_vfmadd213ps 0x3b8b
+#define MN_vfnmadd213ps 0x3b97
+#define MN_vrcp14ps 0x3ba4
+#define MN_vrsqrt14ps 0x3bad
 #define MN_tdpbf16ps (MN_ttdpbf16ps + 1)
-#define MN_ttdpbf16ps 0x3ab0
-#define MN_vdpbf16ps 0x3abb
+#define MN_ttdpbf16ps 0x3bb8
+#define MN_vdpbf16ps 0x3bc3
 #define MN_tcmmrlfp16ps (MN_ttcmmrlfp16ps + 1)
-#define MN_ttcmmrlfp16ps 0x3ac5
+#define MN_ttcmmrlfp16ps 0x3bcd
 #define MN_tcmmimfp16ps (MN_tconjtcmmimfp16ps + 5)
-#define MN_tconjtcmmimfp16ps 0x3ad3
-#define MN_ttcmmimfp16ps 0x3ae5
+#define MN_tconjtcmmimfp16ps 0x3bdb
+#define MN_ttcmmimfp16ps 0x3bed
 #define MN_tdpfp16ps (MN_ttdpfp16ps + 1)
-#define MN_ttdpfp16ps 0x3af3
-#define MN_vrcp28ps 0x3afe
-#define MN_vrsqrt28ps 0x3b07
-#define MN_tdphbf8ps 0x3b12
-#define MN_tdpbf8ps 0x3b1c
-#define MN_tdpbhf8ps 0x3b25
-#define MN_tdphf8ps 0x3b2f
+#define MN_ttdpfp16ps 0x3bfb
+#define MN_vrcp28ps 0x3c06
+#define MN_vrsqrt28ps 0x3c0f
+#define MN_tdphbf8ps 0x3c1a
+#define MN_tdpbf8ps 0x3c24
+#define MN_tdpbhf8ps 0x3c2d
+#define MN_tdphf8ps 0x3c37
 #define MN_movaps (MN_vmovaps + 1)
-#define MN_vmovaps 0x3b38
+#define MN_vmovaps 0x3c40
 #define MN_subps (MN_addsubps + 3)
 #define MN_addsubps (MN_vfmaddsubps + 3)
-#define MN_vfmaddsubps 0x3b40
-#define MN_vaddsubps 0x3b4c
+#define MN_vfmaddsubps 0x3c48
+#define MN_vaddsubps 0x3c54
 #define MN_hsubps (MN_vhsubps + 1)
-#define MN_vhsubps 0x3b56
-#define MN_vfmsubps 0x3b5e
-#define MN_vfnmsubps 0x3b67
-#define MN_vsubps 0x3b71
-#define MN_vgatherpf0dps 0x3b78
-#define MN_vscatterpf0dps 0x3b86
-#define MN_vgatherpf1dps 0x3b95
-#define MN_vscatterpf1dps 0x3ba3
+#define MN_vhsubps 0x3c5e
+#define MN_vfmsubps 0x3c66
+#define MN_vfnmsubps 0x3c6f
+#define MN_vsubps 0x3c79
+#define MN_vgatherpf0dps 0x3c80
+#define MN_vscatterpf0dps 0x3c8e
+#define MN_vgatherpf1dps 0x3c9d
+#define MN_vscatterpf1dps 0x3cab
 #define MN_addps (MN_vfmsubaddps + 6)
-#define MN_vfmsubaddps 0x3bb2
+#define MN_vfmsubaddps 0x3cba
 #define MN_haddps (MN_vhaddps + 1)
-#define MN_vhaddps 0x3bbe
-#define MN_v4fmaddps 0x3bc6
-#define MN_vfmaddps 0x3bd0
-#define MN_v4fnmaddps 0x3bd9
-#define MN_vfnmaddps 0x3be4
-#define MN_vaddps 0x3bee
+#define MN_vhaddps 0x3cc6
+#define MN_v4fmaddps 0x3cce
+#define MN_vfmaddps 0x3cd8
+#define MN_v4fnmaddps 0x3ce1
+#define MN_vfnmaddps 0x3cec
+#define MN_vaddps 0x3cf6
 #define MN_andps (MN_vexpandps + 4)
-#define MN_vexpandps 0x3bf5
-#define MN_vandps 0x3bff
+#define MN_vexpandps 0x3cfd
+#define MN_vandps 0x3d07
 #define MN_blendps (MN_vblendps + 1)
-#define MN_vblendps 0x3c06
+#define MN_vblendps 0x3d0e
 #define MN_roundps (MN_vroundps + 1)
-#define MN_vroundps 0x3c0f
-#define MN_vgatherdps 0x3c18
-#define MN_vscatterdps 0x3c23
+#define MN_vroundps 0x3d17
+#define MN_vgatherdps 0x3d20
+#define MN_vscatterdps 0x3d2b
 #define MN_cmpunordps (MN_vcmpunordps + 1)
-#define MN_vcmpunordps 0x3c2f
+#define MN_vcmpunordps 0x3d37
 #define MN_cmpordps (MN_vcmpordps + 1)
-#define MN_vcmpordps 0x3c3b
-#define MN_vreduceps 0x3c45
-#define MN_vrangeps 0x3c4f
-#define MN_vcmpngeps 0x3c58
-#define MN_vcmpgeps 0x3c62
-#define MN_vrndscaleps 0x3c6b
+#define MN_vcmpordps 0x3d43
+#define MN_vreduceps 0x3d4d
+#define MN_vrangeps 0x3d57
+#define MN_vcmpngeps 0x3d60
+#define MN_vcmpgeps 0x3d6a
+#define MN_vrndscaleps 0x3d73
 #define MN_cmpnleps (MN_vcmpnleps + 1)
-#define MN_vcmpnleps 0x3c77
+#define MN_vcmpnleps 0x3d7f
 #define MN_cmpleps (MN_vcmpleps + 1)
-#define MN_vcmpleps 0x3c81
-#define MN_vcmpfalseps 0x3c8a
-#define MN_vcmptrueps 0x3c96
-#define MN_vscalefps 0x3ca1
+#define MN_vcmpleps 0x3d89
+#define MN_vcmpfalseps 0x3d92
+#define MN_vcmptrueps 0x3d9e
+#define MN_vscalefps 0x3da9
 #define MN_shufps (MN_vshufps + 1)
-#define MN_vshufps 0x3cab
+#define MN_vshufps 0x3db3
 #define MN_unpckhps (MN_vunpckhps + 1)
-#define MN_vunpckhps 0x3cb3
+#define MN_vunpckhps 0x3dbb
 #define MN_movlhps (MN_vmovlhps + 1)
-#define MN_vmovlhps 0x3cbd
-#define MN_vdpphps 0x3cc6
+#define MN_vmovlhps 0x3dc5
+#define MN_vdpphps 0x3dce
 #define MN_movhps (MN_vmovhps + 1)
-#define MN_vmovhps 0x3cce
+#define MN_vmovhps 0x3dd6
 #define MN_movmskps (MN_vmovmskps + 1)
-#define MN_vmovmskps 0x3cd6
+#define MN_vmovmskps 0x3dde
 #define MN_movhlps (MN_vmovhlps + 1)
-#define MN_vmovhlps 0x3ce0
-#define MN_vpermilps 0x3ce9
+#define MN_vmovhlps 0x3de8
+#define MN_vpermilps 0x3df1
 #define MN_unpcklps (MN_vunpcklps + 1)
-#define MN_vunpcklps 0x3cf3
+#define MN_vunpcklps 0x3dfb
 #define MN_mulps (MN_vmulps + 1)
-#define MN_vmulps 0x3cfd
+#define MN_vmulps 0x3e05
 #define MN_movlps (MN_vmovlps + 1)
-#define MN_vmovlps 0x3d04
+#define MN_vmovlps 0x3e0c
 #define MN_cmps (MN_ccmps + 1)
-#define MN_ccmps 0x3d0c
-#define MN_vblendmps 0x3d12
-#define MN_vfixupimmps 0x3d1c
-#define MN_vpermps 0x3d28
+#define MN_ccmps 0x3e14
+#define MN_vblendmps 0x3e1a
+#define MN_vfixupimmps 0x3e24
+#define MN_vpermps 0x3e30
 #define MN_andnps (MN_vandnps + 1)
-#define MN_vandnps 0x3d30
+#define MN_vandnps 0x3e38
 #define MN_minps (MN_vminps + 1)
-#define MN_vminps 0x3d38
-#define MN_seamops 0x3d3f
+#define MN_vminps 0x3e40
+#define MN_seamops 0x3e47
 #define MN_rcpps (MN_vrcpps + 1)
-#define MN_vrcpps 0x3d47
+#define MN_vrcpps 0x3e4f
 #define MN_dpps (MN_vdpps + 1)
-#define MN_vdpps 0x3d4e
+#define MN_vdpps 0x3e56
 #define MN_cmpps (MN_vcmpps + 1)
-#define MN_vcmpps 0x3d54
-#define MN_vgetexpps 0x3d5b
-#define MN_vgatherpf0qps 0x3d65
-#define MN_vscatterpf0qps 0x3d73
-#define MN_vgatherpf1qps 0x3d82
-#define MN_vscatterpf1qps 0x3d90
-#define MN_vcmpunord_qps 0x3d9f
-#define MN_vcmpord_qps 0x3dad
+#define MN_vcmpps 0x3e5c
+#define MN_vgetexpps 0x3e63
+#define MN_vgatherpf0qps 0x3e6d
+#define MN_vscatterpf0qps 0x3e7b
+#define MN_vgatherpf1qps 0x3e8a
+#define MN_vscatterpf1qps 0x3e98
+#define MN_vcmpunord_qps 0x3ea7
+#define MN_vcmpord_qps 0x3eb5
 #define MN_cmpneqps (MN_vcmpneqps + 1)
-#define MN_vcmpneqps 0x3db9
+#define MN_vcmpneqps 0x3ec1
 #define MN_cmpeqps (MN_vcmpeqps + 1)
-#define MN_vcmpeqps 0x3dc3
-#define MN_vcmpge_oqps 0x3dcc
-#define MN_vcmple_oqps 0x3dd8
-#define MN_vcmpfalse_oqps 0x3de4
-#define MN_vcmpneq_oqps 0x3df3
-#define MN_vcmpeq_oqps 0x3e00
-#define MN_vcmpgt_oqps 0x3e0c
-#define MN_vcmplt_oqps 0x3e18
-#define MN_vgatherqps 0x3e24
-#define MN_vscatterqps 0x3e2f
-#define MN_vcmpnge_uqps 0x3e3b
-#define MN_vcmpnle_uqps 0x3e48
-#define MN_vcmptrue_uqps 0x3e55
-#define MN_vcmpneq_uqps 0x3e63
-#define MN_vcmpeq_uqps 0x3e70
-#define MN_vcmpngt_uqps 0x3e7c
-#define MN_vcmpnlt_uqps 0x3e89
+#define MN_vcmpeqps 0x3ecb
+#define MN_vcmpge_oqps 0x3ed4
+#define MN_vcmple_oqps 0x3ee0
+#define MN_vcmpfalse_oqps 0x3eec
+#define MN_vcmpneq_oqps 0x3efb
+#define MN_vcmpeq_oqps 0x3f08
+#define MN_vcmpgt_oqps 0x3f14
+#define MN_vcmplt_oqps 0x3f20
+#define MN_vgatherqps 0x3f2c
+#define MN_vscatterqps 0x3f37
+#define MN_vcmpnge_uqps 0x3f43
+#define MN_vcmpnle_uqps 0x3f50
+#define MN_vcmptrue_uqps 0x3f5d
+#define MN_vcmpneq_uqps 0x3f6b
+#define MN_vcmpeq_uqps 0x3f78
+#define MN_vcmpngt_uqps 0x3f84
+#define MN_vcmpnlt_uqps 0x3f91
 #define MN_orps (MN_vorps + 1)
-#define MN_vorps 0x3e96
+#define MN_vorps 0x3f9e
 #define MN_xorps (MN_vxorps + 1)
-#define MN_vxorps 0x3e9c
-#define MN_vcmpunord_sps 0x3ea3
-#define MN_vcmpord_sps 0x3eb1
-#define MN_vcmpge_osps 0x3ebd
-#define MN_vcmple_osps 0x3ec9
-#define MN_vcmpfalse_osps 0x3ed5
-#define MN_vcmpneq_osps 0x3ee4
-#define MN_vcmpeq_osps 0x3ef1
-#define MN_vcmpgt_osps 0x3efd
-#define MN_vcmplt_osps 0x3f09
-#define MN_vfpclassps 0x3f15
-#define MN_vcompressps 0x3f20
-#define MN_vcmpnge_usps 0x3f2c
-#define MN_vcmpnle_usps 0x3f39
-#define MN_vcmptrue_usps 0x3f46
-#define MN_vcmpneq_usps 0x3f54
-#define MN_vcmpeq_usps 0x3f61
-#define MN_vcmpngt_usps 0x3f6d
-#define MN_vcmpnlt_usps 0x3f7a
+#define MN_vxorps 0x3fa4
+#define MN_vcmpunord_sps 0x3fab
+#define MN_vcmpord_sps 0x3fb9
+#define MN_vcmpge_osps 0x3fc5
+#define MN_vcmple_osps 0x3fd1
+#define MN_vcmpfalse_osps 0x3fdd
+#define MN_vcmpneq_osps 0x3fec
+#define MN_vcmpeq_osps 0x3ff9
+#define MN_vcmpgt_osps 0x4005
+#define MN_vcmplt_osps 0x4011
+#define MN_vfpclassps 0x401d
+#define MN_vcompressps 0x4028
+#define MN_vcmpnge_usps 0x4034
+#define MN_vcmpnle_usps 0x4041
+#define MN_vcmptrue_usps 0x404e
+#define MN_vcmpneq_usps 0x405c
+#define MN_vcmpeq_usps 0x4069
+#define MN_vcmpngt_usps 0x4075
+#define MN_vcmpnlt_usps 0x4082
 #define MN_extractps (MN_vextractps + 1)
-#define MN_vextractps 0x3f87
-#define MN_vcmpngtps 0x3f92
-#define MN_vcmpgtps 0x3f9c
+#define MN_vextractps 0x408f
+#define MN_vcmpngtps 0x409a
+#define MN_vcmpgtps 0x40a4
 #define MN_cmpnltps (MN_vcmpnltps + 1)
-#define MN_vcmpnltps 0x3fa5
+#define MN_vcmpnltps 0x40ad
 #define MN_cmpltps (MN_vcmpltps + 1)
-#define MN_vcmpltps 0x3faf
-#define MN_vgetmantps 0x3fb8
+#define MN_vcmpltps 0x40b7
+#define MN_vgetmantps 0x40c0
 #define MN_movntps (MN_vmovntps + 1)
-#define MN_vmovntps 0x3fc3
+#define MN_vmovntps 0x40cb
 #define MN_insertps (MN_vinsertps + 1)
-#define MN_vinsertps 0x3fcc
+#define MN_vinsertps 0x40d4
 #define MN_sqrtps (MN_rsqrtps + 1)
 #define MN_rsqrtps (MN_vrsqrtps + 1)
-#define MN_vrsqrtps 0x3fd6
-#define MN_vsqrtps 0x3fdf
-#define MN_vtestps 0x3fe7
+#define MN_vrsqrtps 0x40de
+#define MN_vsqrtps 0x40e7
+#define MN_vtestps 0x40ef
 #define MN_movups (MN_vmovups + 1)
-#define MN_vmovups 0x3fef
+#define MN_vmovups 0x40f7
 #define MN_blendvps (MN_vblendvps + 1)
-#define MN_vblendvps 0x3ff7
+#define MN_vblendvps 0x40ff
 #define MN_divps (MN_vdivps + 1)
-#define MN_vdivps 0x4001
-#define MN_vmaskmovps 0x4008
+#define MN_vdivps 0x4109
+#define MN_vmaskmovps 0x4110
 #define MN_maxps (MN_vminmaxps + 4)
-#define MN_vminmaxps 0x4013
-#define MN_vmaxps 0x401d
-#define MN_vfrczps 0x4024
-#define MN_vcvttpd2dqs 0x402c
-#define MN_vcvttps2dqs 0x4038
-#define MN_vcvttpd2udqs 0x4044
-#define MN_vcvttps2udqs 0x4051
-#define MN_vcvttpd2qqs 0x405e
-#define MN_vcvttps2qqs 0x406a
-#define MN_vcvttpd2uqqs 0x4076
-#define MN_vcvttps2uqqs 0x4083
-#define MN_t2rpntlvwz0rs 0x4090
-#define MN_t2rpntlvwz1rs 0x409e
-#define MN_tileloaddrs 0x40ac
-#define MN_xrstors 0x40b8
-#define MN_movrs 0x40c0
+#define MN_vminmaxps 0x411b
+#define MN_vmaxps 0x4125
+#define MN_vfrczps 0x412c
+#define MN_vcvttpd2dqs 0x4134
+#define MN_vcvttps2dqs 0x4140
+#define MN_vcvttpd2udqs 0x414c
+#define MN_vcvttps2udqs 0x4159
+#define MN_vcvttpd2qqs 0x4166
+#define MN_vcvttps2qqs 0x4172
+#define MN_vcvttpd2uqqs 0x417e
+#define MN_vcvttps2uqqs 0x418b
+#define MN_t2rpntlvwz0rs 0x4198
+#define MN_t2rpntlvwz1rs 0x41a6
+#define MN_tileloaddrs 0x41b4
+#define MN_xrstors 0x41c0
+#define MN_movrs 0x41c8
 #define MN_ss (MN_vfmsub231ss + 9)
-#define MN_vfmsub231ss 0x40c6
-#define MN_vfnmsub231ss 0x40d2
-#define MN_vfmadd231ss 0x40df
-#define MN_vfnmadd231ss 0x40eb
-#define MN_vfmsub132ss 0x40f8
-#define MN_vfnmsub132ss 0x4104
-#define MN_vfmadd132ss 0x4111
-#define MN_vfnmadd132ss 0x411d
+#define MN_vfmsub231ss 0x41ce
+#define MN_vfnmsub231ss 0x41da
+#define MN_vfmadd231ss 0x41e7
+#define MN_vfnmadd231ss 0x41f3
+#define MN_vfmsub132ss 0x4200
+#define MN_vfnmsub132ss 0x420c
+#define MN_vfmadd132ss 0x4219
+#define MN_vfnmadd132ss 0x4225
 #define MN_cvtsd2ss (MN_vcvtsd2ss + 1)
-#define MN_vcvtsd2ss 0x412a
-#define MN_vcvtsh2ss 0x4134
+#define MN_vcvtsd2ss 0x4232
+#define MN_vcvtsh2ss 0x423c
 #define MN_cvtsi2ss (MN_vcvtsi2ss + 1)
-#define MN_vcvtsi2ss 0x413e
-#define MN_vcvtusi2ss 0x4148
-#define MN_vfmsub213ss 0x4153
-#define MN_vfnmsub213ss 0x415f
-#define MN_vfmadd213ss 0x416c
-#define MN_vfnmadd213ss 0x4178
-#define MN_vrcp14ss 0x4185
-#define MN_vrsqrt14ss 0x418e
-#define MN_vrcp28ss 0x4199
-#define MN_vrsqrt28ss 0x41a2
+#define MN_vcvtsi2ss 0x4246
+#define MN_vcvtusi2ss 0x4250
+#define MN_vfmsub213ss 0x425b
+#define MN_vfnmsub213ss 0x4267
+#define MN_vfmadd213ss 0x4274
+#define MN_vfnmadd213ss 0x4280
+#define MN_vrcp14ss 0x428d
+#define MN_vrsqrt14ss 0x4296
+#define MN_vrcp28ss 0x42a1
+#define MN_vrsqrt28ss 0x42aa
 #define MN_subss (MN_vfmsubss + 3)
-#define MN_vfmsubss 0x41ad
-#define MN_vfnmsubss 0x41b6
-#define MN_vsubss 0x41c0
+#define MN_vfmsubss 0x42b5
+#define MN_vfnmsubss 0x42be
+#define MN_vsubss 0x42c8
 #define MN_addss (MN_v4fmaddss + 4)
-#define MN_v4fmaddss 0x41c7
-#define MN_vfmaddss 0x41d1
-#define MN_v4fnmaddss 0x41da
-#define MN_vfnmaddss 0x41e5
-#define MN_vaddss 0x41ef
+#define MN_v4fmaddss 0x42cf
+#define MN_vfmaddss 0x42d9
+#define MN_v4fnmaddss 0x42e2
+#define MN_vfnmaddss 0x42ed
+#define MN_vaddss 0x42f7
 #define MN_roundss (MN_vroundss + 1)
-#define MN_vroundss 0x41f6
+#define MN_vroundss 0x42fe
 #define MN_cmpunordss (MN_vcmpunordss + 1)
-#define MN_vcmpunordss 0x41ff
+#define MN_vcmpunordss 0x4307
 #define MN_cmpordss (MN_vcmpordss + 1)
-#define MN_vcmpordss 0x420b
-#define MN_vreducess 0x4215
-#define MN_vrangess 0x421f
-#define MN_vcmpngess 0x4228
-#define MN_vcmpgess 0x4232
-#define MN_vrndscaless 0x423b
+#define MN_vcmpordss 0x4313
+#define MN_vreducess 0x431d
+#define MN_vrangess 0x4327
+#define MN_vcmpngess 0x4330
+#define MN_vcmpgess 0x433a
+#define MN_vrndscaless 0x4343
 #define MN_cmpnless (MN_vcmpnless + 1)
-#define MN_vcmpnless 0x4247
+#define MN_vcmpnless 0x434f
 #define MN_cmpless (MN_vcmpless + 1)
-#define MN_vcmpless 0x4251
-#define MN_vcmpfalsess 0x425a
-#define MN_vcmptruess 0x4266
-#define MN_vscalefss 0x4271
+#define MN_vcmpless 0x4359
+#define MN_vcmpfalsess 0x4362
+#define MN_vcmptruess 0x436e
+#define MN_vscalefss 0x4379
 #define MN_comiss (MN_ucomiss + 1)
 #define MN_ucomiss (MN_vucomiss + 1)
-#define MN_vucomiss 0x427b
-#define MN_vcomiss 0x4284
+#define MN_vucomiss 0x4383
+#define MN_vcomiss 0x438c
 #define MN_lss (MN_mulss + 2)
 #define MN_mulss (MN_vmulss + 1)
-#define MN_vmulss 0x428c
-#define MN_vfixupimmss 0x4293
+#define MN_vmulss 0x4394
+#define MN_vfixupimmss 0x439b
 #define MN_minss (MN_vminss + 1)
-#define MN_vminss 0x429f
+#define MN_vminss 0x43a7
 #define MN_rcpss (MN_vrcpss + 1)
-#define MN_vrcpss 0x42a6
+#define MN_vrcpss 0x43ae
 #define MN_cmpss (MN_vcmpss + 1)
-#define MN_vcmpss 0x42ad
-#define MN_vgetexpss 0x42b4
-#define MN_vcmpunord_qss 0x42be
-#define MN_vcmpord_qss 0x42cc
+#define MN_vcmpss 0x43b5
+#define MN_vgetexpss 0x43bc
+#define MN_vcmpunord_qss 0x43c6
+#define MN_vcmpord_qss 0x43d4
 #define MN_cmpneqss (MN_vcmpneqss + 1)
-#define MN_vcmpneqss 0x42d8
+#define MN_vcmpneqss 0x43e0
 #define MN_cmpeqss (MN_vcmpeqss + 1)
-#define MN_vcmpeqss 0x42e2
-#define MN_vcmpge_oqss 0x42eb
-#define MN_vcmple_oqss 0x42f7
-#define MN_vcmpfalse_oqss 0x4303
-#define MN_vcmpneq_oqss 0x4312
-#define MN_vcmpeq_oqss 0x431f
-#define MN_vcmpgt_oqss 0x432b
-#define MN_vcmplt_oqss 0x4337
-#define MN_vcmpnge_uqss 0x4343
-#define MN_vcmpnle_uqss 0x4350
-#define MN_vcmptrue_uqss 0x435d
-#define MN_vcmpneq_uqss 0x436b
-#define MN_vcmpeq_uqss 0x4378
-#define MN_vcmpngt_uqss 0x4384
-#define MN_vcmpnlt_uqss 0x4391
-#define MN_vcmpunord_sss 0x439e
-#define MN_vcmpord_sss 0x43ac
-#define MN_vcmpge_osss 0x43b8
-#define MN_vcmple_osss 0x43c4
-#define MN_vcmpfalse_osss 0x43d0
-#define MN_vcmpneq_osss 0x43df
-#define MN_vcmpeq_osss 0x43ec
-#define MN_vcmpgt_osss 0x43f8
-#define MN_vcmplt_osss 0x4404
-#define MN_vfpclassss 0x4410
-#define MN_vcmpnge_usss 0x441b
-#define MN_vcmpnle_usss 0x4428
-#define MN_vcmptrue_usss 0x4435
-#define MN_vcmpneq_usss 0x4443
-#define MN_vcmpeq_usss 0x4450
-#define MN_vcmpngt_usss 0x445c
-#define MN_vcmpnlt_usss 0x4469
-#define MN_vcmpngtss 0x4476
-#define MN_vcmpgtss 0x4480
+#define MN_vcmpeqss 0x43ea
+#define MN_vcmpge_oqss 0x43f3
+#define MN_vcmple_oqss 0x43ff
+#define MN_vcmpfalse_oqss 0x440b
+#define MN_vcmpneq_oqss 0x441a
+#define MN_vcmpeq_oqss 0x4427
+#define MN_vcmpgt_oqss 0x4433
+#define MN_vcmplt_oqss 0x443f
+#define MN_vcmpnge_uqss 0x444b
+#define MN_vcmpnle_uqss 0x4458
+#define MN_vcmptrue_uqss 0x4465
+#define MN_vcmpneq_uqss 0x4473
+#define MN_vcmpeq_uqss 0x4480
+#define MN_vcmpngt_uqss 0x448c
+#define MN_vcmpnlt_uqss 0x4499
+#define MN_vcmpunord_sss 0x44a6
+#define MN_vcmpord_sss 0x44b4
+#define MN_vcmpge_osss 0x44c0
+#define MN_vcmple_osss 0x44cc
+#define MN_vcmpfalse_osss 0x44d8
+#define MN_vcmpneq_osss 0x44e7
+#define MN_vcmpeq_osss 0x44f4
+#define MN_vcmpgt_osss 0x4500
+#define MN_vcmplt_osss 0x450c
+#define MN_vfpclassss 0x4518
+#define MN_vcmpnge_usss 0x4523
+#define MN_vcmpnle_usss 0x4530
+#define MN_vcmptrue_usss 0x453d
+#define MN_vcmpneq_usss 0x454b
+#define MN_vcmpeq_usss 0x4558
+#define MN_vcmpngt_usss 0x4564
+#define MN_vcmpnlt_usss 0x4571
+#define MN_vcmpngtss 0x457e
+#define MN_vcmpgtss 0x4588
 #define MN_cmpnltss (MN_vcmpnltss + 1)
-#define MN_vcmpnltss 0x4489
+#define MN_vcmpnltss 0x4591
 #define MN_cmpltss (MN_vcmpltss + 1)
-#define MN_vcmpltss 0x4493
-#define MN_vgetmantss 0x449c
-#define MN_movntss 0x44a7
+#define MN_vcmpltss 0x459b
+#define MN_vgetmantss 0x45a4
+#define MN_movntss 0x45af
 #define MN_sqrtss (MN_rsqrtss + 1)
 #define MN_rsqrtss (MN_vrsqrtss + 1)
-#define MN_vrsqrtss 0x44af
-#define MN_vsqrtss 0x44b8
-#define MN_vbroadcastss 0x44c0
+#define MN_vrsqrtss 0x45b7
+#define MN_vsqrtss 0x45c0
+#define MN_vbroadcastss 0x45c8
 #define MN_divss (MN_vdivss + 1)
-#define MN_vdivss 0x44cd
+#define MN_vdivss 0x45d5
 #define MN_movss (MN_vmovss + 1)
-#define MN_vmovss 0x44d4
+#define MN_vmovss 0x45dc
 #define MN_maxss (MN_vminmaxss + 4)
-#define MN_vminmaxss 0x44db
-#define MN_vmaxss 0x44e5
-#define MN_vucomxss 0x44ec
-#define MN_vcomxss 0x44f5
-#define MN_vfrczss 0x44fd
-#define MN_bts 0x4505
-#define MN_erets 0x4509
-#define MN_sets 0x450f
-#define MN_clts 0x4514
-#define MN_ctests 0x4519
-#define MN_outs 0x4520
-#define MN_setzus 0x4525
+#define MN_vminmaxss 0x45e3
+#define MN_vmaxss 0x45ed
+#define MN_vucomxss 0x45f4
+#define MN_vcomxss 0x45fd
+#define MN_vfrczss 0x4605
+#define MN_bts 0x460d
+#define MN_erets 0x4611
+#define MN_sets 0x4617
+#define MN_clts 0x461c
+#define MN_ctests 0x4621
+#define MN_outs 0x4628
+#define MN_setzus 0x462d
 #define MN_movs (MN_cmovs + 1)
 #define MN_cmovs (MN_cfcmovs + 2)
-#define MN_cfcmovs 0x452c
-#define MN_fldl2t 0x4534
-#define MN_xlat 0x453b
-#define MN_bt 0x4540
-#define MN_fxtract 0x4543
-#define MN_lgdt 0x454b
-#define MN_sgdt 0x4550
-#define MN_lidt 0x4555
-#define MN_sidt 0x455a
-#define MN_fldt 0x455f
-#define MN_lldt 0x4564
-#define MN_sldt 0x4569
+#define MN_cfcmovs 0x4634
+#define MN_fldl2t 0x463c
+#define MN_xlat 0x4643
+#define MN_bt 0x4648
+#define MN_fxtract 0x464b
+#define MN_lgdt 0x4653
+#define MN_sgdt 0x4658
+#define MN_lidt 0x465d
+#define MN_sidt 0x4662
+#define MN_fldt 0x4667
+#define MN_lldt 0x466c
+#define MN_sldt 0x4671
 #define MN_ret (MN_iret + 1)
 #define MN_iret (MN_uiret + 1)
-#define MN_uiret 0x456e
-#define MN_lret 0x4574
-#define MN_seamret 0x4579
-#define MN_sysret 0x4581
-#define MN_hreset 0x4588
-#define MN_pfcmpgt 0x458f
-#define MN_ht 0x4597
+#define MN_uiret 0x4676
+#define MN_lret 0x467c
+#define MN_seamret 0x4681
+#define MN_sysret 0x4689
+#define MN_hreset 0x4690
+#define MN_pfcmpgt 0x4697
+#define MN_ht 0x469f
 #define MN_wait (MN_fwait + 1)
-#define MN_fwait 0x459a
+#define MN_fwait 0x46a2
 #define MN_mwait (MN_umwait + 1)
-#define MN_umwait 0x45a0
-#define MN_mcommit 0x45a7
-#define MN_finit 0x45af
-#define MN_skinit 0x45b5
-#define MN_fninit 0x45bc
-#define MN_vmgexit 0x45c3
-#define MN_sysexit 0x45cb
-#define MN_hlt 0x45d3
-#define MN_popcnt 0x45d7
-#define MN_lzcnt 0x45de
-#define MN_tzcnt 0x45e4
-#define MN_hnt 0x45ea
+#define MN_umwait 0x46a8
+#define MN_mcommit 0x46af
+#define MN_finit 0x46b7
+#define MN_skinit 0x46bd
+#define MN_fninit 0x46c4
+#define MN_vmgexit 0x46cb
+#define MN_sysexit 0x46d3
+#define MN_hlt 0x46db
+#define MN_popcnt 0x46df
+#define MN_lzcnt 0x46e6
+#define MN_tzcnt 0x46ec
+#define MN_hnt 0x46f2
 #define MN_int (MN_frndint + 4)
-#define MN_frndint 0x45ee
-#define MN_not 0x45f6
-#define MN_invept 0x45fa
-#define MN_ccmpt 0x4601
-#define MN_xsaveopt 0x4607
-#define MN_clflushopt 0x4610
-#define MN_fstpt 0x461b
-#define MN_xabort 0x4621
-#define MN_fsqrt 0x4628
-#define MN_pfrsqrt 0x462e
+#define MN_frndint 0x46f6
+#define MN_not 0x46fe
+#define MN_invept 0x4702
+#define MN_ccmpt 0x4709
+#define MN_xsaveopt 0x470f
+#define MN_clflushopt 0x4718
+#define MN_fstpt 0x4723
+#define MN_xabort 0x4729
+#define MN_fsqrt 0x4730
+#define MN_pfrsqrt 0x4736
 #define MN_aesdeclast (MN_vaesdeclast + 1)
-#define MN_vaesdeclast 0x4636
+#define MN_vaesdeclast 0x473e
 #define MN_aesenclast (MN_vaesenclast + 1)
-#define MN_vaesenclast 0x4642
+#define MN_vaesenclast 0x474a
 #define MN_test (MN_ptest + 1)
 #define MN_ptest (MN_vptest + 1)
-#define MN_vptest 0x464e
-#define MN_xtest 0x4655
-#define MN_fst 0x465b
-#define MN_fist 0x465f
-#define MN_rdmsrlist 0x4664
-#define MN_wrmsrlist 0x466e
+#define MN_vptest 0x4756
+#define MN_xtest 0x475d
+#define MN_fst 0x4763
+#define MN_fist 0x4767
+#define MN_rdmsrlist 0x476c
+#define MN_wrmsrlist 0x4776
 #define MN_aeskeygenassist (MN_vaeskeygenassist + 1)
-#define MN_vaeskeygenassist 0x4678
-#define MN_vmptrst 0x4689
-#define MN_ftst 0x4691
-#define MN_rmpadjust 0x4696
-#define MN_ctestt 0x46a0
-#define MN_out 0x46a7
-#define MN_pext 0x46ab
-#define MN_bndcu 0x46b0
-#define MN_enclu 0x46b6
-#define MN_fcmovnu 0x46bc
+#define MN_vaeskeygenassist 0x4780
+#define MN_vmptrst 0x4791
+#define MN_ftst 0x4799
+#define MN_rmpadjust 0x479e
+#define MN_ctestt 0x47a8
+#define MN_out 0x47af
+#define MN_pext 0x47b3
+#define MN_bndcu 0x47b8
+#define MN_enclu 0x47be
+#define MN_fcmovnu 0x47c4
 #define MN_lddqu (MN_vlddqu + 1)
-#define MN_vlddqu 0x46c4
+#define MN_vlddqu 0x47cc
 #define MN_movdqu (MN_maskmovdqu + 4)
 #define MN_maskmovdqu (MN_vmaskmovdqu + 1)
-#define MN_vmaskmovdqu 0x46cb
-#define MN_vmovdqu 0x46d7
-#define MN_rdpkru 0x46df
-#define MN_wrpkru 0x46e6
-#define MN_rdpru 0x46ed
-#define MN_eretu 0x46f3
-#define MN_fcmovu 0x46f9
-#define MN_imulzu 0x4700
-#define MN_xgetbv 0x4707
-#define MN_xsetbv 0x470e
+#define MN_vmaskmovdqu 0x47d3
+#define MN_vmovdqu 0x47df
+#define MN_rdpkru 0x47e7
+#define MN_wrpkru 0x47ee
+#define MN_rdpru 0x47f5
+#define MN_eretu 0x47fb
+#define MN_fcmovu 0x4801
+#define MN_imulzu 0x4808
+#define MN_xgetbv 0x480f
+#define MN_xsetbv 0x4816
 #define MN_div (MN_fdiv + 1)
-#define MN_fdiv 0x4715
+#define MN_fdiv 0x481d
 #define MN_idiv (MN_fidiv + 1)
-#define MN_fidiv 0x471a
-#define MN_enclv 0x4720
-#define MN_fldenv 0x4726
-#define MN_fstenv 0x472d
-#define MN_fnstenv 0x4734
+#define MN_fidiv 0x4822
+#define MN_enclv 0x4828
+#define MN_fldenv 0x482e
+#define MN_fstenv 0x4835
+#define MN_fnstenv 0x483c
 #define MN_mov (MN_vpcmov + 3)
-#define MN_vpcmov 0x473c
-#define MN_bndmov 0x4743
-#define MN_smov 0x474a
-#define MN_rex_w 0x474f
-#define MN_vcvttph2w 0x4755
-#define MN_vcvtph2w 0x475f
-#define MN_vpermi2w 0x4768
-#define MN_vpmovm2w 0x4771
-#define MN_vpermt2w 0x477a
-#define MN_vpshaw 0x4783
+#define MN_vpcmov 0x4844
+#define MN_bndmov 0x484b
+#define MN_smov 0x4852
+#define MN_rex_w 0x4857
+#define MN_vcvttph2w 0x485d
+#define MN_vcvtph2w 0x4867
+#define MN_vpermi2w 0x4870
+#define MN_vpmovm2w 0x4879
+#define MN_vpermt2w 0x4882
+#define MN_vpshaw 0x488b
 #define MN_psraw (MN_vpsraw + 1)
-#define MN_vpsraw 0x478a
-#define MN_vphsubbw 0x4791
-#define MN_cbw 0x479a
+#define MN_vpsraw 0x4892
+#define MN_vphsubbw 0x4899
+#define MN_cbw 0x48a2
 #define MN_psadbw (MN_vdbpsadbw + 3)
-#define MN_vdbpsadbw 0x479e
+#define MN_vdbpsadbw 0x48a6
 #define MN_mpsadbw (MN_vmpsadbw + 1)
-#define MN_vmpsadbw 0x47a8
-#define MN_vpsadbw 0x47b1
-#define MN_vphaddbw 0x47b9
+#define MN_vmpsadbw 0x48b0
+#define MN_vpsadbw 0x48b9
+#define MN_vphaddbw 0x48c1
 #define MN_punpckhbw (MN_vpunpckhbw + 1)
-#define MN_vpunpckhbw 0x47c2
-#define MN_kunpckbw 0x47cd
+#define MN_vpunpckhbw 0x48ca
+#define MN_kunpckbw 0x48d5
 #define MN_punpcklbw (MN_vpunpcklbw + 1)
-#define MN_vpunpcklbw 0x47d6
-#define MN_vphaddubw 0x47e1
+#define MN_vpunpcklbw 0x48de
+#define MN_vphaddubw 0x48e9
 #define MN_phsubw (MN_vphsubw + 1)
-#define MN_vphsubw 0x47eb
+#define MN_vphsubw 0x48f3
 #define MN_psubw (MN_vpsubw + 1)
-#define MN_vpsubw 0x47f3
+#define MN_vpsubw 0x48fb
 #define MN_pmovsxbw (MN_vpmovsxbw + 1)
-#define MN_vpmovsxbw 0x47fa
+#define MN_vpmovsxbw 0x4902
 #define MN_pmovzxbw (MN_vpmovzxbw + 1)
-#define MN_vpmovzxbw 0x4804
-#define MN_fldcw 0x480e
-#define MN_fstcw 0x4814
-#define MN_fnstcw 0x481a
+#define MN_vpmovzxbw 0x490c
+#define MN_fldcw 0x4916
+#define MN_fstcw 0x491c
+#define MN_fnstcw 0x4922
 #define MN_phaddw (MN_vphaddw + 1)
-#define MN_vphaddw 0x4821
-#define MN_kaddw 0x4829
+#define MN_vphaddw 0x4929
+#define MN_kaddw 0x4931
 #define MN_paddw (MN_vpaddw + 1)
-#define MN_vpaddw 0x482f
-#define MN_vpshldw 0x4836
-#define MN_kandw 0x483e
-#define MN_vpexpandw 0x4844
+#define MN_vpaddw 0x4937
+#define MN_vpshldw 0x493e
+#define MN_kandw 0x4946
+#define MN_vpexpandw 0x494c
 #define MN_pblendw (MN_vpblendw + 1)
-#define MN_vpblendw 0x484e
-#define MN_vpshrdw 0x4857
+#define MN_vpblendw 0x4956
+#define MN_vpshrdw 0x495f
 #define MN_packssdw (MN_vpackssdw + 1)
-#define MN_vpackssdw 0x485f
+#define MN_vpackssdw 0x4967
 #define MN_packusdw (MN_vpackusdw + 1)
-#define MN_vpackusdw 0x4869
-#define MN_vpmovusdw 0x4873
-#define MN_vpmovsdw 0x487d
-#define MN_vpmovdw 0x4886
-#define MN_vpcomgew 0x488e
-#define MN_vpcomlew 0x4897
-#define MN_vpcmpnlew 0x48a0
-#define MN_vpcmplew 0x48aa
-#define MN_vpcomfalsew 0x48b3
-#define MN_vpcomtruew 0x48bf
-#define MN_pi2fw 0x48ca
-#define MN_pshufw 0x48d0
+#define MN_vpackusdw 0x4971
+#define MN_vpmovusdw 0x497b
+#define MN_vpmovsdw 0x4985
+#define MN_vpmovdw 0x498e
+#define MN_vpcomgew 0x4996
+#define MN_vpcomlew 0x499f
+#define MN_vpcmpnlew 0x49a8
+#define MN_vpcmplew 0x49b2
+#define MN_vpcomfalsew 0x49bb
+#define MN_vpcomtruew 0x49c7
+#define MN_pi2fw 0x49d2
+#define MN_pshufw 0x49d8
 #define MN_pavgw (MN_vpavgw + 1)
-#define MN_vpavgw 0x48d7
-#define MN_prefetchw 0x48de
+#define MN_vpavgw 0x49df
+#define MN_prefetchw 0x49e6
 #define MN_pshufhw (MN_vpshufhw + 1)
-#define MN_vpshufhw 0x48e8
+#define MN_vpshufhw 0x49f0
 #define MN_pmulhw (MN_vpmulhw + 1)
-#define MN_vpmulhw 0x48f1
-#define MN_pf2iw 0x48f9
+#define MN_vpmulhw 0x49f9
+#define MN_pf2iw 0x4a01
 #define MN_pshuflw (MN_vpshuflw + 1)
-#define MN_vpshuflw 0x48ff
-#define MN_vpshlw 0x4908
+#define MN_vpshuflw 0x4a07
+#define MN_vpshlw 0x4a10
 #define MN_psllw (MN_vpsllw + 1)
-#define MN_vpsllw 0x490f
+#define MN_vpsllw 0x4a17
 #define MN_pmullw (MN_vpmullw + 1)
-#define MN_vpmullw 0x4916
+#define MN_vpmullw 0x4a1e
 #define MN_psrlw (MN_vpsrlw + 1)
-#define MN_vpsrlw 0x491e
-#define MN_kshiftlw 0x4925
-#define MN_vpblendmw 0x492e
-#define MN_vptestnmw 0x4938
-#define MN_vpcomw 0x4942
-#define MN_vpermw 0x4949
-#define MN_vptestmw 0x4950
-#define MN_kandnw 0x4959
+#define MN_vpsrlw 0x4a26
+#define MN_kshiftlw 0x4a2d
+#define MN_vpblendmw 0x4a36
+#define MN_vptestnmw 0x4a40
+#define MN_vpcomw 0x4a4a
+#define MN_vpermw 0x4a51
+#define MN_vptestmw 0x4a58
+#define MN_kandnw 0x4a61
 #define MN_psignw (MN_vpsignw + 1)
-#define MN_vpsignw 0x4960
-#define MN_tilemovrow 0x4968
-#define MN_vpcmpw 0x4973
-#define MN_vpcomeqw 0x497a
-#define MN_vpcomneqw 0x4983
-#define MN_vpcmpneqw 0x498d
+#define MN_vpsignw 0x4a68
+#define MN_tilemovrow 0x4a70
+#define MN_vpcmpw 0x4a7b
+#define MN_vpcomeqw 0x4a82
+#define MN_vpcomneqw 0x4a8b
+#define MN_vpcmpneqw 0x4a95
 #define MN_pcmpeqw (MN_vpcmpeqw + 1)
-#define MN_vpcmpeqw 0x4997
-#define MN_vpmovusqw 0x49a0
-#define MN_vpmovsqw 0x49aa
-#define MN_vpmovqw 0x49b3
-#define MN_verw 0x49bb
-#define MN_pmulhrw 0x49c0
-#define MN_korw 0x49c8
-#define MN_kxnorw 0x49cd
-#define MN_kxorw 0x49d4
+#define MN_vpcmpeqw 0x4a9f
+#define MN_vpmovusqw 0x4aa8
+#define MN_vpmovsqw 0x4ab2
+#define MN_vpmovqw 0x4abb
+#define MN_verw 0x4ac3
+#define MN_pmulhrw 0x4ac8
+#define MN_korw 0x4ad0
+#define MN_kxnorw 0x4ad5
+#define MN_kxorw 0x4adc
 #define MN_pinsrw (MN_vpinsrw + 1)
-#define MN_vpinsrw 0x49da
-#define MN_kshiftrw 0x49e2
+#define MN_vpinsrw 0x4ae2
+#define MN_kshiftrw 0x4aea
 #define MN_pextrw (MN_vpextrw + 1)
-#define MN_vpextrw 0x49eb
+#define MN_vpextrw 0x4af3
 #define MN_pabsw (MN_vpabsw + 1)
-#define MN_vpabsw 0x49f3
+#define MN_vpabsw 0x4afb
 #define MN_pmaddubsw (MN_vpmaddubsw + 1)
-#define MN_vpmaddubsw 0x49fa
+#define MN_vpmaddubsw 0x4b02
 #define MN_phsubsw (MN_vphsubsw + 1)
-#define MN_vphsubsw 0x4a05
+#define MN_vphsubsw 0x4b0d
 #define MN_psubsw (MN_vpsubsw + 1)
-#define MN_vpsubsw 0x4a0e
+#define MN_vpsubsw 0x4b16
 #define MN_phaddsw (MN_vphaddsw + 1)
-#define MN_vphaddsw 0x4a16
+#define MN_vphaddsw 0x4b1e
 #define MN_paddsw (MN_vpaddsw + 1)
-#define MN_vpaddsw 0x4a1f
-#define MN_lmsw 0x4a27
-#define MN_smsw 0x4a2c
+#define MN_vpaddsw 0x4b27
+#define MN_lmsw 0x4b2f
+#define MN_smsw 0x4b34
 #define MN_pminsw (MN_vpminsw + 1)
-#define MN_vpminsw 0x4a31
+#define MN_vpminsw 0x4b39
 #define MN_pmulhrsw (MN_vpmulhrsw + 1)
-#define MN_vpmulhrsw 0x4a39
-#define MN_vmovrsw 0x4a43
-#define MN_vpcompressw 0x4a4b
-#define MN_fstsw 0x4a57
-#define MN_fnstsw 0x4a5d
+#define MN_vpmulhrsw 0x4b41
+#define MN_vmovrsw 0x4b4b
+#define MN_vpcompressw 0x4b53
+#define MN_fstsw 0x4b5f
+#define MN_fnstsw 0x4b65
 #define MN_psubusw (MN_vpsubusw + 1)
-#define MN_vpsubusw 0x4a64
+#define MN_vpsubusw 0x4b6c
 #define MN_paddusw (MN_vpaddusw + 1)
-#define MN_vpaddusw 0x4a6d
-#define MN_movsw 0x4a76
+#define MN_vpaddusw 0x4b75
+#define MN_movsw 0x4b7e
 #define MN_pmaxsw (MN_vpmaxsw + 1)
-#define MN_vpmaxsw 0x4a7c
-#define MN_cbtw 0x4a84
-#define MN_vpcomgtw 0x4a89
+#define MN_vpmaxsw 0x4b84
+#define MN_cbtw 0x4b8c
+#define MN_vpcomgtw 0x4b91
 #define MN_pcmpgtw (MN_vpcmpgtw + 1)
-#define MN_vpcmpgtw 0x4a92
-#define MN_vpcomltw 0x4a9b
-#define MN_vpcmpnltw 0x4aa4
-#define MN_vpcmpltw 0x4aae
-#define MN_vpopcntw 0x4ab7
-#define MN_knotw 0x4ac0
-#define MN_vprotw 0x4ac6
-#define MN_vpbroadcastw 0x4acd
-#define MN_ktestw 0x4ada
-#define MN_kortestw 0x4ae1
-#define MN_vcvttph2uw 0x4aea
-#define MN_vcvtph2uw 0x4af5
-#define MN_vpcomgeuw 0x4aff
-#define MN_vpcomleuw 0x4b09
-#define MN_vpcmpnleuw 0x4b13
-#define MN_vpcmpleuw 0x4b1e
-#define MN_vpcomfalseuw 0x4b28
-#define MN_vpcomtrueuw 0x4b35
+#define MN_vpcmpgtw 0x4b9a
+#define MN_vpcomltw 0x4ba3
+#define MN_vpcmpnltw 0x4bac
+#define MN_vpcmpltw 0x4bb6
+#define MN_vpopcntw 0x4bbf
+#define MN_knotw 0x4bc8
+#define MN_vprotw 0x4bce
+#define MN_vpbroadcastw 0x4bd5
+#define MN_ktestw 0x4be2
+#define MN_kortestw 0x4be9
+#define MN_vcvttph2uw 0x4bf2
+#define MN_vcvtph2uw 0x4bfd
+#define MN_vpcomgeuw 0x4c07
+#define MN_vpcomleuw 0x4c11
+#define MN_vpcmpnleuw 0x4c1b
+#define MN_vpcmpleuw 0x4c26
+#define MN_vpcomfalseuw 0x4c30
+#define MN_vpcomtrueuw 0x4c3d
 #define MN_pmulhuw (MN_vpmulhuw + 1)
-#define MN_vpmulhuw 0x4b41
-#define MN_vpcomuw 0x4b4a
+#define MN_vpmulhuw 0x4c49
+#define MN_vpcomuw 0x4c52
 #define MN_pminuw (MN_vpminuw + 1)
-#define MN_vpminuw 0x4b52
-#define MN_vpcmpuw 0x4b5a
-#define MN_vpcomequw 0x4b62
-#define MN_vpcomnequw 0x4b6c
-#define MN_vpcmpnequw 0x4b77
-#define MN_vpcmpequw 0x4b82
+#define MN_vpminuw 0x4c5a
+#define MN_vpcmpuw 0x4c62
+#define MN_vpcomequw 0x4c6a
+#define MN_vpcomnequw 0x4c74
+#define MN_vpcmpnequw 0x4c7f
+#define MN_vpcmpequw 0x4c8a
 #define MN_phminposuw (MN_vphminposuw + 1)
-#define MN_vphminposuw 0x4b8c
-#define MN_vpcomgtuw 0x4b98
-#define MN_vpcomltuw 0x4ba2
-#define MN_vpcmpnltuw 0x4bac
-#define MN_vpcmpltuw 0x4bb7
+#define MN_vphminposuw 0x4c94
+#define MN_vpcomgtuw 0x4ca0
+#define MN_vpcomltuw 0x4caa
+#define MN_vpcmpnltuw 0x4cb4
+#define MN_vpcmpltuw 0x4cbf
 #define MN_pmaxuw (MN_vpmaxuw + 1)
-#define MN_vpmaxuw 0x4bc1
-#define MN_vpsravw 0x4bc9
-#define MN_vpshldvw 0x4bd1
-#define MN_vpshrdvw 0x4bda
-#define MN_vpsllvw 0x4be3
-#define MN_vpsrlvw 0x4beb
-#define MN_kmovw 0x4bf3
-#define MN_vmovw 0x4bf9
-#define MN_vpmacsww 0x4bff
-#define MN_vpmacssww 0x4c08
-#define MN_movzw 0x4c12
-#define MN_rex_x 0x4c18
-#define MN_fyl2x 0x4c1e
-#define MN_rex64x 0x4c24
-#define MN_vcvtneps2bf16x 0x4c2b
-#define MN_vfpclassbf16x 0x4c3a
-#define MN_vcvtph2bf8x 0x4c48
-#define MN_vcvtph2hf8x 0x4c54
-#define MN_pfmax 0x4c60
-#define MN_adcx 0x4c66
-#define MN_bndldx 0x4c6b
-#define MN_vfpclasspdx 0x4c72
-#define MN_fclex 0x4c7e
-#define MN_fnclex 0x4c84
-#define MN_rex 0x4c8b
-#define MN_vcvtpd2phx 0x4c8f
-#define MN_vcvtdq2phx 0x4c9a
-#define MN_vcvtudq2phx 0x4ca5
-#define MN_vcvtqq2phx 0x4cb1
-#define MN_vcvtuqq2phx 0x4cbc
-#define MN_vcvt2ps2phx 0x4cc8
-#define MN_vcvtps2phx 0x4cd4
-#define MN_vfpclassphx 0x4cdf
-#define MN_shlx 0x4ceb
-#define MN_mulx 0x4cf0
-#define MN_adox 0x4cf5
-#define MN_vcvttpd2dqx 0x4cfa
-#define MN_vcvtpd2dqx 0x4d06
-#define MN_vcvttpd2udqx 0x4d11
-#define MN_vcvtpd2udqx 0x4d1e
-#define MN_rex_rx 0x4d2a
-#define MN_sarx 0x4d31
-#define MN_shrx 0x4d36
-#define MN_rorx 0x4d3b
-#define MN_monitorx 0x4d40
-#define MN_rex_wrx 0x4d49
-#define MN_vcvtph2bf8sx 0x4d51
-#define MN_vcvtph2hf8sx 0x4d5e
-#define MN_vcvtpd2psx 0x4d6b
-#define MN_vcvtph2psx 0x4d76
-#define MN_vcvtqq2psx 0x4d81
-#define MN_vcvtuqq2psx 0x4d8c
-#define MN_vfpclasspsx 0x4d98
-#define MN_vcvttpd2dqsx 0x4da4
-#define MN_vcvttpd2udqsx 0x4db1
-#define MN_movsx 0x4dbf
-#define MN_mwaitx 0x4dc5
-#define MN_bndstx 0x4dcc
-#define MN_rex_wx 0x4dd3
-#define MN_rexx 0x4dda
-#define MN_vcvtps2phxx 0x4ddf
-#define MN_movzx 0x4deb
-#define MN_rex64y 0x4df1
-#define MN_vcvtneps2bf16y 0x4df8
-#define MN_vfpclassbf16y 0x4e07
-#define MN_vcvtph2bf8y 0x4e15
-#define MN_vcvtph2hf8y 0x4e21
-#define MN_vfpclasspdy 0x4e2d
-#define MN_loadiwkey 0x4e39
-#define MN_vcvtpd2phy 0x4e43
-#define MN_vcvtdq2phy 0x4e4e
-#define MN_vcvtudq2phy 0x4e59
-#define MN_vcvtqq2phy 0x4e65
-#define MN_vcvtuqq2phy 0x4e70
-#define MN_vfpclassphy 0x4e7c
-#define MN_vcvttpd2dqy 0x4e88
-#define MN_vcvtpd2dqy 0x4e94
-#define MN_vcvttpd2udqy 0x4e9f
-#define MN_vcvtpd2udqy 0x4eac
-#define MN_rmpquery 0x4eb8
-#define MN_vcvtph2bf8sy 0x4ec1
-#define MN_vcvtph2hf8sy 0x4ece
-#define MN_clrssbsy 0x4edb
-#define MN_setssbsy 0x4ee4
-#define MN_vcvtpd2psy 0x4eed
-#define MN_vcvtqq2psy 0x4ef8
-#define MN_vcvtuqq2psy 0x4f03
-#define MN_vfpclasspsy 0x4f0f
-#define MN_vcvttpd2dqsy 0x4f1b
-#define MN_vcvttpd2udqsy 0x4f28
-#define MN_rex64xy 0x4f36
-#define MN_rexy 0x4f3e
-#define MN_vcvtps2phxy 0x4f43
-#define MN_rexxy 0x4f4f
-#define MN_rex64z 0x4f55
-#define MN_vfpclassbf16z 0x4f5c
-#define MN_fldz 0x4f6a
-#define MN_vfpclasspdz 0x4f6f
-#define MN_vcvtpd2phz 0x4f7b
-#define MN_vcvtqq2phz 0x4f86
-#define MN_vcvtuqq2phz 0x4f91
-#define MN_vfpclassphz 0x4f9d
-#define MN_jz 0x4fa9
-#define MN_jnz 0x4fac
-#define MN_repnz 0x4fb0
-#define MN_ccmpnz 0x4fb6
-#define MN_loopnz 0x4fbd
-#define MN_setnz 0x4fc4
-#define MN_ctestnz 0x4fca
-#define MN_setzunz 0x4fd2
+#define MN_vpmaxuw 0x4cc9
+#define MN_vpsravw 0x4cd1
+#define MN_vpshldvw 0x4cd9
+#define MN_vpshrdvw 0x4ce2
+#define MN_vpsllvw 0x4ceb
+#define MN_vpsrlvw 0x4cf3
+#define MN_kmovw 0x4cfb
+#define MN_vmovw 0x4d01
+#define MN_vpmacsww 0x4d07
+#define MN_vpmacssww 0x4d10
+#define MN_movzw 0x4d1a
+#define MN_rex_x 0x4d20
+#define MN_fyl2x 0x4d26
+#define MN_rex64x 0x4d2c
+#define MN_vcvtneps2bf16x 0x4d33
+#define MN_vfpclassbf16x 0x4d42
+#define MN_vcvtph2bf8x 0x4d50
+#define MN_vcvtph2hf8x 0x4d5c
+#define MN_pfmax 0x4d68
+#define MN_adcx 0x4d6e
+#define MN_bndldx 0x4d73
+#define MN_vfpclasspdx 0x4d7a
+#define MN_fclex 0x4d86
+#define MN_fnclex 0x4d8c
+#define MN_rex 0x4d93
+#define MN_vcvtpd2phx 0x4d97
+#define MN_vcvtdq2phx 0x4da2
+#define MN_vcvtudq2phx 0x4dad
+#define MN_vcvtqq2phx 0x4db9
+#define MN_vcvtuqq2phx 0x4dc4
+#define MN_vcvt2ps2phx 0x4dd0
+#define MN_vcvtps2phx 0x4ddc
+#define MN_vfpclassphx 0x4de7
+#define MN_shlx 0x4df3
+#define MN_mulx 0x4df8
+#define MN_adox 0x4dfd
+#define MN_vcvttpd2dqx 0x4e02
+#define MN_vcvtpd2dqx 0x4e0e
+#define MN_vcvttpd2udqx 0x4e19
+#define MN_vcvtpd2udqx 0x4e26
+#define MN_rex_rx 0x4e32
+#define MN_sarx 0x4e39
+#define MN_shrx 0x4e3e
+#define MN_rorx 0x4e43
+#define MN_monitorx 0x4e48
+#define MN_rex_wrx 0x4e51
+#define MN_vcvtph2bf8sx 0x4e59
+#define MN_vcvtph2hf8sx 0x4e66
+#define MN_vcvtpd2psx 0x4e73
+#define MN_vcvtph2psx 0x4e7e
+#define MN_vcvtqq2psx 0x4e89
+#define MN_vcvtuqq2psx 0x4e94
+#define MN_vfpclasspsx 0x4ea0
+#define MN_vcvttpd2dqsx 0x4eac
+#define MN_vcvttpd2udqsx 0x4eb9
+#define MN_movsx 0x4ec7
+#define MN_mwaitx 0x4ecd
+#define MN_bndstx 0x4ed4
+#define MN_rex_wx 0x4edb
+#define MN_rexx 0x4ee2
+#define MN_vcvtps2phxx 0x4ee7
+#define MN_movzx 0x4ef3
+#define MN_rex64y 0x4ef9
+#define MN_vcvtneps2bf16y 0x4f00
+#define MN_vfpclassbf16y 0x4f0f
+#define MN_vcvtph2bf8y 0x4f1d
+#define MN_vcvtph2hf8y 0x4f29
+#define MN_vfpclasspdy 0x4f35
+#define MN_loadiwkey 0x4f41
+#define MN_vcvtpd2phy 0x4f4b
+#define MN_vcvtdq2phy 0x4f56
+#define MN_vcvtudq2phy 0x4f61
+#define MN_vcvtqq2phy 0x4f6d
+#define MN_vcvtuqq2phy 0x4f78
+#define MN_vfpclassphy 0x4f84
+#define MN_vcvttpd2dqy 0x4f90
+#define MN_vcvtpd2dqy 0x4f9c
+#define MN_vcvttpd2udqy 0x4fa7
+#define MN_vcvtpd2udqy 0x4fb4
+#define MN_rmpquery 0x4fc0
+#define MN_vcvtph2bf8sy 0x4fc9
+#define MN_vcvtph2hf8sy 0x4fd6
+#define MN_clrssbsy 0x4fe3
+#define MN_setssbsy 0x4fec
+#define MN_vcvtpd2psy 0x4ff5
+#define MN_vcvtqq2psy 0x5000
+#define MN_vcvtuqq2psy 0x500b
+#define MN_vfpclasspsy 0x5017
+#define MN_vcvttpd2dqsy 0x5023
+#define MN_vcvttpd2udqsy 0x5030
+#define MN_rex64xy 0x503e
+#define MN_rexy 0x5046
+#define MN_vcvtps2phxy 0x504b
+#define MN_rexxy 0x5057
+#define MN_rex64z 0x505d
+#define MN_vfpclassbf16z 0x5064
+#define MN_fldz 0x5072
+#define MN_vfpclasspdz 0x5077
+#define MN_vcvtpd2phz 0x5083
+#define MN_vcvtqq2phz 0x508e
+#define MN_vcvtuqq2phz 0x5099
+#define MN_vfpclassphz 0x50a5
+#define MN_jz 0x50b1
+#define MN_jnz 0x50b4
+#define MN_repnz 0x50b8
+#define MN_ccmpnz 0x50be
+#define MN_loopnz 0x50c5
+#define MN_setnz 0x50cc
+#define MN_ctestnz 0x50d2
+#define MN_setzunz 0x50da
 #define MN_cmovnz (MN_cfcmovnz + 2)
-#define MN_cfcmovnz 0x4fda
-#define MN_repz 0x4fe3
-#define MN_ccmpz 0x4fe8
-#define MN_loopz 0x4fee
-#define MN_vfpclasspsz 0x4ff4
-#define MN_setz 0x5000
-#define MN_ctestz 0x5005
-#define MN_setzuz 0x500c
+#define MN_cfcmovnz 0x50e2
+#define MN_repz 0x50eb
+#define MN_ccmpz 0x50f0
+#define MN_loopz 0x50f6
+#define MN_vfpclasspsz 0x50fc
+#define MN_setz 0x5108
+#define MN_ctestz 0x510d
+#define MN_setzuz 0x5114
 #define MN_cmovz (MN_cfcmovz + 2)
-#define MN_cfcmovz 0x5013
-#define MN_rex64xz 0x501b
-#define MN_jecxz 0x5023
-#define MN_jcxz 0x5029
-#define MN_jrcxz 0x502e
-#define MN_rexz 0x5034
-#define MN_rexxz 0x5039
-#define MN_rex64yz 0x503f
-#define MN_rex64xyz 0x5047
-#define MN_rexyz 0x5050
-#define MN_rexxyz 0x5056
-#define MN__disp32_ 0x505d
-#define MN__rex2_ 0x5066
-#define MN__vex2_ 0x506d
-#define MN__vex3_ 0x5074
-#define MN__disp16_ 0x507b
-#define MN__disp8_ 0x5084
-#define MN__load_ 0x508c
-#define MN__store_ 0x5093
-#define MN__nooptimize_ 0x509b
-#define MN__nf_ 0x50a8
-#define MN__noimm8s_ 0x50ad
-#define MN__rex_ 0x50b7
-#define MN__evex_ 0x50bd
-#define MN__vex_ 0x50c4
-#define MN__insn 0x50ca
+#define MN_cfcmovz 0x511b
+#define MN_rex64xz 0x5123
+#define MN_jecxz 0x512b
+#define MN_jcxz 0x5131
+#define MN_jrcxz 0x5136
+#define MN_rexz 0x513c
+#define MN_rexxz 0x5141
+#define MN_rex64yz 0x5147
+#define MN_rex64xyz 0x514f
+#define MN_rexyz 0x5158
+#define MN_rexxyz 0x515e
+#define MN__disp32_ 0x5165
+#define MN__rex2_ 0x516e
+#define MN__vex2_ 0x5175
+#define MN__vex3_ 0x517c
+#define MN__disp16_ 0x5183
+#define MN__disp8_ 0x518c
+#define MN__load_ 0x5194
+#define MN__store_ 0x519b
+#define MN__nooptimize_ 0x51a3
+#define MN__nf_ 0x51b0
+#define MN__noimm8s_ 0x51b5
+#define MN__rex_ 0x51bf
+#define MN__evex_ 0x51c5
+#define MN__vex_ 0x51cc
+#define MN__insn 0x51d2
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 54038f90761..0c5f7747ed2 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -328,6 +328,8 @@ enum i386_cpu
   CpuAPX_NDD,
   /* Intel APX No-Flags-update support required.  */
   CpuAPX_NF,
+  /* AVX10.2 Auxiliary Instructions support required.  */
+  CpuAVX10_V2_AUX,
 
   /* NOTE: These items, which can be combined with other ISA flags above, need
      to remain second to last and in sync with CPU_FLAGS_COMMON. */
@@ -567,6 +569,7 @@ typedef union i386_cpu_flags
       unsigned int cpuapx_nci:1;
       unsigned int cpuapx_ndd:1;
       unsigned int cpuapx_nf:1;
+      unsigned int cpuavx10_v2_aux:1;
       CPU_FLAGS_COMMON;
 #ifdef CpuUnused
       unsigned int unused:(CpuNumOfBits - CpuUnused);
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 7042ca4512e..3d3e37b09aa 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3620,6 +3620,95 @@ vucomxs<sdh>, 0x<sdh:spfx>2e, AVX10_2, Modrm|EVexLIG|<sdh:spc1>|<sdh:vexw>|Disp8
 
 // AVX10.2 instructions end.
 
+// AVX10_V2_AUX instructions.
+
+// VCVTPS2BF8, VCVTPS2BF8S, VCVTPS2HF8, VCVTPS2HF8S - narrowing 2-op (F3.MAP5)
+// VCVTROPS2HF8, VCVTROPS2HF8S - narrowing 2-op (66.MAP5)
+
+<cvtps8:opc:pfx, +
+    bf8:39:f3, +
+    bf8s:3b:f3, +
+    hf8:38:f3, +
+    hf8s:3a:f3>
+
+vcvtps2<cvtps8>, 0x<cvtps8:pfx><cvtps8:opc>, AVX10_V2_AUX, Modrm|Map5|EVex128|VexW0|Masking|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
+vcvtps2<cvtps8>, 0x<cvtps8:pfx><cvtps8:opc>, AVX10_V2_AUX, Modrm|Map5|EVex256|VexW0|Masking|Broadcast|Disp8MemShift=5|NoSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegXMM }
+vcvtps2<cvtps8>, 0x<cvtps8:pfx><cvtps8:opc>, AVX10_V2_AUX, Modrm|Map5|EVex512|VexW0|Masking|Broadcast|Disp8MemShift=6|NoSuf, { RegZMM|Dword|Unspecified|BaseIndex, RegXMM }
+
+<cvtps8>
+
+<cvtrops8:opc, +
+    hf8:38, +
+    hf8s:3a>
+
+vcvtrops2<cvtrops8>, 0x66<cvtrops8:opc>, AVX10_V2_AUX, Modrm|Map5|EVex128|VexW0|Masking|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
+vcvtrops2<cvtrops8>, 0x66<cvtrops8:opc>, AVX10_V2_AUX, Modrm|Map5|EVex256|VexW0|Masking|Broadcast|Disp8MemShift=5|NoSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegXMM }
+vcvtrops2<cvtrops8>, 0x66<cvtrops8:opc>, AVX10_V2_AUX, Modrm|Map5|EVex512|VexW0|Masking|Broadcast|Disp8MemShift=6|NoSuf, { RegZMM|Dword|Unspecified|BaseIndex, RegXMM }
+
+<cvtrops8>
+
+// VCVTBIASPS2BF8, VCVTBIASPS2BF8S, VCVTBIASPS2HF8, VCVTBIASPS2HF8S - 3-op narrowing (NP.MAP5)
+
+<cvtbiasps:opc, +
+    bf8:39, +
+    bf8s:3b, +
+    hf8:38, +
+    hf8s:3a>
+
+vcvtbiasps2<cvtbiasps>, 0x<cvtbiasps:opc>, AVX10_V2_AUX, Modrm|Map5|EVex128|Src1VVVV|VexW0|Masking|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM }
+vcvtbiasps2<cvtbiasps>, 0x<cvtbiasps:opc>, AVX10_V2_AUX, Modrm|Map5|EVex256|Src1VVVV|VexW0|Masking|Broadcast|Disp8MemShift=5|NoSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegYMM, RegXMM }
+vcvtbiasps2<cvtbiasps>, 0x<cvtbiasps:opc>, AVX10_V2_AUX, Modrm|Map5|EVex512|Src1VVVV|VexW0|Masking|Broadcast|Disp8MemShift=6|NoSuf, { RegZMM|Dword|Unspecified|BaseIndex, RegZMM, RegXMM }
+
+<cvtbiasps>
+
+// VCVTBF82PS (NP.MAP5.W1) and VCVTHF82PS (NP.MAP5.W0) - widening xmm/m to xmm/ymm/zmm
+vcvtbf82ps, 0x36, AVX10_V2_AUX, Modrm|Map5|EVex128|VexW1|Masking|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
+vcvtbf82ps, 0x36, AVX10_V2_AUX, Modrm|Map5|EVex256|VexW1|Masking|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM }
+vcvtbf82ps, 0x36, AVX10_V2_AUX, Modrm|Map5|EVex512|VexW1|Masking|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM }
+
+vcvthf82ps, 0x36, AVX10_V2_AUX, Modrm|Map5|EVex128|VexW0|Masking|Disp8MemShift=2|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
+vcvthf82ps, 0x36, AVX10_V2_AUX, Modrm|Map5|EVex256|VexW0|Masking|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM }
+vcvthf82ps, 0x36, AVX10_V2_AUX, Modrm|Map5|EVex512|VexW0|Masking|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegZMM }
+
+// VCVTBF82BF4S (F3.MAP5.W1) and VCVTHF82BF4S (F3.MAP5.W0) - narrowing, no mask
+vcvtbf82bf4s, 0xf33d, AVX10_V2_AUX, Modrm|Map5|EVex128|VexW1|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex }
+vcvtbf82bf4s, 0xf33d, AVX10_V2_AUX, Modrm|Map5|EVex256|VexW1|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex }
+vcvtbf82bf4s, 0xf33d, AVX10_V2_AUX, Modrm|Map5|EVex512|VexW1|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex }
+
+vcvthf82bf4s, 0xf33d, AVX10_V2_AUX, Modrm|Map5|EVex128|VexW0|Disp8MemShift=3|NoSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex }
+vcvthf82bf4s, 0xf33d, AVX10_V2_AUX, Modrm|Map5|EVex256|VexW0|Disp8MemShift=4|NoSuf, { RegYMM, RegXMM|Unspecified|BaseIndex }
+vcvthf82bf4s, 0xf33d, AVX10_V2_AUX, Modrm|Map5|EVex512|VexW0|Disp8MemShift=5|NoSuf, { RegZMM, RegYMM|Unspecified|BaseIndex }
+
+// VCVTBF82BF6S (F3.MAP5.W1) - reg-reg only, no mask
+vcvtbf82bf6s, 0xf33e, AVX10_V2_AUX, Modrm|Map5|EVex128|VexW1|NoSuf, { RegXMM, RegXMM }
+vcvtbf82bf6s, 0xf33e, AVX10_V2_AUX, Modrm|Map5|EVex256|VexW1|NoSuf, { RegYMM, RegYMM }
+vcvtbf82bf6s, 0xf33e, AVX10_V2_AUX, Modrm|Map5|EVex512|VexW1|NoSuf, { RegZMM, RegZMM }
+
+// VCVTHF82HF6S (F3.MAP5.W0) - reg-reg only, no mask
+vcvthf82hf6s, 0xf33c, AVX10_V2_AUX, Modrm|Map5|EVex128|VexW0|NoSuf, { RegXMM, RegXMM }
+vcvthf82hf6s, 0xf33c, AVX10_V2_AUX, Modrm|Map5|EVex256|VexW0|NoSuf, { RegYMM, RegYMM }
+vcvthf82hf6s, 0xf33c, AVX10_V2_AUX, Modrm|Map5|EVex512|VexW0|NoSuf, { RegZMM, RegZMM }
+
+// VCVTBF42HF8 (NP.MAP5.W0) - widening-like xmm/m to xmm/ymm/zmm, with mask
+vcvtbf42hf8, 0x37, AVX10_V2_AUX, Modrm|Map5|EVex128|VexW0|Masking|Disp8MemShift=3|NoSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM }
+vcvtbf42hf8, 0x37, AVX10_V2_AUX, Modrm|Map5|EVex256|VexW0|Masking|Disp8MemShift=4|NoSuf, { RegXMM|Unspecified|BaseIndex, RegYMM }
+vcvtbf42hf8, 0x37, AVX10_V2_AUX, Modrm|Map5|EVex512|VexW0|Masking|Disp8MemShift=5|NoSuf, { RegYMM|Unspecified|BaseIndex, RegZMM }
+
+// VCVTBF62HF8 (66.MAP5.W1) and VCVTHF62HF8 (66.MAP5.W0) - reg-reg, with mask
+vcvtbf62hf8, 0x6637, AVX10_V2_AUX, Modrm|Map5|VexW1|Masking|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+
+vcvthf62hf8, 0x6637, AVX10_V2_AUX, Modrm|Map5|VexW0|Masking|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
+
+// VPMOVSSDB (F3.0F38.W0) - narrowing store with mask
+vpmovssdb, 0xf341, AVX10_V2_AUX, Modrm|EVex128|Masking|Space0F38|VexW0|Disp8MemShift=2|NoSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex }
+vpmovssdb, 0xf341, AVX10_V2_AUX, Modrm|EVex256|Masking|Space0F38|VexW0|Disp8MemShift=3|NoSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex }
+vpmovssdb, 0xf341, AVX10_V2_AUX, Modrm|EVex512|Masking|Space0F38|VexW0|Disp8MemShift=4|NoSuf, { RegZMM, RegXMM|Unspecified|BaseIndex }
+
+// VUNPACKB (NP.0F3A.W0) - with imm8
+vunpackb, 0x3d, AVX10_V2_AUX, Modrm|Masking|Space0F3A|VexW0|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
+
+// AVX10_V2_AUX instructions end.
+
 // MOVRS instructions.
 
 prefetchrst2, 0xf18/4, MOVRS, Modrm|Anysize|IgnoreSize|NoSuf, { BaseIndex }
diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 5215f774202..5154d1dfd57 100644
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -48116,6 +48116,602 @@ static const insn_template i386_optab[] =
 	  1, 0, 0, 0, 1, 0 } },
       { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtps2bf8, 0x39, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 2, 0, 0, 2, 1, 3, 0, 0, 4, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  1, 0, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtps2bf8, 0x39, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 2, 0, 0, 3, 1, 3, 0, 0, 5, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  0, 1, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtps2bf8, 0x39, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 2, 0, 0, 1, 1, 3, 0, 0, 6, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  0, 0, 1, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtps2bf8s, 0x3b, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 2, 0, 0, 2, 1, 3, 0, 0, 4, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  1, 0, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtps2bf8s, 0x3b, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 2, 0, 0, 3, 1, 3, 0, 0, 5, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  0, 1, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtps2bf8s, 0x3b, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 2, 0, 0, 1, 1, 3, 0, 0, 6, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  0, 0, 1, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtps2hf8, 0x38, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 2, 0, 0, 2, 1, 3, 0, 0, 4, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  1, 0, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtps2hf8, 0x38, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 2, 0, 0, 3, 1, 3, 0, 0, 5, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  0, 1, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtps2hf8, 0x38, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 2, 0, 0, 1, 1, 3, 0, 0, 6, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  0, 0, 1, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtps2hf8s, 0x3a, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 2, 0, 0, 2, 1, 3, 0, 0, 4, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  1, 0, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtps2hf8s, 0x3a, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 2, 0, 0, 3, 1, 3, 0, 0, 5, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  0, 1, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtps2hf8s, 0x3a, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 2, 0, 0, 1, 1, 3, 0, 0, 6, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  0, 0, 1, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtrops2hf8, 0x38, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 1, 0, 0, 2, 1, 3, 0, 0, 4, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  1, 0, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtrops2hf8, 0x38, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 1, 0, 0, 3, 1, 3, 0, 0, 5, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  0, 1, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtrops2hf8, 0x38, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 3, 0, 0, 6, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  0, 0, 1, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtrops2hf8s, 0x3a, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 1, 0, 0, 2, 1, 3, 0, 0, 4, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  1, 0, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtrops2hf8s, 0x3a, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 1, 0, 0, 3, 1, 3, 0, 0, 5, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  0, 1, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtrops2hf8s, 0x3a, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 3, 0, 0, 6, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  0, 0, 1, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtbiasps2bf8, 0x39, 3, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 1, 1, 0, 0, 0, 2, 1, 3, 0, 0, 4, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  1, 0, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtbiasps2bf8, 0x39, 3, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 1, 1, 0, 0, 0, 3, 1, 3, 0, 0, 5, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  0, 1, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 1, 0, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtbiasps2bf8, 0x39, 3, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 1, 3, 0, 0, 6, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  0, 0, 1, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 1, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtbiasps2bf8s, 0x3b, 3, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 1, 1, 0, 0, 0, 2, 1, 3, 0, 0, 4, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  1, 0, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtbiasps2bf8s, 0x3b, 3, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 1, 1, 0, 0, 0, 3, 1, 3, 0, 0, 5, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  0, 1, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 1, 0, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtbiasps2bf8s, 0x3b, 3, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 1, 3, 0, 0, 6, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  0, 0, 1, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 1, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtbiasps2hf8, 0x38, 3, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 1, 1, 0, 0, 0, 2, 1, 3, 0, 0, 4, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  1, 0, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtbiasps2hf8, 0x38, 3, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 1, 1, 0, 0, 0, 3, 1, 3, 0, 0, 5, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  0, 1, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 1, 0, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtbiasps2hf8, 0x38, 3, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 1, 3, 0, 0, 6, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  0, 0, 1, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 1, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtbiasps2hf8s, 0x3a, 3, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 1, 1, 0, 0, 0, 2, 1, 3, 0, 0, 4, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  1, 0, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtbiasps2hf8s, 0x3a, 3, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 1, 1, 0, 0, 0, 3, 1, 3, 0, 0, 5, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  0, 1, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 1, 0, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtbiasps2hf8s, 0x3a, 3, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 1, 3, 0, 0, 6, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  0, 0, 1, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 1, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtbf82ps, 0x36, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 2, 0, 0, 0, 2, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  1, 0, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtbf82ps, 0x36, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 2, 0, 0, 0, 3, 1, 0, 0, 0, 3, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0,
+	  1, 0, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 1, 0, 0, 0, 0 } } } },
+  { MN_vcvtbf82ps, 0x36, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 2, 0, 0, 0, 1, 1, 0, 0, 0, 4, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 1, 0, 0, 0 } } } },
+  { MN_vcvthf82ps, 0x36, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  1, 0, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvthf82ps, 0x36, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 0, 0, 0, 3, 1, 0, 0, 0, 3, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0,
+	  1, 0, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 1, 0, 0, 0, 0 } } } },
+  { MN_vcvthf82ps, 0x36, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 4, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 1, 0, 0, 0 } } } },
+  { MN_vcvtbf82bf4s, 0x3d, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 2, 2, 0, 0, 2, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0,
+	  1, 0, 0, 0, 1, 0 } } } },
+  { MN_vcvtbf82bf4s, 0x3d, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 2, 2, 0, 0, 3, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 1, 0, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 1, 0 } } } },
+  { MN_vcvtbf82bf4s, 0x3d, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 2, 2, 0, 0, 1, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 1, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+	  0, 1, 0, 0, 1, 0 } } } },
+  { MN_vcvthf82bf4s, 0x3d, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 2, 0, 0, 2, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0,
+	  1, 0, 0, 0, 1, 0 } } } },
+  { MN_vcvthf82bf4s, 0x3d, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 2, 0, 0, 3, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 1, 0, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 1, 0 } } } },
+  { MN_vcvthf82bf4s, 0x3d, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 2, 0, 0, 1, 0, 0, 0, 0, 5, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 1, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+	  0, 1, 0, 0, 1, 0 } } } },
+  { MN_vcvtbf82bf6s, 0x3e, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtbf82bf6s, 0x3e, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 2, 2, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 1, 0, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 1, 0, 0, 0, 0 } } } },
+  { MN_vcvtbf82bf6s, 0x3e, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 2, 2, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 1, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 1, 0, 0, 0 } } } },
+  { MN_vcvthf82hf6s, 0x3c, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvthf82hf6s, 0x3c, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 2, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 1, 0, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 1, 0, 0, 0, 0 } } } },
+  { MN_vcvthf82hf6s, 0x3c, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 2, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 1, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 1, 0, 0, 0 } } } },
+  { MN_vcvtbf42hf8, 0x37, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 0, 0, 0, 2, 1, 0, 0, 0, 3, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0,
+	  1, 0, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } } } },
+  { MN_vcvtbf42hf8, 0x37, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 0, 0, 0, 3, 1, 0, 0, 0, 4, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 1, 0, 0, 0, 0 } } } },
+  { MN_vcvtbf42hf8, 0x37, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 5, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+	  0, 1, 0, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 1, 0, 0, 0 } } } },
+  { MN_vcvtbf62hf8, 0x37, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 2, 1, 0, 0, 5, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 1, 1, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 1, 1, 0, 0, 0 } } } },
+  { MN_vcvthf62hf8, 0x37, 2, SPACE_MAP5, None,
+    { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 1, 0, 0, 5, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 1, 1, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 1, 1, 0, 0, 0 } } } },
+  { MN_vpmovssdb, 0x41, 2, SPACE_0F38, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 2, 0, 0, 2, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 1, 0, 0, 0,
+	  1, 0, 0, 0, 1, 0 } } } },
+  { MN_vpmovssdb, 0x41, 2, SPACE_0F38, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 2, 0, 0, 3, 1, 0, 0, 0, 3, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 1, 0, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1, 0,
+	  1, 0, 0, 0, 1, 0 } } } },
+  { MN_vpmovssdb, 0x41, 2, SPACE_0F38, None,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 2, 0, 0, 1, 1, 0, 0, 0, 4, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 1, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+	  1, 0, 0, 0, 1, 0 } } } },
+  { MN_vunpackb, 0x3d, 3, SPACE_0F3A, None,
+    { 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
+      0, 0, 0, 0, 0, 1, 0, 0, 0, 5, 1, 0, 0, 0, 7, 0, 0, 0, 0, 0,
+      0, 0 },
+    { { 151, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
+    { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0,
+	  1, 1, 1, 0, 1, 0 } },
+      { { 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  1, 1, 1, 0, 0, 0 } } } },
   { MN_prefetchrst2, 0x18, 1, SPACE_0F, 4,
     { 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -48517,7 +49113,10 @@ static const i386_op_off_t i386_op_sets[] =
   4546, 4547, 4548, 4549, 4550, 4553, 4556, 4557,
   4558, 4559, 4560, 4561, 4562, 4563, 4564, 4565,
   4566, 4567, 4568, 4569, 4570, 4571, 4572, 4573,
-  4574, 4576, 4577, 4578, 4579, 4580
+  4576, 4579, 4582, 4585, 4588, 4591, 4594, 4597,
+  4600, 4603, 4606, 4609, 4612, 4615, 4618, 4621,
+  4624, 4625, 4626, 4629, 4630, 4631, 4633, 4634,
+  4635, 4636, 4637
 };
 
 /* i386 mnemonics table.  */
@@ -48668,9 +49267,17 @@ static const char i386_mnemonics[] =
   "\0""vcvt2ph2bf8"
   "\0""vcvtbiasph2bf8"
   "\0""vcvtph2bf8"
+  "\0""vcvtbiasps2bf8"
+  "\0""vcvtps2bf8"
+  "\0""vcvtbf42hf8"
+  "\0""vcvtbf62hf8"
+  "\0""vcvthf62hf8"
   "\0""vcvt2ph2hf8"
   "\0""vcvtbiasph2hf8"
   "\0""vcvtph2hf8"
+  "\0""vcvtrops2hf8"
+  "\0""vcvtbiasps2hf8"
+  "\0""vcvtps2hf8"
   "\0""vmovdqu8"
   "\0""vextractf32x8"
   "\0""vinsertf32x8"
@@ -48720,6 +49327,7 @@ static const char i386_mnemonics[] =
   "\0""vpaddb"
   "\0""kandb"
   "\0""vpexpandb"
+  "\0""vpmovssdb"
   "\0""vpmovusdb"
   "\0""vpmovsdb"
   "\0""udb"
@@ -48738,6 +49346,7 @@ static const char i386_mnemonics[] =
   "\0""invlpgb"
   "\0""vpavgb"
   "\0""jb"
+  "\0""vunpackb"
   "\0""pbndkb"
   "\0""vpmovmskb"
   "\0""vpshlb"
@@ -50038,12 +50647,21 @@ static const char i386_mnemonics[] =
   "\0""fdivr"
   "\0""fidivr"
   "\0""rex.wr"
+  "\0""vcvtbf82bf4s"
+  "\0""vcvthf82bf4s"
+  "\0""vcvtbf82bf6s"
+  "\0""vcvthf82hf6s"
   "\0""vcvt2ph2bf8s"
   "\0""vcvtbiasph2bf8s"
   "\0""vcvtph2bf8s"
+  "\0""vcvtbiasps2bf8s"
+  "\0""vcvtps2bf8s"
   "\0""vcvt2ph2hf8s"
   "\0""vcvtbiasph2hf8s"
   "\0""vcvtph2hf8s"
+  "\0""vcvtrops2hf8s"
+  "\0""vcvtbiasps2hf8s"
+  "\0""vcvtps2hf8s"
   "\0""aas"
   "\0""scas"
   "\0""das"
@@ -50116,6 +50734,8 @@ static const char i386_mnemonics[] =
   "\0""vcvtneebf162ps"
   "\0""vbcstnebf162ps"
   "\0""vcvtneobf162ps"
+  "\0""vcvtbf82ps"
+  "\0""vcvthf82ps"
   "\0""vcvtpd2ps"
   "\0""tcvtrowd2ps"
   "\0""vcvtneeph2ps"
-- 
2.53.0


From jiawei@iscas.ac.cn  Sat Jun 27 10:45:53 2026
From: jiawei@iscas.ac.cn (Jiawei)
Date: Sat, 27 Jun 2026 18:45:53 +0800
Subject: [RFC PATCH 3/5] ld: Add RISC-V --relax-zcmt option
In-Reply-To: <20260627104555.331493-1-jiawei@iscas.ac.cn>
References: <20260627104555.331493-1-jiawei@iscas.ac.cn>
Message-ID: <20260627104555.331493-4-jiawei@iscas.ac.cn>

Expose Zcmt table-jump relaxation as an explicit opt-in RISC-V linker option,
and document the non-position-independent executable links and JVT CSR
requirement, and keep the optimization disabled by default.

ld/ChangeLog:

	* NEWS: Add --relax-zcmt entry.
	* emultempl/riscvelf.em: Handle --relax-zcmt option.
	* gen-doc.texi: Enable RISC-V docs.
	* ld.texi: Document --relax-zcmt.
	* ldlex.h (enum option_values): Add RELAX_ZCMT options.
---
 ld/NEWS                  |  3 +++
 ld/emultempl/riscvelf.em | 17 +++++++++++++++--
 ld/gen-doc.texi          |  2 +-
 ld/ld.texi               | 35 +++++++++++++++++++++++++++++++++++
 ld/ldlex.h               |  2 ++
 5 files changed, 56 insertions(+), 3 deletions(-)

diff --git a/ld/NEWS b/ld/NEWS
index 2de87ae227c..774eaf2c457 100644
--- a/ld/NEWS
+++ b/ld/NEWS
@@ -2,6 +2,9 @@
 
 Changes in 2.47:
 
+* Add the RISC-V --relax-zcmt option for opt-in Zcmt table-jump relaxation
+  in non-position-independent executable links.
+
 * Add a linker optimization level of zero.  Using "-O 0" on the linker command
   line will stop it from combining the contents of mergeable sections.  This
   can significantly speed up the link process at the cost of producing larger
diff --git a/ld/emultempl/riscvelf.em b/ld/emultempl/riscvelf.em
index 814109355d9..67c9c23f289 100644
--- a/ld/emultempl/riscvelf.em
+++ b/ld/emultempl/riscvelf.em
@@ -26,7 +26,8 @@ fragment <<EOF
 #include "elfxx-riscv.h"
 
 static struct riscv_elf_params params = { .relax_gp = 1,
-					  .check_uleb128 = 0};
+					  .check_uleb128 = 0,
+					  .relax_zcmt = 0};
 EOF
 
 # Define some shell vars to insert bits of code into the standard elf
@@ -36,6 +37,8 @@ PARSE_AND_LIST_LONGOPTS=${PARSE_AND_LIST_LONGOPTS}'
     { "no-relax-gp", no_argument, NULL, OPTION_NO_RELAX_GP },
     { "check-uleb128", no_argument, NULL, OPTION_CHECK_ULEB128 },
     { "no-check-uleb128", no_argument, NULL, OPTION_NO_CHECK_ULEB128 },
+    { "relax-zcmt", no_argument, NULL, OPTION_RELAX_ZCMT },
+    { "no-relax-zcmt", no_argument, NULL, OPTION_NO_RELAX_ZCMT },
 '
 
 PARSE_AND_LIST_OPTIONS=${PARSE_AND_LIST_OPTIONS}'
@@ -43,6 +46,8 @@ PARSE_AND_LIST_OPTIONS=${PARSE_AND_LIST_OPTIONS}'
   fprintf (file, _("  --no-relax-gp               Don'\''t perform GP relaxation\n"));
   fprintf (file, _("  --check-uleb128             Check if SUB_ULEB128 has non-zero addend\n"));
   fprintf (file, _("  --no-check-uleb128          Don'\''t check if SUB_ULEB128 has non-zero addend\n"));
+  fprintf (file, _("  --relax-zcmt                Enable RISC-V Zcmt table-jump relaxation\n"));
+  fprintf (file, _("  --no-relax-zcmt             Disable RISC-V Zcmt table-jump relaxation (default)\n"));
 '
 
 PARSE_AND_LIST_ARGS_CASES=${PARSE_AND_LIST_ARGS_CASES}'
@@ -61,6 +66,14 @@ PARSE_AND_LIST_ARGS_CASES=${PARSE_AND_LIST_ARGS_CASES}'
     case OPTION_NO_CHECK_ULEB128:
       params.check_uleb128 = 0;
       break;
+
+    case OPTION_RELAX_ZCMT:
+      params.relax_zcmt = 1;
+      break;
+
+    case OPTION_NO_RELAX_ZCMT:
+      params.relax_zcmt = 0;
+      break;
 '
 
 fragment <<EOF
@@ -81,7 +94,7 @@ riscv_elf_before_allocation (void)
 	ENABLE_RELAXATION;
     }
 
-  link_info.relax_pass = 2;
+  link_info.relax_pass = RELAX_PASS_END;
 }
 
 static void
diff --git a/ld/gen-doc.texi b/ld/gen-doc.texi
index 561869f485a..6f1902aa85c 100644
--- a/ld/gen-doc.texi
+++ b/ld/gen-doc.texi
@@ -21,6 +21,7 @@
 @set PDP11
 @set POWERPC
 @set POWERPC64
+@set RISCV
 @set Renesas
 @set S/390
 @set SPU
@@ -32,4 +33,3 @@
 @clear SingleFormat
 @set UsesEnvVars
 @c ------------------------------ end CONFIGURATION VARS
-
diff --git a/ld/ld.texi b/ld/ld.texi
index 9d6618a4307..ae6217bc70e 100644
--- a/ld/ld.texi
+++ b/ld/ld.texi
@@ -33,6 +33,7 @@
 @set PDP11
 @set POWERPC
 @set POWERPC64
+@set RISCV
 @set Renesas
 @set S/390
 @set SPU
@@ -4123,6 +4124,40 @@ in the PLT entries for MIPS R6.
 @c man end
 @end ifset
 
+@ifset RISCV
+@subsection Options specific to RISC-V targets
+
+@c man begin OPTIONS
+
+@table @gcctabopt
+
+@kindex --relax-zcmt
+@item --relax-zcmt
+Enable RISC-V Zcmt table-jump relaxation when the input architecture
+attributes permit the Zcmt extension.  The extension requires Zca and
+Zicsr, and is not compatible with Zcd.  This relaxation is disabled by
+default and is initially supported only for non-position-independent
+executable links.  It is conservatively disabled for PIC, PIE and shared
+links.
+
+When a non-empty @code{.riscv.jvt} section is emitted, the linker defines
+a local @code{__jvt_base$} symbol at the table base.  Programs using this
+relaxation must initialize the @code{jvt} CSR to @code{__jvt_base$}
+before executing @code{cm.jt} or @code{cm.jalt}.  The symbol is not
+defined when no profitable table is emitted; generic startup code that
+unconditionally references @code{__jvt_base$} is therefore unsupported
+unless it arranges an optional reference or is linked only when a JVT is
+emitted.
+
+@kindex --no-relax-zcmt
+@item --no-relax-zcmt
+Disable RISC-V Zcmt table-jump relaxation.  This is the default.
+
+@end table
+
+@c man end
+@end ifset
+
 
 @ifset PDP11
 @subsection Options specific to PDP11 targets
diff --git a/ld/ldlex.h b/ld/ldlex.h
index 958ec3fbf81..03057e27852 100644
--- a/ld/ldlex.h
+++ b/ld/ldlex.h
@@ -431,6 +431,8 @@ enum option_values
   OPTION_NO_RELAX_GP,
   OPTION_CHECK_ULEB128,
   OPTION_NO_CHECK_ULEB128,
+  OPTION_RELAX_ZCMT,
+  OPTION_NO_RELAX_ZCMT,
   /* Used by emultempl/rxelf.em.  */
   OPTION_NO_FLAG_MISMATCH_WARNINGS,
   OPTION_IGNORE_LMA,
-- 
2.43.0


From jiawei@iscas.ac.cn  Sat Jun 27 10:45:51 2026
From: jiawei@iscas.ac.cn (Jiawei)
Date: Sat, 27 Jun 2026 18:45:51 +0800
Subject: [RFC PATCH 1/5] RISC-V: Add Zcmt table-jump relocation definitions
In-Reply-To: <20260627104555.331493-1-jiawei@iscas.ac.cn>
References: <20260627104555.331493-1-jiawei@iscas.ac.cn>
Message-ID: <20260627104555.331493-2-jiawei@iscas.ac.cn>

Add a ZCMT table jump relaxation pass in the linker, the ELF relocation
number, opcode constants, and RISC-V BFD parameter
state needed by linker table-jump relaxation.

bfd/ChangeLog:

	* elfxx-riscv.c: Add TABLE_JUMP howto.
	* elfxx-riscv.h (struct riscv_elf_params): Add relax_zcmt field.
	(enum riscv_relax_pass): New enum.
	(enum jvt_profiling_trip): Ditto.

include/ChangeLog:

	* elf/riscv.h (R_RISCV_TABLE_JUMP): New reloc number.
	(RISCV_TABLE_JUMP_BASE_SYMBOL): New symbol name.
	(TABLE_JUMP_SEC_NAME): New section name.
	* opcode/riscv.h (ZCMT_TOTAL_ENTRIES): New Zcmt constants.
	(ZCMT_JT_BEGIN): Ditto.
	(ZCMT_JT_END): Ditto.
	(ZCMT_JT_NUM_ENTRIES): Ditto.
	(ZCMT_JALT_BEGIN): Ditto.
	(ZCMT_JALT_END): Ditto.
	(ZCMT_JALT_NUM_ENTRIES): Ditto.
---
 bfd/elfxx-riscv.c      |  4 ++++
 bfd/elfxx-riscv.h      | 21 +++++++++++++++++++++
 include/elf/riscv.h    |  5 +++++
 include/opcode/riscv.h |  9 +++++++++
 4 files changed, 39 insertions(+)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 961c44a9206..615f644d336 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -961,6 +961,10 @@ static const reloc_howto_type howto_table_internal[] =
 	 0,				/* src_mask */
 	 ENCODE_STYPE_IMM (-1U),	/* dst_mask */
 	 false),			/* pcrel_offset */
+
+  /* R_RISCV_TABLE_JUMP is linker-internal.  It is consumed before final
+     relocations are emitted and must never become psABI-visible.  */
+  EMPTY_HOWTO (0),
 };
 
 /* A mapping from BFD reloc types to RISC-V ELF reloc types.  */
diff --git a/bfd/elfxx-riscv.h b/bfd/elfxx-riscv.h
index e57e90462f8..6adf1d6d0ca 100644
--- a/bfd/elfxx-riscv.h
+++ b/bfd/elfxx-riscv.h
@@ -44,6 +44,8 @@ struct riscv_elf_params
   bool relax_gp;
   /* Whether to check if SUB_ULEB128 relocation has non-zero addend.  */
   bool check_uleb128;
+  /* Whether to relax code sequences for Zcmt.  */
+  bool relax_zcmt;
 };
 
 extern void riscv_elf32_set_options (struct bfd_link_info *,
@@ -101,6 +103,25 @@ typedef struct
   bool check_unknown_prefixed_ext;
 } riscv_parse_subset_t;
 
+/* List the relaxation passes.  */
+enum riscv_relax_pass
+{
+  RELAX_PASS_SHORTEN_LUI_CALL_TRREL_PCREL,
+  RELAX_PASS_CAN_BE_DISABLED = RELAX_PASS_SHORTEN_LUI_CALL_TRREL_PCREL,
+  RELAX_PASS_TABLE_JUMP_PROFILING,
+  RELAX_PASS_ALIGNMENT,
+  RELAX_PASS_END,
+};
+
+/* Trips for jvt profiling relaxation pass.  */
+enum jvt_profiling_trip
+{
+  JVT_PROFILING_RECORD_SYM,
+  JVT_PROFILING_RANK,
+  JVT_PROFILING_DETERMINE,
+  JVT_PROFILING_TRIM,
+};
+
 extern bool
 riscv_parse_subset (riscv_parse_subset_t *,
 		    const char *);
diff --git a/include/elf/riscv.h b/include/elf/riscv.h
index f6ca3d4acd8..02a0184b7ee 100644
--- a/include/elf/riscv.h
+++ b/include/elf/riscv.h
@@ -105,6 +105,7 @@ END_RELOC_NUMBERS (R_RISCV_max)
 #define R_RISCV_GPREL_S           (R_RISCV_max + 4)
 #define R_RISCV_TPREL_I           (R_RISCV_max + 5)
 #define R_RISCV_TPREL_S           (R_RISCV_max + 6)
+#define R_RISCV_TABLE_JUMP        (R_RISCV_max + 7)
 
 /* Processor specific flags for the ELF header e_flags field.  */
 
@@ -132,6 +133,10 @@ END_RELOC_NUMBERS (R_RISCV_max)
 /* The name of the global pointer symbol.  */
 #define RISCV_GP_SYMBOL "__global_pointer$"
 
+#define RISCV_TABLE_JUMP_BASE_SYMBOL "__jvt_base$"
+
+#define TABLE_JUMP_SEC_NAME ".riscv.jvt"
+
 /* Processor specific dynamic array tags.  */
 #define DT_RISCV_VARIANT_CC (DT_LOPROC + 1)
 
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index b4587976ea2..5e1157e3e50 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -698,6 +698,15 @@ struct riscv_opcode
    disassembler, and requires special treatment by the assembler.  */
 #define INSN_MACRO		0xffffffff
 
+/* Define Zcmt jump table constants.  */
+#define ZCMT_TOTAL_ENTRIES 256
+#define ZCMT_JT_BEGIN 0
+#define ZCMT_JT_END 31
+#define ZCMT_JT_NUM_ENTRIES (ZCMT_JT_END - ZCMT_JT_BEGIN + 1)
+#define ZCMT_JALT_BEGIN (ZCMT_JT_END + 1)
+#define ZCMT_JALT_END (ZCMT_TOTAL_ENTRIES - 1)
+#define ZCMT_JALT_NUM_ENTRIES (ZCMT_JALT_END - ZCMT_JALT_BEGIN + 1)
+
 /* This is a list of macro expanded instructions.  */
 enum
 {
-- 
2.43.0


From jiawei@iscas.ac.cn  Sat Jun 27 10:45:54 2026
From: jiawei@iscas.ac.cn (Jiawei)
Date: Sat, 27 Jun 2026 18:45:54 +0800
Subject: [RFC PATCH 4/5] RISC-V: Decode Zcmt JVT entries in objdump
In-Reply-To: <20260627104555.331493-1-jiawei@iscas.ac.cn>
References: <20260627104555.331493-1-jiawei@iscas.ac.cn>
Message-ID: <20260627104555.331493-5-jiawei@iscas.ac.cn>

This patch adds the RISC-V disassembler to print JVT table entries
and annotate cm.jt and cm.jalt targets when the table is present.

opcodes/ChangeLog:

	* riscv-dis.c (struct riscv_private_data): Add JVT fields.
	(riscv_set_xlen_from_elf): New function.
	(maybe_print_jvt_address): Ditto.
	(print_insn_args): Annotate JVT target.
	(riscv_disassemble_insn): Handle Zcmt decode.
	(riscv_disassemble_jvt): New function.
	(riscv_init_disasm_info): Init JVT data.
	(print_insn_riscv): Handle JVT section.
	(disassemble_free_riscv): Free JVT content.
---
 opcodes/riscv-dis.c | 164 ++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 149 insertions(+), 15 deletions(-)

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index ca0d9bfd121..5d5ff0f8b3c 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -47,6 +47,10 @@ struct riscv_private_data
   bfd_vma hi_addr[OP_MASK_RD + 1];
   bool to_print_addr;
   bool has_gp;
+  bool has_jvt_base;
+  asection *jvt_section;
+  bfd_byte *jvt_content;
+  bfd_size_type jvt_size;
   /* Current XLEN for the disassembler.  */
   unsigned xlen;
   /* Default ISA specification version.  */
@@ -220,6 +224,48 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset,
     pd->print_addr = (bfd_vma)(uint32_t)pd->print_addr;
 }
 
+/* Set pd->xlen from ELF class if not already known.  */
+
+static void
+riscv_set_xlen_from_elf (struct riscv_private_data *pd,
+			 struct disassemble_info *info)
+{
+  if (pd->xlen != 0)
+    return;
+
+  if (info->mach == bfd_mach_riscv64)
+    pd->xlen = 64;
+  else if (info->mach == bfd_mach_riscv32)
+    pd->xlen = 32;
+  else if (info->section != NULL)
+    {
+      Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner);
+      pd->xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32;
+    }
+}
+
+/* Try to print target address of cm.jalt and cm.jt.  */
+
+static void
+maybe_print_jvt_address (struct riscv_private_data *pd, int index)
+{
+  if (!pd->has_jvt_base || pd->jvt_section == NULL || pd->jvt_content == NULL
+      || pd->xlen == 0)
+    return;
+
+  bfd_size_type entry_size = pd->xlen / 8;
+  bfd_size_type offset = entry_size * (bfd_size_type) index;
+  if (index < 0 || index > (ZCMT_TOTAL_ENTRIES - 1)
+      || offset + entry_size > pd->jvt_size)
+    return;
+
+  bfd_byte *packet = pd->jvt_content + offset;
+
+  pd->to_print_addr = true;
+  pd->print_addr = bfd_get_bits (packet, pd->xlen,
+				 bfd_big_endian (pd->jvt_section->owner));
+}
+
 /* Get Zcmp reg_list field.  */
 
 static void
@@ -747,6 +793,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 		case 'I':
 		  print (info->stream, dis_style_address_offset,
 			 "%" PRIu64, EXTRACT_ZCMT_INDEX (l));
+		  maybe_print_jvt_address (pd, EXTRACT_ZCMT_INDEX (l));
 		  break;
 		default:
 		  goto undefined_modifier;
@@ -1052,17 +1099,7 @@ riscv_disassemble_insn (bfd_vma memaddr,
   if (op != NULL)
     {
       /* If XLEN is not known, get its value from the ELF class.  */
-      if (pd->xlen != 0)
-	;
-      else if (info->mach == bfd_mach_riscv64)
-	pd->xlen = 64;
-      else if (info->mach == bfd_mach_riscv32)
-	pd->xlen = 32;
-      else if (info->section != NULL)
-	{
-	  Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner);
-	  pd->xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32;
-	}
+      riscv_set_xlen_from_elf (pd, info);
 
       /* If arch has the Zfinx extension, replace FPR with GPR.  */
       if (riscv_subset_supports (&pd->riscv_rps_dis, "zfinx"))
@@ -1086,10 +1123,12 @@ riscv_disassemble_insn (bfd_vma memaddr,
 	  if ((op->xlen_requirement != 0)
 	      && (op->xlen_requirement != pd->xlen))
 	    continue;
-	  /* Is this instruction supported by the current architecture?  */
+	  /* Is this instruction supported by the current architecture?
+	     Always disassemble ZCMT instructions if __jvt_base$ is present.  */
 	  if (!pd->all_ext
 	      && !riscv_multi_subset_supports (&pd->riscv_rps_dis,
-					       op->insn_class))
+					       op->insn_class)
+	      && !(pd->has_jvt_base && op->insn_class == INSN_CLASS_ZCMT))
 	    continue;
 
 	  /* It's a match.  */
@@ -1481,6 +1520,51 @@ riscv_disassemble_data (bfd_vma memaddr ATTRIBUTE_UNUSED,
   return info->bytes_per_chunk;
 }
 
+/* DATA is the function address in jump table entry.
+   Lookup the address in symbols and print the function name.  */
+static int
+riscv_disassemble_jvt (bfd_vma memaddr, insn_t data,
+		       const bfd_byte *packet,
+		       disassemble_info *info)
+{
+  struct riscv_private_data *pd = info->private_data;
+  if (pd == NULL || pd->xlen == 0 || info->section == NULL)
+    return -1;
+
+  bfd_size_type entry_size = pd->xlen / 8;
+  bfd_vma offset = memaddr - info->section->vma;
+  bfd_size_type entry_offset = (offset / entry_size) * entry_size;
+  bfd_size_type entry_delta = offset - entry_offset;
+  int idx = entry_offset / entry_size;
+  if (idx < 0 || idx > (ZCMT_TOTAL_ENTRIES - 1))
+    opcodes_error_handler (_ ("invalid jvt index: %i"), idx);
+
+  const char *inst_str;
+  if (idx <= ZCMT_JT_END)
+    inst_str = "jvt.jt";
+  else
+    inst_str = "jvt.jalt";
+
+  if (pd->jvt_content != NULL && entry_offset + entry_size <= pd->jvt_size)
+    packet = pd->jvt_content + entry_offset;
+  data = bfd_get_bits (packet, pd->xlen,
+		       bfd_big_endian (info->section->owner));
+
+  const char *funcname = "<unknown>";
+  for (int i = 0; i < info->symtab_size; i++)
+    {
+      bfd_vma addr = bfd_asymbol_value (info->symtab[i]);
+      if (addr == (bfd_vma) data)
+	{
+	  funcname = info->symtab[i]->name;
+	  break;
+	}
+    }
+  (*info->fprintf_styled_func) (info->stream, dis_style_text, "%s[%i]:\t%s",
+				inst_str, idx, funcname);
+  return entry_size - entry_delta;
+}
+
 static bool
 riscv_init_disasm_info (struct disassemble_info *info)
 {
@@ -1493,7 +1577,34 @@ riscv_init_disasm_info (struct disassemble_info *info)
     pd->hi_addr[i] = -1;
   pd->to_print_addr = false;
 
+  pd->has_jvt_base = false;
   pd->has_gp = false;
+  pd->jvt_section = NULL;
+  pd->jvt_content = NULL;
+  pd->jvt_size = 0;
+
+  if (info->section != NULL)
+    {
+      bfd *abfd = info->section->owner;
+      if (abfd && bfd_get_flavour (abfd) == bfd_target_elf_flavour)
+	{
+	  asection *s = bfd_get_section_by_name (abfd, TABLE_JUMP_SEC_NAME);
+	  if (s != NULL && bfd_section_size (s) > 0)
+	    {
+	      bfd_size_type size = bfd_section_size (s);
+	      bfd_byte *buf = (bfd_byte *) xmalloc (size);
+	      if (bfd_get_section_contents (abfd, s, buf, 0, size))
+		{
+		  pd->jvt_section = s;
+		  pd->jvt_content = buf;
+		  pd->jvt_size = size;
+		}
+	      else
+		free (buf);
+	    }
+	}
+    }
+
   for (i = 0; i < info->symtab_size; i++)
     {
       asymbol *sym = info->symtab[i];
@@ -1502,9 +1613,18 @@ riscv_init_disasm_info (struct disassemble_info *info)
 	  pd->gp = bfd_asymbol_value (sym);
 	  pd->has_gp = true;
 	}
+
+      if (strcmp (bfd_asymbol_name (sym), RISCV_TABLE_JUMP_BASE_SYMBOL) == 0)
+	{
+	  bfd_vma jvt_base = bfd_asymbol_value (sym);
+	  if (pd->jvt_section != NULL
+	      && jvt_base == bfd_section_vma (pd->jvt_section))
+	    pd->has_jvt_base = true;
+	}
     }
 
   pd->xlen = 0;
+  riscv_set_xlen_from_elf (pd, info);
   pd->default_isa_spec = ISA_SPEC_CLASS_DRAFT - 1;
   pd->default_priv_spec = PRIV_SPEC_CLASS_NONE;
 
@@ -1598,8 +1718,21 @@ print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info)
   ((struct riscv_private_data *) info->private_data)->last_map_state = mstate;
 
   /* Set the size to dump.  */
-  if (mstate == MAP_DATA
-      && (info->flags & DISASSEMBLE_DATA) == 0)
+  if (info->section != NULL
+      && strcmp (info->section->name, TABLE_JUMP_SEC_NAME) == 0)
+    {
+      struct riscv_private_data *pd = info->private_data;
+      riscv_set_xlen_from_elf (pd, info);
+
+      dump_size = pd->xlen / 8;
+      info->bytes_per_chunk = dump_size;
+      info->bytes_per_line = dump_size;
+      info->endian_code = bfd_big_endian (info->section->owner)
+			   ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
+      info->display_endian = info->endian_code;
+      riscv_disassembler = riscv_disassemble_jvt;
+    }
+  else if (mstate == MAP_DATA && (info->flags & DISASSEMBLE_DATA) == 0)
     {
       dump_size = riscv_data_length (memaddr, info);
       info->bytes_per_chunk = dump_size;
@@ -1829,5 +1962,6 @@ void disassemble_free_riscv (struct disassemble_info *info ATTRIBUTE_UNUSED)
     {
       riscv_release_subset_list (pd->riscv_rps_dis.subset_list);
       free (pd->riscv_rps_dis.subset_list);
+      free (pd->jvt_content);
     }
 }
-- 
2.43.0


From jiawei@iscas.ac.cn  Sat Jun 27 10:45:50 2026
From: jiawei@iscas.ac.cn (Jiawei)
Date: Sat, 27 Jun 2026 18:45:50 +0800
Subject: [RFC PATCH 0/5] RISC-V: Add Zcmt table-jump relaxation support
Message-ID: <20260627104555.331493-1-jiawei@iscas.ac.cn>

This RFC series adds RISC-V Zcmt table-jump relaxation support to GNU ld.
The optimization is default-off and must be requested with `--relax-zcmt`.

The implementation follows a post-relaxation profitability model.  It records
the residual `R_RISCV_CALL`, `R_RISCV_CALL_PLT`, and `R_RISCV_JAL`
opportunities that still have paired `R_RISCV_RELAX` relocations after ordinary
RISC-V relaxation.  It then ranks JT and JALT candidates separately, uses a
deterministic prefix selection, accounts for the JVT payload cost, and emits no
`.riscv.jvt` section if no positive-benefit table is selected.

Runtime policy:

- when a non-empty `.riscv.jvt` is emitted, the linker defines local
  `__jvt_base$` at the table base;
- programs that execute `cm.jt`/`cm.jalt` remain responsible for initializing
  CSR `jvt` to `__jvt_base$` first;
- when no profitable JVT is emitted, `__jvt_base$` is not defined;
- generic startup code that unconditionally references `__jvt_base$` is not
  supported unless it arranges an optional reference or is linked only when a
  JVT is emitted.

ISA/profile policy:

- Zcmt relaxation is enabled only when output attributes explicitly support
  `zcmt`, `zca`, and `zicsr`;
- output attributes containing `zcd` disable Zcmt relaxation because the
  encodings conflict.

Scope:

- non-position-independent executable links only;
- PIC, PIE, and shared-object links are conservatively not relaxed;
- no Linux ABI claim for automatic `jvt` initialization;

Open questions:

- Is the `__jvt_base$` emission policy acceptable for v1?
- Is `R_RISCV_TABLE_JUMP` acceptable as an internal linker relocation?
- Are `.riscv.jvt` section naming, flags, and 64-byte alignment suitable?
- Should objdump present JVT entries as `jvt.jt[]`/`jvt.jalt[]`, or use a more
  conservative `.word`/`.dword` presentation?
  (Patch 4 is separable; if maintainers prefer, the linker relaxation support
  can be reviewed independently from the objdump JVT annotation.)
- Is default-off `--relax-zcmt` the desired upstream user interface?

Contributors:

This RFC builds on earlier Zcmt table-jump relaxation work carried out
with contributions and discussions from Embecosm, SiFive and ISCAS.

Thanks to Jeremy Bennet, Kito Cheng, Mary Bennett, Nandni Jamnadas,
Simon Cook, Charlie Keaney, Hau Hsu, Jerry Zhang Jian, Sinan Lin,
Shihua Liao and Yulong Shi for the earlier work and feedback that
helped shape this series.

Since this upstream version has been substantially reworked, the commit
authorship is limited to the current patch submission, while the earlier
collaborative work is acknowledged here rather than carrying over
historical authorship trailers.

  RISC-V: Add Zcmt table-jump relocation definitions
  RISC-V: Add Zcmt table-jump relaxation
  ld: Add RISC-V --relax-zcmt option
  RISC-V: Decode Zcmt JVT entries in objdump
  RISC-V: Add Zcmt table-jump linker tests

 bfd/elfnn-riscv.c                             | 1134 ++++++++++++++++-
 bfd/elfxx-riscv.c                             |    4 +
 bfd/elfxx-riscv.h                             |   21 +
 include/elf/riscv.h                           |    5 +
 include/opcode/riscv.h                        |    9 +
 ld/NEWS                                       |    3 +
 ld/emultempl/riscvelf.em                      |   17 +-
 ld/gen-doc.texi                               |    2 +-
 ld/ld.texi                                    |   35 +
 ld/ldlex.h                                    |    2 +
 ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp    |   50 +
 ld/testsuite/ld-riscv-elf/table-jump-addend.d |   18 +
 ld/testsuite/ld-riscv-elf/table-jump-addend.s |   21 +
 .../ld-riscv-elf/table-jump-base-collision.d  |    4 +
 .../ld-riscv-elf/table-jump-base-collision.s  |   18 +
 .../table-jump-base-local-collision.d         |    4 +
 .../table-jump-base-local-collision.s         |   17 +
 .../ld-riscv-elf/table-jump-be32-bytes.d      |   10 +
 .../ld-riscv-elf/table-jump-be32-text.d       |   13 +
 .../ld-riscv-elf/table-jump-be64-bytes.d      |   10 +
 .../ld-riscv-elf/table-jump-be64-text.d       |   13 +
 .../ld-riscv-elf/table-jump-benefit.d         |   17 +
 .../ld-riscv-elf/table-jump-benefit.s         |   51 +
 .../table-jump-default-jvt-relocs.d           |    9 +
 .../table-jump-default-jvt-symbol.d           |   10 +
 .../ld-riscv-elf/table-jump-default-jvt.d     |   12 +
 .../ld-riscv-elf/table-jump-default-no-jvt.d  |   15 +
 .../ld-riscv-elf/table-jump-dump-unknown.d    |   25 +
 .../ld-riscv-elf/table-jump-emit-relocs.d     |    9 +
 .../ld-riscv-elf/table-jump-equal-benefit.d   |   18 +
 .../ld-riscv-elf/table-jump-equal-benefit.s   |   19 +
 .../table-jump-gc-comdat-symbol.d             |    9 +
 .../ld-riscv-elf/table-jump-gc-comdat.d       |   11 +
 .../ld-riscv-elf/table-jump-gc-comdat.s       |   18 +
 .../ld-riscv-elf/table-jump-gc-dead-symbol.d  |    9 +
 .../ld-riscv-elf/table-jump-gc-dead.d         |   11 +
 .../ld-riscv-elf/table-jump-gc-dead.s         |   18 +
 ld/testsuite/ld-riscv-elf/table-jump-jalt.d   |   18 +
 ld/testsuite/ld-riscv-elf/table-jump-jt.d     |   23 +
 .../table-jump-multiple-local-sym-2.s         |   12 +
 .../table-jump-multiple-local-sym.d           |   16 +
 .../table-jump-multiple-local-sym.s           |   18 +
 .../table-jump-no-benefit-jvt-ref.d           |    4 +
 .../table-jump-no-benefit-jvt-ref.s           |   16 +
 .../table-jump-no-benefit-section.d           |    9 +
 .../table-jump-no-benefit-symbol.d            |    9 +
 .../ld-riscv-elf/table-jump-no-benefit.s      |   12 +
 .../ld-riscv-elf/table-jump-no-relax-zcmt.d   |   17 +
 .../ld-riscv-elf/table-jump-no-relo-1.s       |    7 +
 .../ld-riscv-elf/table-jump-no-relo-2.s       |   12 +
 .../ld-riscv-elf/table-jump-no-relo.d         |   16 +
 .../ld-riscv-elf/table-jump-no-zcmt.d         |   16 +
 .../ld-riscv-elf/table-jump-no-zcmt.s         |   16 +
 .../ld-riscv-elf/table-jump-norelax.d         |   15 +
 .../ld-riscv-elf/table-jump-norelax.s         |   17 +
 .../ld-riscv-elf/table-jump-overflow.d        |   11 +
 .../ld-riscv-elf/table-jump-overflow.s        |   49 +
 .../ld-riscv-elf/table-jump-pie-relocs.d      |    9 +
 .../ld-riscv-elf/table-jump-pie-text.d        |    9 +
 ld/testsuite/ld-riscv-elf/table-jump-pie.d    |    9 +
 ld/testsuite/ld-riscv-elf/table-jump-pie.s    |   13 +
 .../ld-riscv-elf/table-jump-relax-zcmt.d      |   23 +
 ld/testsuite/ld-riscv-elf/table-jump-rv32.d   |   15 +
 ld/testsuite/ld-riscv-elf/table-jump-rv32.s   |   25 +
 .../ld-riscv-elf/table-jump-shared-relocs.d   |    9 +
 .../ld-riscv-elf/table-jump-shared-symbol.d   |    9 +
 .../ld-riscv-elf/table-jump-shared-text.d     |    9 +
 ld/testsuite/ld-riscv-elf/table-jump-shared.d |   12 +
 ld/testsuite/ld-riscv-elf/table-jump-shared.s |   15 +
 .../ld-riscv-elf/table-jump-strip-symbol.d    |    9 +
 .../ld-riscv-elf/table-jump-symbol-policy.d   |    8 +
 .../ld-riscv-elf/table-jump-vma-lma.d         |   16 +
 .../ld-riscv-elf/table-jump-vma-lma.ld        |   10 +
 .../ld-riscv-elf/table-jump-vma-zero.d        |   15 +
 .../ld-riscv-elf/table-jump-vma-zero.ld       |   13 +
 .../ld-riscv-elf/table-jump-vma-zero.s        |   14 +
 .../ld-riscv-elf/table-jump-zcd-conflict.d    |    9 +
 .../ld-riscv-elf/table-jump-zcmt-no-zca.d     |    9 +
 .../ld-riscv-elf/table-jump-zcmt-no-zca.s     |   24 +
 .../ld-riscv-elf/table-jump-zcmt-no-zicsr.d   |    9 +
 .../ld-riscv-elf/table-jump-zcmt-no-zicsr.s   |   24 +
 ld/testsuite/ld-riscv-elf/table-jump.ld       |   16 +
 ld/testsuite/ld-riscv-elf/table-jump.s        |   46 +
 opcodes/riscv-dis.c                           |  164 ++-
 84 files changed, 2478 insertions(+), 54 deletions(-)
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-addend.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-addend.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-base-collision.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-base-collision.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-base-local-collision.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-base-local-collision.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-be32-bytes.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-be32-text.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-be64-bytes.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-be64-text.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-benefit.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-benefit.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-default-jvt-relocs.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-default-jvt-symbol.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-default-jvt.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-default-no-jvt.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-dump-unknown.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-emit-relocs.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-equal-benefit.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-equal-benefit.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-gc-comdat-symbol.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-gc-comdat.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-gc-comdat.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-gc-dead-symbol.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-gc-dead.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-gc-dead.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-jalt.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-jt.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-multiple-local-sym-2.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-multiple-local-sym.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-multiple-local-sym.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-no-benefit-jvt-ref.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-no-benefit-jvt-ref.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-no-benefit-section.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-no-benefit-symbol.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-no-benefit.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-no-relax-zcmt.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-no-relo-1.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-no-relo-2.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-no-relo.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-no-zcmt.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-no-zcmt.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-norelax.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-norelax.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-overflow.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-overflow.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-pie-relocs.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-pie-text.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-pie.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-pie.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-relax-zcmt.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-rv32.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-rv32.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-shared-relocs.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-shared-symbol.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-shared-text.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-shared.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-shared.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-strip-symbol.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-symbol-policy.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-vma-lma.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-vma-lma.ld
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-vma-zero.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-vma-zero.ld
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-vma-zero.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-zcd-conflict.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-zcmt-no-zca.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-zcmt-no-zca.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-zcmt-no-zicsr.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-zcmt-no-zicsr.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump.ld
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump.s

-- 
2.43.0


From jiawei@iscas.ac.cn  Sat Jun 27 10:45:52 2026
From: jiawei@iscas.ac.cn (Jiawei)
Date: Sat, 27 Jun 2026 18:45:52 +0800
Subject: [RFC PATCH 2/5] RISC-V: Add Zcmt table-jump relaxation
In-Reply-To: <20260627104555.331493-1-jiawei@iscas.ac.cn>
References: <20260627104555.331493-1-jiawei@iscas.ac.cn>
Message-ID: <20260627104555.331493-3-jiawei@iscas.ac.cn>

Collect profitable post-relax call and jump sites, rank JT and JALT candidates
deterministically, emit a JVT only when the net benefit is positive, and
rewrite selected sites to table-jump relocations for non-position-independent
executable links.

bfd/ChangeLog:

	* elfnn-riscv.c (struct riscv_elf_link_hash_table): Add JVT fields.
	(riscv_set_jvt_addr): Add Zcmt support.
	(riscv_is_local_symbol): Ditto.
	(riscv_is_special_symbol_name): Ditto.
	(riscv_jvt_global_hash_entry): Ditto.
	(riscv_jvt_init_key): Ditto.
	(riscv_jvt_key_hash): Ditto.
	(riscv_jvt_htab_hash): Ditto.
	(riscv_jvt_key_eq): Ditto.
	(riscv_jvt_htab_entry_eq): Ditto.
	(riscv_init_jvt_htab): Ditto.
	(riscv_free_jvt_htab): Ditto.
	(riscv_ensure_jvt_htab): Ditto.
	(riscv_update_jvt_entry): Ditto.
	(riscv_elf_link_hash_table_free): Ditto.
	(riscv_elf_link_hash_table_create): Ditto.
	(riscv_use_jvt): Ditto.
	(riscv_elf_create_jvt_section): Ditto.
	(riscv_reject_local_jvt_base_symbol): Ditto.
	(riscv_define_jvt_base_symbol): Ditto.
	(riscv_elf_check_relocs): Ditto.
	(perform_relocation): Ditto.
	(riscv_elf_relocate_section): Ditto.
	(riscv_get_jvt_htab): Ditto.
	(_bfd_riscv_jvt_record): Ditto.
	(riscv_compare_jvt_key): Ditto.
	(riscv_jvt_entry_better): Ditto.
	(riscv_ranking_jvt): Ditto.
	(riscv_record_jvt_index): Ditto.
	(riscv_jvt_profiling): Ditto.
	(_bfd_riscv_jvt_mark): Ditto.
	(_bfd_riscv_relax_call): Ditto.
	(_bfd_riscv_relax_jal): Ditto.
	(_bfd_riscv_get_max_alignment): Ditto.
	(bfd_elfNN_riscv_set_data_segment_info): Ditto.
	(_bfd_riscv_relax_section): Ditto.
	(riscv_final_link): Ditto.
	(bfd_elfNN_bfd_final_link): Ditto.
---
 bfd/elfnn-riscv.c | 1134 +++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 1098 insertions(+), 36 deletions(-)

diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
index 1c1c3ea36c5..b1b21e996e8 100644
--- a/bfd/elfnn-riscv.c
+++ b/bfd/elfnn-riscv.c
@@ -27,6 +27,7 @@
 #include "libbfd.h"
 #include "bfdlink.h"
 #include "genlink.h"
+#include "hashtab.h"
 #include "elf-bfd.h"
 #include "elfxx-riscv.h"
 #include "elf/riscv.h"
@@ -203,6 +204,65 @@ elfNN_riscv_mkobject (bfd *abfd)
 #include "elf/common.h"
 #include "elf/internal.h"
 
+/* Identity of one JVT entry.  */
+/* JVT candidates are keyed by relocation symbol identity plus addend and PLT
+   selection.  This v2 implementation deliberately does not canonicalize
+   aliases to final section+offset addresses after ordinary relaxation.  */
+typedef struct
+{
+  bool is_local;
+  bool use_plt;
+  bfd *input_bfd;
+  unsigned long symndx;
+  struct elf_link_hash_entry *h;
+  bfd_signed_vma addend;
+} riscv_jvt_key_t;
+
+/* Per-slot data for JVT entries.  */
+typedef struct
+{
+  bfd_size_type benefit;
+  bfd_size_type first_seen;
+  riscv_jvt_key_t key;
+  const char *name;
+} riscv_jvt_slot_t;
+
+/* Hash table for storing table jump candidate entries.  */
+typedef struct
+{
+  /* Hash tables for cm.jt and cm.jalt.  They record all possible
+     entries and will be ranked to put the most beneficial ones into JVT
+     section.  */
+  htab_t jt_htab;
+  htab_t jalt_htab;
+
+  /* Target-endian contents that will be put into JVT section.  */
+  bfd_byte *jvt_addrs;
+
+  asection *jvt_sec;
+  bfd *jvt_sec_owner;
+
+  /* END_IDX is used to calculate size of used slots in the table jump section,
+     and it is set to -1 if the profiling stage is complete.  */
+  int end_idx;
+  bfd_size_type total_benefits;
+  bfd_size_type next_ordinal;
+
+  /* Unified slot array for ranked JVT entries.  */
+  riscv_jvt_slot_t *slots;
+} riscv_jvt_htab_t;
+
+typedef struct
+{
+  unsigned int index;
+
+  riscv_jvt_key_t key;
+
+  bfd_size_type benefit;
+  bfd_size_type first_seen;
+  const char *name;
+} riscv_jvt_htab_entry;
+
 struct riscv_elf_link_hash_table
 {
   struct elf_link_hash_table elf;
@@ -241,6 +301,11 @@ struct riscv_elf_link_hash_table
   bool (*make_plt_header) (bfd *output_bfd, struct riscv_elf_link_hash_table *htab);
   bool (*make_plt_entry) (bfd *output_bfd, asection *got, bfd_vma got_offset,
 			  asection *plt, bfd_vma plt_offset);
+
+  riscv_jvt_htab_t *jvt_htab;
+
+  /* Cached result for riscv_use_jvt, scoped to one link.  */
+  int use_jvt;
 };
 
 /* Instruction access functions. */
@@ -266,6 +331,8 @@ static bool
 riscv_make_plt_header (bfd *, struct riscv_elf_link_hash_table *);
 static bool
 riscv_make_plt_entry (bfd *, asection *, bfd_vma, asection *, bfd_vma);
+static void
+riscv_set_jvt_addr (struct bfd_link_info *, unsigned int, bfd_vma);
 
 void
 riscv_elfNN_set_options (struct bfd_link_info *link_info,
@@ -307,6 +374,13 @@ riscv_is_insn_reloc (const reloc_howto_type *howto)
 	       ? (MINUS_ONE << howto->bitsize) : (bfd_vma)0)) != 0);
 }
 
+/* Return true if the given symbol index is a local symbol.  */
+static inline bool
+riscv_is_local_symbol (Elf_Internal_Shdr *symtab_hdr, unsigned long symndx)
+{
+  return symndx < symtab_hdr->sh_info;
+}
+
 /* PLT/GOT stuff.  */
 #define PLT_HEADER_INSNS 8
 #define PLT_ENTRY_INSNS 4
@@ -533,6 +607,14 @@ riscv_make_plt_zicfilp_unlabeled_entry (bfd *output_bfd, asection *got,
   return true;
 }
 
+static inline bool
+riscv_is_special_symbol_name (bfd *abfd, const char *name)
+{
+  return (!strcmp (name, "")
+	  || _bfd_elf_is_local_label_name (abfd, name)
+	  || riscv_elf_is_mapping_symbols (name));
+}
+
 /* Create an entry in an RISC-V ELF linker hash table.  */
 
 static struct bfd_hash_entry *
@@ -563,6 +645,211 @@ link_hash_newfunc (struct bfd_hash_entry *entry,
   return entry;
 }
 
+static struct elf_link_hash_entry *
+riscv_jvt_global_hash_entry (bfd *abfd, unsigned long symndx)
+{
+  Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (abfd);
+  struct elf_link_hash_entry *h;
+
+  if (symndx < symtab_hdr->sh_info)
+    return NULL;
+
+  h = elf_sym_hashes (abfd)[symndx - symtab_hdr->sh_info];
+  if (h == NULL)
+    return NULL;
+
+  while (h->root.type == bfd_link_hash_indirect
+	 || h->root.type == bfd_link_hash_warning)
+    h = (struct elf_link_hash_entry *) h->root.u.i.link;
+
+  return h;
+}
+
+static bool
+riscv_jvt_init_key (struct bfd_link_info *info, bfd *abfd,
+		    const Elf_Internal_Rela *rel, riscv_jvt_key_t *key,
+		    const char **name)
+{
+  Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (abfd);
+  unsigned long symndx = ELFNN_R_SYM (rel->r_info);
+
+  memset (key, 0, sizeof (*key));
+  key->input_bfd = abfd;
+  key->symndx = symndx;
+  key->addend = rel->r_addend;
+
+  if (riscv_is_local_symbol (symtab_hdr, symndx))
+    {
+      Elf_Internal_Sym *sym;
+
+      if (symtab_hdr->contents == NULL)
+	return false;
+
+      sym = (Elf_Internal_Sym *) symtab_hdr->contents + symndx;
+      *name = bfd_elf_sym_name (abfd, symtab_hdr, sym, NULL);
+      key->is_local = true;
+    }
+  else
+    {
+      struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (info);
+      struct elf_link_hash_entry *h = riscv_jvt_global_hash_entry (abfd,
+								   symndx);
+
+      if (h == NULL || h->type == STT_GNU_IFUNC)
+	return false;
+
+      key->h = h;
+      key->use_plt = htab->elf.splt != NULL && h->plt.offset != MINUS_ONE;
+      *name = h->root.root.string;
+    }
+
+  return *name != NULL && !riscv_is_special_symbol_name (abfd, *name);
+}
+
+static hashval_t
+riscv_jvt_key_hash (const riscv_jvt_key_t *key)
+{
+  hashval_t h;
+  bfd_vma addend = (bfd_vma) key->addend;
+
+  if (key->is_local)
+    {
+      unsigned int id = key->input_bfd->id;
+      unsigned int symndx = key->symndx;
+
+      h = (id + symndx) * (id + symndx + 1) / 2 + id;
+    }
+  else
+    h = htab_hash_pointer (key->h);
+
+  h ^= (hashval_t) addend;
+  h ^= (hashval_t) (addend >> 32);
+  if (key->use_plt)
+    h ^= 0x9e3779b9;
+  return h;
+}
+
+static hashval_t
+riscv_jvt_htab_hash (const void *entry)
+{
+  const riscv_jvt_htab_entry *e = entry;
+  return riscv_jvt_key_hash (&e->key);
+}
+
+static bool
+riscv_jvt_key_eq (const riscv_jvt_key_t *key1, const riscv_jvt_key_t *key2)
+{
+  if (key1->is_local != key2->is_local
+      || key1->use_plt != key2->use_plt
+      || key1->addend != key2->addend)
+    return false;
+
+  if (key1->is_local)
+    return (key1->input_bfd->id == key2->input_bfd->id
+	    && key1->symndx == key2->symndx);
+
+  return key1->h == key2->h;
+}
+
+static int
+riscv_jvt_htab_entry_eq (const void *entry1, const void *entry2)
+{
+  const riscv_jvt_htab_entry *e1 = entry1, *e2 = entry2;
+  return riscv_jvt_key_eq (&e1->key, &e2->key);
+}
+
+static bool
+riscv_init_jvt_htab (riscv_jvt_htab_t *htab)
+{
+  htab->slots = bfd_zmalloc (sizeof (riscv_jvt_slot_t) * ZCMT_TOTAL_ENTRIES);
+  htab->jvt_addrs = bfd_zmalloc (RISCV_ELF_WORD_BYTES * ZCMT_TOTAL_ENTRIES);
+  if (htab->slots == NULL || htab->jvt_addrs == NULL)
+    return false;
+  htab->end_idx = 0;
+  htab->total_benefits = 0;
+  htab->next_ordinal = 0;
+
+  htab->jt_htab = htab_create (ZCMT_JT_NUM_ENTRIES, riscv_jvt_htab_hash,
+			       riscv_jvt_htab_entry_eq, free);
+  if (htab->jt_htab == NULL)
+    return false;
+
+  htab->jalt_htab = htab_create (ZCMT_JALT_NUM_ENTRIES, riscv_jvt_htab_hash,
+				 riscv_jvt_htab_entry_eq, free);
+  return htab->jalt_htab != NULL;
+}
+
+static void
+riscv_free_jvt_htab (riscv_jvt_htab_t *htab)
+{
+  free (htab->slots);
+  free (htab->jvt_addrs);
+  if (htab->jt_htab)
+    htab_delete (htab->jt_htab);
+  if (htab->jalt_htab)
+    htab_delete (htab->jalt_htab);
+}
+
+static bool
+riscv_ensure_jvt_htab (struct riscv_elf_link_hash_table *htab)
+{
+  if (htab->jvt_htab != NULL)
+    return true;
+
+  htab->jvt_htab = (riscv_jvt_htab_t *) bfd_zmalloc (sizeof (*htab->jvt_htab));
+  if (htab->jvt_htab == NULL)
+    return false;
+
+  if (!riscv_init_jvt_htab (htab->jvt_htab))
+    {
+      riscv_free_jvt_htab (htab->jvt_htab);
+      free (htab->jvt_htab);
+      htab->jvt_htab = NULL;
+      return false;
+    }
+
+  return true;
+}
+
+/* Update table jump hash entry.  */
+
+static bool
+riscv_update_jvt_entry (riscv_jvt_htab_t *jvt_htab, htab_t htab,
+			const riscv_jvt_key_t *key,
+			bfd_size_type benefit, const char *name)
+{
+  riscv_jvt_htab_entry search = {.index = 0,
+				 .key = *key,
+				 .benefit = 0,
+				 .first_seen = 0,
+				 .name = NULL};
+
+  riscv_jvt_htab_entry *entry = htab_find (htab, &search);
+
+  if (entry == NULL)
+    {
+      riscv_jvt_htab_entry **slot
+	= (riscv_jvt_htab_entry **) htab_find_slot (htab, &search, INSERT);
+
+      BFD_ASSERT (*slot == NULL);
+
+      *slot
+	= (riscv_jvt_htab_entry *) bfd_zmalloc (sizeof (riscv_jvt_htab_entry));
+
+      if (*slot == NULL)
+	return false;
+
+      (*slot)->key = *key;
+      (*slot)->benefit = benefit;
+      (*slot)->first_seen = jvt_htab->next_ordinal++;
+      (*slot)->name = name;
+    }
+  else
+    entry->benefit += benefit;
+
+  return true;
+}
+
 /* Compute a hash of a local hash entry.  We use elf_link_hash_entry
    for local symbol so that we can handle local STT_GNU_IFUNC symbols
    as global symbol.  We reuse indx and dynstr_index for local symbol
@@ -640,6 +927,12 @@ riscv_elf_link_hash_table_free (bfd *obfd)
   if (ret->loc_hash_memory)
     objalloc_free ((struct objalloc *) ret->loc_hash_memory);
 
+  if (ret->jvt_htab)
+    {
+      riscv_free_jvt_htab (ret->jvt_htab);
+      free (ret->jvt_htab);
+    }
+
   _bfd_elf_link_hash_table_free (obfd);
 }
 
@@ -696,6 +989,7 @@ riscv_elf_link_hash_table_create (bfd *abfd)
 
   ret->max_alignment = (bfd_vma) -1;
   ret->max_alignment_for_gp = (bfd_vma) -1;
+  ret->use_jvt = -1;
 
   setup_plt_values (abfd, ret, PLT_NORMAL);
 
@@ -915,6 +1209,193 @@ bad_static_reloc (bfd *abfd, unsigned r_type, struct elf_link_hash_entry *h)
   return false;
 }
 
+static bool
+riscv_use_jvt (struct bfd_link_info *info)
+{
+  unsigned xlen = ARCH_SIZE;
+  riscv_subset_list_t subsets;
+  struct riscv_elf_link_hash_table *htab;
+
+  htab = riscv_elf_hash_table (info);
+  if (htab->use_jvt >= 0)
+    return htab->use_jvt;
+
+  /* If relax is disabled by user, generating position-independent output,
+     or not linking an executable, table jump insns will not be generated.  */
+  if (info->disable_target_specific_optimizations >= 1
+      || bfd_link_pic (info)
+      || !bfd_link_executable (info)
+      || !htab->params->relax_zcmt)
+    {
+      htab->use_jvt = 0;
+      return htab->use_jvt;
+    }
+
+  bfd *obfd = info->output_bfd;
+  obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
+
+  subsets.head = NULL;
+  subsets.tail = NULL;
+  subsets.arch_str = NULL;
+
+  riscv_parse_subset_t riscv_rps_ld_out
+    = {&subsets, _bfd_error_handler, &xlen, NULL, false};
+
+  if (!riscv_parse_subset (&riscv_rps_ld_out, out_attr[Tag_RISCV_arch].s))
+    {
+      htab->use_jvt = 0;
+      riscv_release_subset_list (&subsets);
+      return htab->use_jvt;
+    }
+
+  /* Mirror the ISA and psABI constraints: Zcmt depends on Zca and Zicsr,
+     and its encodings overlap with Zcd compressed floating-point encodings.  */
+  htab->use_jvt = (riscv_subset_supports (&riscv_rps_ld_out, "zcmt")
+		   && riscv_subset_supports (&riscv_rps_ld_out, "zca")
+		   && riscv_subset_supports (&riscv_rps_ld_out, "zicsr")
+		   && !riscv_subset_supports (&riscv_rps_ld_out, "zcd"));
+  riscv_release_subset_list (&subsets);
+
+  return htab->use_jvt;
+}
+
+static bool
+riscv_elf_create_jvt_section (bfd *abfd, struct bfd_link_info *info)
+{
+  asection *sec;
+  struct riscv_elf_link_hash_table *htab;
+
+  /* Skip if no Zcmt.  */
+  if (!riscv_use_jvt (info))
+    return true;
+
+  htab = riscv_elf_hash_table (info);
+  if (!riscv_ensure_jvt_htab (htab))
+    return false;
+  sec = bfd_get_linker_section (abfd, TABLE_JUMP_SEC_NAME);
+
+  if (sec != NULL)
+    return true;
+
+  if (htab->jvt_htab->jvt_sec == NULL)
+    {
+      sec = bfd_make_section_anyway_with_flags (
+	abfd, TABLE_JUMP_SEC_NAME,
+	(SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_HAS_CONTENTS | SEC_IN_MEMORY
+	 | SEC_KEEP | SEC_CODE));
+
+      /* Create only a zero-sized placeholder before relaxation.  The Zcmt
+	 profiling pass sets the final alignment and size if a profitable
+	 table is chosen, so links that opt in but select no JVT do not reserve
+	 a full table or perturb layout.  */
+      if (sec == NULL || !bfd_set_section_alignment (sec, 0)
+	  || !bfd_set_section_size (sec, 0))
+	return false;
+
+      htab->jvt_htab->jvt_sec = sec;
+      htab->jvt_htab->jvt_sec_owner = abfd;
+    }
+
+  return true;
+}
+
+static bool
+riscv_reject_local_jvt_base_symbol (bfd *abfd)
+{
+  Elf_Internal_Shdr *symtab_hdr = &elf_symtab_hdr (abfd);
+  Elf_Internal_Sym *isymbuf;
+  unsigned long symndx;
+
+  if (symtab_hdr->sh_info == 0)
+    return true;
+
+  if (symtab_hdr->contents == NULL
+      && !(symtab_hdr->contents = (unsigned char *) bfd_elf_get_elf_syms
+	   (abfd, symtab_hdr, symtab_hdr->sh_info, 0, NULL, NULL, NULL)))
+    return false;
+
+  isymbuf = (Elf_Internal_Sym *) symtab_hdr->contents;
+  for (symndx = 0; symndx < symtab_hdr->sh_info; symndx++)
+    {
+      const char *name = bfd_elf_sym_name (abfd, symtab_hdr,
+					   isymbuf + symndx, NULL);
+
+      if (name != NULL && strcmp (name, RISCV_TABLE_JUMP_BASE_SYMBOL) == 0)
+	{
+	  _bfd_error_handler
+	    (_("%pB: %s is reserved for Zcmt table-jump relaxation"),
+	     abfd, RISCV_TABLE_JUMP_BASE_SYMBOL);
+	  bfd_set_error (bfd_error_bad_value);
+	  return false;
+	}
+    }
+
+  return true;
+}
+
+static bool
+riscv_define_jvt_base_symbol (bfd *abfd, struct bfd_link_info *info)
+{
+  struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (info);
+  riscv_jvt_htab_t *jvt_htab = htab->jvt_htab;
+  struct elf_link_hash_entry *h;
+  struct bfd_link_hash_entry *bh = NULL;
+  const struct elf_backend_data *bed = get_elf_backend_data (abfd);
+  bfd *ibfd;
+
+  if (jvt_htab == NULL || jvt_htab->jvt_sec == NULL
+      || jvt_htab->jvt_sec->size == 0)
+    return true;
+
+  if (jvt_htab->jvt_sec->contents == NULL)
+    {
+      jvt_htab->jvt_sec->contents
+	= (bfd_byte *) bfd_zalloc (jvt_htab->jvt_sec->owner,
+				   jvt_htab->jvt_sec->size);
+      jvt_htab->jvt_sec->alloced = 1;
+      if (jvt_htab->jvt_sec->contents == NULL)
+	return false;
+    }
+
+  h = elf_link_hash_lookup (elf_hash_table (info),
+			    RISCV_TABLE_JUMP_BASE_SYMBOL,
+			    false, false, true);
+  /* Code may reference __jvt_base$ to initialize the JVT CSR before
+     executing cm.jt/cm.jalt.  That is not a user definition; resolve
+     undefined references by defining the linker-owned symbol below, but
+     still reject any user-provided definition of the reserved name.  */
+  if (h != NULL
+      && h->root.type != bfd_link_hash_new
+      && h->root.type != bfd_link_hash_undefined
+      && h->root.type != bfd_link_hash_undefweak)
+    {
+      _bfd_error_handler
+	(_("%pB: %s is reserved for Zcmt table-jump relaxation"),
+	 abfd, RISCV_TABLE_JUMP_BASE_SYMBOL);
+      bfd_set_error (bfd_error_bad_value);
+      return false;
+    }
+
+  for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
+    if (!riscv_reject_local_jvt_base_symbol (ibfd))
+      return false;
+
+  if (!_bfd_generic_link_add_one_symbol (info, abfd,
+					 RISCV_TABLE_JUMP_BASE_SYMBOL,
+					 BSF_GLOBAL, jvt_htab->jvt_sec,
+					 0, NULL, true, bed->collect, &bh))
+    return false;
+
+  h = (struct elf_link_hash_entry *) bh;
+  h->root.linker_def = 1;
+  h->def_regular = 1;
+  h->type = STT_NOTYPE;
+  if (ELF_ST_VISIBILITY (h->other) != STV_INTERNAL)
+    h->other = ((h->other & ~ELF_ST_VISIBILITY (-1)) | STV_HIDDEN);
+  bed->elf_backend_hide_symbol (info, h, true);
+  return true;
+}
+
 /* Look through the relocs for a section during the first phase, and
    allocate space in the global offset table or procedure linkage
    table.  */
@@ -1261,6 +1742,9 @@ riscv_elf_check_relocs (bfd *abfd, struct bfd_link_info *info,
 	}
     }
 
+  if (!riscv_elf_create_jvt_section (abfd, info))
+    return false;
+
   return true;
 }
 
@@ -2037,6 +2521,9 @@ perform_relocation (const reloc_howto_type *howto,
       value = ENCODE_CBTYPE_IMM (value);
       break;
 
+    case R_RISCV_TABLE_JUMP:
+      return bfd_reloc_ok;
+
     case R_RISCV_RVC_JUMP:
       if (!VALID_CJTYPE_IMM (value))
 	return bfd_reloc_overflow;
@@ -2985,6 +3472,24 @@ riscv_elf_relocate_section (struct bfd_link_info *info,
 	  }
 	  break;
 
+	case R_RISCV_TABLE_JUMP:
+	  {
+	    bfd_vma insn = bfd_getl16 (contents + rel->r_offset);
+	    unsigned int tbl_index = EXTRACT_ZCMT_INDEX (insn);
+
+	    if (via_plt)
+	      {
+		relocation = sec_addr (htab->elf.splt) + h->plt.offset;
+		unresolved_reloc = false;
+	      }
+
+	    if (!riscv_ensure_jvt_htab (htab))
+	      return false;
+	    riscv_set_jvt_addr (info, tbl_index, relocation + rel->r_addend);
+	    rel->r_info = ELFNN_R_INFO (0, R_RISCV_NONE);
+	    continue;
+	  }
+
 	case R_RISCV_CALL:
 	case R_RISCV_CALL_PLT:
 	  /* Handle a call to an undefined weak function.  This won't be
@@ -4267,6 +4772,331 @@ _riscv_relax_delete_immediate (bfd *abfd,
 				    link_info, p, 0, sec->size);
 }
 
+/* Return the cm.jt hash table for x0, or the cm.jalt hash table for ra.  */
+
+static htab_t
+riscv_get_jvt_htab (struct bfd_link_info *info, unsigned int link_reg)
+{
+  struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (info);
+
+  if (htab == NULL || !riscv_ensure_jvt_htab (htab))
+    return NULL;
+
+  if (link_reg == 0)
+    return htab->jvt_htab->jt_htab;
+  if (link_reg == X_RA)
+    return htab->jvt_htab->jalt_htab;
+
+  return NULL;
+}
+
+/* Record JAL, CALL, or CALL_PLT as a jump table candidate.  */
+
+static bool
+_bfd_riscv_jvt_record (bfd *abfd, asection *sec ATTRIBUTE_UNUSED,
+		       asection *sym_sec ATTRIBUTE_UNUSED,
+		       struct bfd_link_info *link_info, Elf_Internal_Rela *rel,
+		       bfd_vma symval ATTRIBUTE_UNUSED,
+		       bfd_vma max_alignment ATTRIBUTE_UNUSED,
+		       bfd_vma reserve_size ATTRIBUTE_UNUSED,
+		       bool *again ATTRIBUTE_UNUSED,
+		       riscv_pcgp_relocs *pcgp_relocs ATTRIBUTE_UNUSED,
+		       bool undefined_weak ATTRIBUTE_UNUSED)
+{
+  bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
+  int type = ELFNN_R_TYPE (rel->r_info);
+  bfd_vma insn;
+  bfd_size_type benefit;
+  unsigned int rd;
+  htab_t tbljal_htab;
+  const char *name;
+  riscv_jvt_key_t key;
+
+  if (type == R_RISCV_CALL || type == R_RISCV_CALL_PLT)
+    {
+      insn = bfd_getl32 (contents + rel->r_offset + 4);
+      benefit = (4 + 4) - 2; /* AUIPC + JALR -> cm.jt/cm.jalt.  */
+    }
+  else if (type == R_RISCV_JAL)
+    {
+      insn = bfd_getl32 (contents + rel->r_offset);
+      benefit = 4 - 2; /* JAL -> cm.jt/cm.jalt.  */
+    }
+  else
+    {
+      BFD_ASSERT (false);
+      return true;
+    }
+
+  rd = (insn >> OP_SH_RD) & OP_MASK_RD;
+  tbljal_htab = riscv_get_jvt_htab (link_info, rd);
+
+  if (tbljal_htab == NULL)
+    return true;
+
+  if (!riscv_jvt_init_key (link_info, abfd, rel, &key, &name))
+    return true;
+
+  return riscv_update_jvt_entry (riscv_elf_hash_table (link_info)->jvt_htab,
+				 tbljal_htab, &key, benefit, name);
+}
+
+static void
+riscv_set_jvt_addr (struct bfd_link_info *info, unsigned int index,
+		    bfd_vma addr)
+{
+  struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (info);
+  bfd_byte *loc;
+
+  BFD_ASSERT (index < ZCMT_TOTAL_ENTRIES);
+  BFD_ASSERT (htab->jvt_htab != NULL);
+
+  addr &= ~(bfd_vma) 1;
+  loc = htab->jvt_htab->jvt_addrs + index * RISCV_ELF_WORD_BYTES;
+  bfd_put_NN (info->output_bfd, addr, loc);
+}
+
+typedef struct
+{
+  riscv_jvt_htab_t *htab;
+  unsigned int start;
+  unsigned int end;
+} riscv_jvt_args;
+
+static int
+riscv_compare_jvt_key (const riscv_jvt_key_t *key1, const char *name1,
+		       const riscv_jvt_key_t *key2, const char *name2)
+{
+  int cmp;
+
+  cmp = strcmp (name1 == NULL ? "" : name1, name2 == NULL ? "" : name2);
+  if (cmp != 0)
+    return cmp;
+
+  cmp = strcmp (bfd_get_filename (key1->input_bfd),
+		bfd_get_filename (key2->input_bfd));
+  if (cmp != 0)
+    return cmp;
+
+  if (key1->symndx != key2->symndx)
+    return key1->symndx < key2->symndx ? -1 : 1;
+  if (key1->addend != key2->addend)
+    return key1->addend < key2->addend ? -1 : 1;
+  if (key1->use_plt != key2->use_plt)
+    return key1->use_plt ? 1 : -1;
+  return 0;
+}
+
+static bool
+riscv_jvt_entry_better (const riscv_jvt_htab_entry *entry,
+			const riscv_jvt_slot_t *slot)
+{
+  if (slot->benefit == 0)
+    return true;
+  if (entry->benefit != slot->benefit)
+    return entry->benefit > slot->benefit;
+  if (entry->first_seen != slot->first_seen)
+    return entry->first_seen < slot->first_seen;
+  return riscv_compare_jvt_key (&entry->key, entry->name, &slot->key,
+				slot->name) < 0;
+}
+
+static int
+riscv_ranking_jvt (void **entry_ptr, void *arg_)
+{
+  const riscv_jvt_htab_entry *entry = *entry_ptr;
+  riscv_jvt_args *arg = arg_;
+  riscv_jvt_slot_t *slots = arg->htab->slots;
+  unsigned int left;
+
+  for (left = arg->start; left <= arg->end; left++)
+    if (riscv_jvt_entry_better (entry, &slots[left]))
+      break;
+
+  if (left > arg->end)
+    return true;
+
+  for (unsigned int idx = arg->end; idx > left; idx--)
+    slots[idx] = slots[idx - 1];
+
+  slots[left].benefit = entry->benefit;
+  slots[left].first_seen = entry->first_seen;
+  slots[left].name = entry->name;
+  slots[left].key = entry->key;
+
+  return true;
+}
+
+static bool
+riscv_record_jvt_index (htab_t htab, riscv_jvt_args *args,
+			unsigned int count)
+{
+  riscv_jvt_htab_t *jvt_htab = args->htab;
+  riscv_jvt_slot_t *slots = jvt_htab->slots;
+  riscv_jvt_htab_entry *entry = NULL;
+  unsigned int idx, end;
+
+  end = args->start + count;
+  for (idx = args->start; idx < end; idx++)
+    {
+      riscv_jvt_htab_entry search =
+	{
+	  .index = 0,
+	  .key = slots[idx].key,
+	  .benefit = 0,
+	  .first_seen = 0,
+	  .name = NULL,
+	};
+
+      entry = htab_find (htab, &search);
+
+      BFD_ASSERT (entry != NULL);
+      entry->index = idx + 1;
+      jvt_htab->total_benefits += slots[idx].benefit;
+    }
+
+  if (entry != NULL && entry->index != 0)
+    jvt_htab->end_idx = entry->index;
+
+  return true;
+}
+
+static bool
+riscv_jvt_profiling (riscv_jvt_htab_t *jvt_htab, riscv_jvt_args *args)
+{
+  bfd_size_type jt_prefix[ZCMT_JT_NUM_ENTRIES + 1];
+  bfd_size_type jalt_prefix[ZCMT_JALT_NUM_ENTRIES + 1];
+  unsigned int jt_count = 0;
+  unsigned int jalt_count = 0;
+  unsigned int best_jt = 0;
+  unsigned int best_jalt = 0;
+  unsigned int best_entries = 0;
+  bfd_size_type best_benefit = 0;
+  bfd_size_type best_net = 0;
+
+  memset (jvt_htab->slots, 0,
+	  sizeof (riscv_jvt_slot_t) * ZCMT_TOTAL_ENTRIES);
+  jvt_htab->total_benefits = 0;
+  jvt_htab->end_idx = 0;
+
+  args->start = ZCMT_JT_BEGIN;
+  args->end = ZCMT_JT_END;
+  htab_traverse (jvt_htab->jt_htab, riscv_ranking_jvt, args);
+
+  args->start = ZCMT_JALT_BEGIN;
+  args->end = ZCMT_JALT_END;
+  htab_traverse (jvt_htab->jalt_htab, riscv_ranking_jvt, args);
+
+  jt_prefix[0] = 0;
+  while (jt_count < ZCMT_JT_NUM_ENTRIES
+	 && jvt_htab->slots[ZCMT_JT_BEGIN + jt_count].benefit != 0)
+    {
+      jt_prefix[jt_count + 1]
+	= jt_prefix[jt_count]
+	  + jvt_htab->slots[ZCMT_JT_BEGIN + jt_count].benefit;
+      jt_count++;
+    }
+
+  jalt_prefix[0] = 0;
+  while (jalt_count < ZCMT_JALT_NUM_ENTRIES
+	 && jvt_htab->slots[ZCMT_JALT_BEGIN + jalt_count].benefit != 0)
+    {
+      jalt_prefix[jalt_count + 1]
+	= jalt_prefix[jalt_count]
+	  + jvt_htab->slots[ZCMT_JALT_BEGIN + jalt_count].benefit;
+      jalt_count++;
+    }
+
+  for (unsigned int jt = 0; jt <= jt_count; jt++)
+    for (unsigned int jalt = 0; jalt <= jalt_count; jalt++)
+      {
+	unsigned int entries;
+	bfd_size_type benefit;
+	bfd_size_type table_cost, net;
+
+	if (jt == 0 && jalt == 0)
+	  entries = 0;
+	else if (jalt == 0)
+	  entries = jt;
+	else
+	  entries = ZCMT_JALT_BEGIN + jalt;
+
+	benefit = jt_prefix[jt] + jalt_prefix[jalt];
+	table_cost = (bfd_size_type) entries * RISCV_ELF_WORD_BYTES;
+	net = benefit > table_cost ? benefit - table_cost : 0;
+
+	if (net > best_net
+	    || (net == best_net
+		&& (entries < best_entries
+		    || (entries == best_entries
+			&& benefit > best_benefit))))
+	  {
+	    best_net = net;
+	    best_jt = jt;
+	    best_jalt = jalt;
+	    best_entries = entries;
+	    best_benefit = benefit;
+	  }
+      }
+
+  if (best_net == 0)
+    {
+      if (jvt_htab->jvt_sec != NULL)
+	{
+	  asection *sec = jvt_htab->jvt_sec;
+	  asection *out_sec = sec->output_section;
+
+	  /* The JVT placeholder is created before profitability is known so
+	     that orphan placement and relaxation sizing can see a normal
+	     linker-created section.  When no positive-benefit table is chosen,
+	     SEC_EXCLUDE alone is not enough: the orphan output section may
+	     already have been inserted into the output BFD section list and a
+	     zero-sized .riscv.jvt would remain visible to later layout and
+	     inspection.  It is safe to remove these sections here because this
+	     path runs before __jvt_base$ is defined, the placeholder has no
+	     user input section owner, and no table-jump relocations have been
+	     marked.  Tests cover both custom-script and default-script no-JVT
+	     outputs.  */
+	  sec->flags &= ~SEC_KEEP;
+	  sec->flags |= SEC_EXCLUDE;
+	  sec->output_section = bfd_abs_section_ptr;
+
+	  if (out_sec != NULL && out_sec != bfd_abs_section_ptr)
+	    {
+	      out_sec->flags &= ~SEC_KEEP;
+	      out_sec->flags |= SEC_EXCLUDE;
+	      if (!bfd_section_removed_from_list (out_sec->owner, out_sec))
+		{
+		  bfd_section_list_remove (out_sec->owner, out_sec);
+		  out_sec->owner->section_count--;
+		}
+	    }
+
+	  if (sec != out_sec
+	      && !bfd_section_removed_from_list (sec->owner, sec))
+	    {
+	      bfd_section_list_remove (sec->owner, sec);
+	      sec->owner->section_count--;
+	    }
+	}
+      jvt_htab->end_idx = -1;
+      return true;
+    }
+
+  args->start = ZCMT_JT_BEGIN;
+  args->end = ZCMT_JT_END;
+  riscv_record_jvt_index (jvt_htab->jt_htab, args, best_jt);
+
+  args->start = ZCMT_JALT_BEGIN;
+  args->end = ZCMT_JALT_END;
+  riscv_record_jvt_index (jvt_htab->jalt_htab, args, best_jalt);
+
+  jvt_htab->end_idx = best_entries;
+  jvt_htab->total_benefits = best_benefit;
+
+  return true;
+}
+
 /* Return true if TYPE is a delete relocation.  */
 
 static bool
@@ -4346,7 +5176,84 @@ typedef bool (*relax_func_t) (bfd *, asection *, asection *,
 			      riscv_pcgp_relocs *,
 			      bool undefined_weak);
 
-/* Relax AUIPC + JALR into JAL.  */
+/* Mark JAL/CALL/CALL_PLT to use table jump instructions.  */
+
+static bool
+_bfd_riscv_jvt_mark (bfd *abfd, asection *sec,
+		     asection *sym_sec ATTRIBUTE_UNUSED,
+		     struct bfd_link_info *link_info, Elf_Internal_Rela *rel,
+		     bfd_vma symval ATTRIBUTE_UNUSED,
+		     bfd_vma max_alignment ATTRIBUTE_UNUSED,
+		     bfd_vma reserve_size ATTRIBUTE_UNUSED,
+		     bool *again,
+		     riscv_pcgp_relocs *pcgp_relocs,
+		     bool undefined_weak ATTRIBUTE_UNUSED)
+{
+  bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
+  int type = ELFNN_R_TYPE (rel->r_info);
+  bfd_byte *jump_inst_location = NULL;
+  bfd_vma target, jump_inst;
+  unsigned int rd;
+  htab_t tbljal_htab;
+  riscv_jvt_key_t key;
+  const char *name;
+  riscv_jvt_htab_entry search;
+  riscv_jvt_htab_entry *entry;
+  size_t delete_count = 0;
+
+  if (type == R_RISCV_JAL)
+    {
+      jump_inst_location = contents + rel->r_offset;
+      delete_count = 2;
+    }
+  else if (type == R_RISCV_CALL || type == R_RISCV_CALL_PLT)
+    {
+      jump_inst_location = contents + rel->r_offset + 4;
+      delete_count = 6;
+    }
+  else
+    {
+      /* Dispatch should only pass JAL/CALL/CALL_PLT here.  Keep malformed
+	 or unexpected input from turning an internal invariant into a crash.  */
+      BFD_ASSERT (false);
+      return true;
+    }
+
+  jump_inst = bfd_getl32 (jump_inst_location);
+  rd = (jump_inst >> OP_SH_RD) & OP_MASK_RD;
+  tbljal_htab = riscv_get_jvt_htab (link_info, rd);
+
+  /* Check if it uses a valid link register.  */
+  if (tbljal_htab == NULL)
+    return true;
+
+  if (!riscv_jvt_init_key (link_info, abfd, rel, &key, &name))
+    return true;
+
+  search.index = 0;
+  search.key = key;
+  search.benefit = 0;
+  search.first_seen = 0;
+  search.name = NULL;
+  entry = htab_find (tbljal_htab, &search);
+
+  /* entry->index == 0 when the entry is not used as a table jump entry.  */
+  if (entry != NULL && entry->index > 0)
+    {
+      target = MATCH_CM_JT | ENCODE_ZCMT_INDEX (entry->index - 1);
+      bfd_putl16 (target, contents + rel->r_offset);
+      rel->r_info
+	= ELFNN_R_INFO (ELFNN_R_SYM (rel->r_info), R_RISCV_TABLE_JUMP);
+      *again = true;
+      return riscv_relax_delete_bytes (abfd, sec, rel->r_offset + 2,
+				       delete_count, link_info, pcgp_relocs,
+				       rel + 1, false);
+    }
+
+  return true;
+}
+
+/* Relax AUIPC + JALR into JAL or CM.[JT,JALT].  */
 
 static bool
 _bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec,
@@ -4365,6 +5272,9 @@ _bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec,
   bfd_vma auipc, jalr;
   int rd, r_type, len = 4, rvc = elf_elfheader (abfd)->e_flags & EF_RISCV_RVC;
 
+  auipc = bfd_getl32 (contents + rel->r_offset);
+  jalr = bfd_getl32 (contents + rel->r_offset + 4);
+
   /* If the call crosses section boundaries, an alignment directive could
      cause the PC-relative offset to later increase, so we need to add in the
      max alignment of any section inclusive from the call to the target.
@@ -4384,8 +5294,6 @@ _bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec,
   /* Shorten the function call.  */
   BFD_ASSERT (rel->r_offset + 8 <= sec->size);
 
-  auipc = bfd_getl32 (contents + rel->r_offset);
-  jalr = bfd_getl32 (contents + rel->r_offset + 4);
   rd = (jalr >> OP_SH_RD) & OP_MASK_RD;
   rvc = rvc && VALID_CJTYPE_IMM (foff);
 
@@ -4442,13 +5350,14 @@ _bfd_riscv_relax_jal (bfd *abfd, asection *sec, asection *sym_sec,
   bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
   bfd_vma foff = symval - (sec_addr (sec) + rel->r_offset);
   bool rvc = elf_elfheader (abfd)->e_flags & EF_RISCV_RVC;
+  bfd_vma jal = bfd_getl32 (contents + rel->r_offset);
+  int rd;
 
   /* Can't relax to compressed instruction without RVC.  */
   if (!rvc)
     return true;
 
-  bfd_vma jal = bfd_getl32 (contents + rel->r_offset);
-  int rd = (jal >> OP_SH_RD) & OP_MASK_RD;
+  rd = (jal >> OP_SH_RD) & OP_MASK_RD;
 
   /* C.J exists on RV32 and RV64, but C.JAL is RV32-only.  */
   if (!(rd == 0 || (rd == X_RA && ARCH_SIZE == 32)))
@@ -4503,6 +5412,11 @@ _bfd_riscv_get_max_alignment (asection *sec, bfd_vma gp)
   for (o = sec->output_section->owner->sections; o != NULL; o = o->next)
     {
       bool valid = true;
+      /* Exclude the table jump section because it does not affect
+	 alignment.  */
+      if (strcmp (o->name, TABLE_JUMP_SEC_NAME) == 0)
+	continue;
+
       if (gp
 	  && !(VALID_ITYPE_IMM (sec_addr (o) - gp)
 	       || VALID_ITYPE_IMM (sec_addr (o) + o->size - gp)))
@@ -4909,10 +5823,10 @@ bfd_elfNN_riscv_set_data_segment_info (struct bfd_link_info *info,
 }
 
 /* Relax a section.
-
    Pass 0: Shortens code sequences for LUI/CALL/TPREL/PCREL relocs and
 	   deletes the obsolete bytes.
-   Pass 1: Which cannot be disabled, handles code alignment directives.  */
+   Pass 1: Table jump profiling.
+   Pass 2: Which cannot be disabled, handles code alignment directives.  */
 
 static bool
 _bfd_riscv_relax_section (bfd *abfd, asection *sec,
@@ -4925,19 +5839,17 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
   Elf_Internal_Rela *relocs;
   bool ret = false;
   unsigned int i;
-  bfd_vma max_alignment, reserve_size = 0;
+  bfd_vma max_alignment, reserve_size = 0, used_bytes, trimmed_bytes;
   riscv_pcgp_relocs pcgp_relocs;
   static asection *first_section = NULL;
+  riscv_jvt_htab_t *jvt_htab = NULL;
 
   *again = false;
 
-  if (bfd_link_relocatable (info)
-      || sec->sec_flg0
-      || sec->reloc_count == 0
-      || (sec->flags & SEC_RELOC) == 0
-      || (sec->flags & SEC_HAS_CONTENTS) == 0
+  if (bfd_link_relocatable (info) || sec->sec_flg0 || sec->reloc_count == 0
+      || (sec->flags & SEC_RELOC) == 0 || (sec->flags & SEC_HAS_CONTENTS) == 0
       || (info->disable_target_specific_optimizations
-	  && info->relax_pass == 0)
+	  && info->relax_pass <= RELAX_PASS_CAN_BE_DISABLED)
       /* The exp_seg_relro_adjust is enum phase_enum (0x4),
 	 and defined in ld/ldexp.h.  */
       || *(htab->data_segment_phase) == 4)
@@ -4958,6 +5870,16 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
   else if (!(relocs = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL,
 						 info->keep_memory)))
     goto fail;
+  /* Read this BFD's contents if we haven't done so already.  */
+  if (!data->this_hdr.contents
+      && !bfd_malloc_and_get_section (abfd, sec, &data->this_hdr.contents))
+    goto fail;
+
+  /* Read this BFD's symbols if we haven't done so already.  */
+  if (symtab_hdr->sh_info != 0 && !symtab_hdr->contents
+      && !(symtab_hdr->contents = (unsigned char *) bfd_elf_get_elf_syms (
+	     abfd, symtab_hdr, symtab_hdr->sh_info, 0, NULL, NULL, NULL)))
+    goto fail;
 
   /* Estimate the maximum alignment for all output sections once time
      should be enough.  */
@@ -4968,6 +5890,96 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
       htab->max_alignment = max_alignment;
     }
 
+  /* relax_trip 0 / JVT_PROFILING_RECORD_SYM:
+	Record symbol address and expected size saving of each relocation
+	that can be replaced by table jump instructions.
+
+     relax_trip 1 / JVT_PROFILING_RANK:
+	Rank the best ZCMT_JT_NUM_ENTRIES relocations to replace for cm.jt and
+	the best ZCMT_JALT_NUM_ENTRIES relocations for cm.jalt in terms of the
+	total size saved.
+
+     relax_trip 2 / JVT_PROFILING_DETERMINE:
+	Check if table jump can reduce the size, and delete the whole table
+	jump section if the size will not be reduced.
+	If table jump can save size, and then we replace all targeted
+	instructions/instruction pairs (e.g. auipc+jalr) to table jump
+	instructions with the index encoded. Then add relocations to the jump
+	table.
+
+     relax_trip 3 / JVT_PROFILING_TRIM:
+	Trim unused slots in the table jump section.  */
+
+  if (info->relax_pass == RELAX_PASS_TABLE_JUMP_PROFILING
+      && riscv_use_jvt (info))
+    {
+      if (!riscv_ensure_jvt_htab (htab))
+	goto fail;
+      jvt_htab = htab->jvt_htab;
+
+      riscv_relax_delete_bytes = _riscv_relax_delete_immediate;
+      /* Avoid size benefits of relocations to be recorded multiple times.  */
+      if (info->relax_trip == JVT_PROFILING_RECORD_SYM
+	  && *(htab->data_segment_phase) != 0)
+	return true;
+
+      /* Rank the entries, and calculate the expected total saving.  */
+      else if (info->relax_trip == JVT_PROFILING_RANK)
+	{
+	  *again = true;
+	  /* Profiling stage finished.  */
+	  if (jvt_htab->end_idx != 0)
+	    return true;
+
+	  riscv_jvt_args args = {jvt_htab, 0, 0};
+	  /* Estimate size benefits if table jump is used.  */
+	  riscv_jvt_profiling (jvt_htab, &args);
+	  if (jvt_htab->end_idx > 0
+	      && (!bfd_set_section_alignment (jvt_htab->jvt_sec, 6)
+		  || !bfd_set_section_size
+		       (jvt_htab->jvt_sec,
+			(bfd_size_type) jvt_htab->end_idx
+			* RISCV_ELF_WORD_BYTES)))
+	    goto fail;
+	  return true;
+	}
+
+      /* Generate table-jump instructions only if profiling chose a
+	 positive-benefit table and sized .riscv.jvt.  */
+      else if (info->relax_trip == JVT_PROFILING_DETERMINE)
+	{
+	  if (jvt_htab->end_idx <= 0 || jvt_htab->jvt_sec->size == 0)
+	    return true;
+
+	  *again = true;
+	}
+
+      /* Trim unused slots in the table jump section.  */
+      else if (info->relax_trip == JVT_PROFILING_TRIM)
+	{
+	  /* Table jump entry section is trimmed.  */
+	  if (jvt_htab->end_idx < 0)
+	    return true;
+
+	  used_bytes = jvt_htab->end_idx * RISCV_ELF_WORD_BYTES;
+	  if (jvt_htab->jvt_sec->size <= used_bytes)
+	    {
+	      jvt_htab->end_idx = -1;
+	      return true;
+	    }
+
+	  trimmed_bytes = jvt_htab->jvt_sec->size - used_bytes;
+	  /* Trim unused slots.  */
+	  if (!riscv_relax_delete_bytes (jvt_htab->jvt_sec->owner,
+					 jvt_htab->jvt_sec, used_bytes,
+					 trimmed_bytes, info, NULL, NULL, false))
+	    return false;
+	  /* Mark table jump profiling stage as completed.  */
+	  jvt_htab->end_idx = -1;
+	  return true;
+	}
+    }
+
   /* Examine and consider relaxing each reloc.  */
   for (i = 0; i < sec->reloc_count; i++)
     {
@@ -4981,17 +5993,49 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
 
       relax_func = NULL;
       riscv_relax_delete_bytes = NULL;
-      if (info->relax_pass == 0)
+      if (info->relax_pass == RELAX_PASS_TABLE_JUMP_PROFILING)
+	{
+	  if (!riscv_use_jvt (info))
+	    return true;
+	  riscv_relax_delete_bytes = _riscv_relax_delete_immediate;
+
+	  if ((type == R_RISCV_CALL || type == R_RISCV_CALL_PLT
+	       || type == R_RISCV_JAL)
+	      && (i == sec->reloc_count - 1
+		  || ELFNN_R_TYPE ((rel + 1)->r_info) != R_RISCV_RELAX
+		  || rel->r_offset != (rel + 1)->r_offset))
+	    continue;
+
+	  if (info->relax_trip == JVT_PROFILING_RECORD_SYM)
+	    {
+	      if (type == R_RISCV_CALL || type == R_RISCV_CALL_PLT
+		  || type == R_RISCV_JAL)
+		relax_func = _bfd_riscv_jvt_record;
+	      else
+		continue;
+	      *again = true;
+	      i++;
+	    }
+	  else if (info->relax_trip == JVT_PROFILING_DETERMINE)
+	    {
+	      if (type == R_RISCV_CALL || type == R_RISCV_CALL_PLT
+		  || type == R_RISCV_JAL)
+		relax_func = _bfd_riscv_jvt_mark;
+	      else
+		continue;
+	      i++;
+	    }
+	}
+      else if (info->relax_pass == RELAX_PASS_SHORTEN_LUI_CALL_TRREL_PCREL)
 	{
-	  if (type == R_RISCV_CALL
-	      || type == R_RISCV_CALL_PLT)
+	  if (type == R_RISCV_CALL || type == R_RISCV_CALL_PLT)
 	    relax_func = _bfd_riscv_relax_call;
-	  else if (type == R_RISCV_HI20
-		   || type == R_RISCV_LO12_I
+	  else if (type == R_RISCV_JAL)
+	    relax_func = _bfd_riscv_relax_jal;
+	  else if (type == R_RISCV_HI20 || type == R_RISCV_LO12_I
 		   || type == R_RISCV_LO12_S)
 	    relax_func = _bfd_riscv_relax_lui;
-	  else if (type == R_RISCV_TPREL_HI20
-		   || type == R_RISCV_TPREL_ADD
+	  else if (type == R_RISCV_TPREL_HI20 || type == R_RISCV_TPREL_ADD
 		   || type == R_RISCV_TPREL_LO12_I
 		   || type == R_RISCV_TPREL_LO12_S)
 	    relax_func = _bfd_riscv_relax_tls_le;
@@ -5015,7 +6059,8 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
 	  /* Skip over the R_RISCV_RELAX.  */
 	  i++;
 	}
-      else if (info->relax_pass == 1 && type == R_RISCV_ALIGN)
+      else if (info->relax_pass == RELAX_PASS_ALIGNMENT
+	       && type == R_RISCV_ALIGN)
 	{
 	  relax_func = _bfd_riscv_relax_align;
 	  riscv_relax_delete_bytes = _riscv_relax_delete_immediate;
@@ -5025,20 +6070,6 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
 
       data->relocs = relocs;
 
-      /* Read this BFD's contents if we haven't done so already.  */
-      if (!data->this_hdr.contents
-	  && !bfd_malloc_and_get_section (abfd, sec, &data->this_hdr.contents))
-	goto fail;
-
-      /* Read this BFD's symbols if we haven't done so already.  */
-      if (symtab_hdr->sh_info != 0
-	  && !symtab_hdr->contents
-	  && !(symtab_hdr->contents =
-	       (unsigned char *) bfd_elf_get_elf_syms (abfd, symtab_hdr,
-						       symtab_hdr->sh_info,
-						       0, NULL, NULL, NULL)))
-	goto fail;
-
       /* Get the value of the symbol referred to by the reloc.  */
       if (ELFNN_R_SYM (rel->r_info) < symtab_hdr->sh_info)
 	{
@@ -5384,6 +6415,36 @@ riscv_elf_obj_attrs_arg_type (obj_attr_tag_t tag)
   return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
 }
 
+static bool
+riscv_final_link (bfd *abfd, struct bfd_link_info *info)
+{
+  struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (info);
+  riscv_jvt_htab_t *jvt_htab = htab->jvt_htab;
+
+  if (riscv_use_jvt (info)
+      && !riscv_define_jvt_base_symbol (abfd, info))
+    return false;
+
+  if (!_bfd_elf_final_link (abfd, info))
+    return false;
+
+  if (riscv_use_jvt (info)
+      && jvt_htab != NULL
+      && jvt_htab->jvt_sec != NULL
+      && jvt_htab->jvt_sec->size != 0
+      && (jvt_htab->jvt_sec->flags & SEC_EXCLUDE) == 0)
+    {
+      asection *sec = jvt_htab->jvt_sec;
+      asection *out_sec = sec->output_section;
+
+      if (!bfd_set_section_contents (abfd, out_sec, jvt_htab->jvt_addrs,
+				     (file_ptr) sec->output_offset, sec->size))
+	return false;
+    }
+
+  return true;
+}
+
 /* Do not choose mapping symbols as a function name.  */
 
 static bfd_size_type
@@ -5549,6 +6610,7 @@ elfNN_riscv_merge_gnu_properties (struct bfd_link_info *info, bfd *abfd,
 #define bfd_elfNN_mkobject			elfNN_riscv_mkobject
 #define bfd_elfNN_get_synthetic_symtab		\
   elfNN_riscv_get_synthetic_symtab
+#define bfd_elfNN_bfd_final_link riscv_final_link
 
 #define elf_backend_reloc_type_class		riscv_reloc_type_class
 #define elf_backend_copy_indirect_symbol	riscv_elf_copy_indirect_symbol
-- 
2.43.0


From jiawei@iscas.ac.cn  Sat Jun 27 10:45:55 2026
From: jiawei@iscas.ac.cn (Jiawei)
Date: Sat, 27 Jun 2026 18:45:55 +0800
Subject: [RFC PATCH 5/5] RISC-V: Add Zcmt table-jump linker tests
In-Reply-To: <20260627104555.331493-1-jiawei@iscas.ac.cn>
References: <20260627104555.331493-1-jiawei@iscas.ac.cn>
Message-ID: <20260627104555.331493-6-jiawei@iscas.ac.cn>

This patch adds zcmt table jump relaxation tests.

Cover opt-in behavior, profitability, RV32/RV64 table emission,
no-benefit and no-Zcmt cases, PIC/shared negative behavior,
section layout, symbol policy, addends, GC, overflow,
and the Zcd encoding conflict.

ld/ChangeLog:

	* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Add Zcmt tests.
	* testsuite/ld-riscv-elf/table-jump-addend.d: New test.
	* testsuite/ld-riscv-elf/table-jump-addend.s: New test.
	* testsuite/ld-riscv-elf/table-jump-base-collision.d: New test.
	* testsuite/ld-riscv-elf/table-jump-base-collision.s: New test.
	* testsuite/ld-riscv-elf/table-jump-base-local-collision.d: New test.
	* testsuite/ld-riscv-elf/table-jump-base-local-collision.s: New test.
	* testsuite/ld-riscv-elf/table-jump-be32-bytes.d: New test.
	* testsuite/ld-riscv-elf/table-jump-be32-text.d: New test.
	* testsuite/ld-riscv-elf/table-jump-be64-bytes.d: New test.
	* testsuite/ld-riscv-elf/table-jump-be64-text.d: New test.
	* testsuite/ld-riscv-elf/table-jump-benefit.d: New test.
	* testsuite/ld-riscv-elf/table-jump-benefit.s: New test.
	* testsuite/ld-riscv-elf/table-jump-default-jvt-relocs.d: New test.
	* testsuite/ld-riscv-elf/table-jump-default-jvt-symbol.d: New test.
	* testsuite/ld-riscv-elf/table-jump-default-jvt.d: New test.
	* testsuite/ld-riscv-elf/table-jump-default-no-jvt.d: New test.
	* testsuite/ld-riscv-elf/table-jump-dump-unknown.d: New test.
	* testsuite/ld-riscv-elf/table-jump-emit-relocs.d: New test.
	* testsuite/ld-riscv-elf/table-jump-equal-benefit.d: New test.
	* testsuite/ld-riscv-elf/table-jump-equal-benefit.s: New test.
	* testsuite/ld-riscv-elf/table-jump-gc-comdat-symbol.d: New test.
	* testsuite/ld-riscv-elf/table-jump-gc-comdat.d: New test.
	* testsuite/ld-riscv-elf/table-jump-gc-comdat.s: New test.
	* testsuite/ld-riscv-elf/table-jump-gc-dead-symbol.d: New test.
	* testsuite/ld-riscv-elf/table-jump-gc-dead.d: New test.
	* testsuite/ld-riscv-elf/table-jump-gc-dead.s: New test.
	* testsuite/ld-riscv-elf/table-jump-jalt.d: New test.
	* testsuite/ld-riscv-elf/table-jump-jt.d: New test.
	* testsuite/ld-riscv-elf/table-jump-multiple-local-sym-2.s: New test.
	* testsuite/ld-riscv-elf/table-jump-multiple-local-sym.d: New test.
	* testsuite/ld-riscv-elf/table-jump-multiple-local-sym.s: New test.
	* testsuite/ld-riscv-elf/table-jump-no-benefit-jvt-ref.d: New test.
	* testsuite/ld-riscv-elf/table-jump-no-benefit-jvt-ref.s: New test.
	* testsuite/ld-riscv-elf/table-jump-no-benefit-section.d: New test.
	* testsuite/ld-riscv-elf/table-jump-no-benefit-symbol.d: New test.
	* testsuite/ld-riscv-elf/table-jump-no-benefit.s: New test.
	* testsuite/ld-riscv-elf/table-jump-no-relax-zcmt.d: New test.
	* testsuite/ld-riscv-elf/table-jump-no-relo-1.s: New test.
	* testsuite/ld-riscv-elf/table-jump-no-relo-2.s: New test.
	* testsuite/ld-riscv-elf/table-jump-no-relo.d: New test.
	* testsuite/ld-riscv-elf/table-jump-no-zcmt.d: New test.
	* testsuite/ld-riscv-elf/table-jump-no-zcmt.s: New test.
	* testsuite/ld-riscv-elf/table-jump-norelax.d: New test.
	* testsuite/ld-riscv-elf/table-jump-norelax.s: New test.
	* testsuite/ld-riscv-elf/table-jump-overflow.d: New test.
	* testsuite/ld-riscv-elf/table-jump-overflow.s: New test.
	* testsuite/ld-riscv-elf/table-jump-pie-relocs.d: New test.
	* testsuite/ld-riscv-elf/table-jump-pie-text.d: New test.
	* testsuite/ld-riscv-elf/table-jump-pie.d: New test.
	* testsuite/ld-riscv-elf/table-jump-pie.s: New test.
	* testsuite/ld-riscv-elf/table-jump-relax-zcmt.d: New test.
	* testsuite/ld-riscv-elf/table-jump-rv32.d: New test.
	* testsuite/ld-riscv-elf/table-jump-rv32.s: New test.
	* testsuite/ld-riscv-elf/table-jump-shared-relocs.d: New test.
	* testsuite/ld-riscv-elf/table-jump-shared-symbol.d: New test.
	* testsuite/ld-riscv-elf/table-jump-shared-text.d: New test.
	* testsuite/ld-riscv-elf/table-jump-shared.d: New test.
	* testsuite/ld-riscv-elf/table-jump-shared.s: New test.
	* testsuite/ld-riscv-elf/table-jump-strip-symbol.d: New test.
	* testsuite/ld-riscv-elf/table-jump-symbol-policy.d: New test.
	* testsuite/ld-riscv-elf/table-jump-vma-lma.d: New test.
	* testsuite/ld-riscv-elf/table-jump-vma-lma.ld: New test.
	* testsuite/ld-riscv-elf/table-jump-vma-zero.d: New test.
	* testsuite/ld-riscv-elf/table-jump-vma-zero.ld: New test.
	* testsuite/ld-riscv-elf/table-jump-vma-zero.s: New test.
	* testsuite/ld-riscv-elf/table-jump-zcd-conflict.d: New test.
	* testsuite/ld-riscv-elf/table-jump-zcmt-no-zca.d: New test.
	* testsuite/ld-riscv-elf/table-jump-zcmt-no-zca.s: New test.
	* testsuite/ld-riscv-elf/table-jump-zcmt-no-zicsr.d: New test.
	* testsuite/ld-riscv-elf/table-jump-zcmt-no-zicsr.s: New test.
	* testsuite/ld-riscv-elf/table-jump.ld: New test.
	* testsuite/ld-riscv-elf/table-jump.s: New test.
---
 ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp    | 50 ++++++++++++++++++
 ld/testsuite/ld-riscv-elf/table-jump-addend.d | 18 +++++++
 ld/testsuite/ld-riscv-elf/table-jump-addend.s | 21 ++++++++
 .../ld-riscv-elf/table-jump-base-collision.d  |  4 ++
 .../ld-riscv-elf/table-jump-base-collision.s  | 18 +++++++
 .../table-jump-base-local-collision.d         |  4 ++
 .../table-jump-base-local-collision.s         | 17 +++++++
 .../ld-riscv-elf/table-jump-be32-bytes.d      | 10 ++++
 .../ld-riscv-elf/table-jump-be32-text.d       | 13 +++++
 .../ld-riscv-elf/table-jump-be64-bytes.d      | 10 ++++
 .../ld-riscv-elf/table-jump-be64-text.d       | 13 +++++
 .../ld-riscv-elf/table-jump-benefit.d         | 17 +++++++
 .../ld-riscv-elf/table-jump-benefit.s         | 51 +++++++++++++++++++
 .../table-jump-default-jvt-relocs.d           |  9 ++++
 .../table-jump-default-jvt-symbol.d           | 10 ++++
 .../ld-riscv-elf/table-jump-default-jvt.d     | 12 +++++
 .../ld-riscv-elf/table-jump-default-no-jvt.d  | 15 ++++++
 .../ld-riscv-elf/table-jump-dump-unknown.d    | 25 +++++++++
 .../ld-riscv-elf/table-jump-emit-relocs.d     |  9 ++++
 .../ld-riscv-elf/table-jump-equal-benefit.d   | 18 +++++++
 .../ld-riscv-elf/table-jump-equal-benefit.s   | 19 +++++++
 .../table-jump-gc-comdat-symbol.d             |  9 ++++
 .../ld-riscv-elf/table-jump-gc-comdat.d       | 11 ++++
 .../ld-riscv-elf/table-jump-gc-comdat.s       | 18 +++++++
 .../ld-riscv-elf/table-jump-gc-dead-symbol.d  |  9 ++++
 .../ld-riscv-elf/table-jump-gc-dead.d         | 11 ++++
 .../ld-riscv-elf/table-jump-gc-dead.s         | 18 +++++++
 ld/testsuite/ld-riscv-elf/table-jump-jalt.d   | 18 +++++++
 ld/testsuite/ld-riscv-elf/table-jump-jt.d     | 23 +++++++++
 .../table-jump-multiple-local-sym-2.s         | 12 +++++
 .../table-jump-multiple-local-sym.d           | 16 ++++++
 .../table-jump-multiple-local-sym.s           | 18 +++++++
 .../table-jump-no-benefit-jvt-ref.d           |  4 ++
 .../table-jump-no-benefit-jvt-ref.s           | 16 ++++++
 .../table-jump-no-benefit-section.d           |  9 ++++
 .../table-jump-no-benefit-symbol.d            |  9 ++++
 .../ld-riscv-elf/table-jump-no-benefit.s      | 12 +++++
 .../ld-riscv-elf/table-jump-no-relax-zcmt.d   | 17 +++++++
 .../ld-riscv-elf/table-jump-no-relo-1.s       |  7 +++
 .../ld-riscv-elf/table-jump-no-relo-2.s       | 12 +++++
 .../ld-riscv-elf/table-jump-no-relo.d         | 16 ++++++
 .../ld-riscv-elf/table-jump-no-zcmt.d         | 16 ++++++
 .../ld-riscv-elf/table-jump-no-zcmt.s         | 16 ++++++
 .../ld-riscv-elf/table-jump-norelax.d         | 15 ++++++
 .../ld-riscv-elf/table-jump-norelax.s         | 17 +++++++
 .../ld-riscv-elf/table-jump-overflow.d        | 11 ++++
 .../ld-riscv-elf/table-jump-overflow.s        | 49 ++++++++++++++++++
 .../ld-riscv-elf/table-jump-pie-relocs.d      |  9 ++++
 .../ld-riscv-elf/table-jump-pie-text.d        |  9 ++++
 ld/testsuite/ld-riscv-elf/table-jump-pie.d    |  9 ++++
 ld/testsuite/ld-riscv-elf/table-jump-pie.s    | 13 +++++
 .../ld-riscv-elf/table-jump-relax-zcmt.d      | 23 +++++++++
 ld/testsuite/ld-riscv-elf/table-jump-rv32.d   | 15 ++++++
 ld/testsuite/ld-riscv-elf/table-jump-rv32.s   | 25 +++++++++
 .../ld-riscv-elf/table-jump-shared-relocs.d   |  9 ++++
 .../ld-riscv-elf/table-jump-shared-symbol.d   |  9 ++++
 .../ld-riscv-elf/table-jump-shared-text.d     |  9 ++++
 ld/testsuite/ld-riscv-elf/table-jump-shared.d | 12 +++++
 ld/testsuite/ld-riscv-elf/table-jump-shared.s | 15 ++++++
 .../ld-riscv-elf/table-jump-strip-symbol.d    |  9 ++++
 .../ld-riscv-elf/table-jump-symbol-policy.d   |  8 +++
 .../ld-riscv-elf/table-jump-vma-lma.d         | 16 ++++++
 .../ld-riscv-elf/table-jump-vma-lma.ld        | 10 ++++
 .../ld-riscv-elf/table-jump-vma-zero.d        | 15 ++++++
 .../ld-riscv-elf/table-jump-vma-zero.ld       | 13 +++++
 .../ld-riscv-elf/table-jump-vma-zero.s        | 14 +++++
 .../ld-riscv-elf/table-jump-zcd-conflict.d    |  9 ++++
 .../ld-riscv-elf/table-jump-zcmt-no-zca.d     |  9 ++++
 .../ld-riscv-elf/table-jump-zcmt-no-zca.s     | 24 +++++++++
 .../ld-riscv-elf/table-jump-zcmt-no-zicsr.d   |  9 ++++
 .../ld-riscv-elf/table-jump-zcmt-no-zicsr.s   | 24 +++++++++
 ld/testsuite/ld-riscv-elf/table-jump.ld       | 16 ++++++
 ld/testsuite/ld-riscv-elf/table-jump.s        | 46 +++++++++++++++++
 73 files changed, 1131 insertions(+)
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-addend.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-addend.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-base-collision.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-base-collision.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-base-local-collision.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-base-local-collision.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-be32-bytes.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-be32-text.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-be64-bytes.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-be64-text.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-benefit.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-benefit.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-default-jvt-relocs.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-default-jvt-symbol.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-default-jvt.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-default-no-jvt.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-dump-unknown.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-emit-relocs.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-equal-benefit.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-equal-benefit.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-gc-comdat-symbol.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-gc-comdat.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-gc-comdat.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-gc-dead-symbol.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-gc-dead.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-gc-dead.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-jalt.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-jt.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-multiple-local-sym-2.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-multiple-local-sym.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-multiple-local-sym.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-no-benefit-jvt-ref.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-no-benefit-jvt-ref.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-no-benefit-section.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-no-benefit-symbol.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-no-benefit.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-no-relax-zcmt.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-no-relo-1.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-no-relo-2.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-no-relo.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-no-zcmt.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-no-zcmt.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-norelax.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-norelax.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-overflow.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-overflow.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-pie-relocs.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-pie-text.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-pie.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-pie.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-relax-zcmt.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-rv32.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-rv32.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-shared-relocs.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-shared-symbol.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-shared-text.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-shared.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-shared.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-strip-symbol.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-symbol-policy.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-vma-lma.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-vma-lma.ld
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-vma-zero.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-vma-zero.ld
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-vma-zero.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-zcd-conflict.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-zcmt-no-zca.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-zcmt-no-zca.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-zcmt-no-zicsr.d
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump-zcmt-no-zicsr.s
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump.ld
 create mode 100644 ld/testsuite/ld-riscv-elf/table-jump.s

diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
index 8e26ccff10a..32f953aba78 100644
--- a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
+++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
@@ -182,11 +182,60 @@ if [istarget "riscv*-*-*"] {
 	    "-march=rv64i -mabi=lp64" {weakref64.s} \
 	    {{objdump -d weakref64.d}} "weakref64"]]
 
+    # Zcmt (jump table) tests.
+    run_dump_test "table-jump-jalt"
+    run_dump_test "table-jump-jt"
+    run_dump_test "table-jump-dump-unknown"
+    run_dump_test "table-jump-no-relo"
+    run_dump_test "table-jump-relax-zcmt"
+    run_dump_test "table-jump-no-relax-zcmt"
+    run_dump_test "table-jump-multiple-local-sym"
+    run_dump_test "table-jump-benefit"
+    run_dump_test "table-jump-addend"
+    run_dump_test "table-jump-norelax"
+    run_dump_test "table-jump-no-zcmt"
+    run_dump_test "table-jump-zcmt-no-zca"
+    run_dump_test "table-jump-zcmt-no-zicsr"
+    run_dump_test "table-jump-zcd-conflict"
+    run_dump_test "table-jump-overflow"
+    run_dump_test "table-jump-equal-benefit"
+    run_dump_test "table-jump-rv32"
+    run_dump_test "table-jump-vma-zero"
+    run_dump_test "table-jump-emit-relocs"
+    run_dump_test "table-jump-be64-bytes"
+    run_dump_test "table-jump-be64-text"
+    run_dump_test "table-jump-be32-bytes"
+    run_dump_test "table-jump-be32-text"
+    run_dump_test "table-jump-no-benefit-symbol"
+    run_dump_test "table-jump-no-benefit-section"
+    run_dump_test "table-jump-no-benefit-jvt-ref"
+    run_dump_test "table-jump-default-no-jvt"
+    run_dump_test "table-jump-default-jvt"
+    run_dump_test "table-jump-default-jvt-symbol"
+    run_dump_test "table-jump-default-jvt-relocs"
+    run_dump_test "table-jump-base-collision"
+    run_dump_test "table-jump-base-local-collision"
+    run_dump_test "table-jump-symbol-policy"
+    run_dump_test "table-jump-strip-symbol"
+    run_dump_test "table-jump-gc-dead"
+    run_dump_test "table-jump-gc-dead-symbol"
+    run_dump_test "table-jump-gc-comdat"
+    run_dump_test "table-jump-gc-comdat-symbol"
+    run_dump_test "table-jump-vma-lma"
+
     # The following tests require shared library support.
     if ![check_shared_lib_support] {
 	return
     }
 
+    run_dump_test "table-jump-pie"
+    run_dump_test "table-jump-pie-text"
+    run_dump_test "table-jump-pie-relocs"
+    run_dump_test "table-jump-shared"
+    run_dump_test "table-jump-shared-text"
+    run_dump_test "table-jump-shared-symbol"
+    run_dump_test "table-jump-shared-relocs"
+
     run_dump_test "relro-relax-lui"
     run_dump_test "relro-relax-pcrel"
     run_dump_test "variant_cc-now"
@@ -342,4 +391,5 @@ if [istarget "riscv*-*-*"] {
     run_dump_test "tls"
     run_dump_test "tlsbin"
     run_dump_test "absolute-no-relative"
+
 }
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-addend.d b/ld/testsuite/ld-riscv-elf/table-jump-addend.d
new file mode 100644
index 00000000000..11cc2b9fdfe
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-addend.d
@@ -0,0 +1,18 @@
+#source: table-jump-addend.s
+#as: -march=rv64ic_zcmt
+#ld: -Ttable-jump.ld --relax-zcmt
+#objdump: -d
+#...
+Disassembly of section .riscv.jvt:
+0+[0-9a-f]+ <__jvt_base\$>:
+[ 	]+...
+.*:[ 	]+[0-9a-f]+[ 	]+jvt.jalt\[32\]:[ 	]+target
+.*:[ 	]+[0-9a-f]+[ 	]+jvt.jalt\[33\]:[ 	]+target_4
+.*:[ 	]+[0-9a-f]+[ 	]+jvt.jalt\[34\]:[ 	]+target_8
+#...
+Disassembly of section .text:
+0+[0-9a-f]+ <_start>:
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jalt[ 	]+32 # [0-9a-f]+ <target>
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jalt[ 	]+33 # [0-9a-f]+ <target_4>
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jalt[ 	]+34 # [0-9a-f]+ <target_8>
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-addend.s b/ld/testsuite/ld-riscv-elf/table-jump-addend.s
new file mode 100644
index 00000000000..823e0710e08
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-addend.s
@@ -0,0 +1,21 @@
+	.section .text
+
+	.globl _start
+	.type _start, %function
+_start:
+	.rept 50
+	call target
+	call target + 4
+	call target + 8
+	.endr
+
+	.globl target
+	.type target, %function
+target:
+	.word 0x00000013
+	.globl target_4
+target_4:
+	.word 0x00000013
+	.globl target_8
+target_8:
+	ret
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-base-collision.d b/ld/testsuite/ld-riscv-elf/table-jump-base-collision.d
new file mode 100644
index 00000000000..5cdfe8a8e77
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-base-collision.d
@@ -0,0 +1,4 @@
+#source: table-jump-base-collision.s
+#as: -march=rv64ic_zcmt
+#ld: -Ttable-jump.ld --relax-zcmt
+#error: .*__jvt_base\$ is reserved for Zcmt table-jump relaxation
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-base-collision.s b/ld/testsuite/ld-riscv-elf/table-jump-base-collision.s
new file mode 100644
index 00000000000..182150f86a5
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-base-collision.s
@@ -0,0 +1,18 @@
+	.section .text
+
+	.globl _start
+	.type _start, %function
+_start:
+	.rept 5
+	tail target
+	.endr
+	ret
+	.space 4096
+
+	.globl __jvt_base$
+__jvt_base$:
+	.word 0
+
+	.type target, %function
+target:
+	ret
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-base-local-collision.d b/ld/testsuite/ld-riscv-elf/table-jump-base-local-collision.d
new file mode 100644
index 00000000000..2708f2e86d1
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-base-local-collision.d
@@ -0,0 +1,4 @@
+#source: table-jump-base-local-collision.s
+#as: -march=rv64ic_zcmt
+#ld: -Ttable-jump.ld --relax-zcmt
+#error: .*__jvt_base\$ is reserved for Zcmt table-jump relaxation
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-base-local-collision.s b/ld/testsuite/ld-riscv-elf/table-jump-base-local-collision.s
new file mode 100644
index 00000000000..f7206d15b49
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-base-local-collision.s
@@ -0,0 +1,17 @@
+	.section .text
+
+	.globl _start
+	.type _start, %function
+_start:
+	.rept 5
+	tail target
+	.endr
+	ret
+	.space 4096
+
+__jvt_base$:
+	.word 0
+
+	.type target, %function
+target:
+	ret
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-be32-bytes.d b/ld/testsuite/ld-riscv-elf/table-jump-be32-bytes.d
new file mode 100644
index 00000000000..49dc3451e16
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-be32-bytes.d
@@ -0,0 +1,10 @@
+#source: table-jump-rv32.s
+#as: -march=rv32ic_zcmt -mbig-endian
+#ld: -melf32briscv -Ttable-jump.ld --relax-zcmt
+#objdump: -s -j .riscv.jvt
+
+#...
+.*:     file format elf32-bigriscv
+#...
+Contents of section .riscv.jvt:
+[ 	]+0+[0-9a-f]*[ 	]+0000400e[ 	]+0000400c.*
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-be32-text.d b/ld/testsuite/ld-riscv-elf/table-jump-be32-text.d
new file mode 100644
index 00000000000..a7a00bf3e39
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-be32-text.d
@@ -0,0 +1,13 @@
+#source: table-jump-rv32.s
+#as: -march=rv32ic_zcmt -mbig-endian
+#ld: -melf32briscv -Ttable-jump.ld --relax-zcmt
+#objdump: -d
+
+#...
+.*:     file format elf32-bigriscv
+#...
+Disassembly of section .text:
+#...
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+0 # [0-9a-f]+ <foo_local>
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+1 # [0-9a-f]+ <foo_global>
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-be64-bytes.d b/ld/testsuite/ld-riscv-elf/table-jump-be64-bytes.d
new file mode 100644
index 00000000000..7dbc2d1a30e
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-be64-bytes.d
@@ -0,0 +1,10 @@
+#source: table-jump.s
+#as: -march=rv64ic_zcmt --defsym TEST_CM_JT=1 -mbig-endian
+#ld: -melf64briscv -Ttable-jump.ld --relax-zcmt
+#objdump: -s -j .riscv.jvt
+
+#...
+.*:     file format elf64-bigriscv
+#...
+Contents of section .riscv.jvt:
+[ 	]+0+[0-9a-f]*[ 	]+00000000[ 	]+00004016[ 	]+00000000[ 	]+00004014.*
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-be64-text.d b/ld/testsuite/ld-riscv-elf/table-jump-be64-text.d
new file mode 100644
index 00000000000..7477201f199
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-be64-text.d
@@ -0,0 +1,13 @@
+#source: table-jump.s
+#as: -march=rv64ic_zcmt --defsym TEST_CM_JT=1 -mbig-endian
+#ld: -melf64briscv -Ttable-jump.ld --relax-zcmt
+#objdump: -d
+
+#...
+.*:     file format elf64-bigriscv
+#...
+Disassembly of section .text:
+#...
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+0 # [0-9a-f]+ <foo_local>
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+1 # [0-9a-f]+ <foo_global>
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-benefit.d b/ld/testsuite/ld-riscv-elf/table-jump-benefit.d
new file mode 100644
index 00000000000..2fe5c787605
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-benefit.d
@@ -0,0 +1,17 @@
+#source: table-jump-benefit.s
+#as: -march=rv64ic_zcmt
+#ld: -Ttable-jump.ld --relax-zcmt
+#objdump: -d
+#...
+Disassembly of section .riscv.jvt:
+0+[0-9a-f]+ <__jvt_base\$>:
+[ 	]+...
+.*:[ 	]+[0-9a-f]+[ 	]+jvt.jalt\[32\]:[ 	]+func_d
+.*:[ 	]+[0-9a-f]+[ 	]+jvt.jalt\[33\]:[ 	]+func_c
+.*:[ 	]+[0-9a-f]+[ 	]+jvt.jalt\[34\]:[ 	]+func_b
+.*:[ 	]+[0-9a-f]+[ 	]+jvt.jalt\[35\]:[ 	]+func_a
+#...
+Disassembly of section .text:
+0+[0-9a-f]+ <_start>:
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jalt[ 	]+32 # [0-9a-f]+ <func_d>
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-benefit.s b/ld/testsuite/ld-riscv-elf/table-jump-benefit.s
new file mode 100644
index 00000000000..0450fef000f
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-benefit.s
@@ -0,0 +1,51 @@
+	.section .text
+
+	.globl _start
+	.type	_start, %function
+_start:
+	# Test benefit ranking: higher frequency functions should
+	# be prioritized for JVT entry allocation.
+	# Use reverse alphabetical order to verify sorting by benefit,
+	# not by name.
+
+	# func_d called 80 times - highest benefit
+	.rept 80
+	call func_d
+	.endr
+
+	# func_c called 50 times - medium benefit
+	.rept 50
+	call func_c
+	.endr
+
+	# func_b called 20 times - lower benefit
+	.rept 20
+	call func_b
+	.endr
+
+	# func_a called 5 times - lowest benefit
+	.rept 5
+	call func_a
+	.endr
+
+	ret
+
+	.globl func_a
+	.type	func_a, %function
+func_a:
+	ret
+
+	.globl func_b
+	.type	func_b, %function
+func_b:
+	ret
+
+	.globl func_c
+	.type	func_c, %function
+func_c:
+	ret
+
+	.globl func_d
+	.type	func_d, %function
+func_d:
+	ret
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-default-jvt-relocs.d b/ld/testsuite/ld-riscv-elf/table-jump-default-jvt-relocs.d
new file mode 100644
index 00000000000..9b3079f24b3
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-default-jvt-relocs.d
@@ -0,0 +1,9 @@
+#source: table-jump.s
+#as: -march=rv64ic_zcmt --defsym TEST_CM_JT_JALT=1
+#ld: --relax-zcmt
+#readelf: -rW
+
+#failif
+#...
+.*R_RISCV_TABLE_JUMP.*
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-default-jvt-symbol.d b/ld/testsuite/ld-riscv-elf/table-jump-default-jvt-symbol.d
new file mode 100644
index 00000000000..5dd5e43c680
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-default-jvt-symbol.d
@@ -0,0 +1,10 @@
+#source: table-jump.s
+#as: -march=rv64ic_zcmt --defsym TEST_CM_JT_JALT=1
+#ld: --relax-zcmt
+#readelf: -SWs
+
+#...
+.*\.riscv\.jvt[ 	]+PROGBITS[ 	]+[0-9a-f]+[ 	]+[0-9a-f]+[ 	]+[0-9a-f]+.*
+#...
+[ 	]+[0-9]+:[ 	]+0+[0-9a-f]+[ 	]+0[ 	]+NOTYPE[ 	]+LOCAL[ 	]+DEFAULT[ 	]+[0-9]+[ 	]+__jvt_base\$
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-default-jvt.d b/ld/testsuite/ld-riscv-elf/table-jump-default-jvt.d
new file mode 100644
index 00000000000..96c9efaa29d
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-default-jvt.d
@@ -0,0 +1,12 @@
+#source: table-jump.s
+#as: -march=rv64ic_zcmt --defsym TEST_CM_JT_JALT=1
+#ld: --relax-zcmt
+#objdump: -d
+
+#...
+Disassembly of section .text:
+#...
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+0 # [0-9a-f]+ <foo_global>
+#...
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jalt[ 	]+32 # [0-9a-f]+ <foo_global>
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-default-no-jvt.d b/ld/testsuite/ld-riscv-elf/table-jump-default-no-jvt.d
new file mode 100644
index 00000000000..1ebad80ec12
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-default-no-jvt.d
@@ -0,0 +1,15 @@
+#source: table-jump-no-benefit.s
+#as: -march=rv64ic_zcmt
+#ld: --relax-zcmt
+#objdump: -d
+
+#...
+Disassembly of section .text:
+#...
+0+[0-9a-f]+ <_start>:
+.*:[ 	]+[0-9a-f]+[ 	]+j[ 	]+[0-9a-f]+ <target>
+.*:[ 	]+[0-9a-f]+[ 	]+j[ 	]+[0-9a-f]+ <target>
+#...
+0+[0-9a-f]+ <target>:
+.*:[ 	]+[0-9a-f]+[ 	]+ret
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-dump-unknown.d b/ld/testsuite/ld-riscv-elf/table-jump-dump-unknown.d
new file mode 100644
index 00000000000..53e9097603c
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-dump-unknown.d
@@ -0,0 +1,25 @@
+#source: table-jump.s
+#as: -march=rv64ic_zcmt --defsym TEST_CM_JT=1
+#ld: -Ttable-jump.ld --strip-all --relax-zcmt
+#objdump: -d
+#...
+Disassembly of section .riscv.jvt:
+0+[0-9a-f]+ <.riscv.jvt>:
+.*:[ 	]+[0-9a-f]+[ 	]+jvt.jt\[0\]:[ 	]+<unknown>
+.*:[ 	]+[0-9a-f]+[ 	]+jvt.jt\[1\]:[ 	]+<unknown>
+#...
+Disassembly of section .text:
+0+[0-9a-f]+ <.text>:
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+0
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+1
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+0
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+1
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+0
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+1
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+0
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+1
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+0
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+1
+#...
+.*:[ 	]+[0-9a-f]+[ 	]+ret
+.*:[ 	]+[0-9a-f]+[ 	]+ret
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-emit-relocs.d b/ld/testsuite/ld-riscv-elf/table-jump-emit-relocs.d
new file mode 100644
index 00000000000..32c69c727ae
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-emit-relocs.d
@@ -0,0 +1,9 @@
+#source: table-jump.s
+#as: -march=rv64ic_zcmt --defsym TEST_CM_JALT=1
+#ld: -Ttable-jump.ld --emit-relocs --relax-zcmt
+#readelf: -rW
+
+#failif
+#...
+.*R_RISCV_(TABLE_JUMP|DELETE|DELETE_AND_RELAX).*
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-equal-benefit.d b/ld/testsuite/ld-riscv-elf/table-jump-equal-benefit.d
new file mode 100644
index 00000000000..6f4ed2e2682
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-equal-benefit.d
@@ -0,0 +1,18 @@
+#source: table-jump-equal-benefit.s
+#as: -march=rv64ic_zcmt
+#ld: -Ttable-jump.ld --relax-zcmt
+#objdump: -d
+
+#...
+Disassembly of section .riscv.jvt:
+0+[0-9a-f]+ <__jvt_base\$>:
+[ 	]+...
+.*:[ 	]+[0-9a-f]+[ 	]+jvt.jalt\[32\]:[ 	]+func_b
+.*:[ 	]+[0-9a-f]+[ 	]+jvt.jalt\[33\]:[ 	]+func_a
+#...
+Disassembly of section .text:
+#...
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jalt[ 	]+32 # [0-9a-f]+ <func_b>
+#...
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jalt[ 	]+33 # [0-9a-f]+ <func_a>
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-equal-benefit.s b/ld/testsuite/ld-riscv-elf/table-jump-equal-benefit.s
new file mode 100644
index 00000000000..13dc4200569
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-equal-benefit.s
@@ -0,0 +1,19 @@
+	.section .text
+
+	.globl _start
+	.type _start, %function
+_start:
+	.rept 70
+	call func_b
+	call func_a
+	.endr
+
+	.globl func_a
+	.type func_a, %function
+func_a:
+	ret
+
+	.globl func_b
+	.type func_b, %function
+func_b:
+	ret
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-gc-comdat-symbol.d b/ld/testsuite/ld-riscv-elf/table-jump-gc-comdat-symbol.d
new file mode 100644
index 00000000000..0b8ebee90bc
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-gc-comdat-symbol.d
@@ -0,0 +1,9 @@
+#source: table-jump-gc-comdat.s
+#as: -march=rv64ic_zcmt
+#ld: --gc-sections --relax-zcmt -e _start
+#readelf: -SWs
+
+#failif
+#...
+.*(__jvt_base\$|\.riscv\.jvt).*
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-gc-comdat.d b/ld/testsuite/ld-riscv-elf/table-jump-gc-comdat.d
new file mode 100644
index 00000000000..6a5e01c8ae9
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-gc-comdat.d
@@ -0,0 +1,11 @@
+#source: table-jump-gc-comdat.s
+#as: -march=rv64ic_zcmt
+#ld: --gc-sections --relax-zcmt -e _start
+#objdump: -d
+
+#...
+Disassembly of section .text:
+#...
+0+[0-9a-f]+ <_start>:
+.*:[ 	]+[0-9a-f]+[ 	]+ret
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-gc-comdat.s b/ld/testsuite/ld-riscv-elf/table-jump-gc-comdat.s
new file mode 100644
index 00000000000..591d7c47e29
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-gc-comdat.s
@@ -0,0 +1,18 @@
+	.section .text.live, "ax"
+
+	.globl _start
+	.type _start, %function
+_start:
+	ret
+
+	.section .text.dead_group, "axG", @progbits, dead_group, comdat
+	.type dead_group_start, %function
+dead_group_start:
+	.rept 70
+	call dead_group_target
+	.endr
+	ret
+
+	.type dead_group_target, %function
+dead_group_target:
+	ret
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-gc-dead-symbol.d b/ld/testsuite/ld-riscv-elf/table-jump-gc-dead-symbol.d
new file mode 100644
index 00000000000..b8a14241f12
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-gc-dead-symbol.d
@@ -0,0 +1,9 @@
+#source: table-jump-gc-dead.s
+#as: -march=rv64ic_zcmt
+#ld: --gc-sections --relax-zcmt -e _start
+#readelf: -SWs
+
+#failif
+#...
+.*(__jvt_base\$|\.riscv\.jvt).*
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-gc-dead.d b/ld/testsuite/ld-riscv-elf/table-jump-gc-dead.d
new file mode 100644
index 00000000000..1c95f06c7e0
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-gc-dead.d
@@ -0,0 +1,11 @@
+#source: table-jump-gc-dead.s
+#as: -march=rv64ic_zcmt
+#ld: --gc-sections --relax-zcmt -e _start
+#objdump: -d
+
+#...
+Disassembly of section .text:
+#...
+0+[0-9a-f]+ <_start>:
+.*:[ 	]+[0-9a-f]+[ 	]+ret
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-gc-dead.s b/ld/testsuite/ld-riscv-elf/table-jump-gc-dead.s
new file mode 100644
index 00000000000..0030a207897
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-gc-dead.s
@@ -0,0 +1,18 @@
+	.section .text.live, "ax"
+
+	.globl _start
+	.type _start, %function
+_start:
+	ret
+
+	.section .text.dead, "ax"
+	.type dead_start, %function
+dead_start:
+	.rept 70
+	call dead_target
+	.endr
+	ret
+
+	.type dead_target, %function
+dead_target:
+	ret
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-jalt.d b/ld/testsuite/ld-riscv-elf/table-jump-jalt.d
new file mode 100644
index 00000000000..098e65fc403
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-jalt.d
@@ -0,0 +1,18 @@
+#source: table-jump.s
+#as: -march=rv64ic_zcmt --defsym TEST_CM_JALT=1
+#ld: -Ttable-jump.ld --relax-zcmt
+#objdump: -d
+#...
+Disassembly of section .riscv.jvt:
+0+[0-9a-f]+ <__jvt_base\$>:
+[ 	]+...
+.*:[ 	]+[0-9a-f]+[ 	]+jvt.jalt\[32\]:[ 	]+foo_global
+.*:[ 	]+[0-9a-f]+[ 	]+jvt.jalt\[33\]:[ 	]+foo_local
+#...
+Disassembly of section .text:
+0+[0-9a-f]+ <_start>:
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jalt[ 	]+32 # [0-9a-f]+ <foo_global>
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jalt[ 	]+33 # [0-9a-f]+ <foo_local>
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jalt[ 	]+32 # [0-9a-f]+ <foo_global>
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jalt[ 	]+33 # [0-9a-f]+ <foo_local>
+#...
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-jt.d b/ld/testsuite/ld-riscv-elf/table-jump-jt.d
new file mode 100644
index 00000000000..0b0250ee104
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-jt.d
@@ -0,0 +1,23 @@
+#source: table-jump.s
+#as: -march=rv64ic_zcmt --defsym TEST_CM_JT=1
+#ld: -Ttable-jump.ld --relax-zcmt
+#objdump: -d
+#...
+Disassembly of section .riscv.jvt:
+0+[0-9a-f]+ <__jvt_base\$>:
+.*:[ 	]+[0-9a-f]+[ 	]+jvt.jt\[0\]:[ 	]+foo_local
+.*:[ 	]+[0-9a-f]+[ 	]+jvt.jt\[1\]:[ 	]+foo_global
+#...
+Disassembly of section .text:
+0+[0-9a-f]+ <_start>:
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+0 # [0-9a-f]+ <foo_local>
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+1 # [0-9a-f]+ <foo_global>
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+0 # [0-9a-f]+ <foo_local>
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+1 # [0-9a-f]+ <foo_global>
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+0 # [0-9a-f]+ <foo_local>
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+1 # [0-9a-f]+ <foo_global>
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+0 # [0-9a-f]+ <foo_local>
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+1 # [0-9a-f]+ <foo_global>
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+0 # [0-9a-f]+ <foo_local>
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+1 # [0-9a-f]+ <foo_global>
+#...
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-multiple-local-sym-2.s b/ld/testsuite/ld-riscv-elf/table-jump-multiple-local-sym-2.s
new file mode 100644
index 00000000000..bf106b88f2d
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-multiple-local-sym-2.s
@@ -0,0 +1,12 @@
+    .section .text
+    .type   bar, %function
+bar:
+    .rept 70
+    call foo_local
+    call foo_global
+    .endr
+    ret
+
+    .type   foo_local, %function
+foo_local:
+    ret
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-multiple-local-sym.d b/ld/testsuite/ld-riscv-elf/table-jump-multiple-local-sym.d
new file mode 100644
index 00000000000..07dbd3978be
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-multiple-local-sym.d
@@ -0,0 +1,16 @@
+#source: table-jump-multiple-local-sym.s
+#source: table-jump-multiple-local-sym-2.s
+#as: -march=rv64ic_zcmt
+#ld: -Ttable-jump.ld --relax-zcmt
+#objdump: -d
+
+#...
+Disassembly of section .riscv.jvt:
+0+[0-9a-f]+ <__jvt_base\$>:
+[ 	]+...
+.*:[ 	]+[0-9a-f]+[ 	]+jvt.jalt\[32\]:[ 	]+foo_global
+.*:[ 	]+[0-9a-f]+[ 	]+jvt.jalt\[33\]:[ 	]+foo_local
+.*:[ 	]+[0-9a-f]+[ 	]+jvt.jalt\[34\]:[ 	]+foo_local
+
+Disassembly of section .text:
+#...
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-multiple-local-sym.s b/ld/testsuite/ld-riscv-elf/table-jump-multiple-local-sym.s
new file mode 100644
index 00000000000..ccc2525e2f7
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-multiple-local-sym.s
@@ -0,0 +1,18 @@
+    .section .text
+
+    .globl _start
+    .type   _start, %function
+_start:
+    .rept 70
+    call foo_global
+    call foo_local
+    .endr
+
+    .globl  foo_global
+    .type   foo_global, %function
+foo_global:
+    ret
+
+    .type   foo_local, %function
+foo_local:
+    ret
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-no-benefit-jvt-ref.d b/ld/testsuite/ld-riscv-elf/table-jump-no-benefit-jvt-ref.d
new file mode 100644
index 00000000000..3b392efa45c
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-no-benefit-jvt-ref.d
@@ -0,0 +1,4 @@
+#source: table-jump-no-benefit-jvt-ref.s
+#as: -march=rv64ic_zcmt
+#ld: --relax-zcmt
+#error: .*undefined reference to `__jvt_base\$'
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-no-benefit-jvt-ref.s b/ld/testsuite/ld-riscv-elf/table-jump-no-benefit-jvt-ref.s
new file mode 100644
index 00000000000..3665215f92d
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-no-benefit-jvt-ref.s
@@ -0,0 +1,16 @@
+	.section .text
+
+	.globl _start
+	.type _start, %function
+_start:
+	.option push
+	.option norelax
+	la a0, __jvt_base$
+	.option pop
+	tail target
+	tail target
+	.space 4096
+
+	.type target, %function
+target:
+	ret
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-no-benefit-section.d b/ld/testsuite/ld-riscv-elf/table-jump-no-benefit-section.d
new file mode 100644
index 00000000000..74363ad11c6
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-no-benefit-section.d
@@ -0,0 +1,9 @@
+#source: table-jump-no-benefit.s
+#as: -march=rv64ic_zcmt
+#ld: --relax-zcmt
+#readelf: -SW
+
+#failif
+#...
+.*\.riscv\.jvt.*
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-no-benefit-symbol.d b/ld/testsuite/ld-riscv-elf/table-jump-no-benefit-symbol.d
new file mode 100644
index 00000000000..6d5eb9a35b0
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-no-benefit-symbol.d
@@ -0,0 +1,9 @@
+#source: table-jump-no-benefit.s
+#as: -march=rv64ic_zcmt
+#ld: --relax-zcmt
+#readelf: -sW
+
+#failif
+#...
+.*__jvt_base\$.*
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-no-benefit.s b/ld/testsuite/ld-riscv-elf/table-jump-no-benefit.s
new file mode 100644
index 00000000000..2292cc43b3e
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-no-benefit.s
@@ -0,0 +1,12 @@
+	.section .text
+
+	.globl _start
+	.type _start, %function
+_start:
+	tail target
+	tail target
+	.space 4096
+
+	.type target, %function
+target:
+	ret
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-no-relax-zcmt.d b/ld/testsuite/ld-riscv-elf/table-jump-no-relax-zcmt.d
new file mode 100644
index 00000000000..a551a05c97e
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-no-relax-zcmt.d
@@ -0,0 +1,17 @@
+#source: table-jump.s
+#as: -march=rv64ic_zcmt --defsym TEST_CM_JT_JALT=1
+#ld: -Ttable-jump.ld --no-relax-zcmt
+#objdump: -d
+#...
+Disassembly of section .text:
+0+[0-9a-f]+ <_start>:
+.*:[ 	]+[0-9a-f]+[ 	]+j[ 	]+[0-9a-f]+ <foo_global>
+.*:[ 	]+[0-9a-f]+[ 	]+j[ 	]+[0-9a-f]+ <foo_global>
+.*:[ 	]+[0-9a-f]+[ 	]+j[ 	]+[0-9a-f]+ <foo_global>
+.*:[ 	]+[0-9a-f]+[ 	]+j[ 	]+[0-9a-f]+ <foo_global>
+.*:[ 	]+[0-9a-f]+[ 	]+j[ 	]+[0-9a-f]+ <foo_global>
+.*:[ 	]+[0-9a-f]+[ 	]+jal[ 	]+[0-9a-f]+ <foo_global>
+.*:[ 	]+[0-9a-f]+[ 	]+jal[ 	]+[0-9a-f]+ <foo_global>
+.*:[ 	]+[0-9a-f]+[ 	]+jal[ 	]+[0-9a-f]+ <foo_global>
+.*:[ 	]+[0-9a-f]+[ 	]+jal[ 	]+[0-9a-f]+ <foo_global>
+#...
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-no-relo-1.s b/ld/testsuite/ld-riscv-elf/table-jump-no-relo-1.s
new file mode 100644
index 00000000000..d3e9b7ce4dd
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-no-relo-1.s
@@ -0,0 +1,7 @@
+    .section .text
+
+    .globl _start
+    .type	_start, %function
+_start:
+L0: j L0
+    ret
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-no-relo-2.s b/ld/testsuite/ld-riscv-elf/table-jump-no-relo-2.s
new file mode 100644
index 00000000000..f68cdaf423b
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-no-relo-2.s
@@ -0,0 +1,12 @@
+    .section .text
+
+    .globl foo
+    .type  foo, %function
+foo:
+    call bar
+
+
+    .globl bar
+    .type  bar, %function
+bar:
+    ret
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-no-relo.d b/ld/testsuite/ld-riscv-elf/table-jump-no-relo.d
new file mode 100644
index 00000000000..9ff45cb2616
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-no-relo.d
@@ -0,0 +1,16 @@
+#source: table-jump-no-relo-1.s
+#source: table-jump-no-relo-2.s
+#as: -march=rv64ic_zcmt
+#ld: -Ttable-jump.ld --relax-zcmt
+#objdump: -d
+#...
+Disassembly of section .text:
+0+[0-9a-f]+ <_start>:
+.*:[ 	]+[0-9a-f]+[ 	]+j[ 	]+[0-9a-f]+ <_start>
+.*:[ 	]+[0-9a-f]+[ 	]+ret
+
+0+[0-9a-f]+ <foo>:
+.*:[ 	]+[0-9a-f]+[ 	]+jal[ 	]+[0-9a-f]+ <bar>
+
+0+[0-9a-f]+ <bar>:
+.*:[ 	]+[0-9a-f]+[ 	]+ret
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-no-zcmt.d b/ld/testsuite/ld-riscv-elf/table-jump-no-zcmt.d
new file mode 100644
index 00000000000..5b23e81e2c8
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-no-zcmt.d
@@ -0,0 +1,16 @@
+#source: table-jump-no-zcmt.s
+#as: -march=rv64ic
+#ld: -Ttable-jump.ld --relax-zcmt
+#objdump: -d
+#...
+Disassembly of section .text:
+0+[0-9a-f]+ <_start>:
+# All calls should remain as jal (not converted to cm.jalt)
+.*:[ 	]+[0-9a-f]+[ 	]+jal[ 	]+[0-9a-f]+ <foo>
+.*:[ 	]+[0-9a-f]+[ 	]+jal[ 	]+[0-9a-f]+ <foo>
+.*:[ 	]+[0-9a-f]+[ 	]+jal[ 	]+[0-9a-f]+ <foo>
+.*:[ 	]+[0-9a-f]+[ 	]+jal[ 	]+[0-9a-f]+ <foo>
+#...
+0+[0-9a-f]+ <foo>:
+.*:[ 	]+[0-9a-f]+[ 	]+ret
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-no-zcmt.s b/ld/testsuite/ld-riscv-elf/table-jump-no-zcmt.s
new file mode 100644
index 00000000000..3e483757ba5
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-no-zcmt.s
@@ -0,0 +1,16 @@
+	.section .text
+
+	.globl _start
+	.type	_start, %function
+_start:
+	# This file is assembled without Zcmt extension.
+	# The linker should NOT generate JVT section
+	.rept 50
+	call foo
+	.endr
+	ret
+
+	.globl foo
+	.type	foo, %function
+foo:
+	ret
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-norelax.d b/ld/testsuite/ld-riscv-elf/table-jump-norelax.d
new file mode 100644
index 00000000000..8621ad8550b
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-norelax.d
@@ -0,0 +1,15 @@
+#source: table-jump-norelax.s
+#as: -march=rv64ic_zcmt
+#ld: -Ttable-jump.ld --relax-zcmt
+#objdump: -d
+#...
+Disassembly of section .text:
+0+[0-9a-f]+ <_start>:
+.*:[ 	]+[0-9a-f]+[ 	]+auipc[ 	]+ra,0x1
+.*:[ 	]+[0-9a-f]+[ 	]+jalr[ 	]+[0-9]+\(ra\) # [0-9a-f]+ <target>
+.*:[ 	]+[0-9a-f]+[ 	]+auipc[ 	]+t[0-9],0x1
+.*:[ 	]+[0-9a-f]+[ 	]+jr[ 	]+[0-9]+\(t[0-9]\) # [0-9a-f]+ <target>
+.*:[ 	]+[0-9a-f]+[ 	]+j[ 	]+[0-9a-f]+ <target>
+#...
+0+[0-9a-f]+ <target>:
+.*:[ 	]+[0-9a-f]+[ 	]+ret
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-norelax.s b/ld/testsuite/ld-riscv-elf/table-jump-norelax.s
new file mode 100644
index 00000000000..0880f79a5c5
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-norelax.s
@@ -0,0 +1,17 @@
+	.section .text
+
+	.globl _start
+	.type _start, %function
+_start:
+	.option push
+	.option norelax
+	call target
+	tail target
+	jal x0, target
+	.option pop
+
+	.space 4096
+
+	.type target, %function
+target:
+	ret
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-overflow.d b/ld/testsuite/ld-riscv-elf/table-jump-overflow.d
new file mode 100644
index 00000000000..4b5e36005a9
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-overflow.d
@@ -0,0 +1,11 @@
+#source: table-jump-overflow.s
+#as: -march=rv64ic_zcmt
+#ld: -Ttable-jump.ld --relax-zcmt
+#objdump: -d
+#...
+Disassembly of section .text:
+0+[0-9a-f]+ <_start>:
+.*:[ 	]+[0-9a-f]+[ 	]+jal[ 	]+[0-9a-f]+ <func_top>
+#...
+.*:[ 	]+[0-9a-f]+[ 	]+jal[ 	]+[0-9a-f]+ <func_overflow>
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-overflow.s b/ld/testsuite/ld-riscv-elf/table-jump-overflow.s
new file mode 100644
index 00000000000..5aae80f24c6
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-overflow.s
@@ -0,0 +1,49 @@
+	.altmacro
+	.section .text
+
+	# Test JVT overflow: cm.jalt has 224 entries (index 32-255)
+	# func_top: called 10x (highest benefit), guaranteed jvt.jalt[32]
+	# func_0 to func_222: called 2x each, fill remaining 223 JVT slots
+	# func_overflow: called 1x (lowest benefit), overflows, remains jal
+
+	.macro call2 n
+	call func_\n
+	call func_\n
+	.endm
+
+	.macro defn n
+	.type func_\n, %function
+func_\n:	ret
+	.endm
+
+	.globl _start
+	.type	_start, %function
+_start:
+	# func_top: highest benefit, guaranteed first JVT entry
+	.rept 10
+	call func_top
+	.endr
+
+	# 223 functions with 2 calls each (fill remaining JVT entries)
+	.set i, 0
+	.rept 223
+	call2 %i
+	.set i, i+1
+	.endr
+
+	# func_overflow: lowest benefit, will not fit in JVT
+	call func_overflow
+	ret
+
+	# Define functions
+	.type func_top, %function
+func_top:	ret
+
+	.set i, 0
+	.rept 223
+	defn %i
+	.set i, i+1
+	.endr
+
+	.type func_overflow, %function
+func_overflow:	ret
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-pie-relocs.d b/ld/testsuite/ld-riscv-elf/table-jump-pie-relocs.d
new file mode 100644
index 00000000000..407acf5fcc6
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-pie-relocs.d
@@ -0,0 +1,9 @@
+#source: table-jump-pie.s
+#as: -march=rv64ic_zcmt -fpic
+#ld: -pie --relax-zcmt
+#readelf: -rW
+
+#failif
+#...
+.*R_RISCV_(TABLE_JUMP|DELETE|DELETE_AND_RELAX).*
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-pie-text.d b/ld/testsuite/ld-riscv-elf/table-jump-pie-text.d
new file mode 100644
index 00000000000..8cb52d4a5df
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-pie-text.d
@@ -0,0 +1,9 @@
+#source: table-jump-pie.s
+#as: -march=rv64ic_zcmt -fpic
+#ld: -pie --relax-zcmt
+#objdump: -d
+
+#failif
+#...
+.*cm\.j(al)?t.*
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-pie.d b/ld/testsuite/ld-riscv-elf/table-jump-pie.d
new file mode 100644
index 00000000000..d8a8a6a532d
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-pie.d
@@ -0,0 +1,9 @@
+#source: table-jump-pie.s
+#as: -march=rv64ic_zcmt -fpic
+#ld: -pie --relax-zcmt
+#readelf: -SWs
+
+#failif
+#...
+.*(__jvt_base\$|\.riscv\.jvt).*
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-pie.s b/ld/testsuite/ld-riscv-elf/table-jump-pie.s
new file mode 100644
index 00000000000..3d5fe7759bd
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-pie.s
@@ -0,0 +1,13 @@
+	.section .text
+
+	.globl _start
+	.type _start, %function
+_start:
+	.rept 70
+	call target
+	.endr
+	ret
+
+	.type target, %function
+target:
+	ret
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-relax-zcmt.d b/ld/testsuite/ld-riscv-elf/table-jump-relax-zcmt.d
new file mode 100644
index 00000000000..1adb1b289ce
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-relax-zcmt.d
@@ -0,0 +1,23 @@
+#source: table-jump.s
+#as: -march=rv64ic_zcmt --defsym TEST_CM_JT_JALT=1
+#ld: -Ttable-jump.ld --relax-zcmt
+#objdump: -d
+#...
+Disassembly of section .riscv.jvt:
+0+[0-9a-f]+ <__jvt_base\$>:
+.*:[ 	]+[0-9a-f]+[ 	]+jvt.jt\[0\]:[ 	]+foo_global
+[ 	]+...
+.*:[ 	]+[0-9a-f]+[ 	]+jvt.jalt\[32\]:[ 	]+foo_global
+#...
+Disassembly of section .text:
+0+[0-9a-f]+ <_start>:
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+0 # [0-9a-f]+ <foo_global>
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+0 # [0-9a-f]+ <foo_global>
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+0 # [0-9a-f]+ <foo_global>
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+0 # [0-9a-f]+ <foo_global>
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+0 # [0-9a-f]+ <foo_global>
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jalt[ 	]+32 # [0-9a-f]+ <foo_global>
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jalt[ 	]+32 # [0-9a-f]+ <foo_global>
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jalt[ 	]+32 # [0-9a-f]+ <foo_global>
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jalt[ 	]+32 # [0-9a-f]+ <foo_global>
+#...
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-rv32.d b/ld/testsuite/ld-riscv-elf/table-jump-rv32.d
new file mode 100644
index 00000000000..ef6bbcdd526
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-rv32.d
@@ -0,0 +1,15 @@
+#source: table-jump-rv32.s
+#as: -march=rv32ic_zcmt
+#ld: -Ttable-jump.ld --relax-zcmt -melf32lriscv
+#objdump: -d
+#...
+Disassembly of section .riscv.jvt:
+0+[0-9a-f]+ <__jvt_base\$>:
+.*:[ 	]+[0-9a-f]+[ 	]+jvt.jt\[0\]:[ 	]+foo_local
+.*:[ 	]+[0-9a-f]+[ 	]+jvt.jt\[1\]:[ 	]+foo_global
+#...
+Disassembly of section .text:
+0+[0-9a-f]+ <_start>:
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+0 # [0-9a-f]+ <foo_local>
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+1 # [0-9a-f]+ <foo_global>
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-rv32.s b/ld/testsuite/ld-riscv-elf/table-jump-rv32.s
new file mode 100644
index 00000000000..274c3b03f8b
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-rv32.s
@@ -0,0 +1,25 @@
+	.section .text
+
+	# Test RV32 ZCMT relaxation for cm.jt
+	# jal x0 (no link) -> cm.jt (index 0-31)
+	# JVT entry cost: 4 bytes (RV32), benefit = 2 per call
+	# Threshold: 3*2=6 > 4 (just profitable)
+
+	.globl _start
+	.type	_start, %function
+_start:
+	.rept 3
+	tail foo_local
+	tail foo_global
+	.endr
+
+	.space 4096
+
+	.globl  foo_global
+	.type	foo_global, %function
+foo_global:
+	ret
+
+	.type	foo_local, %function
+foo_local:
+	ret
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-shared-relocs.d b/ld/testsuite/ld-riscv-elf/table-jump-shared-relocs.d
new file mode 100644
index 00000000000..1c879fff883
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-shared-relocs.d
@@ -0,0 +1,9 @@
+#source: table-jump-shared.s
+#as: -march=rv64ic_zcmt -fpic
+#ld: -shared --relax-zcmt
+#readelf: -rW
+
+#failif
+#...
+.*R_RISCV_(TABLE_JUMP|DELETE|DELETE_AND_RELAX).*
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-shared-symbol.d b/ld/testsuite/ld-riscv-elf/table-jump-shared-symbol.d
new file mode 100644
index 00000000000..a82763c2f8c
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-shared-symbol.d
@@ -0,0 +1,9 @@
+#source: table-jump-shared.s
+#as: -march=rv64ic_zcmt -fpic
+#ld: -shared --relax-zcmt
+#readelf: -SWs
+
+#failif
+#...
+.*(__jvt_base\$|\.riscv\.jvt).*
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-shared-text.d b/ld/testsuite/ld-riscv-elf/table-jump-shared-text.d
new file mode 100644
index 00000000000..262d4c59643
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-shared-text.d
@@ -0,0 +1,9 @@
+#source: table-jump-shared.s
+#as: -march=rv64ic_zcmt -fpic
+#ld: -shared --relax-zcmt
+#objdump: -d
+
+#failif
+#...
+.*cm\.j(al)?t.*
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-shared.d b/ld/testsuite/ld-riscv-elf/table-jump-shared.d
new file mode 100644
index 00000000000..1fec141e6b6
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-shared.d
@@ -0,0 +1,12 @@
+#source: table-jump-shared.s
+#as: -march=rv64ic_zcmt -fpic
+#ld: -shared --relax-zcmt
+#objdump: -d
+#...
+Disassembly of section .text:
+#...
+0+[0-9a-f]+ <foo>:
+#  Calls should NOT be cm.jalt in shared library (should be jal to PLT)
+.*:[ 	]+[0-9a-f]+[ 	]+jal[ 	]+[0-9a-f]+ <bar@plt>
+.*:[ 	]+[0-9a-f]+[ 	]+jal[ 	]+[0-9a-f]+ <bar@plt>
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-shared.s b/ld/testsuite/ld-riscv-elf/table-jump-shared.s
new file mode 100644
index 00000000000..0bd853d1ae6
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-shared.s
@@ -0,0 +1,15 @@
+	.section .text
+
+	.globl foo
+	.type	foo, %function
+foo:
+	# Shared library: JVT relaxation should be disabled
+	.rept 50
+	call bar
+	.endr
+	ret
+
+	.globl bar
+	.type	bar, %function
+bar:
+	ret
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-strip-symbol.d b/ld/testsuite/ld-riscv-elf/table-jump-strip-symbol.d
new file mode 100644
index 00000000000..39b1d99e93e
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-strip-symbol.d
@@ -0,0 +1,9 @@
+#source: table-jump.s
+#as: -march=rv64ic_zcmt --defsym TEST_CM_JALT=1
+#ld: -Ttable-jump.ld --strip-all --relax-zcmt
+#readelf: -sW
+
+#failif
+#...
+.*__jvt_base\$.*
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-symbol-policy.d b/ld/testsuite/ld-riscv-elf/table-jump-symbol-policy.d
new file mode 100644
index 00000000000..acd152a93be
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-symbol-policy.d
@@ -0,0 +1,8 @@
+#source: table-jump.s
+#as: -march=rv64ic_zcmt --defsym TEST_CM_JALT=1
+#ld: -Ttable-jump.ld --relax-zcmt
+#readelf: -sW
+
+#...
+[ 	]+[0-9]+:[ 	]+0+[0-9a-f]+[ 	]+0[ 	]+NOTYPE[ 	]+LOCAL[ 	]+DEFAULT[ 	]+[0-9]+[ 	]+__jvt_base\$
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-vma-lma.d b/ld/testsuite/ld-riscv-elf/table-jump-vma-lma.d
new file mode 100644
index 00000000000..222d546df8b
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-vma-lma.d
@@ -0,0 +1,16 @@
+#source: table-jump.s
+#as: -march=rv64ic_zcmt --defsym TEST_CM_JALT=1
+#ld: -Ttable-jump-vma-lma.ld --relax-zcmt
+#objdump: -d
+
+#...
+Disassembly of section .riscv.jvt:
+#...
+.*:[ 	]+0000000000003118[ 	]+jvt.jalt\[32\]:[ 	]+foo_global
+.*:[ 	]+000000000000311a[ 	]+jvt.jalt\[33\]:[ 	]+foo_local
+#...
+Disassembly of section .text:
+#...
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jalt[ 	]+32 # 3118 <foo_global>
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jalt[ 	]+33 # 311a <foo_local>
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-vma-lma.ld b/ld/testsuite/ld-riscv-elf/table-jump-vma-lma.ld
new file mode 100644
index 00000000000..a8202afb381
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-vma-lma.ld
@@ -0,0 +1,10 @@
+ENTRY(_start)
+SECTIONS
+{
+	.riscv.jvt 0x1000 : AT(0x8000) {
+		*(.riscv.jvt)
+	}
+	.text 0x3000 : AT(0x9000) {
+		*(.text)
+	}
+}
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-vma-zero.d b/ld/testsuite/ld-riscv-elf/table-jump-vma-zero.d
new file mode 100644
index 00000000000..c93a1c6c4f2
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-vma-zero.d
@@ -0,0 +1,15 @@
+#source: table-jump-vma-zero.s
+#as: -march=rv64ic_zcmt
+#ld: -Ttable-jump-vma-zero.ld --relax-zcmt
+#objdump: -d -s -j .riscv.jvt -j .text
+
+#...
+Contents of section .riscv.jvt:
+[ 	]+1000[ 	]+00000000[ 	]+00000000.*
+#...
+Disassembly of section .text:
+#...
+0+3000 <_start>:
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+0 # 0 <target>
+.*:[ 	]+[0-9a-f]+[ 	]+cm.jt[ 	]+0 # 0 <target>
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-vma-zero.ld b/ld/testsuite/ld-riscv-elf/table-jump-vma-zero.ld
new file mode 100644
index 00000000000..6db8ac52006
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-vma-zero.ld
@@ -0,0 +1,13 @@
+ENTRY(_start)
+SECTIONS
+{
+	.text.target 0x0 : {
+		*(.text.target)
+	}
+	.riscv.jvt 0x1000 : {
+		*(.riscv.jvt)
+	}
+	.text 0x3000 : {
+		*(.text.start)
+	}
+}
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-vma-zero.s b/ld/testsuite/ld-riscv-elf/table-jump-vma-zero.s
new file mode 100644
index 00000000000..742a0ee23fe
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-vma-zero.s
@@ -0,0 +1,14 @@
+	.section .text.start, "ax"
+
+	.globl _start
+	.type _start, %function
+_start:
+	.rept 5
+	tail target
+	.endr
+	ret
+
+	.section .text.target, "ax"
+	.type target, %function
+target:
+	ret
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-zcd-conflict.d b/ld/testsuite/ld-riscv-elf/table-jump-zcd-conflict.d
new file mode 100644
index 00000000000..ed70f3fd94e
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-zcd-conflict.d
@@ -0,0 +1,9 @@
+#source: table-jump.s
+#as: -march=rv64imafd_zicsr_zifencei_zca_zcd_zcmt --defsym TEST_CM_JT_JALT=1
+#ld: -Ttable-jump.ld --relax-zcmt
+#readelf: -SWs
+
+#failif
+#...
+.*(__jvt_base\$|\.riscv\.jvt).*
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-zcmt-no-zca.d b/ld/testsuite/ld-riscv-elf/table-jump-zcmt-no-zca.d
new file mode 100644
index 00000000000..9554df1aa91
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-zcmt-no-zca.d
@@ -0,0 +1,9 @@
+#source: table-jump-zcmt-no-zca.s
+#as: -march=rv64i -mno-arch-attr
+#ld: --relax-zcmt
+#readelf: -SWs
+
+#failif
+#...
+.*(__jvt_base\$|\.riscv\.jvt).*
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-zcmt-no-zca.s b/ld/testsuite/ld-riscv-elf/table-jump-zcmt-no-zca.s
new file mode 100644
index 00000000000..91aa8f07ed3
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-zcmt-no-zca.s
@@ -0,0 +1,24 @@
+	.section .riscv.attributes,"",@0x70000003
+	.byte 0x41
+0:
+	.4byte 1f-0b
+	.asciz "riscv"
+2:
+	.byte 1
+	.4byte 1f-2b
+	.byte 5
+	.asciz "rv64i2p1_zicsr2p0_zcmt1p0"
+1:
+
+	.section .text
+	.globl _start
+	.type _start, %function
+_start:
+	.rept 70
+	call target
+	.endr
+	ret
+
+	.type target, %function
+target:
+	ret
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-zcmt-no-zicsr.d b/ld/testsuite/ld-riscv-elf/table-jump-zcmt-no-zicsr.d
new file mode 100644
index 00000000000..981e5933097
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-zcmt-no-zicsr.d
@@ -0,0 +1,9 @@
+#source: table-jump-zcmt-no-zicsr.s
+#as: -march=rv64i -mno-arch-attr
+#ld: --relax-zcmt
+#readelf: -SWs
+
+#failif
+#...
+.*(__jvt_base\$|\.riscv\.jvt).*
+#pass
diff --git a/ld/testsuite/ld-riscv-elf/table-jump-zcmt-no-zicsr.s b/ld/testsuite/ld-riscv-elf/table-jump-zcmt-no-zicsr.s
new file mode 100644
index 00000000000..768a6fb32fa
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump-zcmt-no-zicsr.s
@@ -0,0 +1,24 @@
+	.section .riscv.attributes,"",@0x70000003
+	.byte 0x41
+0:
+	.4byte 1f-0b
+	.asciz "riscv"
+2:
+	.byte 1
+	.4byte 1f-2b
+	.byte 5
+	.asciz "rv64i2p1_zca1p0_zcmt1p0"
+1:
+
+	.section .text
+	.globl _start
+	.type _start, %function
+_start:
+	.rept 70
+	call target
+	.endr
+	ret
+
+	.type target, %function
+target:
+	ret
diff --git a/ld/testsuite/ld-riscv-elf/table-jump.ld b/ld/testsuite/ld-riscv-elf/table-jump.ld
new file mode 100644
index 00000000000..ab84fdcb772
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump.ld
@@ -0,0 +1,16 @@
+ENTRY(_start)
+SECTIONS
+{
+	.got  0x1000 : {
+		*(.got)
+	}
+	.riscv.jvt : {
+		*(.riscv.jvt)
+	}
+	.data 0x2000: {
+		*(.data)
+	}
+	.text 0x3000 : {
+		*(.text)
+	}
+}
diff --git a/ld/testsuite/ld-riscv-elf/table-jump.s b/ld/testsuite/ld-riscv-elf/table-jump.s
new file mode 100644
index 00000000000..75574a69223
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/table-jump.s
@@ -0,0 +1,46 @@
+    .section .text
+
+    .globl _start
+	.type	_start, %function
+_start:
+.ifdef TEST_CM_JT
+    .rept 5
+    tail foo_local
+    tail foo_global
+    .endr
+.endif
+
+.ifdef TEST_CM_JALT
+    .rept 70
+    call foo_global
+    call foo_local
+    .endr
+.endif
+
+.ifdef TEST_CM_JT_JALT
+    .rept 5
+    tail foo_global
+    .endr
+    .rept 140
+    call foo_global
+    .endr
+.endif
+
+	# Keep paired JAL candidates out of C.J range.  Zcmt profiling runs
+	# after ordinary shortening, so near paired JALs should become C.J
+	# and no longer be Zcmt candidates.
+.ifdef TEST_CM_JT
+    .space 4096
+.endif
+.ifdef TEST_CM_JT_JALT
+    .space 4096
+.endif
+
+    .globl  foo_global
+	.type	foo_global, %function
+foo_global:
+    ret
+
+	.type	foo_local, %function
+foo_local:
+    ret
-- 
2.43.0


From Ganesh.Gopalasubramanian@amd.com  Sat Jun 27 11:53:38 2026
From: Ganesh.Gopalasubramanian@amd.com (Ganesh Gopalasubramanian)
Date: Sat, 27 Jun 2026 17:23:38 +0530
Subject: [PATCH v1 2/2] Support x86 ACE ISA
In-Reply-To: <20260627095543.1627012-1-Ganesh.Gopalasubramanian@amd.com>
References: <20260627095543.1627012-1-Ganesh.Gopalasubramanian@amd.com>
Message-ID: <20260627115338.1632761-1-Ganesh.Gopalasubramanian@amd.com>

Adds assembler and disassembler support for ACE tile, block scale
register, outer product, and MX FP8/INT8/BF16 instructions including:
bsrinit, bsrmovf/h/l, tilemovcol, tilemovrow, top2bf16ps, top4bssd/bsud/
busd/buud, and top4mx* variants.

All ACE v1 instructions are enumerated under a single ACE feature flag
(CPUID.(EAX=07H,ECX=1):ECX[11]), matching the specification.

Key changes:
- opcodes/i386-opc.tbl: ACE instruction definitions with EVexMap6 macro
- opcodes/i386-gen.c: single ACE CPU feature and RegBS register class
- opcodes/i386-dis*.h: Disassembler dispatch tables for MAP6, 0F3A, 0F38
- gas/config/tc-i386.c: ACE operand validation with proper scoping to
  avoid interfering with AMX-AVX512 tilemovrow/tilemovcol variants
- gas/testsuite: ACE instruction test case

The generated tables (opcodes/i386-init.h, opcodes/i386-mnem.h and
opcodes/i386-tbl.h) are omitted from this mail to keep it within the
list size limit; they are regenerated from opcodes/i386-opc.tbl and
opcodes/i386-reg.tbl by i386-gen and are reflected in the diffstat.

Reference: AI Compute Extensions (ACE) Specification, v1.15
https://x86ecosystem.org/wp-content/uploads/2026/06/ACE_v1_Specification_public_1_15.pdf

gas/ChangeLog:

	* NEWS: Mention x86 ACE instruction support.
	* config/tc-i386.c (enum i386_error): Add unsupported_tile_index.
	(cpu_arch): Add ace.
	(_is_cpu): Handle CpuACE.
	(type_names): Add RegBS ("bsr") entry.
	(install_template): Handle CpuACE.
	(i386_assemble): Handle unsupported_tile_index.
	(check_ACE_operands): New function.
	(match_template): Call check_ACE_operands.
	(process_operands): Handle bsrinit like tilezero.
	(output_insn): Set GNU_PROPERTY_X86_FEATURE_2_TMM for ACE.
	(check_register): Allow TMM registers and the block scale
	register for ACE.
	* doc/c-i386.texi: Document .ace.
	* testsuite/gas/i386/x86-64.exp: Run ACE tests.
	* testsuite/gas/i386/x86-64-ace.d: New test.
	* testsuite/gas/i386/x86-64-ace-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-ace.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (OP_BSR): New function.
	(att_names_bsr): New.
	(bsr, zmm_mode): New enumerators.
	(REG_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3): New.
	(MOD_VEX_0F3849_X86_64_L_0_W_1): Ditto.
	(RM_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3_R_0): Ditto.
	(PREFIX_VEX_0F3849_X86_64_L_0_W_1_M_1): Ditto.
	(PREFIX_EVEX_0F384A, PREFIX_EVEX_0F384B, PREFIX_EVEX_0F385C): Ditto.
	(PREFIX_EVEX_0F385E, PREFIX_EVEX_0F3A07, PREFIX_EVEX_0F3A2F): Ditto.
	(PREFIX_EVEX_0F3A8D, PREFIX_EVEX_0F3A8F, PREFIX_EVEX_MAP6_95): Ditto.
	(EVEX_LEN_0F384B, EVEX_LEN_MAP6_95_P_0_W_1): Ditto.
	(EVEX_W_MAP6_95_P_0, EVEX_W_MAP6_95_P_1, EVEX_W_MAP6_95_P_3): Ditto.
	(BSR, EXzmm, Rzmm, VexGd): Define.
	(reg_table): Add REG_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3.
	(prefix_table): Add PREFIX_VEX_0F3849_X86_64_L_0_W_1_M_1.
	(vex_w_table): Add W_1 entry to VEX_W_0F3849_X86_64_L_0.
	(mod_table): Add MOD_VEX_0F3849_X86_64_L_0_W_1.
	(rm_table): Add RM_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3_R_0 (bsrinit).
	(intel_operand_size): Handle zmm_mode.
	(OP_E_memory): Handle zmm_mode.
	(print_vector_reg): Handle zmm_mode.
	(OP_VEX): Select 512-bit register names by bytemode.
	* i386-dis-evex.h: Add ACE entries to evex_table.
	* i386-dis-evex-len.h: Add EVEX_LEN_0F384B and
	EVEX_LEN_MAP6_95_P_0_W_1.
	* i386-dis-evex-prefix.h: Add PREFIX_EVEX_0F384A, PREFIX_EVEX_0F384B,
	PREFIX_EVEX_0F385C, PREFIX_EVEX_0F385E, PREFIX_EVEX_0F3A07,
	PREFIX_EVEX_0F3A2F, PREFIX_EVEX_0F3A8D, PREFIX_EVEX_0F3A8F and
	PREFIX_EVEX_MAP6_95.
	* i386-dis-evex-w.h: Add PREFIX_EVEX_0F384A and PREFIX_EVEX_0F3A07
	entries; add EVEX_W_MAP6_95_P_0, EVEX_W_MAP6_95_P_1 and
	EVEX_W_MAP6_95_P_3.
	* i386-gen.c (isa_dependencies): Add ACE.
	(cpu_flags): Add ACE.
	(operand_classes): Add RegBS.
	* i386-opc.h (CpuACE): New.
	(i386_cpu): Add cpuace.
	(operand_class): Add RegBS.
	* i386-opc.tbl: Add RegBS and EVexMap6 macros.  Add ACE
	instructions and enable the AMX tile, tcvtrow* and tilemovrow
	insns for ACE.
	* i386-reg.tbl: Add bsr0 block scale register.
	* i386-init.h: Regenerated.
	* i386-mnem.h: Ditto.
	* i386-tbl.h: Ditto.

Co-authored-by: Umesh Kalvakuntla
---
 gas/NEWS                                  |     4 +
 gas/config/tc-i386.c                      |    52 +-
 gas/doc/c-i386.texi                       |     3 +-
 gas/testsuite/gas/i386/x86-64-ace-intel.d |    43 +
 gas/testsuite/gas/i386/x86-64-ace.d       |    43 +
 gas/testsuite/gas/i386/x86-64-ace.s       |    45 +
 gas/testsuite/gas/i386/x86-64.exp         |     2 +
 opcodes/i386-dis-evex-len.h               |    13 +
 opcodes/i386-dis-evex-prefix.h            |    57 +
 opcodes/i386-dis-evex-w.h                 |    19 +-
 opcodes/i386-dis-evex.h                   |    14 +-
 opcodes/i386-dis.c                        |   115 +-
 opcodes/i386-gen.c                        |     4 +
 opcodes/i386-init.h                       |   608 +-
 opcodes/i386-mnem.h                       |  3093 ++--
 opcodes/i386-opc.h                        |     4 +
 opcodes/i386-opc.tbl                      |    68 +-
 opcodes/i386-reg.tbl                      |     4 +-
 opcodes/i386-tbl.h                        | 18961 ++++++++++----------
 19 files changed, 11964 insertions(+), 11188 deletions(-)
 create mode 100644 gas/testsuite/gas/i386/x86-64-ace-intel.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-ace.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-ace.s

diff --git a/gas/NEWS b/gas/NEWS
index ef4bd048e4b..a02f11a46ed 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,9 @@
 -*- text -*-
 
+* Add support for the x86 ACE (AI Compute Extensions) instructions,
+  including tile data movement, block scale register operations and tile
+  outer products.
+
 * Add support for the x86 AVX10_V2_AUX instructions, providing FP8, FP4
   and FP6 format conversion instructions.
 
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index d82ed061a78..f6f40589d11 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -272,6 +272,7 @@ enum i386_error
     unsupported_rc_sae,
     unsupported_vector_size,
     unsupported_rsp_register,
+    unsupported_tile_index,
     internal_error,
   };
 
@@ -1200,6 +1201,7 @@ static const arch_entry cpu_arch[] =
   SUBARCH (pconfig, PCONFIG, PCONFIG, false),
   SUBARCH (waitpkg, WAITPKG, WAITPKG, false),
   SUBARCH (cldemote, CLDEMOTE, CLDEMOTE, false),
+  SUBARCH (ace, ACE, ACE, false),
   SUBARCH (amx_int8, AMX_INT8, ANY_AMX_INT8, false),
   SUBARCH (amx_bf16, AMX_BF16, ANY_AMX_BF16, false),
   SUBARCH (amx_fp16, AMX_FP16, ANY_AMX_FP16, false),
@@ -1894,6 +1896,7 @@ _is_cpu (const i386_cpu_attr *a, enum i386_cpu cpu)
     case CpuAPX_F:    return a->bitfield.cpuapx_f;
     case CpuAVX10_2:  return a->bitfield.cpuavx10_2;
     case CpuAMX_TRANSPOSE:  return a->bitfield.cpuamx_transpose;
+    case CpuACE:      return a->bitfield.cpuace;
     case Cpu64:       return a->bitfield.cpu64;
     case CpuNo64:     return a->bitfield.cpuno64;
     default:
@@ -3933,6 +3936,7 @@ const type_names[] =
   { { .bitfield = { .class = RegSIMD, .zmmword = 1 } }, "rZMM" },
   { { .bitfield = { .class = RegSIMD, .tmmword = 1 } }, "rTMM" },
   { { .bitfield = { .class = RegMask } }, "Mask reg" },
+  { { .bitfield = { .class = RegBS } }, "bsr" },
 };
 
 static void
@@ -4253,6 +4257,7 @@ install_template (const insn_template *t)
 	}
 
       if ((maybe_cpu (t, CpuCMPCCXADD) || maybe_cpu (t, CpuAMX_TILE)
+	   || maybe_cpu (t, CpuACE)
 	   || maybe_cpu (t, CpuAVX512F) || maybe_cpu (t, CpuAVX512DQ)
 	   || maybe_cpu (t, CpuAVX512BW) || maybe_cpu (t, CpuBMI)
 	   || maybe_cpu (t, CpuBMI2) || maybe_cpu (t, CpuUSER_MSR)
@@ -7498,6 +7503,9 @@ i386_assemble (char *line)
 	case unsupported_rsp_register:
 	  err_msg = _("'rsp' register cannot be used");
 	  break;
+	case unsupported_tile_index:
+	  err_msg = _("immediate value must be in range 0-15");
+	  break;
 	case internal_error:
 	  err_msg = _("internal error");
 	  break;
@@ -9323,6 +9331,29 @@ check_APX_operands (const insn_template *t)
   return 0;
 }
 
+/* Check if ACE operands are valid for the instruction.  */
+static bool
+check_ACE_operands (const insn_template *t)
+{
+  switch (t->mnem_off)
+    {
+    case MN_tilemovrow:
+    case MN_tilemovcol:
+      if (is_cpu (t, CpuACE)
+	  && i.op[0].imms && i.op[0].imms->X_op == O_constant)
+	{
+	  offsetT val = i.op[0].imms->X_add_number;
+	  if (val < 0 || val > 15)
+	    {
+	      i.error = unsupported_tile_index;
+	      return 1;
+	    }
+	}
+      break;
+    }
+  return 0;
+}
+
 /* Check if the instruction use the REX registers or REX prefix.  */
 static bool
 check_Rex_required (void)
@@ -9905,6 +9936,13 @@ match_template (char mnem_suffix)
 	  continue;
 	}
 
+      /* Check if ACE operands are valid.  */
+      if (check_ACE_operands (t))
+	{
+	  specific_error = progress (i.error);
+	  continue;
+	}
+
       /* Check whether to use the shorter VEX encoding for certain insns where
 	 the EVEX encoding comes first in the table.  This requires the respective
 	 AVX-* feature to be explicitly enabled.
@@ -10994,7 +11032,7 @@ process_operands (void)
      not ModR/M.rm.  To avoid special casing this in build_modrm_byte(), fake a
      new destination operand here, while converting the source one to register
      number 0.  */
-  if (i.tm.mnem_off == MN_tilezero)
+  if (i.tm.mnem_off == MN_tilezero || i.tm.mnem_off == MN_bsrinit)
     {
       copy_operand (1, 0);
       i.op[0].regs -= i.op[0].regs->reg_num;
@@ -12475,7 +12513,8 @@ output_insn (const struct last_insn *last_insn)
       unsigned int feature_2_used = 0;
 
       if ((i.xstate & xstate_tmm) == xstate_tmm
-	  || is_cpu (&i.tm, CpuAMX_TILE))
+	  || is_cpu (&i.tm, CpuAMX_TILE)
+	  || is_cpu (&i.tm, CpuACE))
 	feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_TMM;
 
       if (is_cpu (&i.tm, Cpu8087)
@@ -16943,13 +16982,18 @@ static bool check_register (const reg_entry *r)
     return false;
 
   if (r->reg_type.bitfield.tmmword
-      && (!cpu_arch_flags.bitfield.cpuamx_tile
-          || flag_code != CODE_64BIT))
+      && ((!cpu_arch_flags.bitfield.cpuamx_tile
+	   && !cpu_arch_flags.bitfield.cpuace)
+	  || flag_code != CODE_64BIT))
     return false;
 
   if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx)
     return false;
 
+  if (r->reg_type.bitfield.class == RegBS
+      && !cpu_arch_flags.bitfield.cpuace)
+    return false;
+
   /* Don't allow fake index register unless allow_index_reg isn't 0. */
   if (!allow_index_reg && r->reg_num == RegIZ)
     return false;
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 9f6e8da443d..5d1e15816af 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -242,6 +242,7 @@ accept various extension mnemonics.  For example,
 @code{amx_movrs},
 @code{amx_avx512},
 @code{amx_tile},
+@code{ace},
 @code{vmx},
 @code{vmfunc},
 @code{smx},
@@ -1731,7 +1732,7 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.amx_int8} @tab @samp{.amx_bf16} @tab @samp{.amx_fp16}
 @item @samp{.amx_complex} @tab @samp{.amx_transpose} @tab @samp{.amx_tf32}
 @item @samp{.amx_fp8} @tab @samp{.amx_movrs} @tab @samp{.amx_avx512}
-@item @samp{.amx_tile}
+@item @samp{.amx_tile} @tab @samp{.ace}
 @item @samp{.kl} @tab @samp{.widekl} @tab @samp{.uintr} @tab @samp{.hreset}
 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme}
diff --git a/gas/testsuite/gas/i386/x86-64-ace-intel.d b/gas/testsuite/gas/i386/x86-64-ace-intel.d
new file mode 100644
index 00000000000..b116845d240
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-ace-intel.d
@@ -0,0 +1,43 @@
+#objdump: -dw -Mintel
+#name: 64-bit ACE insns (Intel disassembly)
+#source: x86-64-ace.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <start>:
+[\s]*[a-f0-9]+:[\s]*c4 e2 fb 49 c0[\s]*bsrinit bsr0
+[\s]*[a-f0-9]+:[\s]*62 f6 f4 48 95 c3[\s]*bsrmovf bsr0,zmm1,zmm3
+[\s]*[a-f0-9]+:[\s]*62 d6 ff 48 95 c2[\s]*bsrmovh bsr0,zmm10
+[\s]*[a-f0-9]+:[\s]*62 d6 fe 48 95 c2[\s]*bsrmovl bsr0,zmm10
+[\s]*[a-f0-9]+:[\s]*67 62 f6 ff 48 95 00[\s]*bsrmovh bsr0,ZMMWORD PTR \[eax\]
+[\s]*[a-f0-9]+:[\s]*67 62 f6 fe 48 95 00[\s]*bsrmovl bsr0,ZMMWORD PTR \[eax\]
+[\s]*[a-f0-9]+:[\s]*62 f6 7f 48 95 c4[\s]*bsrmovh zmm4,bsr0
+[\s]*[a-f0-9]+:[\s]*62 f6 7e 48 95 c4[\s]*bsrmovl zmm4,bsr0
+[\s]*[a-f0-9]+:[\s]*67 62 f6 7f 48 95 00[\s]*bsrmovh ZMMWORD PTR \[eax\],bsr0
+[\s]*[a-f0-9]+:[\s]*67 62 f6 7e 48 95 00[\s]*bsrmovl ZMMWORD PTR \[eax\],bsr0
+[\s]*[a-f0-9]+:[\s]*62 f3 fd 48 2f ca 08[\s]*tilemovcol tmm1,zmm2,0x8
+[\s]*[a-f0-9]+:[\s]*62 f3 fd 48 07 ca 08[\s]*tilemovrow tmm1,zmm2,0x8
+[\s]*[a-f0-9]+:[\s]*62 f2 e5 48 4b ca[\s]*tilemovcol tmm1,zmm2,ebx
+[\s]*[a-f0-9]+:[\s]*62 f2 e5 48 4a ca[\s]*tilemovrow tmm1,zmm2,ebx
+[\s]*[a-f0-9]+:[\s]*62 f2 6e 48 5c c1[\s]*top2bf16ps tmm0,zmm1,zmm2
+[\s]*[a-f0-9]+:[\s]*62 f2 6f 48 5e c1[\s]*top4bssd tmm0,zmm1,zmm2
+[\s]*[a-f0-9]+:[\s]*62 f2 6e 48 5e c1[\s]*top4bsud tmm0,zmm1,zmm2
+[\s]*[a-f0-9]+:[\s]*62 f2 6d 48 5e c1[\s]*top4busd tmm0,zmm1,zmm2
+[\s]*[a-f0-9]+:[\s]*62 f2 6c 48 5e c1[\s]*top4buud tmm0,zmm1,zmm2
+[\s]*[a-f0-9]+:[\s]*62 f3 6c 48 8d c9 07[\s]*top4mxbf8ps tmm1,zmm1,zmm2,0x7
+[\s]*[a-f0-9]+:[\s]*62 f3 6f 48 8d c9 07[\s]*top4mxbhf8ps tmm1,zmm1,zmm2,0x7
+[\s]*[a-f0-9]+:[\s]*62 f3 6e 48 8d c9 07[\s]*top4mxhbf8ps tmm1,zmm1,zmm2,0x7
+[\s]*[a-f0-9]+:[\s]*62 f3 6d 48 8d c9 07[\s]*top4mxhf8ps tmm1,zmm1,zmm2,0x7
+[\s]*[a-f0-9]+:[\s]*62 f3 6f 48 8f c9 07[\s]*top4mxbssps tmm1,zmm1,zmm2,0x7
+[\s]*[a-f0-9]+:[\s]*62 62 6e 48 4a f5[\s]*tcvtrowd2ps zmm30,tmm5,edx
+[\s]*[a-f0-9]+:[\s]*62 63 7e 48 07 f5 7b[\s]*tcvtrowd2ps zmm30,tmm5,0x7b
+[\s]*[a-f0-9]+:[\s]*62 62 6f 48 6d f5[\s]*tcvtrowps2bf16h zmm30,tmm5,edx
+[\s]*[a-f0-9]+:[\s]*62 63 7f 48 07 f5 7b[\s]*tcvtrowps2bf16h zmm30,tmm5,0x7b
+[\s]*[a-f0-9]+:[\s]*62 62 6e 48 6d f5[\s]*tcvtrowps2bf16l zmm30,tmm5,edx
+[\s]*[a-f0-9]+:[\s]*62 63 7e 48 77 f5 7b[\s]*tcvtrowps2bf16l zmm30,tmm5,0x7b
+[\s]*[a-f0-9]+:[\s]*62 62 6c 48 6d f5[\s]*tcvtrowps2phh zmm30,tmm5,edx
+[\s]*[a-f0-9]+:[\s]*62 63 7c 48 07 f5 7b[\s]*tcvtrowps2phh zmm30,tmm5,0x7b
+[\s]*[a-f0-9]+:[\s]*62 62 6d 48 6d f5[\s]*tcvtrowps2phl zmm30,tmm5,edx
+[\s]*[a-f0-9]+:[\s]*62 63 7f 48 77 f5 7b[\s]*tcvtrowps2phl zmm30,tmm5,0x7b
diff --git a/gas/testsuite/gas/i386/x86-64-ace.d b/gas/testsuite/gas/i386/x86-64-ace.d
new file mode 100644
index 00000000000..cc91aa7fede
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-ace.d
@@ -0,0 +1,43 @@
+#objdump: -dw
+#name: 64-bit ACE insns
+#source: x86-64-ace.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <start>:
+[\s]*[a-f0-9]+:[\s]*c4 e2 fb 49 c0[\s]*bsrinit %bsr0
+[\s]*[a-f0-9]+:[\s]*62 f6 f4 48 95 c3[\s]*bsrmovf %zmm3,%zmm1,%bsr0
+[\s]*[a-f0-9]+:[\s]*62 d6 ff 48 95 c2[\s]*bsrmovh %zmm10,%bsr0
+[\s]*[a-f0-9]+:[\s]*62 d6 fe 48 95 c2[\s]*bsrmovl %zmm10,%bsr0
+[\s]*[a-f0-9]+:[\s]*67 62 f6 ff 48 95 00[\s]*bsrmovh \(%eax\),%bsr0
+[\s]*[a-f0-9]+:[\s]*67 62 f6 fe 48 95 00[\s]*bsrmovl \(%eax\),%bsr0
+[\s]*[a-f0-9]+:[\s]*62 f6 7f 48 95 c4[\s]*bsrmovh %bsr0,%zmm4
+[\s]*[a-f0-9]+:[\s]*62 f6 7e 48 95 c4[\s]*bsrmovl %bsr0,%zmm4
+[\s]*[a-f0-9]+:[\s]*67 62 f6 7f 48 95 00[\s]*bsrmovh %bsr0,\(%eax\)
+[\s]*[a-f0-9]+:[\s]*67 62 f6 7e 48 95 00[\s]*bsrmovl %bsr0,\(%eax\)
+[\s]*[a-f0-9]+:[\s]*62 f3 fd 48 2f ca 08[\s]*tilemovcol \$0x8,%zmm2,%tmm1
+[\s]*[a-f0-9]+:[\s]*62 f3 fd 48 07 ca 08[\s]*tilemovrow \$0x8,%zmm2,%tmm1
+[\s]*[a-f0-9]+:[\s]*62 f2 e5 48 4b ca[\s]*tilemovcol %ebx,%zmm2,%tmm1
+[\s]*[a-f0-9]+:[\s]*62 f2 e5 48 4a ca[\s]*tilemovrow %ebx,%zmm2,%tmm1
+[\s]*[a-f0-9]+:[\s]*62 f2 6e 48 5c c1[\s]*top2bf16ps %zmm2,%zmm1,%tmm0
+[\s]*[a-f0-9]+:[\s]*62 f2 6f 48 5e c1[\s]*top4bssd %zmm2,%zmm1,%tmm0
+[\s]*[a-f0-9]+:[\s]*62 f2 6e 48 5e c1[\s]*top4bsud %zmm2,%zmm1,%tmm0
+[\s]*[a-f0-9]+:[\s]*62 f2 6d 48 5e c1[\s]*top4busd %zmm2,%zmm1,%tmm0
+[\s]*[a-f0-9]+:[\s]*62 f2 6c 48 5e c1[\s]*top4buud %zmm2,%zmm1,%tmm0
+[\s]*[a-f0-9]+:[\s]*62 f3 6c 48 8d c9 07[\s]*top4mxbf8ps \$0x7,%zmm2,%zmm1,%tmm1
+[\s]*[a-f0-9]+:[\s]*62 f3 6f 48 8d c9 07[\s]*top4mxbhf8ps \$0x7,%zmm2,%zmm1,%tmm1
+[\s]*[a-f0-9]+:[\s]*62 f3 6e 48 8d c9 07[\s]*top4mxhbf8ps \$0x7,%zmm2,%zmm1,%tmm1
+[\s]*[a-f0-9]+:[\s]*62 f3 6d 48 8d c9 07[\s]*top4mxhf8ps \$0x7,%zmm2,%zmm1,%tmm1
+[\s]*[a-f0-9]+:[\s]*62 f3 6f 48 8f c9 07[\s]*top4mxbssps \$0x7,%zmm2,%zmm1,%tmm1
+[\s]*[a-f0-9]+:[\s]*62 62 6e 48 4a f5[\s]*tcvtrowd2ps %edx,%tmm5,%zmm30
+[\s]*[a-f0-9]+:[\s]*62 63 7e 48 07 f5 7b[\s]*tcvtrowd2ps \$0x7b,%tmm5,%zmm30
+[\s]*[a-f0-9]+:[\s]*62 62 6f 48 6d f5[\s]*tcvtrowps2bf16h %edx,%tmm5,%zmm30
+[\s]*[a-f0-9]+:[\s]*62 63 7f 48 07 f5 7b[\s]*tcvtrowps2bf16h \$0x7b,%tmm5,%zmm30
+[\s]*[a-f0-9]+:[\s]*62 62 6e 48 6d f5[\s]*tcvtrowps2bf16l %edx,%tmm5,%zmm30
+[\s]*[a-f0-9]+:[\s]*62 63 7e 48 77 f5 7b[\s]*tcvtrowps2bf16l \$0x7b,%tmm5,%zmm30
+[\s]*[a-f0-9]+:[\s]*62 62 6c 48 6d f5[\s]*tcvtrowps2phh %edx,%tmm5,%zmm30
+[\s]*[a-f0-9]+:[\s]*62 63 7c 48 07 f5 7b[\s]*tcvtrowps2phh \$0x7b,%tmm5,%zmm30
+[\s]*[a-f0-9]+:[\s]*62 62 6d 48 6d f5[\s]*tcvtrowps2phl %edx,%tmm5,%zmm30
+[\s]*[a-f0-9]+:[\s]*62 63 7f 48 77 f5 7b[\s]*tcvtrowps2phl \$0x7b,%tmm5,%zmm30
diff --git a/gas/testsuite/gas/i386/x86-64-ace.s b/gas/testsuite/gas/i386/x86-64-ace.s
new file mode 100644
index 00000000000..9c7bf8a2214
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-ace.s
@@ -0,0 +1,45 @@
+# Check 64-bit ACE instructions
+
+	.text
+start:
+	bsrinit %bsr0
+	bsrmovf %zmm3, %zmm1, %bsr0
+
+	bsrmovh %zmm10, %bsr0
+	bsrmovl %zmm10, %bsr0
+	bsrmovh (%eax), %bsr0
+	bsrmovl (%eax), %bsr0
+
+	bsrmovh %bsr0, %zmm4
+	bsrmovl %bsr0, %zmm4
+	bsrmovh %bsr0, (%eax)
+	bsrmovl %bsr0, (%eax)
+
+	tilemovcol $8, %zmm2, %tmm1
+	tilemovrow $8, %zmm2, %tmm1
+
+	tilemovcol %ebx, %zmm2, %tmm1
+	tilemovrow %ebx, %zmm2, %tmm1
+
+	top2bf16ps %zmm2, %zmm1, %tmm0
+	top4bssd   %zmm2, %zmm1, %tmm0
+	top4bsud   %zmm2, %zmm1, %tmm0
+	top4busd   %zmm2, %zmm1, %tmm0
+	top4buud   %zmm2, %zmm1, %tmm0
+
+	top4mxbf8ps  $7, %zmm2, %zmm1, %tmm1
+	top4mxbhf8ps $7, %zmm2, %zmm1, %tmm1
+	top4mxhbf8ps $7, %zmm2, %zmm1, %tmm1
+	top4mxhf8ps  $7, %zmm2, %zmm1, %tmm1
+	top4mxbssps  $7, %zmm2, %zmm1, %tmm1
+
+	tcvtrowd2ps     %edx, %tmm5, %zmm30
+	tcvtrowd2ps     $0x7b, %tmm5, %zmm30
+	tcvtrowps2bf16h %edx, %tmm5, %zmm30
+	tcvtrowps2bf16h $0x7b, %tmm5, %zmm30
+	tcvtrowps2bf16l %edx, %tmm5, %zmm30
+	tcvtrowps2bf16l $0x7b, %tmm5, %zmm30
+	tcvtrowps2phh   %edx, %tmm5, %zmm30
+	tcvtrowps2phh   $0x7b, %tmm5, %zmm30
+	tcvtrowps2phl   %edx, %tmm5, %zmm30
+	tcvtrowps2phl   $0x7b, %tmm5, %zmm30
diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp
index d0d3cb47117..ae5d8bff1ba 100644
--- a/gas/testsuite/gas/i386/x86-64.exp
+++ b/gas/testsuite/gas/i386/x86-64.exp
@@ -689,6 +689,8 @@ run_list_test "x86-64-amx-inval"
 run_dump_test "x86-64-amx"
 run_dump_test "x86-64-amx-intel"
 run_dump_test "x86-64-amx-bad"
+run_dump_test "x86-64-ace"
+run_dump_test "x86-64-ace-intel"
 
 if { ![istarget "*-*-aix*"]
      && ![istarget "*-*-beos*"]
diff --git a/opcodes/i386-dis-evex-len.h b/opcodes/i386-dis-evex-len.h
index 370710915de..273c6d40d12 100644
--- a/opcodes/i386-dis-evex-len.h
+++ b/opcodes/i386-dis-evex-len.h
@@ -51,6 +51,13 @@ static const struct dis386 evex_len_table[][3] = {
     { PREFIX_TABLE (PREFIX_EVEX_0F384A_X86_64_W_0_L_2) },
   },
 
+  /* EVEX_LEN_0F384B */
+  {
+    { X86_64_EVEX_W_TABLE (VEX_W_0F384B_X86_64_L_0) },
+    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_EVEX_0F384B) },
+  },
+
   /* EVEX_LEN_0F385A */
   {
     { Bad_Opcode },
@@ -207,4 +214,10 @@ static const struct dis386 evex_len_table[][3] = {
     { "vbmacxor16x16x16", { XM, Vex, EXx }, NO_PREFIX },
     { "vbmacxor16x16x16", { XM, Vex, EXx }, NO_PREFIX },
   },
+  /* EVEX_LEN_MAP6_95_P_0_W_1 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "bsrmovf", { BSR, Vex, EXx }, 0 },
+  },
 };
diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h
index ffecef5e796..f3b031470df 100644
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -254,6 +254,18 @@
     { "tcvtrowd2ps",	{ XM, Rtmm, VexGdq }, 0 },
     { "tilemovrow",	{ XM, Rtmm, VexGdq }, 0 },
   },
+  /* PREFIX_EVEX_0F384A */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "tilemovrow",	{ TMM, Rzmm, VexGd }, 0 },
+  },
+  /* PREFIX_EVEX_0F384B */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "tilemovcol",	{ TMM, Rzmm, VexGd }, 0 },
+  },
   /* PREFIX_EVEX_0F3852 */
   {
     { "vdpphp%XS",	{ XM, Vex, EXx }, 0 },
@@ -268,6 +280,18 @@
     { VEX_W_TABLE (VEX_W_0F3853) },
     { "vp4dpws%XSds",	{ XM, Vex, Mxmm }, 0 },
   },
+  /* PREFIX_EVEX_0F385C */
+  {
+    { Bad_Opcode },
+    { "top2bf16ps",	{ TMM, Rzmm, Vex }, 0 },
+  },
+  /* PREFIX_EVEX_0F385E */
+  {
+    { "top4buud",	{ TMM, Rzmm, Vex }, 0 },
+    { "top4bsud",	{ TMM, Rzmm, Vex }, 0 },
+    { "top4busd",	{ TMM, Rzmm, Vex }, 0 },
+    { "top4bssd",	{ TMM, Rzmm, Vex }, 0 },
+  },
   /* PREFIX_EVEX_0F3868 */
   {
     { Bad_Opcode },
@@ -331,6 +355,12 @@
     { "tilemovrow",	{ XM, Rtmm, Ib }, 0 },
     { "tcvtrowps2bf16h",	{ XM, Rtmm, Ib }, 0 },
   },
+  /* PREFIX_EVEX_0F3A07 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "tilemovrow", { TMM, Rzmm, Ib }, 0 },
+  },
   /* PREFIX_EVEX_0F3A08 */
   {
     { "vrndscalep%XH",  { XM, EXxh, EXxEVexS, Ib }, 0 },
@@ -357,6 +387,12 @@
     { Bad_Opcode },
     { "vgetmants%XW",	{ XMScalar, VexScalar, EXdq, EXxEVexS, Ib }, 0 },
   },
+  /* PREFIX_EVEX_0F3A2F */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "tilemovcol", { TMM, Rzmm, Ib }, 0 },
+  },
   /* PREFIX_EVEX_0F3A42_W_0 */
   {
     { Bad_Opcode },
@@ -409,6 +445,20 @@
     { Bad_Opcode },
     { "tcvtrowps2phl",	{ XM, Rtmm, Ib }, 0 },
   },
+  /* PREFIX_EVEX_0F3A8D */
+  {
+    { "top4mxbf8ps",	{ TMM, Rzmm, Vex, Ib }, 0 },
+    { "top4mxhbf8ps",	{ TMM, Rzmm, Vex, Ib }, 0 },
+    { "top4mxhf8ps",	{ TMM, Rzmm, Vex, Ib }, 0 },
+    { "top4mxbhf8ps",	{ TMM, Rzmm, Vex, Ib }, 0 },
+  },
+  /* PREFIX_EVEX_0F3A8F */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "top4mxbssps",	{ TMM, Rzmm, Vex, Ib }, 0 },
+  },
   /* PREFIX_EVEX_0F3AC2 */
   {
     { "vcmpp%XH", { MaskG, Vex, EXxh, EXxEVexS, CMP }, 0 },
@@ -833,6 +883,13 @@
     { Bad_Opcode },
     { "vfnmsub231p%XH",	{ XM, Vex, EXxh, EXxEVexR }, 0 },
   },
+  /* PREFIX_EVEX_MAP6_95 */
+  {
+    { VEX_W_TABLE (EVEX_W_MAP6_95_P_0) },
+    { VEX_W_TABLE (EVEX_W_MAP6_95_P_1) },
+    { Bad_Opcode },
+    { VEX_W_TABLE (EVEX_W_MAP6_95_P_3) },
+  },
   /* PREFIX_EVEX_MAP6_D6 */
   {
     { Bad_Opcode },
diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h
index 6e94bc45fe1..8e0529e1a08 100644
--- a/opcodes/i386-dis-evex-w.h
+++ b/opcodes/i386-dis-evex-w.h
@@ -349,6 +349,7 @@
   /* EVEX_W_0F384A_X86_64 */
   {
     { EVEX_LEN_TABLE (EVEX_LEN_0F384A_X86_64_W_0) },
+    { PREFIX_TABLE (PREFIX_EVEX_0F384A) },
   },
   /* EVEX_W_0F3859 */
   {
@@ -395,6 +396,7 @@
   /* EVEX_W_0F3A07_X86_64 */
   {
     { EVEX_LEN_TABLE (EVEX_LEN_0F3A07_X86_64_W_0) },
+    { PREFIX_TABLE (PREFIX_EVEX_0F3A07) },
   },
   /* EVEX_W_0F3A18_L_n */
   {
@@ -553,4 +555,19 @@
   {
     { "vbitrevb", { XM, EXx }, NO_PREFIX },
     { Bad_Opcode }
-  }
+  },
+  /* EVEX_W_MAP6_95_P_0 */
+  {
+    { Bad_Opcode },
+    { EVEX_LEN_TABLE (EVEX_LEN_MAP6_95_P_0_W_1) },
+  },
+  /* EVEX_W_MAP6_95_P_1 */
+  {
+    { "bsrmovl", { EXzmm, BSR }, 0 },
+    { "bsrmovl", { BSR, EXzmm }, 0 },
+  },
+  /* EVEX_W_MAP6_95_P_3 */
+  {
+    { "bsrmovh", { EXzmm, BSR }, 0 },
+    { "bsrmovh", { BSR, EXzmm }, 0 },
+  },
diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
index 7d555aa9e11..9ad57912231 100644
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -377,7 +377,7 @@ static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { X86_64_EVEX_MEM_W_TABLE (VEX_W_0F3849_X86_64_L_0) },
     { X86_64_TABLE (X86_64_EVEX_0F384A) },
-    { X86_64_EVEX_MEM_W_TABLE (VEX_W_0F384B_X86_64_L_0) },
+    { EVEX_LEN_TABLE (EVEX_LEN_0F384B) },
     { "vrcp14p%XW",	{ XM, EXx }, PREFIX_DATA },
     { "vrcp14s%XW",	{ XMScalar, VexScalar, EXdq }, PREFIX_DATA },
     { "vrsqrt14p%XW",	{ XM, EXx }, 0 },
@@ -396,9 +396,9 @@ static const struct dis386 evex_table[][256] = {
     { VEX_W_TABLE (EVEX_W_0F3859) },
     { EVEX_LEN_TABLE (EVEX_LEN_0F385A) },
     { EVEX_LEN_TABLE (EVEX_LEN_0F385B) },
+    { PREFIX_TABLE (PREFIX_EVEX_0F385C) },
     { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_EVEX_0F385E) },
     { Bad_Opcode },
     /* 60 */
     { Bad_Opcode },
@@ -636,7 +636,7 @@ static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_EVEX_0F3A2F) },
     /* 30 */
     { Bad_Opcode },
     { Bad_Opcode },
@@ -742,9 +742,9 @@ static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_EVEX_0F3A8D) },
     { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_EVEX_0F3A8F) },
     /* 90 */
     { Bad_Opcode },
     { Bad_Opcode },
@@ -1624,7 +1624,7 @@ static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_EVEX_MAP6_95) },
     { "vfmaddsub132p%XH",  { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
     { "vfmsubadd132p%XH",  { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
     /* 98 */
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 5643cfe55d5..f39774f2a83 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -70,6 +70,7 @@ static bool OP_D (instr_info *, int, int);
 static bool OP_T (instr_info *, int, int);
 static bool OP_MMX (instr_info *, int, int);
 static bool OP_XMM (instr_info *, int, int);
+static bool OP_BSR (instr_info *, int, int);
 static bool OP_EM (instr_info *, int, int);
 static bool OP_EX (instr_info *, int, int);
 static bool OP_EMC (instr_info *, int,int);
@@ -513,6 +514,7 @@ fetch_error (const instr_info *ins)
 #define RMBH { OP_REG, bh_reg }
 #define RMAX { OP_REG, ax_reg }
 #define RMDX { OP_REG, dx_reg }
+#define BSR { OP_BSR, bsr }
 
 #define eAX { OP_IMREG, eAX_reg }
 #define AL { OP_IMREG, al_reg }
@@ -566,6 +568,7 @@ fetch_error (const instr_info *ins)
 #define EXxS { OP_EX, x_swap_mode }
 #define EXxmm { OP_EX, xmm_mode }
 #define EXymm { OP_EX, ymm_mode }
+#define EXzmm { OP_EX, zmm_mode }
 #define EXxmmq { OP_EX, xmmq_mode }
 #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
@@ -583,6 +586,7 @@ fetch_error (const instr_info *ins)
 #define Uxmm { OP_R, xmm_mode }
 #define Rxmmq { OP_R, xmmq_mode }
 #define Rymm { OP_R, ymm_mode }
+#define Rzmm { OP_R, zmm_mode }
 #define Rtmm { OP_R, tmm_mode }
 #define EMCq { OP_EMC, q_mode }
 #define MXC { OP_MXC, 0 }
@@ -600,6 +604,7 @@ fetch_error (const instr_info *ins)
 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 #define VexGdq { OP_VEX, dq_mode }
 #define VexGb { OP_VEX, b_mode }
+#define VexGd { OP_VEX, d_mode }
 #define VexGv { OP_VEX, v_mode }
 #define VexTmm { OP_VEX, tmm_mode }
 #define XMVexI4 { OP_REG_VexI4, x_mode }
@@ -720,6 +725,8 @@ enum
   ymm_mode,
   /* quad word, ymmword or zmmword memory operand.  */
   ymmq_mode,
+  /* 64-byte ZMM operand */
+  zmm_mode,
   /* TMM operand */
   tmm_mode,
   /* d_mode in 32bit, q_mode in 64bit mode.  */
@@ -821,6 +828,8 @@ enum
   rSI_reg,
   rDI_reg,
 
+  bsr,
+
   z_mode_ax_reg,
   indir_dx_reg
 };
@@ -908,6 +917,7 @@ enum
   REG_VEX_0F73,
   REG_VEX_0FAE,
   REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0,
+  REG_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3,
   REG_VEX_0F38F3_L_0_P_0,
   REG_VEX_MAP7_F6_L_0_W_0,
   REG_VEX_MAP7_F8_L_0_W_0,
@@ -971,6 +981,7 @@ enum
   MOD_0F38F8,
 
   MOD_VEX_0F3849_X86_64_L_0_W_0,
+  MOD_VEX_0F3849_X86_64_L_0_W_1,
 
   MOD_EVEX_MAP4_60,
   MOD_EVEX_MAP4_61,
@@ -995,6 +1006,7 @@ enum
 
   RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0,
   RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3,
+  RM_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3_R_0,
 };
 
 enum
@@ -1141,6 +1153,7 @@ enum
   PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0,
   PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1,
   PREFIX_VEX_0F384A_X86_64_W_0_L_0,
+  PREFIX_VEX_0F3849_X86_64_L_0_W_1_M_1,
   PREFIX_VEX_0F384B_X86_64_L_0_W_0,
   PREFIX_VEX_0F3850_W_0,
   PREFIX_VEX_0F3851_W_0,
@@ -1213,8 +1226,12 @@ enum
   PREFIX_EVEX_0F383A,
   PREFIX_EVEX_0F3841,
   PREFIX_EVEX_0F384A_X86_64_W_0_L_2,
+  PREFIX_EVEX_0F384A,
+  PREFIX_EVEX_0F384B,
   PREFIX_EVEX_0F3852,
   PREFIX_EVEX_0F3853,
+  PREFIX_EVEX_0F385C,
+  PREFIX_EVEX_0F385E,
   PREFIX_EVEX_0F3868,
   PREFIX_EVEX_0F386D_X86_64_W_0_L_2,
   PREFIX_EVEX_0F3872,
@@ -1225,10 +1242,12 @@ enum
   PREFIX_EVEX_0F38AB,
 
   PREFIX_EVEX_0F3A07_X86_64_W_0_L_2,
+  PREFIX_EVEX_0F3A07,
   PREFIX_EVEX_0F3A08,
   PREFIX_EVEX_0F3A0A,
   PREFIX_EVEX_0F3A26,
   PREFIX_EVEX_0F3A27,
+  PREFIX_EVEX_0F3A2F,
   PREFIX_EVEX_0F3A42_W_0,
   PREFIX_EVEX_0F3A52,
   PREFIX_EVEX_0F3A53,
@@ -1237,6 +1256,8 @@ enum
   PREFIX_EVEX_0F3A66,
   PREFIX_EVEX_0F3A67,
   PREFIX_EVEX_0F3A77_X86_64_W_0_L_2,
+  PREFIX_EVEX_0F3A8D,
+  PREFIX_EVEX_0F3A8F,
   PREFIX_EVEX_0F3AC2,
 
   PREFIX_EVEX_MAP4_4x,
@@ -1310,6 +1331,7 @@ enum
   PREFIX_EVEX_MAP6_BA,
   PREFIX_EVEX_MAP6_BC,
   PREFIX_EVEX_MAP6_BE,
+  PREFIX_EVEX_MAP6_95,
   PREFIX_EVEX_MAP6_D6,
   PREFIX_EVEX_MAP6_D7,
 };
@@ -1601,6 +1623,7 @@ enum
   EVEX_LEN_0F381B,
   EVEX_LEN_0F3836,
   EVEX_LEN_0F384A_X86_64_W_0,
+  EVEX_LEN_0F384B,
   EVEX_LEN_0F385A,
   EVEX_LEN_0F385B,
   EVEX_LEN_0F386D_X86_64_W_0,
@@ -1625,6 +1648,7 @@ enum
   EVEX_LEN_MAP5_7E,
   EVEX_LEN_MAP6_80_W_0,
   EVEX_LEN_MAP6_80_W_1,
+  EVEX_LEN_MAP6_95_P_0_W_1,
 };
 
 enum
@@ -1884,6 +1908,9 @@ enum
   EVEX_W_MAP5_7E_P_1,
   EVEX_W_MAP6_80,
   EVEX_W_MAP6_81,
+  EVEX_W_MAP6_95_P_0,
+  EVEX_W_MAP6_95_P_1,
+  EVEX_W_MAP6_95_P_3,
 };
 
 typedef bool (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
@@ -2709,6 +2736,10 @@ static const char att_names_tmm[][8] = {
   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
 };
 
+static const char att_names_bsr[][8] = {
+  "%bsr0"
+};
+
 static const char att_names_mask[][8] = {
   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
 };
@@ -3095,6 +3126,10 @@ static const struct dis386 reg_table[][8] = {
   {
     { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0) },
   },
+  /* REG_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3 */
+  {
+    { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3_R_0) },
+  },
   /* REG_VEX_0F38F3_L_0_P_0 */
   {
     { Bad_Opcode },
@@ -4176,6 +4211,14 @@ static const struct dis386 prefix_table[][4] = {
     { "tileloaddrs",	{ TMM, MVexSIBMEM }, 0 },
   },
 
+  /* PREFIX_VEX_0F3849_X86_64_L_0_W_1_M_1 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { REG_TABLE (REG_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3) },
+  },
+
   /* PREFIX_VEX_0F384B_X86_64_L_0_W_0 */
   {
     { Bad_Opcode },
@@ -8107,6 +8150,7 @@ static const struct dis386 vex_w_table[][2] = {
   {
     /* VEX_W_0F3849_X86_64_L_0 */
     { MOD_TABLE (MOD_VEX_0F3849_X86_64_L_0_W_0) },
+    { MOD_TABLE (MOD_VEX_0F3849_X86_64_L_0_W_1) },
   },
   {
     /* VEX_W_0F384A_X86_64 */
@@ -8683,6 +8727,11 @@ static const struct dis386 mod_table[][2] = {
     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) },
     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1) },
   },
+  {
+    /* MOD_VEX_0F3849_X86_64_L_0_W_1 */
+    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_1_M_1) },
+  },
 
 #include "i386-dis-evex-mod.h"
 };
@@ -8793,6 +8842,10 @@ static const struct dis386 rm_table[][8] = {
     /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3 */
     { "tilezero",	{ TMM, Skip_MODRM }, 0 },
   },
+  {
+    /* RM_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3_R_0 */
+    { "bsrinit",	{ BSR, Skip_MODRM }, 0 },
+  },
 };
 
 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
@@ -11920,6 +11973,9 @@ intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
     case ymm_mode:
       oappend (ins, "YMMWORD PTR ");
       break;
+    case zmm_mode:
+      oappend (ins, "ZMMWORD PTR ");
+      break;
     case xmmq_mode:
     case evex_half_bcst_xmmqh_mode:
     case evex_half_bcst_xmmq_mode:
@@ -12357,6 +12413,9 @@ OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
 	  else if (bytemode == xmmdw_mode)
 	    shift -= 3;
 	  break;
+	case zmm_mode:
+	  shift = 6;
+	  break;
 	case ymm_mode:
 	  shift = 5;
 	  break;
@@ -13407,6 +13466,8 @@ print_vector_reg (instr_info *ins, unsigned int reg, int bytemode)
 	  abort ();
 	}
     }
+  else if (bytemode == zmm_mode)
+    names = att_names_zmm;
   else if (bytemode == ymm_mode)
     names = att_names_ymm;
   else if (bytemode == tmm_mode)
@@ -13482,6 +13543,18 @@ OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
   return true;
 }
 
+static bool
+OP_BSR (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
+{
+  if (ins->modrm.reg)
+    {
+      oappend (ins, "(bad)");
+      return false;
+    }
+  oappend_register (ins, att_names_bsr[0]);
+  return true;
+}
+
 static bool
 OP_EM (instr_info *ins, int bytemode, int sizeflag)
 {
@@ -14252,9 +14325,45 @@ OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
 	}
       break;
     case 512:
-      names = att_names_zmm;
-      ins->evex_used |= EVEX_len_used;
-      break;
+      switch (bytemode)
+	{
+	case x_mode:
+	case v_mode:
+	  names = att_names_zmm;
+	  ins->evex_used |= EVEX_len_used;
+	  break;
+	case dq_mode:
+	  if (ins->rex & REX_W)
+	    names = att_names64;
+	  else if (bytemode == v_mode
+		   && !(sizeflag & DFLAG))
+	    names = att_names16;
+	  else
+	    names = att_names32;
+	  break;
+	case b_mode:
+	  names = att_names8rex;
+	  break;
+	case d_mode:
+	  names = att_names32;
+	  break;
+	case q_mode:
+	  names = att_names64;
+	  break;
+	case mask_bd_mode:
+	case mask_mode:
+	  if (reg > 0x7)
+	    {
+	      oappend (ins, "(bad)");
+	      return true;
+	    }
+	  names = att_names_mask;
+	  break;
+	default:
+	  abort ();
+	  return true;
+	}
+	break;
     default:
       abort ();
       break;
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 11cc4ff19dc..dded2d906e6 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -263,6 +263,8 @@ static const dependency isa_dependencies[] =
     "RTM|HLE" },
   { "TSXLDTRK",
     "RTM" },
+  { "ACE",
+    "AVX512F|64" },
   { "AMX_TILE",
     "XSAVE|64" },
   { "AMX_INT8",
@@ -470,6 +472,7 @@ static bitfield cpu_flags[] =
   BITFIELD (WAITPKG),
   BITFIELD (UINTR),
   BITFIELD (CLDEMOTE),
+  BITFIELD (ACE),
   BITFIELD (AMX_INT8),
   BITFIELD (AMX_BF16),
   BITFIELD (AMX_FP16),
@@ -571,6 +574,7 @@ static const struct {
   CLASS (RegSIMD),
   CLASS (RegMask),
   CLASS (RegBND),
+  CLASS (RegBS),
 };
 
 #undef CLASS
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 0c5f7747ed2..a8d9ac59c8b 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -359,6 +359,8 @@ enum i386_cpu
   CpuAVX10_2,
   /* Intel AMX-TRANSPOSE Instructions support required.  */
   CpuAMX_TRANSPOSE,
+  /* ACE instructions support required.  */
+  CpuACE,
   /* Not supported in the 64bit mode  */
   CpuNo64,
 
@@ -397,6 +399,7 @@ enum i386_cpu
 		   cpuapx_f:1, \
 		   cpuavx10_2:1, \
 		   cpuamx_transpose:1, \
+		   cpuace:1, \
       /* NOTE: This field needs to remain last. */ \
 		   cpuno64:1
 
@@ -889,6 +892,7 @@ enum operand_class
   RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
   RegMask, /* Vector Mask register */
   RegBND, /* Bound register */
+  RegBS, /* Block scale register */
 };
 
 /* Special operand instances.  */
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 3d3e37b09aa..b85afcf5720 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -62,6 +62,8 @@
 
 #define RegBND Class=RegBND
 
+#define RegBS Class=RegBS
+
 #define Mmword Qword
 #define Oword  Xmmword
 
@@ -118,6 +120,7 @@
 #define SpaceXOP0A OpcodeSpace=SPACE_XOP0A
 
 #define EVexMap4 OpcodeSpace=SPACE_MAP4|EVex128
+#define EVexMap6 OpcodeSpace=SPACE_MAP6
 
 #define Map5 OpcodeSpace=SPACE_MAP5
 #define Map6 OpcodeSpace=SPACE_MAP6
@@ -3234,10 +3237,12 @@ xresldtrk, 0xf20f01e9, TSXLDTRK, NoSuf, {}
 
 // TSXLDTRK instructions end.
 
-// AMX instructions.
+// AMX & ACE instructions.
 
 ldtilecfg, 0x49/0, APX_F(AMX_TILE), Modrm|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex }
+ldtilecfg, 0x49/0, ACE, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex }
 sttilecfg, 0x6649/0, APX_F(AMX_TILE), Modrm|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex }
+sttilecfg, 0x6649/0, ACE, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex }
 
 tcmmimfp16ps, 0x666c, AMX_COMPLEX, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
 tcmmrlfp16ps, 0x6c, AMX_COMPLEX, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
@@ -3250,14 +3255,18 @@ tdpbusd, 0x665e, AMX_INT8, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM
 tdpbsud, 0xf35e, AMX_INT8, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
 
 tileloadd, 0xf24b, APX_F(AMX_TILE), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
+tileloadd, 0xf24b, ACE, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
 tileloaddt1, 0x664b, APX_F(AMX_TILE), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
+tileloaddt1, 0x664b, ACE, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
 tileloaddrs, 0xf24a, APX_F(AMX_MOVRS), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
 tileloaddrst1, 0x664a, APX_F(AMX_MOVRS), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
 tilestored, 0xf34b, APX_F(AMX_TILE), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { RegTMM, Unspecified|BaseIndex }
+tilestored, 0xf34b, ACE, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { RegTMM, Unspecified|BaseIndex }
 
 tilerelease, 0x49c0, AMX_TILE, Vex128|Space0F38|VexW0|NoSuf, {}
+tilerelease, 0x49c0, ACE, Vex128|Space0F38|VexW0|NoSuf, {}
 
-tilezero, 0xf249, AMX_TILE, Modrm|Vex128|Space0F38|VexW0|NoSuf, { RegTMM }
+tilezero, 0xf249, AMX_TILE|ACE, Modrm|Vex128|Space0F38|VexW0|NoSuf, { RegTMM }
 
 <z:pfx, z0:, z1:66>
 
@@ -3288,22 +3297,51 @@ tdpbhf8ps, 0xf2fd, AMX_FP8, Modrm|Vex128|Map5|Src2VVVV|VexW0|NoSuf, { RegTMM, Re
 tdphbf8ps, 0xf3fd, AMX_FP8, Modrm|Vex128|Map5|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
 tdphf8ps, 0x66fd, AMX_FP8, Modrm|Vex128|Map5|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
 
-tcvtrowd2ps, 0xf34a, AMX_AVX512, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
-tcvtrowd2ps, 0xf307, AMX_AVX512, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
+tcvtrowd2ps, 0xf34a, AMX_AVX512|ACE, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
+tcvtrowd2ps, 0xf307, AMX_AVX512|ACE, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
+
+tcvtrowps2bf16h, 0xf26d, AMX_AVX512|ACE, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
+tcvtrowps2bf16h, 0xf207, AMX_AVX512|ACE, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
+tcvtrowps2bf16l, 0xf36d, AMX_AVX512|ACE, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
+tcvtrowps2bf16l, 0xf377, AMX_AVX512|ACE, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
+tcvtrowps2phh, 0x6d, AMX_AVX512|ACE, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
+tcvtrowps2phh, 0x07, AMX_AVX512|ACE, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
+tcvtrowps2phl, 0x666d, AMX_AVX512|ACE, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
+tcvtrowps2phl, 0xf277, AMX_AVX512|ACE, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
+
+tilemovrow, 0x664a, AMX_AVX512|ACE, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
+tilemovrow, 0x6607, AMX_AVX512|ACE, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
+
+// AMX & ACE instructions end.
+
+// ACE instructions.
+
+bsrinit, 0xf249, ACE, Modrm|Vex128|Space0F38|VexW1|NoSuf, { RegBS }
+bsrmovf, 0x95, ACE, Modrm|EVex512|EVexMap6|VexW1|Src1VVVV|NoSuf, { RegZMM|Unspecified|BaseIndex, RegZMM, RegBS }
+bsrmovh, 0xf295, ACE, Modrm|EVex512|EVexMap6|VexW1|NoSuf, { RegZMM|Unspecified|BaseIndex, RegBS }
+bsrmovh, 0xf295, ACE, RegMem|Modrm|EVex512|EVexMap6|VexW0|NoSuf, { RegBS, RegZMM|Unspecified|BaseIndex }
+bsrmovl, 0xf395, ACE, Modrm|EVex512|EVexMap6|VexW1|NoSuf, { RegZMM|Unspecified|BaseIndex, RegBS }
+bsrmovl, 0xf395, ACE, RegMem|Modrm|EVex512|EVexMap6|VexW0|NoSuf, { RegBS, RegZMM|Unspecified|BaseIndex }
+
+tilemovcol, 0x662f, ACE, Modrm|EVex512|Space0F3A|VexW1|NoSuf, { Imm8, RegZMM, RegTMM }
+tilemovcol, 0x664b, ACE, Modrm|EVex512|Space0F38|VexW1|Src2VVVV|NoSuf, { Reg32, RegZMM, RegTMM }
+tilemovrow, 0x6607, ACE, Modrm|EVex512|Space0F3A|VexW1|NoSuf, { Imm8, RegZMM, RegTMM }
+tilemovrow, 0x664a, ACE, Modrm|EVex512|Space0F38|VexW1|Src2VVVV|NoSuf, { Reg32, RegZMM, RegTMM }
+
+top2bf16ps, 0xf35c, ACE, Modrm|EVex512|Space0F38|VexW0|Src2VVVV|NoSuf, { RegZMM, RegZMM, RegTMM }
 
-tcvtrowps2bf16h, 0xf26d, AMX_AVX512, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
-tcvtrowps2bf16h, 0xf207, AMX_AVX512, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
-tcvtrowps2bf16l, 0xf36d, AMX_AVX512, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
-tcvtrowps2bf16l, 0xf377, AMX_AVX512, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
-tcvtrowps2phh, 0x6d, AMX_AVX512, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
-tcvtrowps2phh, 0x07, AMX_AVX512, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
-tcvtrowps2phl, 0x666d, AMX_AVX512, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
-tcvtrowps2phl, 0xf277, AMX_AVX512, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
+top4bssd, 0xf25e, ACE, Modrm|EVex512|Space0F38|VexW0|Src2VVVV|NoSuf, { RegZMM, RegZMM, RegTMM }
+top4bsud, 0xf35e, ACE, Modrm|EVex512|Space0F38|VexW0|Src2VVVV|NoSuf, { RegZMM, RegZMM, RegTMM }
+top4busd, 0x665e, ACE, Modrm|EVex512|Space0F38|VexW0|Src2VVVV|NoSuf, { RegZMM, RegZMM, RegTMM }
+top4buud, 0x5e, ACE, Modrm|EVex512|Space0F38|VexW0|Src2VVVV|NoSuf, { RegZMM, RegZMM, RegTMM }
 
-tilemovrow, 0x664a, AMX_AVX512, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
-tilemovrow, 0x6607, AMX_AVX512, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
+top4mxbf8ps, 0x8d, ACE, Modrm|EVex512|Space0F3A|VexW0|Src2VVVV|NoSuf, { Imm8, RegZMM, RegZMM, RegTMM }
+top4mxbhf8ps, 0xf28d, ACE, Modrm|EVex512|Space0F3A|VexW0|Src2VVVV|NoSuf, { Imm8, RegZMM, RegZMM, RegTMM }
+top4mxhbf8ps, 0xf38d, ACE, Modrm|EVex512|Space0F3A|VexW0|Src2VVVV|NoSuf, { Imm8, RegZMM, RegZMM, RegTMM }
+top4mxhf8ps, 0x668d, ACE, Modrm|EVex512|Space0F3A|VexW0|Src2VVVV|NoSuf, { Imm8, RegZMM, RegZMM, RegTMM }
+top4mxbssps, 0xf28f, ACE, Modrm|EVex512|Space0F3A|VexW0|Src2VVVV|NoSuf, { Imm8, RegZMM, RegZMM, RegTMM }
 
-// AMX instructions end.
+// ACE instructions end.
 
 // KEYLOCKER instructions.
 
diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl
index 74234c503d6..ee6923252c9 100644
--- a/opcodes/i386-reg.tbl
+++ b/opcodes/i386-reg.tbl
@@ -344,7 +344,7 @@ zmm28, Class=RegSIMD|Zmmword, RegVRex|RegRex, 4, Dw2Inval, 79
 zmm29, Class=RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval, 80
 zmm30, Class=RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, 81
 zmm31, Class=RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, 82
-// TMM registers for AMX
+// TMM registers for AMX/ACE
 tmm0, Class=RegSIMD|Tmmword, 0, 0, Dw2Inval, Dw2Inval
 tmm1, Class=RegSIMD|Tmmword, 0, 1, Dw2Inval, Dw2Inval
 tmm2, Class=RegSIMD|Tmmword, 0, 2, Dw2Inval, Dw2Inval
@@ -353,6 +353,8 @@ tmm4, Class=RegSIMD|Tmmword, 0, 4, Dw2Inval, Dw2Inval
 tmm5, Class=RegSIMD|Tmmword, 0, 5, Dw2Inval, Dw2Inval
 tmm6, Class=RegSIMD|Tmmword, 0, 6, Dw2Inval, Dw2Inval
 tmm7, Class=RegSIMD|Tmmword, 0, 7, Dw2Inval, Dw2Inval
+// Block scale register for ACE
+bsr0, Class=RegBS, 0, 0, Dw2Inval, Dw2Inval
 // Bound registers for MPX
 bnd0, Class=RegBND, 0, 0, Dw2Inval, 126
 bnd1, Class=RegBND, 0, 1, Dw2Inval, 127
-- 
2.53.0


From Ganesh.Gopalasubramanian@amd.com  Sat Jun 27 11:55:33 2026
From: Ganesh.Gopalasubramanian@amd.com (Ganesh Gopalasubramanian)
Date: Sat, 27 Jun 2026 17:25:33 +0530
Subject: [PATCH v1 2/2] Support x86 ACE ISA
In-Reply-To: <20260627095543.1627012-1-Ganesh.Gopalasubramanian@amd.com>
References: <20260627095543.1627012-1-Ganesh.Gopalasubramanian@amd.com>
Message-ID: <20260627115533.1633143-1-Ganesh.Gopalasubramanian@amd.com>

Adds assembler and disassembler support for ACE tile, block scale
register, outer product, and MX FP8/INT8/BF16 instructions including:
bsrinit, bsrmovf/h/l, tilemovcol, tilemovrow, top2bf16ps, top4bssd/bsud/
busd/buud, and top4mx* variants.

All ACE v1 instructions are enumerated under a single ACE feature flag
(CPUID.(EAX=07H,ECX=1):ECX[11]), matching the specification.

Key changes:
- opcodes/i386-opc.tbl: ACE instruction definitions with EVexMap6 macro
- opcodes/i386-gen.c: single ACE CPU feature and RegBS register class
- opcodes/i386-dis*.h: Disassembler dispatch tables for MAP6, 0F3A, 0F38
- gas/config/tc-i386.c: ACE operand validation with proper scoping to
  avoid interfering with AMX-AVX512 tilemovrow/tilemovcol variants
- gas/testsuite: ACE instruction test case

The generated tables (opcodes/i386-init.h, opcodes/i386-mnem.h and
opcodes/i386-tbl.h) are omitted from this mail to keep it within the
list size limit; they are regenerated from opcodes/i386-opc.tbl and
opcodes/i386-reg.tbl by i386-gen and are reflected in the diffstat.

Reference: AI Compute Extensions (ACE) Specification, v1.15
https://x86ecosystem.org/wp-content/uploads/2026/06/ACE_v1_Specification_public_1_15.pdf

gas/ChangeLog:

	* NEWS: Mention x86 ACE instruction support.
	* config/tc-i386.c (enum i386_error): Add unsupported_tile_index.
	(cpu_arch): Add ace.
	(_is_cpu): Handle CpuACE.
	(type_names): Add RegBS ("bsr") entry.
	(install_template): Handle CpuACE.
	(i386_assemble): Handle unsupported_tile_index.
	(check_ACE_operands): New function.
	(match_template): Call check_ACE_operands.
	(process_operands): Handle bsrinit like tilezero.
	(output_insn): Set GNU_PROPERTY_X86_FEATURE_2_TMM for ACE.
	(check_register): Allow TMM registers and the block scale
	register for ACE.
	* doc/c-i386.texi: Document .ace.
	* testsuite/gas/i386/x86-64.exp: Run ACE tests.
	* testsuite/gas/i386/x86-64-ace.d: New test.
	* testsuite/gas/i386/x86-64-ace-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-ace.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (OP_BSR): New function.
	(att_names_bsr): New.
	(bsr, zmm_mode): New enumerators.
	(REG_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3): New.
	(MOD_VEX_0F3849_X86_64_L_0_W_1): Ditto.
	(RM_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3_R_0): Ditto.
	(PREFIX_VEX_0F3849_X86_64_L_0_W_1_M_1): Ditto.
	(PREFIX_EVEX_0F384A, PREFIX_EVEX_0F384B, PREFIX_EVEX_0F385C): Ditto.
	(PREFIX_EVEX_0F385E, PREFIX_EVEX_0F3A07, PREFIX_EVEX_0F3A2F): Ditto.
	(PREFIX_EVEX_0F3A8D, PREFIX_EVEX_0F3A8F, PREFIX_EVEX_MAP6_95): Ditto.
	(EVEX_LEN_0F384B, EVEX_LEN_MAP6_95_P_0_W_1): Ditto.
	(EVEX_W_MAP6_95_P_0, EVEX_W_MAP6_95_P_1, EVEX_W_MAP6_95_P_3): Ditto.
	(BSR, EXzmm, Rzmm, VexGd): Define.
	(reg_table): Add REG_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3.
	(prefix_table): Add PREFIX_VEX_0F3849_X86_64_L_0_W_1_M_1.
	(vex_w_table): Add W_1 entry to VEX_W_0F3849_X86_64_L_0.
	(mod_table): Add MOD_VEX_0F3849_X86_64_L_0_W_1.
	(rm_table): Add RM_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3_R_0 (bsrinit).
	(intel_operand_size): Handle zmm_mode.
	(OP_E_memory): Handle zmm_mode.
	(print_vector_reg): Handle zmm_mode.
	(OP_VEX): Select 512-bit register names by bytemode.
	* i386-dis-evex.h: Add ACE entries to evex_table.
	* i386-dis-evex-len.h: Add EVEX_LEN_0F384B and
	EVEX_LEN_MAP6_95_P_0_W_1.
	* i386-dis-evex-prefix.h: Add PREFIX_EVEX_0F384A, PREFIX_EVEX_0F384B,
	PREFIX_EVEX_0F385C, PREFIX_EVEX_0F385E, PREFIX_EVEX_0F3A07,
	PREFIX_EVEX_0F3A2F, PREFIX_EVEX_0F3A8D, PREFIX_EVEX_0F3A8F and
	PREFIX_EVEX_MAP6_95.
	* i386-dis-evex-w.h: Add PREFIX_EVEX_0F384A and PREFIX_EVEX_0F3A07
	entries; add EVEX_W_MAP6_95_P_0, EVEX_W_MAP6_95_P_1 and
	EVEX_W_MAP6_95_P_3.
	* i386-gen.c (isa_dependencies): Add ACE.
	(cpu_flags): Add ACE.
	(operand_classes): Add RegBS.
	* i386-opc.h (CpuACE): New.
	(i386_cpu): Add cpuace.
	(operand_class): Add RegBS.
	* i386-opc.tbl: Add RegBS and EVexMap6 macros.  Add ACE
	instructions and enable the AMX tile, tcvtrow* and tilemovrow
	insns for ACE.
	* i386-reg.tbl: Add bsr0 block scale register.
	* i386-init.h: Regenerated.
	* i386-mnem.h: Ditto.
	* i386-tbl.h: Ditto.

Co-authored-by: Umesh Kalvakuntla
---
 gas/NEWS                                  |     4 +
 gas/config/tc-i386.c                      |    52 +-
 gas/doc/c-i386.texi                       |     3 +-
 gas/testsuite/gas/i386/x86-64-ace-intel.d |    43 +
 gas/testsuite/gas/i386/x86-64-ace.d       |    43 +
 gas/testsuite/gas/i386/x86-64-ace.s       |    45 +
 gas/testsuite/gas/i386/x86-64.exp         |     2 +
 opcodes/i386-dis-evex-len.h               |    13 +
 opcodes/i386-dis-evex-prefix.h            |    57 +
 opcodes/i386-dis-evex-w.h                 |    19 +-
 opcodes/i386-dis-evex.h                   |    14 +-
 opcodes/i386-dis.c                        |   115 +-
 opcodes/i386-gen.c                        |     4 +
 opcodes/i386-init.h                       |   608 +-
 opcodes/i386-mnem.h                       |  3093 ++--
 opcodes/i386-opc.h                        |     4 +
 opcodes/i386-opc.tbl                      |    68 +-
 opcodes/i386-reg.tbl                      |     4 +-
 opcodes/i386-tbl.h                        | 18961 ++++++++++----------
 19 files changed, 11964 insertions(+), 11188 deletions(-)
 create mode 100644 gas/testsuite/gas/i386/x86-64-ace-intel.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-ace.d
 create mode 100644 gas/testsuite/gas/i386/x86-64-ace.s

diff --git a/gas/NEWS b/gas/NEWS
index ef4bd048e4b..a02f11a46ed 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,9 @@
 -*- text -*-
 
+* Add support for the x86 ACE (AI Compute Extensions) instructions,
+  including tile data movement, block scale register operations and tile
+  outer products.
+
 * Add support for the x86 AVX10_V2_AUX instructions, providing FP8, FP4
   and FP6 format conversion instructions.
 
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index d82ed061a78..f6f40589d11 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -272,6 +272,7 @@ enum i386_error
     unsupported_rc_sae,
     unsupported_vector_size,
     unsupported_rsp_register,
+    unsupported_tile_index,
     internal_error,
   };
 
@@ -1200,6 +1201,7 @@ static const arch_entry cpu_arch[] =
   SUBARCH (pconfig, PCONFIG, PCONFIG, false),
   SUBARCH (waitpkg, WAITPKG, WAITPKG, false),
   SUBARCH (cldemote, CLDEMOTE, CLDEMOTE, false),
+  SUBARCH (ace, ACE, ACE, false),
   SUBARCH (amx_int8, AMX_INT8, ANY_AMX_INT8, false),
   SUBARCH (amx_bf16, AMX_BF16, ANY_AMX_BF16, false),
   SUBARCH (amx_fp16, AMX_FP16, ANY_AMX_FP16, false),
@@ -1894,6 +1896,7 @@ _is_cpu (const i386_cpu_attr *a, enum i386_cpu cpu)
     case CpuAPX_F:    return a->bitfield.cpuapx_f;
     case CpuAVX10_2:  return a->bitfield.cpuavx10_2;
     case CpuAMX_TRANSPOSE:  return a->bitfield.cpuamx_transpose;
+    case CpuACE:      return a->bitfield.cpuace;
     case Cpu64:       return a->bitfield.cpu64;
     case CpuNo64:     return a->bitfield.cpuno64;
     default:
@@ -3933,6 +3936,7 @@ const type_names[] =
   { { .bitfield = { .class = RegSIMD, .zmmword = 1 } }, "rZMM" },
   { { .bitfield = { .class = RegSIMD, .tmmword = 1 } }, "rTMM" },
   { { .bitfield = { .class = RegMask } }, "Mask reg" },
+  { { .bitfield = { .class = RegBS } }, "bsr" },
 };
 
 static void
@@ -4253,6 +4257,7 @@ install_template (const insn_template *t)
 	}
 
       if ((maybe_cpu (t, CpuCMPCCXADD) || maybe_cpu (t, CpuAMX_TILE)
+	   || maybe_cpu (t, CpuACE)
 	   || maybe_cpu (t, CpuAVX512F) || maybe_cpu (t, CpuAVX512DQ)
 	   || maybe_cpu (t, CpuAVX512BW) || maybe_cpu (t, CpuBMI)
 	   || maybe_cpu (t, CpuBMI2) || maybe_cpu (t, CpuUSER_MSR)
@@ -7498,6 +7503,9 @@ i386_assemble (char *line)
 	case unsupported_rsp_register:
 	  err_msg = _("'rsp' register cannot be used");
 	  break;
+	case unsupported_tile_index:
+	  err_msg = _("immediate value must be in range 0-15");
+	  break;
 	case internal_error:
 	  err_msg = _("internal error");
 	  break;
@@ -9323,6 +9331,29 @@ check_APX_operands (const insn_template *t)
   return 0;
 }
 
+/* Check if ACE operands are valid for the instruction.  */
+static bool
+check_ACE_operands (const insn_template *t)
+{
+  switch (t->mnem_off)
+    {
+    case MN_tilemovrow:
+    case MN_tilemovcol:
+      if (is_cpu (t, CpuACE)
+	  && i.op[0].imms && i.op[0].imms->X_op == O_constant)
+	{
+	  offsetT val = i.op[0].imms->X_add_number;
+	  if (val < 0 || val > 15)
+	    {
+	      i.error = unsupported_tile_index;
+	      return 1;
+	    }
+	}
+      break;
+    }
+  return 0;
+}
+
 /* Check if the instruction use the REX registers or REX prefix.  */
 static bool
 check_Rex_required (void)
@@ -9905,6 +9936,13 @@ match_template (char mnem_suffix)
 	  continue;
 	}
 
+      /* Check if ACE operands are valid.  */
+      if (check_ACE_operands (t))
+	{
+	  specific_error = progress (i.error);
+	  continue;
+	}
+
       /* Check whether to use the shorter VEX encoding for certain insns where
 	 the EVEX encoding comes first in the table.  This requires the respective
 	 AVX-* feature to be explicitly enabled.
@@ -10994,7 +11032,7 @@ process_operands (void)
      not ModR/M.rm.  To avoid special casing this in build_modrm_byte(), fake a
      new destination operand here, while converting the source one to register
      number 0.  */
-  if (i.tm.mnem_off == MN_tilezero)
+  if (i.tm.mnem_off == MN_tilezero || i.tm.mnem_off == MN_bsrinit)
     {
       copy_operand (1, 0);
       i.op[0].regs -= i.op[0].regs->reg_num;
@@ -12475,7 +12513,8 @@ output_insn (const struct last_insn *last_insn)
       unsigned int feature_2_used = 0;
 
       if ((i.xstate & xstate_tmm) == xstate_tmm
-	  || is_cpu (&i.tm, CpuAMX_TILE))
+	  || is_cpu (&i.tm, CpuAMX_TILE)
+	  || is_cpu (&i.tm, CpuACE))
 	feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_TMM;
 
       if (is_cpu (&i.tm, Cpu8087)
@@ -16943,13 +16982,18 @@ static bool check_register (const reg_entry *r)
     return false;
 
   if (r->reg_type.bitfield.tmmword
-      && (!cpu_arch_flags.bitfield.cpuamx_tile
-          || flag_code != CODE_64BIT))
+      && ((!cpu_arch_flags.bitfield.cpuamx_tile
+	   && !cpu_arch_flags.bitfield.cpuace)
+	  || flag_code != CODE_64BIT))
     return false;
 
   if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx)
     return false;
 
+  if (r->reg_type.bitfield.class == RegBS
+      && !cpu_arch_flags.bitfield.cpuace)
+    return false;
+
   /* Don't allow fake index register unless allow_index_reg isn't 0. */
   if (!allow_index_reg && r->reg_num == RegIZ)
     return false;
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 9f6e8da443d..5d1e15816af 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -242,6 +242,7 @@ accept various extension mnemonics.  For example,
 @code{amx_movrs},
 @code{amx_avx512},
 @code{amx_tile},
+@code{ace},
 @code{vmx},
 @code{vmfunc},
 @code{smx},
@@ -1731,7 +1732,7 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.amx_int8} @tab @samp{.amx_bf16} @tab @samp{.amx_fp16}
 @item @samp{.amx_complex} @tab @samp{.amx_transpose} @tab @samp{.amx_tf32}
 @item @samp{.amx_fp8} @tab @samp{.amx_movrs} @tab @samp{.amx_avx512}
-@item @samp{.amx_tile}
+@item @samp{.amx_tile} @tab @samp{.ace}
 @item @samp{.kl} @tab @samp{.widekl} @tab @samp{.uintr} @tab @samp{.hreset}
 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme}
diff --git a/gas/testsuite/gas/i386/x86-64-ace-intel.d b/gas/testsuite/gas/i386/x86-64-ace-intel.d
new file mode 100644
index 00000000000..b116845d240
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-ace-intel.d
@@ -0,0 +1,43 @@
+#objdump: -dw -Mintel
+#name: 64-bit ACE insns (Intel disassembly)
+#source: x86-64-ace.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <start>:
+[\s]*[a-f0-9]+:[\s]*c4 e2 fb 49 c0[\s]*bsrinit bsr0
+[\s]*[a-f0-9]+:[\s]*62 f6 f4 48 95 c3[\s]*bsrmovf bsr0,zmm1,zmm3
+[\s]*[a-f0-9]+:[\s]*62 d6 ff 48 95 c2[\s]*bsrmovh bsr0,zmm10
+[\s]*[a-f0-9]+:[\s]*62 d6 fe 48 95 c2[\s]*bsrmovl bsr0,zmm10
+[\s]*[a-f0-9]+:[\s]*67 62 f6 ff 48 95 00[\s]*bsrmovh bsr0,ZMMWORD PTR \[eax\]
+[\s]*[a-f0-9]+:[\s]*67 62 f6 fe 48 95 00[\s]*bsrmovl bsr0,ZMMWORD PTR \[eax\]
+[\s]*[a-f0-9]+:[\s]*62 f6 7f 48 95 c4[\s]*bsrmovh zmm4,bsr0
+[\s]*[a-f0-9]+:[\s]*62 f6 7e 48 95 c4[\s]*bsrmovl zmm4,bsr0
+[\s]*[a-f0-9]+:[\s]*67 62 f6 7f 48 95 00[\s]*bsrmovh ZMMWORD PTR \[eax\],bsr0
+[\s]*[a-f0-9]+:[\s]*67 62 f6 7e 48 95 00[\s]*bsrmovl ZMMWORD PTR \[eax\],bsr0
+[\s]*[a-f0-9]+:[\s]*62 f3 fd 48 2f ca 08[\s]*tilemovcol tmm1,zmm2,0x8
+[\s]*[a-f0-9]+:[\s]*62 f3 fd 48 07 ca 08[\s]*tilemovrow tmm1,zmm2,0x8
+[\s]*[a-f0-9]+:[\s]*62 f2 e5 48 4b ca[\s]*tilemovcol tmm1,zmm2,ebx
+[\s]*[a-f0-9]+:[\s]*62 f2 e5 48 4a ca[\s]*tilemovrow tmm1,zmm2,ebx
+[\s]*[a-f0-9]+:[\s]*62 f2 6e 48 5c c1[\s]*top2bf16ps tmm0,zmm1,zmm2
+[\s]*[a-f0-9]+:[\s]*62 f2 6f 48 5e c1[\s]*top4bssd tmm0,zmm1,zmm2
+[\s]*[a-f0-9]+:[\s]*62 f2 6e 48 5e c1[\s]*top4bsud tmm0,zmm1,zmm2
+[\s]*[a-f0-9]+:[\s]*62 f2 6d 48 5e c1[\s]*top4busd tmm0,zmm1,zmm2
+[\s]*[a-f0-9]+:[\s]*62 f2 6c 48 5e c1[\s]*top4buud tmm0,zmm1,zmm2
+[\s]*[a-f0-9]+:[\s]*62 f3 6c 48 8d c9 07[\s]*top4mxbf8ps tmm1,zmm1,zmm2,0x7
+[\s]*[a-f0-9]+:[\s]*62 f3 6f 48 8d c9 07[\s]*top4mxbhf8ps tmm1,zmm1,zmm2,0x7
+[\s]*[a-f0-9]+:[\s]*62 f3 6e 48 8d c9 07[\s]*top4mxhbf8ps tmm1,zmm1,zmm2,0x7
+[\s]*[a-f0-9]+:[\s]*62 f3 6d 48 8d c9 07[\s]*top4mxhf8ps tmm1,zmm1,zmm2,0x7
+[\s]*[a-f0-9]+:[\s]*62 f3 6f 48 8f c9 07[\s]*top4mxbssps tmm1,zmm1,zmm2,0x7
+[\s]*[a-f0-9]+:[\s]*62 62 6e 48 4a f5[\s]*tcvtrowd2ps zmm30,tmm5,edx
+[\s]*[a-f0-9]+:[\s]*62 63 7e 48 07 f5 7b[\s]*tcvtrowd2ps zmm30,tmm5,0x7b
+[\s]*[a-f0-9]+:[\s]*62 62 6f 48 6d f5[\s]*tcvtrowps2bf16h zmm30,tmm5,edx
+[\s]*[a-f0-9]+:[\s]*62 63 7f 48 07 f5 7b[\s]*tcvtrowps2bf16h zmm30,tmm5,0x7b
+[\s]*[a-f0-9]+:[\s]*62 62 6e 48 6d f5[\s]*tcvtrowps2bf16l zmm30,tmm5,edx
+[\s]*[a-f0-9]+:[\s]*62 63 7e 48 77 f5 7b[\s]*tcvtrowps2bf16l zmm30,tmm5,0x7b
+[\s]*[a-f0-9]+:[\s]*62 62 6c 48 6d f5[\s]*tcvtrowps2phh zmm30,tmm5,edx
+[\s]*[a-f0-9]+:[\s]*62 63 7c 48 07 f5 7b[\s]*tcvtrowps2phh zmm30,tmm5,0x7b
+[\s]*[a-f0-9]+:[\s]*62 62 6d 48 6d f5[\s]*tcvtrowps2phl zmm30,tmm5,edx
+[\s]*[a-f0-9]+:[\s]*62 63 7f 48 77 f5 7b[\s]*tcvtrowps2phl zmm30,tmm5,0x7b
diff --git a/gas/testsuite/gas/i386/x86-64-ace.d b/gas/testsuite/gas/i386/x86-64-ace.d
new file mode 100644
index 00000000000..cc91aa7fede
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-ace.d
@@ -0,0 +1,43 @@
+#objdump: -dw
+#name: 64-bit ACE insns
+#source: x86-64-ace.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <start>:
+[\s]*[a-f0-9]+:[\s]*c4 e2 fb 49 c0[\s]*bsrinit %bsr0
+[\s]*[a-f0-9]+:[\s]*62 f6 f4 48 95 c3[\s]*bsrmovf %zmm3,%zmm1,%bsr0
+[\s]*[a-f0-9]+:[\s]*62 d6 ff 48 95 c2[\s]*bsrmovh %zmm10,%bsr0
+[\s]*[a-f0-9]+:[\s]*62 d6 fe 48 95 c2[\s]*bsrmovl %zmm10,%bsr0
+[\s]*[a-f0-9]+:[\s]*67 62 f6 ff 48 95 00[\s]*bsrmovh \(%eax\),%bsr0
+[\s]*[a-f0-9]+:[\s]*67 62 f6 fe 48 95 00[\s]*bsrmovl \(%eax\),%bsr0
+[\s]*[a-f0-9]+:[\s]*62 f6 7f 48 95 c4[\s]*bsrmovh %bsr0,%zmm4
+[\s]*[a-f0-9]+:[\s]*62 f6 7e 48 95 c4[\s]*bsrmovl %bsr0,%zmm4
+[\s]*[a-f0-9]+:[\s]*67 62 f6 7f 48 95 00[\s]*bsrmovh %bsr0,\(%eax\)
+[\s]*[a-f0-9]+:[\s]*67 62 f6 7e 48 95 00[\s]*bsrmovl %bsr0,\(%eax\)
+[\s]*[a-f0-9]+:[\s]*62 f3 fd 48 2f ca 08[\s]*tilemovcol \$0x8,%zmm2,%tmm1
+[\s]*[a-f0-9]+:[\s]*62 f3 fd 48 07 ca 08[\s]*tilemovrow \$0x8,%zmm2,%tmm1
+[\s]*[a-f0-9]+:[\s]*62 f2 e5 48 4b ca[\s]*tilemovcol %ebx,%zmm2,%tmm1
+[\s]*[a-f0-9]+:[\s]*62 f2 e5 48 4a ca[\s]*tilemovrow %ebx,%zmm2,%tmm1
+[\s]*[a-f0-9]+:[\s]*62 f2 6e 48 5c c1[\s]*top2bf16ps %zmm2,%zmm1,%tmm0
+[\s]*[a-f0-9]+:[\s]*62 f2 6f 48 5e c1[\s]*top4bssd %zmm2,%zmm1,%tmm0
+[\s]*[a-f0-9]+:[\s]*62 f2 6e 48 5e c1[\s]*top4bsud %zmm2,%zmm1,%tmm0
+[\s]*[a-f0-9]+:[\s]*62 f2 6d 48 5e c1[\s]*top4busd %zmm2,%zmm1,%tmm0
+[\s]*[a-f0-9]+:[\s]*62 f2 6c 48 5e c1[\s]*top4buud %zmm2,%zmm1,%tmm0
+[\s]*[a-f0-9]+:[\s]*62 f3 6c 48 8d c9 07[\s]*top4mxbf8ps \$0x7,%zmm2,%zmm1,%tmm1
+[\s]*[a-f0-9]+:[\s]*62 f3 6f 48 8d c9 07[\s]*top4mxbhf8ps \$0x7,%zmm2,%zmm1,%tmm1
+[\s]*[a-f0-9]+:[\s]*62 f3 6e 48 8d c9 07[\s]*top4mxhbf8ps \$0x7,%zmm2,%zmm1,%tmm1
+[\s]*[a-f0-9]+:[\s]*62 f3 6d 48 8d c9 07[\s]*top4mxhf8ps \$0x7,%zmm2,%zmm1,%tmm1
+[\s]*[a-f0-9]+:[\s]*62 f3 6f 48 8f c9 07[\s]*top4mxbssps \$0x7,%zmm2,%zmm1,%tmm1
+[\s]*[a-f0-9]+:[\s]*62 62 6e 48 4a f5[\s]*tcvtrowd2ps %edx,%tmm5,%zmm30
+[\s]*[a-f0-9]+:[\s]*62 63 7e 48 07 f5 7b[\s]*tcvtrowd2ps \$0x7b,%tmm5,%zmm30
+[\s]*[a-f0-9]+:[\s]*62 62 6f 48 6d f5[\s]*tcvtrowps2bf16h %edx,%tmm5,%zmm30
+[\s]*[a-f0-9]+:[\s]*62 63 7f 48 07 f5 7b[\s]*tcvtrowps2bf16h \$0x7b,%tmm5,%zmm30
+[\s]*[a-f0-9]+:[\s]*62 62 6e 48 6d f5[\s]*tcvtrowps2bf16l %edx,%tmm5,%zmm30
+[\s]*[a-f0-9]+:[\s]*62 63 7e 48 77 f5 7b[\s]*tcvtrowps2bf16l \$0x7b,%tmm5,%zmm30
+[\s]*[a-f0-9]+:[\s]*62 62 6c 48 6d f5[\s]*tcvtrowps2phh %edx,%tmm5,%zmm30
+[\s]*[a-f0-9]+:[\s]*62 63 7c 48 07 f5 7b[\s]*tcvtrowps2phh \$0x7b,%tmm5,%zmm30
+[\s]*[a-f0-9]+:[\s]*62 62 6d 48 6d f5[\s]*tcvtrowps2phl %edx,%tmm5,%zmm30
+[\s]*[a-f0-9]+:[\s]*62 63 7f 48 77 f5 7b[\s]*tcvtrowps2phl \$0x7b,%tmm5,%zmm30
diff --git a/gas/testsuite/gas/i386/x86-64-ace.s b/gas/testsuite/gas/i386/x86-64-ace.s
new file mode 100644
index 00000000000..9c7bf8a2214
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-ace.s
@@ -0,0 +1,45 @@
+# Check 64-bit ACE instructions
+
+	.text
+start:
+	bsrinit %bsr0
+	bsrmovf %zmm3, %zmm1, %bsr0
+
+	bsrmovh %zmm10, %bsr0
+	bsrmovl %zmm10, %bsr0
+	bsrmovh (%eax), %bsr0
+	bsrmovl (%eax), %bsr0
+
+	bsrmovh %bsr0, %zmm4
+	bsrmovl %bsr0, %zmm4
+	bsrmovh %bsr0, (%eax)
+	bsrmovl %bsr0, (%eax)
+
+	tilemovcol $8, %zmm2, %tmm1
+	tilemovrow $8, %zmm2, %tmm1
+
+	tilemovcol %ebx, %zmm2, %tmm1
+	tilemovrow %ebx, %zmm2, %tmm1
+
+	top2bf16ps %zmm2, %zmm1, %tmm0
+	top4bssd   %zmm2, %zmm1, %tmm0
+	top4bsud   %zmm2, %zmm1, %tmm0
+	top4busd   %zmm2, %zmm1, %tmm0
+	top4buud   %zmm2, %zmm1, %tmm0
+
+	top4mxbf8ps  $7, %zmm2, %zmm1, %tmm1
+	top4mxbhf8ps $7, %zmm2, %zmm1, %tmm1
+	top4mxhbf8ps $7, %zmm2, %zmm1, %tmm1
+	top4mxhf8ps  $7, %zmm2, %zmm1, %tmm1
+	top4mxbssps  $7, %zmm2, %zmm1, %tmm1
+
+	tcvtrowd2ps     %edx, %tmm5, %zmm30
+	tcvtrowd2ps     $0x7b, %tmm5, %zmm30
+	tcvtrowps2bf16h %edx, %tmm5, %zmm30
+	tcvtrowps2bf16h $0x7b, %tmm5, %zmm30
+	tcvtrowps2bf16l %edx, %tmm5, %zmm30
+	tcvtrowps2bf16l $0x7b, %tmm5, %zmm30
+	tcvtrowps2phh   %edx, %tmm5, %zmm30
+	tcvtrowps2phh   $0x7b, %tmm5, %zmm30
+	tcvtrowps2phl   %edx, %tmm5, %zmm30
+	tcvtrowps2phl   $0x7b, %tmm5, %zmm30
diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp
index d0d3cb47117..ae5d8bff1ba 100644
--- a/gas/testsuite/gas/i386/x86-64.exp
+++ b/gas/testsuite/gas/i386/x86-64.exp
@@ -689,6 +689,8 @@ run_list_test "x86-64-amx-inval"
 run_dump_test "x86-64-amx"
 run_dump_test "x86-64-amx-intel"
 run_dump_test "x86-64-amx-bad"
+run_dump_test "x86-64-ace"
+run_dump_test "x86-64-ace-intel"
 
 if { ![istarget "*-*-aix*"]
      && ![istarget "*-*-beos*"]
diff --git a/opcodes/i386-dis-evex-len.h b/opcodes/i386-dis-evex-len.h
index 370710915de..273c6d40d12 100644
--- a/opcodes/i386-dis-evex-len.h
+++ b/opcodes/i386-dis-evex-len.h
@@ -51,6 +51,13 @@ static const struct dis386 evex_len_table[][3] = {
     { PREFIX_TABLE (PREFIX_EVEX_0F384A_X86_64_W_0_L_2) },
   },
 
+  /* EVEX_LEN_0F384B */
+  {
+    { X86_64_EVEX_W_TABLE (VEX_W_0F384B_X86_64_L_0) },
+    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_EVEX_0F384B) },
+  },
+
   /* EVEX_LEN_0F385A */
   {
     { Bad_Opcode },
@@ -207,4 +214,10 @@ static const struct dis386 evex_len_table[][3] = {
     { "vbmacxor16x16x16", { XM, Vex, EXx }, NO_PREFIX },
     { "vbmacxor16x16x16", { XM, Vex, EXx }, NO_PREFIX },
   },
+  /* EVEX_LEN_MAP6_95_P_0_W_1 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "bsrmovf", { BSR, Vex, EXx }, 0 },
+  },
 };
diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h
index ffecef5e796..f3b031470df 100644
--- a/opcodes/i386-dis-evex-prefix.h
+++ b/opcodes/i386-dis-evex-prefix.h
@@ -254,6 +254,18 @@
     { "tcvtrowd2ps",	{ XM, Rtmm, VexGdq }, 0 },
     { "tilemovrow",	{ XM, Rtmm, VexGdq }, 0 },
   },
+  /* PREFIX_EVEX_0F384A */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "tilemovrow",	{ TMM, Rzmm, VexGd }, 0 },
+  },
+  /* PREFIX_EVEX_0F384B */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "tilemovcol",	{ TMM, Rzmm, VexGd }, 0 },
+  },
   /* PREFIX_EVEX_0F3852 */
   {
     { "vdpphp%XS",	{ XM, Vex, EXx }, 0 },
@@ -268,6 +280,18 @@
     { VEX_W_TABLE (VEX_W_0F3853) },
     { "vp4dpws%XSds",	{ XM, Vex, Mxmm }, 0 },
   },
+  /* PREFIX_EVEX_0F385C */
+  {
+    { Bad_Opcode },
+    { "top2bf16ps",	{ TMM, Rzmm, Vex }, 0 },
+  },
+  /* PREFIX_EVEX_0F385E */
+  {
+    { "top4buud",	{ TMM, Rzmm, Vex }, 0 },
+    { "top4bsud",	{ TMM, Rzmm, Vex }, 0 },
+    { "top4busd",	{ TMM, Rzmm, Vex }, 0 },
+    { "top4bssd",	{ TMM, Rzmm, Vex }, 0 },
+  },
   /* PREFIX_EVEX_0F3868 */
   {
     { Bad_Opcode },
@@ -331,6 +355,12 @@
     { "tilemovrow",	{ XM, Rtmm, Ib }, 0 },
     { "tcvtrowps2bf16h",	{ XM, Rtmm, Ib }, 0 },
   },
+  /* PREFIX_EVEX_0F3A07 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "tilemovrow", { TMM, Rzmm, Ib }, 0 },
+  },
   /* PREFIX_EVEX_0F3A08 */
   {
     { "vrndscalep%XH",  { XM, EXxh, EXxEVexS, Ib }, 0 },
@@ -357,6 +387,12 @@
     { Bad_Opcode },
     { "vgetmants%XW",	{ XMScalar, VexScalar, EXdq, EXxEVexS, Ib }, 0 },
   },
+  /* PREFIX_EVEX_0F3A2F */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "tilemovcol", { TMM, Rzmm, Ib }, 0 },
+  },
   /* PREFIX_EVEX_0F3A42_W_0 */
   {
     { Bad_Opcode },
@@ -409,6 +445,20 @@
     { Bad_Opcode },
     { "tcvtrowps2phl",	{ XM, Rtmm, Ib }, 0 },
   },
+  /* PREFIX_EVEX_0F3A8D */
+  {
+    { "top4mxbf8ps",	{ TMM, Rzmm, Vex, Ib }, 0 },
+    { "top4mxhbf8ps",	{ TMM, Rzmm, Vex, Ib }, 0 },
+    { "top4mxhf8ps",	{ TMM, Rzmm, Vex, Ib }, 0 },
+    { "top4mxbhf8ps",	{ TMM, Rzmm, Vex, Ib }, 0 },
+  },
+  /* PREFIX_EVEX_0F3A8F */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "top4mxbssps",	{ TMM, Rzmm, Vex, Ib }, 0 },
+  },
   /* PREFIX_EVEX_0F3AC2 */
   {
     { "vcmpp%XH", { MaskG, Vex, EXxh, EXxEVexS, CMP }, 0 },
@@ -833,6 +883,13 @@
     { Bad_Opcode },
     { "vfnmsub231p%XH",	{ XM, Vex, EXxh, EXxEVexR }, 0 },
   },
+  /* PREFIX_EVEX_MAP6_95 */
+  {
+    { VEX_W_TABLE (EVEX_W_MAP6_95_P_0) },
+    { VEX_W_TABLE (EVEX_W_MAP6_95_P_1) },
+    { Bad_Opcode },
+    { VEX_W_TABLE (EVEX_W_MAP6_95_P_3) },
+  },
   /* PREFIX_EVEX_MAP6_D6 */
   {
     { Bad_Opcode },
diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h
index 6e94bc45fe1..8e0529e1a08 100644
--- a/opcodes/i386-dis-evex-w.h
+++ b/opcodes/i386-dis-evex-w.h
@@ -349,6 +349,7 @@
   /* EVEX_W_0F384A_X86_64 */
   {
     { EVEX_LEN_TABLE (EVEX_LEN_0F384A_X86_64_W_0) },
+    { PREFIX_TABLE (PREFIX_EVEX_0F384A) },
   },
   /* EVEX_W_0F3859 */
   {
@@ -395,6 +396,7 @@
   /* EVEX_W_0F3A07_X86_64 */
   {
     { EVEX_LEN_TABLE (EVEX_LEN_0F3A07_X86_64_W_0) },
+    { PREFIX_TABLE (PREFIX_EVEX_0F3A07) },
   },
   /* EVEX_W_0F3A18_L_n */
   {
@@ -553,4 +555,19 @@
   {
     { "vbitrevb", { XM, EXx }, NO_PREFIX },
     { Bad_Opcode }
-  }
+  },
+  /* EVEX_W_MAP6_95_P_0 */
+  {
+    { Bad_Opcode },
+    { EVEX_LEN_TABLE (EVEX_LEN_MAP6_95_P_0_W_1) },
+  },
+  /* EVEX_W_MAP6_95_P_1 */
+  {
+    { "bsrmovl", { EXzmm, BSR }, 0 },
+    { "bsrmovl", { BSR, EXzmm }, 0 },
+  },
+  /* EVEX_W_MAP6_95_P_3 */
+  {
+    { "bsrmovh", { EXzmm, BSR }, 0 },
+    { "bsrmovh", { BSR, EXzmm }, 0 },
+  },
diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
index 7d555aa9e11..9ad57912231 100644
--- a/opcodes/i386-dis-evex.h
+++ b/opcodes/i386-dis-evex.h
@@ -377,7 +377,7 @@ static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { X86_64_EVEX_MEM_W_TABLE (VEX_W_0F3849_X86_64_L_0) },
     { X86_64_TABLE (X86_64_EVEX_0F384A) },
-    { X86_64_EVEX_MEM_W_TABLE (VEX_W_0F384B_X86_64_L_0) },
+    { EVEX_LEN_TABLE (EVEX_LEN_0F384B) },
     { "vrcp14p%XW",	{ XM, EXx }, PREFIX_DATA },
     { "vrcp14s%XW",	{ XMScalar, VexScalar, EXdq }, PREFIX_DATA },
     { "vrsqrt14p%XW",	{ XM, EXx }, 0 },
@@ -396,9 +396,9 @@ static const struct dis386 evex_table[][256] = {
     { VEX_W_TABLE (EVEX_W_0F3859) },
     { EVEX_LEN_TABLE (EVEX_LEN_0F385A) },
     { EVEX_LEN_TABLE (EVEX_LEN_0F385B) },
+    { PREFIX_TABLE (PREFIX_EVEX_0F385C) },
     { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_EVEX_0F385E) },
     { Bad_Opcode },
     /* 60 */
     { Bad_Opcode },
@@ -636,7 +636,7 @@ static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_EVEX_0F3A2F) },
     /* 30 */
     { Bad_Opcode },
     { Bad_Opcode },
@@ -742,9 +742,9 @@ static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_EVEX_0F3A8D) },
     { Bad_Opcode },
-    { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_EVEX_0F3A8F) },
     /* 90 */
     { Bad_Opcode },
     { Bad_Opcode },
@@ -1624,7 +1624,7 @@ static const struct dis386 evex_table[][256] = {
     { Bad_Opcode },
     { Bad_Opcode },
     { Bad_Opcode },
-    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_EVEX_MAP6_95) },
     { "vfmaddsub132p%XH",  { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
     { "vfmsubadd132p%XH",  { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
     /* 98 */
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 5643cfe55d5..f39774f2a83 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -70,6 +70,7 @@ static bool OP_D (instr_info *, int, int);
 static bool OP_T (instr_info *, int, int);
 static bool OP_MMX (instr_info *, int, int);
 static bool OP_XMM (instr_info *, int, int);
+static bool OP_BSR (instr_info *, int, int);
 static bool OP_EM (instr_info *, int, int);
 static bool OP_EX (instr_info *, int, int);
 static bool OP_EMC (instr_info *, int,int);
@@ -513,6 +514,7 @@ fetch_error (const instr_info *ins)
 #define RMBH { OP_REG, bh_reg }
 #define RMAX { OP_REG, ax_reg }
 #define RMDX { OP_REG, dx_reg }
+#define BSR { OP_BSR, bsr }
 
 #define eAX { OP_IMREG, eAX_reg }
 #define AL { OP_IMREG, al_reg }
@@ -566,6 +568,7 @@ fetch_error (const instr_info *ins)
 #define EXxS { OP_EX, x_swap_mode }
 #define EXxmm { OP_EX, xmm_mode }
 #define EXymm { OP_EX, ymm_mode }
+#define EXzmm { OP_EX, zmm_mode }
 #define EXxmmq { OP_EX, xmmq_mode }
 #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
@@ -583,6 +586,7 @@ fetch_error (const instr_info *ins)
 #define Uxmm { OP_R, xmm_mode }
 #define Rxmmq { OP_R, xmmq_mode }
 #define Rymm { OP_R, ymm_mode }
+#define Rzmm { OP_R, zmm_mode }
 #define Rtmm { OP_R, tmm_mode }
 #define EMCq { OP_EMC, q_mode }
 #define MXC { OP_MXC, 0 }
@@ -600,6 +604,7 @@ fetch_error (const instr_info *ins)
 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 #define VexGdq { OP_VEX, dq_mode }
 #define VexGb { OP_VEX, b_mode }
+#define VexGd { OP_VEX, d_mode }
 #define VexGv { OP_VEX, v_mode }
 #define VexTmm { OP_VEX, tmm_mode }
 #define XMVexI4 { OP_REG_VexI4, x_mode }
@@ -720,6 +725,8 @@ enum
   ymm_mode,
   /* quad word, ymmword or zmmword memory operand.  */
   ymmq_mode,
+  /* 64-byte ZMM operand */
+  zmm_mode,
   /* TMM operand */
   tmm_mode,
   /* d_mode in 32bit, q_mode in 64bit mode.  */
@@ -821,6 +828,8 @@ enum
   rSI_reg,
   rDI_reg,
 
+  bsr,
+
   z_mode_ax_reg,
   indir_dx_reg
 };
@@ -908,6 +917,7 @@ enum
   REG_VEX_0F73,
   REG_VEX_0FAE,
   REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0,
+  REG_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3,
   REG_VEX_0F38F3_L_0_P_0,
   REG_VEX_MAP7_F6_L_0_W_0,
   REG_VEX_MAP7_F8_L_0_W_0,
@@ -971,6 +981,7 @@ enum
   MOD_0F38F8,
 
   MOD_VEX_0F3849_X86_64_L_0_W_0,
+  MOD_VEX_0F3849_X86_64_L_0_W_1,
 
   MOD_EVEX_MAP4_60,
   MOD_EVEX_MAP4_61,
@@ -995,6 +1006,7 @@ enum
 
   RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0,
   RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3,
+  RM_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3_R_0,
 };
 
 enum
@@ -1141,6 +1153,7 @@ enum
   PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0,
   PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1,
   PREFIX_VEX_0F384A_X86_64_W_0_L_0,
+  PREFIX_VEX_0F3849_X86_64_L_0_W_1_M_1,
   PREFIX_VEX_0F384B_X86_64_L_0_W_0,
   PREFIX_VEX_0F3850_W_0,
   PREFIX_VEX_0F3851_W_0,
@@ -1213,8 +1226,12 @@ enum
   PREFIX_EVEX_0F383A,
   PREFIX_EVEX_0F3841,
   PREFIX_EVEX_0F384A_X86_64_W_0_L_2,
+  PREFIX_EVEX_0F384A,
+  PREFIX_EVEX_0F384B,
   PREFIX_EVEX_0F3852,
   PREFIX_EVEX_0F3853,
+  PREFIX_EVEX_0F385C,
+  PREFIX_EVEX_0F385E,
   PREFIX_EVEX_0F3868,
   PREFIX_EVEX_0F386D_X86_64_W_0_L_2,
   PREFIX_EVEX_0F3872,
@@ -1225,10 +1242,12 @@ enum
   PREFIX_EVEX_0F38AB,
 
   PREFIX_EVEX_0F3A07_X86_64_W_0_L_2,
+  PREFIX_EVEX_0F3A07,
   PREFIX_EVEX_0F3A08,
   PREFIX_EVEX_0F3A0A,
   PREFIX_EVEX_0F3A26,
   PREFIX_EVEX_0F3A27,
+  PREFIX_EVEX_0F3A2F,
   PREFIX_EVEX_0F3A42_W_0,
   PREFIX_EVEX_0F3A52,
   PREFIX_EVEX_0F3A53,
@@ -1237,6 +1256,8 @@ enum
   PREFIX_EVEX_0F3A66,
   PREFIX_EVEX_0F3A67,
   PREFIX_EVEX_0F3A77_X86_64_W_0_L_2,
+  PREFIX_EVEX_0F3A8D,
+  PREFIX_EVEX_0F3A8F,
   PREFIX_EVEX_0F3AC2,
 
   PREFIX_EVEX_MAP4_4x,
@@ -1310,6 +1331,7 @@ enum
   PREFIX_EVEX_MAP6_BA,
   PREFIX_EVEX_MAP6_BC,
   PREFIX_EVEX_MAP6_BE,
+  PREFIX_EVEX_MAP6_95,
   PREFIX_EVEX_MAP6_D6,
   PREFIX_EVEX_MAP6_D7,
 };
@@ -1601,6 +1623,7 @@ enum
   EVEX_LEN_0F381B,
   EVEX_LEN_0F3836,
   EVEX_LEN_0F384A_X86_64_W_0,
+  EVEX_LEN_0F384B,
   EVEX_LEN_0F385A,
   EVEX_LEN_0F385B,
   EVEX_LEN_0F386D_X86_64_W_0,
@@ -1625,6 +1648,7 @@ enum
   EVEX_LEN_MAP5_7E,
   EVEX_LEN_MAP6_80_W_0,
   EVEX_LEN_MAP6_80_W_1,
+  EVEX_LEN_MAP6_95_P_0_W_1,
 };
 
 enum
@@ -1884,6 +1908,9 @@ enum
   EVEX_W_MAP5_7E_P_1,
   EVEX_W_MAP6_80,
   EVEX_W_MAP6_81,
+  EVEX_W_MAP6_95_P_0,
+  EVEX_W_MAP6_95_P_1,
+  EVEX_W_MAP6_95_P_3,
 };
 
 typedef bool (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
@@ -2709,6 +2736,10 @@ static const char att_names_tmm[][8] = {
   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
 };
 
+static const char att_names_bsr[][8] = {
+  "%bsr0"
+};
+
 static const char att_names_mask[][8] = {
   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
 };
@@ -3095,6 +3126,10 @@ static const struct dis386 reg_table[][8] = {
   {
     { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0) },
   },
+  /* REG_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3 */
+  {
+    { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3_R_0) },
+  },
   /* REG_VEX_0F38F3_L_0_P_0 */
   {
     { Bad_Opcode },
@@ -4176,6 +4211,14 @@ static const struct dis386 prefix_table[][4] = {
     { "tileloaddrs",	{ TMM, MVexSIBMEM }, 0 },
   },
 
+  /* PREFIX_VEX_0F3849_X86_64_L_0_W_1_M_1 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { REG_TABLE (REG_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3) },
+  },
+
   /* PREFIX_VEX_0F384B_X86_64_L_0_W_0 */
   {
     { Bad_Opcode },
@@ -8107,6 +8150,7 @@ static const struct dis386 vex_w_table[][2] = {
   {
     /* VEX_W_0F3849_X86_64_L_0 */
     { MOD_TABLE (MOD_VEX_0F3849_X86_64_L_0_W_0) },
+    { MOD_TABLE (MOD_VEX_0F3849_X86_64_L_0_W_1) },
   },
   {
     /* VEX_W_0F384A_X86_64 */
@@ -8683,6 +8727,11 @@ static const struct dis386 mod_table[][2] = {
     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) },
     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1) },
   },
+  {
+    /* MOD_VEX_0F3849_X86_64_L_0_W_1 */
+    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_1_M_1) },
+  },
 
 #include "i386-dis-evex-mod.h"
 };
@@ -8793,6 +8842,10 @@ static const struct dis386 rm_table[][8] = {
     /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3 */
     { "tilezero",	{ TMM, Skip_MODRM }, 0 },
   },
+  {
+    /* RM_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3_R_0 */
+    { "bsrinit",	{ BSR, Skip_MODRM }, 0 },
+  },
 };
 
 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
@@ -11920,6 +11973,9 @@ intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
     case ymm_mode:
       oappend (ins, "YMMWORD PTR ");
       break;
+    case zmm_mode:
+      oappend (ins, "ZMMWORD PTR ");
+      break;
     case xmmq_mode:
     case evex_half_bcst_xmmqh_mode:
     case evex_half_bcst_xmmq_mode:
@@ -12357,6 +12413,9 @@ OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
 	  else if (bytemode == xmmdw_mode)
 	    shift -= 3;
 	  break;
+	case zmm_mode:
+	  shift = 6;
+	  break;
 	case ymm_mode:
 	  shift = 5;
 	  break;
@@ -13407,6 +13466,8 @@ print_vector_reg (instr_info *ins, unsigned int reg, int bytemode)
 	  abort ();
 	}
     }
+  else if (bytemode == zmm_mode)
+    names = att_names_zmm;
   else if (bytemode == ymm_mode)
     names = att_names_ymm;
   else if (bytemode == tmm_mode)
@@ -13482,6 +13543,18 @@ OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
   return true;
 }
 
+static bool
+OP_BSR (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
+{
+  if (ins->modrm.reg)
+    {
+      oappend (ins, "(bad)");
+      return false;
+    }
+  oappend_register (ins, att_names_bsr[0]);
+  return true;
+}
+
 static bool
 OP_EM (instr_info *ins, int bytemode, int sizeflag)
 {
@@ -14252,9 +14325,45 @@ OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
 	}
       break;
     case 512:
-      names = att_names_zmm;
-      ins->evex_used |= EVEX_len_used;
-      break;
+      switch (bytemode)
+	{
+	case x_mode:
+	case v_mode:
+	  names = att_names_zmm;
+	  ins->evex_used |= EVEX_len_used;
+	  break;
+	case dq_mode:
+	  if (ins->rex & REX_W)
+	    names = att_names64;
+	  else if (bytemode == v_mode
+		   && !(sizeflag & DFLAG))
+	    names = att_names16;
+	  else
+	    names = att_names32;
+	  break;
+	case b_mode:
+	  names = att_names8rex;
+	  break;
+	case d_mode:
+	  names = att_names32;
+	  break;
+	case q_mode:
+	  names = att_names64;
+	  break;
+	case mask_bd_mode:
+	case mask_mode:
+	  if (reg > 0x7)
+	    {
+	      oappend (ins, "(bad)");
+	      return true;
+	    }
+	  names = att_names_mask;
+	  break;
+	default:
+	  abort ();
+	  return true;
+	}
+	break;
     default:
       abort ();
       break;
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 11cc4ff19dc..dded2d906e6 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -263,6 +263,8 @@ static const dependency isa_dependencies[] =
     "RTM|HLE" },
   { "TSXLDTRK",
     "RTM" },
+  { "ACE",
+    "AVX512F|64" },
   { "AMX_TILE",
     "XSAVE|64" },
   { "AMX_INT8",
@@ -470,6 +472,7 @@ static bitfield cpu_flags[] =
   BITFIELD (WAITPKG),
   BITFIELD (UINTR),
   BITFIELD (CLDEMOTE),
+  BITFIELD (ACE),
   BITFIELD (AMX_INT8),
   BITFIELD (AMX_BF16),
   BITFIELD (AMX_FP16),
@@ -571,6 +574,7 @@ static const struct {
   CLASS (RegSIMD),
   CLASS (RegMask),
   CLASS (RegBND),
+  CLASS (RegBS),
 };
 
 #undef CLASS
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 0c5f7747ed2..a8d9ac59c8b 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -359,6 +359,8 @@ enum i386_cpu
   CpuAVX10_2,
   /* Intel AMX-TRANSPOSE Instructions support required.  */
   CpuAMX_TRANSPOSE,
+  /* ACE instructions support required.  */
+  CpuACE,
   /* Not supported in the 64bit mode  */
   CpuNo64,
 
@@ -397,6 +399,7 @@ enum i386_cpu
 		   cpuapx_f:1, \
 		   cpuavx10_2:1, \
 		   cpuamx_transpose:1, \
+		   cpuace:1, \
       /* NOTE: This field needs to remain last. */ \
 		   cpuno64:1
 
@@ -889,6 +892,7 @@ enum operand_class
   RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
   RegMask, /* Vector Mask register */
   RegBND, /* Bound register */
+  RegBS, /* Block scale register */
 };
 
 /* Special operand instances.  */
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 3d3e37b09aa..b85afcf5720 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -62,6 +62,8 @@
 
 #define RegBND Class=RegBND
 
+#define RegBS Class=RegBS
+
 #define Mmword Qword
 #define Oword  Xmmword
 
@@ -118,6 +120,7 @@
 #define SpaceXOP0A OpcodeSpace=SPACE_XOP0A
 
 #define EVexMap4 OpcodeSpace=SPACE_MAP4|EVex128
+#define EVexMap6 OpcodeSpace=SPACE_MAP6
 
 #define Map5 OpcodeSpace=SPACE_MAP5
 #define Map6 OpcodeSpace=SPACE_MAP6
@@ -3234,10 +3237,12 @@ xresldtrk, 0xf20f01e9, TSXLDTRK, NoSuf, {}
 
 // TSXLDTRK instructions end.
 
-// AMX instructions.
+// AMX & ACE instructions.
 
 ldtilecfg, 0x49/0, APX_F(AMX_TILE), Modrm|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex }
+ldtilecfg, 0x49/0, ACE, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex }
 sttilecfg, 0x6649/0, APX_F(AMX_TILE), Modrm|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex }
+sttilecfg, 0x6649/0, ACE, Modrm|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex }
 
 tcmmimfp16ps, 0x666c, AMX_COMPLEX, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
 tcmmrlfp16ps, 0x6c, AMX_COMPLEX, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
@@ -3250,14 +3255,18 @@ tdpbusd, 0x665e, AMX_INT8, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM
 tdpbsud, 0xf35e, AMX_INT8, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
 
 tileloadd, 0xf24b, APX_F(AMX_TILE), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
+tileloadd, 0xf24b, ACE, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
 tileloaddt1, 0x664b, APX_F(AMX_TILE), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
+tileloaddt1, 0x664b, ACE, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
 tileloaddrs, 0xf24a, APX_F(AMX_MOVRS), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
 tileloaddrst1, 0x664a, APX_F(AMX_MOVRS), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
 tilestored, 0xf34b, APX_F(AMX_TILE), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { RegTMM, Unspecified|BaseIndex }
+tilestored, 0xf34b, ACE, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { RegTMM, Unspecified|BaseIndex }
 
 tilerelease, 0x49c0, AMX_TILE, Vex128|Space0F38|VexW0|NoSuf, {}
+tilerelease, 0x49c0, ACE, Vex128|Space0F38|VexW0|NoSuf, {}
 
-tilezero, 0xf249, AMX_TILE, Modrm|Vex128|Space0F38|VexW0|NoSuf, { RegTMM }
+tilezero, 0xf249, AMX_TILE|ACE, Modrm|Vex128|Space0F38|VexW0|NoSuf, { RegTMM }
 
 <z:pfx, z0:, z1:66>
 
@@ -3288,22 +3297,51 @@ tdpbhf8ps, 0xf2fd, AMX_FP8, Modrm|Vex128|Map5|Src2VVVV|VexW0|NoSuf, { RegTMM, Re
 tdphbf8ps, 0xf3fd, AMX_FP8, Modrm|Vex128|Map5|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
 tdphf8ps, 0x66fd, AMX_FP8, Modrm|Vex128|Map5|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
 
-tcvtrowd2ps, 0xf34a, AMX_AVX512, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
-tcvtrowd2ps, 0xf307, AMX_AVX512, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
+tcvtrowd2ps, 0xf34a, AMX_AVX512|ACE, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
+tcvtrowd2ps, 0xf307, AMX_AVX512|ACE, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
+
+tcvtrowps2bf16h, 0xf26d, AMX_AVX512|ACE, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
+tcvtrowps2bf16h, 0xf207, AMX_AVX512|ACE, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
+tcvtrowps2bf16l, 0xf36d, AMX_AVX512|ACE, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
+tcvtrowps2bf16l, 0xf377, AMX_AVX512|ACE, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
+tcvtrowps2phh, 0x6d, AMX_AVX512|ACE, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
+tcvtrowps2phh, 0x07, AMX_AVX512|ACE, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
+tcvtrowps2phl, 0x666d, AMX_AVX512|ACE, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
+tcvtrowps2phl, 0xf277, AMX_AVX512|ACE, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
+
+tilemovrow, 0x664a, AMX_AVX512|ACE, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
+tilemovrow, 0x6607, AMX_AVX512|ACE, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
+
+// AMX & ACE instructions end.
+
+// ACE instructions.
+
+bsrinit, 0xf249, ACE, Modrm|Vex128|Space0F38|VexW1|NoSuf, { RegBS }
+bsrmovf, 0x95, ACE, Modrm|EVex512|EVexMap6|VexW1|Src1VVVV|NoSuf, { RegZMM|Unspecified|BaseIndex, RegZMM, RegBS }
+bsrmovh, 0xf295, ACE, Modrm|EVex512|EVexMap6|VexW1|NoSuf, { RegZMM|Unspecified|BaseIndex, RegBS }
+bsrmovh, 0xf295, ACE, RegMem|Modrm|EVex512|EVexMap6|VexW0|NoSuf, { RegBS, RegZMM|Unspecified|BaseIndex }
+bsrmovl, 0xf395, ACE, Modrm|EVex512|EVexMap6|VexW1|NoSuf, { RegZMM|Unspecified|BaseIndex, RegBS }
+bsrmovl, 0xf395, ACE, RegMem|Modrm|EVex512|EVexMap6|VexW0|NoSuf, { RegBS, RegZMM|Unspecified|BaseIndex }
+
+tilemovcol, 0x662f, ACE, Modrm|EVex512|Space0F3A|VexW1|NoSuf, { Imm8, RegZMM, RegTMM }
+tilemovcol, 0x664b, ACE, Modrm|EVex512|Space0F38|VexW1|Src2VVVV|NoSuf, { Reg32, RegZMM, RegTMM }
+tilemovrow, 0x6607, ACE, Modrm|EVex512|Space0F3A|VexW1|NoSuf, { Imm8, RegZMM, RegTMM }
+tilemovrow, 0x664a, ACE, Modrm|EVex512|Space0F38|VexW1|Src2VVVV|NoSuf, { Reg32, RegZMM, RegTMM }
+
+top2bf16ps, 0xf35c, ACE, Modrm|EVex512|Space0F38|VexW0|Src2VVVV|NoSuf, { RegZMM, RegZMM, RegTMM }
 
-tcvtrowps2bf16h, 0xf26d, AMX_AVX512, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
-tcvtrowps2bf16h, 0xf207, AMX_AVX512, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
-tcvtrowps2bf16l, 0xf36d, AMX_AVX512, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
-tcvtrowps2bf16l, 0xf377, AMX_AVX512, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
-tcvtrowps2phh, 0x6d, AMX_AVX512, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
-tcvtrowps2phh, 0x07, AMX_AVX512, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
-tcvtrowps2phl, 0x666d, AMX_AVX512, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
-tcvtrowps2phl, 0xf277, AMX_AVX512, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
+top4bssd, 0xf25e, ACE, Modrm|EVex512|Space0F38|VexW0|Src2VVVV|NoSuf, { RegZMM, RegZMM, RegTMM }
+top4bsud, 0xf35e, ACE, Modrm|EVex512|Space0F38|VexW0|Src2VVVV|NoSuf, { RegZMM, RegZMM, RegTMM }
+top4busd, 0x665e, ACE, Modrm|EVex512|Space0F38|VexW0|Src2VVVV|NoSuf, { RegZMM, RegZMM, RegTMM }
+top4buud, 0x5e, ACE, Modrm|EVex512|Space0F38|VexW0|Src2VVVV|NoSuf, { RegZMM, RegZMM, RegTMM }
 
-tilemovrow, 0x664a, AMX_AVX512, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
-tilemovrow, 0x6607, AMX_AVX512, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
+top4mxbf8ps, 0x8d, ACE, Modrm|EVex512|Space0F3A|VexW0|Src2VVVV|NoSuf, { Imm8, RegZMM, RegZMM, RegTMM }
+top4mxbhf8ps, 0xf28d, ACE, Modrm|EVex512|Space0F3A|VexW0|Src2VVVV|NoSuf, { Imm8, RegZMM, RegZMM, RegTMM }
+top4mxhbf8ps, 0xf38d, ACE, Modrm|EVex512|Space0F3A|VexW0|Src2VVVV|NoSuf, { Imm8, RegZMM, RegZMM, RegTMM }
+top4mxhf8ps, 0x668d, ACE, Modrm|EVex512|Space0F3A|VexW0|Src2VVVV|NoSuf, { Imm8, RegZMM, RegZMM, RegTMM }
+top4mxbssps, 0xf28f, ACE, Modrm|EVex512|Space0F3A|VexW0|Src2VVVV|NoSuf, { Imm8, RegZMM, RegZMM, RegTMM }
 
-// AMX instructions end.
+// ACE instructions end.
 
 // KEYLOCKER instructions.
 
diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl
index 74234c503d6..ee6923252c9 100644
--- a/opcodes/i386-reg.tbl
+++ b/opcodes/i386-reg.tbl
@@ -344,7 +344,7 @@ zmm28, Class=RegSIMD|Zmmword, RegVRex|RegRex, 4, Dw2Inval, 79
 zmm29, Class=RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval, 80
 zmm30, Class=RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, 81
 zmm31, Class=RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, 82
-// TMM registers for AMX
+// TMM registers for AMX/ACE
 tmm0, Class=RegSIMD|Tmmword, 0, 0, Dw2Inval, Dw2Inval
 tmm1, Class=RegSIMD|Tmmword, 0, 1, Dw2Inval, Dw2Inval
 tmm2, Class=RegSIMD|Tmmword, 0, 2, Dw2Inval, Dw2Inval
@@ -353,6 +353,8 @@ tmm4, Class=RegSIMD|Tmmword, 0, 4, Dw2Inval, Dw2Inval
 tmm5, Class=RegSIMD|Tmmword, 0, 5, Dw2Inval, Dw2Inval
 tmm6, Class=RegSIMD|Tmmword, 0, 6, Dw2Inval, Dw2Inval
 tmm7, Class=RegSIMD|Tmmword, 0, 7, Dw2Inval, Dw2Inval
+// Block scale register for ACE
+bsr0, Class=RegBS, 0, 0, Dw2Inval, Dw2Inval
 // Bound registers for MPX
 bnd0, Class=RegBND, 0, 0, Dw2Inval, 126
 bnd1, Class=RegBND, 0, 1, Dw2Inval, 127
-- 
2.53.0


From chendongyan@isrc.iscas.ac.cn  Sat Jun 27 14:45:17 2026
From: chendongyan@isrc.iscas.ac.cn (Dongyan Chen)
Date: Sat, 27 Jun 2026 14:45:17 +0000
Subject: [PATCH 1/1] RISC-V: Add support for zama16b extension.
Message-ID: <20260627144517.3442618-1-chendongyan@isrc.iscas.ac.cn>

This patch adds minimal support for the RISC-V Zama16b extension, version 1.0[1].

[1] https://github.com/riscv/riscv-isa-manual/blob/main/src/unpriv/zama.adoc

bfd/ChangeLog:

	* elfxx-riscv.c: Add zama16b extension.

gas/ChangeLog:

	* NEWS: Add zama16b extension.
	* testsuite/gas/riscv/march-help.l: Ditto.

---
 bfd/elfxx-riscv.c                    | 1 +
 gas/NEWS                             | 2 ++
 gas/testsuite/gas/riscv/march-help.l | 1 +
 3 files changed, 4 insertions(+)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 961c44a9206..3b5a944e9c4 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1483,6 +1483,7 @@ static const struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zaamo",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zabha",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zacas",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"zama16b",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zalasr",           ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zalrsc",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zawrs",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
diff --git a/gas/NEWS b/gas/NEWS
index 4c55a544f25..3531a917d86 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -11,6 +11,8 @@
 * Add support for RISC-V vendor extensions:
   SpacemiT: xsmtvdot v1.0, xsmtvdotii v1.0.
 
+* Add support for RISC-V zama16b extension with version 1.0.
+
 Changes in 2.46:
 
 * Add support for AMD Zen6 processor.
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index db6a86bc287..f3b99993394 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -37,6 +37,7 @@ All available -march extensions for RISC-V:
 	zacas                                   1.0
 	zalasr                                  1.0
 	zalrsc                                  1.0
+	zama16b                                 1.0
 	zawrs                                   1.0
 	zfbfmin                                 1.0
 	zfa                                     1.0
-- 
2.34.1


From chendongyan@isrc.iscas.ac.cn  Sat Jun 27 15:05:13 2026
From: chendongyan@isrc.iscas.ac.cn (Dongyan Chen)
Date: Sat, 27 Jun 2026 15:05:13 +0000
Subject: [PATCH] RISC-V: Add support for ziccamoc extension.
Message-ID: <20260627150513.3464679-1-chendongyan@isrc.iscas.ac.cn>

This patch adds minimal support for the RISC-V Ziccamoc extension, version 1.0[1].

[1] https://github.com/riscv/riscv-isa-manual/blob/main/src/unpriv/ziccamoc.adoc

bfd/ChangeLog:

	* elfxx-riscv.c: Add ziccamoc extension.

gas/ChangeLog:

	* NEWS: Add ziccamoc extension.
	* testsuite/gas/riscv/march-help.l: Ditto.

---
 bfd/elfxx-riscv.c                    | 1 +
 gas/NEWS                             | 2 ++
 gas/testsuite/gas/riscv/march-help.l | 1 +
 3 files changed, 4 insertions(+)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 961c44a9206..9053719ee5b 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1458,6 +1458,7 @@ static const struct riscv_supported_ext riscv_supported_std_z_ext[] =
 {
   {"zic64b",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"ziccamoa",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"ziccamoc",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"ziccif",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zicclsm",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"ziccrse",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
diff --git a/gas/NEWS b/gas/NEWS
index 4c55a544f25..ab2d44a10f9 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -11,6 +11,8 @@
 * Add support for RISC-V vendor extensions:
   SpacemiT: xsmtvdot v1.0, xsmtvdotii v1.0.

+* Add support for RISC-V ziccamoc extension with version 1.0.
+
 Changes in 2.46:

 * Add support for AMD Zen6 processor.
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index db6a86bc287..7def0ff801e 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -12,6 +12,7 @@ All available -march extensions for RISC-V:
 	h                                       1.0
 	zic64b                                  1.0
 	ziccamoa                                1.0
+	ziccamoc                                1.0
 	ziccif                                  1.0
 	zicclsm                                 1.0
 	ziccrse                                 1.0
--
2.34.1


From zhuangqiubin@linux.spacemit.com  Sat Jun 27 16:32:53 2026
From: zhuangqiubin@linux.spacemit.com (Mark Zhuang)
Date: Sun, 28 Jun 2026 00:32:53 +0800
Subject: [PATCH v3] RISC-V: Fix build with GCC-8
In-Reply-To: <dc6104a6-70d6-443a-9605-993bfb1c7851@suse.com>
References: <f2abf263-4730-4ccd-af87-e3de2289b35c@suse.com>
 <20260623133508.2896582-1-zhuangqiubin@linux.spacemit.com>
 <alpine.DEB.2.21.2606252232520.58268@angie.orcam.me.uk>
 <7f84f26f-9f88-4690-8f61-e7e893831f65@suse.com>
 <alpine.DEB.2.21.2606261151490.58268@angie.orcam.me.uk>
 <dc6104a6-70d6-443a-9605-993bfb1c7851@suse.com>
Message-ID: <20260627163253.1673970-1-zhuangqiubin@linux.spacemit.com>

Hi Jan, Maciej,

I redid some testing, and this build error reproduces with both gcc-9.4.0
and gcc-10.5.0; in both cases it is fixed by this patch.

Please feel free to adjust the commit message as needed when committing,
as well as the break/continue placement discussed earlier.

Thanks a lot,
Mark

From amodra@gmail.com  Sun Jun 28 02:51:01 2026
From: amodra@gmail.com (Alan Modra)
Date: Sun, 28 Jun 2026 12:21:01 +0930
Subject: asan: buffer overflow in m32r_elf_generic_reloc
Message-ID: <akCMFdaP2DDrktRo@squeak.grove.modra.org>

The existing sanity check didn't take into account the size of the
reloc field.  So a field that started before the end of section, but
extended past it, accessed past the end of the contents buffer.

	* elf32-m32r.c (m32r_elf_generic_reloc): Properly check reloc
	offset.
	(m32r_elf_do_10_pcrel_reloc): Likewise.

diff --git a/bfd/elf32-m32r.c b/bfd/elf32-m32r.c
index 80a1b1eaa7a..1219d9b04fc 100644
--- a/bfd/elf32-m32r.c
+++ b/bfd/elf32-m32r.c
@@ -98,7 +98,7 @@ m32r_elf_do_10_pcrel_reloc (bfd *abfd,
   bfd_reloc_status_type status;
 
   /* Sanity check the address (offset in section).  */
-  if (offset > bfd_get_section_limit (abfd, input_section))
+  if (!bfd_reloc_offset_in_range (howto, abfd, input_section, offset))
     return bfd_reloc_outofrange;
 
   relocation = symbol_value + addend;
@@ -192,7 +192,8 @@ m32r_elf_generic_reloc (bfd *input_bfd,
      a section relative addend which is wrong.  */
 
   /* Sanity check the address (offset in section).  */
-  if (reloc_entry->address > bfd_get_section_limit (input_bfd, input_section))
+  if (!bfd_reloc_offset_in_range (reloc_entry->howto, input_bfd,
+				  input_section, reloc_entry->address))
     return bfd_reloc_outofrange;
 
   ret = bfd_reloc_ok;

-- 
Alan Modra

From amodra@gmail.com  Sun Jun 28 02:51:55 2026
From: amodra@gmail.com (Alan Modra)
Date: Sun, 28 Jun 2026 12:21:55 +0930
Subject: asan: use of uninitialised value in s_ifeqs
Message-ID: <akCMS7j2mROTsVIV@squeak.grove.modra.org>

demand_copy_string returns NULL when a double-quoted string is not
found, and calls ignore_rest_of_line.  demand_copy_C_string can also
return NULL when finding an embedded \0, but doesn't call
ignore_rest_of_line for this condition.  This makes it difficult to
handle errors.

I believe ignore_rest_of_line should only be called at the level of
functions handling an entire line.  It will typically appear then only
in functions that call demand_empty_rest_of_line.  So this patch
removes the ignore_rest_of_file call in demand_copy_string, moving it
to callers of these functions.  Missing error handling is added in the
second part of the changelog below.

	* read.c (demand_copy_string): Don't call ignore_rest_of_file.
	(demand_copy_C_string): Don't zero length on error.
	(s_file, s_incbin, s_include): Call ignore_rest_of_file on
	demand_copy_string error.
	(s_errwarn, s_print): Call ignore_rest_of_file on
	demand_copy_C_string error.
	(s_linefile): Move ignore_rest_of_line call for negative linenum
	earlier and similarly for missing file, reducing block
	indentation.
	* config/tc-tic54x.c (tic54x_mlib): Call ignore_rest_of_line
	after demand_copy_C_string error.
	* dwarf2dbg.c (dwarf2_directive_filename): Likewise.
	* stabs.c (s_stab_generic, s_xstab): Likewise.

	* cond.c (s_ifeqs): Handle NULL return from demand_copy_C_string.
	* config/tc-ia64.c (dot_pred_rel): Likewise.
	* config/tc-ppc.c (ppc_rename, ppc_stabx, ppc_biei, ppc_bc): Likewise.
	* config/tc-tic54x.c (tic54x_asg, tic54x_sect, tic54x_include),
	(tic54x_message, tic54x_sblock, subsym_get_arg): Likewise.
	* ecoff.c (ecoff_directive_file): Likewise.
	* config/tc-alpha.c (s_alpha_file): Handle NULL return from
	demand_copy_string.
	* config/tc-ppc.c (ppc_file): Likewise.

diff --git a/gas/cond.c b/gas/cond.c
index 53c6e3e459b..300bb270f76 100644
--- a/gas/cond.c
+++ b/gas/cond.c
@@ -460,6 +460,11 @@ s_ifeqs (int arg)
   struct conditional_frame cframe;
 
   s1 = demand_copy_C_string (&len1);
+  if (s1 == NULL)
+    {
+      ignore_rest_of_line ();
+      return;
+    }
 
   SKIP_WHITESPACE ();
   if (*input_line_pointer != ',')
@@ -472,6 +477,11 @@ s_ifeqs (int arg)
   ++input_line_pointer;
 
   s2 = demand_copy_C_string (&len2);
+  if (s2 == NULL)
+    {
+      ignore_rest_of_line ();
+      return;
+    }
 
   res = len1 == len2 && strncmp (s1, s2, len1) == 0;
 
diff --git a/gas/config/tc-alpha.c b/gas/config/tc-alpha.c
index f2acb22da5f..f9f04a8389e 100644
--- a/gas/config/tc-alpha.c
+++ b/gas/config/tc-alpha.c
@@ -4785,6 +4785,7 @@ static void
 s_alpha_file (int ignore ATTRIBUTE_UNUSED)
 {
   symbolS *s;
+  char *name;
   int length;
   static char case_hack[32];
 
@@ -4795,7 +4796,13 @@ s_alpha_file (int ignore ATTRIBUTE_UNUSED)
   symbol_get_bfdsym (s)->flags |= BSF_FILE;
 
   get_absolute_expression ();
-  s = symbol_find_or_make (demand_copy_string (&length));
+  name = demand_copy_string (&length);
+  if (name == NULL)
+    {
+      ignore_rest_of_line ();
+      return;
+    }
+  s = symbol_find_or_make (name);
   symbol_get_bfdsym (s)->flags |= BSF_FILE;
   demand_empty_rest_of_line ();
 }
diff --git a/gas/config/tc-ia64.c b/gas/config/tc-ia64.c
index d90780c9d04..a5cfa46fe34 100644
--- a/gas/config/tc-ia64.c
+++ b/gas/config/tc-ia64.c
@@ -4990,6 +4990,11 @@ dot_pred_rel (int type)
 	{
 	  int len;
 	  char *form = demand_copy_C_string (&len);
+	  if (form == NULL)
+	    {
+	      ignore_rest_of_line ();
+	      return;
+	    }
 
 	  if (strcmp (form, "mutex") == 0)
 	    type = 'm';
diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 78e5941484c..b82ba2eaebd 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -5059,8 +5059,14 @@ ppc_rename (int ignore ATTRIBUTE_UNUSED)
     }
   ++input_line_pointer;
 
-  symbol_get_tc (sym)->real_name = demand_copy_C_string (&len);
+  name = demand_copy_C_string (&len);
+  if (name == NULL)
+    {
+      ignore_rest_of_line ();
+      return;
+    }
 
+  symbol_get_tc (sym)->real_name = name;
   demand_empty_rest_of_line ();
 }
 
@@ -5080,6 +5086,11 @@ ppc_stabx (int ignore ATTRIBUTE_UNUSED)
   expressionS exp;
 
   name = demand_copy_C_string (&len);
+  if (name == NULL)
+    {
+      ignore_rest_of_line ();
+      return;
+    }
 
   if (*input_line_pointer != ',')
     {
@@ -5199,56 +5210,75 @@ ppc_file (int ignore ATTRIBUTE_UNUSED)
 {
   char *sfname, *s1 = NULL, *s2 = NULL, *s3 = NULL;
   int length, auxnb = 1;
+  coff_symbol_type *coffsym;
 
   /* Some assemblers tolerate immediately following '"'.  */
-  if ((sfname = demand_copy_string (&length)) != 0)
+  sfname = demand_copy_string (&length);
+  if (sfname == NULL)
+    {
+      ignore_rest_of_line ();
+      return;
+    }
+
+  if (*input_line_pointer == ',')
     {
-      coff_symbol_type *coffsym;
+      ++input_line_pointer;
+      s1 = demand_copy_string (&length);
+      if (s1 == NULL)
+	{
+	  ignore_rest_of_line ();
+	  return;
+	}
+      auxnb++;
+
       if (*input_line_pointer == ',')
 	{
 	  ++input_line_pointer;
-	  s1 = demand_copy_string (&length);
+	  s2 = demand_copy_string (&length);
+	  if (s2 == NULL)
+	    {
+	      ignore_rest_of_line ();
+	      return;
+	    }
 	  auxnb++;
 
 	  if (*input_line_pointer == ',')
 	    {
 	      ++input_line_pointer;
-	      s2 = demand_copy_string (&length);
-	      auxnb++;
-
-	      if (*input_line_pointer == ',')
+	      s3 = demand_copy_string (&length);
+	      if (s3 == NULL)
 		{
-		  ++input_line_pointer;
-		  s3 = demand_copy_string (&length);
-		  auxnb++;
+		  ignore_rest_of_line ();
+		  return;
 		}
+	      auxnb++;
 	    }
 	}
+    }
 
-      /* Use coff dot_file creation and adjust auxiliary entries.  */
-      c_dot_file_symbol (sfname);
-      S_SET_NUMBER_AUXILIARY (symbol_rootP, auxnb);
-      coffsym = coffsymbol (symbol_get_bfdsym (symbol_rootP));
-      coffsym->native[1].u.auxent.x_file.x_ftype = XFT_FN;
-
-      if (s1)
-	{
-	  coffsym->native[2].u.auxent.x_file.x_ftype = XFT_CT;
-	  coffsym->native[2].extrap = s1;
-	}
-      if (s2)
-	{
-	  coffsym->native[3].u.auxent.x_file.x_ftype = XFT_CV;
-	  coffsym->native[3].extrap = s2;
-	}
-      if (s3)
-	{
-	  coffsym->native[4].u.auxent.x_file.x_ftype = XFT_CD;
-	  coffsym->native[4].extrap = s3;
-	}
+  /* Use coff dot_file creation and adjust auxiliary entries.  */
+  c_dot_file_symbol (sfname);
+  S_SET_NUMBER_AUXILIARY (symbol_rootP, auxnb);
+  coffsym = coffsymbol (symbol_get_bfdsym (symbol_rootP));
+  coffsym->native[1].u.auxent.x_file.x_ftype = XFT_FN;
 
-      demand_empty_rest_of_line ();
+  if (s1)
+    {
+      coffsym->native[2].u.auxent.x_file.x_ftype = XFT_CT;
+      coffsym->native[2].extrap = s1;
+    }
+  if (s2)
+    {
+      coffsym->native[3].u.auxent.x_file.x_ftype = XFT_CV;
+      coffsym->native[3].extrap = s2;
+    }
+  if (s3)
+    {
+      coffsym->native[4].u.auxent.x_file.x_ftype = XFT_CD;
+      coffsym->native[4].extrap = s3;
     }
+
+  demand_empty_rest_of_line ();
 }
 
 /* The .function pseudo-op.  This takes several arguments.  The first
@@ -5414,6 +5444,11 @@ ppc_biei (int ei)
   symbolS *look;
 
   name = demand_copy_C_string (&len);
+  if (name == NULL)
+    {
+      ignore_rest_of_line ();
+      return;
+    }
 
   /* The value of these symbols is actually file offset.  Here we set
      the value to the index into the line number entries.  In
@@ -5573,6 +5608,12 @@ ppc_bc (int ignore ATTRIBUTE_UNUSED)
   symbolS *sym;
 
   name = demand_copy_C_string (&len);
+  if (name == NULL)
+    {
+      ignore_rest_of_line ();
+      return;
+    }
+
   sym = symbol_make (name);
   S_SET_SEGMENT (sym, ppc_coff_debug_section);
   symbol_get_bfdsym (sym)->flags |= BSF_DEBUGGING;
diff --git a/gas/config/tc-tic54x.c b/gas/config/tc-tic54x.c
index 7b3b0738a1f..b53571251c4 100644
--- a/gas/config/tc-tic54x.c
+++ b/gas/config/tc-tic54x.c
@@ -353,6 +353,11 @@ tic54x_asg (int x ATTRIBUTE_UNUSED)
     {
       int len;
       str = demand_copy_C_string (&len);
+      if (str == NULL)
+	{
+	  ignore_rest_of_line ();
+	  return;
+	}
       c = *input_line_pointer;
     }
   else
@@ -1227,6 +1232,11 @@ tic54x_sect (int arg)
       if (*input_line_pointer == '"')
 	{
 	  name = demand_copy_C_string (&len);
+	  if (name == NULL)
+	    {
+	      ignore_rest_of_line ();
+	      return;
+	    }
 	  demand_empty_rest_of_line ();
 	  name = concat (name, flags, (char *) NULL);
 	}
@@ -1946,6 +1956,11 @@ tic54x_include (int ignored ATTRIBUTE_UNUSED)
   if (*input_line_pointer == '"')
     {
       filename = demand_copy_C_string (&len);
+      if (filename == NULL)
+	{
+	  ignore_rest_of_line ();
+	  return;
+	}
       demand_empty_rest_of_line ();
     }
   else
@@ -1983,7 +1998,14 @@ tic54x_message (int type)
   ILLEGAL_WITHIN_STRUCT ();
 
   if (*input_line_pointer == '"')
-    msg = demand_copy_C_string (&len);
+    {
+      msg = demand_copy_C_string (&len);
+      if (msg == NULL)
+	{
+	  ignore_rest_of_line ();
+	  return;
+	}
+    }
   else
     {
       msg = input_line_pointer;
@@ -2152,6 +2174,11 @@ tic54x_sblock (int ignore ATTRIBUTE_UNUSED)
 	  int len;
 
 	  name = demand_copy_C_string (&len);
+	  if (name == NULL)
+	    {
+	      ignore_rest_of_line ();
+	      return;
+	    }
 	}
       else
 	{
@@ -2313,7 +2340,10 @@ tic54x_mlib (int ignore ATTRIBUTE_UNUSED)
   if (*input_line_pointer == '"')
     {
       if ((filename = demand_copy_C_string (&len)) == NULL)
-	return;
+	{
+	  ignore_rest_of_line ();
+	  return;
+	}
     }
   else
     {
@@ -4307,11 +4337,13 @@ subsym_get_arg (char *line, const char *terminators, char **str, int nosub)
 
       input_line_pointer = ptr;
       *str = demand_copy_C_string (&len);
+      if (*str == NULL)
+	ignore_rest_of_line ();
       endp = input_line_pointer;
       input_line_pointer = savedp;
 
       /* Do forced substitutions if requested.  */
-      if (!nosub && **str == ':')
+      if (!nosub && *str && **str == ':')
 	*str = subsym_substitute (*str, 1);
     }
   else
diff --git a/gas/dwarf2dbg.c b/gas/dwarf2dbg.c
index 7b338bb11cd..a1ceab4e428 100644
--- a/gas/dwarf2dbg.c
+++ b/gas/dwarf2dbg.c
@@ -1199,8 +1199,11 @@ dwarf2_directive_filename (void)
 
   filename = demand_copy_C_string (&filename_len);
   if (filename == NULL)
-    /* demand_copy_C_string will have already generated an error message.  */
-    return NULL;
+    {
+      /* demand_copy_C_string will have already generated an error.  */
+      ignore_rest_of_line ();
+      return NULL;
+    }
 
   /* For DWARF-5 support we also accept:
      .file <NUM> ["<dir>"] "<file>" [md5 <NUM>]  */
@@ -1212,7 +1215,10 @@ dwarf2_directive_filename (void)
 	  dirname = filename;
 	  filename = demand_copy_C_string (&filename_len);
 	  if (filename == NULL)
-	    return NULL;
+	    {
+	      ignore_rest_of_line ();
+	      return NULL;
+	    }
 	  SKIP_WHITESPACE ();
 	}
 
diff --git a/gas/ecoff.c b/gas/ecoff.c
index 0bd6a4e366a..9890a1fb8b4 100644
--- a/gas/ecoff.c
+++ b/gas/ecoff.c
@@ -3086,6 +3086,11 @@ ecoff_directive_file (int ignore ATTRIBUTE_UNUSED)
 
   /* FIXME: we don't have to save the name here.  */
   name = demand_copy_C_string (&len);
+  if (name == NULL)
+    {
+      ignore_rest_of_line ();
+      return;
+    }
 
   add_file (name, indx - 1, 0);
 
diff --git a/gas/read.c b/gas/read.c
index 56bd222acf0..1a7537ba2a1 100644
--- a/gas/read.c
+++ b/gas/read.c
@@ -2045,6 +2045,8 @@ s_file (int ignore ATTRIBUTE_UNUSED)
       demand_empty_rest_of_line ();
       s_file_string (s);
     }
+  else
+    ignore_rest_of_line ();
 }
 
 static bool
@@ -2099,90 +2101,94 @@ s_linefile (int ignore ATTRIBUTE_UNUSED)
     }
 
   if (linenum < 0)
-    /* Some of the back ends can't deal with non-positive line numbers.
-       Besides, it's silly.  GCC however will generate a line number of
-       zero when it is pre-processing builtins for assembler-with-cpp files:
+    {
+      /* Some of the back ends can't deal with non-positive line numbers.
+	 Besides, it's silly.  GCC however will generate a line number of
+	 zero when it is pre-processing builtins for assembler-with-cpp files:
 
-	  # 0 "<built-in>"
+	 # 0 "<built-in>"
 
-       We do not want to barf on this, especially since such files are used
-       in the GCC and GDB testsuites.  So we check for negative line numbers
-       rather than non-positive line numbers.  */
-    as_warn (_("line numbers must be positive; line number %d rejected"),
-	     linenum);
-  else
-    {
-      int length = 0;
+	 We do not want to barf on this, especially since such files are used
+	 in the GCC and GDB testsuites.  So we check for negative line numbers
+	 rather than non-positive line numbers.  */
+      as_warn (_("line numbers must be positive; line number %d rejected"),
+	       linenum);
+      ignore_rest_of_line ();
+      return;
+    }
 
-      SKIP_WHITESPACE ();
+  SKIP_WHITESPACE ();
 
-      if (*input_line_pointer == '"')
-	file = demand_copy_string (&length);
-      else if (*input_line_pointer == '.')
+  if (*input_line_pointer == '"')
+    {
+      int this_flag;
+      int length = 0;
+      file = demand_copy_string (&length);
+      if (file == NULL)
 	{
-	  /* buffer_and_nest() may insert this form.  */
-	  ++input_line_pointer;
-	  flags = 1 << 3;
+	  ignore_rest_of_line ();
+	  return;
 	}
 
-      if (file)
-	{
-	  int this_flag;
-
-	  while (get_linefile_number (&this_flag))
-	    switch (this_flag)
-	      {
-		/* From GCC's cpp documentation:
-		   1: start of a new file.
-		   2: returning to a file after having included another file.
-		   3: following text comes from a system header file.
-		   4: following text should be treated as extern "C".
+      while (get_linefile_number (&this_flag))
+	switch (this_flag)
+	  {
+	    /* From GCC's cpp documentation:
+	       1: start of a new file.
+	       2: returning to a file after having included another file.
+	       3: following text comes from a system header file.
+	       4: following text should be treated as extern "C".
 
-		   4 is nonsensical for the assembler; 3, we don't care about,
-		   so we ignore it just in case a system header file is
-		   included while preprocessing assembly.  So 1 and 2 are all
-		   we care about, and they are mutually incompatible.
-		   new_logical_line_flags() demands this.  */
-	      case 1:
-	      case 2:
-		if (flags && flags != (1 << this_flag))
-		  as_warn (_("incompatible flag %i in line directive"),
-			   this_flag);
-		else
-		  flags |= 1 << this_flag;
-		break;
+	       4 is nonsensical for the assembler; 3, we don't care about,
+	       so we ignore it just in case a system header file is
+	       included while preprocessing assembly.  So 1 and 2 are all
+	       we care about, and they are mutually incompatible.
+	       new_logical_line_flags() demands this.  */
+	  case 1:
+	  case 2:
+	    if (flags && flags != (1 << this_flag))
+	      as_warn (_("incompatible flag %i in line directive"),
+		       this_flag);
+	    else
+	      flags |= 1 << this_flag;
+	    break;
 
-	      case 3:
-	      case 4:
-		/* We ignore these.  */
-		break;
+	  case 3:
+	  case 4:
+	    /* We ignore these.  */
+	    break;
 
-	      default:
-		as_warn (_("unsupported flag %i in line directive"),
-			 this_flag);
-		break;
-	      }
+	  default:
+	    as_warn (_("unsupported flag %i in line directive"),
+		     this_flag);
+	    break;
+	  }
 
-	  if (!is_end_of_stmt (*input_line_pointer))
-	    file = NULL;
-        }
+      if (!is_end_of_stmt (*input_line_pointer))
+	file = NULL;
+    }
+  else if (*input_line_pointer == '.')
+    {
+      /* buffer_and_nest() may insert this form.  */
+      ++input_line_pointer;
+      flags = 1 << 3;
+    }
 
-      if (file || flags)
-	{
-	  demand_empty_rest_of_line ();
+  if (file || flags)
+    {
+      demand_empty_rest_of_line ();
 
-	  /* read_a_source_file() will bump the line number only if the line
-	     is terminated by '\n'.  */
-	  if (input_line_pointer[-1] == '\n')
-	    linenum--;
+      /* read_a_source_file() will bump the line number only if the line
+	 is terminated by '\n'.  */
+      if (input_line_pointer[-1] == '\n')
+	linenum--;
 
-	  new_logical_line_flags (file, linenum, flags);
+      new_logical_line_flags (file, linenum, flags);
 #ifdef LISTING
-	  if (listing)
-	    listing_source_line (linenum);
+      if (listing)
+	listing_source_line (linenum);
 #endif
-	  return;
-	}
+      return;
     }
   ignore_rest_of_line ();
 }
@@ -2241,7 +2247,10 @@ s_errwarn (int err)
 
       msg = demand_copy_C_string (&len);
       if (msg == NULL)
-	return;
+	{
+	  ignore_rest_of_line ();
+	  return;
+	}
     }
 
   if (err)
@@ -3135,8 +3144,12 @@ s_print (int ignore ATTRIBUTE_UNUSED)
   int len;
 
   s = demand_copy_C_string (&len);
-  if (s != NULL)
-    printf ("%s\n", s);
+  if (s == NULL)
+    {
+      ignore_rest_of_line ();
+      return;
+    }
+  printf ("%s\n", s);
   demand_empty_rest_of_line ();
 }
 
@@ -6342,8 +6355,7 @@ demand_copy_C_string (int *len_pointer)
 	{
 	  if (s[len - 1] == 0)
 	    {
-	      s = 0;
-	      *len_pointer = 0;
+	      s = NULL;
 	      as_bad (_("this string may not contain \'\\0\'"));
 	      break;
 	    }
@@ -6383,7 +6395,6 @@ demand_copy_string (int *lenP)
     {
       as_bad (_("missing string"));
       retval = NULL;
-      ignore_rest_of_line ();
     }
   *lenP = len;
   return retval;
@@ -6478,7 +6489,10 @@ s_incbin (int x ATTRIBUTE_UNUSED)
   SKIP_WHITESPACE ();
   filename = demand_copy_string (& len);
   if (filename == NULL)
-    return;
+    {
+      ignore_rest_of_line ();
+      return;
+    }
 
   SKIP_WHITESPACE ();
 
@@ -6578,8 +6592,8 @@ s_include (int arg ATTRIBUTE_UNUSED)
       filename = demand_copy_string (&i);
       if (filename == NULL)
 	{
-	  /* demand_copy_string has already printed an error and
-	     called ignore_rest_of_line.  */
+	  /* demand_copy_string has already printed an error.  */
+	  ignore_rest_of_line ();
 	  return;
 	}
     }
diff --git a/gas/stabs.c b/gas/stabs.c
index 0233cc5e018..3e09e10f045 100644
--- a/gas/stabs.c
+++ b/gas/stabs.c
@@ -259,7 +259,10 @@ s_stab_generic (int what,
 
       string = demand_copy_C_string (&length);
       if (string == NULL)
-	goto out2;
+	{
+	  ignore_rest_of_line ();
+	  goto out2;
+	}
       /* FIXME: We should probably find some other temporary storage
 	 for string, rather than leaking memory if someone else
 	 happens to use the notes obstack.  */
@@ -399,8 +402,10 @@ s_xstab (int what)
 
   stab_secname = demand_copy_C_string (&length);
   if (stab_secname == NULL)
-    /* as_bad error has been reported.  */
-    return;
+    {
+      ignore_rest_of_line ();
+      return;
+    }
   SKIP_WHITESPACE ();
   if (*input_line_pointer == ',')
     {

-- 
Alan Modra

From amodra@gmail.com  Sun Jun 28 02:52:32 2026
From: amodra@gmail.com (Alan Modra)
Date: Sun, 28 Jun 2026 12:22:32 +0930
Subject: asan: buffer overflow in elf32_dlx_relocate26
Message-ID: <akCMcB_qrP87iXnu@squeak.grove.modra.org>

	* elf32-dlx.c (elf32_dlx_relocate26): Sanity check reloc offset.
	(elf32_dlx_relocate16): Likewise.
	(_bfd_dlx_elf_hi16_reloc): Likewise, and remove ineffective
	existing check.

diff --git a/bfd/elf32-dlx.c b/bfd/elf32-dlx.c
index 2dfeb4d7390..0f9a49695d7 100644
--- a/bfd/elf32-dlx.c
+++ b/bfd/elf32-dlx.c
@@ -77,6 +77,10 @@ _bfd_dlx_elf_hi16_reloc (bfd *abfd,
       return bfd_reloc_ok;
     }
 
+  if (!bfd_reloc_offset_in_range (reloc_entry->howto, abfd,
+				  input_section, reloc_entry->address))
+    return bfd_reloc_outofrange;
+
   ret = bfd_reloc_ok;
 
   if (bfd_is_und_section (symbol->section)
@@ -89,9 +93,6 @@ _bfd_dlx_elf_hi16_reloc (bfd *abfd,
   relocation += reloc_entry->addend;
   relocation += bfd_get_16 (abfd, (bfd_byte *)data + reloc_entry->address);
 
-  if (reloc_entry->address > bfd_get_section_limit (abfd, input_section))
-    return bfd_reloc_outofrange;
-
   bfd_put_16 (abfd, (short)((relocation >> 16) & 0xFFFF),
 	      (bfd_byte *)data + reloc_entry->address);
 
@@ -143,6 +144,10 @@ elf32_dlx_relocate16 (bfd *abfd,
       return bfd_reloc_undefined;
     }
 
+  if (!bfd_reloc_offset_in_range (reloc_entry->howto, abfd,
+				  input_section, reloc_entry->address))
+    return bfd_reloc_outofrange;
+
   insn  = bfd_get_32 (abfd, (bfd_byte *)data + reloc_entry->address);
   allignment = 1 << (input_section->output_section->alignment_power - 1);
   vallo = insn & 0x0000FFFF;
@@ -206,6 +211,10 @@ elf32_dlx_relocate26 (bfd *abfd,
       return bfd_reloc_undefined;
     }
 
+  if (!bfd_reloc_offset_in_range (reloc_entry->howto, abfd,
+				  input_section, reloc_entry->address))
+    return bfd_reloc_outofrange;
+
   insn  = bfd_get_32 (abfd, (bfd_byte *)data + reloc_entry->address);
   allignment = 1 << (input_section->output_section->alignment_power - 1);
   vallo = insn & 0x03FFFFFF;

-- 
Alan Modra

From predatorvisionhq@gmail.com  Sun Jun 28 06:42:12 2026
From: predatorvisionhq@gmail.com (Predator Vision)
Date: Sat, 27 Jun 2026 23:42:12 -0700
Subject: =?UTF-8?Q?binutils_objdump_DLX_FILE=2Dvtable_hijack_via_crafted_?=
 =?UTF-8?Q?ELF_relocations_=28High=29_=E2=80=94_missing_bfd=5Freloc=5Foffset=5Fin=5Frange?=
Message-ID: <CAO+ZWL2ZkiWWQdDpCzSmPbBHAqpOBRxjdVKCK2oh0e+HmwjcWg@mail.gmail.com>


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From amodra@gmail.com  Sun Jun 28 10:37:59 2026
From: amodra@gmail.com (Alan Modra)
Date: Sun, 28 Jun 2026 20:07:59 +0930
Subject: asan: index out of bounds in print_insn_tic6x
Message-ID: <akD5h_0re39tyi5-@squeak.grove.modra.org>

header.word_compact is a seven element array.  If fp_offset has values
of 29 to 31 then word_compact[7] is read to set num_bits which is then
never used since the function returns before its first use.

	* tic6x-dis.c (print_insn_tic6x): Delay setting num_bits until
	invalid fp_offset values are handled.

diff --git a/opcodes/tic6x-dis.c b/opcodes/tic6x-dis.c
index ca0156e21e3..eb9e1e340ea 100644
--- a/opcodes/tic6x-dis.c
+++ b/opcodes/tic6x-dis.c
@@ -264,21 +264,19 @@ print_insn_tic6x (bfd_vma addr, struct disassemble_info *info)
     {
       if (fp_offset & 0x1)
 	bad_offset = true;
-      if ((fp_offset & 0x3) && (fp_offset >= 28
-				|| !header.word_compact[fp_offset >> 2]))
+      else if ((fp_offset & 0x3) && (fp_offset >= 28
+				     || !header.word_compact[fp_offset >> 2]))
 	bad_offset = true;
-      if (fp_offset == 28)
+      else if (fp_offset == 28)
 	{
 	  info->bytes_per_chunk = 4;
 	  info->fprintf_func (info->stream, "<fetch packet header 0x%.8x>",
 			      header.header);
 	  return 4;
 	}
-      num_bits = (header.word_compact[fp_offset >> 2] ? 16 : 32);
     }
   else
     {
-      num_bits = 32;
       if (fp_offset & 0x3)
 	bad_offset = true;
     }
@@ -290,6 +288,10 @@ print_insn_tic6x (bfd_vma addr, struct disassemble_info *info)
       return 1;
     }
 
+  num_bits = 32;
+  if (fetch_packet_header_based && header.word_compact[fp_offset >> 2])
+    num_bits = 16;
+
   if (num_bits == 16)
     {
       /* The least-significant part of a 32-bit word comes logically

-- 
Alan Modra

From amodra@gmail.com  Sun Jun 28 13:18:01 2026
From: amodra@gmail.com (Alan Modra)
Date: Sun, 28 Jun 2026 22:48:01 +0930
Subject: elf32_arm_copy_special_section_fields wild read
Message-ID: <akEfCcsYy1muyyf4@squeak.grove.modra.org>

This function has a number of loops with a controlling expression of
(i-- > 0) with tests in the loop to break out on finding something.
If that something is not found, the value of i is -1u on loop exit.
Code following the loop expects the "not found" value of i to be 0.
This can lead to an attempted access of oheaders[-1u].

oheaders is elf_elfsections(obfd), the ELF section header table.  We
are not interested here in anything at index zero of the array, so the
proper loop control is --i > 0, or equivalently, --i != 0.

	* elf32-arm.c (elf32_arm_copy_special_section_fields): Correct
	loop controlling expressions.

diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
index e27aff48411..6a9be5dda2f 100644
--- a/bfd/elf32-arm.c
+++ b/bfd/elf32-arm.c
@@ -20062,7 +20062,7 @@ elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
 	    && iheaders[isection->sh_link]->bfd_section->output_section != NULL
 	    )
 	  {
-	    for (i = elf_numsections (obfd); i-- > 0;)
+	    for (i = elf_numsections (obfd); --i != 0;)
 	      if (oheaders[i]->bfd_section
 		  == iheaders[isection->sh_link]->bfd_section->output_section)
 		break;
@@ -20075,16 +20075,16 @@ elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
 	       with input section names.  Unfortunately we don't.  So instead
 	       we use a simple heuristic and look for the nearest executable
 	       section before this one.  */
-	    for (i = elf_numsections (obfd); i-- > 0;)
+	    for (i = elf_numsections (obfd); --i != 0;)
 	      if (oheaders[i] == osection)
 		break;
 	    if (i == 0)
 	      break;
 
-	    while (i-- > 0)
+	    while (--i != 0)
 	      if (oheaders[i]->sh_type == SHT_PROGBITS
-		  && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
-		  == (SHF_ALLOC | SHF_EXECINSTR))
+		  && ((oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
+		      == (SHF_ALLOC | SHF_EXECINSTR)))
 		break;
 	  }
 

-- 
Alan Modra

From avr@gjlay.de  Sun Jun 28 16:21:00 2026
From: avr@gjlay.de (Georg-Johann Lay)
Date: Sun, 28 Jun 2026 18:21:00 +0200
Subject: [patch, avr] Overhaul section AVR modifiers and document gs()
In-Reply-To: <d3e8a57c-da3b-47fb-a0d0-4114fc222803@gjlay.de>
References: <d3e8a57c-da3b-47fb-a0d0-4114fc222803@gjlay.de>
Message-ID: <010e6027-fa3f-4474-997d-15130e366644@gjlay.de>

Am 23.06.26 um 19:14 schrieb Georg-Johann Lay via Binutils:
> This patch overhauls the "AVR modifiers" section of the GAS manual.
> It adds documentation for gs() that is still missing to this day.
> 
> Ok for trunk?
> 
> Johann
> 
> -- 
> 
> AVR: PR13129 - Overhaul section AVR modifiers and document gs().
> 
> This patch adds documentation for gs() to the GAS manual,
> and it overhauls the "AVR modifiers" section.
> 
>  ????PR gas/13129
> gas/
>  ????* doc/c-avr.texi (AVR modifiers): Overhaul and add gs()
>  ????documentation.

This is the updated version:


AVR: PR13129 - Overhaul c-avr.texi and document gs().

This patch adds documentation for gs() to the GAS manual
and overhauls gas/doc/c-avr.texi as a whole.

	PR gas/13129
gas/
	* doc/c-avr.texi: Overhaul and add gs() documentation.

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From gnutoolsweekly@gmail.com  Sun Jun 28 21:24:55 2026
From: gnutoolsweekly@gmail.com (GNU Tools weekly)
Date: Sun, 28 Jun 2026 14:24:55 -0700
Subject: GNU Tools Weekly News Week 44 (June 28, 2026)
In-Reply-To: <CAHt=NyPsTpkp+cZ=MyYAjprMHzo_RkbSPAkZnaB1Bp-2rytbPw@mail.gmail.com>
References: <CAHt=NyPpC47e6400=ZxqwJ5W5B2ABmhUZk+SWsRKSTdxVu4SVA@mail.gmail.com>
 <CAHt=NyPnAeEzUoCVUFVDErpM7C+ieaNti8HxSwi-nJD-anSBuQ@mail.gmail.com>
 <CAHt=NyOxTmdRe6oysAQJxoCA=qAwSKZTOAe4NQn1ZMYF9OhmoQ@mail.gmail.com>
 <CAHt=NyNKa=eQ8ytymevK-r_Zz5p_DhzOzpYC35YLdqzJ4XhgMQ@mail.gmail.com>
 <CAHt=NyNXXPShoxuBUdL5zK_XMU4tkjnuf00C_3Sgor9pOQEiVA@mail.gmail.com>
 <CAHt=NyO8g64b7LBuAOUM2m5E_ruuKV8osytFvseDUz--XaHNjA@mail.gmail.com>
 <CAHt=NyMASMc-5h9zYqH1L3Scbx2oJ6i-RzAS7Eb-WPbQqCmyuQ@mail.gmail.com>
 <CAHt=NyPaAZhqc3WSi1_WMBr=uZmZL=Jc2jwgQibeR1n6xwqyKA@mail.gmail.com>
 <CAHt=NyPntsf9FjtMa2p+vFEDPMkq62J5R4fzK7+qbSDtPUNR_Q@mail.gmail.com>
 <CAHt=NyPsn0jFHzwsxeLrQM6Ha+oktc2o9ZKFu=xJkHy1CjxwSQ@mail.gmail.com>
 <CAHt=NyORRFiB8Jy1sK6rAfJJy+XiV0RTGHZaXJuM4Bd5SkRkEw@mail.gmail.com>
 <CAHt=NyP8xPvZ3+Ugh9rzp2R=qcW+oxNcU3RgUQFdeVM7kHR9bA@mail.gmail.com>
 <CAHt=NyMO-bGXqi_9QcWY6+QoUycSqFLipON6nw-KRTOJvS45pw@mail.gmail.com>
 <CAHt=NyPM=1hX72U+3cShS55bTzaGHg_sXcO1yONOVqanC_NsvQ@mail.gmail.com>
 <CAHt=NyPC4okeNg3HX3DWM4eV5Q8SJ7tV2Vzj===QftzBhTOupQ@mail.gmail.com>
 <CAHt=NyOHu7=XXWBWLnvvFsg63cOVuVYPUz5c-fQw05wT2=rUBw@mail.gmail.com>
 <CAHt=NyNPrZdOeUgEJG_3_ma0OSJUDjOA=co_FbvQr=FSurqdMA@mail.gmail.com>
 <CAHt=NyOACt0uHs3a0XEGf9_saq_MkW_XQw=uegOtPUPm6t8qYg@mail.gmail.com>
 <CAHt=NyNUyUiehSd4ZvQuFGrRm2X4vUBmUssA-+FpfPvey2vnKA@mail.gmail.com>
 <CAHt=NyPh7WCXgNAoi+Cb+Ae+vEqc_tVZ3KJDUEiD7osid-OZvA@mail.gmail.com>
 <CAHt=NyP07x=0qgHDP9Fx7Uwix_ZW3=94yGUTuJShNE8NAAE=kA@mail.gmail.com>
 <CAHt=NyNhJhGsdDq1u-ByQs=C_dZOD8bssxc+pEydHvP=A2O9_w@mail.gmail.com>
 <CAHt=NyOUyeBwKufE75Jn3MmcndHJnPrajhP4Pse+d0DA0eaa6w@mail.gmail.com>
 <CAHt=NyMt0Y0yL1Xrzt-i1TVWjjX_kEWhsvYE0yKDYSDAwz8XSQ@mail.gmail.com>
 <CAHt=NyNGFEZq=+MzzR3scJRpMPLey0NgoHuTnQBz50yP_vfjXQ@mail.gmail.com>
 <CAHt=NyN1HLULR_wFt5NU2N6jw_L8XTrm64PufwhCfVkdFgSaAQ@mail.gmail.com>
 <CAHt=NyO6evRk0DbxBHD-QnOpf9RsUri5cMBNDOsVtm_kkTc76w@mail.gmail.com>
 <CAHt=NyMe32SEHNGf0A=cfeimQXYzfB1Mxo9crhT0WX9dPnJTAA@mail.gmail.com>
 <CAHt=NyN5g2Um4gDB7rjfiTKPuSs5R7w5Qsym9errGO7U2tz6tg@mail.gmail.com>
 <CAHt=NyNjxhyARZEbMHihV5U1AsUwaJwP8QZx6MiL8AV0wXe=Yg@mail.gmail.com>
 <CAHt=NyPk0yxTt+TA3GNDV75+1Pb-Q11Ps-8FXF0aUTCEHax08g@mail.gmail.com>
 <CAHt=NyP1bySRnwNQABx4K6ktyhUXR=BjXvWcP9342RQjtFNgvw@mail.gmail.com>
 <CAHt=NyPgGdtW+CC8COxpCTQgiGwf827FgD_1jV=XRfcCZ__0Hw@mail.gmail.com>
 <CAHt=NyPX=1drCFkU_b7kCP_JmWYHtZAejKh4U1ia6j+MgmYEEQ@mail.gmail.com>
 <CAHt=NyNvCGuc=HTF72YSj3wkReQpOvNEfkGzn2NFUZKK9e8-CQ@mail.gmail.com>
 <CAHt=NyNWPV6FMbzGQe+b+ifm=T3OZ5R7-3MwGu4odFkuO-OAzQ@mail.gmail.com>
 <CAHt=NyPLDnHzbsV8xc7TC9Us9Djg6sDMo+QqKpbg0Kgnp6MzRw@mail.gmail.com>
 <CAHt=NyN_knMJeN3pGqHbpNbjknFt-Vw+0u3AeR2jChdHX7wG1w@mail.gmail.com>
 <CAHt=NyMQqSikhJAd2inR4X8=D-1pWZwxGJtxwb3GwhfwuuWLvg@mail.gmail.com>
 <CAHt=NyNonbJn-qYgZy4UR54x_0g39iMtzGreWj+mp5sM2wJyOg@mail.gmail.com>
 <CAHt=NyPsTpkp+cZ=MyYAjprMHzo_RkbSPAkZnaB1Bp-2rytbPw@mail.gmail.com>
Message-ID: <CAHt=NyPxHN-rwaTfOxP32XX4NDDb7c0V5QBi13MPzYjeX6D0JA@mail.gmail.com>

GNU Tools Weekly News Week 44 (June 28, 2026)

Release updates for GNU toolchain:
 * GCC 14.4.0 was released
  * https://inbox.sourceware.org/gcc/aj5L4BbnW8XMF7GQ@tucnak/

GNU toolchain conference reminders:
 * FOSSY 2026 toolchain track North America, Aug 6-9 (Vancouver, Canada)
  * https://gcc.gnu.org/wiki/fossy2026
 * GNU Tools Cauldron 2026, Fri-Sun, October 2-4 (Prague, Czechia)
  * https://gcc.gnu.org/wiki/cauldron2026
  * https://conf.gnu-tools-cauldron.org/prg26/cfp
 * Toolchains Track at LPC 2026, October 7th (Prague, Czechia)
  * https://lpc.events/event/20/abstracts/

General/big GNU toolchain news (including sourceware news):
 *


GCC easy issue to tackle of the week (2 this week):
 * ICE with return type of typedef of void and `#pragma omp declare simd`
  * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111856
  * Reach out to Andrea Pinski <andrew.pinski@oss.qualcomm.com> for
mentoring on this issue.
 * For RISC-V, prefer li+slli rather than lui+add for some constants
  * https://gcc.gnu.org/bugzilla/show_bug.cgi?id=126022
  * Reach out to Jeff Law <jeffrey.law@oss.qualcomm.com> for mentoring
on this issue.
 * Previous ones are listed on https://gcc.gnu.org/wiki/EasyIssuesOfTheWeek

GCC commits:
 * https://gcc.gnu.org/r17-1733 ...  r17-1943  211 commits
 * RTL: add dependent filter handling
  * https://gcc.gnu.org/r17-1779-g9d82914d073e2e ...
https://gcc.gnu.org/r17-1783-gc23f20c10d89af
  * https://inbox.sourceware.org/gcc-patches/20260526142247.172296-1-rdapp.gcc@gmail.com/
 * AArch64/SVE: Optimize vec_init for partial SVE vector modes
  * https://gcc.gnu.org/r17-1799-gb3acc5dd98f44d
 * rs6000: Add Future Vector Integer Arithmetic Instructions
  * https://gcc.gnu.org/r17-1800-ga3b8e252101ada
 * OMP improvements
  * De-duplicate libgomp entry points for OMPT
  * https://inbox.sourceware.org/gcc-patches/20260622165754.226314-1-parras@baylibre.com/
  * https://gcc.gnu.org/r17-1803-g37c96bf08325bf ...
https://gcc.gnu.org/r17-1806-gd50e9f17fffa9b
 * rs6000: Builtins for ECC cryptography instructions
  * https://gcc.gnu.org/r17-1856-g2b3c882b5b8e96
 * RISC-V: GLIBC's setjmp preserves callee-saved registers
  * https://gcc.gnu.org/r17-1857-g21dad398994ff5
 * GCC rust sync
  * https://gcc.gnu.org/r17-1863-g5333e241a36912 ...
https://gcc.gnu.org/r17-1904-g30a64527c56af9
 * match: Use ranges for int-float comparisons
  * https://gcc.gnu.org/r17-1931-g8351875a5e2c52
 * Use tree_expr_nonnegative_p instead of TYPE_UNSIGNED for MAX (A, B)
(==,!=) 0 -> (A|B) (==,!=) 0
  * https://gcc.gnu.org/r17-1938-g61b702d88c8e55
 * Remove BOOL_BITFIELD define from system.h and update its uses
 * https://gcc.gnu.org/r17-1943-g08944b70002610

GCC discussion:
 * [RFC TREE-WIDE] gcc: stop using 'int' to represent sets of qualifiers
  * https://inbox.sourceware.org/gcc/20260626191622.1785567-1-aarsenovic@baylibre.com/
 * RFC: Allow "(mem:<vectype> (reg:<vectype>))"
  * https://inbox.sourceware.org/gcc/82bf28f3-5543-4925-98d9-5ddf7dc23855@baylibre.com/
 * [RFC] LRA: Carrying hard registers around
  * https://inbox.sourceware.org/gcc/ajuBckDkxUIVXvyu@li-819a89cc-2401-11b2-a85c-cca1ce6aa768.ibm.com/
 * RFC: Bump minimum GNU Make version to 3.81
  * https://inbox.sourceware.org/gcc/CAH6eHdRuOhrEEYp6jmGZgq6QXUsMe4kr66LY62uk59MpYnTauw@mail.gmail.com/
 * [RFC] Add simple forwprop across edges (PHIs)
  * https://inbox.sourceware.org/gcc-patches/20260625233902.2605630-1-andrew.pinski@oss.qualcomm.com/


GCC bugzilla stats
 *  101 new issues filed
 *  76 issues closed

binutils/gdb commits:
 * binutils: RISC-V: Add some extensions
  * Zalasr
  * SpacemiT vendor extension xsmtvdot
  * SpacemiT vendor extension xsmtvdotii
  * Svrsw60t59b
  * Zvabd
  * https://sourceware.org/cgit/binutils-gdb/log/?qt=range&q=d3b84dac949ac10f8736c85253b4a1073d244ac1...d26861e53c74d54be86149dd5b78d339487bebb4
  * Smpmpmt
   * https://sourceware.org/cgit/binutils-gdb/commit/?id=e56bd09181016800870de47c1f3a1091f71d9120
 * gdb: Handle nested Ada functions with gnat-llvm
  * https://sourceware.org/cgit/binutils-gdb/commit/?id=26d17a9b24dfd4a3894bc19ac752466ea10e80b2
 *

gdb discussion:
 * Adding architecture-specific commands in GDB
  * https://inbox.sourceware.org/gdb/077b9f00-ec84-440f-a84a-d804815aa77e@arm.com/

binutils discussion:
 *

glibc commits:
 * manual: Document indirect functions (IFUNC)
  * https://sourceware.org/cgit/glibc/commit/?id=657fe73fb1ce09c109fffafb16d565eedbbe05ed

glibc discussion:
 *

From mark@klomp.org  Sun Jun 28 21:59:02 2026
From: mark@klomp.org (Mark Wielaard)
Date: Sun, 28 Jun 2026 23:59:02 +0200
Subject: Sourceware budget and funding 2026/2027, Fri 12, 15:00 UTC
In-Reply-To: <20260614225910.GA14303@gnu.wildebeest.org>
References: <20260611103835.GH14081@gnu.wildebeest.org>
 <20260614225910.GA14303@gnu.wildebeest.org>
Message-ID: <20260628215902.GB12192@gnu.wildebeest.org>

Hi all,

On Mon, Jun 15, 2026 at 12:59:10AM +0200, Mark Wielaard wrote:
> On Thu, Jun 11, 2026 at 12:38:35PM +0200, Mark Wielaard wrote:
> > Based on last months budget discussions and last years financial
> > overview the Sourceware Project Leadership Committee wrote up an
> > ambitious budget and funding proposal for 2026/2027, see below. Lets
> > discuss if this matches community expectations and what the most
> > effective way is to drive this fundraising campaign.
> [...] 
> What is next?
> 
> - Create a new sponsors page that lists incentives, levels and "bonus"
>   targets.
> - Link it all together with the financials and donate pages.
> - Find Sourceware Ambassadors to drive the fundraising campaign.

The Sourceware PLC reviewed all feedback and we now have:

- https://sourceware.org/donate.html
  The individual donation page. Please donate if you haven't yet.
  Every contribution makes a difference.

- https://sourceware.org/sponsor.html
  The corporate sponsorship page. With three different tiers.
  If your company would like to become a financial sponsor, or become
  a resource partner please contact us at sponsor@sourceware.org

- https://sourceware.org/financials.html
  Sourceware financials, budget and funding targets for 2026/2027.

Next week, start of next month, we'll start a formal fundraising
campaign.

Cheers,

Mark

From hjl.tools@gmail.com  Sun Jun 28 22:52:43 2026
From: hjl.tools@gmail.com (H.J. Lu)
Date: Mon, 29 Jun 2026 06:52:43 +0800
Subject: [COMMITTED,
 PATCH] ld-elf/linux-x86.exp: Remove $options in readelf log
Message-ID: <CAMe9rOowv9OR9c7wJTerxsB2VUwFLWUb0P9e_vMqSUsgkj8K0g@mail.gmail.com>

Remove $options in readelf log since it isn't passed to readelf.

* testsuite/ld-elf/linux-x86.exp (elfedit_test): Remove $options
in readelf log.

-- 
H.J.
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From amodra@gmail.com  Mon Jun 29 01:24:04 2026
From: amodra@gmail.com (Alan Modra)
Date: Mon, 29 Jun 2026 10:54:04 +0930
Subject: [PATCH v4] elf: Set image base address to the maximum page size
In-Reply-To: <CAMe9rOoW4dnsHBBLqAbHS_6fTaDwmSbjw=Ah2M0SaZVWei7i4Q@mail.gmail.com>
References: <05c74589-fa62-4673-bb6e-9154d37024ee@redhat.com>
 <CAMe9rOpmyweh-+Dp4F_K2H15C4x+aTSO__fLRFxCivMnA+oDKg@mail.gmail.com>
 <CAMe9rOoW4dnsHBBLqAbHS_6fTaDwmSbjw=Ah2M0SaZVWei7i4Q@mail.gmail.com>
Message-ID: <akHJNFLXxoqB-WOU@squeak.grove.modra.org>

On Fri, Jun 26, 2026 at 12:06:50PM +0800, H.J. Lu wrote:
> Here is the v4 patch.

On x86_64-linux I see FAIL: ld-elf/textaddr8 due to not matching the
expected header.

Program Headers:
  Type           Offset   VirtAddr           PhysAddr           FileSiz  MemSiz   Flg Align
  LOAD           0x000000 0x0000000000800000 0x0000000000800000 0x0000e8 0x0000e8 R   0x800000
  LOAD           0x800000 0x0000000001000000 0x0000000001000000 0x000004 0x000004 R E 0x800000
  LOAD           0x1000000 0x0000000001800000 0x0000000001800000 0x000004 0x000004 RW  0x800000

aarch64-linux-gnu  +FAIL: ld-elf/textaddr8
alpha-linux-gnu  +FAIL: ld-elf/textaddr8
am33_2.0-linux-gnu  +FAIL: ld-elf/textaddr8
armeb-linux-gnueabi  +FAIL: ld-elf/textaddr8
arm-linux-gnueabi  +FAIL: ld-elf/textaddr8
cris-linux-gnu  +FAIL: ld-elf/textaddr8
crisv32-linux-gnu  +FAIL: ld-elf/textaddr8
csky-linux-gnu  +FAIL: ld-elf/textaddr8
frv-linux-gnu  +FAIL: ld-elf/textaddr8
h8300-linux-gnu  +FAIL: ld-elf/textaddr8
hppa64-linux-gnu  +FAIL: ld-elf/textaddr8
hppa-linux-gnu  +FAIL: ld-elf/textaddr8
i586-linux-gnu  +FAIL: ld-elf/textaddr8
ia64-linux-gnu  +FAIL: ld-elf/textaddr8
kvx-linux-gnu  +FAIL: ld-elf/textaddr8
lm32-linux-gnu  +FAIL: ld-elf/textaddr8
loongarch64-linux-gnu  +FAIL: ld-elf/textaddr8
m32r-linux-gnu  +FAIL: ld-elf/textaddr8
m68k-linux-gnu  +FAIL: ld-elf/textaddr8
metag-linux-gnu  +FAIL: ld-elf/textaddr8
microblaze-linux-gnu  +FAIL: ld-elf/textaddr8
microblaze-linux-gnu  +FAIL: ld-elf/textaddr9
mips64-linux-gnuabi64  +FAIL: ld-elf/textaddr8
mipsel-linux-gnu  +FAIL: ld-elf/textaddr8
mipsisa32el-linux-gnu  +FAIL: ld-elf/textaddr8
mips-linux-gnu  +FAIL: ld-elf/textaddr8
nds32le-linux-gnu  +FAIL: ld-elf/textaddr8
nds32le-linux-gnu  +FAIL: ld-elf/textaddr9
or1k-linux-gnu  +FAIL: ld-elf/textaddr8
powerpc64le-linux-gnu  +FAIL: ld-elf/textaddr8
powerpc64-linux-gnu  +FAIL: ld-elf/textaddr8
powerpc-linux-gnu  +FAIL: ld-elf/textaddr8
riscv64-linux-gnu  +FAIL: ld-elf/textaddr8
s390-linux-gnu  +FAIL: ld-elf/textaddr8
s390x-linux-gnu  +FAIL: ld-elf/textaddr8
sh4-linux-gnu  +FAIL: ld-elf/textaddr8
sparc64-linux-gnu  +FAIL: ld-elf/textaddr8
sparc-linux-gnu  +FAIL: ld-elf/textaddr8
tilegx-linux-gnu  +FAIL: ld-elf/textaddr8
tilepro-linux-gnu  +FAIL: ld-elf/textaddr8
x86_64-pc-linux-gnu  +FAIL: ld-elf/textaddr8
x86_64-pc-linux-gnux32  +FAIL: ld-elf/textaddr8


-- 
Alan Modra

From hjl.tools@gmail.com  Mon Jun 29 03:40:53 2026
From: hjl.tools@gmail.com (H.J. Lu)
Date: Mon, 29 Jun 2026 11:40:53 +0800
Subject: [PATCH v5] elf: Set image base address to the maximum page size
In-Reply-To: <akHJNFLXxoqB-WOU@squeak.grove.modra.org>
References: <05c74589-fa62-4673-bb6e-9154d37024ee@redhat.com>
 <CAMe9rOpmyweh-+Dp4F_K2H15C4x+aTSO__fLRFxCivMnA+oDKg@mail.gmail.com>
 <CAMe9rOoW4dnsHBBLqAbHS_6fTaDwmSbjw=Ah2M0SaZVWei7i4Q@mail.gmail.com>
 <akHJNFLXxoqB-WOU@squeak.grove.modra.org>
Message-ID: <CAMe9rOqiiAqYstWWSE0JOowMLi6M973OOAiA7s1opkvAZ6Nv+w@mail.gmail.com>

On Mon, Jun 29, 2026 at 9:24?AM Alan Modra <amodra@gmail.com> wrote:
>
> On Fri, Jun 26, 2026 at 12:06:50PM +0800, H.J. Lu wrote:
> > Here is the v4 patch.
>
> On x86_64-linux I see FAIL: ld-elf/textaddr8 due to not matching the
> expected header.
>
> Program Headers:
>   Type           Offset   VirtAddr           PhysAddr           FileSiz  MemSiz   Flg Align
>   LOAD           0x000000 0x0000000000800000 0x0000000000800000 0x0000e8 0x0000e8 R   0x800000
>   LOAD           0x800000 0x0000000001000000 0x0000000001000000 0x000004 0x000004 R E 0x800000
>   LOAD           0x1000000 0x0000000001800000 0x0000000001800000 0x000004 0x000004 RW  0x800000
>
> aarch64-linux-gnu  +FAIL: ld-elf/textaddr8
> alpha-linux-gnu  +FAIL: ld-elf/textaddr8
> am33_2.0-linux-gnu  +FAIL: ld-elf/textaddr8
> armeb-linux-gnueabi  +FAIL: ld-elf/textaddr8
> arm-linux-gnueabi  +FAIL: ld-elf/textaddr8
> cris-linux-gnu  +FAIL: ld-elf/textaddr8
> crisv32-linux-gnu  +FAIL: ld-elf/textaddr8
> csky-linux-gnu  +FAIL: ld-elf/textaddr8
> frv-linux-gnu  +FAIL: ld-elf/textaddr8
> h8300-linux-gnu  +FAIL: ld-elf/textaddr8
> hppa64-linux-gnu  +FAIL: ld-elf/textaddr8
> hppa-linux-gnu  +FAIL: ld-elf/textaddr8
> i586-linux-gnu  +FAIL: ld-elf/textaddr8
> ia64-linux-gnu  +FAIL: ld-elf/textaddr8
> kvx-linux-gnu  +FAIL: ld-elf/textaddr8
> lm32-linux-gnu  +FAIL: ld-elf/textaddr8
> loongarch64-linux-gnu  +FAIL: ld-elf/textaddr8
> m32r-linux-gnu  +FAIL: ld-elf/textaddr8
> m68k-linux-gnu  +FAIL: ld-elf/textaddr8
> metag-linux-gnu  +FAIL: ld-elf/textaddr8
> microblaze-linux-gnu  +FAIL: ld-elf/textaddr8
> microblaze-linux-gnu  +FAIL: ld-elf/textaddr9
> mips64-linux-gnuabi64  +FAIL: ld-elf/textaddr8
> mipsel-linux-gnu  +FAIL: ld-elf/textaddr8
> mipsisa32el-linux-gnu  +FAIL: ld-elf/textaddr8
> mips-linux-gnu  +FAIL: ld-elf/textaddr8
> nds32le-linux-gnu  +FAIL: ld-elf/textaddr8
> nds32le-linux-gnu  +FAIL: ld-elf/textaddr9
> or1k-linux-gnu  +FAIL: ld-elf/textaddr8
> powerpc64le-linux-gnu  +FAIL: ld-elf/textaddr8
> powerpc64-linux-gnu  +FAIL: ld-elf/textaddr8
> powerpc-linux-gnu  +FAIL: ld-elf/textaddr8
> riscv64-linux-gnu  +FAIL: ld-elf/textaddr8
> s390-linux-gnu  +FAIL: ld-elf/textaddr8
> s390x-linux-gnu  +FAIL: ld-elf/textaddr8
> sh4-linux-gnu  +FAIL: ld-elf/textaddr8
> sparc64-linux-gnu  +FAIL: ld-elf/textaddr8
> sparc-linux-gnu  +FAIL: ld-elf/textaddr8
> tilegx-linux-gnu  +FAIL: ld-elf/textaddr8
> tilepro-linux-gnu  +FAIL: ld-elf/textaddr8
> x86_64-pc-linux-gnu  +FAIL: ld-elf/textaddr8
> x86_64-pc-linux-gnux32  +FAIL: ld-elf/textaddr8
>
>

Changes in v5:

1.  Adjust ld-elf/textaddr8 and ld-elf/textaddr9.
2.  Add testsuite/ld-elf/textaddr10.d.

-- 
H.J.
----
When generating Position Dependent Executable for ELF with the maximum
page size set on command-line, set the default image base address to the
maximum page size to avoid segfault if it is lower than the maximum page
size and issue an warning if the image base address set on command-line
is lower than the maximum page size.

PR ld/34184
* ldexp.c (fold_binary): Set the default image base address to
the maximum page size for ELF PDE output if it is lower than
the maximum page size set on command-line and issue an warning
if the image base address set on command-line is lower than the
maximum page size.
* testsuite/ld-elf/elf.exp: Add ld/34184 tests for PDE, PIE
static PDE and static PIE.
* testsuite/ld-elf/pr34184.c: New file.
* testsuite/ld-elf/textaddr3.d: Change -Ttext-segment address
to 0x200100 so that it > the maximum page size.
* testsuite/ld-elf/textaddr5.d: Likewise.
* testsuite/ld-elf/textaddr8.d: New test.
* testsuite/ld-elf/textaddr9.d: Likewise.
* testsuite/ld-elf/textaddr10.d: Likewise.
-------------- next part --------------
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From amodra@gmail.com  Mon Jun 29 03:41:32 2026
From: amodra@gmail.com (Alan Modra)
Date: Mon, 29 Jun 2026 13:11:32 +0930
Subject: [PATCH v3] RISC-V: Fix build with GCC-8
In-Reply-To: <20260627163253.1673970-1-zhuangqiubin@linux.spacemit.com>
References: <f2abf263-4730-4ccd-af87-e3de2289b35c@suse.com>
 <20260623133508.2896582-1-zhuangqiubin@linux.spacemit.com>
 <alpine.DEB.2.21.2606252232520.58268@angie.orcam.me.uk>
 <7f84f26f-9f88-4690-8f61-e7e893831f65@suse.com>
 <alpine.DEB.2.21.2606261151490.58268@angie.orcam.me.uk>
 <dc6104a6-70d6-443a-9605-993bfb1c7851@suse.com>
 <20260627163253.1673970-1-zhuangqiubin@linux.spacemit.com>
Message-ID: <akHpbLZYhkVaEpSs@squeak.grove.modra.org>

On Sun, Jun 28, 2026 at 12:32:53AM +0800, Mark Zhuang wrote:
> Hi Jan, Maciej,
> 
> I redid some testing, and this build error reproduces with both gcc-9.4.0
> and gcc-10.5.0; in both cases it is fixed by this patch.
> 
> Please feel free to adjust the commit message as needed when committing,
> as well as the break/continue placement discussed earlier.
> 
> Thanks a lot,
> Mark

Committed, thanks for your patience.

-- 
Alan Modra

From haochen.jiang@intel.com  Mon Jun 29 03:41:51 2026
From: haochen.jiang@intel.com (Jiang, Haochen)
Date: Mon, 29 Jun 2026 03:41:51 +0000
Subject: [PATCH v1 1/2] Support AVX10_V2_AUX instructions
In-Reply-To: <20260627095543.1627012-2-Ganesh.Gopalasubramanian@amd.com>
References: <20260627095543.1627012-1-Ganesh.Gopalasubramanian@amd.com>
 <20260627095543.1627012-2-Ganesh.Gopalasubramanian@amd.com>
Message-ID: <IA4PR11MB90099AD311BE8AAFACDF3873ECE82@IA4PR11MB9009.namprd11.prod.outlook.com>

> From: Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
> Sent: Saturday, June 27, 2026 5:56 PM

Hi Ganesh,

First of all, you should always omit those generated files like what you
have done in ACE patch.

> 
> - AVX10_V1_AUX instructions are already present as part of AVX10.2
> instructions. They are just available under new cpuid bit.

What is your plan on supporting that bit?

> diff --git a/gas/testsuite/gas/i386/x86-64-avx10_v2_aux.d
> b/gas/testsuite/gas/i386/x86-64-avx10_v2_aux.d
> +[ 	]*[a-f0-9]+:[ 	]*62 f5 7d 08 38 01[ 	]*vcvtrops2hf8
> \(%rcx\),%xmm0

Your test did not cover the full set of the insts. You could only emit
128 bit memory here, no 256/512 bit according to your upcoming
Implementation.

> diff --git a/gas/testsuite/gas/i386/x86-64-avx10_v2_aux.s
> b/gas/testsuite/gas/i386/x86-64-avx10_v2_aux.s
> new file mode 100644
> index 00000000000..24c2901f599
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-avx10_v2_aux.s
> @@ -0,0 +1,149 @@
> +	.text
> +	.arch .avx10_v2_aux
> +_start:
> +	# VCVTPS2BF8 - F3.MAP5.W0 opcode 39
> +	vcvtps2bf8	%xmm1, %xmm0
> +	vcvtps2bf8	%ymm1, %xmm0
> +	vcvtps2bf8	%zmm1, %xmm0
> +	vcvtps2bf8	(%rcx), %xmm0
> +	vcvtps2bf8	0x10(%rcx), %xmm0
> +	vcvtps2bf8	%xmm1, %xmm0{%k1}
> +	vcvtps2bf8	%xmm1, %xmm0{%k1}{z}
> +
> +	# VCVTPS2BF8S - F3.MAP5.W0 opcode 3B
> +	vcvtps2bf8s	%xmm1, %xmm0
> +	vcvtps2bf8s	%ymm1, %xmm0
> +	vcvtps2bf8s	%zmm1, %xmm0
> +	vcvtps2bf8s	(%rcx), %xmm0
> +	vcvtps2bf8s	%xmm1, %xmm0{%k1}
> +
> +	# VCVTPS2HF8 - F3.MAP5.W0 opcode 38
> +	vcvtps2hf8	%xmm1, %xmm0
> +	vcvtps2hf8	%ymm1, %xmm0
> +	vcvtps2hf8	%zmm1, %xmm0
> +	vcvtps2hf8	(%rcx), %xmm0
> +	vcvtps2hf8	%xmm1, %xmm0{%k1}
> +
> +	# VCVTPS2HF8S - F3.MAP5.W0 opcode 3A
> +	vcvtps2hf8s	%xmm1, %xmm0
> +	vcvtps2hf8s	%ymm1, %xmm0
> +	vcvtps2hf8s	%zmm1, %xmm0
> +	vcvtps2hf8s	(%rcx), %xmm0
> +	vcvtps2hf8s	%xmm1, %xmm0{%k1}

Please use .irp to shrink the testcase lines.

> diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
> index be580d48a18..11cc4ff19dc 100644
> --- a/opcodes/i386-gen.c
> +++ b/opcodes/i386-gen.c
> @@ -249,6 +249,8 @@ static const dependency isa_dependencies[] =
> 
> "|AVX512_VNNI|AVX512_BF16|AVX512_FP16|AVX512_VPOPCNTDQ|AVX
> 512_BITALG" },
>    { "AVX10_2",
>      "AVX10_1" },
> +  { "AVX10_V2_AUX",
> +    "AVX10_2" },

Are you sure this should be AVX10_2 but not AVX10_1? According to the
documentation for CPUID ACEv1 emulation:

"
To detect full ACE v1 support, software should verify:
1. (AVX10.1 and AVX10_V1_AUX) or AVX10.2
2. AVX10_V2_AUX
"

There will be possibilities for some x86 vendors have not full AVX10.2
support but AVX10_V2_AUX support, or the documentation won't do
so.

Now it is the assembler and disassembler part. Before the comments
coming in, I would like to mention for those convert insts:

When the encoding is designed as this, we are trying to keep the
encoding as consistent as we can. We have the following rules for
convert when assigning encoding:

For down convert:
- The different dst size will result in different opcode.
- W bit will indicate the src size pairs, i.e., PS=PD, PH-BF16, HF8-BF8, etc.
The former is always at W0, the latter is always at W1.
- The different type of convert is indicated at prefixes, where cvtbias at
NP, cvt at F3, cvt2 at F2, leaving 66 for special types in case we need it
(Here is the cvtro).

For up covert, since we have fewer variants for convert (we definitely
won't have cvt2), we may choose to fold them a little bit, but we will still
keep the W rule in down convert.

Then it is the comment part. If you don't want to do some of the combine
or table pass simplification, I will have an upcoming patch to do so. We
need at least to keep the implementation is correct, i.e, all the tables
needed are passed and the assembler/disassembler is doing what they
should do.

> diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h
> index 1aeac210c5d..ffecef5e796 100644
> --- a/opcodes/i386-dis-evex-prefix.h
> +++ b/opcodes/i386-dis-evex-prefix.h
> +  /* PREFIX_EVEX_MAP5_36 */
> +  {
> +    { VEX_W_TABLE (EVEX_W_MAP5_36_P_0) },
> +  },

You could avoid W table pass by adding a macro like
%XF, to output hf for W1 and bf for W0. And the same
for similar both hf/bf existing cases. For those only
one of them exists, you still need to pass W table to
invalid the other one, like...

> +  /* PREFIX_EVEX_MAP5_37 */
> +  {
> +    { "vcvtbf42hf8",	{ XM, EXxmmq }, 0 },

... here. You need to pass W table.

> +    { Bad_Opcode },
> +    { VEX_W_TABLE (EVEX_W_MAP5_37_P_2) },
> +  },
> +  /* PREFIX_EVEX_MAP5_38 */
> +  {
> +    { "vcvtbiasps2hf8",	{ XMM, Vex, EXx }, 0 },
> +    { "vcvtps2hf8",	{ XMM, EXx }, 0 },
> +    { "vcvtrops2hf8",	{ XMM, EXx }, 0 },

It is what I mentioned in testcase part, you will need
a suffix for ATT syntax if memory is involved and you
could not determine the memory size according to
other operands. Unlike Intel syntax has the memory
size directly at memory operand, ATT syntax won't.
The only way to distinguish them is adding x/y/z
when needed at the end of the mnemonics.

Take this scenario as example, here we need suffix
for vcvtps2hf8 and vcvtrops2hf8, since the other
operand will always be xmm, it does not contain
any info to indicate the other operand. Adding %XZ
is needed since it needs all x/y/z.
vcvtbiasps2hf8 does not need that suffix because the
second operand contains the info.

Please also check other similar scenarios. If I don't
miss something, should be vcvt[ro,]ps2[h,b]f8[,s] if
they exists.

> +  /* PREFIX_EVEX_MAP5_3C */
> +  {
> +    { Bad_Opcode },
> +    { "vcvthf82hf6s",	{ XM, EXx }, 0 },
> +  },

There are several mod table pass missing throughout
the implementation. You need restrict MOD.R/M as
11 here.

Also, for non-broadcast operands, please use
EXEvexXNoBcst instead of EXx.

Similar for vunpackb and vcvtbf82bf6s.

> +  /* PREFIX_EVEX_MAP5_3D */
> +  {
> +    { Bad_Opcode },
> +    { VEX_W_TABLE (EVEX_W_MAP5_3D_P_1) },
> +  },
> +  /* PREFIX_EVEX_MAP5_3E */
> +  {
> +    { Bad_Opcode },
> +    { VEX_W_TABLE (EVEX_W_MAP5_3E_P_1) },
> +  },
>    /* PREFIX_EVEX_MAP5_74 */
>    {
>      { "vcvtbiasp%XH2bf8s",	{ XMxmmq, Vex, EXxh }, 0 },
> diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h
> index 310f121f499..6e94bc45fe1 100644
> --- a/opcodes/i386-dis-evex-w.h
> +++ b/opcodes/i386-dis-evex-w.h
> +  /* EVEX_W_MAP5_3E_P_1 */
> +  {
> +    { Bad_Opcode },
> +    { "vcvtbf82bf6s",	{ XM, EXx }, 0 },
> +  },

Please pass W table before prefix table to reduce
potential tree size.

> diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
> index b2f02e494f9..7d555aa9e11 100644
> --- a/opcodes/i386-dis-evex.h
> +++ b/opcodes/i386-dis-evex.h
> @@ -652,7 +652,7 @@ static const struct dis386 evex_table[][256] = {
>      { EVEX_LEN_TABLE (EVEX_LEN_0F3A3A) },
>      { EVEX_LEN_TABLE (EVEX_LEN_0F3A3B) },
>      { Bad_Opcode },
> -    { Bad_Opcode },
> +    { "vunpackb",	{ XM, EXx, Ib }, 0 },

Missing W and prefix table pass here.

> diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
> index 7042ca4512e..3d3e37b09aa 100644
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -3620,6 +3620,95 @@ vucomxs<sdh>, 0x<sdh:spfx>2e, AVX10_2,
> Modrm|EVexLIG|<sdh:spc1>|<sdh:vexw>|Disp8
> 
>  // AVX10.2 instructions end.
> 
> +// AVX10_V2_AUX instructions.
> +
> +// VCVTPS2BF8, VCVTPS2BF8S, VCVTPS2HF8, VCVTPS2HF8S - narrowing 2-
> op (F3.MAP5)
> +// VCVTROPS2HF8, VCVTROPS2HF8S - narrowing 2-op (66.MAP5)
> +
> +<cvtps8:opc:pfx, +
> +    bf8:39:f3, +
> +    bf8s:3b:f3, +
> +    hf8:38:f3, +
> +    hf8s:3a:f3>

Why do you need to put pfx in iterator? They are all f3.

And we could simply separate them as <fp8> and <sat> here, not <cvtps8>,
<cvtrops8>, <cvtbiasps8>, where <fp8> has the base opcode 38 and 39,
<sat> add 2 for them when there is saturation.

And just as mentioned, you will also need to handle ATT Syntax here, you will
need a new <Exyz>.

> +
> +vcvtps2<cvtps8>, 0x<cvtps8:pfx><cvtps8:opc>, AVX10_V2_AUX,
> Modrm|Map5|EVex128|VexW0|Masking|Broadcast|Disp8MemShift=4|NoS
> uf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
> +vcvtps2<cvtps8>, 0x<cvtps8:pfx><cvtps8:opc>, AVX10_V2_AUX,
> Modrm|Map5|EVex256|VexW0|Masking|Broadcast|Disp8MemShift=5|NoS
> uf, { RegYMM|Dword|Unspecified|BaseIndex, RegXMM }
> +vcvtps2<cvtps8>, 0x<cvtps8:pfx><cvtps8:opc>, AVX10_V2_AUX,
> Modrm|Map5|EVex512|VexW0|Masking|Broadcast|Disp8MemShift=6|NoS
> uf, { RegZMM|Dword|Unspecified|BaseIndex, RegXMM }

Disp8ShiftVL will combine Disp8MemShift=4/5/6. Then you could combine the
templates. Similar for vcvtro and vcvtbias.

> +
> +<cvtps8>
> +
> +<cvtrops8:opc, +
> +    hf8:38, +
> +    hf8s:3a>
> +
> +vcvtrops2<cvtrops8>, 0x66<cvtrops8:opc>, AVX10_V2_AUX,
> Modrm|Map5|EVex128|VexW0|Masking|Broadcast|Disp8MemShift=4|NoS
> uf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
> +vcvtrops2<cvtrops8>, 0x66<cvtrops8:opc>, AVX10_V2_AUX,
> Modrm|Map5|EVex256|VexW0|Masking|Broadcast|Disp8MemShift=5|NoS
> uf, { RegYMM|Dword|Unspecified|BaseIndex, RegXMM }
> +vcvtrops2<cvtrops8>, 0x66<cvtrops8:opc>, AVX10_V2_AUX,
> Modrm|Map5|EVex512|VexW0|Masking|Broadcast|Disp8MemShift=6|NoS
> uf, { RegZMM|Dword|Unspecified|BaseIndex, RegXMM }
> +
> +<cvtrops8>
> +
> +// VCVTBIASPS2BF8, VCVTBIASPS2BF8S, VCVTBIASPS2HF8,
> VCVTBIASPS2HF8S - 3-op narrowing (NP.MAP5)
> +
> +<cvtbiasps:opc, +
> +    bf8:39, +
> +    bf8s:3b, +
> +    hf8:38, +
> +    hf8s:3a>
> +
> +vcvtbiasps2<cvtbiasps>, 0x<cvtbiasps:opc>, AVX10_V2_AUX,
> Modrm|Map5|EVex128|Src1VVVV|VexW0|Masking|Broadcast|Disp8Mem
> Shift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM,
> RegXMM }
> +vcvtbiasps2<cvtbiasps>, 0x<cvtbiasps:opc>, AVX10_V2_AUX,
> Modrm|Map5|EVex256|Src1VVVV|VexW0|Masking|Broadcast|Disp8Mem
> Shift=5|NoSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegYMM,
> RegXMM }
> +vcvtbiasps2<cvtbiasps>, 0x<cvtbiasps:opc>, AVX10_V2_AUX,
> Modrm|Map5|EVex512|Src1VVVV|VexW0|Masking|Broadcast|Disp8Mem
> Shift=6|NoSuf, { RegZMM|Dword|Unspecified|BaseIndex, RegZMM,
> RegXMM }
> +
> +<cvtbiasps>
> +
> +// VCVTBF82PS (NP.MAP5.W1) and VCVTHF82PS (NP.MAP5.W0) - widening
> xmm/m to xmm/ymm/zmm
> +vcvtbf82ps, 0x36, AVX10_V2_AUX,
> Modrm|Map5|EVex128|VexW1|Masking|Disp8MemShift=2|NoSuf,
> { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
> +vcvtbf82ps, 0x36, AVX10_V2_AUX,
> Modrm|Map5|EVex256|VexW1|Masking|Disp8MemShift=3|NoSuf,
> { RegXMM|Qword|Unspecified|BaseIndex, RegYMM }
> +vcvtbf82ps, 0x36, AVX10_V2_AUX,
> Modrm|Map5|EVex512|VexW1|Masking|Disp8MemShift=4|NoSuf,
> { RegXMM|Unspecified|BaseIndex, RegZMM }
> +
> +vcvthf82ps, 0x36, AVX10_V2_AUX,
> Modrm|Map5|EVex128|VexW0|Masking|Disp8MemShift=2|NoSuf,
> { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
> +vcvthf82ps, 0x36, AVX10_V2_AUX,
> Modrm|Map5|EVex256|VexW0|Masking|Disp8MemShift=3|NoSuf,
> { RegXMM|Qword|Unspecified|BaseIndex, RegYMM }
> +vcvthf82ps, 0x36, AVX10_V2_AUX,
> Modrm|Map5|EVex512|VexW0|Masking|Disp8MemShift=4|NoSuf,
> { RegXMM|Unspecified|BaseIndex, RegZMM }

You could combine bf and hf with <fp>, where bf as VexW1, hf as VexW0.
Similar for other cases.

> +
> +// VCVTBF82BF4S (F3.MAP5.W1) and VCVTHF82BF4S (F3.MAP5.W0) -
> narrowing, no mask
> +vcvtbf82bf4s, 0xf33d, AVX10_V2_AUX,
> Modrm|Map5|EVex128|VexW1|Disp8MemShift=3|NoSuf, { RegXMM,
> RegXMM|Qword|Unspecified|BaseIndex }

We may need RegMem to swap the operand.

If I miss something, I will reply afterwards.

Thx,
Haochen

From jbeulich@suse.com  Mon Jun 29 06:21:58 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Mon, 29 Jun 2026 08:21:58 +0200
Subject: [PATCH v1 1/2] Support AVX10_V2_AUX instructions
In-Reply-To: <IA4PR11MB90099AD311BE8AAFACDF3873ECE82@IA4PR11MB9009.namprd11.prod.outlook.com>
References: <20260627095543.1627012-1-Ganesh.Gopalasubramanian@amd.com>
 <20260627095543.1627012-2-Ganesh.Gopalasubramanian@amd.com>
 <IA4PR11MB90099AD311BE8AAFACDF3873ECE82@IA4PR11MB9009.namprd11.prod.outlook.com>
Message-ID: <a6c192c9-4e8e-417d-8473-0db71ba1c0d1@suse.com>

On 29.06.2026 05:41, Jiang, Haochen wrote:
>> From: Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
>> Sent: Saturday, June 27, 2026 5:56 PM
>> +  /* PREFIX_EVEX_MAP5_3C */
>> +  {
>> +    { Bad_Opcode },
>> +    { "vcvthf82hf6s",	{ XM, EXx }, 0 },
>> +  },
> 
> There are several mod table pass missing throughout
> the implementation. You need restrict MOD.R/M as
> 11 here.
> 
> Also, for non-broadcast operands, please use
> EXEvexXNoBcst instead of EXx.

Except that in cases where memory operands aren't allowed in the first place,
that won't be necessary (nor wanted, for adding clutter).

>> --- a/opcodes/i386-dis-evex-w.h
>> +++ b/opcodes/i386-dis-evex-w.h
>> +  /* EVEX_W_MAP5_3E_P_1 */
>> +  {
>> +    { Bad_Opcode },
>> +    { "vcvtbf82bf6s",	{ XM, EXx }, 0 },
>> +  },
> 
> Please pass W table before prefix table to reduce
> potential tree size.

Judging from the name of the identifier in the comment that's the case already?
With major opcodes 0x3c and 0x3e having only a single code point for now, there
may also be no difference in table size.

>> --- a/opcodes/i386-dis-evex.h
>> +++ b/opcodes/i386-dis-evex.h
>> @@ -652,7 +652,7 @@ static const struct dis386 evex_table[][256] = {
>>      { EVEX_LEN_TABLE (EVEX_LEN_0F3A3A) },
>>      { EVEX_LEN_TABLE (EVEX_LEN_0F3A3B) },
>>      { Bad_Opcode },
>> -    { Bad_Opcode },
>> +    { "vunpackb",	{ XM, EXx, Ib }, 0 },
> 
> Missing W and prefix table pass here.

Going through prefix_table[] shouldn't be needed: NO_PREFIX could be used to
"replace" that.

>> --- a/opcodes/i386-opc.tbl
>> +++ b/opcodes/i386-opc.tbl
>> @@ -3620,6 +3620,95 @@ vucomxs<sdh>, 0x<sdh:spfx>2e, AVX10_2,
>> Modrm|EVexLIG|<sdh:spc1>|<sdh:vexw>|Disp8
>>
>>  // AVX10.2 instructions end.
>>
>> +// AVX10_V2_AUX instructions.

AVX10.2-aux

>> +// VCVTPS2BF8, VCVTPS2BF8S, VCVTPS2HF8, VCVTPS2HF8S - narrowing 2-
>> op (F3.MAP5)
>> +// VCVTROPS2HF8, VCVTROPS2HF8S - narrowing 2-op (66.MAP5)

Please limit such commentary to what you find elsewhere. That is, nothing at
all here. Unexpected aspects, anomalies, etc of course want commenting.

>> +<cvtps8:opc:pfx, +
>> +    bf8:39:f3, +
>> +    bf8s:3b:f3, +
>> +    hf8:38:f3, +
>> +    hf8s:3a:f3>
> 
> Why do you need to put pfx in iterator? They are all f3.
> 
> And we could simply separate them as <fp8> and <sat> here, not <cvtps8>,
> <cvtrops8>, <cvtbiasps8>, where <fp8> has the base opcode 38 and 39,
> <sat> add 2 for them when there is saturation.

Splitting likely won't be a benefit here, and we didn't do so for AVX10.1 (see
<cvt8:...> there.

Jan

From srinath.parvathaneni@arm.com  Mon Jun 29 07:31:58 2026
From: srinath.parvathaneni@arm.com (srinath.parvathaneni@arm.com)
Date: Mon, 29 Jun 2026 07:31:58 +0000
Subject: [PATCH v1] bfd/readelf: Add core file support for FEAT_S1POE
Message-ID: <20260629073158.36053-1-srinath.parvathaneni@arm.com>

From: Srinath Parvathaneni <srinath.parvathaneni@arm.com>

Hi,

Add support for `NT_ARM_POE` dumps/reads for core files.

Regression tested for aarch64-none-linux-gnu target and
found no regressions.

Ok for binutils-master?

Regards,
Srinath.
---
 bfd/elf.c            | 25 +++++++++++++++++++++++++
 binutils/readelf.c   |  2 ++
 include/elf/common.h |  2 ++
 3 files changed, 29 insertions(+)

diff --git a/bfd/elf.c b/bfd/elf.c
index c9a68404e9d..c7f557b8be6 100644
--- a/bfd/elf.c
+++ b/bfd/elf.c
@@ -64,6 +64,7 @@ SECTION
 /* Names of a pseudo-section which represent core notes.  */
 #define NOTE_PSEUDO_SECTION_AARCH_FPMR		".reg-aarch-fpmr"
 #define NOTE_PSEUDO_SECTION_AARCH_GCS		".reg-aarch-gcs"
+#define NOTE_PSEUDO_SECTION_AARCH_POE		".reg-aarch-poe"
 #define NOTE_PSEUDO_SECTION_AARCH_HW_BREAK	".reg-aarch-hw-break"
 #define NOTE_PSEUDO_SECTION_AARCH_HW_WATCH	".reg-aarch-hw-watch"
 #define NOTE_PSEUDO_SECTION_AARCH_MTE		".reg-aarch-mte"
@@ -10735,6 +10736,15 @@ elfcore_grok_aarch_gcs (bfd *abfd, Elf_Internal_Note *note)
   return elfcore_make_note_pseudosection (abfd, NOTE_PSEUDO_SECTION_AARCH_GCS, note);
 }
 
+/* Convert NOTE into a bfd_section called ".reg-aarch-poe".  Return TRUE if
+   successful, otherwise return FALSE.  */
+
+static bool
+elfcore_grok_aarch_poe (bfd *abfd, Elf_Internal_Note *note)
+{
+  return elfcore_make_note_pseudosection (abfd, NOTE_PSEUDO_SECTION_AARCH_POE, note);
+}
+
 /* Convert NOTE into the appropriate note pseudo-section for the AArch64 FPMR.
  * Return TRUE if successful, otherwise return FALSE.  */
 
@@ -11179,6 +11189,7 @@ elfcore_grok_note (bfd *abfd, Elf_Internal_Note *note)
 	case NT_ARC_V2:		return elfcore_grok_arc_v2 (abfd, note);
 	case NT_ARM_FPMR:	return elfcore_grok_aarch_fpmr (abfd, note);
 	case NT_ARM_GCS:	return elfcore_grok_aarch_gcs (abfd, note);
+	case NT_ARM_POE:	return elfcore_grok_aarch_poe (abfd, note);
 	case NT_ARM_HW_BREAK:	return elfcore_grok_aarch_hw_break (abfd, note);
 	case NT_ARM_HW_WATCH:	return elfcore_grok_aarch_hw_watch (abfd, note);
 	case NT_ARM_PAC_MASK:	return elfcore_grok_aarch_pauth (abfd, note);
@@ -12900,6 +12911,19 @@ elfcore_write_aarch_gcs (bfd *abfd, char *buf, int *bufsiz,
 			     aarch_gcs, size);
 }
 
+/* Write the buffer of POE register values in AARCH_POE (length SIZE) into
+   the note buffer BUF and update *BUFSIZ.  ABFD is the bfd the note is being
+   written into.  Return a pointer to the new start of the note buffer, to
+   replace BUF which may no longer be valid.  */
+
+static char *
+elfcore_write_aarch_poe (bfd *abfd, char *buf, int *bufsiz,
+			 const void *aarch_poe, int size)
+{
+  return elfcore_write_note (abfd, buf, bufsiz, NOTE_NAME_LINUX, NT_ARM_POE,
+			     aarch_poe, size);
+}
+
 /* Write the buffer of FPMR value in AARCH_FPMR (length SIZE) into
    the note buffer BUF and update *BUFSIZ.  ABFD is the bfd the note is being
    written into.  Return a pointer to the new start of the note buffer, to
@@ -13024,6 +13048,7 @@ elfcore_write_register_note (bfd *abfd,
     {
       { NOTE_PSEUDO_SECTION_AARCH_FPMR,       elfcore_write_aarch_fpmr},
       { NOTE_PSEUDO_SECTION_AARCH_GCS,        elfcore_write_aarch_gcs},
+      { NOTE_PSEUDO_SECTION_AARCH_POE,        elfcore_write_aarch_poe},
       { NOTE_PSEUDO_SECTION_AARCH_HW_BREAK,   elfcore_write_aarch_hw_break},
       { NOTE_PSEUDO_SECTION_AARCH_HW_WATCH,   elfcore_write_aarch_hw_watch},
       { NOTE_PSEUDO_SECTION_AARCH_MTE,        elfcore_write_aarch_mte},
diff --git a/binutils/readelf.c b/binutils/readelf.c
index bf27f9eec23..61354d7ab11 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -21915,6 +21915,8 @@ get_note_type (Filedata * filedata, unsigned e_type)
 	return _("NT_ARM_PAC_ENABLED_KEYS (AArch64 pointer authentication enabled keys)");
       case NT_ARM_FPMR:
 	return _("NT_ARM_FPMR (AArch64 Floating Point Mode Register)");
+      case NT_ARM_POE:
+	return _("NT_ARM_POE (AArch64 Permission Overlay Extension Register)");
       case NT_ARC_V2:
 	return _("NT_ARC_V2 (ARC HS accumulator/extra registers)");
       case NT_RISCV_CSR:
diff --git a/include/elf/common.h b/include/elf/common.h
index 1ae68221a89..f811b8daeb5 100644
--- a/include/elf/common.h
+++ b/include/elf/common.h
@@ -760,6 +760,8 @@
 					/*   Note: name must be "LINUX".  */
 #define NT_ARM_FPMR     0x40e           /* AArch64 FPMR.  */
 					/*   Note: name must be "LINUX".  */
+#define NT_ARM_POE	0x40f		/* AArch64 POE register.  */
+					/*   Note: name must be "LINUX".  */
 #define NT_ARM_GCS	0x410		/* AArch64 Guarded Control Stack
 					   registers.  */
 					/*   Note  name must be "LINUX".  */
-- 
2.43.0


From jdx@o2.pl  Mon Jun 29 07:27:22 2026
From: jdx@o2.pl (Jan Dubiec)
Date: Mon, 29 Jun 2026 09:27:22 +0200
Subject: [PATCH] ld: Skip p33265-2 and pr33265-2 tests on Windows
Message-ID: <20260629072757.72898-1-jdx@o2.pl>

These tests are expected to fail on Windows because by default maximum path length
is only 260 characters:
https://learn.microsoft.com/en-us/windows/win32/fileio/maximum-file-path-limitation?tabs=registry

Theoretically the issue could be fixed in two ways, as pointed in the linked article:
   1. using the "\\?\" prefix, but this probably requires a lot of work
   and should be done "binutils-wide", i.e. all tools should be reviewed
   from this point of view,
   2. using manifest file, but this still would require an action from
   the user ? they would have to turn on long paths support in the
   Windows registry.

Excerpt from the log:
[...]
PASS: ld-scripts/pr33265-1
/d/Works/xcomp/build-binutils-h8300-mingw/ld/../gas/as-new     -o tmpdir/start.o /d/Works/binutils/ld/testsuite/ld-scripts/start.s
Executing on host: sh -c {/d/Works/xcomp/build-binutils-h8300-mingw/ld/../gas/as-new     -o tmpdir/start.o /d/Works/binutils/ld/testsuite/ld-scripts/start.s 2>&1}  /dev/null dump.tmp (timeout = 300)
spawn [open ...]
./ld-new   -L/d/Works/binutils/ld/testsuite/ld-scripts  -r --whole-archive -lpr33265-2 -o tmpdir/dump tmpdir/start.o 
Executing on host: sh -c {./ld-new   -L/d/Works/binutils/ld/testsuite/ld-scripts  -r --whole-archive -lpr33265-2 -o tmpdir/dump tmpdir/start.o  2>&1}  /dev/null dump.tmp (timeout = 300)
spawn [open ...]
D:\Works\xcomp\build-binutils-h8300-mingw\ld\ld-new.exe: cannot open linker script file D:/Works/binutils/ld/testsuite/ld-scripts\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\./././././/libpr33265-2.a: No such file or directory
failed with: <\Works\xcomp\build-binutils-h8300-mingw\ld\ld-new.exe: cannot open linker script file D:/Works/binutils/ld/testsuite/ld-scripts\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\./././././/libpr33265-2.a: No such file or directory>, expected: <.*group nested too deeply.*>
FAIL: ld-scripts/pr33265-2
/d/Works/xcomp/build-binutils-h8300-mingw/ld/../gas/as-new     -o tmpdir/start.o /d/Works/binutils/ld/testsuite/ld-scripts/start.s
Executing on host: sh -c {/d/Works/xcomp/build-binutils-h8300-mingw/ld/../gas/as-new     -o tmpdir/start.o /d/Works/binutils/ld/testsuite/ld-scripts/start.s 2>&1}  /dev/null dump.tmp (timeout = 300)
spawn [open ...]
./ld-new   -L/d/Works/binutils/ld/testsuite/ld-scripts  -r --whole-archive -lpr33265-3a -o tmpdir/dump tmpdir/start.o 
Executing on host: sh -c {./ld-new   -L/d/Works/binutils/ld/testsuite/ld-scripts  -r --whole-archive -lpr33265-3a -o tmpdir/dump tmpdir/start.o  2>&1}  /dev/null dump.tmp (timeout = 300)
spawn [open ...]
D:\Works\xcomp\build-binutils-h8300-mingw\ld\ld-new.exe: cannot open linker script file D:/Works/binutils/ld/testsuite/ld-scripts\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\./././././/libpr33265-3b.a: No such file or directory
failed with: <\Works\xcomp\build-binutils-h8300-mingw\ld\ld-new.exe: cannot open linker script file D:/Works/binutils/ld/testsuite/ld-scripts\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\./././././/libpr33265-3b.a: No such file or directory>, expected: <.*group nested too deeply.*>
FAIL: ld-scripts/pr33265-3
testcase /d/Works/binutils/ld/testsuite/ld-scripts/script.exp completed in 6 seconds
[...]

ld/
	* testsuite/ld-scripts/script.exp: Skip p33265-2 and pr33265-2
	tests on Windows because default path length is too short.
---
 ld/testsuite/ld-scripts/script.exp | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/ld/testsuite/ld-scripts/script.exp b/ld/testsuite/ld-scripts/script.exp
index ff65e397b6b..4ac338589e1 100644
--- a/ld/testsuite/ld-scripts/script.exp
+++ b/ld/testsuite/ld-scripts/script.exp
@@ -246,7 +246,11 @@ run_dump_test "segment-start" {{name (overridden)} \
 			       {ld -Ttext-segment=0x10000000}}
 
 run_dump_test "pr33265-1"
-run_dump_test "pr33265-2"
-run_dump_test "pr33265-3"
+# On Windows hosts the following two cases are expected to fail because
+# by default maximum path length is only 260 characters.
+if { ![ishost *-mingw*] } {
+    run_dump_test "pr33265-2"
+    run_dump_test "pr33265-3"
+}
 
 set LDFLAGS $old_LDFLAGS
-- 
2.54.0


From jbeulich@suse.com  Mon Jun 29 07:54:09 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Mon, 29 Jun 2026 09:54:09 +0200
Subject: [PATCH] ld: Skip p33265-2 and pr33265-2 tests on Windows
In-Reply-To: <20260629072757.72898-1-jdx@o2.pl>
References: <20260629072757.72898-1-jdx@o2.pl>
Message-ID: <01119d26-0ae4-4a32-af55-9f913756d8c8@suse.com>

On 29.06.2026 09:27, Jan Dubiec wrote:
> These tests are expected to fail on Windows because by default maximum path length
> is only 260 characters:
> https://learn.microsoft.com/en-us/windows/win32/fileio/maximum-file-path-limitation?tabs=registry
> 
> Theoretically the issue could be fixed in two ways, as pointed in the linked article:
>    1. using the "\\?\" prefix, but this probably requires a lot of work
>    and should be done "binutils-wide", i.e. all tools should be reviewed
>    from this point of view,
>    2. using manifest file, but this still would require an action from
>    the user ? they would have to turn on long paths support in the
>    Windows registry.

Based on this, imo the two tests should become XFAILs instead of being excluded
altogether. However, ...

> Excerpt from the log:
> [...]
> PASS: ld-scripts/pr33265-1
> /d/Works/xcomp/build-binutils-h8300-mingw/ld/../gas/as-new     -o tmpdir/start.o /d/Works/binutils/ld/testsuite/ld-scripts/start.s
> Executing on host: sh -c {/d/Works/xcomp/build-binutils-h8300-mingw/ld/../gas/as-new     -o tmpdir/start.o /d/Works/binutils/ld/testsuite/ld-scripts/start.s 2>&1}  /dev/null dump.tmp (timeout = 300)
> spawn [open ...]
> ./ld-new   -L/d/Works/binutils/ld/testsuite/ld-scripts  -r --whole-archive -lpr33265-2 -o tmpdir/dump tmpdir/start.o 
> Executing on host: sh -c {./ld-new   -L/d/Works/binutils/ld/testsuite/ld-scripts  -r --whole-archive -lpr33265-2 -o tmpdir/dump tmpdir/start.o  2>&1}  /dev/null dump.tmp (timeout = 300)
> spawn [open ...]
> D:\Works\xcomp\build-binutils-h8300-mingw\ld\ld-new.exe: cannot open linker script file D:/Works/binutils/ld/testsuite/ld-scripts\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\./././././/libpr33265-2.a: No such file or directory

... where are these absurd paths coming from? If there wasn't this excessive
referencing of the current directory, not problem would arise in the first
place, as it looks.

> --- a/ld/testsuite/ld-scripts/script.exp
> +++ b/ld/testsuite/ld-scripts/script.exp
> @@ -246,7 +246,11 @@ run_dump_test "segment-start" {{name (overridden)} \
>  			       {ld -Ttext-segment=0x10000000}}
>  
>  run_dump_test "pr33265-1"
> -run_dump_test "pr33265-2"
> -run_dump_test "pr33265-3"
> +# On Windows hosts the following two cases are expected to fail because
> +# by default maximum path length is only 260 characters.
> +if { ![ishost *-mingw*] } {
> +    run_dump_test "pr33265-2"
> +    run_dump_test "pr33265-3"
> +}

What about Cygwin? Does this somehow circumvent the issue?

Jan

From jbeulich@suse.com  Mon Jun 29 07:57:03 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Mon, 29 Jun 2026 09:57:03 +0200
Subject: [PATCH v1 1/2] Support AVX10_V2_AUX instructions
In-Reply-To: <20260627095543.1627012-2-Ganesh.Gopalasubramanian@amd.com>
References: <20260627095543.1627012-1-Ganesh.Gopalasubramanian@amd.com>
 <20260627095543.1627012-2-Ganesh.Gopalasubramanian@amd.com>
Message-ID: <ce0d35ec-b25f-436e-953b-207861f57c52@suse.com>

On 27.06.2026 11:55, Ganesh Gopalasubramanian wrote:
> - AVX10_V1_AUX instructions are already present as part of AVX10.2
> instructions. They are just available under new cpuid bit.
> - AVX10_V2_AUX are new x86 instructions.
> 
> Reference: AI Compute Extensions (ACE) Specification, v1.15
> https://x86ecosystem.org/wp-content/uploads/2026/06/ACE_v1_Specification_public_1_15.pdf

Is there going to be a more dedicated revision of the AVX10 spec, covering
10.2-aux?

Jan

From jbeulich@suse.com  Mon Jun 29 08:03:43 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Mon, 29 Jun 2026 10:03:43 +0200
Subject: [PATCH v1 1/2] Support AVX10_V2_AUX instructions
In-Reply-To: <a6c192c9-4e8e-417d-8473-0db71ba1c0d1@suse.com>
References: <20260627095543.1627012-1-Ganesh.Gopalasubramanian@amd.com>
 <20260627095543.1627012-2-Ganesh.Gopalasubramanian@amd.com>
 <IA4PR11MB90099AD311BE8AAFACDF3873ECE82@IA4PR11MB9009.namprd11.prod.outlook.com>
 <a6c192c9-4e8e-417d-8473-0db71ba1c0d1@suse.com>
Message-ID: <36607945-e0ac-4293-84eb-54229815a24e@suse.com>

On 29.06.2026 08:21, Jan Beulich wrote:
> On 29.06.2026 05:41, Jiang, Haochen wrote:
>>> --- a/opcodes/i386-dis-evex-w.h
>>> +++ b/opcodes/i386-dis-evex-w.h
>>> +  /* EVEX_W_MAP5_3E_P_1 */
>>> +  {
>>> +    { Bad_Opcode },
>>> +    { "vcvtbf82bf6s",	{ XM, EXx }, 0 },
>>> +  },
>>
>> Please pass W table before prefix table to reduce
>> potential tree size.
> 
> Judging from the name of the identifier in the comment that's the case already?

Scratch this part of my earlier reply.

Jan

From jbeulich@suse.com  Mon Jun 29 08:23:27 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Mon, 29 Jun 2026 10:23:27 +0200
Subject: [PATCH v1 1/2] Support AVX10_V2_AUX instructions
In-Reply-To: <20260627095543.1627012-2-Ganesh.Gopalasubramanian@amd.com>
References: <20260627095543.1627012-1-Ganesh.Gopalasubramanian@amd.com>
 <20260627095543.1627012-2-Ganesh.Gopalasubramanian@amd.com>
Message-ID: <c8532d49-3a19-4412-9177-e2b7fa535249@suse.com>

On 27.06.2026 11:55, Ganesh Gopalasubramanian wrote:
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -3620,6 +3620,95 @@ vucomxs<sdh>, 0x<sdh:spfx>2e, AVX10_2, Modrm|EVexLIG|<sdh:spc1>|<sdh:vexw>|Disp8
>  
>  // AVX10.2 instructions end.
>  
> +// AVX10_V2_AUX instructions.
> +
> +// VCVTPS2BF8, VCVTPS2BF8S, VCVTPS2HF8, VCVTPS2HF8S - narrowing 2-op (F3.MAP5)
> +// VCVTROPS2HF8, VCVTROPS2HF8S - narrowing 2-op (66.MAP5)
> +
> +<cvtps8:opc:pfx, +
> +    bf8:39:f3, +
> +    bf8s:3b:f3, +
> +    hf8:38:f3, +
> +    hf8s:3a:f3>
> +
> +vcvtps2<cvtps8>, 0x<cvtps8:pfx><cvtps8:opc>, AVX10_V2_AUX, Modrm|Map5|EVex128|VexW0|Masking|Broadcast|Disp8MemShift=4|NoSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM }
> +vcvtps2<cvtps8>, 0x<cvtps8:pfx><cvtps8:opc>, AVX10_V2_AUX, Modrm|Map5|EVex256|VexW0|Masking|Broadcast|Disp8MemShift=5|NoSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegXMM }
> +vcvtps2<cvtps8>, 0x<cvtps8:pfx><cvtps8:opc>, AVX10_V2_AUX, Modrm|Map5|EVex512|VexW0|Masking|Broadcast|Disp8MemShift=6|NoSuf, { RegZMM|Dword|Unspecified|BaseIndex, RegXMM }

To extend what Haochen has said, please go look at pre-existing templates (preferably
ones added more recently, as older ones may have legacy quirks) to see how patterns
like this want handling.

> +// VCVTBF82BF6S (F3.MAP5.W1) - reg-reg only, no mask
> +vcvtbf82bf6s, 0xf33e, AVX10_V2_AUX, Modrm|Map5|EVex128|VexW1|NoSuf, { RegXMM, RegXMM }
> +vcvtbf82bf6s, 0xf33e, AVX10_V2_AUX, Modrm|Map5|EVex256|VexW1|NoSuf, { RegYMM, RegYMM }
> +vcvtbf82bf6s, 0xf33e, AVX10_V2_AUX, Modrm|Map5|EVex512|VexW1|NoSuf, { RegZMM, RegZMM }

These and ...

> +// VCVTHF82HF6S (F3.MAP5.W0) - reg-reg only, no mask
> +vcvthf82hf6s, 0xf33c, AVX10_V2_AUX, Modrm|Map5|EVex128|VexW0|NoSuf, { RegXMM, RegXMM }
> +vcvthf82hf6s, 0xf33c, AVX10_V2_AUX, Modrm|Map5|EVex256|VexW0|NoSuf, { RegYMM, RegYMM }
> +vcvthf82hf6s, 0xf33c, AVX10_V2_AUX, Modrm|Map5|EVex512|VexW0|NoSuf, { RegZMM, RegZMM }

... these want folding into one (each). Just like you have it ...

> +// VUNPACKB (NP.0F3A.W0) - with imm8
> +vunpackb, 0x3d, AVX10_V2_AUX, Modrm|Masking|Space0F3A|VexW0|Disp8ShiftVL|CheckOperandSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
... here.

Jan

From jbeulich@suse.com  Mon Jun 29 08:45:00 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Mon, 29 Jun 2026 10:45:00 +0200
Subject: [PATCH] x86/gas: add missing RegBND to debugging code
Message-ID: <2557bc68-e260-4d2f-901f-5a3fadd2b254@suse.com>

This must have been overlooked when MPX support was added.

--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -3932,6 +3932,7 @@ const type_names[] =
   { { .bitfield = { .class = RegSIMD, .zmmword = 1 } }, "rZMM" },
   { { .bitfield = { .class = RegSIMD, .tmmword = 1 } }, "rTMM" },
   { { .bitfield = { .class = RegMask } }, "Mask reg" },
+  { { .bitfield = { .class = RegBND } }, "rBND" },
 };
 
 static void

From haochen.jiang@intel.com  Mon Jun 29 08:51:20 2026
From: haochen.jiang@intel.com (Jiang, Haochen)
Date: Mon, 29 Jun 2026 08:51:20 +0000
Subject: [PATCH v1 1/2] Support AVX10_V2_AUX instructions
In-Reply-To: <ce0d35ec-b25f-436e-953b-207861f57c52@suse.com>
References: <20260627095543.1627012-1-Ganesh.Gopalasubramanian@amd.com>
 <20260627095543.1627012-2-Ganesh.Gopalasubramanian@amd.com>
 <ce0d35ec-b25f-436e-953b-207861f57c52@suse.com>
Message-ID: <IA4PR11MB900937DF7F4B109033884985ECE82@IA4PR11MB9009.namprd11.prod.outlook.com>

> From: Jan Beulich <jbeulich@suse.com>
> Sent: Monday, June 29, 2026 3:57 PM
> 
> On 27.06.2026 11:55, Ganesh Gopalasubramanian wrote:
> > - AVX10_V1_AUX instructions are already present as part of AVX10.2
> > instructions. They are just available under new cpuid bit.
> > - AVX10_V2_AUX are new x86 instructions.
> >
> > Reference: AI Compute Extensions (ACE) Specification, v1.15
> > https://x86ecosystem.org/wp-
> content/uploads/2026/06/ACE_v1_Specification_public_1_15.pdf
> 
> Is there going to be a more dedicated revision of the AVX10 spec, covering
> 10.2-aux?
> 

I don't see that on the table currently since there is a joint documentation
already. But it should happen one day since we have AVX10_V1_AUX in avx10
spec.

Thx,
Haochen

From ro@CeBiTec.Uni-Bielefeld.DE  Mon Jun 29 09:19:28 2026
From: ro@CeBiTec.Uni-Bielefeld.DE (Rainer Orth)
Date: Mon, 29 Jun 2026 11:19:28 +0200
Subject: [PATCH] Remove 32-bit-only Solaris configurations
Message-ID: <yddik71d7q7.fsf@CeBiTec.Uni-Bielefeld.DE>

After the removal of all Solaris configurations but Solaris 10/11
(*-*-solaris2.1[01]), the 32-bit-only configurations can no longer be
matched.  This patch removes them.

Tested on {amd64,i386}-pc-solaris2.11 and sparc{v9,}-sun-solaris2.11.

Ok for trunk.

I thought about obsoleting Solaris 10, too, because it's no longer
tested.  However, AFAICS there's no Solaris 10-specific code or
workaround present.  I've also checked that trunk still builds on
Solaris 10, unlike Solaris 8 and 9 which already didn't build before
their removal, so such an obsoletion would gain nothing.

	Rainer

-- 
-----------------------------------------------------------------------------
Rainer Orth, Center for Biotechnology, Bielefeld University


2026-06-28  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>

	bfd:
	* config.bfd <i[3-7]86-*-solaris*>: Remove.
	<sparc*-*-solaris*>: Likewise.

	ld:
	* configure.tgt <i[3-7]86-*-solaris*>: Remove.
	<sparc*-*-solaris*>: Likewise.

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From ro@CeBiTec.Uni-Bielefeld.DE  Mon Jun 29 09:26:12 2026
From: ro@CeBiTec.Uni-Bielefeld.DE (Rainer Orth)
Date: Mon, 29 Jun 2026 11:26:12 +0200
Subject: [PATCH] bfd: Always use CP_ACP=1 on Solaris [PR11280]
Message-ID: <yddechpd7ez.fsf@CeBiTec.Uni-Bielefeld.DE>

bfd/configure.host defines CP_ACP=1 on Solaris 11 as a workaround for
the lack the MS-ANSI codepage in Solaris libc iconv(3C).  However, the
issue isn't restricted to some OpenSolaris build as the comment
suggests, but present on Solaris in general as can be seen in the iconv -l
output:

On both Solaris 10 and 11.4, one gets

	CP1252 (1252, ANSI-1252, WINDOWS-1252),

unlike GNU iconv which lists

	CP1252 MS-ANSI WINDOWS-1252

Therefore, this patch applies the patch on all Solaris versions.

Tested on {amd64,i386}-pc-solaris2.11 and sparc{v9,}-sun-solaris2.11.

Ok for trunk?


I didn't try to reproduce the original issue as reported in PR
binutils/11280, but just went by the description there.

	Rainer

-- 
-----------------------------------------------------------------------------
Rainer Orth, Center for Biotechnology, Bielefeld University


2026-06-28  Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>

	bfd:
	PR binutils/11280
	* configure.host (HDEFINES): Always define CP_ACP=1 on Solaris.

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From jbeulich@suse.com  Mon Jun 29 09:52:44 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Mon, 29 Jun 2026 11:52:44 +0200
Subject: [PATCH v1 2/2] Support x86 ACE ISA
In-Reply-To: <20260627115338.1632761-1-Ganesh.Gopalasubramanian@amd.com>
References: <20260627095543.1627012-1-Ganesh.Gopalasubramanian@amd.com>
 <20260627115338.1632761-1-Ganesh.Gopalasubramanian@amd.com>
Message-ID: <196a627b-0727-4ff9-ac35-cf29a8fa1207@suse.com>

On 27.06.2026 13:53, Ganesh Gopalasubramanian wrote:
> @@ -4253,6 +4257,7 @@ install_template (const insn_template *t)
>  	}
>  
>        if ((maybe_cpu (t, CpuCMPCCXADD) || maybe_cpu (t, CpuAMX_TILE)
> +	   || maybe_cpu (t, CpuACE)
>  	   || maybe_cpu (t, CpuAVX512F) || maybe_cpu (t, CpuAVX512DQ)
>  	   || maybe_cpu (t, CpuAVX512BW) || maybe_cpu (t, CpuBMI)
>  	   || maybe_cpu (t, CpuBMI2) || maybe_cpu (t, CpuUSER_MSR)

Please can you append to such conditionals, or at least insert based on
how many templates there are, and hence (very vaguely) how often one of
them would make it here? (The ordering here is far from great, but I
think ACE wants to at least go after AVX512*.)

> @@ -9323,6 +9331,29 @@ check_APX_operands (const insn_template *t)
>    return 0;
>  }
>  
> +/* Check if ACE operands are valid for the instruction.  */
> +static bool
> +check_ACE_operands (const insn_template *t)
> +{
> +  switch (t->mnem_off)
> +    {
> +    case MN_tilemovrow:
> +    case MN_tilemovcol:
> +      if (is_cpu (t, CpuACE)
> +	  && i.op[0].imms && i.op[0].imms->X_op == O_constant)

i.op[].imms is a member of a union. You can't check or deref it without first
checking that the corresponding operand actually is an immediate one.

That said, ...

> +	{
> +	  offsetT val = i.op[0].imms->X_add_number;
> +	  if (val < 0 || val > 15)
> +	    {
> +	      i.error = unsupported_tile_index;
> +	      return 1;
> +	    }
> +	}
> +      break;
> +    }
> +  return 0;
> +}

... do we need such a check, seeing that the respective AMX-AVX512 insn doesn't
have one? And if so, should it perhaps better be a warning?

And then function having a return type "bool" want to return "true" / "false",
not 0 / 1. The fact that many pre-existing ones don't (yet) has historical
reasons.

> @@ -16943,13 +16982,18 @@ static bool check_register (const reg_entry *r)
>      return false;
>  
>    if (r->reg_type.bitfield.tmmword
> -      && (!cpu_arch_flags.bitfield.cpuamx_tile
> -          || flag_code != CODE_64BIT))
> +      && ((!cpu_arch_flags.bitfield.cpuamx_tile
> +	   && !cpu_arch_flags.bitfield.cpuace)
> +	  || flag_code != CODE_64BIT))
>      return false;
>  
>    if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx)
>      return false;
>  
> +  if (r->reg_type.bitfield.class == RegBS
> +      && !cpu_arch_flags.bitfield.cpuace)
> +    return false;

Juding from the earlier if(), this one also will fit on a single line, and
hence would better do so for uniformity.

> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-ace.s
> @@ -0,0 +1,45 @@
> +# Check 64-bit ACE instructions
> +
> +	.text
> +start:
> +	bsrinit %bsr0
> +	bsrmovf %zmm3, %zmm1, %bsr0
> +
> +	bsrmovh %zmm10, %bsr0
> +	bsrmovl %zmm10, %bsr0
> +	bsrmovh (%eax), %bsr0
> +	bsrmovl (%eax), %bsr0
> +
> +	bsrmovh %bsr0, %zmm4
> +	bsrmovl %bsr0, %zmm4
> +	bsrmovh %bsr0, (%eax)
> +	bsrmovl %bsr0, (%eax)
> +
> +	tilemovcol $8, %zmm2, %tmm1
> +	tilemovrow $8, %zmm2, %tmm1
> +
> +	tilemovcol %ebx, %zmm2, %tmm1
> +	tilemovrow %ebx, %zmm2, %tmm1
> +
> +	top2bf16ps %zmm2, %zmm1, %tmm0
> +	top4bssd   %zmm2, %zmm1, %tmm0
> +	top4bsud   %zmm2, %zmm1, %tmm0
> +	top4busd   %zmm2, %zmm1, %tmm0
> +	top4buud   %zmm2, %zmm1, %tmm0
> +
> +	top4mxbf8ps  $7, %zmm2, %zmm1, %tmm1
> +	top4mxbhf8ps $7, %zmm2, %zmm1, %tmm1
> +	top4mxhbf8ps $7, %zmm2, %zmm1, %tmm1
> +	top4mxhf8ps  $7, %zmm2, %zmm1, %tmm1
> +	top4mxbssps  $7, %zmm2, %zmm1, %tmm1
> +
> +	tcvtrowd2ps     %edx, %tmm5, %zmm30
> +	tcvtrowd2ps     $0x7b, %tmm5, %zmm30
> +	tcvtrowps2bf16h %edx, %tmm5, %zmm30
> +	tcvtrowps2bf16h $0x7b, %tmm5, %zmm30
> +	tcvtrowps2bf16l %edx, %tmm5, %zmm30
> +	tcvtrowps2bf16l $0x7b, %tmm5, %zmm30
> +	tcvtrowps2phh   %edx, %tmm5, %zmm30
> +	tcvtrowps2phh   $0x7b, %tmm5, %zmm30
> +	tcvtrowps2phl   %edx, %tmm5, %zmm30
> +	tcvtrowps2phl   $0x7b, %tmm5, %zmm30

If you cover pre-existing, re-used insns in the testcase, please cover them
all. For this to be really useful you will want to have another variant of
the test with the same output expectations, but with the ISA limited to ACE
(i.e. in particular no AMX). Iirc you can achieve this by having two #as:
lines (specifying different options) in the respective .d file(s).

> --- a/opcodes/i386-dis-evex-len.h
> +++ b/opcodes/i386-dis-evex-len.h
> @@ -51,6 +51,13 @@ static const struct dis386 evex_len_table[][3] = {
>      { PREFIX_TABLE (PREFIX_EVEX_0F384A_X86_64_W_0_L_2) },
>    },
>  
> +  /* EVEX_LEN_0F384B */
> +  {
> +    { X86_64_EVEX_W_TABLE (VEX_W_0F384B_X86_64_L_0) },
> +    { Bad_Opcode },
> +    { PREFIX_TABLE (PREFIX_EVEX_0F384B) },

The referenced enumerator needs renaming, to carry in its name that L_2
was already decoded.

> --- a/opcodes/i386-dis-evex-prefix.h
> +++ b/opcodes/i386-dis-evex-prefix.h
> @@ -254,6 +254,18 @@
>      { "tcvtrowd2ps",	{ XM, Rtmm, VexGdq }, 0 },
>      { "tilemovrow",	{ XM, Rtmm, VexGdq }, 0 },
>    },
> +  /* PREFIX_EVEX_0F384A */
> +  {
> +    { Bad_Opcode },
> +    { Bad_Opcode },
> +    { "tilemovrow",	{ TMM, Rzmm, VexGd }, 0 },
> +  },
> +  /* PREFIX_EVEX_0F384B */
> +  {
> +    { Bad_Opcode },
> +    { Bad_Opcode },
> +    { "tilemovcol",	{ TMM, Rzmm, VexGd }, 0 },

As per above, the enumerators in the comments need to specify what was
already decoded. As it stands, this gives the impression that neither
L'L nor W were. (Also applies elsewhere.)

> --- a/opcodes/i386-dis.c
> +++ b/opcodes/i386-dis.c
> @@ -70,6 +70,7 @@ static bool OP_D (instr_info *, int, int);
>  static bool OP_T (instr_info *, int, int);
>  static bool OP_MMX (instr_info *, int, int);
>  static bool OP_XMM (instr_info *, int, int);
> +static bool OP_BSR (instr_info *, int, int);
>  static bool OP_EM (instr_info *, int, int);
>  static bool OP_EX (instr_info *, int, int);
>  static bool OP_EMC (instr_info *, int,int);
> @@ -513,6 +514,7 @@ fetch_error (const instr_info *ins)
>  #define RMBH { OP_REG, bh_reg }
>  #define RMAX { OP_REG, ax_reg }
>  #define RMDX { OP_REG, dx_reg }
> +#define BSR { OP_BSR, bsr }
>  
>  #define eAX { OP_IMREG, eAX_reg }
>  #define AL { OP_IMREG, al_reg }
> @@ -566,6 +568,7 @@ fetch_error (const instr_info *ins)
>  #define EXxS { OP_EX, x_swap_mode }
>  #define EXxmm { OP_EX, xmm_mode }
>  #define EXymm { OP_EX, ymm_mode }
> +#define EXzmm { OP_EX, zmm_mode }

Why would this be needed? You use it in places where ordinary EVEX.L'L-
controlled reg/mem operands (without broadcast) are used, i.e. EXEvexXNoBcst
should do there.

> @@ -583,6 +586,7 @@ fetch_error (const instr_info *ins)
>  #define Uxmm { OP_R, xmm_mode }
>  #define Rxmmq { OP_R, xmmq_mode }
>  #define Rymm { OP_R, ymm_mode }
> +#define Rzmm { OP_R, zmm_mode }
The R-prefixed constants here aren't quite correct. As you can see newer
ones use U instead, and so should you. We try to match the SDM nomenclature.
And we already have Uxmm, which (like EXx / EXEvexXNoBcst above) should fit
here.

> @@ -600,6 +604,7 @@ fetch_error (const instr_info *ins)
>  #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
>  #define VexGdq { OP_VEX, dq_mode }
>  #define VexGb { OP_VEX, b_mode }
> +#define VexGd { OP_VEX, d_mode }

This doesn't match the existing TILEMOVROW and TCVTROW*, which use VexGdq.
With EVEX.W now gaining a different meaning, that wants sorting first (and
preferably separately).

> @@ -821,6 +828,8 @@ enum
>    rSI_reg,
>    rDI_reg,
>  
> +  bsr,

Do we really need this when OP_BSR() is a separate routine anyway?

> --- a/opcodes/i386-gen.c
> +++ b/opcodes/i386-gen.c
> @@ -263,6 +263,8 @@ static const dependency isa_dependencies[] =
>      "RTM|HLE" },
>    { "TSXLDTRK",
>      "RTM" },
> +  { "ACE",
> +    "AVX512F|64" },

Isn't AVX512BW|AVX512_BF16 the minimally sensible prereq, seeing the element
types of the outer-product insns?

> --- a/opcodes/i386-opc.h
> +++ b/opcodes/i386-opc.h
> @@ -359,6 +359,8 @@ enum i386_cpu
>    CpuAVX10_2,
>    /* Intel AMX-TRANSPOSE Instructions support required.  */
>    CpuAMX_TRANSPOSE,
> +  /* ACE instructions support required.  */
> +  CpuACE,
>    /* Not supported in the 64bit mode  */
>    CpuNo64,
>  
> @@ -397,6 +399,7 @@ enum i386_cpu
>  		   cpuapx_f:1, \
>  		   cpuavx10_2:1, \
>  		   cpuamx_transpose:1, \
> +		   cpuace:1, \
>        /* NOTE: This field needs to remain last. */ \
>  		   cpuno64:1
>  
> @@ -889,6 +892,7 @@ enum operand_class
>    RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
>    RegMask, /* Vector Mask register */
>    RegBND, /* Bound register */
> +  RegBS, /* Block scale register */

I think RegBSR would be a better name here.

> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -62,6 +62,8 @@
>  
>  #define RegBND Class=RegBND
>  
> +#define RegBS Class=RegBS
> +
>  #define Mmword Qword
>  #define Oword  Xmmword
>  
> @@ -118,6 +120,7 @@
>  #define SpaceXOP0A OpcodeSpace=SPACE_XOP0A
>  
>  #define EVexMap4 OpcodeSpace=SPACE_MAP4|EVex128
> +#define EVexMap6 OpcodeSpace=SPACE_MAP6

Why, when this isn't any different from ...

>  #define Map5 OpcodeSpace=SPACE_MAP5
>  #define Map6 OpcodeSpace=SPACE_MAP6

... this?

> @@ -3288,22 +3297,51 @@ tdpbhf8ps, 0xf2fd, AMX_FP8, Modrm|Vex128|Map5|Src2VVVV|VexW0|NoSuf, { RegTMM, Re
>  tdphbf8ps, 0xf3fd, AMX_FP8, Modrm|Vex128|Map5|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
>  tdphf8ps, 0x66fd, AMX_FP8, Modrm|Vex128|Map5|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM, RegTMM }
>  
> -tcvtrowd2ps, 0xf34a, AMX_AVX512, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
> -tcvtrowd2ps, 0xf307, AMX_AVX512, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
> +tcvtrowd2ps, 0xf34a, AMX_AVX512|ACE, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
> +tcvtrowd2ps, 0xf307, AMX_AVX512|ACE, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
> +
> +tcvtrowps2bf16h, 0xf26d, AMX_AVX512|ACE, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
> +tcvtrowps2bf16h, 0xf207, AMX_AVX512|ACE, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
> +tcvtrowps2bf16l, 0xf36d, AMX_AVX512|ACE, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
> +tcvtrowps2bf16l, 0xf377, AMX_AVX512|ACE, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
> +tcvtrowps2phh, 0x6d, AMX_AVX512|ACE, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
> +tcvtrowps2phh, 0x07, AMX_AVX512|ACE, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
> +tcvtrowps2phl, 0x666d, AMX_AVX512|ACE, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
> +tcvtrowps2phl, 0xf277, AMX_AVX512|ACE, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
> +
> +tilemovrow, 0x664a, AMX_AVX512|ACE, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
> +tilemovrow, 0x6607, AMX_AVX512|ACE, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
> +
> +// AMX & ACE instructions end.
> +
> +// ACE instructions.
> +
> +bsrinit, 0xf249, ACE, Modrm|Vex128|Space0F38|VexW1|NoSuf, { RegBS }
> +bsrmovf, 0x95, ACE, Modrm|EVex512|EVexMap6|VexW1|Src1VVVV|NoSuf, { RegZMM|Unspecified|BaseIndex, RegZMM, RegBS }
> +bsrmovh, 0xf295, ACE, Modrm|EVex512|EVexMap6|VexW1|NoSuf, { RegZMM|Unspecified|BaseIndex, RegBS }
> +bsrmovh, 0xf295, ACE, RegMem|Modrm|EVex512|EVexMap6|VexW0|NoSuf, { RegBS, RegZMM|Unspecified|BaseIndex }
> +bsrmovl, 0xf395, ACE, Modrm|EVex512|EVexMap6|VexW1|NoSuf, { RegZMM|Unspecified|BaseIndex, RegBS }
> +bsrmovl, 0xf395, ACE, RegMem|Modrm|EVex512|EVexMap6|VexW0|NoSuf, { RegBS, RegZMM|Unspecified|BaseIndex }

These two pairs may want to use D, just like the FMA4 and XOP insns do (where
VEX.W has a similar purpose as EVEX.W here).

> +tilemovcol, 0x662f, ACE, Modrm|EVex512|Space0F3A|VexW1|NoSuf, { Imm8, RegZMM, RegTMM }
> +tilemovcol, 0x664b, ACE, Modrm|EVex512|Space0F38|VexW1|Src2VVVV|NoSuf, { Reg32, RegZMM, RegTMM }
> +tilemovrow, 0x6607, ACE, Modrm|EVex512|Space0F3A|VexW1|NoSuf, { Imm8, RegZMM, RegTMM }
> +tilemovrow, 0x664a, ACE, Modrm|EVex512|Space0F38|VexW1|Src2VVVV|NoSuf, { Reg32, RegZMM, RegTMM }
> +
> +top2bf16ps, 0xf35c, ACE, Modrm|EVex512|Space0F38|VexW0|Src2VVVV|NoSuf, { RegZMM, RegZMM, RegTMM }
>  
> -tcvtrowps2bf16h, 0xf26d, AMX_AVX512, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
> -tcvtrowps2bf16h, 0xf207, AMX_AVX512, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
> -tcvtrowps2bf16l, 0xf36d, AMX_AVX512, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
> -tcvtrowps2bf16l, 0xf377, AMX_AVX512, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
> -tcvtrowps2phh, 0x6d, AMX_AVX512, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
> -tcvtrowps2phh, 0x07, AMX_AVX512, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
> -tcvtrowps2phl, 0x666d, AMX_AVX512, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
> -tcvtrowps2phl, 0xf277, AMX_AVX512, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
> +top4bssd, 0xf25e, ACE, Modrm|EVex512|Space0F38|VexW0|Src2VVVV|NoSuf, { RegZMM, RegZMM, RegTMM }
> +top4bsud, 0xf35e, ACE, Modrm|EVex512|Space0F38|VexW0|Src2VVVV|NoSuf, { RegZMM, RegZMM, RegTMM }
> +top4busd, 0x665e, ACE, Modrm|EVex512|Space0F38|VexW0|Src2VVVV|NoSuf, { RegZMM, RegZMM, RegTMM }
> +top4buud, 0x5e, ACE, Modrm|EVex512|Space0F38|VexW0|Src2VVVV|NoSuf, { RegZMM, RegZMM, RegTMM }

Along the lines of the existing <dpb> for AVX-VNNI-INT, the tile dot product
insns will want templatizing, for that template then to be re-use here.

> -tilemovrow, 0x664a, AMX_AVX512, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
> -tilemovrow, 0x6607, AMX_AVX512, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
> +top4mxbf8ps, 0x8d, ACE, Modrm|EVex512|Space0F3A|VexW0|Src2VVVV|NoSuf, { Imm8, RegZMM, RegZMM, RegTMM }
> +top4mxbhf8ps, 0xf28d, ACE, Modrm|EVex512|Space0F3A|VexW0|Src2VVVV|NoSuf, { Imm8, RegZMM, RegZMM, RegTMM }
> +top4mxhbf8ps, 0xf38d, ACE, Modrm|EVex512|Space0F3A|VexW0|Src2VVVV|NoSuf, { Imm8, RegZMM, RegZMM, RegTMM }
> +top4mxhf8ps, 0x668d, ACE, Modrm|EVex512|Space0F3A|VexW0|Src2VVVV|NoSuf, { Imm8, RegZMM, RegZMM, RegTMM }
> +top4mxbssps, 0xf28f, ACE, Modrm|EVex512|Space0F3A|VexW0|Src2VVVV|NoSuf, { Imm8, RegZMM, RegZMM, RegTMM }
>  
> -// AMX instructions end.
> +// ACE instructions end.

Overall: Might be nice to split things - 1st patch to re-use pre-existing insns,
2nd one to add new ones.

> --- a/opcodes/i386-reg.tbl
> +++ b/opcodes/i386-reg.tbl
> @@ -344,7 +344,7 @@ zmm28, Class=RegSIMD|Zmmword, RegVRex|RegRex, 4, Dw2Inval, 79
>  zmm29, Class=RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval, 80
>  zmm30, Class=RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, 81
>  zmm31, Class=RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, 82
> -// TMM registers for AMX
> +// TMM registers for AMX/ACE
>  tmm0, Class=RegSIMD|Tmmword, 0, 0, Dw2Inval, Dw2Inval
>  tmm1, Class=RegSIMD|Tmmword, 0, 1, Dw2Inval, Dw2Inval
>  tmm2, Class=RegSIMD|Tmmword, 0, 2, Dw2Inval, Dw2Inval
> @@ -353,6 +353,8 @@ tmm4, Class=RegSIMD|Tmmword, 0, 4, Dw2Inval, Dw2Inval
>  tmm5, Class=RegSIMD|Tmmword, 0, 5, Dw2Inval, Dw2Inval
>  tmm6, Class=RegSIMD|Tmmword, 0, 6, Dw2Inval, Dw2Inval
>  tmm7, Class=RegSIMD|Tmmword, 0, 7, Dw2Inval, Dw2Inval
> +// Block scale register for ACE
> +bsr0, Class=RegBS, 0, 0, Dw2Inval, Dw2Inval

Again a new register without the ability to represent it in Dwarf / EH-frame?

Jan

From jbeulich@suse.com  Mon Jun 29 09:59:35 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Mon, 29 Jun 2026 11:59:35 +0200
Subject: [PATCH] Remove 32-bit-only Solaris configurations
In-Reply-To: <yddik71d7q7.fsf@CeBiTec.Uni-Bielefeld.DE>
References: <yddik71d7q7.fsf@CeBiTec.Uni-Bielefeld.DE>
Message-ID: <eb79c27b-31e1-4cf3-af0b-0b3d9ca597e0@suse.com>

On 29.06.2026 11:19, Rainer Orth wrote:
> After the removal of all Solaris configurations but Solaris 10/11
> (*-*-solaris2.1[01]), the 32-bit-only configurations can no longer be
> matched.  This patch removes them.
> 
> Tested on {amd64,i386}-pc-solaris2.11 and sparc{v9,}-sun-solaris2.11.
> 
> Ok for trunk.

Assuming this was a question: Yes.

Jan

From jbeulich@suse.com  Mon Jun 29 10:00:52 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Mon, 29 Jun 2026 12:00:52 +0200
Subject: [PATCH] bfd: Always use CP_ACP=1 on Solaris [PR11280]
In-Reply-To: <yddechpd7ez.fsf@CeBiTec.Uni-Bielefeld.DE>
References: <yddechpd7ez.fsf@CeBiTec.Uni-Bielefeld.DE>
Message-ID: <f2a17539-9117-4922-b3d6-1ab4fe49b637@suse.com>

On 29.06.2026 11:26, Rainer Orth wrote:
> bfd/configure.host defines CP_ACP=1 on Solaris 11 as a workaround for
> the lack the MS-ANSI codepage in Solaris libc iconv(3C).  However, the
> issue isn't restricted to some OpenSolaris build as the comment
> suggests, but present on Solaris in general as can be seen in the iconv -l
> output:
> 
> On both Solaris 10 and 11.4, one gets
> 
> 	CP1252 (1252, ANSI-1252, WINDOWS-1252),
> 
> unlike GNU iconv which lists
> 
> 	CP1252 MS-ANSI WINDOWS-1252
> 
> Therefore, this patch applies the patch on all Solaris versions.
> 
> Tested on {amd64,i386}-pc-solaris2.11 and sparc{v9,}-sun-solaris2.11.
> 
> Ok for trunk?

Yes.

Jan

From Richard.Earnshaw@arm.com  Mon Jun 29 10:44:24 2026
From: Richard.Earnshaw@arm.com (Richard Earnshaw (foss))
Date: Mon, 29 Jun 2026 11:44:24 +0100
Subject: [PATCH v2 2/3] aarch64: warn if the TME feature is used during
 assembly.
In-Reply-To: <15d29e84-0c9b-c2d6-bb8c-feef3be9aa0c@e124511.cambridge.arm.com>
References: <20260626133516.1904430-1-rearnsha@arm.com>
 <20260626133516.1904430-3-rearnsha@arm.com>
 <15d29e84-0c9b-c2d6-bb8c-feef3be9aa0c@e124511.cambridge.arm.com>
Message-ID: <f4d8136e-9e67-4f2f-86c9-6572d842f92a@arm.com>

On 26/06/2026 16:54, Alice Carlotti wrote:
> On Fri, Jun 26, 2026 at 02:35:15PM +0100, Richard Earnshaw wrote:
>> Arm has obsoleted the unimplemented TME feature.  Warn if instructions
>> from this feature are encountered.
> 
> We could only use these instruction in assembly if we specify the +tme
> extension, and if we're deprecating the instructions then we should deprecate
> the flag as well.  So I think it would be better to emit the deprecation
> warning when parsing the "+tme" extension (and we need only warn about this
> once).
> 

I did ponder that approach, but the downside is that it will report problems on Makefiles rather than problems in source code that might be using the feature.  That makes it more difficult to focus on files that would need cleaning up as a result of this change (not that I expect there to be many cases).

The +tme option on the command line is harmless unless code is using such instructions.

R.

> Alice
> 
>>
>> Also tweak warn_unpredictable_ldst to use const more often, since the
>> arguments are the same as for the new warn_deprecated function.
>> ---
>>  gas/NEWS                             |  4 ++++
>>  gas/config/tc-aarch64.c              | 24 ++++++++++++++++++++++--
>>  gas/testsuite/gas/aarch64/tme-warn.l | 15 +++++++++++++++
>>  gas/testsuite/gas/aarch64/tme.d      |  1 +
>>  include/opcode/aarch64.h             |  6 ++++--
>>  opcodes/aarch64-tbl.h                | 10 +++++-----
>>  6 files changed, 51 insertions(+), 9 deletions(-)
>>  create mode 100644 gas/testsuite/gas/aarch64/tme-warn.l
>>
>> diff --git a/gas/NEWS b/gas/NEWS
>> index 4c55a544f25..116d5e62be6 100644
>> --- a/gas/NEWS
>> +++ b/gas/NEWS
>> @@ -1,5 +1,9 @@
>>  -*- text -*-
>>  
>> +* The aarch64 TME extension has never been implemented in any products.  Arm
>> +  has withdrawn it from the architecture.  The assembler will now warn if
>> +  instructions from the extension are detected during assembly.
>> +
>>  * The legacy .vtable_entry and .vtable_inherit directives that were
>>    needed for versions of GCC prior to gcc-3.0 (when the generic C++
>>    ABI was adopted) are now considered obsolete.  They are now deprecated
>> diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
>> index 9632a5b2a01..587c3588b09 100644
>> --- a/gas/config/tc-aarch64.c
>> +++ b/gas/config/tc-aarch64.c
>> @@ -8743,9 +8743,9 @@ programmer_friendly_fixup (aarch64_instruction *instr)
>>  /* Check for loads and stores that will cause unpredictable behavior.  */
>>  
>>  static void
>> -warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
>> +warn_unpredictable_ldst (const aarch64_instruction *instr, const char *str)
>>  {
>> -  aarch64_inst *base = &instr->base;
>> +  const aarch64_inst *base = &instr->base;
>>    const aarch64_opcode *opcode = base->opcode;
>>    const aarch64_opnd_info *opnds = base->operands;
>>    switch (opcode->iclass)
>> @@ -8841,6 +8841,25 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
>>      }
>>  }
>>  
>> +static void
>> +warn_deprecated (const aarch64_instruction *instr, const char *str)
>> +{
>> +  const aarch64_inst *base = &instr->base;
>> +  const aarch64_opcode *opcode = base->opcode;
>> +  if (!(opcode->flags & F_DEPRECATED_INSN))
>> +    return;
>> +  switch (opcode->iclass)
>> +    {
>> +    case tme:
>> +      as_warn (_("the TME feature has been deprecated -- `%s'"), str);
>> +      break;
>> +    default:
>> +      /* Instruction marked as deprecated, but a suitable warning not
>> +	 added above.  */
>> +      abort();
>> +    }
>> +}
>> +
>>  static void
>>  force_automatic_sequence_close (void)
>>  {
>> @@ -9019,6 +9038,7 @@ md_assemble (char *str)
>>  	    }
>>  
>>  	  warn_unpredictable_ldst (&inst, str);
>> +	  warn_deprecated (&inst, str);
>>  
>>  	  if (inst.reloc.type == BFD_RELOC_UNUSED
>>  	      || !inst.reloc.need_libopcodes_p)
>> diff --git a/gas/testsuite/gas/aarch64/tme-warn.l b/gas/testsuite/gas/aarch64/tme-warn.l
>> new file mode 100644
>> index 00000000000..ed26e4ed95c
>> --- /dev/null
>> +++ b/gas/testsuite/gas/aarch64/tme-warn.l
>> @@ -0,0 +1,15 @@
>> +[^:]*: Assembler messages:
>> +.*: Warning: the TME feature has been deprecated -- `tstart x0'
>> +.*: Warning: the TME feature has been deprecated -- `tstart X0'
>> +.*: Warning: the TME feature has been deprecated -- `tstart x15'
>> +.*: Warning: the TME feature has been deprecated -- `tstart X15'
>> +.*: Warning: the TME feature has been deprecated -- `tstart x30'
>> +.*: Warning: the TME feature has been deprecated -- `tstart X30'
>> +.*: Warning: the TME feature has been deprecated -- `tcommit'
>> +.*: Warning: the TME feature has been deprecated -- `tcommit'
>> +.*: Warning: the TME feature has been deprecated -- `ttest x0'
>> +.*: Warning: the TME feature has been deprecated -- `ttest X30'
>> +.*: Warning: the TME feature has been deprecated -- `tcancel 0'
>> +.*: Warning: the TME feature has been deprecated -- `tcancel 65535'
>> +.*: Warning: the TME feature has been deprecated -- `tcancel 0xffff'
>> +.*: Warning: the TME feature has been deprecated -- `tcancel 0XA'
>> diff --git a/gas/testsuite/gas/aarch64/tme.d b/gas/testsuite/gas/aarch64/tme.d
>> index 24d34ea9561..66527b03921 100644
>> --- a/gas/testsuite/gas/aarch64/tme.d
>> +++ b/gas/testsuite/gas/aarch64/tme.d
>> @@ -1,4 +1,5 @@
>>  #as: -march=armv8-a+tme
>> +#warning_output: tme-warn.l
>>  #objdump: -dr
>>  
>>  .* file format .*
>> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
>> index f51045210c9..2d8514b8e7d 100644
>> --- a/include/opcode/aarch64.h
>> +++ b/include/opcode/aarch64.h
>> @@ -1219,6 +1219,7 @@ enum aarch64_insn_class
>>    sve_shift_tsz_bhsd,
>>    sve_size_tsz_bhs,
>>    testbranch,
>> +  tme,
>>    cryptosm3,
>>    cryptosm4,
>>    dotproduct,
>> @@ -1479,7 +1480,8 @@ extern const aarch64_opcode aarch64_opcode_table[];
>>  #define F_OD(X) (((X) & 0x7) << 24)
>>  /* Instruction has the field of 'sz'.  */
>>  #define F_LSE_SZ (1 << 27)
>> -
>> +/* The instruction has been deprecated.  */
>> +#define F_DEPRECATED_INSN (1 << 28)
>>  
>>  #define F_SYS_READ (1ULL << 29)
>>  /* This system instruction is used to write system registers.  */
>> @@ -1542,7 +1544,7 @@ extern const aarch64_opcode aarch64_opcode_table[];
>>  /* As above, plus PN registers.  */
>>  #define F_INVALID_IMM_SYMS_3 (3ULL << 42)
>>  
>> -/* Next bit is 44, and 28 is also unused.  */
>> +/* Next bit is 44.  */
>>  
>>  /* Instruction constraints.  */
>>  /* This instruction has a predication constraint on the instruction at PC+4.  */
>> diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
>> index 518109ecfd6..c6cb5257008 100644
>> --- a/opcodes/aarch64-tbl.h
>> +++ b/opcodes/aarch64-tbl.h
>> @@ -3374,7 +3374,7 @@ static const aarch64_feature_set aarch64_feature_mpamv2 =
>>  #define MEMTAG_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
>>    { NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
>>  #define _TME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
>> -  { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
>> +  { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1 | F_DEPRECATED_INSN, 0, 0, NULL }
>>  #define SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
>>    { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
>>      FLAGS | F_INVALID_IMM_SYMS_2, 0, TIED, NULL }
>> @@ -5154,10 +5154,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =
>>    CORE_INSN ("adr",  0x10000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_PCREL21), QL_ADRP, 0),
>>    CORE_INSN ("adrp", 0x90000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_ADRP), QL_ADRP, 0),
>>    /* TME Instructions.  */
>> -  _TME_INSN ("tstart", 0xd5233060, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
>> -  _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, 0, 0, OP0 (), QL_0, 0),
>> -  _TME_INSN ("ttest", 0xd5233160, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
>> -  _TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, 0, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0),
>> +  _TME_INSN ("tstart", 0xd5233060, 0xffffffe0, tme, 0, OP1 (Rd), QL_I1X, 0),
>> +  _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, tme, 0, OP0 (), QL_0, 0),
>> +  _TME_INSN ("ttest", 0xd5233160, 0xffffffe0, tme, 0, OP1 (Rd), QL_I1X, 0),
>> +  _TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, tme, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0),
>>    /* SME instructions (aliases for MSR <sysreg> operations.  */
>>    SME_INSN ("smstart", 0xd503477f, 0xffffffff, sme_start, 0, OP0 (), QL_0, F_SYS_WRITE, 0),
>>    SME_INSN ("smstop",  0xd503467f, 0xffffffff, sme_stop,  0, OP0 (), QL_0, F_SYS_WRITE, 0),
>> -- 
>> 2.43.0
>>


From Richard.Earnshaw@arm.com  Mon Jun 29 10:45:43 2026
From: Richard.Earnshaw@arm.com (Richard Earnshaw (foss))
Date: Mon, 29 Jun 2026 11:45:43 +0100
Subject: [PATCH v2 1/3] aarch64: Remove a stray comment from
 opcode/aarch64.h
In-Reply-To: <0f58bb35-352f-99bd-5dad-0ab24510a16b@e124511.cambridge.arm.com>
References: <20260626133516.1904430-1-rearnsha@arm.com>
 <20260626133516.1904430-2-rearnsha@arm.com>
 <0f58bb35-352f-99bd-5dad-0ab24510a16b@e124511.cambridge.arm.com>
Message-ID: <6017f3bc-deb6-48fd-bbed-a8cceb83e13c@arm.com>

On 26/06/2026 16:41, Alice Carlotti wrote:
> On Fri, Jun 26, 2026 at 02:35:14PM +0100, Richard Earnshaw wrote:
>> When flag bit 28 was removed in an earlier patch, the comment describing
>> it was left behind.  This just cleans that up.
>> ---
>>  include/opcode/aarch64.h | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
>> index 6d1b414444a..f51045210c9 100644
>> --- a/include/opcode/aarch64.h
>> +++ b/include/opcode/aarch64.h
>> @@ -1479,7 +1479,7 @@ extern const aarch64_opcode aarch64_opcode_table[];
>>  #define F_OD(X) (((X) & 0x7) << 24)
>>  /* Instruction has the field of 'sz'.  */
>>  #define F_LSE_SZ (1 << 27)
>> -/* Require an exact qualifier match, even for NIL qualifiers.  */
>> +
>>  
>>  #define F_SYS_READ (1ULL << 29)
>>  /* This system instruction is used to write system registers.  */
>> -- 
>> 2.43.0
>>
> 
> The extra blank line looks unnecessary to me, but you'll be touching this again
> in the next patch anyway.  Ignoring that nit, this patch is obviously ok -
> thanks for fixing my earlier mistake.
> 
> Alice

I assumed it was deliberate to make it clear that there was a gap in the number system.  The gap gets closed in the next patch though...

R.

From jbeulich@suse.com  Mon Jun 29 10:54:13 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Mon, 29 Jun 2026 12:54:13 +0200
Subject: [PATCH v2] PE/COFF: auto-promote oversized objects to bigobj
In-Reply-To: <20260623213900.2000-2-oleg.tolmatcev@gmail.com>
References: <20260623213900.2000-2-oleg.tolmatcev@gmail.com>
Message-ID: <9b88c57f-0bf6-49f2-9324-88cc8f2cc86e@suse.com>

On 23.06.2026 23:39, Oleg Tolmatcev wrote:
> --- a/gas/testsuite/gas/pe/pe.exp
> +++ b/gas/testsuite/gas/pe/pe.exp
> @@ -68,6 +68,8 @@ if {[istarget "aarch64-*-pe*"] || [istarget "aarch64-*-mingw*"]} {
>  # Big obj
>  
>  
> -if ([istarget "*-*-mingw*"]) then {
> +if { [istarget "aarch64-*-*"] || [istarget "i*86-*-*"]
> +    || [istarget "x86_64-*-*"] } then {

This went too far: bfd/config.bfd confirms me observing both tests to fail on
i?86-interix, and it further suggests i?86-beospe* to also be affected. Or wait,
*-*-beos* is covered by the "target removed" switch higher up in the file, so
the individual entries later are all stale. I'll prune that, but for committing
this patch I'll also need to exclude *-*-interix* above.

Jan

>  	run_dump_test "big-obj"
> +	run_dump_test "big-obj-auto"
>  }


From jbeulich@suse.com  Mon Jun 29 14:12:08 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Mon, 29 Jun 2026 16:12:08 +0200
Subject: [PATCH] prune BeOS leftovers
Message-ID: <4c0063d4-1c2d-4257-ae91-4d8c19303cb7@suse.com>

The target was marked removed by bd3828b0de50 ("Remove support for the
beos file format") in early 2024. Drop leftover entries.
---
Purely because of a contextual conflict this is assumed to go on top of
"gas: ignore ONLY_STANDARD_ESCAPES in scrubber" sent previously.

--- a/bfd/config.bfd
+++ b/bfd/config.bfd
@@ -615,14 +615,6 @@ case "${targ}" in
     targ_defvec=i386_elf32_vec
     targ_selvecs="i386_msdos_vec i386_aout_vec"
     ;;
-  i[3-7]86-*-beospe*)
-    targ_defvec=i386_pe_vec
-    targ_selvecs="i386_pe_vec i386_pei_vec"
-    ;;
-  i[3-7]86-*-beos*)
-    targ_defvec=i386_elf32_vec
-    targ_selvecs="i386_pe_vec i386_pei_vec"
-    ;;
   i[3-7]86-*-haiku*)
     targ_defvec=i386_elf32_vec
     targ_selvecs="i386_pei_vec"
@@ -1008,7 +1000,7 @@ case "${targ}" in
     ;;
 #endif
 
-  powerpc-*-aix* | powerpc-*-beos* | rs6000-*-*)
+  powerpc-*-aix* | rs6000-*-*)
     targ_defvec=rs6000_xcoff_vec
     targ64_selvecs=rs6000_xcoff64_vec
     case "${targ}" in
--- a/bfd/configure
+++ b/bfd/configure
@@ -16400,7 +16400,6 @@ rm -f core conftest.err conftest.$ac_obj
   powerpc64-*-aix*)	COREFILE=rs6000-core.lo ;;
   powerpc-*-aix4*)	COREFILE=rs6000-core.lo ;;
   powerpc-*-aix*)	COREFILE=rs6000-core.lo ;;
-  powerpc-*-beos*)	;;
   powerpc-*-freebsd* | powerpc-*-kfreebsd*-gnu)
 		        COREFILE='' ;;
   powerpc-*-netbsd*)	COREFILE=netbsd-core.lo ;;
--- a/bfd/configure.ac
+++ b/bfd/configure.ac
@@ -926,7 +926,6 @@ changequote([,])dnl
   powerpc64-*-aix*)	COREFILE=rs6000-core.lo ;;
   powerpc-*-aix4*)	COREFILE=rs6000-core.lo ;;
   powerpc-*-aix*)	COREFILE=rs6000-core.lo ;;
-  powerpc-*-beos*)	;;
   powerpc-*-freebsd* | powerpc-*-kfreebsd*-gnu)
 		        COREFILE='' ;;
   powerpc-*-netbsd*)	COREFILE=netbsd-core.lo ;;
--- a/binutils/testsuite/binutils-all/nm.exp
+++ b/binutils/testsuite/binutils-all/nm.exp
@@ -147,7 +147,6 @@ if {![binutils_assemble $srcdir/$subdir/
 # all the ELF variants, but adding the patterns here to that proc then
 # introduces a whole slew of new regressions in the GAS and LD testsuites.
 if {   [is_elf_format]
-    || [istarget *-*-beos]
     || [istarget *-*-dragonfly*]
     || [istarget *-*-*elf]
     || [istarget *-*-freebsd*]
--- a/binutils/testsuite/lib/binutils-common.exp
+++ b/binutils/testsuite/lib/binutils-common.exp
@@ -53,15 +53,10 @@ proc is_elf_format {} {
 	 && ![istarget *-*-wasm32*]
 	 && ![istarget avr-*-*]
 	 && ![istarget hppa*64*-*-hpux*]
-	 && ![istarget i?86-*-beos*]
 	 && ![istarget ia64-*-hpux*] } {
 	return 0
     }
 
-    if { [istarget i?86-*-beospe*] } {
-	return 0
-    }
-
     if { [istarget *-*-linux*ecoff*] } {
 	return 0
     }
@@ -100,8 +95,7 @@ proc is_pecoff_format args {
     } else {
 	set m_os *-*
     }
-    if { [istarget $m_os-beospe*]
-	 || [istarget $m_os-cegcc*]
+    if { [istarget $m_os-cegcc*]
 	 || [istarget $m_os-cygwin*]
 	 || [istarget $m_os-interix*]
 	 || [istarget $m_os-mingw*]
@@ -143,7 +137,6 @@ proc is_som_format {} {
 proc is_xcoff_format {} {
     if { [istarget rs6000-*-*]
 	 || [istarget powerpc*-*-aix*]
-	 || [istarget powerpc*-*-beos*]
 	 || [istarget powerpc*-*-macos*] } {
 	return 1;
     }
--- a/gas/configure.tgt
+++ b/gas/configure.tgt
@@ -225,8 +225,6 @@ case ${generic_target} in
   h8300-*-elf)				fmt=elf ;;
   h8300-*-linux*)			fmt=elf em=linux ;;
 
-  i386-*-beospe*)			fmt=coff em=pe ;;
-  i386-*-beos*)				fmt=elf ;;
   i386-*-elfiamcu)			fmt=elf arch=iamcu ;;
   i386-*-elf*)				fmt=elf ;;
   i386-*-fuchsia*)			fmt=elf ;;
@@ -361,7 +359,6 @@ case ${generic_target} in
   ppc-*-aix5.[01])			fmt=coff em=aix5 ;;
   ppc-*-aix[5-9].*)			fmt=coff em=aix5 ;;
   ppc-*-aix*)				fmt=coff em=aix ;;
-  ppc-*-beos*)				fmt=coff ;;
   ppc-*-*n*bsd* | ppc-*-elf*)		fmt=elf ;;
   ppc-*-eabi* | ppc-*-sysv4*)		fmt=elf ;;
   ppc-*-haiku*)				fmt=elf em=haiku ;;
--- a/gas/testsuite/gas/all/quoted-label-blank.d
+++ b/gas/testsuite/gas/all/quoted-label-blank.d
@@ -1,7 +1,7 @@
 #nm: --extern-only --numeric-sort
 #name: quoted label name followed by whitespace
 # No quoted strings handling (TC_STRING_ESCAPES set to 0):
-#notarget: powerpc*-*-aix* powerpc*-*-beos* powerpc-*-macos* rs6000-*-*
+#notarget: powerpc*-*-aix* powerpc-*-macos* rs6000-*-*
 # Certain LABELS_WITHOUT_COLONS targets:
 #notarget: mmix-*-* tic54*-*-* z80-*-*
 
--- a/gas/testsuite/gas/all/quoted-sym-names.d
+++ b/gas/testsuite/gas/all/quoted-sym-names.d
@@ -1,7 +1,7 @@
 #nm: --extern-only --numeric-sort
 #name: quoted symbol names
 # No quoted strings handling (TC_STRING_ESCAPES set to 0):
-#notarget: powerpc*-*-aix* powerpc*-*-beos* powerpc-*-macos* rs6000-*-*
+#notarget: powerpc*-*-aix* powerpc-*-macos* rs6000-*-*
 # Explicitly no escapes in quoted strings:
 #notarget: z80-*-*
 
--- a/gas/testsuite/gas/i386/x86-64.exp
+++ b/gas/testsuite/gas/i386/x86-64.exp
@@ -689,7 +689,6 @@ run_dump_test "x86-64-amx-intel"
 run_dump_test "x86-64-amx-bad"
 
 if { ![istarget "*-*-aix*"]
-     && ![istarget "*-*-beos*"]
      && ![istarget "*-*-*bsd*"]
      && ![istarget "*-*-lynx*"]
      && ![istarget "*-*-moss*"]
--- a/gas/testsuite/gas/macros/macros.exp
+++ b/gas/testsuite/gas/macros/macros.exp
@@ -54,7 +54,7 @@ switch -glob $target_triplet {
 
 if { ![istarget hppa*-*-*] || [istarget *-*-linux*] } {
     # These fail due to !TC_STRING_ESCAPES
-    setup_xfail "powerpc*-*-aix*" "powerpc*-*-beos*" "powerpc*-*-macos*"
+    setup_xfail "powerpc*-*-aix*" "powerpc*-*-macos*"
     setup_xfail "rs6000-*-*"
 
     # FIXME: Due to difference in what "consecutive octets" means.
--- a/include/coff/internal.h
+++ b/include/coff/internal.h
@@ -159,10 +159,6 @@ typedef struct _CODEVIEW_INFO
 #define NT_EXE_IMAGE_BASE 0x400000
 #define NT_DLL_IMAGE_BASE 0x10000000
 
-/* Default image base for BeOS. */
-#define BEOS_EXE_IMAGE_BASE 0x80000000
-#define BEOS_DLL_IMAGE_BASE 0x10000000
-
 /* Extra stuff in a PE aouthdr */
 
 #define PE_DEF_SECTION_ALIGNMENT 0x1000
--- a/ld/Makefile.am
+++ b/ld/Makefile.am
@@ -299,7 +299,6 @@ ALL_EMULATION_SOURCES = \
 	ehppanbsd.c \
 	ehppaobsd.c \
 	ei386aout.c \
-	ei386beos.c \
 	ei386bsd.c \
 	ei386go32.c \
 	ei386lynx.c \
--- a/ld/Makefile.in
+++ b/ld/Makefile.in
@@ -814,7 +814,6 @@ ALL_EMULATION_SOURCES = \
 	ehppanbsd.c \
 	ehppaobsd.c \
 	ei386aout.c \
-	ei386beos.c \
 	ei386bsd.c \
 	ei386go32.c \
 	ei386lynx.c \
@@ -1496,7 +1495,6 @@ distclean-compile:
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ehppanbsd.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ehppaobsd.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ei386aout.Po@am__quote@
-@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ei386beos.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ei386bsd.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ei386go32.Po@am__quote@
 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ei386lynx.Po@am__quote@
--- a/ld/configure.tgt
+++ b/ld/configure.tgt
@@ -414,11 +414,6 @@ i[3-7]86-*-mingw32*)	targ_emul=i386pe ;
 i[3-7]86-*-interix*)	targ_emul=i386pe_posix;
 			targ_extra_ofiles="deffilep.o pe-dll.o"
 			;;
-i[3-7]86-*-beospe*)	targ_emul=i386beos
-			targ_extra_ofiles=
-			;;
-i[3-7]86-*-beos*)	targ_emul=elf_i386_be
-			;;
 i[3-7]86-*-haiku*)	targ_emul=elf_i386_haiku
 			;;
 i[3-7]86-*-vxworks*)	targ_emul=elf_i386_vxworks
@@ -758,9 +753,6 @@ powerpc-*-aix[5-9]*)	targ_emul=aix5ppc
 powerpc-*-aix*)		targ_emul=aixppc
 			targ_extra_ofiles=
 			;;
-powerpc-*-beos*)	targ_emul=aixppc
-			targ_extra_ofiles=
-			;;
 powerpc-*-haiku*)	targ_emul=elf32ppchaiku
 			;;
 powerpc-*-windiss*)	targ_emul=elf32ppcwindiss
--- a/ld/emulparams/i386beos.sh
+++ /dev/null
@@ -1,5 +0,0 @@
-ARCH=i386
-SCRIPT_NAME=i386beos
-OUTPUT_FORMAT="pei-i386"
-RELOCATEABLE_OUTPUT_FORMAT="pe-i386"
-TEMPLATE_NAME=beos
--- a/ld/emultempl/beos.em
+++ /dev/null
@@ -1,746 +0,0 @@
-# This shell script emits a C file. -*- C -*-
-# It does some substitutions.
-if [ -z "$MACHINE" ]; then
-  OUTPUT_ARCH=${ARCH}
-else
-  OUTPUT_ARCH=${ARCH}:${MACHINE}
-fi
-fragment <<EOF
-/* This file is part of GLD, the Gnu Linker.
-   Copyright (C) 1995-2026 Free Software Foundation, Inc.
-
-   This file is part of the GNU Binutils.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 3 of the License, or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
-   MA 02110-1301, USA.  */
-
-
-/* For WINDOWS_NT */
-/* The original file generated returned different default scripts depending
-   on whether certain switches were set, but these switches pertain to the
-   Linux system and that particular version of coff.  In the NT case, we
-   only determine if the subsystem is console or windows in order to select
-   the correct entry point by default. */
-
-#include "sysdep.h"
-#include "bfd.h"
-#include "bfdlink.h"
-#include "ctf-api.h"
-#include "getopt.h"
-#include "libiberty.h"
-#include "filenames.h"
-#include "ld.h"
-#include "ldmain.h"
-#include "ldexp.h"
-#include "ldlang.h"
-#include "ldfile.h"
-#include "ldemul.h"
-#include <ldgram.h>
-#include "ldlex.h"
-#include "ldmisc.h"
-#include "ldctor.h"
-#include "coff/internal.h"
-#include "../bfd/libcoff.h"
-
-#define TARGET_IS_${EMULATION_NAME}
-
-static struct internal_extra_pe_aouthdr pe;
-static int dll;
-
-extern const char *output_filename;
-
-static void
-gld${EMULATION_NAME}_before_parse (void)
-{
-  ldfile_set_output_arch ("${OUTPUT_ARCH}", bfd_arch_`echo ${ARCH} | sed -e 's/:.*//'`);
-  output_filename = "a.exe";
-}
-

-/* PE format extra command line options.  */
-
-static void
-gld${EMULATION_NAME}_add_options
-  (int ns ATTRIBUTE_UNUSED, char **shortopts ATTRIBUTE_UNUSED, int nl,
-   struct option **longopts, int nrl ATTRIBUTE_UNUSED,
-   struct option **really_longopts ATTRIBUTE_UNUSED)
-{
-  static const struct option xtra_long[] = {
-    /* PE options */
-    {"base-file", required_argument, NULL, OPTION_BASE_FILE},
-    {"dll", no_argument, NULL, OPTION_DLL},
-    {"file-alignment", required_argument, NULL, OPTION_FILE_ALIGNMENT},
-    {"heap", required_argument, NULL, OPTION_HEAP},
-    {"major-image-version", required_argument, NULL, OPTION_MAJOR_IMAGE_VERSION},
-    {"major-os-version", required_argument, NULL, OPTION_MAJOR_OS_VERSION},
-    {"major-subsystem-version", required_argument, NULL, OPTION_MAJOR_SUBSYSTEM_VERSION},
-    {"minor-image-version", required_argument, NULL, OPTION_MINOR_IMAGE_VERSION},
-    {"minor-os-version", required_argument, NULL, OPTION_MINOR_OS_VERSION},
-    {"minor-subsystem-version", required_argument, NULL, OPTION_MINOR_SUBSYSTEM_VERSION},
-    {"section-alignment", required_argument, NULL, OPTION_SECTION_ALIGNMENT},
-    {"stack", required_argument, NULL, OPTION_STACK},
-    {"subsystem", required_argument, NULL, OPTION_SUBSYSTEM},
-    {NULL, no_argument, NULL, 0}
-  };
-
-  *longopts = (struct option *)
-    xrealloc (*longopts, nl * sizeof (struct option) + sizeof (xtra_long));
-  memcpy (*longopts + nl, &xtra_long, sizeof (xtra_long));
-}
-
-
-/* PE/WIN32; added routines to get the subsystem type, heap and/or stack
-   parameters which may be input from the command line */
-
-typedef struct {
-  void *ptr;
-  int size;
-  int value;
-  char *symbol;
-  int inited;
-} definfo;
-
-#define D(field,symbol,def)  {&pe.field,sizeof(pe.field), def, symbol,0}
-
-static definfo init[] =
-{
-  /* imagebase must be first */
-#define IMAGEBASEOFF 0
-  D(ImageBase,"__image_base__", BEOS_EXE_IMAGE_BASE),
-#define DLLOFF 1
-  {&dll, sizeof(dll), 0, "__dll__", 0},
-  D(SectionAlignment,"__section_alignment__", PE_DEF_SECTION_ALIGNMENT),
-  D(FileAlignment,"__file_alignment__", PE_DEF_FILE_ALIGNMENT),
-  D(MajorOperatingSystemVersion,"__major_os_version__", 4),
-  D(MinorOperatingSystemVersion,"__minor_os_version__", 0),
-  D(MajorImageVersion,"__major_image_version__", 1),
-  D(MinorImageVersion,"__minor_image_version__", 0),
-  D(MajorSubsystemVersion,"__major_subsystem_version__", 4),
-  D(MinorSubsystemVersion,"__minor_subsystem_version__", 0),
-  D(Subsystem,"__subsystem__", 3),
-  D(SizeOfStackReserve,"__size_of_stack_reserve__", 0x2000000),
-  D(SizeOfStackCommit,"__size_of_stack_commit__", 0x1000),
-  D(SizeOfHeapReserve,"__size_of_heap_reserve__", 0x100000),
-  D(SizeOfHeapCommit,"__size_of_heap_commit__", 0x1000),
-  D(LoaderFlags,"__loader_flags__", 0x0),
-  { NULL, 0, 0, NULL, 0 }
-};
-
-
-static void
-set_pe_name (char *name, long val)
-{
-  int i;
-  /* Find the name and set it. */
-  for (i = 0; init[i].ptr; i++)
-    {
-      if (strcmp (name, init[i].symbol) == 0)
-	{
-	  init[i].value = val;
-	  init[i].inited = 1;
-	  return;
-	}
-    }
-  abort();
-}
-
-
-static void
-set_pe_subsystem (void)
-{
-  const char *sver;
-  int len;
-  int i;
-  static const struct
-    {
-      const char *name;
-      const int value;
-      const char *entry;
-    }
-  v[] =
-    {
-      { "native", 1, "_NtProcessStartup" },
-      { "windows", 2, "_WinMainCRTStartup" },
-      { "wwindows", 2, "_wWinMainCRTStartup" },
-      { "console", 3, "_mainCRTStartup" },
-      { "wconsole", 3, "_wmainCRTStartup" },
-      { "posix", 7, "___PosixProcessStartup"},
-      { 0, 0, 0 }
-    };
-
-  sver = strchr (optarg, ':');
-  if (sver == NULL)
-    len = strlen (optarg);
-  else
-    {
-      char *end;
-
-      len = sver - optarg;
-      set_pe_name ("__major_subsystem_version__",
-		   strtoul (sver + 1, &end, 0));
-      if (*end == '.')
-	set_pe_name ("__minor_subsystem_version__",
-		     strtoul (end + 1, &end, 0));
-      if (*end != '\0')
-	einfo (_("%P: warning: bad version number in -subsystem option\n"));
-    }
-
-  for (i = 0; v[i].name; i++)
-    {
-      if (strncmp (optarg, v[i].name, len) == 0
-	  && v[i].name[len] == '\0')
-	{
-	  set_pe_name ("__subsystem__", v[i].value);
-
-	  /* If the subsystem is windows, we use a different entry
-	     point.  */
-	  lang_default_entry (v[i].entry);
-
-	  return;
-	}
-    }
-  fatal (_("%P: invalid subsystem type %s\n"), optarg);
-}
-
-
-static void
-set_pe_value (char *name)
-{
-  char *end;
-  set_pe_name (name,  strtoul (optarg, &end, 0));
-  if (end == optarg)
-    fatal (_("%P: invalid hex number for PE parameter '%s'\n"), optarg);
-
-  optarg = end;
-}
-
-static void
-set_pe_stack_heap (char *resname, char *comname)
-{
-  set_pe_value (resname);
-  if (*optarg == ',')
-    {
-      optarg++;
-      set_pe_value (comname);
-    }
-  else if (*optarg)
-    fatal (_("%P: strange hex info for PE parameter '%s'\n"), optarg);
-}
-
-
-static bool
-gld${EMULATION_NAME}_handle_option (int optc)
-{
-  switch (optc)
-    {
-    default:
-      return false;
-
-    case OPTION_BASE_FILE:
-      link_info.base_file = fopen (optarg, FOPEN_WB);
-      if (link_info.base_file == NULL)
-	fatal (_("%P: cannot open base file %s\n"), optarg);
-      break;
-
-      /* PE options */
-    case OPTION_HEAP:
-      set_pe_stack_heap ("__size_of_heap_reserve__", "__size_of_heap_commit__");
-      break;
-    case OPTION_STACK:
-      set_pe_stack_heap ("__size_of_stack_reserve__", "__size_of_stack_commit__");
-      break;
-    case OPTION_SUBSYSTEM:
-      set_pe_subsystem ();
-      break;
-    case OPTION_MAJOR_OS_VERSION:
-      set_pe_value ("__major_os_version__");
-      break;
-    case OPTION_MINOR_OS_VERSION:
-      set_pe_value ("__minor_os_version__");
-      break;
-    case OPTION_MAJOR_SUBSYSTEM_VERSION:
-      set_pe_value ("__major_subsystem_version__");
-      break;
-    case OPTION_MINOR_SUBSYSTEM_VERSION:
-      set_pe_value ("__minor_subsystem_version__");
-      break;
-    case OPTION_MAJOR_IMAGE_VERSION:
-      set_pe_value ("__major_image_version__");
-      break;
-    case OPTION_MINOR_IMAGE_VERSION:
-      set_pe_value ("__minor_image_version__");
-      break;
-    case OPTION_FILE_ALIGNMENT:
-      set_pe_value ("__file_alignment__");
-      break;
-    case OPTION_SECTION_ALIGNMENT:
-      set_pe_value ("__section_alignment__");
-      break;
-    case OPTION_DLL:
-      set_pe_name ("__dll__", 1);
-      break;
-    case OPTION_IMAGE_BASE:
-      set_pe_value ("__image_base__");
-      break;
-    }
-  return true;
-}
-

-/* Assign values to the special symbols before the linker script is
-   read.  */
-
-static void
-gld${EMULATION_NAME}_set_symbols (void)
-{
-  /* Run through and invent symbols for all the
-     names and insert the defaults. */
-  int j;
-
-  if (!init[IMAGEBASEOFF].inited)
-    {
-      if (bfd_link_relocatable (&link_info))
-	init[IMAGEBASEOFF].value = 0;
-      else if (init[DLLOFF].value)
-	init[IMAGEBASEOFF].value = BEOS_DLL_IMAGE_BASE;
-      else
-	init[IMAGEBASEOFF].value = BEOS_EXE_IMAGE_BASE;
-    }
-
-  /* Don't do any symbol assignments if this is a relocatable link.  */
-  if (bfd_link_relocatable (&link_info))
-    return;
-
-  /* Glue the assignments into the abs section */
-  push_stat_ptr (&abs_output_section->children);
-
-  for (j = 0; init[j].ptr; j++)
-    {
-      long val = init[j].value;
-      lang_add_assignment (exp_assign (init[j].symbol, exp_intop (val),
-				       false));
-      if (init[j].size == sizeof(short))
-	*(short *)init[j].ptr = val;
-      else if (init[j].size == sizeof(int))
-	*(int *)init[j].ptr = val;
-      else if (init[j].size == sizeof(long))
-	*(long *)init[j].ptr = val;
-      /* This might be a long long or other special type.  */
-      else if (init[j].size == sizeof(bfd_vma))
-	*(bfd_vma *)init[j].ptr = val;
-      else	abort();
-    }
-  /* Restore the pointer. */
-  pop_stat_ptr ();
-
-  if (pe.FileAlignment >
-      pe.SectionAlignment)
-    {
-      einfo (_("%P: warning, file alignment > section alignment\n"));
-    }
-}
-
-static void
-gld${EMULATION_NAME}_after_open (void)
-{
-  after_open_default ();
-
-  /* Pass the wacky PE command line options into the output bfd.
-     FIXME: This should be done via a function, rather than by
-     including an internal BFD header.  */
-  if (!obj_pe (link_info.output_bfd))
-    fatal (_("%P: PE operations on non PE file\n"));
-
-  pe_data(link_info.output_bfd)->pe_opthdr = pe;
-  pe_data(link_info.output_bfd)->dll = init[DLLOFF].value;
-
-}
-

-/* Callback functions for qsort in sort_sections. */
-
-static int
-sort_by_file_name (const void *a, const void *b)
-{
-  const lang_input_section_type *const *ra = a;
-  const lang_input_section_type *const *rb = b;
-  asection *sa = (*ra)->section;
-  asection *sb = (*rb)->section;
-  int i, a_sec, b_sec;
-
-  i = filename_cmp (bfd_get_filename (sa->owner->my_archive),
-		    bfd_get_filename (sb->owner->my_archive));
-  if (i != 0)
-    return i;
-
-  i = filename_cmp (bfd_get_filename (sa->owner),
-		    bfd_get_filename (sb->owner));
-  if (i != 0)
-    return i;
-  /* the tail idata4/5 are the only ones without relocs to an
-     idata$6 section unless we are importing by ordinal,
-     so sort them to last to terminate the IAT
-     and HNT properly. if no reloc this one is import by ordinal
-     so we have to sort by section contents */
-
-  if (sa->reloc_count + sb->reloc_count != 0)
-    {
-      i = sa->reloc_count > sb->reloc_count ? -1 : 0;
-      if (i != 0)
-	return i;
-
-      return sa->reloc_count > sb->reloc_count ? 0 : 1;
-    }
-  else
-    {
-      /* don't sort .idata$6 or .idata$7 FIXME dlltool eliminate .idata$7 */
-      if ((strcmp (sa->name, ".idata$6") == 0))
-	return 0;
-
-      if (!bfd_get_section_contents (sa->owner, sa, &a_sec, (file_ptr) 0,
-				     (bfd_size_type) sizeof (a_sec)))
-	fatal (_("%P: %pB: can't read contents of section .idata: %E\n"),
-	       sa->owner);
-
-      if (!bfd_get_section_contents (sb->owner, sb, &b_sec, (file_ptr) 0,
-				     (bfd_size_type) sizeof (b_sec)))
-	fatal (_("%P: %pB: can't read contents of section .idata: %E\n"),
-	       sb->owner);
-
-      i = a_sec < b_sec ? -1 : 0;
-      if (i != 0)
-	return i;
-      return a_sec < b_sec ? 0 : 1;
-    }
-  return 0;
-}
-
-static int
-sort_by_section_name (const void *a, const void *b)
-{
-  const lang_input_section_type *const *ra = a;
-  const lang_input_section_type *const *rb = b;
-  const char *sna = (*ra)->section->name;
-  const char *snb = (*rb)->section->name;
-  int i;
-  i = strcmp (sna, snb);
-  /* This is a hack to make .stab and .stabstr last, so we don't have
-     to fix strip/objcopy for .reloc sections.
-     FIXME stripping images with a .rsrc section still needs to be fixed.  */
-  if (i != 0)
-    {
-      if ((startswith (sna, ".stab"))
-	  && (!startswith (snb, ".stab")))
-	return 1;
-    }
-  return i;
-}
-
-/* Subroutine of sort_sections to a contiguous subset of a list of sections.
-   NEXT_AFTER is the element after the last one to sort.
-   The result is a pointer to the last element's "next" pointer.  */
-
-static lang_statement_union_type **
-sort_sections_1 (lang_statement_union_type **startptr,
-		 lang_statement_union_type *next_after,
-		 int count,
-		 int (*sort_func) (const void *, const void *))
-{
-  lang_statement_union_type **vec;
-  lang_statement_union_type *p;
-  int i;
-  lang_statement_union_type **ret;
-
-  if (count == 0)
-    return startptr;
-
-  vec = ((lang_statement_union_type **)
-	 xmalloc (count * sizeof (lang_statement_union_type *)));
-
-  for (p = *startptr, i = 0; i < count; i++, p = p->header.next)
-    vec[i] = p;
-
-  qsort (vec, count, sizeof (vec[0]), sort_func);
-
-  /* Fill in the next pointers again. */
-  *startptr = vec[0];
-  for (i = 0; i < count - 1; i++)
-    vec[i]->header.next = vec[i + 1];
-  vec[i]->header.next = next_after;
-  ret = &vec[i]->header.next;
-  free (vec);
-  return ret;
-}
-
-/* Sort the .idata\$foo input sections of archives into filename order.
-   The reason is so dlltool can arrange to have the pe dll import information
-   generated correctly - the head of the list goes into dh.o, the tail into
-   dt.o, and the guts into ds[nnnn].o.  Note that this is only needed for the
-   .idata section.
-   FIXME: This may no longer be necessary with grouped sections.  Instead of
-   sorting on dh.o, ds[nnnn].o, dt.o, one could, for example, have dh.o use
-   .idata\$4h, have ds[nnnn].o use .idata\$4s[nnnn], and have dt.o use .idata\$4t.
-   This would have to be elaborated upon to handle multiple dll's
-   [assuming such an eloboration is possible of course].
-
-   We also sort sections in '\$' wild statements.  These are created by the
-   place_orphans routine to implement grouped sections.  */
-
-static void
-sort_sections (lang_statement_union_type *s)
-{
-  for (; s ; s = s->header.next)
-    switch (s->header.type)
-      {
-      case lang_output_section_statement_enum:
-	sort_sections (s->output_section_statement.children.head);
-	break;
-      case lang_wild_statement_enum:
-	{
-	  lang_statement_union_type **p = &s->wild_statement.children.head;
-	  struct wildcard_list *sec;
-
-	  for (sec = s->wild_statement.section_list; sec; sec = sec->next)
-	    {
-	      /* Is this the .idata section?  */
-	      if (sec->spec.name != NULL
-		  && startswith (sec->spec.name, ".idata"))
-		{
-		  /* Sort the children.  We want to sort any objects in
-		     the same archive.  In order to handle the case of
-		     including a single archive multiple times, we sort
-		     all the children by archive name and then by object
-		     name.  After sorting them, we re-thread the pointer
-		     chain.  */
-
-		  while (*p)
-		    {
-		      lang_statement_union_type *start = *p;
-		      if (start->header.type != lang_input_section_enum
-			  || !start->input_section.section->owner->my_archive)
-			p = &(start->header.next);
-		      else
-			{
-			  lang_statement_union_type *end;
-			  int count;
-
-			  for (end = start, count = 0;
-			       end && (end->header.type
-				       == lang_input_section_enum);
-			       end = end->header.next)
-			    count++;
-
-			  p = sort_sections_1 (p, end, count,
-					       sort_by_file_name);
-			}
-		    }
-		  break;
-		}
-
-	      /* If this is a collection of grouped sections, sort them.
-		 The linker script must explicitly mention "*(.foo\$)" or
-		 "*(.foo\$*)".  Don't sort them if \$ is not the last
-		 character (not sure if this is really useful, but it
-		 allows explicitly mentioning some \$ sections and letting
-		 the linker handle the rest).  */
-	      if (sec->spec.name != NULL)
-		{
-		  const char *q = strchr (sec->spec.name, '\$');
-
-		  if (q != NULL
-		      && (q[1] == '\0'
-			  || (q[1] == '*' && q[2] == '\0')))
-		    {
-		      lang_statement_union_type *end;
-		      int count;
-
-		      for (end = *p, count = 0; end; end = end->header.next)
-			{
-			  if (end->header.type != lang_input_section_enum)
-			    abort ();
-			  count++;
-			}
-		      (void) sort_sections_1 (p, end, count,
-					      sort_by_section_name);
-		    }
-		  break;
-		}
-	    }
-	}
-	break;
-      default:
-	break;
-      }
-}
-
-static void
-gld${EMULATION_NAME}_before_allocation (void)
-{
-#ifdef TARGET_IS_armpe
-  /* FIXME: we should be able to set the size of the interworking stub
-     section.
-
-     Here we rummage through the found bfds to collect glue
-     information.  FIXME: should this be based on a command line
-     option?  krk@cygnus.com */
-  {
-    LANG_FOR_EACH_INPUT_STATEMENT (is)
-    {
-      if (!arm_process_before_allocation (is->the_bfd, & link_info))
-	{
-	  einfo (_("%P: errors encountered processing file %s\n"),
-		 is->filename);
-	}
-    }
-  }
-
-  /* We have seen it all. Allocate it, and carry on */
-  arm_allocate_interworking_sections (& link_info);
-#endif /* TARGET_IS_armpe */
-
-  sort_sections (stat_ptr->head);
-
-  before_allocation_default ();
-}
-

-/* Place an orphan section.  We use this to put sections with a '\$' in them
-   into the right place.  Any section with a '\$' in them (e.g. .text\$foo)
-   gets mapped to the output section with everything from the '\$' on stripped
-   (e.g. .text).
-   See the Microsoft Portable Executable and Common Object File Format
-   Specification 4.1, section 4.2, Grouped Sections.
-
-   FIXME: This is now handled by the linker script using wildcards,
-   but I'm leaving this here in case we want to enable it for sections
-   which are not mentioned in the linker script.  */
-
-static lang_output_section_statement_type *
-gld${EMULATION_NAME}_place_orphan (asection *s,
-				   const char *secname,
-				   int constraint)
-{
-  char *output_secname, *ps;
-  lang_output_section_statement_type *os;
-  lang_statement_union_type *l;
-
-  if ((s->flags & SEC_ALLOC) == 0)
-    return NULL;
-
-  /* Don't process grouped sections unless doing a final link.
-     If they're marked as COMDAT sections, we don't want .text\$foo to
-     end up in .text and then have .text disappear because it's marked
-     link-once-discard.  */
-  if (bfd_link_relocatable (&link_info))
-    return NULL;
-
-  /* Everything from the '\$' on gets deleted so don't allow '\$' as the
-     first character.  */
-  if (*secname == '\$')
-    fatal (_("%P: section %s has '\$' as first character\n"), secname);
-  if (strchr (secname + 1, '\$') == NULL)
-    return NULL;
-
-  /* Look up the output section.  The Microsoft specs say sections names in
-     image files never contain a '\$'.  Fortunately, lang_..._lookup creates
-     the section if it doesn't exist.  */
-  output_secname = xstrdup (secname);
-  ps = strchr (output_secname + 1, '\$');
-  *ps = 0;
-  os = lang_output_section_statement_lookup (output_secname, constraint, true);
-
-  /* Find the '\$' wild statement for this section.  We currently require the
-     linker script to explicitly mention "*(.foo\$)".  */
-
-  ps[0] = '\$';
-  ps[1] = 0;
-  for (l = os->children.head; l; l = l->header.next)
-    if (l->header.type == lang_wild_statement_enum)
-      {
-	struct wildcard_list *sec;
-
-	for (sec = l->wild_statement.section_list; sec; sec = sec->next)
-	  if (sec->spec.name && strcmp (sec->spec.name, output_secname) == 0)
-	    break;
-	if (sec)
-	  break;
-      }
-  ps[0] = 0;
-  if (l == NULL)
-    fatal (_("%P: *(%s\$) missing from linker script\n"), output_secname);
-
-  /* Link the input section in and we're done for now.
-     The sections still have to be sorted, but that has to wait until
-     all such sections have been processed by us.  The sorting is done by
-     sort_sections.  */
-  lang_add_section (&l->wild_statement.children, s, NULL, NULL, os);
-
-  return os;
-}
-

-static char *
-gld${EMULATION_NAME}_get_script (int *isfile)
-EOF
-
-if test x"$COMPILE_IN" = xyes
-then
-# Scripts compiled in.
-
-# sed commands to quote an ld script as a C string.
-sc="-f ${srcdir}/emultempl/stringify.sed"
-
-fragment <<EOF
-{
-  *isfile = 0;
-
-  if (bfd_link_relocatable (&link_info) && config.build_constructors)
-    return
-EOF
-sed $sc ldscripts/${EMULATION_NAME}.xu                 >> e${EMULATION_NAME}.c
-echo '  ; else if (bfd_link_relocatable (&link_info)) return' >> e${EMULATION_NAME}.c
-sed $sc ldscripts/${EMULATION_NAME}.xr                 >> e${EMULATION_NAME}.c
-echo '  ; else if (!config.text_read_only) return'     >> e${EMULATION_NAME}.c
-sed $sc ldscripts/${EMULATION_NAME}.xbn                >> e${EMULATION_NAME}.c
-echo '  ; else if (!config.magic_demand_paged) return' >> e${EMULATION_NAME}.c
-sed $sc ldscripts/${EMULATION_NAME}.xn                 >> e${EMULATION_NAME}.c
-echo '  ; else return'                                 >> e${EMULATION_NAME}.c
-sed $sc ldscripts/${EMULATION_NAME}.x                  >> e${EMULATION_NAME}.c
-echo '; }'                                             >> e${EMULATION_NAME}.c
-
-else
-# Scripts read from the filesystem.
-
-fragment <<EOF
-{
-  *isfile = 1;
-
-  if (bfd_link_relocatable (&link_info) && config.build_constructors)
-    return "ldscripts/${EMULATION_NAME}.xu";
-  else if (bfd_link_relocatable (&link_info))
-    return "ldscripts/${EMULATION_NAME}.xr";
-  else if (!config.text_read_only)
-    return "ldscripts/${EMULATION_NAME}.xbn";
-  else if (!config.magic_demand_paged)
-    return "ldscripts/${EMULATION_NAME}.xn";
-  else
-    return "ldscripts/${EMULATION_NAME}.x";
-}
-EOF
-fi
-
-LDEMUL_AFTER_OPEN=gld${EMULATION_NAME}_after_open
-LDEMUL_BEFORE_ALLOCATION=gld${EMULATION_NAME}_before_allocation
-LDEMUL_PLACE_ORPHAN=gld${EMULATION_NAME}_place_orphan
-LDEMUL_SET_SYMBOLS=gld${EMULATION_NAME}_set_symbols
-LDEMUL_ADD_OPTIONS=gld${EMULATION_NAME}_add_options
-LDEMUL_HANDLE_OPTION=gld${EMULATION_NAME}_handle_option
-
-source_em ${srcdir}/emultempl/emulation.em
--- a/ld/ldlex.h
+++ b/ld/ldlex.h
@@ -190,8 +190,7 @@ enum option_values
   /* Used by emultempl/elf.em, emultempl/pe.em and emultempl/pep.em.  */
   OPTION_BUILD_ID,
   OPTION_EXCLUDE_LIBS,
-  /* Used by emulparams/elf32mcore.sh, emultempl/beos.em, emultempl/pe.em
-     and emultempl/pep.em.  */
+  /* Used by emulparams/elf32mcore.sh, emultempl/pe.em and emultempl/pep.em.  */
   OPTION_BASE_FILE,
   /* Used by emultempl/ppc32elf.em and emultempl/ppc64elf.em.  */
   OPTION_NO_INLINE_OPT,
@@ -209,8 +208,7 @@ enum option_values
   OPTION_NO_WCHAR_SIZE_WARNING,
   /* Used by emultempl/armelf.em and emultempl/pe.em.  */
   OPTION_THUMB_ENTRY,
-  /* Used by emultempl/beos.em, emultempl/nto.em, emultempl/pe.em and
-     emultempl/pep.em.  */
+  /* Used by emultempl/nto.em, emultempl/pe.em and emultempl/pep.em.  */
   OPTION_STACK,
   /* Used by emultempl/aarch64elf.em, emultempl/armelf.em,
      emultempl/cskyelf.em, emultempl/hppaelf.em, emultempl/metagelf.em
@@ -327,7 +325,7 @@ enum option_values
   OPTION_NO_TLSDESC_TRAMPOLINE,
   /* Used by emultempl/nto.em.  */
   OPTION_LAZY_STACK,
-  /* Used by emultempl/pe.em, emultempl/pep.em and emultempl/beos.em.  */
+  /* Used by emultempl/pe.em and emultempl/pep.em.  */
   OPTION_DLL,
   OPTION_FILE_ALIGNMENT,
   OPTION_MAJOR_IMAGE_VERSION,
--- a/ld/lexsup.c
+++ b/ld/lexsup.c
@@ -1527,7 +1527,7 @@ parse_args (unsigned argc, char **argv)
 	  break;
 	case OPTION_IMAGE_BASE:
 	  /* Unless PE, --image-base and -Ttext-segment behavior is the same
-	     PE-specific functionality is implemented in emultempl/{pe, pep, beos}.em  */
+	     PE-specific functionality is implemented in emultempl/{pe, pep}.em  */
 	case OPTION_TTEXT_SEGMENT:
 	  set_segment_start (".text-segment", optarg);
 	  break;
--- a/ld/scripttempl/i386beos.sc
+++ /dev/null
@@ -1,181 +0,0 @@
-# Linker script for PE.
-#
-# Copyright (C) 2014-2026 Free Software Foundation, Inc.
-#
-# Copying and distribution of this file, with or without modification,
-# are permitted in any medium without royalty provided the copyright
-# notice and this notice are preserved.
-
-if test -z "${RELOCATEABLE_OUTPUT_FORMAT}"; then
-  RELOCATEABLE_OUTPUT_FORMAT=${OUTPUT_FORMAT}
-fi
-
-# We can't easily and portably get an unquoted $ in a shell
-# substitution, so we do this instead.
-if test "${RELOCATING}"; then
-  R_TEXT='*(.text$*)'
-  R_DATA='*(.data$*)'
-  R_RDATA='*(.rdata$*)'
-  R_IDATA='
-    *(.idata$2)
-    *(.idata$3)
-    /* These zeroes mark the end of the import list.  */
-    LONG (0); LONG (0); LONG (0); LONG (0); LONG (0);
-    *(.idata$4)
-    *(.idata$5)
-    *(.idata$6)
-    *(.idata$7)'
-  R_CRT='*(.CRT$*)'
-  R_RSRC='*(.rsrc$*)'
-  R_EXC='*(.exc$*)'
-else
-  R_TEXT=
-  R_DATA=
-  R_RDATA=
-  R_IDATA=
-  R_CRT=
-  R_RSRC=
-  R_EXC=
-fi
-
-cat <<EOF
-/* Copyright (C) 2014-2026 Free Software Foundation, Inc.
-
-   Copying and distribution of this script, with or without modification,
-   are permitted in any medium without royalty provided the copyright
-   notice and this notice are preserved.  */
-
-${RELOCATING+OUTPUT_FORMAT(${OUTPUT_FORMAT})}
-${RELOCATING-OUTPUT_FORMAT(${RELOCATEABLE_OUTPUT_FORMAT})}
-
-${LIB_SEARCH_DIRS}
-
-${RELOCATING+ENTRY (__start)}
-${RELOCATING+header = .;}
-${RELOCATING+__fltused = .; /* set up floating pt for MS .obj\'s */}
-${RELOCATING+__ldused = .;}
-SECTIONS
-{
-  .text ${RELOCATING+ __image_base__ + __section_alignment__ } :
-  {
-    ${RELOCATING+ __text_start__ = . ;}
-    ${RELOCATING+ KEEP (*(SORT_NONE(.init)))}
-    *(.text)
-    ${R_TEXT}
-    *(.glue_7t)
-    *(.glue_7)
-    ${CONSTRUCTING+ ___CTOR_LIST__ = .; __CTOR_LIST__ = . ;
-			LONG (-1); *(.ctors); *(.ctor); LONG (0); }
-    ${CONSTRUCTING+ ___DTOR_LIST__ = .; __DTOR_LIST__ = . ;
-			LONG (-1); *(.dtors); *(.dtor);  LONG (0); }
-    ${RELOCATING+ KEEP (*(SORT_NONE(.fini)))}
-    ${RELOCATING+/* ??? Why is .gcc_exc here?  */}
-    ${RELOCATING+ *(.gcc_exc)}
-    ${RELOCATING+ etext = .;}
-    ${RELOCATING+ __text_end__ = .;}
-    *(.gcc_except_table)
-  }
-
-  /* The Cygwin32 library uses a section to avoid copying certain data
-     on fork.  This used to be named ".data$nocopy".  The linker used
-     to include this between __data_start__ and __data_end__, but that
-     breaks building the cygwin32 dll.  Instead, we name the section
-     ".data_cygwin_nocopy" and explicitly include it after __data_end__. */
-
-  .data ${RELOCATING+BLOCK(__section_alignment__)} :
-  {
-    ${RELOCATING+__data_start__ = . ;}
-    *(.data)
-    *(.data2)
-    ${R_DATA}
-    ${RELOCATING+__data_end__ = . ;}
-    ${RELOCATING+*(.data_cygwin_nocopy)}
-  }
-
-  .bss ${RELOCATING+BLOCK(__section_alignment__)} :
-  {
-    ${RELOCATING+__bss_start__ = . ;}
-    *(.bss)
-    *(COMMON)
-    /* link.exe apparently pulls in .obj's because of UNDEF common
-	symbols, which is not the coff way, but that's MS for you. */
-    *(.CRT\$XCA)
-    *(.CRT\$XCZ)
-    *(.CRT\$XIA)
-    *(.CRT\$XIZ)
-    ${RELOCATING+__bss_end__ = . ;}
-  }
-
-  .rdata ${RELOCATING+BLOCK(__section_alignment__)} :
-  {
-    *(.rdata)
-    ${R_RDATA}
-    *(.eh_frame)
-  }
-
-  .edata ${RELOCATING+BLOCK(__section_alignment__)} :
-  {
-    *(.edata)
-  }
-
-  /DISCARD/ :
-  {
-    *(.debug\$S)
-    *(.debug\$T)
-    *(.debug\$F)
-    *(.drectve)
-    *(.debug*)
-  }
-
-  .idata ${RELOCATING+BLOCK(__section_alignment__)} :
-  {
-    /* This cannot currently be handled with grouped sections.
-	See pe.em:sort_sections.  */
-    ${R_IDATA}
-  }
-  .CRT ${RELOCATING+BLOCK(__section_alignment__)} :
-  {
-    ${R_CRT}
-  }
-
-  .endjunk ${RELOCATING+BLOCK(__section_alignment__)} :
-  {
-    /* end is deprecated, don't use it */
-    ${RELOCATING+ end = .;}
-    ${RELOCATING+ _end = .;}
-    ${RELOCATING+ __end__ = .;}
-  }
-
-  .reloc ${RELOCATING+BLOCK(__section_alignment__)} :
-  {
-    *(.reloc)
-  }
-
-  .rsrc ${RELOCATING+BLOCK(__section_alignment__)} :
-  {
-    *(.rsrc)
-    ${R_RSRC}
-  }
-
-  .exc ${RELOCATING+BLOCK(__section_alignment__)} :
-  {
-    *(.exc)
-    ${R_EXC}
-  }
-
-  .stab ${RELOCATING+BLOCK(__section_alignment__)} ${RELOCATING+(NOLOAD)} :
-  {
-    [ .stab ]
-  }
-
-  .stabstr ${RELOCATING+BLOCK(__section_alignment__)} ${RELOCATING+(NOLOAD)} :
-  {
-    [ .stabstr ]
-  }
-EOF
-
-source_sh $srcdir/scripttempl/DWARF.sc
-
-cat <<EOF
-}
-EOF
--- a/ld/testsuite/ld-bootstrap/bootstrap.exp
+++ b/ld/testsuite/ld-bootstrap/bootstrap.exp
@@ -238,8 +238,7 @@ foreach flags $test_flags {
 	|| [istarget "*-*-cygwin*"]
 	|| [istarget "*-*-winnt*"]
 	|| [istarget "*-*-mingw*"]
-	|| [istarget "*-*-interix*"]
-	|| [istarget "*-*-beospe*"]} {
+	|| [istarget "*-*-interix*"]} {
 	# Trim off the date present in PE binaries by only looking
 	#   at the ends of the files
 	# Although this works, a way to set the date would be better.
--- a/ld/testsuite/ld-vsb/vsb.exp
+++ b/ld/testsuite/ld-vsb/vsb.exp
@@ -360,7 +360,6 @@ proc visibility_run {visibility} {
 	    if { [ string match $visibility "hidden_weak" ]
 		 || [ string match $visibility "protected_weak" ] } {
 		setup_xfail "*-*-aix*"
-		setup_xfail "*-*-beos*"
 	    }
 
 	    visibility_test $visibility vnp "visibility ($visibility) (non PIC)" mainnp.o sh1np.o sh2np.o $datfile "" $NOPIE_LDFLAGS
@@ -409,7 +408,6 @@ proc visibility_run {visibility} {
 	    if { [ string match $visibility "hidden_weak" ]
 		 || [ string match $visibility "protected_weak" ] } {
 		setup_xfail "*-*-aix*"
-		setup_xfail "*-*-beos*"
 	    }
 
 	    if { ![is_xcoff_format] } {
@@ -483,7 +481,6 @@ proc visibility_run {visibility} {
 	    if { [ string match $visibility "hidden_weak" ]
 		 || [ string match $visibility "protected_weak" ] } {
 		setup_xfail "*-*-aix*"
-		setup_xfail "*-*-beos*"
 	    }
 
 	    visibility_test $visibility vmpnp "visibility ($visibility) (PIC main, non PIC so)" mainp.o sh1np.o sh2np.o $datfile "" $NOPIE_LDFLAGS
@@ -505,7 +502,6 @@ proc visibility_run {visibility} {
 	    if { [ string match $visibility "hidden_weak" ]
 		 || [ string match $visibility "protected_weak" ] } {
 		setup_xfail "*-*-aix*"
-		setup_xfail "*-*-beos*"
 	    }
 
 	    visibility_test $visibility vmpp "visibility ($visibility) (PIC main)" mainp.o sh1p.o sh2p.o $datfile "" $NOPIE_LDFLAGS

From jeffrey.law@oss.qualcomm.com  Mon Jun 29 16:49:55 2026
From: jeffrey.law@oss.qualcomm.com (Jeffrey Law)
Date: Mon, 29 Jun 2026 10:49:55 -0600
Subject: [PATCH v3] RISC-V: Fix build with GCC-8
In-Reply-To: <akHpbLZYhkVaEpSs@squeak.grove.modra.org>
References: <f2abf263-4730-4ccd-af87-e3de2289b35c@suse.com>
 <20260623133508.2896582-1-zhuangqiubin@linux.spacemit.com>
 <alpine.DEB.2.21.2606252232520.58268@angie.orcam.me.uk>
 <7f84f26f-9f88-4690-8f61-e7e893831f65@suse.com>
 <alpine.DEB.2.21.2606261151490.58268@angie.orcam.me.uk>
 <dc6104a6-70d6-443a-9605-993bfb1c7851@suse.com>
 <20260627163253.1673970-1-zhuangqiubin@linux.spacemit.com>
 <akHpbLZYhkVaEpSs@squeak.grove.modra.org>
Message-ID: <89937d9e-d967-4623-b8c8-553f690fe3e2@oss.qualcomm.com>



On 6/28/2026 9:41 PM, Alan Modra wrote:
> On Sun, Jun 28, 2026 at 12:32:53AM +0800, Mark Zhuang wrote:
>> Hi Jan, Maciej,
>>
>> I redid some testing, and this build error reproduces with both gcc-9.4.0
>> and gcc-10.5.0; in both cases it is fixed by this patch.
>>
>> Please feel free to adjust the commit message as needed when committing,
>> as well as the break/continue placement discussed earlier.
>>
>> Thanks a lot,
>> Mark
> Committed, thanks for your patience.
TYVM.? I meant to get to this over the weekend, but ran out of time.

jeff

From jeffrey.law@oss.qualcomm.com  Mon Jun 29 18:32:55 2026
From: jeffrey.law@oss.qualcomm.com (Jeffrey Law)
Date: Mon, 29 Jun 2026 12:32:55 -0600
Subject: PING^2: [PATCH 0/7] RISC-V: Add support for Andes floating-point
 and vector extensions
In-Reply-To: <aeCGSeEiI2Y441KL@atctlc04>
References: <20251118091350.2300884-1-ycl669@andestech.com>
 <aUT4_ByLdG5sljFB@atctlc04> <aeCGSeEiI2Y441KL@atctlc04>
Message-ID: <80d64b95-eda5-4a57-91d8-000573682fa4@oss.qualcomm.com>



On 4/16/2026 12:48 AM, Ethan Y. C. Liang wrote:
> Hi Nelson,
>
> Just another ping on the patch series.
So I believe Nelson is getting himself settled back in at SiFive. You 
might want to give him a bit more time to settle in, then re-ping.? I'm 
generally not the best person to review assembler, linker, loader stuff 
(though I can in a pinch).

Jeff

From jeffrey.law@oss.qualcomm.com  Mon Jun 29 19:15:52 2026
From: jeffrey.law@oss.qualcomm.com (Jeffrey Law)
Date: Mon, 29 Jun 2026 13:15:52 -0600
Subject: [PATCH] RISC-V: Check if the merged ISA string is conflicting
In-Reply-To: <CALWc1WCqpTRM_tq8uT94AV9FGGg=5SHHaDfL0cyyg3XXCGu5wQ@mail.gmail.com>
References: <CALWc1WCqpTRM_tq8uT94AV9FGGg=5SHHaDfL0cyyg3XXCGu5wQ@mail.gmail.com>
Message-ID: <7344c43c-5cb6-449c-86cd-64789d8e50f0@oss.qualcomm.com>



On 1/12/2025 11:29 PM, Yu-Cheng Liang wrote:
> In the current implementation, the linker does not check if the merged
> ISA string is conflicting when attempting to merge two ISA strings.
> For instance, no error message is generated when the linker links
> objectA (rv64i_zfinx) with objectB (rv64if).
>
> Signed-off-by: Yu-Cheng Liang <yclwlcy@gmail.com>
> ---
>   bfd/elfnn-riscv.c | 8 ++++++++
>   1 file changed, 8 insertions(+)
>
> diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
> index 3aba9c85b0f..0b8c7c33117 100644
> --- a/bfd/elfnn-riscv.c
> +++ b/bfd/elfnn-riscv.c
> @@ -3965,6 +3965,14 @@ riscv_merge_arch_attr_info (bfd *ibfd, char
> *in_arch, char *out_arch)
>
>     merged_arch_str = riscv_arch_str (ARCH_SIZE, &merged_subsets);
>
> +  /* Check if the merged ISA string is conflicting.  */
> +  riscv_subset_list_t subsets = {NULL, NULL, NULL};
> +  unsigned xlen;
> +  riscv_parse_subset_t riscv_rps_merged =
> +    {&subsets, _bfd_error_handler, &xlen, NULL, false};
> +  if (!riscv_parse_subset (&riscv_rps_merged, merged_arch_str))
> +    return NULL;
> +
>     /* Release the subset lists.  */
>     riscv_release_subset_list (&in_subsets);
>     riscv_release_subset_list (&out_subsets);
So this code was recently moved into elfxx-riscv.c.

The patch applies cleanly over in that context and Kito already gave 
approval around multilib questions that I think Nelson raised.

The question I have is don't we possibly leak memory for various objects 
allocated by riscv_parse_subset and its children and stored into the 
subsets and perhaps other fields of riscv_rps_merged?

Jeff


From hjl.tools@gmail.com  Mon Jun 29 22:39:47 2026
From: hjl.tools@gmail.com (H.J. Lu)
Date: Tue, 30 Jun 2026 06:39:47 +0800
Subject: [PATCH] readelf: Also set do_got_section_contents to false
Message-ID: <CAMe9rOoBkGLNBAijT_7d6dY2cnFnHm1+zUs+PShN6pjeAzSvgg@mail.gmail.com>

Also set do_got_section_contents to false if section headers are failed
to load.

PR binutils/34323
* readelf.c (process_object): Also set do_got_section_contents.


-- 
H.J.
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From jeffrey.law@oss.qualcomm.com  Mon Jun 29 22:55:52 2026
From: jeffrey.law@oss.qualcomm.com (Jeffrey Law)
Date: Mon, 29 Jun 2026 16:55:52 -0600
Subject: [RFC 1/2] RISC-V: Add Zvdota extension classes
In-Reply-To: <20260609153844.538604-1-jiawei@iscas.ac.cn>
References: <20260609153844.538604-1-jiawei@iscas.ac.cn>
Message-ID: <4607ca3f-d21f-41ec-89fe-a58e149bacac@oss.qualcomm.com>



On 6/9/2026 9:38 AM, Jiawei wrote:
> This patch adds assembler/disassembler support for the RISC-V Zvdota
> family of extensions [1], which compute a dot product between two vector
> register groups.
>
> The Zvdota extension family includes the following extensions:
>
> Zvqwdota8i: dot product of 8-bit integers with 32-bit accumulation.
> Zvqwdota16i: dot product of 16-bit integers with 64-bit accumulation.
> Zvfwdota16bf: dot product of bfloat16 floating-point numbers with
> 32-bit accumulation.
> Zvfqwdota8f: dot product of 8-bit floating-point numbers with
> 32-bit accumulation.
>
> Zvdota also uses the vtype alternative format bit, altfmt, which is bit 8
> of the vtype CSR. This patch adds symbolic e8alt and e16alt vsew
> constants for vsetvli/vsetivli so that assembly code can select the
> alternative element formats required by these dot-product instructions.
>
> [1] https://github.com/riscv/riscv-isa-manual/blob/zvbdot/src/zvdota.adoc
>
> bfd/ChangeLog:
>
> 	* elfxx-riscv.c (riscv_implicit_subsets): New implies.
> 	(riscv_supported_std_z_ext): New extensions.
> 	(riscv_multi_subset_supports): Ditto.
> 	(riscv_multi_subset_supports_ext): Ditto.
>
> gas/ChangeLog:
>
> 	* NEWS: Add zvqwdota8i, zvqwdota16i, zvfwdota16bf and
> 	zvfqwdota8f extensions.
> 	* config/tc-riscv.c (riscv_vsew_altfmt): New vsew altfmt
> 	constants array for e8alt and e16alt.
> 	(riscv_vtype_altfmt_supported): New function.
> 	(my_getVsetvliExpression): Ditto.
> 	* testsuite/gas/riscv/march-help.l: New test.
> 	* testsuite/gas/riscv/vector-vtype-altfmt.d: Ditto.
> 	* testsuite/gas/riscv/vector-vtype-altfmt.s: Ditto.
> 	* testsuite/gas/riscv/zvdota.d: Ditto.
> 	* testsuite/gas/riscv/zvdota.s: Ditto.
>
> include/ChangeLog:
>
> 	* opcode/riscv-opc.h (MATCH_VQWDOTAU_VV, MASK_VQWDOTAU_VV): New
> 	encoding.
> 	(MATCH_VQWDOTAS_VV, MASK_VQWDOTAS_VV): Ditto.
> 	(MATCH_VFWDOTA_VV, MASK_VFWDOTA_VV): Ditto.
> 	(MATCH_VFQWDOTA_VV, MASK_VFQWDOTA_VV): Ditto.
> 	(MATCH_VFQWDOTA_ALT_VV, MASK_VFQWDOTA_ALT_VV): Ditto.
> 	(DECLARE_INSN): New declarations.
> 	* opcode/riscv.h (OP_MASK_VTYPE_ALTFMT, OP_SH_VTYPE_ALTFMT):
> 	New vtype altfmt.
> 	(enum riscv_insn_class): New extension classes.
>
> opcodes/ChangeLog:
>
> 	* riscv-dis.c (print_insn_args): Add altfmt support.
> 	* riscv-opc.c (riscv_opcodes): New instructions.
Overall this looks pretty sensible.


> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 67fbf0f72ca..7714e5dcd49 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1234,6 +1234,10 @@ static const struct riscv_implicit_subset riscv_implicit_subsets[] =
>     {"zvfhmin", "+zve32f", check_implicit_always},
>     {"zvfbfwma", "+zve32f,+zfbfmin", check_implicit_always},
>     {"zvfbfmin", "+zve32f", check_implicit_always},
> +  {"zvfqwdota8f", "+zve32f", check_implicit_always},
> +  {"zvfwdota16bf", "+zve32f", check_implicit_always},
> +  {"zvqwdota8i", "+zve32x", check_implicit_always},
> +  {"zvqwdota16i", "+zve64x", check_implicit_always},
I'd double-check the zvfwdota16bf entry. I haven't looked real closely 
and it's just a bit odd looking that the 16i case is +zve64x, but the 16 
case is ust +zve32f rather than +zve64f.
> diff --git a/gas/NEWS b/gas/NEWS
> index e384d1135c0..ddb7983aea0 100644
> --- a/gas/NEWS
> +++ b/gas/NEWS
> @@ -1,5 +1,8 @@
>   -*- text -*-
>   
> +* Add support for RISC-V standard extensions:
> +  zvqwdota8i, zvqwdota16i, zvfwdota16bf and zvfqwdota8f v1.0.
> +
>   Changes in 2.46:
>   
>   * Add support for AMD Zen6 processor.
The NEWS entry probably needs updating given the other changes that have 
gone in recently.

I'd like to include this in the upcoming release, so please double-check 
that one entry noted above and adjust the NEWS file. With those changes 
this is OK.? I can handle pushing the final version.

Jeff

From jefflaw@qti.qualcomm.com  Mon Jun 29 23:01:56 2026
From: jefflaw@qti.qualcomm.com (Jeffrey Law)
Date: Mon, 29 Jun 2026 23:01:56 +0000
Subject: [RFC 2/2] RISC-V: Add Zvbdota extension support
In-Reply-To: <20260609153844.538604-2-jiawei@iscas.ac.cn>
References: <20260609153844.538604-1-jiawei@iscas.ac.cn>
 <20260609153844.538604-2-jiawei@iscas.ac.cn>
Message-ID: <2bebfce2-43f5-4d4a-8edc-17ab445f984c@qti.qualcomm.com>




On 6/9/2026 9:38 AM, Jiawei wrote:
> This patch supports the RISC-V Zvbdota family of batched dot-product
> extensions [1].
>
> Compared to the non-batched Zvdota family, Zvbdota computes up to eight
> dot products at a time.  These instructions use an EMUL=8 `vs2` vector
> register group and a scaled-by-8 `ci` immediate encoded in `vs2[2:0]`.
> This patch adds assembler/disassembler support for those additional
> operand constraints.
>
> The Zvbdota extension family includes the following extensions:
>
> * Zvqwbdota8i: batched dot product of 8-bit integers with 32-bit
>    accumulation.
> * Zvqwbdota16i: batched dot product of 16-bit integers with 64-bit
>    accumulation.
> * Zvfwbdota16bf: batched dot product of bfloat16 floating-point numbers
>    with 32-bit accumulation.
> * Zvfqwbdota8f: batched dot product of 8-bit floating-point numbers with
>    32-bit accumulation.
> * Zvfbdota32f: batched dot product of 32-bit single-precision
>    floating-point numbers with 32-bit accumulation.
>
> [1] https://github.com/riscv/riscv-isa-manual/blob/zvbdot/src/zvdota.adoc
>
>
> bfd/ChangeLog:
>
> 	* elfxx-riscv.c (riscv_implicit_subsets): New implies.
> 	(riscv_supported_std_z_ext): New extensions.
> 	(riscv_multi_subset_supports): Ditto.
> 	(riscv_multi_subset_supports_ext): Ditto.
>
> gas/ChangeLog:
>
> 	* NEWS: Add zvqwbdota8i, zvqwbdota16i, zvfwbdota16bf,
> 	zvfqwbdota8f and zvfbdota32f extensions.
> 	* config/tc-riscv.c (validate_riscv_insn): Add Zvbdota operand
> 	type 'q' and 'r' bits validation.
> 	(riscv_vtype_altfmt_supported): Add Zvbdota extensions.
> 	(my_getVsetvliExpression): Update altfmt error message.
> 	(riscv_ip): Add 'q' operand for VS2 EMUL=8 alignment check
> 	and 'r' operand for ci immediate.
> 	* testsuite/gas/riscv/march-help.l: Ditto.
> 	* testsuite/gas/riscv/zvbdota.d: New test.
> 	* testsuite/gas/riscv/zvbdota.s: Ditto.
> 	* testsuite/gas/riscv/zvbdota-operands-fail.d: Ditto.
> 	* testsuite/gas/riscv/zvbdota-operands-fail.l: Ditto.
> 	* testsuite/gas/riscv/zvbdota-operands-fail.s: Ditto.
> 	* testsuite/gas/riscv/zvbdota-zvqwbdota16i.d: Ditto.
> 	* testsuite/gas/riscv/zvbdota-zvqwbdota16i.s: Ditto.
>
> include/ChangeLog:
>
> 	* opcode/riscv-opc.h (MATCH_VQWBDOTAU_VV, MASK_VQWBDOTAU_VV):
> 	New encoding.
> 	(MATCH_VQWBDOTAS_VV, MASK_VQWBDOTAS_VV): Ditto.
> 	(MATCH_VFWBDOTA_VV, MASK_VFWBDOTA_VV): Ditto.
> 	(MATCH_VFQWBDOTA_VV, MASK_VFQWBDOTA_VV): Ditto.
> 	(MATCH_VFQWBDOTA_ALT_VV, MASK_VFQWBDOTA_ALT_VV): Ditto.
> 	(MATCH_VFBDOTA_VV, MASK_VFBDOTA_VV): Ditto.
> 	(DECLARE_INSN): New declarations.
> 	* opcode/riscv.h (enum riscv_insn_class): New extension classes.
>
> opcodes/ChangeLog:
>
> 	* riscv-dis.c (print_insn_args): Add 'q' and 'r' operand types
> 	for Zvbdota.
> 	* riscv-opc.c (riscv_opcodes): New instructions.
>
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 7714e5dcd49..afe7073ddb7 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1234,8 +1234,13 @@ static const struct riscv_implicit_subset riscv_implicit_subsets[] =
>     {"zvfhmin", "+zve32f", check_implicit_always},
>     {"zvfbfwma", "+zve32f,+zfbfmin", check_implicit_always},
>     {"zvfbfmin", "+zve32f", check_implicit_always},
> +  {"zvfbdota32f", "+zve32f", check_implicit_always},
> +  {"zvfqwbdota8f", "+zve32f", check_implicit_always},
>     {"zvfqwdota8f", "+zve32f", check_implicit_always},
> +  {"zvfwbdota16bf", "+zve32f", check_implicit_always},
>     {"zvfwdota16bf", "+zve32f", check_implicit_always},
> +  {"zvqwbdota8i", "+zve32x", check_implicit_always},
> +  {"zvqwbdota16i", "+zve64x", check_implicit_always},
>     {"zvqwdota8i", "+zve32x", check_implicit_always},
>     {"zvqwdota16i", "+zve64x", check_implicit_always},
>     {"zve64d", "+d,+zve64f", check_implicit_always},
So again, double check the implicit subset stuff.


> diff --git a/gas/NEWS b/gas/NEWS
> index ddb7983aea0..253f25a4691 100644
> --- a/gas/NEWS
> +++ b/gas/NEWS
> @@ -1,7 +1,8 @@
>   -*- text -*-
>   
> -* Add support for RISC-V standard extensions:
> -  zvqwdota8i, zvqwdota16i, zvfwdota16bf and zvfqwdota8f v1.0.
> +* Add support for RISC-V extensions:
> +  zvqwdota8i, zvqwdota16i, zvfwdota16bf, zvfqwdota8f, zvqwbdota8i,
> +  zvqwbdota16i, zvfwbdota16bf, zvfqwbdota8f and zvfbdota32f v1.0.
>   
>   Changes in 2.46:
And this will need updating too.

So, basically same issues to double-check/update as in the first patch 
in this series.? And like the first in this series, I'd like to include 
it in the upcoming release, so if you can turn around any updates, I can 
push it into the trunk.

Thanks!

jeff


From amodra@gmail.com  Mon Jun 29 23:39:34 2026
From: amodra@gmail.com (Alan Modra)
Date: Tue, 30 Jun 2026 09:09:34 +0930
Subject: [PATCH v5] elf: Set image base address to the maximum page size
In-Reply-To: <CAMe9rOqiiAqYstWWSE0JOowMLi6M973OOAiA7s1opkvAZ6Nv+w@mail.gmail.com>
References: <05c74589-fa62-4673-bb6e-9154d37024ee@redhat.com>
 <CAMe9rOpmyweh-+Dp4F_K2H15C4x+aTSO__fLRFxCivMnA+oDKg@mail.gmail.com>
 <CAMe9rOoW4dnsHBBLqAbHS_6fTaDwmSbjw=Ah2M0SaZVWei7i4Q@mail.gmail.com>
 <akHJNFLXxoqB-WOU@squeak.grove.modra.org>
 <CAMe9rOqiiAqYstWWSE0JOowMLi6M973OOAiA7s1opkvAZ6Nv+w@mail.gmail.com>
Message-ID: <akMCNmAY-TPVHvWp@squeak.grove.modra.org>

On Mon, Jun 29, 2026 at 11:40:53AM +0800, H.J. Lu wrote:
> 	PR ld/34184
> 	* ldexp.c (fold_binary): Set the default image base address to
> 	the maximum page size for ELF PDE output if it is lower than
> 	the maximum page size set on command-line and issue an warning
> 	if the image base address set on command-line is lower than the
> 	maximum page size.
> 	* testsuite/ld-elf/elf.exp: Add ld/34184 tests for PDE, PIE
> 	static PDE and static PIE.
> 	* testsuite/ld-elf/pr34184.c: New file.
> 	* testsuite/ld-elf/textaddr3.d: Change -Ttext-segment address
> 	to 0x200100 so that it > the maximum page size.
> 	* testsuite/ld-elf/textaddr5.d: Likewise.
> 	* testsuite/ld-elf/textaddr8.d: New test.
> 	* testsuite/ld-elf/textaddr9.d: Likewise.
> 	* testsuite/ld-elf/textaddr10.d: Likewise.

The testcases still introduce new failures.
alpha-linux-gnu  +FAIL: ld-elf/textaddr10
h8300-linux-gnu  +FAIL: ld-elf/textaddr8
microblaze-linux-gnu  +FAIL: ld-elf/textaddr10
microblaze-linux-gnu  +FAIL: ld-elf/textaddr9

alpha because the testsuite adds -Ttext-segment.  h8300 with a RWE
segment starting at 0x800000, combining .text and .data.  microblaze
also mashes .text and .data together.  None of these are your problem,
so the patch is OK.

-- 
Alan Modra

From ycl669@andestech.com  Tue Jun 30 01:49:07 2026
From: ycl669@andestech.com (=?big5?B?RXRoYW4gWXUtQ2hlbmcgTGlhbmcosefSUrV7KQ==?=)
Date: Tue, 30 Jun 2026 01:49:07 +0000
Subject: =?big5?B?pl7C0DogUElOR14yOiBbUEFUQ0ggMC83XSBSSVNDLVY6IEFkZCBzdXBwb3J0IGZv?=
 =?big5?Q?r_Andes_floating-point_and_vector_extensions?=
In-Reply-To: <80d64b95-eda5-4a57-91d8-000573682fa4@oss.qualcomm.com>
References: <20251118091350.2300884-1-ycl669@andestech.com>
 <aUT4_ByLdG5sljFB@atctlc04> <aeCGSeEiI2Y441KL@atctlc04>
 <80d64b95-eda5-4a57-91d8-000573682fa4@oss.qualcomm.com>
Message-ID: <TYZPR03MB70591B11E0EB58A44072F9839DF72@TYZPR03MB7059.apcprd03.prod.outlook.com>

Got it. Thanks for the heads-up! I really appreciate it.

Ethan
________________________________
???: Jeffrey Law <jeffrey.law@oss.qualcomm.com>
????: 2026?6?30? ?? 02:32
???: Ethan Yu-Cheng Liang(???) <ycl669@andestech.com>; binutils@sourceware.org <binutils@sourceware.org>; nelson.chu1990@gmail.com <nelson.chu1990@gmail.com>
??: Yu-Qi Liu(???) <yuqiliu@andestech.com>; Alec I-Wei Wu(???) <wuiw@andestech.com>; jasonwucj@gmail.com <jasonwucj@gmail.com>; jbeulich@suse.com <jbeulich@suse.com>
??: Re: PING^2: [PATCH 0/7] RISC-V: Add support for Andes floating-point and vector extensions

[EXTERNAL MAIL]

On 4/16/2026 12:48 AM, Ethan Y. C. Liang wrote:
> Hi Nelson,
>
> Just another ping on the patch series.
So I believe Nelson is getting himself settled back in at SiFive. You
might want to give him a bit more time to settle in, then re-ping.  I'm
generally not the best person to review assembler, linker, loader stuff
(though I can in a pinch).

Jeff
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From kito.cheng@gmail.com  Tue Jun 30 01:51:21 2026
From: kito.cheng@gmail.com (Kito Cheng)
Date: Tue, 30 Jun 2026 09:51:21 +0800
Subject: PING^2: [PATCH 0/7] RISC-V: Add support for Andes floating-point
 and vector extensions
In-Reply-To: <TYZPR03MB70591B11E0EB58A44072F9839DF72@TYZPR03MB7059.apcprd03.prod.outlook.com>
References: <20251118091350.2300884-1-ycl669@andestech.com>
 <aUT4_ByLdG5sljFB@atctlc04> <aeCGSeEiI2Y441KL@atctlc04>
 <80d64b95-eda5-4a57-91d8-000573682fa4@oss.qualcomm.com>
 <TYZPR03MB70591B11E0EB58A44072F9839DF72@TYZPR03MB7059.apcprd03.prod.outlook.com>
Message-ID: <CA+yXCZAQ2VpULn3BXyB8XRquuX1sxo088pX4V52Z047CsdVZFQ@mail.gmail.com>

loop Nelson's new mail, he is working on setting up work env...:P

Ethan Yu-Cheng Liang(???) via Binutils <binutils@sourceware.org> ?
2026?6?30??? ??9:49???
>
> Got it. Thanks for the heads-up! I really appreciate it.
>
> Ethan
> ________________________________
> ???: Jeffrey Law <jeffrey.law@oss.qualcomm.com>
> ????: 2026?6?30? ?? 02:32
> ???: Ethan Yu-Cheng Liang(???) <ycl669@andestech.com>; binutils@sourceware.org <binutils@sourceware.org>; nelson.chu1990@gmail.com <nelson.chu1990@gmail.com>
> ??: Yu-Qi Liu(???) <yuqiliu@andestech.com>; Alec I-Wei Wu(???) <wuiw@andestech.com>; jasonwucj@gmail.com <jasonwucj@gmail.com>; jbeulich@suse.com <jbeulich@suse.com>
> ??: Re: PING^2: [PATCH 0/7] RISC-V: Add support for Andes floating-point and vector extensions
>
> [EXTERNAL MAIL]
>
> On 4/16/2026 12:48 AM, Ethan Y. C. Liang wrote:
> > Hi Nelson,
> >
> > Just another ping on the patch series.
> So I believe Nelson is getting himself settled back in at SiFive. You
> might want to give him a bit more time to settle in, then re-ping.  I'm
> generally not the best person to review assembler, linker, loader stuff
> (though I can in a pinch).
>
> Jeff
> CONFIDENTIALITY NOTICE:
>
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From jiawei@iscas.ac.cn  Tue Jun 30 02:05:29 2026
From: jiawei@iscas.ac.cn (Jiawei)
Date: Tue, 30 Jun 2026 10:05:29 +0800
Subject: [RFC 1/2] RISC-V: Add Zvdota extension classes
In-Reply-To: <4607ca3f-d21f-41ec-89fe-a58e149bacac@oss.qualcomm.com>
References: <20260609153844.538604-1-jiawei@iscas.ac.cn>
 <4607ca3f-d21f-41ec-89fe-a58e149bacac@oss.qualcomm.com>
Message-ID: <04be1a37-c749-4ee5-a873-27f611fcb2fb@iscas.ac.cn>

On 2026/6/30 6:55, Jeffrey Law wrote:

>> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
>> index 67fbf0f72ca..7714e5dcd49 100644
>> --- a/bfd/elfxx-riscv.c
>> +++ b/bfd/elfxx-riscv.c
>> @@ -1234,6 +1234,10 @@ static const struct riscv_implicit_subset 
>> riscv_implicit_subsets[] =
>> ??? {"zvfhmin", "+zve32f", check_implicit_always},
>> ??? {"zvfbfwma", "+zve32f,+zfbfmin", check_implicit_always},
>> ??? {"zvfbfmin", "+zve32f", check_implicit_always},
>> +? {"zvfqwdota8f", "+zve32f", check_implicit_always},
>> +? {"zvfwdota16bf", "+zve32f", check_implicit_always},
>> +? {"zvqwdota8i", "+zve32x", check_implicit_always},
>> +? {"zvqwdota16i", "+zve64x", check_implicit_always},
> I'd double-check the zvfwdota16bf entry. I haven't looked real closely 
> and it's just a bit odd looking that the 16i case is +zve64x, but the 
> 16 case is ust +zve32f rather than +zve64f.

I checked the currently spec PR and it defined that the Zvfwdota16bf 
extension depends on the Zve32f extension.
The note description says "as an unordered FP32 dot-product instruction 
is not provided for the same" So I think it is correct here.
https://github.com/riscv/riscv-isa-manual/pull/2618/changes#diff-acc7be3418935b447f6db653029f86cc07b6b27237862bd70f5c49aa881b159dR121

>> diff --git a/gas/NEWS b/gas/NEWS
>> index e384d1135c0..ddb7983aea0 100644
>> --- a/gas/NEWS
>> +++ b/gas/NEWS
>> @@ -1,5 +1,8 @@
>> ? -*- text -*-
>> ? +* Add support for RISC-V standard extensions:
>> +? zvqwdota8i, zvqwdota16i, zvfwdota16bf and zvfqwdota8f v1.0.
>> +
>> ? Changes in 2.46:
>> ? ? * Add support for AMD Zen6 processor.
> The NEWS entry probably needs updating given the other changes that 
> have gone in recently.
>
> I'd like to include this in the upcoming release, so please 
> double-check that one entry noted above and adjust the NEWS file. With 
> those changes this is OK.? I can handle pushing the final version.
>
> Jeff

Thanks for the review Jeff.? I will update the rebased patches soon.


Best,
Jiawei


From lin1.hu@intel.com  Tue Jun 30 03:17:20 2026
From: lin1.hu@intel.com (Hu, Lin1)
Date: Tue, 30 Jun 2026 03:17:20 +0000
Subject: [PATCH v1 2/2] Support x86 ACE ISA
In-Reply-To: <20260627115533.1633143-1-Ganesh.Gopalasubramanian@amd.com>
References: <20260627095543.1627012-1-Ganesh.Gopalasubramanian@amd.com>
 <20260627115533.1633143-1-Ganesh.Gopalasubramanian@amd.com>
Message-ID: <PH3PPF801A91A7D9BCD052BC2228570C282A6F72@PH3PPF801A91A7D.namprd11.prod.outlook.com>


> -----Original Message-----
> From: Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
> Sent: Saturday, June 27, 2026 7:56 PM
> To: binutils@sourceware.org
> Cc: Jiang, Haochen <haochen.jiang@intel.com>; Beulich, Jan
> <JBeulich@suse.com>; Ganesh Gopalasubramanian
> <Ganesh.Gopalasubramanian@amd.com>
> Subject: [PATCH v1 2/2] Support x86 ACE ISA
> 
> Adds assembler and disassembler support for ACE tile, block scale register, outer
> product, and MX FP8/INT8/BF16 instructions including:
> bsrinit, bsrmovf/h/l, tilemovcol, tilemovrow, top2bf16ps, top4bssd/bsud/
> busd/buud, and top4mx* variants.
> 
> All ACE v1 instructions are enumerated under a single ACE feature flag
> (CPUID.(EAX=07H,ECX=1):ECX[11]), matching the specification.
> 
> Key changes:
> - opcodes/i386-opc.tbl: ACE instruction definitions with EVexMap6 macro
> - opcodes/i386-gen.c: single ACE CPU feature and RegBS register class
> - opcodes/i386-dis*.h: Disassembler dispatch tables for MAP6, 0F3A, 0F38
> - gas/config/tc-i386.c: ACE operand validation with proper scoping to
>   avoid interfering with AMX-AVX512 tilemovrow/tilemovcol variants
> - gas/testsuite: ACE instruction test case
> 
> The generated tables (opcodes/i386-init.h, opcodes/i386-mnem.h and
> opcodes/i386-tbl.h) are omitted from this mail to keep it within the list size limit;
> they are regenerated from opcodes/i386-opc.tbl and opcodes/i386-reg.tbl by
> i386-gen and are reflected in the diffstat.
> 
> Reference: AI Compute Extensions (ACE) Specification, v1.15
> https://x86ecosystem.org/wp-
> content/uploads/2026/06/ACE_v1_Specification_public_1_15.pdf
> 
> gas/ChangeLog:
> 
> 	* NEWS: Mention x86 ACE instruction support.
> 	* config/tc-i386.c (enum i386_error): Add unsupported_tile_index.
> 	(cpu_arch): Add ace.
> 	(_is_cpu): Handle CpuACE.
> 	(type_names): Add RegBS ("bsr") entry.
> 	(install_template): Handle CpuACE.
> 	(i386_assemble): Handle unsupported_tile_index.
> 	(check_ACE_operands): New function.
> 	(match_template): Call check_ACE_operands.
> 	(process_operands): Handle bsrinit like tilezero.
> 	(output_insn): Set GNU_PROPERTY_X86_FEATURE_2_TMM for ACE.
> 	(check_register): Allow TMM registers and the block scale
> 	register for ACE.
> 	* doc/c-i386.texi: Document .ace.
> 	* testsuite/gas/i386/x86-64.exp: Run ACE tests.
> 	* testsuite/gas/i386/x86-64-ace.d: New test.
> 	* testsuite/gas/i386/x86-64-ace-intel.d: Ditto.
> 	* testsuite/gas/i386/x86-64-ace.s: Ditto.
> 
> opcodes/ChangeLog:
> 
> 	* i386-dis.c (OP_BSR): New function.
> 	(att_names_bsr): New.
> 	(bsr, zmm_mode): New enumerators.
> 	(REG_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3): New.
> 	(MOD_VEX_0F3849_X86_64_L_0_W_1): Ditto.
> 	(RM_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3_R_0): Ditto.
> 	(PREFIX_VEX_0F3849_X86_64_L_0_W_1_M_1): Ditto.
> 	(PREFIX_EVEX_0F384A, PREFIX_EVEX_0F384B, PREFIX_EVEX_0F385C):
> Ditto.
> 	(PREFIX_EVEX_0F385E, PREFIX_EVEX_0F3A07, PREFIX_EVEX_0F3A2F):
> Ditto.
> 	(PREFIX_EVEX_0F3A8D, PREFIX_EVEX_0F3A8F, PREFIX_EVEX_MAP6_95):
> Ditto.
> 	(EVEX_LEN_0F384B, EVEX_LEN_MAP6_95_P_0_W_1): Ditto.
> 	(EVEX_W_MAP6_95_P_0, EVEX_W_MAP6_95_P_1,
> EVEX_W_MAP6_95_P_3): Ditto.
> 	(BSR, EXzmm, Rzmm, VexGd): Define.
> 	(reg_table): Add REG_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3.
> 	(prefix_table): Add PREFIX_VEX_0F3849_X86_64_L_0_W_1_M_1.
> 	(vex_w_table): Add W_1 entry to VEX_W_0F3849_X86_64_L_0.
> 	(mod_table): Add MOD_VEX_0F3849_X86_64_L_0_W_1.
> 	(rm_table): Add RM_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3_R_0
> (bsrinit).
> 	(intel_operand_size): Handle zmm_mode.
> 	(OP_E_memory): Handle zmm_mode.
> 	(print_vector_reg): Handle zmm_mode.
> 	(OP_VEX): Select 512-bit register names by bytemode.
> 	* i386-dis-evex.h: Add ACE entries to evex_table.
> 	* i386-dis-evex-len.h: Add EVEX_LEN_0F384B and
> 	EVEX_LEN_MAP6_95_P_0_W_1.
> 	* i386-dis-evex-prefix.h: Add PREFIX_EVEX_0F384A,
> PREFIX_EVEX_0F384B,
> 	PREFIX_EVEX_0F385C, PREFIX_EVEX_0F385E, PREFIX_EVEX_0F3A07,
> 	PREFIX_EVEX_0F3A2F, PREFIX_EVEX_0F3A8D, PREFIX_EVEX_0F3A8F and
> 	PREFIX_EVEX_MAP6_95.
> 	* i386-dis-evex-w.h: Add PREFIX_EVEX_0F384A and
> PREFIX_EVEX_0F3A07
> 	entries; add EVEX_W_MAP6_95_P_0, EVEX_W_MAP6_95_P_1 and
> 	EVEX_W_MAP6_95_P_3.
> 	* i386-gen.c (isa_dependencies): Add ACE.
> 	(cpu_flags): Add ACE.
> 	(operand_classes): Add RegBS.
> 	* i386-opc.h (CpuACE): New.
> 	(i386_cpu): Add cpuace.
> 	(operand_class): Add RegBS.
> 	* i386-opc.tbl: Add RegBS and EVexMap6 macros.  Add ACE
> 	instructions and enable the AMX tile, tcvtrow* and tilemovrow
> 	insns for ACE.
> 	* i386-reg.tbl: Add bsr0 block scale register.
> 	* i386-init.h: Regenerated.
> 	* i386-mnem.h: Ditto.
> 	* i386-tbl.h: Ditto.
> 
> Co-authored-by: Umesh Kalvakuntla
> ---
>  gas/NEWS                                  |     4 +
>  gas/config/tc-i386.c                      |    52 +-
>  gas/doc/c-i386.texi                       |     3 +-
>  gas/testsuite/gas/i386/x86-64-ace-intel.d |    43 +
>  gas/testsuite/gas/i386/x86-64-ace.d       |    43 +
>  gas/testsuite/gas/i386/x86-64-ace.s       |    45 +
>  gas/testsuite/gas/i386/x86-64.exp         |     2 +
>  opcodes/i386-dis-evex-len.h               |    13 +
>  opcodes/i386-dis-evex-prefix.h            |    57 +
>  opcodes/i386-dis-evex-w.h                 |    19 +-
>  opcodes/i386-dis-evex.h                   |    14 +-
>  opcodes/i386-dis.c                        |   115 +-
>  opcodes/i386-gen.c                        |     4 +
>  opcodes/i386-init.h                       |   608 +-
>  opcodes/i386-mnem.h                       |  3093 ++--
>  opcodes/i386-opc.h                        |     4 +
>  opcodes/i386-opc.tbl                      |    68 +-
>  opcodes/i386-reg.tbl                      |     4 +-
>  opcodes/i386-tbl.h                        | 18961 ++++++++++----------
>  19 files changed, 11964 insertions(+), 11188 deletions(-)  create mode 100644
> gas/testsuite/gas/i386/x86-64-ace-intel.d
>  create mode 100644 gas/testsuite/gas/i386/x86-64-ace.d
>  create mode 100644 gas/testsuite/gas/i386/x86-64-ace.s
> 
> diff --git a/gas/NEWS b/gas/NEWS
> index ef4bd048e4b..a02f11a46ed 100644
> --- a/gas/NEWS
> +++ b/gas/NEWS
> @@ -1,5 +1,9 @@
>  -*- text -*-
> 
> +* Add support for the x86 ACE (AI Compute Extensions) instructions,
> +  including tile data movement, block scale register operations and
> +tile
> +  outer products.
> +
>  * Add support for the x86 AVX10_V2_AUX instructions, providing FP8, FP4
>    and FP6 format conversion instructions.
> 
> diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index
> d82ed061a78..f6f40589d11 100644
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -272,6 +272,7 @@ enum i386_error
>      unsupported_rc_sae,
>      unsupported_vector_size,
>      unsupported_rsp_register,
> +    unsupported_tile_index,
>      internal_error,
>    };
> 
> @@ -1200,6 +1201,7 @@ static const arch_entry cpu_arch[] =
>    SUBARCH (pconfig, PCONFIG, PCONFIG, false),
>    SUBARCH (waitpkg, WAITPKG, WAITPKG, false),
>    SUBARCH (cldemote, CLDEMOTE, CLDEMOTE, false),
> +  SUBARCH (ace, ACE, ACE, false),
>    SUBARCH (amx_int8, AMX_INT8, ANY_AMX_INT8, false),
>    SUBARCH (amx_bf16, AMX_BF16, ANY_AMX_BF16, false),
>    SUBARCH (amx_fp16, AMX_FP16, ANY_AMX_FP16, false), @@ -1894,6 +1896,7
> @@ _is_cpu (const i386_cpu_attr *a, enum i386_cpu cpu)
>      case CpuAPX_F:    return a->bitfield.cpuapx_f;
>      case CpuAVX10_2:  return a->bitfield.cpuavx10_2;
>      case CpuAMX_TRANSPOSE:  return a->bitfield.cpuamx_transpose;
> +    case CpuACE:      return a->bitfield.cpuace;
>      case Cpu64:       return a->bitfield.cpu64;
>      case CpuNo64:     return a->bitfield.cpuno64;
>      default:
> @@ -3933,6 +3936,7 @@ const type_names[] =
>    { { .bitfield = { .class = RegSIMD, .zmmword = 1 } }, "rZMM" },
>    { { .bitfield = { .class = RegSIMD, .tmmword = 1 } }, "rTMM" },
>    { { .bitfield = { .class = RegMask } }, "Mask reg" },
> +  { { .bitfield = { .class = RegBS } }, "bsr" },
>  };
> 
>  static void
> @@ -4253,6 +4257,7 @@ install_template (const insn_template *t)
>  	}
> 
>        if ((maybe_cpu (t, CpuCMPCCXADD) || maybe_cpu (t, CpuAMX_TILE)
> +	   || maybe_cpu (t, CpuACE)

Outer condition is if (t->opcode_modifier.vex && t->opcode_modifier.evex),  seems that the line is invalid.

>  	   || maybe_cpu (t, CpuAVX512F) || maybe_cpu (t, CpuAVX512DQ)
>  	   || maybe_cpu (t, CpuAVX512BW) || maybe_cpu (t, CpuBMI)
>  	   || maybe_cpu (t, CpuBMI2) || maybe_cpu (t, CpuUSER_MSR) @@ -
> 7498,6 +7503,9 @@ i386_assemble (char *line)
>  	case unsupported_rsp_register:
>  	  err_msg = _("'rsp' register cannot be used");
>  	  break;
> +	case unsupported_tile_index:
> +	  err_msg = _("immediate value must be in range 0-15");
> +	  break;
>  	case internal_error:
>  	  err_msg = _("internal error");
>  	  break;
> @@ -9323,6 +9331,29 @@ check_APX_operands (const insn_template *t)
>    return 0;
>  }
> 
> +/* Check if ACE operands are valid for the instruction.  */ static bool
> +check_ACE_operands (const insn_template *t) {
> +  switch (t->mnem_off)
> +    {
> +    case MN_tilemovrow:
> +    case MN_tilemovcol:
> +      if (is_cpu (t, CpuACE)
> +	  && i.op[0].imms && i.op[0].imms->X_op == O_constant)
> +	{
> +	  offsetT val = i.op[0].imms->X_add_number;
> +	  if (val < 0 || val > 15)
> +	    {
> +	      i.error = unsupported_tile_index;
> +	      return 1;
> +	    }
> +	}
> +      break;
> +    }
> +  return 0;
> +}
> +
>  /* Check if the instruction use the REX registers or REX prefix.  */  static bool
> check_Rex_required (void) @@ -9905,6 +9936,13 @@ match_template (char
> mnem_suffix)
>  	  continue;
>  	}
> 
> +      /* Check if ACE operands are valid.  */
> +      if (check_ACE_operands (t))
> +	{
> +	  specific_error = progress (i.error);
> +	  continue;
> +	}
> +
>        /* Check whether to use the shorter VEX encoding for certain insns where
>  	 the EVEX encoding comes first in the table.  This requires the respective
>  	 AVX-* feature to be explicitly enabled.
> @@ -10994,7 +11032,7 @@ process_operands (void)
>       not ModR/M.rm.  To avoid special casing this in build_modrm_byte(), fake a
>       new destination operand here, while converting the source one to register
>       number 0.  */
> -  if (i.tm.mnem_off == MN_tilezero)
> +  if (i.tm.mnem_off == MN_tilezero || i.tm.mnem_off == MN_bsrinit)
>      {
>        copy_operand (1, 0);
>        i.op[0].regs -= i.op[0].regs->reg_num; @@ -12475,7 +12513,8 @@
> output_insn (const struct last_insn *last_insn)
>        unsigned int feature_2_used = 0;
> 
>        if ((i.xstate & xstate_tmm) == xstate_tmm
> -	  || is_cpu (&i.tm, CpuAMX_TILE))
> +	  || is_cpu (&i.tm, CpuAMX_TILE)
> +	  || is_cpu (&i.tm, CpuACE))
>  	feature_2_used |= GNU_PROPERTY_X86_FEATURE_2_TMM;
> 
>        if (is_cpu (&i.tm, Cpu8087)
> @@ -16943,13 +16982,18 @@ static bool check_register (const reg_entry *r)
>      return false;
> 
>    if (r->reg_type.bitfield.tmmword
> -      && (!cpu_arch_flags.bitfield.cpuamx_tile
> -          || flag_code != CODE_64BIT))
> +      && ((!cpu_arch_flags.bitfield.cpuamx_tile
> +	   && !cpu_arch_flags.bitfield.cpuace)
> +	  || flag_code != CODE_64BIT))
>      return false;
> 
>    if (r->reg_type.bitfield.class == RegBND && !cpu_arch_flags.bitfield.cpumpx)
>      return false;
> 
> +  if (r->reg_type.bitfield.class == RegBS
> +      && !cpu_arch_flags.bitfield.cpuace)
> +    return false;
> +
>    /* Don't allow fake index register unless allow_index_reg isn't 0. */
>    if (!allow_index_reg && r->reg_num == RegIZ)
>      return false;
> diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index
> 9f6e8da443d..5d1e15816af 100644
> --- a/gas/doc/c-i386.texi
> +++ b/gas/doc/c-i386.texi
> @@ -242,6 +242,7 @@ accept various extension mnemonics.  For example,
> @code{amx_movrs},  @code{amx_avx512},  @code{amx_tile},
> +@code{ace},
>  @code{vmx},
>  @code{vmfunc},
>  @code{smx},
> @@ -1731,7 +1732,7 @@ supported on the CPU specified.  The choices for
> @var{cpu_type} are:
>  @item @samp{.amx_int8} @tab @samp{.amx_bf16} @tab @samp{.amx_fp16}
> @item @samp{.amx_complex} @tab @samp{.amx_transpose} @tab
> @samp{.amx_tf32}  @item @samp{.amx_fp8} @tab @samp{.amx_movrs} @tab
> @samp{.amx_avx512} -@item @samp{.amx_tile}
> +@item @samp{.amx_tile} @tab @samp{.ace}
>  @item @samp{.kl} @tab @samp{.widekl} @tab @samp{.uintr} @tab
> @samp{.hreset}  @item @samp{.3dnow} @tab @samp{.3dnowa} @tab
> @samp{.sse4a} @tab @samp{.sse5}  @item @samp{.syscall} @tab
> @samp{.rdtscp} @tab @samp{.svme} diff --git a/gas/testsuite/gas/i386/x86-64-
> ace-intel.d b/gas/testsuite/gas/i386/x86-64-ace-intel.d
> new file mode 100644
> index 00000000000..b116845d240
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-ace-intel.d
> @@ -0,0 +1,43 @@
> +#objdump: -dw -Mintel
> +#name: 64-bit ACE insns (Intel disassembly)
> +#source: x86-64-ace.s
> +
> +.*: +file format .*
> +
> +Disassembly of section \.text:
> +
> +[0-9a-f]+ <start>:
> +[\s]*[a-f0-9]+:[\s]*c4 e2 fb 49 c0[\s]*bsrinit bsr0
> +[\s]*[a-f0-9]+:[\s]*62 f6 f4 48 95 c3[\s]*bsrmovf bsr0,zmm1,zmm3
> +[\s]*[a-f0-9]+:[\s]*62 d6 ff 48 95 c2[\s]*bsrmovh bsr0,zmm10
> +[\s]*[a-f0-9]+:[\s]*62 d6 fe 48 95 c2[\s]*bsrmovl bsr0,zmm10
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 ff 48 95 00[\s]*bsrmovh bsr0,ZMMWORD PTR
> +\[eax\]
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 fe 48 95 00[\s]*bsrmovl bsr0,ZMMWORD PTR
> +\[eax\]
> +[\s]*[a-f0-9]+:[\s]*62 f6 7f 48 95 c4[\s]*bsrmovh zmm4,bsr0
> +[\s]*[a-f0-9]+:[\s]*62 f6 7e 48 95 c4[\s]*bsrmovl zmm4,bsr0
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 7f 48 95 00[\s]*bsrmovh ZMMWORD PTR
> +\[eax\],bsr0
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 7e 48 95 00[\s]*bsrmovl ZMMWORD PTR
> +\[eax\],bsr0
> +[\s]*[a-f0-9]+:[\s]*62 f3 fd 48 2f ca 08[\s]*tilemovcol tmm1,zmm2,0x8
> +[\s]*[a-f0-9]+:[\s]*62 f3 fd 48 07 ca 08[\s]*tilemovrow tmm1,zmm2,0x8
> +[\s]*[a-f0-9]+:[\s]*62 f2 e5 48 4b ca[\s]*tilemovcol tmm1,zmm2,ebx
> +[\s]*[a-f0-9]+:[\s]*62 f2 e5 48 4a ca[\s]*tilemovrow tmm1,zmm2,ebx
> +[\s]*[a-f0-9]+:[\s]*62 f2 6e 48 5c c1[\s]*top2bf16ps tmm0,zmm1,zmm2
> +[\s]*[a-f0-9]+:[\s]*62 f2 6f 48 5e c1[\s]*top4bssd tmm0,zmm1,zmm2
> +[\s]*[a-f0-9]+:[\s]*62 f2 6e 48 5e c1[\s]*top4bsud tmm0,zmm1,zmm2
> +[\s]*[a-f0-9]+:[\s]*62 f2 6d 48 5e c1[\s]*top4busd tmm0,zmm1,zmm2
> +[\s]*[a-f0-9]+:[\s]*62 f2 6c 48 5e c1[\s]*top4buud tmm0,zmm1,zmm2
> +[\s]*[a-f0-9]+:[\s]*62 f3 6c 48 8d c9 07[\s]*top4mxbf8ps
> +tmm1,zmm1,zmm2,0x7
> +[\s]*[a-f0-9]+:[\s]*62 f3 6f 48 8d c9 07[\s]*top4mxbhf8ps
> +tmm1,zmm1,zmm2,0x7
> +[\s]*[a-f0-9]+:[\s]*62 f3 6e 48 8d c9 07[\s]*top4mxhbf8ps
> +tmm1,zmm1,zmm2,0x7
> +[\s]*[a-f0-9]+:[\s]*62 f3 6d 48 8d c9 07[\s]*top4mxhf8ps
> +tmm1,zmm1,zmm2,0x7
> +[\s]*[a-f0-9]+:[\s]*62 f3 6f 48 8f c9 07[\s]*top4mxbssps
> +tmm1,zmm1,zmm2,0x7
> +[\s]*[a-f0-9]+:[\s]*62 62 6e 48 4a f5[\s]*tcvtrowd2ps zmm30,tmm5,edx
> +[\s]*[a-f0-9]+:[\s]*62 63 7e 48 07 f5 7b[\s]*tcvtrowd2ps
> +zmm30,tmm5,0x7b
> +[\s]*[a-f0-9]+:[\s]*62 62 6f 48 6d f5[\s]*tcvtrowps2bf16h
> +zmm30,tmm5,edx
> +[\s]*[a-f0-9]+:[\s]*62 63 7f 48 07 f5 7b[\s]*tcvtrowps2bf16h
> +zmm30,tmm5,0x7b
> +[\s]*[a-f0-9]+:[\s]*62 62 6e 48 6d f5[\s]*tcvtrowps2bf16l
> +zmm30,tmm5,edx
> +[\s]*[a-f0-9]+:[\s]*62 63 7e 48 77 f5 7b[\s]*tcvtrowps2bf16l
> +zmm30,tmm5,0x7b
> +[\s]*[a-f0-9]+:[\s]*62 62 6c 48 6d f5[\s]*tcvtrowps2phh zmm30,tmm5,edx
> +[\s]*[a-f0-9]+:[\s]*62 63 7c 48 07 f5 7b[\s]*tcvtrowps2phh
> +zmm30,tmm5,0x7b
> +[\s]*[a-f0-9]+:[\s]*62 62 6d 48 6d f5[\s]*tcvtrowps2phl zmm30,tmm5,edx
> +[\s]*[a-f0-9]+:[\s]*62 63 7f 48 77 f5 7b[\s]*tcvtrowps2phl
> +zmm30,tmm5,0x7b
> diff --git a/gas/testsuite/gas/i386/x86-64-ace.d b/gas/testsuite/gas/i386/x86-
> 64-ace.d
> new file mode 100644
> index 00000000000..cc91aa7fede
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-ace.d
> @@ -0,0 +1,43 @@
> +#objdump: -dw
> +#name: 64-bit ACE insns
> +#source: x86-64-ace.s
> +
> +.*: +file format .*
> +
> +Disassembly of section \.text:
> +
> +[0-9a-f]+ <start>:
> +[\s]*[a-f0-9]+:[\s]*c4 e2 fb 49 c0[\s]*bsrinit %bsr0
> +[\s]*[a-f0-9]+:[\s]*62 f6 f4 48 95 c3[\s]*bsrmovf %zmm3,%zmm1,%bsr0
> +[\s]*[a-f0-9]+:[\s]*62 d6 ff 48 95 c2[\s]*bsrmovh %zmm10,%bsr0
> +[\s]*[a-f0-9]+:[\s]*62 d6 fe 48 95 c2[\s]*bsrmovl %zmm10,%bsr0
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 ff 48 95 00[\s]*bsrmovh \(%eax\),%bsr0
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 fe 48 95 00[\s]*bsrmovl \(%eax\),%bsr0
> +[\s]*[a-f0-9]+:[\s]*62 f6 7f 48 95 c4[\s]*bsrmovh %bsr0,%zmm4
> +[\s]*[a-f0-9]+:[\s]*62 f6 7e 48 95 c4[\s]*bsrmovl %bsr0,%zmm4
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 7f 48 95 00[\s]*bsrmovh %bsr0,\(%eax\)
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 7e 48 95 00[\s]*bsrmovl %bsr0,\(%eax\)
> +[\s]*[a-f0-9]+:[\s]*62 f3 fd 48 2f ca 08[\s]*tilemovcol
> +\$0x8,%zmm2,%tmm1
> +[\s]*[a-f0-9]+:[\s]*62 f3 fd 48 07 ca 08[\s]*tilemovrow
> +\$0x8,%zmm2,%tmm1
> +[\s]*[a-f0-9]+:[\s]*62 f2 e5 48 4b ca[\s]*tilemovcol %ebx,%zmm2,%tmm1
> +[\s]*[a-f0-9]+:[\s]*62 f2 e5 48 4a ca[\s]*tilemovrow %ebx,%zmm2,%tmm1
> +[\s]*[a-f0-9]+:[\s]*62 f2 6e 48 5c c1[\s]*top2bf16ps %zmm2,%zmm1,%tmm0
> +[\s]*[a-f0-9]+:[\s]*62 f2 6f 48 5e c1[\s]*top4bssd %zmm2,%zmm1,%tmm0
> +[\s]*[a-f0-9]+:[\s]*62 f2 6e 48 5e c1[\s]*top4bsud %zmm2,%zmm1,%tmm0
> +[\s]*[a-f0-9]+:[\s]*62 f2 6d 48 5e c1[\s]*top4busd %zmm2,%zmm1,%tmm0
> +[\s]*[a-f0-9]+:[\s]*62 f2 6c 48 5e c1[\s]*top4buud %zmm2,%zmm1,%tmm0
> +[\s]*[a-f0-9]+:[\s]*62 f3 6c 48 8d c9 07[\s]*top4mxbf8ps
> +\$0x7,%zmm2,%zmm1,%tmm1
> +[\s]*[a-f0-9]+:[\s]*62 f3 6f 48 8d c9 07[\s]*top4mxbhf8ps
> +\$0x7,%zmm2,%zmm1,%tmm1
> +[\s]*[a-f0-9]+:[\s]*62 f3 6e 48 8d c9 07[\s]*top4mxhbf8ps
> +\$0x7,%zmm2,%zmm1,%tmm1
> +[\s]*[a-f0-9]+:[\s]*62 f3 6d 48 8d c9 07[\s]*top4mxhf8ps
> +\$0x7,%zmm2,%zmm1,%tmm1
> +[\s]*[a-f0-9]+:[\s]*62 f3 6f 48 8f c9 07[\s]*top4mxbssps
> +\$0x7,%zmm2,%zmm1,%tmm1
> +[\s]*[a-f0-9]+:[\s]*62 62 6e 48 4a f5[\s]*tcvtrowd2ps %edx,%tmm5,%zmm30
> +[\s]*[a-f0-9]+:[\s]*62 63 7e 48 07 f5 7b[\s]*tcvtrowd2ps
> +\$0x7b,%tmm5,%zmm30
> +[\s]*[a-f0-9]+:[\s]*62 62 6f 48 6d f5[\s]*tcvtrowps2bf16h
> +%edx,%tmm5,%zmm30
> +[\s]*[a-f0-9]+:[\s]*62 63 7f 48 07 f5 7b[\s]*tcvtrowps2bf16h
> +\$0x7b,%tmm5,%zmm30
> +[\s]*[a-f0-9]+:[\s]*62 62 6e 48 6d f5[\s]*tcvtrowps2bf16l
> +%edx,%tmm5,%zmm30
> +[\s]*[a-f0-9]+:[\s]*62 63 7e 48 77 f5 7b[\s]*tcvtrowps2bf16l
> +\$0x7b,%tmm5,%zmm30
> +[\s]*[a-f0-9]+:[\s]*62 62 6c 48 6d f5[\s]*tcvtrowps2phh
> +%edx,%tmm5,%zmm30
> +[\s]*[a-f0-9]+:[\s]*62 63 7c 48 07 f5 7b[\s]*tcvtrowps2phh
> +\$0x7b,%tmm5,%zmm30
> +[\s]*[a-f0-9]+:[\s]*62 62 6d 48 6d f5[\s]*tcvtrowps2phl
> +%edx,%tmm5,%zmm30
> +[\s]*[a-f0-9]+:[\s]*62 63 7f 48 77 f5 7b[\s]*tcvtrowps2phl
> +\$0x7b,%tmm5,%zmm30
> diff --git a/gas/testsuite/gas/i386/x86-64-ace.s b/gas/testsuite/gas/i386/x86-64-
> ace.s
> new file mode 100644
> index 00000000000..9c7bf8a2214
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-ace.s
> @@ -0,0 +1,45 @@
> +# Check 64-bit ACE instructions
> +
> +	.text
> +start:
> +	bsrinit %bsr0
> +	bsrmovf %zmm3, %zmm1, %bsr0
> +
> +	bsrmovh %zmm10, %bsr0
> +	bsrmovl %zmm10, %bsr0
> +	bsrmovh (%eax), %bsr0
> +	bsrmovl (%eax), %bsr0
> +
> +	bsrmovh %bsr0, %zmm4
> +	bsrmovl %bsr0, %zmm4
> +	bsrmovh %bsr0, (%eax)
> +	bsrmovl %bsr0, (%eax)
> +
> +	tilemovcol $8, %zmm2, %tmm1
> +	tilemovrow $8, %zmm2, %tmm1
> +
> +	tilemovcol %ebx, %zmm2, %tmm1
> +	tilemovrow %ebx, %zmm2, %tmm1
> +
> +	top2bf16ps %zmm2, %zmm1, %tmm0
> +	top4bssd   %zmm2, %zmm1, %tmm0
> +	top4bsud   %zmm2, %zmm1, %tmm0
> +	top4busd   %zmm2, %zmm1, %tmm0
> +	top4buud   %zmm2, %zmm1, %tmm0
> +
> +	top4mxbf8ps  $7, %zmm2, %zmm1, %tmm1
> +	top4mxbhf8ps $7, %zmm2, %zmm1, %tmm1
> +	top4mxhbf8ps $7, %zmm2, %zmm1, %tmm1
> +	top4mxhf8ps  $7, %zmm2, %zmm1, %tmm1
> +	top4mxbssps  $7, %zmm2, %zmm1, %tmm1
> +
> +	tcvtrowd2ps     %edx, %tmm5, %zmm30
> +	tcvtrowd2ps     $0x7b, %tmm5, %zmm30
> +	tcvtrowps2bf16h %edx, %tmm5, %zmm30
> +	tcvtrowps2bf16h $0x7b, %tmm5, %zmm30
> +	tcvtrowps2bf16l %edx, %tmm5, %zmm30
> +	tcvtrowps2bf16l $0x7b, %tmm5, %zmm30
> +	tcvtrowps2phh   %edx, %tmm5, %zmm30
> +	tcvtrowps2phh   $0x7b, %tmm5, %zmm30
> +	tcvtrowps2phl   %edx, %tmm5, %zmm30
> +	tcvtrowps2phl   $0x7b, %tmm5, %zmm30
> diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-
> 64.exp
> index d0d3cb47117..ae5d8bff1ba 100644
> --- a/gas/testsuite/gas/i386/x86-64.exp
> +++ b/gas/testsuite/gas/i386/x86-64.exp
> @@ -689,6 +689,8 @@ run_list_test "x86-64-amx-inval"
>  run_dump_test "x86-64-amx"
>  run_dump_test "x86-64-amx-intel"
>  run_dump_test "x86-64-amx-bad"
> +run_dump_test "x86-64-ace"
> +run_dump_test "x86-64-ace-intel"
> 
>  if { ![istarget "*-*-aix*"]
>       && ![istarget "*-*-beos*"]
> diff --git a/opcodes/i386-dis-evex-len.h b/opcodes/i386-dis-evex-len.h index
> 370710915de..273c6d40d12 100644
> --- a/opcodes/i386-dis-evex-len.h
> +++ b/opcodes/i386-dis-evex-len.h
> @@ -51,6 +51,13 @@ static const struct dis386 evex_len_table[][3] = {
>      { PREFIX_TABLE (PREFIX_EVEX_0F384A_X86_64_W_0_L_2) },
>    },
> 
> +  /* EVEX_LEN_0F384B */
> +  {
> +    { X86_64_EVEX_W_TABLE (VEX_W_0F384B_X86_64_L_0) },
> +    { Bad_Opcode },
> +    { PREFIX_TABLE (PREFIX_EVEX_0F384B) },  },
> +
>    /* EVEX_LEN_0F385A */
>    {
>      { Bad_Opcode },
> @@ -207,4 +214,10 @@ static const struct dis386 evex_len_table[][3] = {
>      { "vbmacxor16x16x16", { XM, Vex, EXx }, NO_PREFIX },
>      { "vbmacxor16x16x16", { XM, Vex, EXx }, NO_PREFIX },
>    },
> +  /* EVEX_LEN_MAP6_95_P_0_W_1 */
> +  {
> +    { Bad_Opcode },
> +    { Bad_Opcode },
> +    { "bsrmovf", { BSR, Vex, EXx }, 0 },  },
>  };
> diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h
> index ffecef5e796..f3b031470df 100644
> --- a/opcodes/i386-dis-evex-prefix.h
> +++ b/opcodes/i386-dis-evex-prefix.h
> @@ -254,6 +254,18 @@
>      { "tcvtrowd2ps",	{ XM, Rtmm, VexGdq }, 0 },
>      { "tilemovrow",	{ XM, Rtmm, VexGdq }, 0 },
>    },
> +  /* PREFIX_EVEX_0F384A */
> +  {
> +    { Bad_Opcode },
> +    { Bad_Opcode },
> +    { "tilemovrow",	{ TMM, Rzmm, VexGd }, 0 },
> +  },
> +  /* PREFIX_EVEX_0F384B */
> +  {
> +    { Bad_Opcode },
> +    { Bad_Opcode },
> +    { "tilemovcol",	{ TMM, Rzmm, VexGd }, 0 },
> +  },
>    /* PREFIX_EVEX_0F3852 */
>    {
>      { "vdpphp%XS",	{ XM, Vex, EXx }, 0 },
> @@ -268,6 +280,18 @@
>      { VEX_W_TABLE (VEX_W_0F3853) },
>      { "vp4dpws%XSds",	{ XM, Vex, Mxmm }, 0 },
>    },
> +  /* PREFIX_EVEX_0F385C */
> +  {
> +    { Bad_Opcode },
> +    { "top2bf16ps",	{ TMM, Rzmm, Vex }, 0 },
> +  },
> +  /* PREFIX_EVEX_0F385E */
> +  {
> +    { "top4buud",	{ TMM, Rzmm, Vex }, 0 },
> +    { "top4bsud",	{ TMM, Rzmm, Vex }, 0 },
> +    { "top4busd",	{ TMM, Rzmm, Vex }, 0 },
> +    { "top4bssd",	{ TMM, Rzmm, Vex }, 0 },
> +  },
>    /* PREFIX_EVEX_0F3868 */
>    {
>      { Bad_Opcode },
> @@ -331,6 +355,12 @@
>      { "tilemovrow",	{ XM, Rtmm, Ib }, 0 },
>      { "tcvtrowps2bf16h",	{ XM, Rtmm, Ib }, 0 },
>    },
> +  /* PREFIX_EVEX_0F3A07 */
> +  {
> +    { Bad_Opcode },
> +    { Bad_Opcode },
> +    { "tilemovrow", { TMM, Rzmm, Ib }, 0 },  },
>    /* PREFIX_EVEX_0F3A08 */
>    {
>      { "vrndscalep%XH",  { XM, EXxh, EXxEVexS, Ib }, 0 }, @@ -357,6 +387,12 @@
>      { Bad_Opcode },
>      { "vgetmants%XW",	{ XMScalar, VexScalar, EXdq, EXxEVexS, Ib }, 0 },
>    },
> +  /* PREFIX_EVEX_0F3A2F */
> +  {
> +    { Bad_Opcode },
> +    { Bad_Opcode },
> +    { "tilemovcol", { TMM, Rzmm, Ib }, 0 },  },
>    /* PREFIX_EVEX_0F3A42_W_0 */
>    {
>      { Bad_Opcode },
> @@ -409,6 +445,20 @@
>      { Bad_Opcode },
>      { "tcvtrowps2phl",	{ XM, Rtmm, Ib }, 0 },
>    },
> +  /* PREFIX_EVEX_0F3A8D */
> +  {
> +    { "top4mxbf8ps",	{ TMM, Rzmm, Vex, Ib }, 0 },
> +    { "top4mxhbf8ps",	{ TMM, Rzmm, Vex, Ib }, 0 },
> +    { "top4mxhf8ps",	{ TMM, Rzmm, Vex, Ib }, 0 },
> +    { "top4mxbhf8ps",	{ TMM, Rzmm, Vex, Ib }, 0 },
> +  },
> +  /* PREFIX_EVEX_0F3A8F */
> +  {
> +    { Bad_Opcode },
> +    { Bad_Opcode },
> +    { Bad_Opcode },
> +    { "top4mxbssps",	{ TMM, Rzmm, Vex, Ib }, 0 },
> +  },
>    /* PREFIX_EVEX_0F3AC2 */
>    {
>      { "vcmpp%XH", { MaskG, Vex, EXxh, EXxEVexS, CMP }, 0 }, @@ -833,6 +883,13
> @@
>      { Bad_Opcode },
>      { "vfnmsub231p%XH",	{ XM, Vex, EXxh, EXxEVexR }, 0 },
>    },
> +  /* PREFIX_EVEX_MAP6_95 */
> +  {
> +    { VEX_W_TABLE (EVEX_W_MAP6_95_P_0) },
> +    { VEX_W_TABLE (EVEX_W_MAP6_95_P_1) },
> +    { Bad_Opcode },
> +    { VEX_W_TABLE (EVEX_W_MAP6_95_P_3) },  },
>    /* PREFIX_EVEX_MAP6_D6 */
>    {
>      { Bad_Opcode },
> diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h index
> 6e94bc45fe1..8e0529e1a08 100644
> --- a/opcodes/i386-dis-evex-w.h
> +++ b/opcodes/i386-dis-evex-w.h
> @@ -349,6 +349,7 @@
>    /* EVEX_W_0F384A_X86_64 */
>    {
>      { EVEX_LEN_TABLE (EVEX_LEN_0F384A_X86_64_W_0) },
> +    { PREFIX_TABLE (PREFIX_EVEX_0F384A) },
>    },
>    /* EVEX_W_0F3859 */
>    {
> @@ -395,6 +396,7 @@
>    /* EVEX_W_0F3A07_X86_64 */
>    {
>      { EVEX_LEN_TABLE (EVEX_LEN_0F3A07_X86_64_W_0) },
> +    { PREFIX_TABLE (PREFIX_EVEX_0F3A07) },
>    },
>    /* EVEX_W_0F3A18_L_n */
>    {
> @@ -553,4 +555,19 @@
>    {
>      { "vbitrevb", { XM, EXx }, NO_PREFIX },
>      { Bad_Opcode }
> -  }
> +  },
> +  /* EVEX_W_MAP6_95_P_0 */
> +  {
> +    { Bad_Opcode },
> +    { EVEX_LEN_TABLE (EVEX_LEN_MAP6_95_P_0_W_1) },  },
> +  /* EVEX_W_MAP6_95_P_1 */
> +  {
> +    { "bsrmovl", { EXzmm, BSR }, 0 },
> +    { "bsrmovl", { BSR, EXzmm }, 0 },
> +  },
> +  /* EVEX_W_MAP6_95_P_3 */
> +  {
> +    { "bsrmovh", { EXzmm, BSR }, 0 },
> +    { "bsrmovh", { BSR, EXzmm }, 0 },
> +  },
> diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h index
> 7d555aa9e11..9ad57912231 100644
> --- a/opcodes/i386-dis-evex.h
> +++ b/opcodes/i386-dis-evex.h
> @@ -377,7 +377,7 @@ static const struct dis386 evex_table[][256] = {
>      { Bad_Opcode },
>      { X86_64_EVEX_MEM_W_TABLE (VEX_W_0F3849_X86_64_L_0) },
>      { X86_64_TABLE (X86_64_EVEX_0F384A) },
> -    { X86_64_EVEX_MEM_W_TABLE (VEX_W_0F384B_X86_64_L_0) },
> +    { EVEX_LEN_TABLE (EVEX_LEN_0F384B) },
>      { "vrcp14p%XW",	{ XM, EXx }, PREFIX_DATA },
>      { "vrcp14s%XW",	{ XMScalar, VexScalar, EXdq }, PREFIX_DATA },
>      { "vrsqrt14p%XW",	{ XM, EXx }, 0 },
> @@ -396,9 +396,9 @@ static const struct dis386 evex_table[][256] = {
>      { VEX_W_TABLE (EVEX_W_0F3859) },
>      { EVEX_LEN_TABLE (EVEX_LEN_0F385A) },
>      { EVEX_LEN_TABLE (EVEX_LEN_0F385B) },
> +    { PREFIX_TABLE (PREFIX_EVEX_0F385C) },
>      { Bad_Opcode },
> -    { Bad_Opcode },
> -    { Bad_Opcode },
> +    { PREFIX_TABLE (PREFIX_EVEX_0F385E) },
>      { Bad_Opcode },
>      /* 60 */
>      { Bad_Opcode },
> @@ -636,7 +636,7 @@ static const struct dis386 evex_table[][256] = {
>      { Bad_Opcode },
>      { Bad_Opcode },
>      { Bad_Opcode },
> -    { Bad_Opcode },
> +    { PREFIX_TABLE (PREFIX_EVEX_0F3A2F) },
>      /* 30 */
>      { Bad_Opcode },
>      { Bad_Opcode },
> @@ -742,9 +742,9 @@ static const struct dis386 evex_table[][256] = {
>      { Bad_Opcode },
>      { Bad_Opcode },
>      { Bad_Opcode },
> +    { PREFIX_TABLE (PREFIX_EVEX_0F3A8D) },
>      { Bad_Opcode },
> -    { Bad_Opcode },
> -    { Bad_Opcode },
> +    { PREFIX_TABLE (PREFIX_EVEX_0F3A8F) },
>      /* 90 */
>      { Bad_Opcode },
>      { Bad_Opcode },
> @@ -1624,7 +1624,7 @@ static const struct dis386 evex_table[][256] = {
>      { Bad_Opcode },
>      { Bad_Opcode },
>      { Bad_Opcode },
> -    { Bad_Opcode },
> +    { PREFIX_TABLE (PREFIX_EVEX_MAP6_95) },
>      { "vfmaddsub132p%XH",  { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
>      { "vfmsubadd132p%XH",  { XM, Vex, EXxh, EXxEVexR }, PREFIX_DATA },
>      /* 98 */
> diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index
> 5643cfe55d5..f39774f2a83 100644
> --- a/opcodes/i386-dis.c
> +++ b/opcodes/i386-dis.c
> @@ -70,6 +70,7 @@ static bool OP_D (instr_info *, int, int);  static bool OP_T
> (instr_info *, int, int);  static bool OP_MMX (instr_info *, int, int);  static bool
> OP_XMM (instr_info *, int, int);
> +static bool OP_BSR (instr_info *, int, int);
>  static bool OP_EM (instr_info *, int, int);  static bool OP_EX (instr_info *, int, int);
> static bool OP_EMC (instr_info *, int,int); @@ -513,6 +514,7 @@ fetch_error
> (const instr_info *ins)  #define RMBH { OP_REG, bh_reg }  #define RMAX
> { OP_REG, ax_reg }  #define RMDX { OP_REG, dx_reg }
> +#define BSR { OP_BSR, bsr }
> 
>  #define eAX { OP_IMREG, eAX_reg }
>  #define AL { OP_IMREG, al_reg }
> @@ -566,6 +568,7 @@ fetch_error (const instr_info *ins)  #define EXxS { OP_EX,
> x_swap_mode }  #define EXxmm { OP_EX, xmm_mode }  #define EXymm { OP_EX,
> ymm_mode }
> +#define EXzmm { OP_EX, zmm_mode }
>  #define EXxmmq { OP_EX, xmmq_mode }
>  #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }  #define
> EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } @@ -583,6
> +586,7 @@ fetch_error (const instr_info *ins)  #define Uxmm { OP_R,
> xmm_mode }  #define Rxmmq { OP_R, xmmq_mode }  #define Rymm { OP_R,
> ymm_mode }
> +#define Rzmm { OP_R, zmm_mode }
>  #define Rtmm { OP_R, tmm_mode }
>  #define EMCq { OP_EMC, q_mode }
>  #define MXC { OP_MXC, 0 }
> @@ -600,6 +604,7 @@ fetch_error (const instr_info *ins)  #define VexGatherQ
> { OP_VEX, vex_vsib_q_w_dq_mode }  #define VexGdq { OP_VEX, dq_mode }
> #define VexGb { OP_VEX, b_mode }
> +#define VexGd { OP_VEX, d_mode }
>  #define VexGv { OP_VEX, v_mode }
>  #define VexTmm { OP_VEX, tmm_mode }
>  #define XMVexI4 { OP_REG_VexI4, x_mode } @@ -720,6 +725,8 @@ enum
>    ymm_mode,
>    /* quad word, ymmword or zmmword memory operand.  */
>    ymmq_mode,
> +  /* 64-byte ZMM operand */
> +  zmm_mode,
>    /* TMM operand */
>    tmm_mode,
>    /* d_mode in 32bit, q_mode in 64bit mode.  */ @@ -821,6 +828,8 @@ enum
>    rSI_reg,
>    rDI_reg,
> 
> +  bsr,
> +
>    z_mode_ax_reg,
>    indir_dx_reg
>  };
> @@ -908,6 +917,7 @@ enum
>    REG_VEX_0F73,
>    REG_VEX_0FAE,
>    REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0,
> +  REG_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3,
>    REG_VEX_0F38F3_L_0_P_0,
>    REG_VEX_MAP7_F6_L_0_W_0,
>    REG_VEX_MAP7_F8_L_0_W_0,
> @@ -971,6 +981,7 @@ enum
>    MOD_0F38F8,
> 
>    MOD_VEX_0F3849_X86_64_L_0_W_0,
> +  MOD_VEX_0F3849_X86_64_L_0_W_1,
> 
>    MOD_EVEX_MAP4_60,
>    MOD_EVEX_MAP4_61,
> @@ -995,6 +1006,7 @@ enum
> 
>    RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0,
>    RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3,
> +  RM_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3_R_0,
>  };
> 
>  enum
> @@ -1141,6 +1153,7 @@ enum
>    PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0,
>    PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1,
>    PREFIX_VEX_0F384A_X86_64_W_0_L_0,
> +  PREFIX_VEX_0F3849_X86_64_L_0_W_1_M_1,
>    PREFIX_VEX_0F384B_X86_64_L_0_W_0,
>    PREFIX_VEX_0F3850_W_0,
>    PREFIX_VEX_0F3851_W_0,
> @@ -1213,8 +1226,12 @@ enum
>    PREFIX_EVEX_0F383A,
>    PREFIX_EVEX_0F3841,
>    PREFIX_EVEX_0F384A_X86_64_W_0_L_2,
> +  PREFIX_EVEX_0F384A,
> +  PREFIX_EVEX_0F384B,
>    PREFIX_EVEX_0F3852,
>    PREFIX_EVEX_0F3853,
> +  PREFIX_EVEX_0F385C,
> +  PREFIX_EVEX_0F385E,
>    PREFIX_EVEX_0F3868,
>    PREFIX_EVEX_0F386D_X86_64_W_0_L_2,
>    PREFIX_EVEX_0F3872,
> @@ -1225,10 +1242,12 @@ enum
>    PREFIX_EVEX_0F38AB,
> 
>    PREFIX_EVEX_0F3A07_X86_64_W_0_L_2,
> +  PREFIX_EVEX_0F3A07,
>    PREFIX_EVEX_0F3A08,
>    PREFIX_EVEX_0F3A0A,
>    PREFIX_EVEX_0F3A26,
>    PREFIX_EVEX_0F3A27,
> +  PREFIX_EVEX_0F3A2F,
>    PREFIX_EVEX_0F3A42_W_0,
>    PREFIX_EVEX_0F3A52,
>    PREFIX_EVEX_0F3A53,
> @@ -1237,6 +1256,8 @@ enum
>    PREFIX_EVEX_0F3A66,
>    PREFIX_EVEX_0F3A67,
>    PREFIX_EVEX_0F3A77_X86_64_W_0_L_2,
> +  PREFIX_EVEX_0F3A8D,
> +  PREFIX_EVEX_0F3A8F,
>    PREFIX_EVEX_0F3AC2,
> 
>    PREFIX_EVEX_MAP4_4x,
> @@ -1310,6 +1331,7 @@ enum
>    PREFIX_EVEX_MAP6_BA,
>    PREFIX_EVEX_MAP6_BC,
>    PREFIX_EVEX_MAP6_BE,
> +  PREFIX_EVEX_MAP6_95,
>    PREFIX_EVEX_MAP6_D6,
>    PREFIX_EVEX_MAP6_D7,
>  };
> @@ -1601,6 +1623,7 @@ enum
>    EVEX_LEN_0F381B,
>    EVEX_LEN_0F3836,
>    EVEX_LEN_0F384A_X86_64_W_0,
> +  EVEX_LEN_0F384B,
>    EVEX_LEN_0F385A,
>    EVEX_LEN_0F385B,
>    EVEX_LEN_0F386D_X86_64_W_0,
> @@ -1625,6 +1648,7 @@ enum
>    EVEX_LEN_MAP5_7E,
>    EVEX_LEN_MAP6_80_W_0,
>    EVEX_LEN_MAP6_80_W_1,
> +  EVEX_LEN_MAP6_95_P_0_W_1,
>  };
> 
>  enum
> @@ -1884,6 +1908,9 @@ enum
>    EVEX_W_MAP5_7E_P_1,
>    EVEX_W_MAP6_80,
>    EVEX_W_MAP6_81,
> +  EVEX_W_MAP6_95_P_0,
> +  EVEX_W_MAP6_95_P_1,
> +  EVEX_W_MAP6_95_P_3,
>  };
> 
>  typedef bool (*op_rtn) (instr_info *ins, int bytemode, int sizeflag); @@ -2709,6
> +2736,10 @@ static const char att_names_tmm[][8] = {
>    "%tmm4", "%tmm5", "%tmm6", "%tmm7"
>  };
> 
> +static const char att_names_bsr[][8] = {
> +  "%bsr0"
> +};
> +
>  static const char att_names_mask[][8] = {
>    "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
>  };
> @@ -3095,6 +3126,10 @@ static const struct dis386 reg_table[][8] = {
>    {
>      { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0) },
>    },
> +  /* REG_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3 */  {
> +    { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3_R_0) },  },
>    /* REG_VEX_0F38F3_L_0_P_0 */
>    {
>      { Bad_Opcode },
> @@ -4176,6 +4211,14 @@ static const struct dis386 prefix_table[][4] = {
>      { "tileloaddrs",	{ TMM, MVexSIBMEM }, 0 },
>    },
> 
> +  /* PREFIX_VEX_0F3849_X86_64_L_0_W_1_M_1 */  {
> +    { Bad_Opcode },
> +    { Bad_Opcode },
> +    { Bad_Opcode },
> +    { REG_TABLE (REG_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3) },  },
> +
>    /* PREFIX_VEX_0F384B_X86_64_L_0_W_0 */
>    {
>      { Bad_Opcode },
> @@ -8107,6 +8150,7 @@ static const struct dis386 vex_w_table[][2] = {
>    {
>      /* VEX_W_0F3849_X86_64_L_0 */
>      { MOD_TABLE (MOD_VEX_0F3849_X86_64_L_0_W_0) },
> +    { MOD_TABLE (MOD_VEX_0F3849_X86_64_L_0_W_1) },
>    },
>    {
>      /* VEX_W_0F384A_X86_64 */
> @@ -8683,6 +8727,11 @@ static const struct dis386 mod_table[][2] = {
>      { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) },
>      { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1) },
>    },
> +  {
> +    /* MOD_VEX_0F3849_X86_64_L_0_W_1 */
> +    { Bad_Opcode },
> +    { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_1_M_1) },  },
> 
>  #include "i386-dis-evex-mod.h"
>  };
> @@ -8793,6 +8842,10 @@ static const struct dis386 rm_table[][8] = {
>      /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3 */
>      { "tilezero",	{ TMM, Skip_MODRM }, 0 },
>    },
> +  {
> +    /* RM_VEX_0F3849_X86_64_L_0_W_1_M_1_P_3_R_0 */
> +    { "bsrinit",	{ BSR, Skip_MODRM }, 0 },
> +  },
>  };
> 
>  #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
> @@ -11920,6 +11973,9 @@ intel_operand_size (instr_info *ins, int bytemode,
> int sizeflag)
>      case ymm_mode:
>        oappend (ins, "YMMWORD PTR ");
>        break;
> +    case zmm_mode:
> +      oappend (ins, "ZMMWORD PTR ");
> +      break;
>      case xmmq_mode:
>      case evex_half_bcst_xmmqh_mode:
>      case evex_half_bcst_xmmq_mode:
> @@ -12357,6 +12413,9 @@ OP_E_memory (instr_info *ins, int bytemode, int
> sizeflag)
>  	  else if (bytemode == xmmdw_mode)
>  	    shift -= 3;
>  	  break;
> +	case zmm_mode:
> +	  shift = 6;
> +	  break;

These lines may decode bsrmovh 0x40(%rax), %bsr0 incorrectly. Please verify the disp8 round-trip and add those tests.

>  	case ymm_mode:
>  	  shift = 5;
>  	  break;
> @@ -13407,6 +13466,8 @@ print_vector_reg (instr_info *ins, unsigned int reg,
> int bytemode)
>  	  abort ();
>  	}
>      }
> +  else if (bytemode == zmm_mode)
> +    names = att_names_zmm;
>    else if (bytemode == ymm_mode)
>      names = att_names_ymm;
>    else if (bytemode == tmm_mode)
> @@ -13482,6 +13543,18 @@ OP_XMM (instr_info *ins, int bytemode, int sizeflag
> ATTRIBUTE_UNUSED)
>    return true;
>  }
> 
> +static bool
> +OP_BSR (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, int sizeflag
> +ATTRIBUTE_UNUSED) {
> +  if (ins->modrm.reg)
> +    {
> +      oappend (ins, "(bad)");
> +      return false;

Should be return true, and can be merged into print_register, no need to define a new function.

> +    }
> +  oappend_register (ins, att_names_bsr[0]);
> +  return true;
> +}
> +
>  static bool
>  OP_EM (instr_info *ins, int bytemode, int sizeflag)  { @@ -14252,9 +14325,45
> @@ OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
>  	}
>        break;
>      case 512:
> -      names = att_names_zmm;
> -      ins->evex_used |= EVEX_len_used;
> -      break;
> +      switch (bytemode)
> +	{
> +	case x_mode:
> +	case v_mode:
> +	  names = att_names_zmm;
> +	  ins->evex_used |= EVEX_len_used;
> +	  break;
> +	case dq_mode:
> +	  if (ins->rex & REX_W)
> +	    names = att_names64;
> +	  else if (bytemode == v_mode
> +		   && !(sizeflag & DFLAG))
> +	    names = att_names16;
> +	  else
> +	    names = att_names32;
> +	  break;
> +	case b_mode:
> +	  names = att_names8rex;
> +	  break;
> +	case d_mode:
> +	  names = att_names32;
> +	  break;
> +	case q_mode:
> +	  names = att_names64;
> +	  break;
> +	case mask_bd_mode:
> +	case mask_mode:
> +	  if (reg > 0x7)
> +	    {
> +	      oappend (ins, "(bad)");
> +	      return true;
> +	    }
> +	  names = att_names_mask;
> +	  break;
> +	default:
> +	  abort ();
> +	  return true;
> +	}
> +	break;
>      default:
>        abort ();
>        break;
> diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c index
> 11cc4ff19dc..dded2d906e6 100644
> --- a/opcodes/i386-gen.c
> +++ b/opcodes/i386-gen.c
> @@ -263,6 +263,8 @@ static const dependency isa_dependencies[] =
>      "RTM|HLE" },
>    { "TSXLDTRK",
>      "RTM" },
> +  { "ACE",
> +    "AVX512F|64" },
>    { "AMX_TILE",
>      "XSAVE|64" },
>    { "AMX_INT8",
> @@ -470,6 +472,7 @@ static bitfield cpu_flags[] =
>    BITFIELD (WAITPKG),
>    BITFIELD (UINTR),
>    BITFIELD (CLDEMOTE),
> +  BITFIELD (ACE),
>    BITFIELD (AMX_INT8),
>    BITFIELD (AMX_BF16),
>    BITFIELD (AMX_FP16),
> @@ -571,6 +574,7 @@ static const struct {
>    CLASS (RegSIMD),
>    CLASS (RegMask),
>    CLASS (RegBND),
> +  CLASS (RegBS),
>  };
> 
>  #undef CLASS
> diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index
> 0c5f7747ed2..a8d9ac59c8b 100644
> --- a/opcodes/i386-opc.h
> +++ b/opcodes/i386-opc.h
> @@ -359,6 +359,8 @@ enum i386_cpu
>    CpuAVX10_2,
>    /* Intel AMX-TRANSPOSE Instructions support required.  */
>    CpuAMX_TRANSPOSE,
> +  /* ACE instructions support required.  */  CpuACE,
>    /* Not supported in the 64bit mode  */
>    CpuNo64,
> 
> @@ -397,6 +399,7 @@ enum i386_cpu
>  		   cpuapx_f:1, \
>  		   cpuavx10_2:1, \
>  		   cpuamx_transpose:1, \
> +		   cpuace:1, \
>        /* NOTE: This field needs to remain last. */ \
>  		   cpuno64:1
> 
> @@ -889,6 +892,7 @@ enum operand_class
>    RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
>    RegMask, /* Vector Mask register */
>    RegBND, /* Bound register */
> +  RegBS, /* Block scale register */
>  };
> 
>  /* Special operand instances.  */
> diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index
> 3d3e37b09aa..b85afcf5720 100644
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -62,6 +62,8 @@
> 
>  #define RegBND Class=RegBND
> 
> +#define RegBS Class=RegBS
> +
>  #define Mmword Qword
>  #define Oword  Xmmword
> 
> @@ -118,6 +120,7 @@
>  #define SpaceXOP0A OpcodeSpace=SPACE_XOP0A
> 
>  #define EVexMap4 OpcodeSpace=SPACE_MAP4|EVex128
> +#define EVexMap6 OpcodeSpace=SPACE_MAP6

You can use Map6 directly.

> 
>  #define Map5 OpcodeSpace=SPACE_MAP5
>  #define Map6 OpcodeSpace=SPACE_MAP6
> @@ -3234,10 +3237,12 @@ xresldtrk, 0xf20f01e9, TSXLDTRK, NoSuf, {}
> 
>  // TSXLDTRK instructions end.
> 
> -// AMX instructions.
> +// AMX & ACE instructions.
> 
>  ldtilecfg, 0x49/0, APX_F(AMX_TILE),
> Modrm|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex }
> +ldtilecfg, 0x49/0, ACE, Modrm|Vex128|Space0F38|VexW0|NoSuf, {
> +Unspecified|BaseIndex }
>  sttilecfg, 0x6649/0, APX_F(AMX_TILE),
> Modrm|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex }
> +sttilecfg, 0x6649/0, ACE, Modrm|Vex128|Space0F38|VexW0|NoSuf, {
> +Unspecified|BaseIndex }
> 
>  tcmmimfp16ps, 0x666c, AMX_COMPLEX,
> Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM,
> RegTMM }  tcmmrlfp16ps, 0x6c, AMX_COMPLEX,
> Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM,
> RegTMM } @@ -3250,14 +3255,18 @@ tdpbusd, 0x665e, AMX_INT8,
> Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf, { RegTMM  tdpbsud,
> 0xf35e, AMX_INT8, Modrm|Vex128|Space0F38|Src2VVVV|VexW0|NoSuf,
> { RegTMM, RegTMM, RegTMM }
> 
>  tileloadd, 0xf24b, APX_F(AMX_TILE),
> Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex,
> RegTMM }
> +tileloadd, 0xf24b, ACE, Sibmem|Vex128|Space0F38|VexW0|NoSuf, {
> +Unspecified|BaseIndex, RegTMM }
>  tileloaddt1, 0x664b, APX_F(AMX_TILE),
> Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex,
> RegTMM }
> +tileloaddt1, 0x664b, ACE, Sibmem|Vex128|Space0F38|VexW0|NoSuf, {
> +Unspecified|BaseIndex, RegTMM }
>  tileloaddrs, 0xf24a, APX_F(AMX_MOVRS),
> Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex,
> RegTMM }  tileloaddrst1, 0x664a, APX_F(AMX_MOVRS),
> Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex,
> RegTMM }  tilestored, 0xf34b, APX_F(AMX_TILE),
> Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { RegTMM,
> Unspecified|BaseIndex }
> +tilestored, 0xf34b, ACE, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { RegTMM,
> +Unspecified|BaseIndex }
> 
>  tilerelease, 0x49c0, AMX_TILE, Vex128|Space0F38|VexW0|NoSuf, {}
> +tilerelease, 0x49c0, ACE, Vex128|Space0F38|VexW0|NoSuf, {}
> 
> -tilezero, 0xf249, AMX_TILE, Modrm|Vex128|Space0F38|VexW0|NoSuf,
> { RegTMM }
> +tilezero, 0xf249, AMX_TILE|ACE, Modrm|Vex128|Space0F38|VexW0|NoSuf, {
> +RegTMM }
> 
>  <z:pfx, z0:, z1:66>
> 
> @@ -3288,22 +3297,51 @@ tdpbhf8ps, 0xf2fd, AMX_FP8,
> Modrm|Vex128|Map5|Src2VVVV|VexW0|NoSuf, { RegTMM, Re  tdphbf8ps,
> 0xf3fd, AMX_FP8, Modrm|Vex128|Map5|Src2VVVV|VexW0|NoSuf, { RegTMM,
> RegTMM, RegTMM }  tdphf8ps, 0x66fd, AMX_FP8,
> Modrm|Vex128|Map5|Src2VVVV|VexW0|NoSuf, { RegTMM, RegTMM,
> RegTMM }
> 
> -tcvtrowd2ps, 0xf34a, AMX_AVX512,
> Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM,
> RegZMM } -tcvtrowd2ps, 0xf307, AMX_AVX512,
> Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
> +tcvtrowd2ps, 0xf34a, AMX_AVX512|ACE,
> +Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM,
> RegZMM }
> +tcvtrowd2ps, 0xf307, AMX_AVX512|ACE,
> +Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
> +
> +tcvtrowps2bf16h, 0xf26d, AMX_AVX512|ACE,
> +Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM,
> RegZMM }
> +tcvtrowps2bf16h, 0xf207, AMX_AVX512|ACE,
> +Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
> +tcvtrowps2bf16l, 0xf36d, AMX_AVX512|ACE,
> +Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM,
> RegZMM }
> +tcvtrowps2bf16l, 0xf377, AMX_AVX512|ACE,
> +Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
> +tcvtrowps2phh, 0x6d, AMX_AVX512|ACE,
> +Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM,
> RegZMM }
> +tcvtrowps2phh, 0x07, AMX_AVX512|ACE,
> +Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
> +tcvtrowps2phl, 0x666d, AMX_AVX512|ACE,
> +Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM,
> RegZMM }
> +tcvtrowps2phl, 0xf277, AMX_AVX512|ACE,
> +Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
> +
> +tilemovrow, 0x664a, AMX_AVX512|ACE,
> +Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM,
> RegZMM }
> +tilemovrow, 0x6607, AMX_AVX512|ACE,
> +Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
> +
> +// AMX & ACE instructions end.
> +
> +// ACE instructions.
> +
> +bsrinit, 0xf249, ACE, Modrm|Vex128|Space0F38|VexW1|NoSuf, { RegBS }
> +bsrmovf, 0x95, ACE, Modrm|EVex512|EVexMap6|VexW1|Src1VVVV|NoSuf, {
> +RegZMM|Unspecified|BaseIndex, RegZMM, RegBS } bsrmovh, 0xf295, ACE,
> +Modrm|EVex512|EVexMap6|VexW1|NoSuf,
> { RegZMM|Unspecified|BaseIndex,
> +RegBS } bsrmovh, 0xf295, ACE,
> +RegMem|Modrm|EVex512|EVexMap6|VexW0|NoSuf, { RegBS,

RegMem is redundant here: another operand has BaseIndex, which already steers it into the r/m slot.

BRs,
Lin

> +RegZMM|Unspecified|BaseIndex } bsrmovl, 0xf395, ACE,
> +Modrm|EVex512|EVexMap6|VexW1|NoSuf,
> { RegZMM|Unspecified|BaseIndex,
> +RegBS } bsrmovl, 0xf395, ACE,
> +RegMem|Modrm|EVex512|EVexMap6|VexW0|NoSuf, { RegBS,
> +RegZMM|Unspecified|BaseIndex }
> +
> +tilemovcol, 0x662f, ACE, Modrm|EVex512|Space0F3A|VexW1|NoSuf, { Imm8,
> +RegZMM, RegTMM } tilemovcol, 0x664b, ACE,
> +Modrm|EVex512|Space0F38|VexW1|Src2VVVV|NoSuf, { Reg32, RegZMM,
> RegTMM }
> +tilemovrow, 0x6607, ACE, Modrm|EVex512|Space0F3A|VexW1|NoSuf, { Imm8,
> +RegZMM, RegTMM } tilemovrow, 0x664a, ACE,
> +Modrm|EVex512|Space0F38|VexW1|Src2VVVV|NoSuf, { Reg32, RegZMM,
> RegTMM }
> +
> +top2bf16ps, 0xf35c, ACE,
> Modrm|EVex512|Space0F38|VexW0|Src2VVVV|NoSuf,
> +{ RegZMM, RegZMM, RegTMM }
> 
> -tcvtrowps2bf16h, 0xf26d, AMX_AVX512,
> Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM,
> RegZMM } -tcvtrowps2bf16h, 0xf207, AMX_AVX512,
> Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM } -
> tcvtrowps2bf16l, 0xf36d, AMX_AVX512,
> Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM,
> RegZMM } -tcvtrowps2bf16l, 0xf377, AMX_AVX512,
> Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM } -
> tcvtrowps2phh, 0x6d, AMX_AVX512,
> Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM,
> RegZMM } -tcvtrowps2phh, 0x07, AMX_AVX512,
> Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM } -
> tcvtrowps2phl, 0x666d, AMX_AVX512,
> Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM,
> RegZMM } -tcvtrowps2phl, 0xf277, AMX_AVX512,
> Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
> +top4bssd, 0xf25e, ACE, Modrm|EVex512|Space0F38|VexW0|Src2VVVV|NoSuf,
> {
> +RegZMM, RegZMM, RegTMM } top4bsud, 0xf35e, ACE,
> +Modrm|EVex512|Space0F38|VexW0|Src2VVVV|NoSuf, { RegZMM, RegZMM,
> RegTMM
> +} top4busd, 0x665e, ACE,
> Modrm|EVex512|Space0F38|VexW0|Src2VVVV|NoSuf,
> +{ RegZMM, RegZMM, RegTMM } top4buud, 0x5e, ACE,
> +Modrm|EVex512|Space0F38|VexW0|Src2VVVV|NoSuf, { RegZMM, RegZMM,
> RegTMM
> +}
> 
> -tilemovrow, 0x664a, AMX_AVX512,
> Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM,
> RegZMM } -tilemovrow, 0x6607, AMX_AVX512,
> Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
> +top4mxbf8ps, 0x8d, ACE,
> Modrm|EVex512|Space0F3A|VexW0|Src2VVVV|NoSuf, {
> +Imm8, RegZMM, RegZMM, RegTMM } top4mxbhf8ps, 0xf28d, ACE,
> +Modrm|EVex512|Space0F3A|VexW0|Src2VVVV|NoSuf, { Imm8, RegZMM,
> RegZMM,
> +RegTMM } top4mxhbf8ps, 0xf38d, ACE,
> +Modrm|EVex512|Space0F3A|VexW0|Src2VVVV|NoSuf, { Imm8, RegZMM,
> RegZMM,
> +RegTMM } top4mxhf8ps, 0x668d, ACE,
> +Modrm|EVex512|Space0F3A|VexW0|Src2VVVV|NoSuf, { Imm8, RegZMM,
> RegZMM,
> +RegTMM } top4mxbssps, 0xf28f, ACE,
> +Modrm|EVex512|Space0F3A|VexW0|Src2VVVV|NoSuf, { Imm8, RegZMM,
> RegZMM,
> +RegTMM }
> 
> -// AMX instructions end.
> +// ACE instructions end.
> 
>  // KEYLOCKER instructions.
> 
> diff --git a/opcodes/i386-reg.tbl b/opcodes/i386-reg.tbl index
> 74234c503d6..ee6923252c9 100644
> --- a/opcodes/i386-reg.tbl
> +++ b/opcodes/i386-reg.tbl
> @@ -344,7 +344,7 @@ zmm28, Class=RegSIMD|Zmmword, RegVRex|RegRex, 4,
> Dw2Inval, 79  zmm29, Class=RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval,
> 80  zmm30, Class=RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, 81
> zmm31, Class=RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, 82 -// TMM
> registers for AMX
> +// TMM registers for AMX/ACE
>  tmm0, Class=RegSIMD|Tmmword, 0, 0, Dw2Inval, Dw2Inval  tmm1,
> Class=RegSIMD|Tmmword, 0, 1, Dw2Inval, Dw2Inval  tmm2,
> Class=RegSIMD|Tmmword, 0, 2, Dw2Inval, Dw2Inval @@ -353,6 +353,8 @@
> tmm4, Class=RegSIMD|Tmmword, 0, 4, Dw2Inval, Dw2Inval  tmm5,
> Class=RegSIMD|Tmmword, 0, 5, Dw2Inval, Dw2Inval  tmm6,
> Class=RegSIMD|Tmmword, 0, 6, Dw2Inval, Dw2Inval  tmm7,
> Class=RegSIMD|Tmmword, 0, 7, Dw2Inval, Dw2Inval
> +// Block scale register for ACE
> +bsr0, Class=RegBS, 0, 0, Dw2Inval, Dw2Inval
>  // Bound registers for MPX
>  bnd0, Class=RegBND, 0, 0, Dw2Inval, 126  bnd1, Class=RegBND, 0, 1, Dw2Inval,
> 127
> --
> 2.53.0


From jiawei@iscas.ac.cn  Tue Jun 30 03:34:37 2026
From: jiawei@iscas.ac.cn (Jiawei)
Date: Tue, 30 Jun 2026 11:34:37 +0800
Subject: [PATCH 1/2] RISC-V: Add Zvdota extension classes
Message-ID: <20260630033438.143289-1-jiawei@iscas.ac.cn>

This patch adds assembler/disassembler support for the RISC-V Zvdota family of extensions [1], which compute a dot product between two vector register groups.

The Zvdota extension family includes the following extensions:

Zvqwdota8i: dot product of 8-bit integers with 32-bit accumulation.
Zvqwdota16i: dot product of 16-bit integers with 64-bit accumulation.
Zvfwdota16bf: dot product of bfloat16 floating-point numbers with 32-bit accumulation.
Zvfqwdota8f: dot product of 8-bit floating-point numbers with 32-bit accumulation.

Zvdota also uses the vtype alternative format bit, altfmt, which is bit 8 of the vtype CSR. This patch adds symbolic e8alt and e16alt vsew constants for vsetvli/vsetivli so that assembly code can select the alternative element formats required by these dot-product instructions.

[1] https://github.com/riscv/riscv-isa-manual/blob/zvbdot/src/zvdota.adoc

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): New implies.
	(riscv_supported_std_z_ext): New extensions.
	(riscv_multi_subset_supports): Ditto.
	(riscv_multi_subset_supports_ext): Ditto.

gas/ChangeLog:

	* NEWS: Add zvqwdota8i, zvqwdota16i, zvfwdota16bf and
	zvfqwdota8f extensions.
	* config/tc-riscv.c (riscv_vsew_altfmt): New vsew altfmt
	constants array for e8alt and e16alt.
	(riscv_vtype_altfmt_supported): New function.
	(my_getVsetvliExpression): Ditto.
	* testsuite/gas/riscv/march-help.l: New test.
	* testsuite/gas/riscv/vector-vtype-altfmt.d: Ditto.
	* testsuite/gas/riscv/vector-vtype-altfmt.s: Ditto.
	* testsuite/gas/riscv/zvdota.d: Ditto.
	* testsuite/gas/riscv/zvdota.s: Ditto.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VQWDOTAU_VV, MASK_VQWDOTAU_VV): New encoding.
	(MATCH_VQWDOTAS_VV, MASK_VQWDOTAS_VV): Ditto.
	(MATCH_VFWDOTA_VV, MASK_VFWDOTA_VV): Ditto.
	(MATCH_VFQWDOTA_VV, MASK_VFQWDOTA_VV): Ditto.
	(MATCH_VFQWDOTA_ALT_VV, MASK_VFQWDOTA_ALT_VV): Ditto.
	(DECLARE_INSN): New declarations.
	* opcode/riscv.h (OP_MASK_VTYPE_ALTFMT, OP_SH_VTYPE_ALTFMT): New vtype altfmt.
	(enum riscv_insn_class): New extension classes.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Add altfmt support.
	* riscv-opc.c (riscv_opcodes): New instructions.
---
 bfd/elfxx-riscv.c                             | 29 +++++++++++++++++
 gas/NEWS                                      |  3 +-
 gas/config/tc-riscv.c                         | 32 +++++++++++++++++--
 gas/testsuite/gas/riscv/march-help.l          |  4 +++
 gas/testsuite/gas/riscv/vector-vtype-altfmt.d | 15 +++++++++
 gas/testsuite/gas/riscv/vector-vtype-altfmt.s |  7 ++++
 gas/testsuite/gas/riscv/zvdota.d              | 19 +++++++++++
 gas/testsuite/gas/riscv/zvdota.s              | 11 +++++++
 include/opcode/riscv-opc.h                    | 17 ++++++++++
 include/opcode/riscv.h                        |  8 +++++
 opcodes/riscv-dis.c                           | 10 ++++--
 opcodes/riscv-opc.c                           | 13 ++++++++
 12 files changed, 162 insertions(+), 6 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/vector-vtype-altfmt.d
 create mode 100644 gas/testsuite/gas/riscv/vector-vtype-altfmt.s
 create mode 100644 gas/testsuite/gas/riscv/zvdota.d
 create mode 100644 gas/testsuite/gas/riscv/zvdota.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 961c44a9206..44bdb5f2a99 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1239,6 +1239,10 @@ static const struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zvfhmin", "+zve32f", check_implicit_always},
   {"zvfbfwma", "+zve32f,+zfbfmin", check_implicit_always},
   {"zvfbfmin", "+zve32f", check_implicit_always},
+  {"zvfqwdota8f", "+zve32f", check_implicit_always},
+  {"zvfwdota16bf", "+zve32f", check_implicit_always},
+  {"zvqwdota8i", "+zve32x", check_implicit_always},
+  {"zvqwdota16i", "+zve64x", check_implicit_always},
   {"zve64d", "+d,+zve64f", check_implicit_always},
   {"zve64f", "+zve32f,+zve64x,+zvl64b", check_implicit_always},
   {"zve32f", "+f,+zve32x,+zvl32b", check_implicit_always},
@@ -1524,6 +1528,8 @@ static const struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvfbfwma",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvfh",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvfhmin",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"zvfqwdota8f",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"zvfwdota16bf",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvkb",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvkg",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvkn",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
@@ -1538,6 +1544,8 @@ static const struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvksg",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvksc",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvkt",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"zvqwdota8i",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"zvqwdota16i",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvl64b",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvl128b",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
@@ -2985,6 +2993,10 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zvfbfmin");
     case INSN_CLASS_ZVFBFWMA:
       return riscv_subset_supports (rps, "zvfbfwma");
+    case INSN_CLASS_ZVFQWDOTA8F:
+      return riscv_subset_supports (rps, "zvfqwdota8f");
+    case INSN_CLASS_ZVFWDOTA16BF:
+      return riscv_subset_supports (rps, "zvfwdota16bf");
     case INSN_CLASS_ZVKB:
       return riscv_subset_supports (rps, "zvkb");
     case INSN_CLASS_ZVKG:
@@ -2998,6 +3010,13 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zvksed");
     case INSN_CLASS_ZVKSH:
       return riscv_subset_supports (rps, "zvksh");
+    case INSN_CLASS_ZVQWDOTA8I:
+      return riscv_subset_supports (rps, "zvqwdota8i");
+    case INSN_CLASS_ZVQWDOTA16I:
+      return riscv_subset_supports (rps, "zvqwdota16i");
+    case INSN_CLASS_ZVQWDOTA8I_OR_ZVQWDOTA16I:
+      return (riscv_subset_supports (rps, "zvqwdota8i")
+	      || riscv_subset_supports (rps, "zvqwdota16i"));
     case INSN_CLASS_ZCB:
       return riscv_subset_supports (rps, "zcb");
     case INSN_CLASS_ZCB_AND_ZBB:
@@ -3312,6 +3331,10 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "zvfbfmin";
     case INSN_CLASS_ZVFBFWMA:
       return "zvfbfwma";
+    case INSN_CLASS_ZVFQWDOTA8F:
+      return "zvfqwdota8f";
+    case INSN_CLASS_ZVFWDOTA16BF:
+      return "zvfwdota16bf";
     case INSN_CLASS_ZVKB:
       return _("zvkb");
     case INSN_CLASS_ZVKG:
@@ -3324,6 +3347,12 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zvksed");
     case INSN_CLASS_ZVKSH:
       return _("zvksh");
+    case INSN_CLASS_ZVQWDOTA8I:
+      return "zvqwdota8i";
+    case INSN_CLASS_ZVQWDOTA16I:
+      return "zvqwdota16i";
+    case INSN_CLASS_ZVQWDOTA8I_OR_ZVQWDOTA16I:
+      return _("zvqwdota8i' or `zvqwdota16i");
     case INSN_CLASS_ZCB:
       return "zcb";
     case INSN_CLASS_ZCB_AND_ZBA:
diff --git a/gas/NEWS b/gas/NEWS
index 4c55a544f25..c3e254689e0 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -6,7 +6,8 @@
   and will be removed in a future release.
 
 * Add support for RISC-V standard extensions:
-  zalasr v1.0, svrsw60t59b v1.0, zvabd v1.0, smpmpmt v1.0.
+  zalasr v1.0, svrsw60t59b v1.0, zvabd v1.0, smpmpmt v1.0,
+  zvqwdota8i, zvqwdota16i, zvfwdota16bf and zvfqwdota8f v1.0.
 
 * Add support for RISC-V vendor extensions:
   SpacemiT: xsmtvdot v1.0, xsmtvdotii v1.0.
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 28875e77ff0..53cc234cde4 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -2692,15 +2692,40 @@ my_getOpcodeExpression (expressionS *ep, bfd_reloc_code_real_type *reloc,
    On exit, EXPR_PARSE_END points to the first character after the
    expression.  */
 
+static bool
+riscv_vtype_altfmt_supported (void)
+{
+  return (riscv_subset_supports (&riscv_rps_as, "zvfbfa")
+	  || riscv_subset_supports (&riscv_rps_as, "zvfofp8min")
+	  || riscv_subset_supports (&riscv_rps_as, "zvfqwdota8f")
+	  || riscv_subset_supports (&riscv_rps_as, "zvfwdota16bf")
+	  || riscv_subset_supports (&riscv_rps_as, "zvqwdota8i")
+	  || riscv_subset_supports (&riscv_rps_as, "zvqwdota16i"));
+}
+
 static void
 my_getVsetvliExpression (expressionS *ep, char *str)
 {
   unsigned int vsew_value = 0, vlmul_value = 0;
-  unsigned int vta_value = 0, vma_value = 0;
+  unsigned int vta_value = 0, vma_value = 0, altfmt_value = 0;
   bool vsew_found = false, vlmul_found = false;
   bool vta_found = false, vma_found = false;
 
-  if (arg_lookup (&str, riscv_vsew, ARRAY_SIZE (riscv_vsew), &vsew_value))
+  if (arg_lookup (&str, riscv_vsew_altfmt,
+		  ARRAY_SIZE (riscv_vsew_altfmt), &vsew_value))
+    {
+      if (*str == ',')
+	++str;
+      if (vsew_found)
+	as_bad (_("multiple vsew constants"));
+      if (!riscv_vtype_altfmt_supported ())
+	as_bad (_("symbolic vtype altfmt requires `zvfbfa', "
+		  "`zvfofp8min' or a `zvdota' extension"));
+      altfmt_value = 1 << OP_SH_VTYPE_ALTFMT;
+      vsew_found = true;
+    }
+  if (!vsew_found
+      && arg_lookup (&str, riscv_vsew, ARRAY_SIZE (riscv_vsew), &vsew_value))
     {
       if (*str == ',')
 	++str;
@@ -2739,7 +2764,8 @@ my_getVsetvliExpression (expressionS *ep, char *str)
       ep->X_add_number = (vlmul_value << OP_SH_VLMUL)
 			 | (vsew_value << OP_SH_VSEW)
 			 | (vta_value << OP_SH_VTA)
-			 | (vma_value << OP_SH_VMA);
+			 | (vma_value << OP_SH_VMA)
+			 | altfmt_value;
       expr_parse_end = str;
     }
   else
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index db6a86bc287..2b5efe808d6 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -76,6 +76,8 @@ All available -march extensions for RISC-V:
 	zvfbfwma                                1.0
 	zvfh                                    1.0
 	zvfhmin                                 1.0
+	zvfqwdota8f                             1.0
+	zvfwdota16bf                            1.0
 	zvkb                                    1.0
 	zvkg                                    1.0
 	zvkn                                    1.0
@@ -90,6 +92,8 @@ All available -march extensions for RISC-V:
 	zvksg                                   1.0
 	zvksc                                   1.0
 	zvkt                                    1.0
+	zvqwdota8i                              1.0
+	zvqwdota16i                             1.0
 	zvl32b                                  1.0
 	zvl64b                                  1.0
 	zvl128b                                 1.0
diff --git a/gas/testsuite/gas/riscv/vector-vtype-altfmt.d b/gas/testsuite/gas/riscv/vector-vtype-altfmt.d
new file mode 100644
index 00000000000..398f7682a91
--- /dev/null
+++ b/gas/testsuite/gas/riscv/vector-vtype-altfmt.d
@@ -0,0 +1,15 @@
+#as: -march=rv64gc_zvfqwdota8f
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+10707057[ 	]+vsetvli[ 	]+zero,zero,e8alt,mf2,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+10707057[ 	]+vsetvli[ 	]+zero,zero,e8alt,mf2,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+10707057[ 	]+vsetvli[ 	]+zero,zero,e8alt,mf2,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+10f07057[ 	]+vsetvli[ 	]+zero,zero,e16alt,mf2,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+10f07057[ 	]+vsetvli[ 	]+zero,zero,e16alt,mf2,tu,mu
+[ 	]+[0-9a-f]+:[ 	]+10f07057[ 	]+vsetvli[ 	]+zero,zero,e16alt,mf2,tu,mu
diff --git a/gas/testsuite/gas/riscv/vector-vtype-altfmt.s b/gas/testsuite/gas/riscv/vector-vtype-altfmt.s
new file mode 100644
index 00000000000..de8418236f1
--- /dev/null
+++ b/gas/testsuite/gas/riscv/vector-vtype-altfmt.s
@@ -0,0 +1,7 @@
+target:
+	vsetvli zero, zero, e8alt, mf2, tu, mu
+	vsetvli zero, zero, e8alt, mf2, tu, mu
+	vsetvli zero, zero, e8alt, mf2, tu, mu
+	vsetvli zero, zero, e16alt, mf2, tu, mu
+	vsetvli zero, zero, e16alt, mf2, tu, mu
+	vsetvli zero, zero, e16alt, mf2, tu, mu
diff --git a/gas/testsuite/gas/riscv/zvdota.d b/gas/testsuite/gas/riscv/zvdota.d
new file mode 100644
index 00000000000..8d133255993
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvdota.d
@@ -0,0 +1,19 @@
+#as: -march=rv64gc_zvqwdota8i_zvqwdota16i_zvfwdota16bf_zvfqwdota8f
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+9a8f8877[ 	]+vqwdotau.vv[ 	]+v16,v8,v31
+[ 	]+[0-9a-f]+:[ 	]+9e8f8877[ 	]+vqwdotas.vv[ 	]+v16,v8,v31
+[ 	]+[0-9a-f]+:[ 	]+928f9877[ 	]+vfwdota.vv[ 	]+v16,v8,v31
+[ 	]+[0-9a-f]+:[ 	]+9a8f9877[ 	]+vfqwdota.vv[ 	]+v16,v8,v31
+[ 	]+[0-9a-f]+:[ 	]+9e8f9877[ 	]+vfqwdota.alt.vv[ 	]+v16,v8,v31
+[ 	]+[0-9a-f]+:[ 	]+988f8877[ 	]+vqwdotau.vv[ 	]+v16,v8,v31
+[ 	]+[0-9a-f]+:[ 	]+9c8f8877[ 	]+vqwdotas.vv[ 	]+v16,v8,v31
+[ 	]+[0-9a-f]+:[ 	]+928f9877[ 	]+vfwdota.vv[ 	]+v16,v8,v31
+[ 	]+[0-9a-f]+:[ 	]+980f9877[ 	]+vfqwdota.vv[ 	]+v16,v0,v31,v0.t
+[ 	]+[0-9a-f]+:[ 	]+9c0f9877[ 	]+vfqwdota.alt.vv[ 	]+v16,v0,v31,v0.t
diff --git a/gas/testsuite/gas/riscv/zvdota.s b/gas/testsuite/gas/riscv/zvdota.s
new file mode 100644
index 00000000000..a40453faf82
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvdota.s
@@ -0,0 +1,11 @@
+target:
+	vqwdotau.vv v16, v8, v31
+	vqwdotas.vv v16, v8, v31
+	vfwdota.vv v16, v8, v31
+	vfqwdota.vv v16, v8, v31
+	vfqwdota.alt.vv v16, v8, v31
+	vqwdotau.vv v16, v8, v31, v0.t
+	vqwdotas.vv v16, v8, v31, v0.t
+	vfwdota.vv v16, v8, v31, v0.t
+	vfqwdota.vv v16, v0, v31, v0.t
+	vfqwdota.alt.vv v16, v0, v31, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index eebf8f2a435..812f24c083c 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2577,6 +2577,17 @@
 #define MASK_VFWMACCBF16_VF 0xfc00707f
 #define MATCH_VFWMACCBF16_VV 0xec001057
 #define MASK_VFWMACCBF16_VV 0xfc00707f
+/* Zvdota instructions.  */
+#define MATCH_VQWDOTAU_VV 0x98000077
+#define MASK_VQWDOTAU_VV 0xfc00707f
+#define MATCH_VQWDOTAS_VV 0x9c000077
+#define MASK_VQWDOTAS_VV 0xfc00707f
+#define MATCH_VFWDOTA_VV 0x90001077
+#define MASK_VFWDOTA_VV 0xfc00707f
+#define MATCH_VFQWDOTA_VV 0x98001077
+#define MASK_VFQWDOTA_VV 0xfc00707f
+#define MATCH_VFQWDOTA_ALT_VV 0x9c001077
+#define MASK_VFQWDOTA_ALT_VV 0xfc00707f
 /* Vendor-specific (CORE-V) Xcvmac instructions.  */
 #define MATCH_CV_MAC       0x9000302b
 #define MASK_CV_MAC        0xfe00707f
@@ -4902,6 +4913,12 @@ DECLARE_INSN(VFWCVTBF16_F_F_V, MATCH_VFWCVTBF16_F_F_V, MASK_VFWCVTBF16_F_F_V)
 /* Zvfbfwma instructions.  */
 DECLARE_INSN(VFWMACCBF16_VF, MATCH_VFWMACCBF16_VF, MASK_VFWMACCBF16_VF)
 DECLARE_INSN(VFWMACCBF16_VV, MATCH_VFWMACCBF16_VV, MASK_VFWMACCBF16_VV)
+/* Zvdota instructions.  */
+DECLARE_INSN(vqwdotau_vv, MATCH_VQWDOTAU_VV, MASK_VQWDOTAU_VV)
+DECLARE_INSN(vqwdotas_vv, MATCH_VQWDOTAS_VV, MASK_VQWDOTAS_VV)
+DECLARE_INSN(vfwdota_vv, MATCH_VFWDOTA_VV, MASK_VFWDOTA_VV)
+DECLARE_INSN(vfqwdota_vv, MATCH_VFQWDOTA_VV, MASK_VFQWDOTA_VV)
+DECLARE_INSN(vfqwdota_alt_vv, MATCH_VFQWDOTA_ALT_VV, MASK_VFQWDOTA_ALT_VV)
 /* Zvbb/Zvkb instructions.  */
 DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV)
 DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index b4587976ea2..45b6c7979db 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -374,6 +374,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
 #define OP_SH_VTA		6
 #define OP_MASK_VMA		0x1
 #define OP_SH_VMA		7
+#define OP_MASK_VTYPE_ALTFMT	0x1
+#define OP_SH_VTYPE_ALTFMT	8
 #define OP_MASK_VWD		0x1
 #define OP_SH_VWD		26
 
@@ -560,6 +562,8 @@ enum riscv_insn_class
   INSN_CLASS_ZVBC,
   INSN_CLASS_ZVFBFMIN,
   INSN_CLASS_ZVFBFWMA,
+  INSN_CLASS_ZVFQWDOTA8F,
+  INSN_CLASS_ZVFWDOTA16BF,
   INSN_CLASS_ZVKB,
   INSN_CLASS_ZVKG,
   INSN_CLASS_ZVKNED,
@@ -567,6 +571,9 @@ enum riscv_insn_class
   INSN_CLASS_ZVKSED,
   INSN_CLASS_ZVKSH,
   INSN_CLASS_ZVABD,
+  INSN_CLASS_ZVQWDOTA8I,
+  INSN_CLASS_ZVQWDOTA16I,
+  INSN_CLASS_ZVQWDOTA8I_OR_ZVQWDOTA16I,
   INSN_CLASS_ZICFISS,
   INSN_CLASS_ZICFISS_AND_ZCMOP,
   INSN_CLASS_ZICFILP,
@@ -737,6 +744,7 @@ extern const char * const riscv_pred_succ[16];
 extern const char riscv_vecr_names_numeric[NVECR][NRC];
 extern const char riscv_vecm_names_numeric[NVECM][NRC];
 extern const char * const riscv_vsew[8];
+extern const char * const riscv_vsew_altfmt[2];
 extern const char * const riscv_vlmul[8];
 extern const char * const riscv_vta[2];
 extern const char * const riscv_vma[2];
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index edb9ce04778..86dbdb18456 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -453,17 +453,23 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 		unsigned int imm_vsew = EXTRACT_OPERAND (VSEW, imm);
 		unsigned int imm_vta = EXTRACT_OPERAND (VTA, imm);
 		unsigned int imm_vma = EXTRACT_OPERAND (VMA, imm);
-		unsigned int imm_vtype_res = (imm >> 8);
+		unsigned int imm_vtype_altfmt
+		  = EXTRACT_OPERAND (VTYPE_ALTFMT, imm);
+		unsigned int imm_vtype_res = (imm >> 9);
 
 		if (imm_vsew < ARRAY_SIZE (riscv_vsew)
 		    && imm_vlmul < ARRAY_SIZE (riscv_vlmul)
 		    && imm_vta < ARRAY_SIZE (riscv_vta)
 		    && imm_vma < ARRAY_SIZE (riscv_vma)
 		    && !imm_vtype_res
+		    && (imm_vtype_altfmt == 0
+			|| imm_vsew < ARRAY_SIZE (riscv_vsew_altfmt))
 		    && riscv_vsew[imm_vsew] != NULL
 		    && riscv_vlmul[imm_vlmul] != NULL)
 		  print (info->stream, dis_style_text, "%s,%s,%s,%s",
-			 riscv_vsew[imm_vsew],
+			 imm_vtype_altfmt
+			 ? riscv_vsew_altfmt[imm_vsew]
+			 : riscv_vsew[imm_vsew],
 			 riscv_vlmul[imm_vlmul], riscv_vta[imm_vta],
 			 riscv_vma[imm_vma]);
 		else
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 589495ac6c7..cfec774ecdb 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -93,6 +93,12 @@ const char * const riscv_vsew[8] =
   "e8", "e16", "e32", "e64", NULL, NULL, NULL, NULL
 };
 
+/* The vsetvli/vsetivli vsew altfmt constants.  */
+const char * const riscv_vsew_altfmt[2] =
+{
+  "e8alt", "e16alt"
+};
+
 /* The vsetvli vlmul constants.  */
 const char * const riscv_vlmul[8] =
 {
@@ -2244,6 +2250,13 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vfwmaccbf16.vf",  0, INSN_CLASS_ZVFBFWMA, "Vd,S,VtVm",  MATCH_VFWMACCBF16_VF, MASK_VFWMACCBF16_VF, match_opcode, 0},
 {"vfwmaccbf16.vv",  0, INSN_CLASS_ZVFBFWMA, "Vd,Vs,VtVm", MATCH_VFWMACCBF16_VV, MASK_VFWMACCBF16_VV, match_opcode, 0},
 
+/* Zvdota instructions.  */
+{"vqwdotau.vv", 0, INSN_CLASS_ZVQWDOTA8I_OR_ZVQWDOTA16I, "Vd,Vt,VsVm", MATCH_VQWDOTAU_VV, MASK_VQWDOTAU_VV, match_opcode, 0},
+{"vqwdotas.vv", 0, INSN_CLASS_ZVQWDOTA8I_OR_ZVQWDOTA16I, "Vd,Vt,VsVm", MATCH_VQWDOTAS_VV, MASK_VQWDOTAS_VV, match_opcode, 0},
+{"vfwdota.vv",  0, INSN_CLASS_ZVFWDOTA16BF, "Vd,Vt,VsVm", MATCH_VFWDOTA_VV, MASK_VFWDOTA_VV, match_opcode, 0},
+{"vfqwdota.vv", 0, INSN_CLASS_ZVFQWDOTA8F, "Vd,Vt,VsVm", MATCH_VFQWDOTA_VV, MASK_VFQWDOTA_VV, match_opcode, 0},
+{"vfqwdota.alt.vv", 0, INSN_CLASS_ZVFQWDOTA8F, "Vd,Vt,VsVm", MATCH_VFQWDOTA_ALT_VV, MASK_VFQWDOTA_ALT_VV, match_opcode, 0},
+
 /* Zvbb/Zvkb instructions.  */
 {"vandn.vv",   0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VANDN_VV, MASK_VANDN_VV, match_opcode, 0},
 {"vandn.vx",   0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VANDN_VX, MASK_VANDN_VX, match_opcode, 0},
-- 
2.43.0


From jiawei@iscas.ac.cn  Tue Jun 30 03:34:38 2026
From: jiawei@iscas.ac.cn (Jiawei)
Date: Tue, 30 Jun 2026 11:34:38 +0800
Subject: [PATCH 2/2] RISC-V: Add Zvbdota extension support
In-Reply-To: <20260630033438.143289-1-jiawei@iscas.ac.cn>
References: <20260630033438.143289-1-jiawei@iscas.ac.cn>
Message-ID: <20260630033438.143289-2-jiawei@iscas.ac.cn>

This patch supports the RISC-V Zvbdota family of batched dot-product
extensions [1].

Compared to the non-batched Zvdota family, Zvbdota computes up to eight
dot products at a time.  These instructions use an EMUL=8 `vs2` vector
register group and a scaled-by-8 `ci` immediate encoded in `vs2[2:0]`.
This patch adds assembler/disassembler support for those additional
operand constraints.

The Zvbdota extension family includes the following extensions:

* Zvqwbdota8i: batched dot product of 8-bit integers with 32-bit
  accumulation.
* Zvqwbdota16i: batched dot product of 16-bit integers with 64-bit
  accumulation.
* Zvfwbdota16bf: batched dot product of bfloat16 floating-point numbers
  with 32-bit accumulation.
* Zvfqwbdota8f: batched dot product of 8-bit floating-point numbers with
  32-bit accumulation.
* Zvfbdota32f: batched dot product of 32-bit single-precision
  floating-point numbers with 32-bit accumulation.

[1] https://github.com/riscv/riscv-isa-manual/blob/zvbdot/src/zvdota.adoc

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): New implies.
	(riscv_supported_std_z_ext): New extensions.
	(riscv_multi_subset_supports): Ditto.
	(riscv_multi_subset_supports_ext): Ditto.

gas/ChangeLog:

	* NEWS: Add zvqwbdota8i, zvqwbdota16i, zvfwbdota16bf,
	zvfqwbdota8f and zvfbdota32f extensions.
	* config/tc-riscv.c (validate_riscv_insn): Add Zvbdota operand
	type 'q' and 'r' bits validation.
	(riscv_vtype_altfmt_supported): Add Zvbdota extensions.
	(my_getVsetvliExpression): Update altfmt error message.
	(riscv_ip): Add 'q' operand for VS2 EMUL=8 alignment check
	and 'r' operand for ci immediate.
	* testsuite/gas/riscv/march-help.l: Ditto.
	* testsuite/gas/riscv/zvbdota.d: New test.
	* testsuite/gas/riscv/zvbdota.s: Ditto.
	* testsuite/gas/riscv/zvbdota-operands-fail.d: Ditto.
	* testsuite/gas/riscv/zvbdota-operands-fail.l: Ditto.
	* testsuite/gas/riscv/zvbdota-operands-fail.s: Ditto.
	* testsuite/gas/riscv/zvbdota-zvqwbdota16i.d: Ditto.
	* testsuite/gas/riscv/zvbdota-zvqwbdota16i.s: Ditto.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VQWBDOTAU_VV, MASK_VQWBDOTAU_VV):
	New encoding.
	(MATCH_VQWBDOTAS_VV, MASK_VQWBDOTAS_VV): Ditto.
	(MATCH_VFWBDOTA_VV, MASK_VFWBDOTA_VV): Ditto.
	(MATCH_VFQWBDOTA_VV, MASK_VFQWBDOTA_VV): Ditto.
	(MATCH_VFQWBDOTA_ALT_VV, MASK_VFQWBDOTA_ALT_VV): Ditto.
	(MATCH_VFBDOTA_VV, MASK_VFBDOTA_VV): Ditto.
	(DECLARE_INSN): New declarations.
	* opcode/riscv.h (enum riscv_insn_class): New extension classes.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Add 'q' and 'r' operand types
	for Zvbdota.
	* riscv-opc.c (riscv_opcodes): New instructions.
---
 bfd/elfxx-riscv.c                             | 35 ++++++++++++++++++
 gas/NEWS                                      |  4 +-
 gas/config/tc-riscv.c                         | 37 ++++++++++++++++++-
 gas/testsuite/gas/riscv/march-help.l          |  5 +++
 .../gas/riscv/zvbdota-operands-fail.d         |  3 ++
 .../gas/riscv/zvbdota-operands-fail.l         |  4 ++
 .../gas/riscv/zvbdota-operands-fail.s         |  4 ++
 .../gas/riscv/zvbdota-zvqwbdota16i.d          | 11 ++++++
 .../gas/riscv/zvbdota-zvqwbdota16i.s          |  3 ++
 gas/testsuite/gas/riscv/zvbdota.d             | 23 ++++++++++++
 gas/testsuite/gas/riscv/zvbdota.s             | 15 ++++++++
 include/opcode/riscv-opc.h                    | 20 ++++++++++
 include/opcode/riscv.h                        |  6 +++
 opcodes/riscv-dis.c                           | 11 ++++++
 opcodes/riscv-opc.c                           |  8 ++++
 15 files changed, 187 insertions(+), 2 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/zvbdota-operands-fail.d
 create mode 100644 gas/testsuite/gas/riscv/zvbdota-operands-fail.l
 create mode 100644 gas/testsuite/gas/riscv/zvbdota-operands-fail.s
 create mode 100644 gas/testsuite/gas/riscv/zvbdota-zvqwbdota16i.d
 create mode 100644 gas/testsuite/gas/riscv/zvbdota-zvqwbdota16i.s
 create mode 100644 gas/testsuite/gas/riscv/zvbdota.d
 create mode 100644 gas/testsuite/gas/riscv/zvbdota.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 44bdb5f2a99..e1639cbc2cb 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1239,8 +1239,13 @@ static const struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zvfhmin", "+zve32f", check_implicit_always},
   {"zvfbfwma", "+zve32f,+zfbfmin", check_implicit_always},
   {"zvfbfmin", "+zve32f", check_implicit_always},
+  {"zvfbdota32f", "+zve32f", check_implicit_always},
+  {"zvfqwbdota8f", "+zve32f", check_implicit_always},
   {"zvfqwdota8f", "+zve32f", check_implicit_always},
+  {"zvfwbdota16bf", "+zve32f", check_implicit_always},
   {"zvfwdota16bf", "+zve32f", check_implicit_always},
+  {"zvqwbdota8i", "+zve32x", check_implicit_always},
+  {"zvqwbdota16i", "+zve64x", check_implicit_always},
   {"zvqwdota8i", "+zve32x", check_implicit_always},
   {"zvqwdota16i", "+zve64x", check_implicit_always},
   {"zve64d", "+d,+zve64f", check_implicit_always},
@@ -1524,11 +1529,14 @@ static const struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvabd",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvbb",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvbc",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"zvfbdota32f",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvfbfmin",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvfbfwma",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvfh",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvfhmin",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"zvfqwbdota8f",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvfqwdota8f",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"zvfwbdota16bf",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvfwdota16bf",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvkb",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvkg",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
@@ -1544,6 +1552,8 @@ static const struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zvksg",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvksc",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvkt",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"zvqwbdota8i",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"zvqwbdota16i",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvqwdota8i",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvqwdota16i",	ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"zvl32b",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
@@ -2993,8 +3003,14 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zvfbfmin");
     case INSN_CLASS_ZVFBFWMA:
       return riscv_subset_supports (rps, "zvfbfwma");
+    case INSN_CLASS_ZVFBDOTA32F:
+      return riscv_subset_supports (rps, "zvfbdota32f");
+    case INSN_CLASS_ZVFQWBDOTA8F:
+      return riscv_subset_supports (rps, "zvfqwbdota8f");
     case INSN_CLASS_ZVFQWDOTA8F:
       return riscv_subset_supports (rps, "zvfqwdota8f");
+    case INSN_CLASS_ZVFWBDOTA16BF:
+      return riscv_subset_supports (rps, "zvfwbdota16bf");
     case INSN_CLASS_ZVFWDOTA16BF:
       return riscv_subset_supports (rps, "zvfwdota16bf");
     case INSN_CLASS_ZVKB:
@@ -3010,6 +3026,13 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zvksed");
     case INSN_CLASS_ZVKSH:
       return riscv_subset_supports (rps, "zvksh");
+    case INSN_CLASS_ZVQWBDOTA8I:
+      return riscv_subset_supports (rps, "zvqwbdota8i");
+    case INSN_CLASS_ZVQWBDOTA16I:
+      return riscv_subset_supports (rps, "zvqwbdota16i");
+    case INSN_CLASS_ZVQWBDOTA8I_OR_ZVQWBDOTA16I:
+      return (riscv_subset_supports (rps, "zvqwbdota8i")
+	      || riscv_subset_supports (rps, "zvqwbdota16i"));
     case INSN_CLASS_ZVQWDOTA8I:
       return riscv_subset_supports (rps, "zvqwdota8i");
     case INSN_CLASS_ZVQWDOTA16I:
@@ -3331,8 +3354,14 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return "zvfbfmin";
     case INSN_CLASS_ZVFBFWMA:
       return "zvfbfwma";
+    case INSN_CLASS_ZVFBDOTA32F:
+      return "zvfbdota32f";
+    case INSN_CLASS_ZVFQWBDOTA8F:
+      return "zvfqwbdota8f";
     case INSN_CLASS_ZVFQWDOTA8F:
       return "zvfqwdota8f";
+    case INSN_CLASS_ZVFWBDOTA16BF:
+      return "zvfwbdota16bf";
     case INSN_CLASS_ZVFWDOTA16BF:
       return "zvfwdota16bf";
     case INSN_CLASS_ZVKB:
@@ -3347,6 +3376,12 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zvksed");
     case INSN_CLASS_ZVKSH:
       return _("zvksh");
+    case INSN_CLASS_ZVQWBDOTA8I:
+      return "zvqwbdota8i";
+    case INSN_CLASS_ZVQWBDOTA16I:
+      return "zvqwbdota16i";
+    case INSN_CLASS_ZVQWBDOTA8I_OR_ZVQWBDOTA16I:
+      return _("zvqwbdota8i' or `zvqwbdota16i");
     case INSN_CLASS_ZVQWDOTA8I:
       return "zvqwdota8i";
     case INSN_CLASS_ZVQWDOTA16I:
diff --git a/gas/NEWS b/gas/NEWS
index c3e254689e0..b36bcb5cf3d 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -7,7 +7,9 @@
 
 * Add support for RISC-V standard extensions:
   zalasr v1.0, svrsw60t59b v1.0, zvabd v1.0, smpmpmt v1.0,
-  zvqwdota8i, zvqwdota16i, zvfwdota16bf and zvfqwdota8f v1.0.
+  zvqwdota8i, zvqwdota16i, zvfwdota16bf and zvfqwdota8f v1.0,
+  zvqwbdota8i, zvqwbdota16i, zvfwbdota16bf, zvfqwbdota8f and
+  zvfbdota32f v1.0.
 
 * Add support for RISC-V vendor extensions:
   SpacemiT: xsmtvdot v1.0, xsmtvdotii v1.0.
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index 53cc234cde4..0f3283cbb96 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -1568,6 +1568,8 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
 	    case 'e': USE_BITS (OP_MASK_VWD, OP_SH_VWD); break;
 	    case 's': USE_BITS (OP_MASK_VS1, OP_SH_VS1); break;
 	    case 't': USE_BITS (OP_MASK_VS2, OP_SH_VS2); break;
+	    case 'q': USE_BITS (0x3, OP_SH_VS2 + 3); break;
+	    case 'r': USE_BITS (0x7, OP_SH_VS2); break;
 	    case 'u': USE_BITS (OP_MASK_VS1, OP_SH_VS1);
 		      USE_BITS (OP_MASK_VS2, OP_SH_VS2); break;
 	    case 'v': USE_BITS (OP_MASK_VD, OP_SH_VD);
@@ -2697,8 +2699,12 @@ riscv_vtype_altfmt_supported (void)
 {
   return (riscv_subset_supports (&riscv_rps_as, "zvfbfa")
 	  || riscv_subset_supports (&riscv_rps_as, "zvfofp8min")
+	  || riscv_subset_supports (&riscv_rps_as, "zvfqwbdota8f")
 	  || riscv_subset_supports (&riscv_rps_as, "zvfqwdota8f")
+	  || riscv_subset_supports (&riscv_rps_as, "zvfwbdota16bf")
 	  || riscv_subset_supports (&riscv_rps_as, "zvfwdota16bf")
+	  || riscv_subset_supports (&riscv_rps_as, "zvqwbdota8i")
+	  || riscv_subset_supports (&riscv_rps_as, "zvqwbdota16i")
 	  || riscv_subset_supports (&riscv_rps_as, "zvqwdota8i")
 	  || riscv_subset_supports (&riscv_rps_as, "zvqwdota16i"));
 }
@@ -2720,7 +2726,7 @@ my_getVsetvliExpression (expressionS *ep, char *str)
 	as_bad (_("multiple vsew constants"));
       if (!riscv_vtype_altfmt_supported ())
 	as_bad (_("symbolic vtype altfmt requires `zvfbfa', "
-		  "`zvfofp8min' or a `zvdota' extension"));
+		  "`zvfofp8min' or an altfmt dot-product extension"));
       altfmt_value = 1 << OP_SH_VTYPE_ALTFMT;
       vsew_found = true;
     }
@@ -3376,6 +3382,35 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		  INSERT_OPERAND (VS2, *ip, regno);
 		  continue;
 
+		case 'q': /* Zvbdota VS2 group base.  */
+		  if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
+		    break;
+		  if (regno & 0x7)
+		    as_bad (_("vector register must be aligned to an "
+			      "EMUL=8 group"));
+		  INSERT_BITS (ip->insn_opcode, regno & 0x18, 0x18,
+			       OP_SH_VS2);
+		  continue;
+
+		case 'r': /* Zvbdota ci immediate in VS2.  */
+		  {
+		    offsetT ci;
+
+		    my_getExpression (imm_expr, asarg, force_reloc);
+		    check_absolute_expr (ip, imm_expr, false);
+		    ci = imm_expr->X_add_number;
+		    if (ci < 0 || ci > 56 || (ci & 0x7))
+		      {
+			as_bad (_("bad value for Zvbdota ci immediate field, "
+				  "value must be a multiple of 8 in 0..56"));
+			ci = 0;
+		      }
+		    INSERT_BITS (ip->insn_opcode, ci / 8, 0x7, OP_SH_VS2);
+		    imm_expr->X_op = O_absent;
+		    asarg = expr_parse_end;
+		    continue;
+		  }
+
 		case 'u': /* VS1 == VS2 */
 		  if (!reg_lookup (&asarg, RCLASS_VECR, &regno))
 		    break;
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 2b5efe808d6..142369b6b1d 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -72,11 +72,14 @@ All available -march extensions for RISC-V:
 	zvabd                                   1.0
 	zvbb                                    1.0
 	zvbc                                    1.0
+	zvfbdota32f                             1.0
 	zvfbfmin                                1.0
 	zvfbfwma                                1.0
 	zvfh                                    1.0
 	zvfhmin                                 1.0
+	zvfqwbdota8f                            1.0
 	zvfqwdota8f                             1.0
+	zvfwbdota16bf                           1.0
 	zvfwdota16bf                            1.0
 	zvkb                                    1.0
 	zvkg                                    1.0
@@ -92,6 +95,8 @@ All available -march extensions for RISC-V:
 	zvksg                                   1.0
 	zvksc                                   1.0
 	zvkt                                    1.0
+	zvqwbdota8i                             1.0
+	zvqwbdota16i                            1.0
 	zvqwdota8i                              1.0
 	zvqwdota16i                             1.0
 	zvl32b                                  1.0
diff --git a/gas/testsuite/gas/riscv/zvbdota-operands-fail.d b/gas/testsuite/gas/riscv/zvbdota-operands-fail.d
new file mode 100644
index 00000000000..32028f6bb8c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbdota-operands-fail.d
@@ -0,0 +1,3 @@
+#as: -march=rv64gc_zvqwbdota8i
+#source: zvbdota-operands-fail.s
+#error_output: zvbdota-operands-fail.l
diff --git a/gas/testsuite/gas/riscv/zvbdota-operands-fail.l b/gas/testsuite/gas/riscv/zvbdota-operands-fail.l
new file mode 100644
index 00000000000..6ba8dfca2e8
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbdota-operands-fail.l
@@ -0,0 +1,4 @@
+.*: Assembler messages:
+.*: Error: vector register must be aligned to an EMUL=8 group
+.*: Error: bad value for Zvbdota ci immediate field, value must be a multiple of 8 in 0..56
+.*: Error: bad value for Zvbdota ci immediate field, value must be a multiple of 8 in 0..56
diff --git a/gas/testsuite/gas/riscv/zvbdota-operands-fail.s b/gas/testsuite/gas/riscv/zvbdota-operands-fail.s
new file mode 100644
index 00000000000..0709892db8d
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbdota-operands-fail.s
@@ -0,0 +1,4 @@
+target:
+	vqwbdotas.vv v16, v9, v31, 0
+	vqwbdotas.vv v16, v8, v31, 4
+	vqwbdotas.vv v16, v8, v31, 64
diff --git a/gas/testsuite/gas/riscv/zvbdota-zvqwbdota16i.d b/gas/testsuite/gas/riscv/zvbdota-zvqwbdota16i.d
new file mode 100644
index 00000000000..349cd81f759
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbdota-zvqwbdota16i.d
@@ -0,0 +1,11 @@
+#as: -march=rv64gc_zvqwbdota16i
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+ba8f8877[ 	]+vqwbdotau.vv[ 	]+v16,v8,v31,0
+[ 	]+[0-9a-f]+:[ 	]+be9f8877[ 	]+vqwbdotas.vv[ 	]+v16,v8,v31,8
diff --git a/gas/testsuite/gas/riscv/zvbdota-zvqwbdota16i.s b/gas/testsuite/gas/riscv/zvbdota-zvqwbdota16i.s
new file mode 100644
index 00000000000..1a5bb4ef4bc
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbdota-zvqwbdota16i.s
@@ -0,0 +1,3 @@
+target:
+	vqwbdotau.vv v16, v8, v31, 0
+	vqwbdotas.vv v16, v8, v31, 8
diff --git a/gas/testsuite/gas/riscv/zvbdota.d b/gas/testsuite/gas/riscv/zvbdota.d
new file mode 100644
index 00000000000..63fa13853fa
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbdota.d
@@ -0,0 +1,23 @@
+#as: -march=rv64gc_zvqwbdota8i_zvqwbdota16i_zvfwbdota16bf_zvfqwbdota8f_zvfbdota32f
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+[0-9a-f]+:[ 	]+ba8f8877[ 	]+vqwbdotau.vv[ 	]+v16,v8,v31,0
+[ 	]+[0-9a-f]+:[ 	]+ba9f8877[ 	]+vqwbdotau.vv[ 	]+v16,v8,v31,8
+[ 	]+[0-9a-f]+:[ 	]+be8f8877[ 	]+vqwbdotas.vv[ 	]+v16,v8,v31,0
+[ 	]+[0-9a-f]+:[ 	]+be9f8877[ 	]+vqwbdotas.vv[ 	]+v16,v8,v31,8
+[ 	]+[0-9a-f]+:[ 	]+b28f9877[ 	]+vfwbdota.vv[ 	]+v16,v8,v31,0
+[ 	]+[0-9a-f]+:[ 	]+b29f9877[ 	]+vfwbdota.vv[ 	]+v16,v8,v31,8
+[ 	]+[0-9a-f]+:[ 	]+ba8f9877[ 	]+vfqwbdota.vv[ 	]+v16,v8,v31,0
+[ 	]+[0-9a-f]+:[ 	]+ba9f9877[ 	]+vfqwbdota.vv[ 	]+v16,v8,v31,8
+[ 	]+[0-9a-f]+:[ 	]+be8f9877[ 	]+vfqwbdota.alt.vv[ 	]+v16,v8,v31,0
+[ 	]+[0-9a-f]+:[ 	]+be9f9877[ 	]+vfqwbdota.alt.vv[ 	]+v16,v8,v31,8
+[ 	]+[0-9a-f]+:[ 	]+ae8f9877[ 	]+vfbdota.vv[ 	]+v16,v8,v31,0
+[ 	]+[0-9a-f]+:[ 	]+ae9f9877[ 	]+vfbdota.vv[ 	]+v16,v8,v31,8
+[ 	]+[0-9a-f]+:[ 	]+bc8f8877[ 	]+vqwbdotas.vv[ 	]+v16,v8,v31,0,v0.t
+[ 	]+[0-9a-f]+:[ 	]+b89f9877[ 	]+vfqwbdota.vv[ 	]+v16,v8,v31,8,v0.t
diff --git a/gas/testsuite/gas/riscv/zvbdota.s b/gas/testsuite/gas/riscv/zvbdota.s
new file mode 100644
index 00000000000..c87975a4cc9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvbdota.s
@@ -0,0 +1,15 @@
+target:
+	vqwbdotau.vv v16, v8, v31, 0
+	vqwbdotau.vv v16, v8, v31, 8
+	vqwbdotas.vv v16, v8, v31, 0
+	vqwbdotas.vv v16, v8, v31, 8
+	vfwbdota.vv v16, v8, v31, 0
+	vfwbdota.vv v16, v8, v31, 8
+	vfqwbdota.vv v16, v8, v31, 0
+	vfqwbdota.vv v16, v8, v31, 8
+	vfqwbdota.alt.vv v16, v8, v31, 0
+	vfqwbdota.alt.vv v16, v8, v31, 8
+	vfbdota.vv v16, v8, v31, 0
+	vfbdota.vv v16, v8, v31, 8
+	vqwbdotas.vv v16, v8, v31, 0, v0.t
+	vfqwbdota.vv v16, v8, v31, 8, v0.t
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 812f24c083c..6846655aeed 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2588,6 +2588,19 @@
 #define MASK_VFQWDOTA_VV 0xfc00707f
 #define MATCH_VFQWDOTA_ALT_VV 0x9c001077
 #define MASK_VFQWDOTA_ALT_VV 0xfc00707f
+/* Zvbdota instructions.  */
+#define MATCH_VQWBDOTAU_VV 0xb8000077
+#define MASK_VQWBDOTAU_VV 0xfc00707f
+#define MATCH_VQWBDOTAS_VV 0xbc000077
+#define MASK_VQWBDOTAS_VV 0xfc00707f
+#define MATCH_VFWBDOTA_VV 0xb0001077
+#define MASK_VFWBDOTA_VV 0xfc00707f
+#define MATCH_VFQWBDOTA_VV 0xb8001077
+#define MASK_VFQWBDOTA_VV 0xfc00707f
+#define MATCH_VFQWBDOTA_ALT_VV 0xbc001077
+#define MASK_VFQWBDOTA_ALT_VV 0xfc00707f
+#define MATCH_VFBDOTA_VV 0xac001077
+#define MASK_VFBDOTA_VV 0xfc00707f
 /* Vendor-specific (CORE-V) Xcvmac instructions.  */
 #define MATCH_CV_MAC       0x9000302b
 #define MASK_CV_MAC        0xfe00707f
@@ -4919,6 +4932,13 @@ DECLARE_INSN(vqwdotas_vv, MATCH_VQWDOTAS_VV, MASK_VQWDOTAS_VV)
 DECLARE_INSN(vfwdota_vv, MATCH_VFWDOTA_VV, MASK_VFWDOTA_VV)
 DECLARE_INSN(vfqwdota_vv, MATCH_VFQWDOTA_VV, MASK_VFQWDOTA_VV)
 DECLARE_INSN(vfqwdota_alt_vv, MATCH_VFQWDOTA_ALT_VV, MASK_VFQWDOTA_ALT_VV)
+/* Zvbdota instructions.  */
+DECLARE_INSN(vqwbdotau_vv, MATCH_VQWBDOTAU_VV, MASK_VQWBDOTAU_VV)
+DECLARE_INSN(vqwbdotas_vv, MATCH_VQWBDOTAS_VV, MASK_VQWBDOTAS_VV)
+DECLARE_INSN(vfwbdota_vv, MATCH_VFWBDOTA_VV, MASK_VFWBDOTA_VV)
+DECLARE_INSN(vfqwbdota_vv, MATCH_VFQWBDOTA_VV, MASK_VFQWBDOTA_VV)
+DECLARE_INSN(vfqwbdota_alt_vv, MATCH_VFQWBDOTA_ALT_VV, MASK_VFQWBDOTA_ALT_VV)
+DECLARE_INSN(vfbdota_vv, MATCH_VFBDOTA_VV, MASK_VFBDOTA_VV)
 /* Zvbb/Zvkb instructions.  */
 DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV)
 DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX)
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 45b6c7979db..f500b877ca6 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -562,7 +562,10 @@ enum riscv_insn_class
   INSN_CLASS_ZVBC,
   INSN_CLASS_ZVFBFMIN,
   INSN_CLASS_ZVFBFWMA,
+  INSN_CLASS_ZVFBDOTA32F,
+  INSN_CLASS_ZVFQWBDOTA8F,
   INSN_CLASS_ZVFQWDOTA8F,
+  INSN_CLASS_ZVFWBDOTA16BF,
   INSN_CLASS_ZVFWDOTA16BF,
   INSN_CLASS_ZVKB,
   INSN_CLASS_ZVKG,
@@ -571,6 +574,9 @@ enum riscv_insn_class
   INSN_CLASS_ZVKSED,
   INSN_CLASS_ZVKSH,
   INSN_CLASS_ZVABD,
+  INSN_CLASS_ZVQWBDOTA8I,
+  INSN_CLASS_ZVQWBDOTA16I,
+  INSN_CLASS_ZVQWBDOTA8I_OR_ZVQWBDOTA16I,
   INSN_CLASS_ZVQWDOTA8I,
   INSN_CLASS_ZVQWDOTA16I,
   INSN_CLASS_ZVQWDOTA8I_OR_ZVQWDOTA16I,
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 86dbdb18456..724c8b90b12 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -440,6 +440,17 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
 	      print (info->stream, dis_style_register, "%s",
 		     riscv_vecr_names_numeric[EXTRACT_OPERAND (VS2, l)]);
 	      break;
+	    case 'q':
+	      {
+		unsigned int vs2 = EXTRACT_OPERAND (VS2, l);
+		print (info->stream, dis_style_register, "%s",
+		       riscv_vecr_names_numeric[vs2 & 0x18]);
+	      }
+	      break;
+	    case 'r':
+	      print (info->stream, dis_style_immediate, "%u",
+		     (unsigned int) (EXTRACT_OPERAND (VS2, l) & 0x7) * 8);
+	      break;
 	    case '0':
 	      print (info->stream, dis_style_register, "%s",
 		     riscv_vecr_names_numeric[0]);
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index cfec774ecdb..cd1e2910307 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2257,6 +2257,14 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vfqwdota.vv", 0, INSN_CLASS_ZVFQWDOTA8F, "Vd,Vt,VsVm", MATCH_VFQWDOTA_VV, MASK_VFQWDOTA_VV, match_opcode, 0},
 {"vfqwdota.alt.vv", 0, INSN_CLASS_ZVFQWDOTA8F, "Vd,Vt,VsVm", MATCH_VFQWDOTA_ALT_VV, MASK_VFQWDOTA_ALT_VV, match_opcode, 0},
 
+/* Zvbdota instructions.  */
+{"vqwbdotau.vv", 0, INSN_CLASS_ZVQWBDOTA8I_OR_ZVQWBDOTA16I, "Vd,Vq,Vs,VrVm", MATCH_VQWBDOTAU_VV, MASK_VQWBDOTAU_VV, match_opcode, 0},
+{"vqwbdotas.vv", 0, INSN_CLASS_ZVQWBDOTA8I_OR_ZVQWBDOTA16I, "Vd,Vq,Vs,VrVm", MATCH_VQWBDOTAS_VV, MASK_VQWBDOTAS_VV, match_opcode, 0},
+{"vfwbdota.vv",  0, INSN_CLASS_ZVFWBDOTA16BF, "Vd,Vq,Vs,VrVm", MATCH_VFWBDOTA_VV, MASK_VFWBDOTA_VV, match_opcode, 0},
+{"vfqwbdota.vv", 0, INSN_CLASS_ZVFQWBDOTA8F, "Vd,Vq,Vs,VrVm", MATCH_VFQWBDOTA_VV, MASK_VFQWBDOTA_VV, match_opcode, 0},
+{"vfqwbdota.alt.vv", 0, INSN_CLASS_ZVFQWBDOTA8F, "Vd,Vq,Vs,VrVm", MATCH_VFQWBDOTA_ALT_VV, MASK_VFQWBDOTA_ALT_VV, match_opcode, 0},
+{"vfbdota.vv",   0, INSN_CLASS_ZVFBDOTA32F, "Vd,Vq,Vs,VrVm", MATCH_VFBDOTA_VV, MASK_VFBDOTA_VV, match_opcode, 0},
+
 /* Zvbb/Zvkb instructions.  */
 {"vandn.vv",   0, INSN_CLASS_ZVKB, "Vd,Vt,VsVm", MATCH_VANDN_VV, MASK_VANDN_VV, match_opcode, 0},
 {"vandn.vx",   0, INSN_CLASS_ZVKB, "Vd,Vt,sVm", MATCH_VANDN_VX, MASK_VANDN_VX, match_opcode, 0},
-- 
2.43.0


From amodra@gmail.com  Tue Jun 30 03:51:34 2026
From: amodra@gmail.com (Alan Modra)
Date: Tue, 30 Jun 2026 13:21:34 +0930
Subject: ld testsuite alpha_ld_flags
Message-ID: <akM9Rh8FYspvGdXY@squeak.grove.modra.org>

This is how alpha can use -Ttext-segment on just those tests that need
it.  And since the way run_dump_test uses $opts(ld) allows tcl procs to
be embedded, there is no need to specially expand [big_or_little_endian].

binutils/
	* testsuite/lib/binutils-common.exp (run_dump_test <opts(ld)>): No
	need to handle big_or_little_endian specially.
ld/
	* testsuite/ld-elf/elf.exp (alpha_ld_flags): New proc.
	(LDFLAGS): Don't set -Ttext-segment for alpha globally.
	* testsuite/ld-elf/compress1a.d: Add alpha_ld_flags.
	* testsuite/ld-elf/compressed1a.d: Likewise.
	* testsuite/ld-elf/eh5.d: Likewise.

diff --git a/binutils/testsuite/lib/binutils-common.exp b/binutils/testsuite/lib/binutils-common.exp
index 8a484454e65..48c6f46bd1c 100644
--- a/binutils/testsuite/lib/binutils-common.exp
+++ b/binutils/testsuite/lib/binutils-common.exp
@@ -1242,9 +1242,6 @@ proc run_dump_test { name {extra_options {}} } {
 	lappend as_final_flags $x
     }
 
-    regsub {\[big_or_little_endian\]} $opts(ld) \
-	[big_or_little_endian] opts(ld)
-
     if { $opts(name) == "" } {
 	set base_testname "$subdir/$name"
     } else {
diff --git a/ld/testsuite/ld-elf/compress1a.d b/ld/testsuite/ld-elf/compress1a.d
index 44f35aacf15..8e29d01f20b 100644
--- a/ld/testsuite/ld-elf/compress1a.d
+++ b/ld/testsuite/ld-elf/compress1a.d
@@ -1,6 +1,6 @@
 #source: compress1.s
 #as: --compress-debug-sections
-#ld: -e func_cu2
+#ld: -e func_cu2 [alpha_ld_flags]
 #readelf: -S --wide
 #xfail: alpha-*-*ecoff
 # PR ld/25802
diff --git a/ld/testsuite/ld-elf/compressed1a.d b/ld/testsuite/ld-elf/compressed1a.d
index e9a7e3b842f..2ffe9413db3 100644
--- a/ld/testsuite/ld-elf/compressed1a.d
+++ b/ld/testsuite/ld-elf/compressed1a.d
@@ -1,6 +1,6 @@
 #source: compress1.s
 #as: --compress-debug-sections=zlib-gabi
-#ld: -e func_cu2
+#ld: -e func_cu2 [alpha_ld_flags]
 #readelf: -t
 #xfail: alpha-*-*ecoff
 # PR ld/25802
diff --git a/ld/testsuite/ld-elf/eh5.d b/ld/testsuite/ld-elf/eh5.d
index 48109d38310..266e6f31621 100644
--- a/ld/testsuite/ld-elf/eh5.d
+++ b/ld/testsuite/ld-elf/eh5.d
@@ -1,7 +1,7 @@
 #source: eh5.s
 #source: eh5a.s
 #source: eh5b.s
-#ld:
+#ld: [alpha_ld_flags]
 #readelf: -wf
 #target: [check_as_cfi]
 #xfail: alpha-*-*ecoff tile*-*-* visium-*-*
diff --git a/ld/testsuite/ld-elf/elf.exp b/ld/testsuite/ld-elf/elf.exp
index 51b8c942648..337206318ab 100644
--- a/ld/testsuite/ld-elf/elf.exp
+++ b/ld/testsuite/ld-elf/elf.exp
@@ -51,11 +51,15 @@ if [istarget "*-*-hpux*"] {
     set ASFLAGS "$ASFLAGS --defsym HPUX=1"
 }
 
+# Some tests expect 32-bit addresses.  Force the executable to low addresses.
+proc alpha_ld_flags { } {
+    if { [istarget alpha*-*-* ] } {
+	return "-Ttext-segment 0x1000000"
+    }
+    return ""
+}
+
 if { [istarget alpha*-*-* ] } {
-    # The compress1 test is written expecting 32-bit addresses; force the
-    # executable down into the low address space to match.
-    # ??? How can we adjust just the one testcase?
-    set LDFLAGS "$LDFLAGS -Ttext-segment 0x1000000"
     set ASFLAGS "$ASFLAGS --defsym NO_SET=1"
 }
 

-- 
Alan Modra

From jbeulich@suse.com  Tue Jun 30 05:58:36 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Tue, 30 Jun 2026 07:58:36 +0200
Subject: [PATCH v1 2/2] Support x86 ACE ISA
In-Reply-To: <PH3PPF801A91A7D9BCD052BC2228570C282A6F72@PH3PPF801A91A7D.namprd11.prod.outlook.com>
References: <20260627095543.1627012-1-Ganesh.Gopalasubramanian@amd.com>
 <20260627115533.1633143-1-Ganesh.Gopalasubramanian@amd.com>
 <PH3PPF801A91A7D9BCD052BC2228570C282A6F72@PH3PPF801A91A7D.namprd11.prod.outlook.com>
Message-ID: <44102d0a-4ebc-4b3a-a135-3739d05caf6a@suse.com>

On 30.06.2026 05:17, Hu, Lin1 wrote:
>> -----Original Message-----
>> From: Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
>> Sent: Saturday, June 27, 2026 7:56 PM
>>
>> @@ -4253,6 +4257,7 @@ install_template (const insn_template *t)
>>  	}
>>
>>        if ((maybe_cpu (t, CpuCMPCCXADD) || maybe_cpu (t, CpuAMX_TILE)
>> +	   || maybe_cpu (t, CpuACE)
> 
> Outer condition is if (t->opcode_modifier.vex && t->opcode_modifier.evex),  seems that the line is invalid.

"invalid" as in "unnecessary"? Else please explain.

Also, as a general remark: Please trim reply context, especially when what
you reply to was large.

Jan

From lin1.hu@intel.com  Tue Jun 30 06:28:29 2026
From: lin1.hu@intel.com (Hu, Lin1)
Date: Tue, 30 Jun 2026 06:28:29 +0000
Subject: [PATCH v1 2/2] Support x86 ACE ISA
In-Reply-To: <44102d0a-4ebc-4b3a-a135-3739d05caf6a@suse.com>
References: <20260627095543.1627012-1-Ganesh.Gopalasubramanian@amd.com>
 <20260627115533.1633143-1-Ganesh.Gopalasubramanian@amd.com>
 <PH3PPF801A91A7D9BCD052BC2228570C282A6F72@PH3PPF801A91A7D.namprd11.prod.outlook.com>
 <44102d0a-4ebc-4b3a-a135-3739d05caf6a@suse.com>
Message-ID: <DS4PPF8140589512BC3BF3700D7EEE3F1FBA6F72@DS4PPF814058951.namprd11.prod.outlook.com>

> From: Jan Beulich <jbeulich@suse.com>
> Sent: Tuesday, June 30, 2026 1:59 PM
> On 30.06.2026 05:17, Hu, Lin1 wrote:
> >> -----Original Message-----
> >> From: Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
> >> Sent: Saturday, June 27, 2026 7:56 PM
> >>
> >> @@ -4253,6 +4257,7 @@ install_template (const insn_template *t)
> >>  	}
> >>
> >>        if ((maybe_cpu (t, CpuCMPCCXADD) || maybe_cpu (t, CpuAMX_TILE)
> >> +	   || maybe_cpu (t, CpuACE)
> >
> > Outer condition is if (t->opcode_modifier.vex && t->opcode_modifier.evex),
> seems that the line is invalid.
> 
> "invalid" as in "unnecessary"? Else please explain.
> 
> Also, as a general remark: Please trim reply context, especially when what you
> reply to was large.
>

Yes, it's unnecessary. ACE instructions don't set vex and evex at the same time.

BRs,
Lin

From jbeulich@suse.com  Tue Jun 30 07:13:03 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Tue, 30 Jun 2026 09:13:03 +0200
Subject: [PATCH] readelf: Also set do_got_section_contents to false
In-Reply-To: <CAMe9rOoBkGLNBAijT_7d6dY2cnFnHm1+zUs+PShN6pjeAzSvgg@mail.gmail.com>
References: <CAMe9rOoBkGLNBAijT_7d6dY2cnFnHm1+zUs+PShN6pjeAzSvgg@mail.gmail.com>
Message-ID: <9ba3a26a-2cff-411a-8629-dc1e073e6182@suse.com>

On 30.06.2026 00:39, H.J. Lu wrote:
> Also set do_got_section_contents to false if section headers are failed
> to load.
> 
> PR binutils/34323
> * readelf.c (process_object): Also set do_got_section_contents.

Okay.

Jan

From chigot@adacore.com  Tue Jun 30 07:55:10 2026
From: chigot@adacore.com (=?UTF-8?Q?Cl=C3=A9ment_Chigot?=)
Date: Tue, 30 Jun 2026 09:55:10 +0200
Subject: [PATCH v2] ld/testsuite: add support for remote testing in
 ld-cdtest
In-Reply-To: <CAJ307EghSg-BPajFHCG-3HqA5VF0FwoEoE92CMfNW5WWMqu4ug@mail.gmail.com>
References: <20260618075856.2258643-1-chigot@adacore.com>
 <CAJ307EghSg-BPajFHCG-3HqA5VF0FwoEoE92CMfNW5WWMqu4ug@mail.gmail.com>
Message-ID: <CAJ307Ej5cutoMYAt3hGkubD3VsMc0xXtrQtOeRmEWhG5OLwMzg@mail.gmail.com>

On Thu, Jun 18, 2026 at 10:04?AM Cl?ment Chigot <chigot@adacore.com> wrote:
>
> On Thu, Jun 18, 2026 at 9:58?AM Cl?ment Chigot <chigot@adacore.com> wrote:
> >
> > This converts the existing to code to use "remote_load" allowing
> > execution on both native and remote targets.
> >
> > The "diff" between the output and the expected result has been
> > transformed to the usual regexp_diff. The previous could have been
> > transformed into `remote_exec build diff` but tends to be fickled with
> > new lines.
>
> Arf got Maciej's Redhat email rejected. Trying with macro@orcam.me.uk.

Gentle ping to Maciej.
Otherwise, Alan ok to merge in a few days if he doesn't answer ?

> > ---
> >  ld/testsuite/ld-cdtest/cdtest-nrv.dat | 26 ++++----
> >  ld/testsuite/ld-cdtest/cdtest.dat     | 30 ++++-----
> >  ld/testsuite/ld-cdtest/cdtest.exp     | 95 +++++++++++++--------------
> >  3 files changed, 73 insertions(+), 78 deletions(-)
> >
> > diff --git a/ld/testsuite/ld-cdtest/cdtest-nrv.dat b/ld/testsuite/ld-cdtest/cdtest-nrv.dat
> > index d3f871ff108..76fcbaa03d4 100644
> > --- a/ld/testsuite/ld-cdtest/cdtest-nrv.dat
> > +++ b/ld/testsuite/ld-cdtest/cdtest-nrv.dat
> > @@ -1,13 +1,13 @@
> > -Constructing Foo(1) "static_foo"
> > -Constructing Foo(2) "static_foo"
> > -Constructing Foo(3) "automatic_foo"
> > -Constructing Foo(4) "default-foo"
> > -Constructing Foo(5) "other_foo1"
> > -Constructing Foo(6) "other_foo2"
> > -Copying Foo(5) "other_foo1" to Foo(6)
> > -Destructing Foo(6) "other_foo1" (remaining foos: 5)
> > -Destructing Foo(5) "other_foo1" (remaining foos: 4)
> > -Destructing Foo(4) "default-foo" (remaining foos: 3)
> > -Destructing Foo(3) "automatic_foo" (remaining foos: 2)
> > -Destructing Foo(2) "static_foo" (remaining foos: 1)
> > -Destructing Foo(1) "static_foo" (remaining foos: 0)
> > +Constructing Foo\(1\) "static_foo"
> > +Constructing Foo\(2\) "static_foo"
> > +Constructing Foo\(3\) "automatic_foo"
> > +Constructing Foo\(4\) "default-foo"
> > +Constructing Foo\(5\) "other_foo1"
> > +Constructing Foo\(6\) "other_foo2"
> > +Copying Foo\(5\) "other_foo1" to Foo\(6\)
> > +Destructing Foo\(6\) "other_foo1" \(remaining foos: 5\)
> > +Destructing Foo\(5\) "other_foo1" \(remaining foos: 4\)
> > +Destructing Foo\(4\) "default-foo" \(remaining foos: 3\)
> > +Destructing Foo\(3\) "automatic_foo" \(remaining foos: 2\)
> > +Destructing Foo\(2\) "static_foo" \(remaining foos: 1\)
> > +Destructing Foo\(1\) "static_foo" \(remaining foos: 0\)
> > diff --git a/ld/testsuite/ld-cdtest/cdtest.dat b/ld/testsuite/ld-cdtest/cdtest.dat
> > index 39be0dbc2c7..c0bdffb3c26 100644
> > --- a/ld/testsuite/ld-cdtest/cdtest.dat
> > +++ b/ld/testsuite/ld-cdtest/cdtest.dat
> > @@ -1,15 +1,15 @@
> > -Constructing Foo(1) "static_foo"
> > -Constructing Foo(2) "static_foo"
> > -Constructing Foo(3) "automatic_foo"
> > -Constructing Foo(4) "default-foo"
> > -Initializing Foo(5) "default-foo" with Foo(4)
> > -Destructing Foo(4) "default-foo" (remaining foos: 4)
> > -Constructing Foo(5) "other_foo1"
> > -Constructing Foo(6) "other_foo2"
> > -Copying Foo(5) "other_foo1" to Foo(6)
> > -Destructing Foo(6) "other_foo1" (remaining foos: 5)
> > -Destructing Foo(5) "other_foo1" (remaining foos: 4)
> > -Destructing Foo(5) "default-foo" (remaining foos: 3)
> > -Destructing Foo(3) "automatic_foo" (remaining foos: 2)
> > -Destructing Foo(2) "static_foo" (remaining foos: 1)
> > -Destructing Foo(1) "static_foo" (remaining foos: 0)
> > +Constructing Foo\(1\) "static_foo"
> > +Constructing Foo\(2\) "static_foo"
> > +Constructing Foo\(3\) "automatic_foo"
> > +Constructing Foo\(4\) "default-foo"
> > +Initializing Foo\(5\) "default-foo" with Foo\(4\)
> > +Destructing Foo\(4\) "default-foo" \(remaining foos: 4\)
> > +Constructing Foo\(5\) "other_foo1"
> > +Constructing Foo\(6\) "other_foo2"
> > +Copying Foo\(5\) "other_foo1" to Foo\(6\)
> > +Destructing Foo\(6\) "other_foo1" \(remaining foos: 5\)
> > +Destructing Foo\(5\) "other_foo1" \(remaining foos: 4\)
> > +Destructing Foo\(5\) "default-foo" \(remaining foos: 3\)
> > +Destructing Foo\(3\) "automatic_foo" \(remaining foos: 2\)
> > +Destructing Foo\(2\) "static_foo" \(remaining foos: 1\)
> > +Destructing Foo\(1\) "static_foo" \(remaining foos: 0\)
> > diff --git a/ld/testsuite/ld-cdtest/cdtest.exp b/ld/testsuite/ld-cdtest/cdtest.exp
> > index 89fdd581abb..81547af3c9e 100644
> > --- a/ld/testsuite/ld-cdtest/cdtest.exp
> > +++ b/ld/testsuite/ld-cdtest/cdtest.exp
> > @@ -28,11 +28,7 @@ set test1 "cdtest"
> >  set test2 "cdtest with -Ur"
> >
> >  # This test requires running the executable generated by ld.
> > -if ![isnative] {
> > -    return
> > -}
> > -
> > -if { [which $CXX_FOR_TARGET] == 0 } {
> > +if { [which $CXX_FOR_TARGET] == 0 || ![check_execution_available] } {
> >      untested $test1
> >      untested $test2
> >      return
> > @@ -51,44 +47,39 @@ set expected_output "$srcdir/$subdir/cdtest.dat"
> >  if ![ld_link $CC_FOR_TARGET tmpdir/cdtest "$CFLAGS_FOR_TARGET tmpdir/cdtest-foo.o tmpdir/cdtest-bar.o tmpdir/cdtest-main.o"] {
> >      fail $test1
> >  } else {
> > -    send_log   "tmpdir/cdtest >tmpdir/cdtest.out\n"
> > -    verbose    "tmpdir/cdtest >tmpdir/cdtest.out"
> > -    catch "exec tmpdir/cdtest >tmpdir/cdtest.out" exec_output
> > +    set failed 0
> >
> > -    if ![string match "" $exec_output] then {
> > +    send_log "Running: tmpdir/cdtest\n"
> > +    verbose "Running: tmpdir/cdtest"
> > +    set state [remote_load target tmpdir/cdtest]
> > +    set status [lindex $state 0]
> > +    set exec_output [lindex $state 1]
> > +
> > +    if { $status != "pass"  } {
> >         send_log "$exec_output\n"
> >         verbose "$exec_output" 1
> > -
> > -       fail $test1
> > +       set failed 1
> >      } else {
> > -       send_log   "diff tmpdir/cdtest.out $expected_output\n"
> > -       verbose    "diff tmpdir/cdtest.out $expected_output"
> > -       catch "exec diff tmpdir/cdtest.out $expected_output" exec_output
> > -       set exec_output [prune_warnings $exec_output]
> > -
> > -       if ![string match "" $exec_output] then {
> > -           send_log "$exec_output\n"
> > -           verbose  "$exec_output" 1
> > +       set output_filename "tmpdir/cdtest.out"
> > +       set_file_contents $output_filename $exec_output
> >
> > +       send_log [file_contents $output_filename]
> > +       verbose [file_contents $output_filename] 2
> > +       if [regexp_diff $output_filename $expected_output] {
> >             send_log "Checking against Named Return Value optimization\n"
> >             verbose  "Checking against Named Return Value optimization" 1
> >
> >             set expected_output "$srcdir/$subdir/cdtest-nrv.dat"
> > -
> > -           send_log   "diff tmpdir/cdtest.out $expected_output\n"
> > -           verbose    "diff tmpdir/cdtest.out $expected_output"
> > -           catch "exec diff tmpdir/cdtest.out $expected_output" exec_output
> > -           set exec_output [prune_warnings $exec_output]
> > +           if [regexp_diff $output_filename $expected_output] {
> > +               set failed 1
> > +           }
> >         }
> > +    }
> >
> > -       if [string match "" $exec_output] then {
> > -           pass $test1
> > -       } else {
> > -           send_log "$exec_output\n"
> > -           verbose  "$exec_output" 1
> > -
> > -           fail $test1
> > -       }
> > +    if { $failed != 0 } {
> > +       fail $test1
> > +    } else {
> > +       pass $test1
> >      }
> >  }
> >
> > @@ -103,29 +94,33 @@ if ![ld_relocate $ld tmpdir/cdtest.o {-Ur tmpdir/cdtest-foo.o tmpdir/cdtest-bar.
> >      if ![ld_link $CC_FOR_TARGET tmpdir/cdtest "$CFLAGS_FOR_TARGET tmpdir/cdtest.o"] {
> >         fail $test2
> >      } else {
> > -       send_log   "tmpdir/cdtest >tmpdir/cdtest.out\n"
> > -       verbose    "tmpdir/cdtest >tmpdir/cdtest.out"
> > -       catch "exec tmpdir/cdtest >tmpdir/cdtest.out" exec_output
> > +       set failed 0
> > +
> > +       send_log "Running: tmpdir/cdtest\n"
> > +       verbose "Running: tmpdir/cdtest"
> > +       set state [remote_load target tmpdir/cdtest]
> > +       set status [lindex $state 0]
> > +       set exec_output [lindex $state 1]
> >
> > -       if ![string match "" $exec_output] then {
> > +       if { $status != "pass" } {
> >             send_log "$exec_output\n"
> > -           verbose  "$exec_output" 1
> > +           verbose "$exec_output" 1
> > +           set failed 1
> > +       } else {
> > +           set output_filename "tmpdir/cdtest.out"
> > +           set_file_contents $output_filename $exec_output
> >
> > +           send_log [file_contents $output_filename]
> > +           verbose [file_contents $output_filename] 2
> > +           if [regexp_diff $output_filename $expected_output] {
> > +               set failed 1
> > +           }
> > +       }
> > +
> > +       if { $failed != 0 } {
> >             fail $test2
> >         } else {
> > -           send_log   "diff tmpdir/cdtest.out $expected_output\n"
> > -           verbose    "diff tmpdir/cdtest.out $expected_output"
> > -           catch "exec diff tmpdir/cdtest.out $expected_output" exec_output
> > -           set exec_output [prune_warnings $exec_output]
> > -
> > -           if [string match "" $exec_output] then {
> > -               pass $test2
> > -           } else {
> > -               send_log "$exec_output\n"
> > -               verbose  "$exec_output" 1
> > -
> > -               fail $test2
> > -           }
> > +           pass $test2
> >         }
> >      }
> >  }
> > --
> > 2.43.0
> >
>
> On Thu, Jun 18, 2026 at 9:58?AM Cl?ment Chigot <chigot@adacore.com> wrote:
> >
> > This converts the existing to code to use "remote_load" allowing
> > execution on both native and remote targets.
> >
> > The "diff" between the output and the expected result has been
> > transformed to the usual regexp_diff. The previous could have been
> > transformed into `remote_exec build diff` but tends to be fickled with
> > new lines.
> > ---
> >  ld/testsuite/ld-cdtest/cdtest-nrv.dat | 26 ++++----
> >  ld/testsuite/ld-cdtest/cdtest.dat     | 30 ++++-----
> >  ld/testsuite/ld-cdtest/cdtest.exp     | 95 +++++++++++++--------------
> >  3 files changed, 73 insertions(+), 78 deletions(-)
> >
> > diff --git a/ld/testsuite/ld-cdtest/cdtest-nrv.dat b/ld/testsuite/ld-cdtest/cdtest-nrv.dat
> > index d3f871ff108..76fcbaa03d4 100644
> > --- a/ld/testsuite/ld-cdtest/cdtest-nrv.dat
> > +++ b/ld/testsuite/ld-cdtest/cdtest-nrv.dat
> > @@ -1,13 +1,13 @@
> > -Constructing Foo(1) "static_foo"
> > -Constructing Foo(2) "static_foo"
> > -Constructing Foo(3) "automatic_foo"
> > -Constructing Foo(4) "default-foo"
> > -Constructing Foo(5) "other_foo1"
> > -Constructing Foo(6) "other_foo2"
> > -Copying Foo(5) "other_foo1" to Foo(6)
> > -Destructing Foo(6) "other_foo1" (remaining foos: 5)
> > -Destructing Foo(5) "other_foo1" (remaining foos: 4)
> > -Destructing Foo(4) "default-foo" (remaining foos: 3)
> > -Destructing Foo(3) "automatic_foo" (remaining foos: 2)
> > -Destructing Foo(2) "static_foo" (remaining foos: 1)
> > -Destructing Foo(1) "static_foo" (remaining foos: 0)
> > +Constructing Foo\(1\) "static_foo"
> > +Constructing Foo\(2\) "static_foo"
> > +Constructing Foo\(3\) "automatic_foo"
> > +Constructing Foo\(4\) "default-foo"
> > +Constructing Foo\(5\) "other_foo1"
> > +Constructing Foo\(6\) "other_foo2"
> > +Copying Foo\(5\) "other_foo1" to Foo\(6\)
> > +Destructing Foo\(6\) "other_foo1" \(remaining foos: 5\)
> > +Destructing Foo\(5\) "other_foo1" \(remaining foos: 4\)
> > +Destructing Foo\(4\) "default-foo" \(remaining foos: 3\)
> > +Destructing Foo\(3\) "automatic_foo" \(remaining foos: 2\)
> > +Destructing Foo\(2\) "static_foo" \(remaining foos: 1\)
> > +Destructing Foo\(1\) "static_foo" \(remaining foos: 0\)
> > diff --git a/ld/testsuite/ld-cdtest/cdtest.dat b/ld/testsuite/ld-cdtest/cdtest.dat
> > index 39be0dbc2c7..c0bdffb3c26 100644
> > --- a/ld/testsuite/ld-cdtest/cdtest.dat
> > +++ b/ld/testsuite/ld-cdtest/cdtest.dat
> > @@ -1,15 +1,15 @@
> > -Constructing Foo(1) "static_foo"
> > -Constructing Foo(2) "static_foo"
> > -Constructing Foo(3) "automatic_foo"
> > -Constructing Foo(4) "default-foo"
> > -Initializing Foo(5) "default-foo" with Foo(4)
> > -Destructing Foo(4) "default-foo" (remaining foos: 4)
> > -Constructing Foo(5) "other_foo1"
> > -Constructing Foo(6) "other_foo2"
> > -Copying Foo(5) "other_foo1" to Foo(6)
> > -Destructing Foo(6) "other_foo1" (remaining foos: 5)
> > -Destructing Foo(5) "other_foo1" (remaining foos: 4)
> > -Destructing Foo(5) "default-foo" (remaining foos: 3)
> > -Destructing Foo(3) "automatic_foo" (remaining foos: 2)
> > -Destructing Foo(2) "static_foo" (remaining foos: 1)
> > -Destructing Foo(1) "static_foo" (remaining foos: 0)
> > +Constructing Foo\(1\) "static_foo"
> > +Constructing Foo\(2\) "static_foo"
> > +Constructing Foo\(3\) "automatic_foo"
> > +Constructing Foo\(4\) "default-foo"
> > +Initializing Foo\(5\) "default-foo" with Foo\(4\)
> > +Destructing Foo\(4\) "default-foo" \(remaining foos: 4\)
> > +Constructing Foo\(5\) "other_foo1"
> > +Constructing Foo\(6\) "other_foo2"
> > +Copying Foo\(5\) "other_foo1" to Foo\(6\)
> > +Destructing Foo\(6\) "other_foo1" \(remaining foos: 5\)
> > +Destructing Foo\(5\) "other_foo1" \(remaining foos: 4\)
> > +Destructing Foo\(5\) "default-foo" \(remaining foos: 3\)
> > +Destructing Foo\(3\) "automatic_foo" \(remaining foos: 2\)
> > +Destructing Foo\(2\) "static_foo" \(remaining foos: 1\)
> > +Destructing Foo\(1\) "static_foo" \(remaining foos: 0\)
> > diff --git a/ld/testsuite/ld-cdtest/cdtest.exp b/ld/testsuite/ld-cdtest/cdtest.exp
> > index 89fdd581abb..81547af3c9e 100644
> > --- a/ld/testsuite/ld-cdtest/cdtest.exp
> > +++ b/ld/testsuite/ld-cdtest/cdtest.exp
> > @@ -28,11 +28,7 @@ set test1 "cdtest"
> >  set test2 "cdtest with -Ur"
> >
> >  # This test requires running the executable generated by ld.
> > -if ![isnative] {
> > -    return
> > -}
> > -
> > -if { [which $CXX_FOR_TARGET] == 0 } {
> > +if { [which $CXX_FOR_TARGET] == 0 || ![check_execution_available] } {
> >      untested $test1
> >      untested $test2
> >      return
> > @@ -51,44 +47,39 @@ set expected_output "$srcdir/$subdir/cdtest.dat"
> >  if ![ld_link $CC_FOR_TARGET tmpdir/cdtest "$CFLAGS_FOR_TARGET tmpdir/cdtest-foo.o tmpdir/cdtest-bar.o tmpdir/cdtest-main.o"] {
> >      fail $test1
> >  } else {
> > -    send_log   "tmpdir/cdtest >tmpdir/cdtest.out\n"
> > -    verbose    "tmpdir/cdtest >tmpdir/cdtest.out"
> > -    catch "exec tmpdir/cdtest >tmpdir/cdtest.out" exec_output
> > +    set failed 0
> >
> > -    if ![string match "" $exec_output] then {
> > +    send_log "Running: tmpdir/cdtest\n"
> > +    verbose "Running: tmpdir/cdtest"
> > +    set state [remote_load target tmpdir/cdtest]
> > +    set status [lindex $state 0]
> > +    set exec_output [lindex $state 1]
> > +
> > +    if { $status != "pass"  } {
> >         send_log "$exec_output\n"
> >         verbose "$exec_output" 1
> > -
> > -       fail $test1
> > +       set failed 1
> >      } else {
> > -       send_log   "diff tmpdir/cdtest.out $expected_output\n"
> > -       verbose    "diff tmpdir/cdtest.out $expected_output"
> > -       catch "exec diff tmpdir/cdtest.out $expected_output" exec_output
> > -       set exec_output [prune_warnings $exec_output]
> > -
> > -       if ![string match "" $exec_output] then {
> > -           send_log "$exec_output\n"
> > -           verbose  "$exec_output" 1
> > +       set output_filename "tmpdir/cdtest.out"
> > +       set_file_contents $output_filename $exec_output
> >
> > +       send_log [file_contents $output_filename]
> > +       verbose [file_contents $output_filename] 2
> > +       if [regexp_diff $output_filename $expected_output] {
> >             send_log "Checking against Named Return Value optimization\n"
> >             verbose  "Checking against Named Return Value optimization" 1
> >
> >             set expected_output "$srcdir/$subdir/cdtest-nrv.dat"
> > -
> > -           send_log   "diff tmpdir/cdtest.out $expected_output\n"
> > -           verbose    "diff tmpdir/cdtest.out $expected_output"
> > -           catch "exec diff tmpdir/cdtest.out $expected_output" exec_output
> > -           set exec_output [prune_warnings $exec_output]
> > +           if [regexp_diff $output_filename $expected_output] {
> > +               set failed 1
> > +           }
> >         }
> > +    }
> >
> > -       if [string match "" $exec_output] then {
> > -           pass $test1
> > -       } else {
> > -           send_log "$exec_output\n"
> > -           verbose  "$exec_output" 1
> > -
> > -           fail $test1
> > -       }
> > +    if { $failed != 0 } {
> > +       fail $test1
> > +    } else {
> > +       pass $test1
> >      }
> >  }
> >
> > @@ -103,29 +94,33 @@ if ![ld_relocate $ld tmpdir/cdtest.o {-Ur tmpdir/cdtest-foo.o tmpdir/cdtest-bar.
> >      if ![ld_link $CC_FOR_TARGET tmpdir/cdtest "$CFLAGS_FOR_TARGET tmpdir/cdtest.o"] {
> >         fail $test2
> >      } else {
> > -       send_log   "tmpdir/cdtest >tmpdir/cdtest.out\n"
> > -       verbose    "tmpdir/cdtest >tmpdir/cdtest.out"
> > -       catch "exec tmpdir/cdtest >tmpdir/cdtest.out" exec_output
> > +       set failed 0
> > +
> > +       send_log "Running: tmpdir/cdtest\n"
> > +       verbose "Running: tmpdir/cdtest"
> > +       set state [remote_load target tmpdir/cdtest]
> > +       set status [lindex $state 0]
> > +       set exec_output [lindex $state 1]
> >
> > -       if ![string match "" $exec_output] then {
> > +       if { $status != "pass" } {
> >             send_log "$exec_output\n"
> > -           verbose  "$exec_output" 1
> > +           verbose "$exec_output" 1
> > +           set failed 1
> > +       } else {
> > +           set output_filename "tmpdir/cdtest.out"
> > +           set_file_contents $output_filename $exec_output
> >
> > +           send_log [file_contents $output_filename]
> > +           verbose [file_contents $output_filename] 2
> > +           if [regexp_diff $output_filename $expected_output] {
> > +               set failed 1
> > +           }
> > +       }
> > +
> > +       if { $failed != 0 } {
> >             fail $test2
> >         } else {
> > -           send_log   "diff tmpdir/cdtest.out $expected_output\n"
> > -           verbose    "diff tmpdir/cdtest.out $expected_output"
> > -           catch "exec diff tmpdir/cdtest.out $expected_output" exec_output
> > -           set exec_output [prune_warnings $exec_output]
> > -
> > -           if [string match "" $exec_output] then {
> > -               pass $test2
> > -           } else {
> > -               send_log "$exec_output\n"
> > -               verbose  "$exec_output" 1
> > -
> > -               fail $test2
> > -           }
> > +           pass $test2
> >         }
> >      }
> >  }
> > --
> > 2.43.0
> >

From haochen.jiang@intel.com  Tue Jun 30 08:11:26 2026
From: haochen.jiang@intel.com (Haochen Jiang)
Date: Tue, 30 Jun 2026 16:11:26 +0800
Subject: [PATCH] x86: Disable AMX-TF32 by default
Message-ID: <20260630081126.3508651-1-haochen.jiang@intel.com>

Hi all,

AMX-TF32 got depublished in ISE062. Just like AMX-TRANSPOSE, we
will keep the AMX-TF32 support for now in case there are x86 vendors
want to utilize the feature. AMX-TF32 will not show up on any
Intel/AMD hardware. Also in foreseeable future, no hardware will
support AMX-TF32, we will disable it by default. For testcases,
we will simply add .arch .amx_tf32 to keep the original test
intuition.

Tested on x86-64. Ok for trunk?

Thx,
Haochen

gas/ChangeLog:

        * testsuite/gas/i386/x86-64-amx-tf32.s: Add .amx_tf32.
        * testsuite/gas/i386/x86-64-amx-tf32-inval.s: Ditto.
        * testsuite/gas/i386/x86-64-amx-transpose.s: Ditto.
        * testsuite/gas/i386/x86-64-amx-transpose-inval.s: Ditto.
        * testsuite/gas/i386/x86-64-amx-tf32-inval.l: Adjust line
	number.
        * testsuite/gas/i386/x86-64-amx-transpose-inval.l: Ditto.

opcodes/ChangeLog:

        * i386-gen.c: Disable AMX-TF32 by default.
        * i386-init.h: Regenerated.
---
 .../gas/i386/x86-64-amx-tf32-inval.l          |  2 +-
 .../gas/i386/x86-64-amx-tf32-inval.s          |  1 +
 gas/testsuite/gas/i386/x86-64-amx-tf32.s      |  1 +
 .../gas/i386/x86-64-amx-transpose-inval.l     | 24 +++++++++----------
 .../gas/i386/x86-64-amx-transpose-inval.s     |  1 +
 gas/testsuite/gas/i386/x86-64-amx-transpose.s |  1 +
 opcodes/i386-gen.c                            |  2 +-
 opcodes/i386-init.h                           |  2 +-
 8 files changed, 19 insertions(+), 15 deletions(-)

diff --git a/gas/testsuite/gas/i386/x86-64-amx-tf32-inval.l b/gas/testsuite/gas/i386/x86-64-amx-tf32-inval.l
index 2ac207f90ca..81db933e346 100644
--- a/gas/testsuite/gas/i386/x86-64-amx-tf32-inval.l
+++ b/gas/testsuite/gas/i386/x86-64-amx-tf32-inval.l
@@ -1,4 +1,4 @@
 .* Assembler messages:
-.*:5: Error: all tmm registers must be distinct for `tmmultf32ps'
 .*:6: Error: all tmm registers must be distinct for `tmmultf32ps'
 .*:7: Error: all tmm registers must be distinct for `tmmultf32ps'
+.*:8: Error: all tmm registers must be distinct for `tmmultf32ps'
diff --git a/gas/testsuite/gas/i386/x86-64-amx-tf32-inval.s b/gas/testsuite/gas/i386/x86-64-amx-tf32-inval.s
index 7357c3c392f..c7b4538e300 100644
--- a/gas/testsuite/gas/i386/x86-64-amx-tf32-inval.s
+++ b/gas/testsuite/gas/i386/x86-64-amx-tf32-inval.s
@@ -1,6 +1,7 @@
 # Check Illegal 64bit AMX-TF32 instructions
 
 	.text
+	.arch .amx_tf32
 _start:
 	tmmultf32ps	%tmm1, %tmm1, %tmm2
 	tmmultf32ps	%tmm1, %tmm2, %tmm1
diff --git a/gas/testsuite/gas/i386/x86-64-amx-tf32.s b/gas/testsuite/gas/i386/x86-64-amx-tf32.s
index bb82380da48..c7a4667b04f 100644
--- a/gas/testsuite/gas/i386/x86-64-amx-tf32.s
+++ b/gas/testsuite/gas/i386/x86-64-amx-tf32.s
@@ -1,6 +1,7 @@
 # Check 64bit AMX-TF32 instructions
 
 	.text
+	.arch .amx_tf32
 _start:
 	tmmultf32ps	%tmm4, %tmm5, %tmm6
 	tmmultf32ps	%tmm1, %tmm2, %tmm3
diff --git a/gas/testsuite/gas/i386/x86-64-amx-transpose-inval.l b/gas/testsuite/gas/i386/x86-64-amx-transpose-inval.l
index 02ad60d8343..406be53fa2c 100644
--- a/gas/testsuite/gas/i386/x86-64-amx-transpose-inval.l
+++ b/gas/testsuite/gas/i386/x86-64-amx-transpose-inval.l
@@ -4,16 +4,15 @@
 .*:7: Error: `t2rpntlvwz1rs' is not supported on `x86_64'
 .*:8: Error: `t2rpntlvwz1rst1' is not supported on `x86_64'
 .*:9: Error: `ttmmultf32ps' is not supported on `x86_64'
-.*:13: Error: all tmm registers must be distinct for `ttdpbf16ps'
 .*:14: Error: all tmm registers must be distinct for `ttdpbf16ps'
 .*:15: Error: all tmm registers must be distinct for `ttdpbf16ps'
-.*:16: Error: all tmm registers must be distinct for `ttdpfp16ps'
+.*:16: Error: all tmm registers must be distinct for `ttdpbf16ps'
 .*:17: Error: all tmm registers must be distinct for `ttdpfp16ps'
 .*:18: Error: all tmm registers must be distinct for `ttdpfp16ps'
-.*:19: Error: all tmm registers must be distinct for `ttmmultf32ps'
+.*:19: Error: all tmm registers must be distinct for `ttdpfp16ps'
 .*:20: Error: all tmm registers must be distinct for `ttmmultf32ps'
 .*:21: Error: all tmm registers must be distinct for `ttmmultf32ps'
-.*:22: Error: `\(%rip\)' cannot be used here
+.*:22: Error: all tmm registers must be distinct for `ttmmultf32ps'
 .*:23: Error: `\(%rip\)' cannot be used here
 .*:24: Error: `\(%rip\)' cannot be used here
 .*:25: Error: `\(%rip\)' cannot be used here
@@ -21,11 +20,12 @@
 .*:27: Error: `\(%rip\)' cannot be used here
 .*:28: Error: `\(%rip\)' cannot be used here
 .*:29: Error: `\(%rip\)' cannot be used here
-.*:30: Warning: operand 2 `%tmm1' implicitly denotes `%tmm0' to `%tmm1' group in `t2rpntlvwz0'
-.*:31: Warning: operand 2 `%tmm3' implicitly denotes `%tmm2' to `%tmm3' group in `t2rpntlvwz0t1'
-.*:32: Warning: operand 2 `%tmm5' implicitly denotes `%tmm4' to `%tmm5' group in `t2rpntlvwz1'
-.*:33: Warning: operand 2 `%tmm7' implicitly denotes `%tmm6' to `%tmm7' group in `t2rpntlvwz1t1'
-.*:34: Warning: operand 2 `%tmm1' implicitly denotes `%tmm0' to `%tmm1' group in `t2rpntlvwz0rs'
-.*:35: Warning: operand 2 `%tmm3' implicitly denotes `%tmm2' to `%tmm3' group in `t2rpntlvwz0rst1'
-.*:36: Warning: operand 2 `%tmm5' implicitly denotes `%tmm4' to `%tmm5' group in `t2rpntlvwz1rs'
-.*:37: Warning: operand 2 `%tmm7' implicitly denotes `%tmm6' to `%tmm7' group in `t2rpntlvwz1rst1'
+.*:30: Error: `\(%rip\)' cannot be used here
+.*:31: Warning: operand 2 `%tmm1' implicitly denotes `%tmm0' to `%tmm1' group in `t2rpntlvwz0'
+.*:32: Warning: operand 2 `%tmm3' implicitly denotes `%tmm2' to `%tmm3' group in `t2rpntlvwz0t1'
+.*:33: Warning: operand 2 `%tmm5' implicitly denotes `%tmm4' to `%tmm5' group in `t2rpntlvwz1'
+.*:34: Warning: operand 2 `%tmm7' implicitly denotes `%tmm6' to `%tmm7' group in `t2rpntlvwz1t1'
+.*:35: Warning: operand 2 `%tmm1' implicitly denotes `%tmm0' to `%tmm1' group in `t2rpntlvwz0rs'
+.*:36: Warning: operand 2 `%tmm3' implicitly denotes `%tmm2' to `%tmm3' group in `t2rpntlvwz0rst1'
+.*:37: Warning: operand 2 `%tmm5' implicitly denotes `%tmm4' to `%tmm5' group in `t2rpntlvwz1rs'
+.*:38: Warning: operand 2 `%tmm7' implicitly denotes `%tmm6' to `%tmm7' group in `t2rpntlvwz1rst1'
diff --git a/gas/testsuite/gas/i386/x86-64-amx-transpose-inval.s b/gas/testsuite/gas/i386/x86-64-amx-transpose-inval.s
index 7bbc1babb17..a2d8d3818b4 100644
--- a/gas/testsuite/gas/i386/x86-64-amx-transpose-inval.s
+++ b/gas/testsuite/gas/i386/x86-64-amx-transpose-inval.s
@@ -9,6 +9,7 @@ _start:
 	ttmmultf32ps	%tmm1, %tmm2, %tmm3
 
 	.arch .amx_transpose
+	.arch .amx_tf32
 _transpose:
 	ttdpbf16ps	%tmm1, %tmm1, %tmm2
 	ttdpbf16ps	%tmm1, %tmm2, %tmm1
diff --git a/gas/testsuite/gas/i386/x86-64-amx-transpose.s b/gas/testsuite/gas/i386/x86-64-amx-transpose.s
index ef4a72a0cae..885a1a68391 100644
--- a/gas/testsuite/gas/i386/x86-64-amx-transpose.s
+++ b/gas/testsuite/gas/i386/x86-64-amx-transpose.s
@@ -1,6 +1,7 @@
 # Check 64bit AMX-TRANSPOSE instructions
 
 	.arch .amx_transpose
+	.arch .amx_tf32
 	.text
 _start:
 	ttdpbf16ps	%tmm4, %tmm5, %tmm6
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index be580d48a18..dd8f936edcd 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -47,7 +47,7 @@ typedef struct dependency
 static const dependency isa_dependencies[] =
 {
   { "UNKNOWN",
-    "~(IAMCU|MPX|AMX_TRANSPOSE)" },
+    "~(IAMCU|MPX|AMX_TRANSPOSE|AMX_TF32)" },
   { "GENERIC32",
     "386" },
   { "GENERIC64",
-- 
2.31.1


From jdx@o2.pl  Tue Jun 30 08:19:41 2026
From: jdx@o2.pl (Jan Dubiec)
Date: Tue, 30 Jun 2026 10:19:41 +0200
Subject: [PATCH] ld: Skip p33265-2 and pr33265-2 tests on Windows
In-Reply-To: <01119d26-0ae4-4a32-af55-9f913756d8c8@suse.com>
References: <20260629072757.72898-1-jdx@o2.pl>
 <01119d26-0ae4-4a32-af55-9f913756d8c8@suse.com>
Message-ID: <0f4a5f34-fdae-4620-b3e3-10b90f165e00@o2.pl>

On 29.06.2026 09:54, Jan Beulich wrote:
> On 29.06.2026 09:27, Jan Dubiec wrote:
>> These tests are expected to fail on Windows because by default maximum path length
>> is only 260 characters:
>> https://learn.microsoft.com/en-us/windows/win32/fileio/maximum-file-path-limitation?tabs=registry
>>
>> Theoretically the issue could be fixed in two ways, as pointed in the linked article:
>>     1. using the "\\?\" prefix, but this probably requires a lot of work
>>     and should be done "binutils-wide", i.e. all tools should be reviewed
>>     from this point of view,
>>     2. using manifest file, but this still would require an action from
>>     the user ? they would have to turn on long paths support in the
>>     Windows registry.
> 
> Based on this, imo the two tests should become XFAILs instead of being excluded
> altogether. However, ...

I agree, but I wanted the patch be "in spirit of" pr24576-1 and 
pr24576-2 related patch which was posted here in February. Also 
binutils' test framework does not offer an elegant way to xfail a test 
depending on *host*. At least I don't know such a way?

> 
>> Excerpt from the log:
>> [...]
>> PASS: ld-scripts/pr33265-1
>> /d/Works/xcomp/build-binutils-h8300-mingw/ld/../gas/as-new     -o tmpdir/start.o /d/Works/binutils/ld/testsuite/ld-scripts/start.s
>> Executing on host: sh -c {/d/Works/xcomp/build-binutils-h8300-mingw/ld/../gas/as-new     -o tmpdir/start.o /d/Works/binutils/ld/testsuite/ld-scripts/start.s 2>&1}  /dev/null dump.tmp (timeout = 300)
>> spawn [open ...]
>> ./ld-new   -L/d/Works/binutils/ld/testsuite/ld-scripts  -r --whole-archive -lpr33265-2 -o tmpdir/dump tmpdir/start.o
>> Executing on host: sh -c {./ld-new   -L/d/Works/binutils/ld/testsuite/ld-scripts  -r --whole-archive -lpr33265-2 -o tmpdir/dump tmpdir/start.o  2>&1}  /dev/null dump.tmp (timeout = 300)
>> spawn [open ...]
>> D:\Works\xcomp\build-binutils-h8300-mingw\ld\ld-new.exe: cannot open linker script file D:/Works/binutils/ld/testsuite/ld-scripts\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\./././././/libpr33265-2.a: No such file or directory
> 
> ... where are these absurd paths coming from? If there wasn't this excessive
> referencing of the current directory, not problem would arise in the first
> place, as it looks.

 From ld/testsuite/ld-scripts/libpr33265-2.a which recursively includes 
itself:
GROUP ( ./././././/libpr33265-2.a )

The recursion depth is set to 100 (MAX_NESTED_GROUP_DEPTH in ldlang.c) 
and that's why the path is so weird. On Linux the tests pass because 
max. path length is ~4KiB there, on Windows they fail because default 
max. path length is ~16x smaller.

The tests pass on Windows when one sets MAX_NESTED_GROUP_DEPTH to a 
small value, e.g. 20.

> 
>> --- a/ld/testsuite/ld-scripts/script.exp
>> +++ b/ld/testsuite/ld-scripts/script.exp
>> @@ -246,7 +246,11 @@ run_dump_test "segment-start" {{name (overridden)} \
>>   			       {ld -Ttext-segment=0x10000000}}
>>   
>>   run_dump_test "pr33265-1"
>> -run_dump_test "pr33265-2"
>> -run_dump_test "pr33265-3"
>> +# On Windows hosts the following two cases are expected to fail because
>> +# by default maximum path length is only 260 characters.
>> +if { ![ishost *-mingw*] } {
>> +    run_dump_test "pr33265-2"
>> +    run_dump_test "pr33265-3"
>> +}
> 
> What about Cygwin? Does this somehow circumvent the issue?

I have no idea. But I bet that there is no such problem.

> 
> Jan

Jan D.


From haochen.jiang@intel.com  Tue Jun 30 08:42:53 2026
From: haochen.jiang@intel.com (Jiang, Haochen)
Date: Tue, 30 Jun 2026 08:42:53 +0000
Subject: [PATCH v1 2/2] Support x86 ACE ISA
In-Reply-To: <20260627115338.1632761-1-Ganesh.Gopalasubramanian@amd.com>
References: <20260627095543.1627012-1-Ganesh.Gopalasubramanian@amd.com>
 <20260627115338.1632761-1-Ganesh.Gopalasubramanian@amd.com>
Message-ID: <IA4PR11MB900905D3BA7803AEAE7B2EE7ECF72@IA4PR11MB9009.namprd11.prod.outlook.com>

> From: Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
> Sent: Saturday, June 27, 2026 7:54 PM
>

Besides the comments Jan and Lin has given,

> diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
> index d82ed061a78..f6f40589d11 100644
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -1200,6 +1201,7 @@ static const arch_entry cpu_arch[] =
>    SUBARCH (pconfig, PCONFIG, PCONFIG, false),
>    SUBARCH (waitpkg, WAITPKG, WAITPKG, false),
>    SUBARCH (cldemote, CLDEMOTE, CLDEMOTE, false),
> +  SUBARCH (ace, ACE, ACE, false),
>    SUBARCH (amx_int8, AMX_INT8, ANY_AMX_INT8, false),
>    SUBARCH (amx_bf16, AMX_BF16, ANY_AMX_BF16, false),
>    SUBARCH (amx_fp16, AMX_FP16, ANY_AMX_FP16, false),

Should we call it as ACEV1 instead of ACE? Documentation mentioned
it as ACEv1.

> @@ -7498,6 +7503,9 @@ i386_assemble (char *line)
>  	case unsupported_rsp_register:
>  	  err_msg = _("'rsp' register cannot be used");
>  	  break;
> +	case unsupported_tile_index:
> +	  err_msg = _("immediate value must be in range 0-15");
> +	  break;

I also think this might not be needed. If I read the pseudocode correctly,
it will read last 4 bit.

> diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
> index 11cc4ff19dc..dded2d906e6 100644
> --- a/opcodes/i386-gen.c
> +++ b/opcodes/i386-gen.c
> @@ -263,6 +263,8 @@ static const dependency isa_dependencies[] =
>      "RTM|HLE" },
>    { "TSXLDTRK",
>      "RTM" },
> +  { "ACE",
> +    "AVX512F|64" },

I have different opinion on this implication. I suppose it should
directly use AVX10_V2_AUX according to documentation CPUID
emulation part. That part clearly showed AVX10_V2_AUX is a must.

Thx,
Haochen

From amodra@gmail.com  Tue Jun 30 09:00:39 2026
From: amodra@gmail.com (Alan Modra)
Date: Tue, 30 Jun 2026 18:30:39 +0930
Subject: [PATCH v2] ld/testsuite: add support for remote testing in
 ld-cdtest
In-Reply-To: <CAJ307Ej5cutoMYAt3hGkubD3VsMc0xXtrQtOeRmEWhG5OLwMzg@mail.gmail.com>
References: <20260618075856.2258643-1-chigot@adacore.com>
 <CAJ307EghSg-BPajFHCG-3HqA5VF0FwoEoE92CMfNW5WWMqu4ug@mail.gmail.com>
 <CAJ307Ej5cutoMYAt3hGkubD3VsMc0xXtrQtOeRmEWhG5OLwMzg@mail.gmail.com>
Message-ID: <akOFtwO3vYCKxO1T@squeak.grove.modra.org>

On Tue, Jun 30, 2026 at 09:55:10AM +0200, Cl?ment Chigot wrote:
> On Thu, Jun 18, 2026 at 10:04?AM Cl?ment Chigot <chigot@adacore.com> wrote:
> >
> > On Thu, Jun 18, 2026 at 9:58?AM Cl?ment Chigot <chigot@adacore.com> wrote:
> > >
> > > This converts the existing to code to use "remote_load" allowing
> > > execution on both native and remote targets.
> > >
> > > The "diff" between the output and the expected result has been
> > > transformed to the usual regexp_diff. The previous could have been
> > > transformed into `remote_exec build diff` but tends to be fickled with
> > > new lines.
> >
> > Arf got Maciej's Redhat email rejected. Trying with macro@orcam.me.uk.
> 
> Gentle ping to Maciej.
> Otherwise, Alan ok to merge in a few days if he doesn't answer ?

Yes.

-- 
Alan Modra

From jbeulich@suse.com  Tue Jun 30 09:08:32 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Tue, 30 Jun 2026 11:08:32 +0200
Subject: [PATCH] ld: Skip p33265-2 and pr33265-2 tests on Windows
In-Reply-To: <0f4a5f34-fdae-4620-b3e3-10b90f165e00@o2.pl>
References: <20260629072757.72898-1-jdx@o2.pl>
 <01119d26-0ae4-4a32-af55-9f913756d8c8@suse.com>
 <0f4a5f34-fdae-4620-b3e3-10b90f165e00@o2.pl>
Message-ID: <db94391e-f7dd-4a3a-8797-2bad2cc81a9d@suse.com>

On 30.06.2026 10:19, Jan Dubiec wrote:
> On 29.06.2026 09:54, Jan Beulich wrote:
>> On 29.06.2026 09:27, Jan Dubiec wrote:
>>> These tests are expected to fail on Windows because by default maximum path length
>>> is only 260 characters:
>>> https://learn.microsoft.com/en-us/windows/win32/fileio/maximum-file-path-limitation?tabs=registry
>>>
>>> Theoretically the issue could be fixed in two ways, as pointed in the linked article:
>>>     1. using the "\\?\" prefix, but this probably requires a lot of work
>>>     and should be done "binutils-wide", i.e. all tools should be reviewed
>>>     from this point of view,
>>>     2. using manifest file, but this still would require an action from
>>>     the user ? they would have to turn on long paths support in the
>>>     Windows registry.
>>
>> Based on this, imo the two tests should become XFAILs instead of being excluded
>> altogether. However, ...
> 
> I agree, but I wanted the patch be "in spirit of" pr24576-1 and 
> pr24576-2 related patch which was posted here in February. Also 
> binutils' test framework does not offer an elegant way to xfail a test 
> depending on *host*. At least I don't know such a way?

Can't the [ishost ...] you present use in the .exp file equally be used
in the .d files:

#xfail: [ishost *-mingw*]

?

>>> Excerpt from the log:
>>> [...]
>>> PASS: ld-scripts/pr33265-1
>>> /d/Works/xcomp/build-binutils-h8300-mingw/ld/../gas/as-new     -o tmpdir/start.o /d/Works/binutils/ld/testsuite/ld-scripts/start.s
>>> Executing on host: sh -c {/d/Works/xcomp/build-binutils-h8300-mingw/ld/../gas/as-new     -o tmpdir/start.o /d/Works/binutils/ld/testsuite/ld-scripts/start.s 2>&1}  /dev/null dump.tmp (timeout = 300)
>>> spawn [open ...]
>>> ./ld-new   -L/d/Works/binutils/ld/testsuite/ld-scripts  -r --whole-archive -lpr33265-2 -o tmpdir/dump tmpdir/start.o
>>> Executing on host: sh -c {./ld-new   -L/d/Works/binutils/ld/testsuite/ld-scripts  -r --whole-archive -lpr33265-2 -o tmpdir/dump tmpdir/start.o  2>&1}  /dev/null dump.tmp (timeout = 300)
>>> spawn [open ...]
>>> D:\Works\xcomp\build-binutils-h8300-mingw\ld\ld-new.exe: cannot open linker script file D:/Works/binutils/ld/testsuite/ld-scripts\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\././././.\./././././/libpr33265-2.a: No such file or directory
>>
>> ... where are these absurd paths coming from? If there wasn't this excessive
>> referencing of the current directory, not problem would arise in the first
>> place, as it looks.
> 
>  From ld/testsuite/ld-scripts/libpr33265-2.a which recursively includes 
> itself:
> GROUP ( ./././././/libpr33265-2.a )
> 
> The recursion depth is set to 100 (MAX_NESTED_GROUP_DEPTH in ldlang.c) 
> and that's why the path is so weird. On Linux the tests pass because 
> max. path length is ~4KiB there, on Windows they fail because default 
> max. path length is ~16x smaller.
> 
> The tests pass on Windows when one sets MAX_NESTED_GROUP_DEPTH to a 
> small value, e.g. 20.

I see.

>>> --- a/ld/testsuite/ld-scripts/script.exp
>>> +++ b/ld/testsuite/ld-scripts/script.exp
>>> @@ -246,7 +246,11 @@ run_dump_test "segment-start" {{name (overridden)} \
>>>   			       {ld -Ttext-segment=0x10000000}}
>>>   
>>>   run_dump_test "pr33265-1"
>>> -run_dump_test "pr33265-2"
>>> -run_dump_test "pr33265-3"
>>> +# On Windows hosts the following two cases are expected to fail because
>>> +# by default maximum path length is only 260 characters.
>>> +if { ![ishost *-mingw*] } {
>>> +    run_dump_test "pr33265-2"
>>> +    run_dump_test "pr33265-3"
>>> +}
>>
>> What about Cygwin? Does this somehow circumvent the issue?
> 
> I have no idea. But I bet that there is no such problem.

Is this betting of yours backed by any insight you have? (If we're uncertain,
I think at least the commit message should mention this fact. If later someone
notices the same issue on Cygwin, they'd know right away what to do about it.)

Jan

From jbeulich@suse.com  Tue Jun 30 09:17:04 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Tue, 30 Jun 2026 11:17:04 +0200
Subject: [PATCH v1 2/2] Support x86 ACE ISA
In-Reply-To: <IA4PR11MB900905D3BA7803AEAE7B2EE7ECF72@IA4PR11MB9009.namprd11.prod.outlook.com>
References: <20260627095543.1627012-1-Ganesh.Gopalasubramanian@amd.com>
 <20260627115338.1632761-1-Ganesh.Gopalasubramanian@amd.com>
 <IA4PR11MB900905D3BA7803AEAE7B2EE7ECF72@IA4PR11MB9009.namprd11.prod.outlook.com>
Message-ID: <fd28114f-f3b1-4219-924a-3cdee31d4551@suse.com>

On 30.06.2026 10:42, Jiang, Haochen wrote:
>> From: Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
>> Sent: Saturday, June 27, 2026 7:54 PM
>>
>> --- a/gas/config/tc-i386.c
>> +++ b/gas/config/tc-i386.c
>> @@ -1200,6 +1201,7 @@ static const arch_entry cpu_arch[] =
>>    SUBARCH (pconfig, PCONFIG, PCONFIG, false),
>>    SUBARCH (waitpkg, WAITPKG, WAITPKG, false),
>>    SUBARCH (cldemote, CLDEMOTE, CLDEMOTE, false),
>> +  SUBARCH (ace, ACE, ACE, false),
>>    SUBARCH (amx_int8, AMX_INT8, ANY_AMX_INT8, false),
>>    SUBARCH (amx_bf16, AMX_BF16, ANY_AMX_BF16, false),
>>    SUBARCH (amx_fp16, AMX_FP16, ANY_AMX_FP16, false),
> 
> Should we call it as ACEV1 instead of ACE? Documentation mentioned
> it as ACEv1.

Perhaps. We have "avx10.1" and "avx10.2" as .arch specifiers as well. So
perhaps "ace_v1" as counterpart ("acev1" being a little odd without
separator)?

>> --- a/opcodes/i386-gen.c
>> +++ b/opcodes/i386-gen.c
>> @@ -263,6 +263,8 @@ static const dependency isa_dependencies[] =
>>      "RTM|HLE" },
>>    { "TSXLDTRK",
>>      "RTM" },
>> +  { "ACE",
>> +    "AVX512F|64" },
> 
> I have different opinion on this implication. I suppose it should
> directly use AVX10_V2_AUX according to documentation CPUID
> emulation part. That part clearly showed AVX10_V2_AUX is a must.

+1

Jan

From jbeulich@suse.com  Tue Jun 30 09:26:36 2026
From: jbeulich@suse.com (Jan Beulich)
Date: Tue, 30 Jun 2026 11:26:36 +0200
Subject: [PATCH] x86: Disable AMX-TF32 by default
In-Reply-To: <20260630081126.3508651-1-haochen.jiang@intel.com>
References: <20260630081126.3508651-1-haochen.jiang@intel.com>
Message-ID: <2297833d-6863-47dc-8600-3004b44a9fe8@suse.com>

On 30.06.2026 10:11, Haochen Jiang wrote:
> AMX-TF32 got depublished in ISE062. Just like AMX-TRANSPOSE, we
> will keep the AMX-TF32 support for now in case there are x86 vendors
> want to utilize the feature. AMX-TF32 will not show up on any
> Intel/AMD hardware. Also in foreseeable future, no hardware will
> support AMX-TF32, we will disable it by default. For testcases,
> we will simply add .arch .amx_tf32 to keep the original test
> intuition.
> 
> Tested on x86-64. Ok for trunk?

Yes.

Jan

From rearnsha@arm.com  Tue Jun 30 09:41:56 2026
From: rearnsha@arm.com (Richard Earnshaw)
Date: Tue, 30 Jun 2026 10:41:56 +0100
Subject: [PATCH v3 0/7] aarch64: deprecate some ISA features
Message-ID: <20260630094203.2328048-1-rearnsha@arm.com>

A couple of features which were specified in the architecture, but
never implemented in products have been withdrawn.  This short series
adjusts the assembler to warn if they are used in real code.  The
intent is to ultimately remove support entirely from the tools, but
we'll do that in stages and deprecation is the first step.

I've taken a slightly different approach this time for the MPAMv2_VID
changes, opting to use git reverts for most of the removal.  The
reverts don't apply completely cleanly due to subsequent updates, but
the conflict wasn't hard to resolve.

I'd like to get this committed some time this week, so that it's in
with plenty of time before for the upcoming branch.

Changes since v1:

 - Incorporate most of the feedback from Jan

Changes since v2:
 - Rework the MPAMv2_VID changes to cover the MLBI instruction and
   remove the +mpamv2 architecture feature flag.


Richard Earnshaw (7):
  aarch64: Remove a stray comment from opcode/aarch64.h
  aarch64: warn if the TME feature is used during assembly.
  aarch64: remove MLBI from sys-rt-alias test.
  Revert "aarch64: Add support for MLBI system instructions"
  Revert "aarch64: Add FEAT_MPAMv2_VID system registers"
  aarch64: Remove +mpamv2 feature option
  NEWS: Update for withdrawal of the MPAMv2_VID feature.

 gas/NEWS                                      |  6 +++
 gas/config/tc-aarch64.c                       | 37 +++++++++++--------
 gas/doc/c-aarch64.texi                        |  2 -
 gas/testsuite/gas/aarch64/mlbi-1.d            | 14 -------
 gas/testsuite/gas/aarch64/mlbi-1.s            |  9 -----
 gas/testsuite/gas/aarch64/mlbi-invalid-1.d    |  3 --
 gas/testsuite/gas/aarch64/mlbi-invalid-1.l    |  7 ----
 gas/testsuite/gas/aarch64/mlbi-invalid-1.s    |  9 -----
 gas/testsuite/gas/aarch64/mlbi-invalid-2.d    |  4 --
 gas/testsuite/gas/aarch64/mlbi-invalid-2.l    | 13 -------
 gas/testsuite/gas/aarch64/sys-rt-alias.d      |  2 -
 gas/testsuite/gas/aarch64/sys-rt-alias.s      |  2 -
 gas/testsuite/gas/aarch64/sysreg/mpamv2-bad.d |  2 +-
 gas/testsuite/gas/aarch64/sysreg/mpamv2.d     |  2 +-
 .../gas/aarch64/sysreg/mpamv2_vid-bad.d       |  3 --
 .../gas/aarch64/sysreg/mpamv2_vid-bad.l       | 13 -------
 gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.d | 14 -------
 gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.s |  5 ---
 gas/testsuite/gas/aarch64/tme-warn.l          | 15 ++++++++
 gas/testsuite/gas/aarch64/tme.d               |  1 +
 include/opcode/aarch64.h                      | 12 +++---
 opcodes/aarch64-asm-2.c                       |  2 -
 opcodes/aarch64-dis-2.c                       |  4 --
 opcodes/aarch64-dis.c                         |  1 -
 opcodes/aarch64-opc-2.c                       |  1 -
 opcodes/aarch64-opc.c                         | 10 -----
 opcodes/aarch64-sys-regs.def                  | 11 ++----
 opcodes/aarch64-tbl-2.h                       |  1 -
 opcodes/aarch64-tbl.h                         | 18 +++------
 29 files changed, 60 insertions(+), 163 deletions(-)
 delete mode 100644 gas/testsuite/gas/aarch64/mlbi-1.d
 delete mode 100644 gas/testsuite/gas/aarch64/mlbi-1.s
 delete mode 100644 gas/testsuite/gas/aarch64/mlbi-invalid-1.d
 delete mode 100644 gas/testsuite/gas/aarch64/mlbi-invalid-1.l
 delete mode 100644 gas/testsuite/gas/aarch64/mlbi-invalid-1.s
 delete mode 100644 gas/testsuite/gas/aarch64/mlbi-invalid-2.d
 delete mode 100644 gas/testsuite/gas/aarch64/mlbi-invalid-2.l
 delete mode 100644 gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.d
 delete mode 100644 gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.l
 delete mode 100644 gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.d
 delete mode 100644 gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.s
 create mode 100644 gas/testsuite/gas/aarch64/tme-warn.l

-- 
2.43.0


From rearnsha@arm.com  Tue Jun 30 09:41:57 2026
From: rearnsha@arm.com (Richard Earnshaw)
Date: Tue, 30 Jun 2026 10:41:57 +0100
Subject: [PATCH v3 1/7] aarch64: Remove a stray comment from opcode/aarch64.h
In-Reply-To: <20260630094203.2328048-1-rearnsha@arm.com>
References: <20260630094203.2328048-1-rearnsha@arm.com>
Message-ID: <20260630094203.2328048-2-rearnsha@arm.com>

When flag bit 28 was removed in an earlier patch, the comment describing
it was left behind.  This just cleans that up.
---
 include/opcode/aarch64.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 6d1b414444a..f51045210c9 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1479,7 +1479,7 @@ extern const aarch64_opcode aarch64_opcode_table[];
 #define F_OD(X) (((X) & 0x7) << 24)
 /* Instruction has the field of 'sz'.  */
 #define F_LSE_SZ (1 << 27)
-/* Require an exact qualifier match, even for NIL qualifiers.  */
+
 
 #define F_SYS_READ (1ULL << 29)
 /* This system instruction is used to write system registers.  */
-- 
2.43.0


From rearnsha@arm.com  Tue Jun 30 09:41:58 2026
From: rearnsha@arm.com (Richard Earnshaw)
Date: Tue, 30 Jun 2026 10:41:58 +0100
Subject: [PATCH v3 2/7] aarch64: warn if the TME feature is used during
 assembly.
In-Reply-To: <20260630094203.2328048-1-rearnsha@arm.com>
References: <20260630094203.2328048-1-rearnsha@arm.com>
Message-ID: <20260630094203.2328048-3-rearnsha@arm.com>

Arm has obsoleted the unimplemented TME feature.  Warn if instructions
from this feature are encountered.

Also tweak warn_unpredictable_ldst to use const more often, since the
arguments are the same as for the new warn_deprecated function.
---
 gas/NEWS                             |  4 ++++
 gas/config/tc-aarch64.c              | 24 ++++++++++++++++++++++--
 gas/testsuite/gas/aarch64/tme-warn.l | 15 +++++++++++++++
 gas/testsuite/gas/aarch64/tme.d      |  1 +
 include/opcode/aarch64.h             |  8 +++++---
 opcodes/aarch64-tbl.h                | 10 +++++-----
 6 files changed, 52 insertions(+), 10 deletions(-)
 create mode 100644 gas/testsuite/gas/aarch64/tme-warn.l

diff --git a/gas/NEWS b/gas/NEWS
index 4c55a544f25..116d5e62be6 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,9 @@
 -*- text -*-
 
+* The aarch64 TME extension has never been implemented in any products.  Arm
+  has withdrawn it from the architecture.  The assembler will now warn if
+  instructions from the extension are detected during assembly.
+
 * The legacy .vtable_entry and .vtable_inherit directives that were
   needed for versions of GCC prior to gcc-3.0 (when the generic C++
   ABI was adopted) are now considered obsolete.  They are now deprecated
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 9632a5b2a01..587c3588b09 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -8743,9 +8743,9 @@ programmer_friendly_fixup (aarch64_instruction *instr)
 /* Check for loads and stores that will cause unpredictable behavior.  */
 
 static void
-warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
+warn_unpredictable_ldst (const aarch64_instruction *instr, const char *str)
 {
-  aarch64_inst *base = &instr->base;
+  const aarch64_inst *base = &instr->base;
   const aarch64_opcode *opcode = base->opcode;
   const aarch64_opnd_info *opnds = base->operands;
   switch (opcode->iclass)
@@ -8841,6 +8841,25 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
     }
 }
 
+static void
+warn_deprecated (const aarch64_instruction *instr, const char *str)
+{
+  const aarch64_inst *base = &instr->base;
+  const aarch64_opcode *opcode = base->opcode;
+  if (!(opcode->flags & F_DEPRECATED_INSN))
+    return;
+  switch (opcode->iclass)
+    {
+    case tme:
+      as_warn (_("the TME feature has been deprecated -- `%s'"), str);
+      break;
+    default:
+      /* Instruction marked as deprecated, but a suitable warning not
+	 added above.  */
+      abort();
+    }
+}
+
 static void
 force_automatic_sequence_close (void)
 {
@@ -9019,6 +9038,7 @@ md_assemble (char *str)
 	    }
 
 	  warn_unpredictable_ldst (&inst, str);
+	  warn_deprecated (&inst, str);
 
 	  if (inst.reloc.type == BFD_RELOC_UNUSED
 	      || !inst.reloc.need_libopcodes_p)
diff --git a/gas/testsuite/gas/aarch64/tme-warn.l b/gas/testsuite/gas/aarch64/tme-warn.l
new file mode 100644
index 00000000000..ed26e4ed95c
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/tme-warn.l
@@ -0,0 +1,15 @@
+[^:]*: Assembler messages:
+.*: Warning: the TME feature has been deprecated -- `tstart x0'
+.*: Warning: the TME feature has been deprecated -- `tstart X0'
+.*: Warning: the TME feature has been deprecated -- `tstart x15'
+.*: Warning: the TME feature has been deprecated -- `tstart X15'
+.*: Warning: the TME feature has been deprecated -- `tstart x30'
+.*: Warning: the TME feature has been deprecated -- `tstart X30'
+.*: Warning: the TME feature has been deprecated -- `tcommit'
+.*: Warning: the TME feature has been deprecated -- `tcommit'
+.*: Warning: the TME feature has been deprecated -- `ttest x0'
+.*: Warning: the TME feature has been deprecated -- `ttest X30'
+.*: Warning: the TME feature has been deprecated -- `tcancel 0'
+.*: Warning: the TME feature has been deprecated -- `tcancel 65535'
+.*: Warning: the TME feature has been deprecated -- `tcancel 0xffff'
+.*: Warning: the TME feature has been deprecated -- `tcancel 0XA'
diff --git a/gas/testsuite/gas/aarch64/tme.d b/gas/testsuite/gas/aarch64/tme.d
index 24d34ea9561..66527b03921 100644
--- a/gas/testsuite/gas/aarch64/tme.d
+++ b/gas/testsuite/gas/aarch64/tme.d
@@ -1,4 +1,5 @@
 #as: -march=armv8-a+tme
+#warning_output: tme-warn.l
 #objdump: -dr
 
 .* file format .*
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index f51045210c9..709d76c9a79 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1219,6 +1219,7 @@ enum aarch64_insn_class
   sve_shift_tsz_bhsd,
   sve_size_tsz_bhs,
   testbranch,
+  tme,
   cryptosm3,
   cryptosm4,
   dotproduct,
@@ -1479,8 +1480,9 @@ extern const aarch64_opcode aarch64_opcode_table[];
 #define F_OD(X) (((X) & 0x7) << 24)
 /* Instruction has the field of 'sz'.  */
 #define F_LSE_SZ (1 << 27)
-
-
+/* The instruction has been deprecated.  */
+#define F_DEPRECATED_INSN (1 << 28)
+/* This system instruction is used to read system registers.  */
 #define F_SYS_READ (1ULL << 29)
 /* This system instruction is used to write system registers.  */
 #define F_SYS_WRITE (1ULL << 30)
@@ -1542,7 +1544,7 @@ extern const aarch64_opcode aarch64_opcode_table[];
 /* As above, plus PN registers.  */
 #define F_INVALID_IMM_SYMS_3 (3ULL << 42)
 
-/* Next bit is 44, and 28 is also unused.  */
+/* Next bit is 44.  */
 
 /* Instruction constraints.  */
 /* This instruction has a predication constraint on the instruction at PC+4.  */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 518109ecfd6..c6cb5257008 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -3374,7 +3374,7 @@ static const aarch64_feature_set aarch64_feature_mpamv2 =
 #define MEMTAG_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
 #define _TME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
-  { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
+  { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1 | F_DEPRECATED_INSN, 0, 0, NULL }
 #define SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
   { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
     FLAGS | F_INVALID_IMM_SYMS_2, 0, TIED, NULL }
@@ -5154,10 +5154,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   CORE_INSN ("adr",  0x10000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_PCREL21), QL_ADRP, 0),
   CORE_INSN ("adrp", 0x90000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_ADRP), QL_ADRP, 0),
   /* TME Instructions.  */
-  _TME_INSN ("tstart", 0xd5233060, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
-  _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, 0, 0, OP0 (), QL_0, 0),
-  _TME_INSN ("ttest", 0xd5233160, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
-  _TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, 0, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0),
+  _TME_INSN ("tstart", 0xd5233060, 0xffffffe0, tme, 0, OP1 (Rd), QL_I1X, 0),
+  _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, tme, 0, OP0 (), QL_0, 0),
+  _TME_INSN ("ttest", 0xd5233160, 0xffffffe0, tme, 0, OP1 (Rd), QL_I1X, 0),
+  _TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, tme, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0),
   /* SME instructions (aliases for MSR <sysreg> operations.  */
   SME_INSN ("smstart", 0xd503477f, 0xffffffff, sme_start, 0, OP0 (), QL_0, F_SYS_WRITE, 0),
   SME_INSN ("smstop",  0xd503467f, 0xffffffff, sme_stop,  0, OP0 (), QL_0, F_SYS_WRITE, 0),
-- 
2.43.0


From rearnsha@arm.com  Tue Jun 30 09:41:59 2026
From: rearnsha@arm.com (Richard Earnshaw)
Date: Tue, 30 Jun 2026 10:41:59 +0100
Subject: [PATCH v3 3/7] aarch64: remove MLBI from sys-rt-alias test.
In-Reply-To: <20260630094203.2328048-1-rearnsha@arm.com>
References: <20260630094203.2328048-1-rearnsha@arm.com>
Message-ID: <20260630094203.2328048-4-rearnsha@arm.com>

---
 gas/testsuite/gas/aarch64/sys-rt-alias.d | 2 --
 gas/testsuite/gas/aarch64/sys-rt-alias.s | 2 --
 2 files changed, 4 deletions(-)

diff --git a/gas/testsuite/gas/aarch64/sys-rt-alias.d b/gas/testsuite/gas/aarch64/sys-rt-alias.d
index 96c2f6844a8..5967ce9ef5c 100644
--- a/gas/testsuite/gas/aarch64/sys-rt-alias.d
+++ b/gas/testsuite/gas/aarch64/sys-rt-alias.d
@@ -9,8 +9,6 @@ Disassembly of section \.text:
 .*:	d50c8780 	sys	#4, C8, C7, #4, x0
 .*:	d50ca79f 	plbi	alle1
 .*:	d50ca780 	sys	#4, C10, C7, #4, x0
-.*:	d50c709f 	mlbi	alle1
-.*:	d50c7080 	sys	#4, C7, C0, #4, x0
 .*:	d508751f 	ic	iallu
 .*:	d5087500 	sys	#0, C7, C5, #0, x0
 .*:	d50887bf 	tlbi	vale1, xzr
diff --git a/gas/testsuite/gas/aarch64/sys-rt-alias.s b/gas/testsuite/gas/aarch64/sys-rt-alias.s
index 2aa107fa6d9..213acc68790 100644
--- a/gas/testsuite/gas/aarch64/sys-rt-alias.s
+++ b/gas/testsuite/gas/aarch64/sys-rt-alias.s
@@ -5,8 +5,6 @@
 	sys #4, c8, c7, #4, x0  // TLBI ALLE1 with Rt!=31
 	sys #4, c10, c7, #4     // PLBI ALLE1 with Rt=31
 	sys #4, c10, c7, #4, x0 // PLBI ALLE1 with Rt!=31
-	sys #4, c7, c0, #4      // MLBI ALLE1 with Rt=31
-	sys #4, c7, c0, #4, x0  // MLBI ALLE1 with Rt!=31
 	sys #0, c7, c5, #0      // IC IALLU with Rt=31
 	sys #0, c7, c5, #0, x0  // IC IALLU with Rt!=31
 	sys #0, c8, c7, #5, xzr // TLBI VALE1 with Rt=31 (valid Xt form)
-- 
2.43.0


From rearnsha@arm.com  Tue Jun 30 09:42:01 2026
From: rearnsha@arm.com (Richard Earnshaw)
Date: Tue, 30 Jun 2026 10:42:01 +0100
Subject: [PATCH v3 5/7] Revert "aarch64: Add FEAT_MPAMv2_VID system registers"
In-Reply-To: <20260630094203.2328048-1-rearnsha@arm.com>
References: <20260630094203.2328048-1-rearnsha@arm.com>
Message-ID: <20260630094203.2328048-6-rearnsha@arm.com>

This reverts commit 5fc6b09c078532fa4206a350e34d82488b80a5fb.
---
 gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.d |  3 ---
 gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.l | 13 -------------
 gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.d     | 14 --------------
 gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.s     |  5 -----
 opcodes/aarch64-sys-regs.def                      |  3 ---
 5 files changed, 38 deletions(-)
 delete mode 100644 gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.d
 delete mode 100644 gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.l
 delete mode 100644 gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.d
 delete mode 100644 gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.s

diff --git a/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.d b/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.d
deleted file mode 100644
index 5d00da59694..00000000000
--- a/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#as: -march=armv9.4-a -menable-sysreg-checking -I$srcdir/$subdir
-#source: mpamv2_vid.s
-#error_output: mpamv2_vid-bad.l
diff --git a/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.l b/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.l
deleted file mode 100644
index 6ab3d16fba0..00000000000
--- a/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid-bad.l
+++ /dev/null
@@ -1,13 +0,0 @@
-.*: Assembler messages:
-.*: Error: selected processor does not support system register name 'mpamvidcr_el2'
-.*:  Info: macro invoked from here
-.*: Error: selected processor does not support system register name 'mpamvidcr_el2'
-.*:  Info: macro invoked from here
-.*: Error: selected processor does not support system register name 'mpamvidsr_el2'
-.*:  Info: macro invoked from here
-.*: Error: selected processor does not support system register name 'mpamvidsr_el2'
-.*:  Info: macro invoked from here
-.*: Error: selected processor does not support system register name 'mpamvidsr_el3'
-.*:  Info: macro invoked from here
-.*: Error: selected processor does not support system register name 'mpamvidsr_el3'
-.*:  Info: macro invoked from here
diff --git a/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.d b/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.d
deleted file mode 100644
index 88c0c1883d8..00000000000
--- a/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.d
+++ /dev/null
@@ -1,14 +0,0 @@
-#as: -menable-sysreg-checking -march=armv8-a+mpamv2 -I$srcdir/$subdir
-#objdump: -dr
-
-.*:     file format .*
-
-Disassembly of section \.text:
-
-0+ <.*>:
-.*:	d51ca700 	msr	mpamvidcr_el2, x0
-.*:	d53ca700 	mrs	x0, mpamvidcr_el2
-.*:	d51ca720 	msr	mpamvidsr_el2, x0
-.*:	d53ca720 	mrs	x0, mpamvidsr_el2
-.*:	d51ea720 	msr	mpamvidsr_el3, x0
-.*:	d53ea720 	mrs	x0, mpamvidsr_el3
diff --git a/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.s b/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.s
deleted file mode 100644
index 132d48f0781..00000000000
--- a/gas/testsuite/gas/aarch64/sysreg/mpamv2_vid.s
+++ /dev/null
@@ -1,5 +0,0 @@
-.include "sysreg-test-utils.inc"
-
-	rw_sys_reg mpamvidcr_el2
-	rw_sys_reg mpamvidsr_el2
-	rw_sys_reg mpamvidsr_el3
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index 9daa178ed7b..6f9f2b4c0a8 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -929,9 +929,6 @@
   SYSREG ("mpamhcr_el2",	CPENC (3,4,10,4,0),	0,		AARCH64_FEATURE (V8_2A)) /* MPAM */
   SYSREG ("mpamidr_el1",	CPENC (3,0,10,4,4),	F_REG_READ,	AARCH64_FEATURE (V8_2A)) /* MPAM */
   SYSREG ("mpamsm_el1",		CPENC (3,0,10,5,3),	0,		AARCH64_FEATURES (2, SME, V8_2A)) /* SME && MPAM */
-  SYSREG ("mpamvidcr_el2",	CPENC (3,4,10,7,0),	0,		AARCH64_FEATURE (MPAMv2))
-  SYSREG ("mpamvidsr_el2",	CPENC (3,4,10,7,1),	0,		AARCH64_FEATURE (MPAMv2))
-  SYSREG ("mpamvidsr_el3",	CPENC (3,6,10,7,1),	0,		AARCH64_FEATURE (MPAMv2))
   SYSREG ("mpamvpm0_el2",	CPENC (3,4,10,6,0),	0,		AARCH64_FEATURE (V8_2A)) /* MPAM */
   SYSREG ("mpamvpm1_el2",	CPENC (3,4,10,6,1),	0,		AARCH64_FEATURE (V8_2A)) /* MPAM */
   SYSREG ("mpamvpm2_el2",	CPENC (3,4,10,6,2),	0,		AARCH64_FEATURE (V8_2A)) /* MPAM */
-- 
2.43.0


From rearnsha@arm.com  Tue Jun 30 09:42:00 2026
From: rearnsha@arm.com (Richard Earnshaw)
Date: Tue, 30 Jun 2026 10:42:00 +0100
Subject: [PATCH v3 4/7] Revert "aarch64: Add support for MLBI system
 instructions"
In-Reply-To: <20260630094203.2328048-1-rearnsha@arm.com>
References: <20260630094203.2328048-1-rearnsha@arm.com>
Message-ID: <20260630094203.2328048-5-rearnsha@arm.com>

This reverts commit d8e004f124877849c654c0f24c2960970dbc1ee8.
---
 gas/config/tc-aarch64.c                    | 12 ------------
 gas/testsuite/gas/aarch64/mlbi-1.d         | 14 --------------
 gas/testsuite/gas/aarch64/mlbi-1.s         |  9 ---------
 gas/testsuite/gas/aarch64/mlbi-invalid-1.d |  3 ---
 gas/testsuite/gas/aarch64/mlbi-invalid-1.l |  7 -------
 gas/testsuite/gas/aarch64/mlbi-invalid-1.s |  9 ---------
 gas/testsuite/gas/aarch64/mlbi-invalid-2.d |  4 ----
 gas/testsuite/gas/aarch64/mlbi-invalid-2.l | 13 -------------
 include/opcode/aarch64.h                   |  2 --
 opcodes/aarch64-asm-2.c                    |  2 --
 opcodes/aarch64-dis-2.c                    |  4 ----
 opcodes/aarch64-dis.c                      |  1 -
 opcodes/aarch64-opc-2.c                    |  1 -
 opcodes/aarch64-opc.c                      | 10 ----------
 opcodes/aarch64-tbl-2.h                    |  1 -
 opcodes/aarch64-tbl.h                      |  8 --------
 16 files changed, 100 deletions(-)
 delete mode 100644 gas/testsuite/gas/aarch64/mlbi-1.d
 delete mode 100644 gas/testsuite/gas/aarch64/mlbi-1.s
 delete mode 100644 gas/testsuite/gas/aarch64/mlbi-invalid-1.d
 delete mode 100644 gas/testsuite/gas/aarch64/mlbi-invalid-1.l
 delete mode 100644 gas/testsuite/gas/aarch64/mlbi-invalid-1.s
 delete mode 100644 gas/testsuite/gas/aarch64/mlbi-invalid-2.d
 delete mode 100644 gas/testsuite/gas/aarch64/mlbi-invalid-2.l

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 587c3588b09..ae59edcdce9 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -559,7 +559,6 @@ static htab_t aarch64_sys_regs_dc_hsh;
 static htab_t aarch64_sys_regs_at_hsh;
 static htab_t aarch64_sys_regs_tlbi_hsh;
 static htab_t aarch64_sys_regs_plbi_hsh;
-static htab_t aarch64_sys_regs_mlbi_hsh;
 static htab_t aarch64_sys_regs_sr_hsh;
 static htab_t aarch64_reg_hsh;
 static htab_t aarch64_barrier_opt_hsh;
@@ -8202,11 +8201,6 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 	    parse_sys_ins_reg (&str, aarch64_sys_regs_plbi_hsh, false);
 	  goto sys_reg_ins;
 
-	case AARCH64_OPND_SYSREG_MLBI:
-	  inst.base.operands[i].sysins_op =
-	    parse_sys_ins_reg (&str, aarch64_sys_regs_mlbi_hsh, false);
-	  goto sys_reg_ins;
-
 	case AARCH64_OPND_SYSREG_TLBIP:
 	  info->sysins_op =
 	    parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh, true);
@@ -10648,7 +10642,6 @@ md_begin (void)
   aarch64_sys_regs_at_hsh = str_htab_create ();
   aarch64_sys_regs_tlbi_hsh = str_htab_create ();
   aarch64_sys_regs_plbi_hsh = str_htab_create ();
-  aarch64_sys_regs_mlbi_hsh = str_htab_create ();
   aarch64_sys_regs_sr_hsh = str_htab_create ();
   aarch64_reg_hsh = str_htab_create ();
   aarch64_barrier_opt_hsh = str_htab_create ();
@@ -10695,11 +10688,6 @@ md_begin (void)
 			aarch64_sys_regs_plbi[i].name,
 			aarch64_sys_regs_plbi + i);
 
-  for (i = 0; aarch64_sys_regs_mlbi[i].name != NULL; i++)
-    sysreg_hash_insert (aarch64_sys_regs_mlbi_hsh,
-			aarch64_sys_regs_mlbi[i].name,
-			aarch64_sys_regs_mlbi + i);
-
   for (i = 0; aarch64_sys_regs_sr[i].name != NULL; i++)
     sysreg_hash_insert (aarch64_sys_regs_sr_hsh,
 			aarch64_sys_regs_sr[i].name,
diff --git a/gas/testsuite/gas/aarch64/mlbi-1.d b/gas/testsuite/gas/aarch64/mlbi-1.d
deleted file mode 100644
index 32647b6e829..00000000000
--- a/gas/testsuite/gas/aarch64/mlbi-1.d
+++ /dev/null
@@ -1,14 +0,0 @@
-#as: -march=armv8-a+mpamv2
-#objdump: -dr
-
-[^:]+:     file format .*
-
-Disassembly of section \.text:
-
-[^:]+:
-.*:	d50c70bf 	mlbi	vmalle1
-.*:	d50c709f 	mlbi	alle1
-.*:	d50c70c0 	mlbi	vpide1, x0
-.*:	d50c70df 	mlbi	vpide1, xzr
-.*:	d50c70e0 	mlbi	vpmge1, x0
-.*:	d50c70ff 	mlbi	vpmge1, xzr
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/mlbi-1.s b/gas/testsuite/gas/aarch64/mlbi-1.s
deleted file mode 100644
index 008715f2f7b..00000000000
--- a/gas/testsuite/gas/aarch64/mlbi-1.s
+++ /dev/null
@@ -1,9 +0,0 @@
-	.irp	mlbi_op vmalle1,alle1
-	mlbi	\mlbi_op
-	.endr
-
-	.irp	mlbi_op vpide1,vpmge1
-	.irp    rt, x0, xzr
-	mlbi	\mlbi_op, \rt
-	.endr
-	.endr
diff --git a/gas/testsuite/gas/aarch64/mlbi-invalid-1.d b/gas/testsuite/gas/aarch64/mlbi-invalid-1.d
deleted file mode 100644
index 6b66cb8f47c..00000000000
--- a/gas/testsuite/gas/aarch64/mlbi-invalid-1.d
+++ /dev/null
@@ -1,3 +0,0 @@
-#name: Invalid mpamv2 MLBI instructions.
-#as: -march=armv8-a+mpamv2
-#error_output: mlbi-invalid-1.l
diff --git a/gas/testsuite/gas/aarch64/mlbi-invalid-1.l b/gas/testsuite/gas/aarch64/mlbi-invalid-1.l
deleted file mode 100644
index 65af536ae55..00000000000
--- a/gas/testsuite/gas/aarch64/mlbi-invalid-1.l
+++ /dev/null
@@ -1,7 +0,0 @@
-.*: Assembler messages:
-.*: Error: missing register at operand 2 -- `mlbi vpide1'
-.*: Error: missing register at operand 2 -- `mlbi vpmge1'
-.*: Error: extraneous register at operand 2 -- `mlbi vmalle1,x0'
-.*: Error: extraneous register at operand 2 -- `mlbi vmalle1,xzr'
-.*: Error: extraneous register at operand 2 -- `mlbi alle1,x0'
-.*: Error: extraneous register at operand 2 -- `mlbi alle1,xzr'
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/mlbi-invalid-1.s b/gas/testsuite/gas/aarch64/mlbi-invalid-1.s
deleted file mode 100644
index a687d83c42e..00000000000
--- a/gas/testsuite/gas/aarch64/mlbi-invalid-1.s
+++ /dev/null
@@ -1,9 +0,0 @@
-	.irp	mlbi_op vpide1,vpmge1
-	mlbi	\mlbi_op
-	.endr
-
-	.irp	mlbi_op vmalle1,alle1
-	.irp    rt, x0, xzr
-	mlbi	\mlbi_op, \rt
-	.endr
-	.endr
diff --git a/gas/testsuite/gas/aarch64/mlbi-invalid-2.d b/gas/testsuite/gas/aarch64/mlbi-invalid-2.d
deleted file mode 100644
index 11ea14f644b..00000000000
--- a/gas/testsuite/gas/aarch64/mlbi-invalid-2.d
+++ /dev/null
@@ -1,4 +0,0 @@
-#name: MLBI instructions without +mpamv2.
-#as: -march=armv8-a
-#source: mlbi-1.s
-#error_output: mlbi-invalid-2.l
\ No newline at end of file
diff --git a/gas/testsuite/gas/aarch64/mlbi-invalid-2.l b/gas/testsuite/gas/aarch64/mlbi-invalid-2.l
deleted file mode 100644
index cfc61f68d3b..00000000000
--- a/gas/testsuite/gas/aarch64/mlbi-invalid-2.l
+++ /dev/null
@@ -1,13 +0,0 @@
-.*: Assembler messages:
-.*: Error: selected processor does not support system register name 'vmalle1'
-.*: Error: selected processor does not support `mlbi vmalle1'
-.*: Error: selected processor does not support system register name 'alle1'
-.*: Error: selected processor does not support `mlbi alle1'
-.*: Error: selected processor does not support system register name 'vpide1'
-.*: Error: selected processor does not support `mlbi vpide1,x0'
-.*: Error: selected processor does not support system register name 'vpide1'
-.*: Error: selected processor does not support `mlbi vpide1,xzr'
-.*: Error: selected processor does not support system register name 'vpmge1'
-.*: Error: selected processor does not support `mlbi vpmge1,x0'
-.*: Error: selected processor does not support system register name 'vpmge1'
-.*: Error: selected processor does not support `mlbi vpmge1,xzr'
\ No newline at end of file
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 709d76c9a79..ea5c507d06e 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -757,7 +757,6 @@ enum aarch64_opnd
   AARCH64_OPND_SYSREG_TLBI,	/* System register <tlbi_op> operand.  */
   AARCH64_OPND_SYSREG_TLBIP,	/* System register <tlbip_op> operand.  */
   AARCH64_OPND_SYSREG_PLBI,	/* System register <plbi_op> operand.  */
-  AARCH64_OPND_SYSREG_MLBI,	/* System register <mlbi_op> operand.  */
   AARCH64_OPND_SYSREG_SR,	/* System register RCTX operand.  */
   AARCH64_OPND_BARRIER,		/* Barrier operand.  */
   AARCH64_OPND_BARRIER_DSB_NXS,	/* Barrier operand for DSB nXS variant.  */
@@ -1684,7 +1683,6 @@ extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 extern const aarch64_sys_ins_reg aarch64_sys_regs_plbi [];
-extern const aarch64_sys_ins_reg aarch64_sys_regs_mlbi [];
 extern const aarch64_sys_ins_reg aarch64_sys_ins_gic [];
 extern const aarch64_sys_ins_reg aarch64_sys_ins_gicr [];
 extern const aarch64_sys_ins_reg aarch64_sys_ins_gsb [];
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index d2e302e6100..eed062eebe0 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -572,7 +572,6 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
     case A64_OPID_d5080000_ic_SYSREG_IC_Rt_SYS:
     case A64_OPID_d5080000_dc_SYSREG_DC_Rt:
     case A64_OPID_d5080000_at_SYSREG_AT_Rt:
-    case A64_OPID_d5080000_mlbi_SYSREG_MLBI_Rt_SYS:
     case A64_OPID_d5080000_sys_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt:
       value = A64_OPID_d5080000_sys_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt;
       break;
@@ -1022,7 +1021,6 @@ aarch64_insert_operand (const aarch64_operand *self,
     case AARCH64_OPND_SYSREG_TLBI:
     case AARCH64_OPND_SYSREG_TLBIP:
     case AARCH64_OPND_SYSREG_PLBI:
-    case AARCH64_OPND_SYSREG_MLBI:
     case AARCH64_OPND_SYSREG_SR:
     case AARCH64_OPND_GIC:
     case AARCH64_OPND_GICR:
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 3cbf33db77c..33cb384b4a5 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -37594,9 +37594,6 @@ aarch64_find_next_alias_opcode (const aarch64_opcode *opcode)
       value = A64_OPID_d5080000_at_SYSREG_AT_Rt;
       break;
     case A64_OPID_d5080000_at_SYSREG_AT_Rt:
-      value = A64_OPID_d5080000_mlbi_SYSREG_MLBI_Rt_SYS;
-      break;
-    case A64_OPID_d5080000_mlbi_SYSREG_MLBI_Rt_SYS:
       value = A64_OPID_d5080000_sys_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt;
       break;
     case A64_OPID_d5480000_tlbip_SYSREG_TLBIP_Rt_SYS_PAIRREG_OR_XZR:
@@ -38010,7 +38007,6 @@ aarch64_extract_operand (const aarch64_operand *self,
     case AARCH64_OPND_SYSREG_TLBI:
     case AARCH64_OPND_SYSREG_TLBIP:
     case AARCH64_OPND_SYSREG_PLBI:
-    case AARCH64_OPND_SYSREG_MLBI:
     case AARCH64_OPND_SYSREG_SR:
     case AARCH64_OPND_GIC:
     case AARCH64_OPND_GICR:
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index c3a809ef576..3505a7d911d 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -1448,7 +1448,6 @@ aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED,
     case AARCH64_OPND_SYSREG_TLBI: sysins_ops = aarch64_sys_regs_tlbi; break;
     case AARCH64_OPND_SYSREG_TLBIP: sysins_ops = aarch64_sys_regs_tlbi; break;
     case AARCH64_OPND_SYSREG_PLBI: sysins_ops = aarch64_sys_regs_plbi; break;
-    case AARCH64_OPND_SYSREG_MLBI: sysins_ops = aarch64_sys_regs_mlbi; break;
     case AARCH64_OPND_SYSREG_SR:
 	sysins_ops = aarch64_sys_regs_sr;
 	 /* Let's remove op2 for rctx.  Refer to comments in the definition of
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 8a2c560e53f..8d99101fb1c 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -143,7 +143,6 @@ const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_TLBI", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a TBL invalidation operation specifier"},
   {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_TLBIP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a 128-bit TBL invalidation operation specifier"},
   {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_PLBI", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a PLB invalidation operation specifier"},
-  {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_MLBI", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a MLB invalidation operation specifier"},
   {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_SR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a Speculation Restriction option name (RCTX)"},
   {AARCH64_OPND_CLASS_SYSTEM, "BARRIER", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a barrier option name"},
   {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_DSB_NXS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the DSB nXS option qualifier name SY, ISH, NSH, OSH or an optional 5-bit unsigned immediate"},
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 62bb11868fd..e651efb341c 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -4982,7 +4982,6 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
     case AARCH64_OPND_SYSREG_TLBI:
     case AARCH64_OPND_SYSREG_TLBIP:
     case AARCH64_OPND_SYSREG_PLBI:
-    case AARCH64_OPND_SYSREG_MLBI:
     case AARCH64_OPND_SYSREG_SR:
       snprintf (buf, size, "%s", style_reg (styler, opnd->sysins_op->name));
       break;
@@ -5449,15 +5448,6 @@ const aarch64_sys_ins_reg aarch64_sys_regs_plbi[] =
     { 0,	CPENS (0,0,0,0), 0, AARCH64_NO_FEATURES }
 };
 
-const aarch64_sys_ins_reg aarch64_sys_regs_mlbi[] =
-{
-    { "alle1",    CPENS (4, C7, C0, 4), 0, AARCH64_FEATURE (MPAMv2)},
-    { "vmalle1",  CPENS (4, C7, C0, 5), 0, AARCH64_FEATURE (MPAMv2)},
-    { "vpide1",   CPENS (4, C7, C0, 6), F_HASXT, AARCH64_FEATURE (MPAMv2)},
-    { "vpmge1",   CPENS (4, C7, C0, 7), F_HASXT, AARCH64_FEATURE (MPAMv2)},
-    { 0,       CPENS(0,0,0,0), 0, AARCH64_NO_FEATURES }
-};
-
 const aarch64_sys_ins_reg aarch64_sys_ins_gic[] =
 {
     { "cdaff", CPENS (0,C12,C1,3), 0, AARCH64_NO_FEATURES },
diff --git a/opcodes/aarch64-tbl-2.h b/opcodes/aarch64-tbl-2.h
index ee96b332794..64e79d709d5 100644
--- a/opcodes/aarch64-tbl-2.h
+++ b/opcodes/aarch64-tbl-2.h
@@ -1398,7 +1398,6 @@ enum aarch64_opcode_idx
   A64_OPID_d503349f_pssbb,
   A64_OPID_d50330bf_dmb_BARRIER,
   A64_OPID_d50330df_isb_BARRIER_ISB,
-  A64_OPID_d5080000_mlbi_SYSREG_MLBI_Rt_SYS,
   A64_OPID_d50330ff_sb,
   A64_OPID_d508779f_gcspushx,
   A64_OPID_d50877df_gcspopx,
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index c6cb5257008..a94ff572ed0 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -3162,8 +3162,6 @@ static const aarch64_feature_set aarch64_feature_POE2 =
   AARCH64_FEATURE (POE2);
 static const aarch64_feature_set aarch64_feature_tev =
   AARCH64_FEATURE (TEV);
-static const aarch64_feature_set aarch64_feature_mpamv2 =
-  AARCH64_FEATURE (MPAMv2);
 
 #define CORE		&aarch64_feature_v8
 #define FP		&aarch64_feature_fp
@@ -3301,7 +3299,6 @@ static const aarch64_feature_set aarch64_feature_mpamv2 =
 #define SVE_B16MM	&aarch64_feature_sve_b16mm
 #define POE2		&aarch64_feature_POE2
 #define TEV		&aarch64_feature_tev
-#define MPAMV2		&aarch64_feature_mpamv2
 
 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
@@ -3497,8 +3494,6 @@ static const aarch64_feature_set aarch64_feature_mpamv2 =
 #define MOPS_GO_INSN(NAME, OPCODE, MASK, CLASS, OPS, QUALS, FLAGS, CONSTRAINTS, VERIFIER) \
   { NAME, OPCODE, MASK, CLASS, 0, MOPS_GO, OPS, QUALS, FLAGS, \
     CONSTRAINTS, 0, VERIFIER }
-#define MPAMV2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-  { NAME, OPCODE, MASK, CLASS, 0, MPAMV2, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
 #define HBC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, HBC, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define CSSC_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \
@@ -5196,7 +5191,6 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   CORE_INSN ("pssbb", 0xd503349f, 0xffffffff, ic_system, 0, OP0 (), QL_0, F_ALIAS),
   CORE_INSN ("dmb", 0xd50330bf, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), QL_NIL1, 0),
   CORE_INSN ("isb", 0xd50330df, 0xfffff0ff, ic_system, 0, OP1 (BARRIER_ISB), QL_NIL1, F_OPD0_OPT | F_DEFAULT (0xF)),
-  MPAMV2_INSN ("mlbi", 0xd5080000, 0xfff80000, ic_system, OP2 (SYSREG_MLBI, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)),
   SB_INSN ("sb", 0xd50330ff, 0xffffffff, ic_system, OP0 (), QL_0, 0),
   GCS_INSN ("gcspushx", 0xd508779f, 0xffffffff, OP0 (), QL_0, 0),
   GCS_INSN ("gcspopx", 0xd50877df, 0xffffffff, OP0 (), QL_0, 0),
@@ -8210,8 +8204,6 @@ const struct aarch64_opcode aarch64_opcode_table[] =
       "a 128-bit TBL invalidation operation specifier")			\
     Y(SYSTEM, sysins_op, "SYSREG_PLBI", 0, F(),				\
       "a PLB invalidation operation specifier")				\
-    Y(SYSTEM, sysins_op, "SYSREG_MLBI", 0, F(),				\
-      "a MLB invalidation operation specifier")				\
     Y(SYSTEM, sysins_op, "SYSREG_SR", 0, F(),				\
       "a Speculation Restriction option name (RCTX)")			\
     Y(SYSTEM, barrier, "BARRIER", 0, F(),				\
-- 
2.43.0


From rearnsha@arm.com  Tue Jun 30 09:42:02 2026
From: rearnsha@arm.com (Richard Earnshaw)
Date: Tue, 30 Jun 2026 10:42:02 +0100
Subject: [PATCH v3 6/7] aarch64: Remove +mpamv2 feature option
In-Reply-To: <20260630094203.2328048-1-rearnsha@arm.com>
References: <20260630094203.2328048-1-rearnsha@arm.com>
Message-ID: <20260630094203.2328048-7-rearnsha@arm.com>

The remaining mpamv2 details only use system registers; so by our
conventions we do not use a feature option to enable them.  Remove the
now +mpamv2 architecture option and adjust the tests accordingly.
---
 gas/config/tc-aarch64.c                       | 1 -
 gas/doc/c-aarch64.texi                        | 2 --
 gas/testsuite/gas/aarch64/sysreg/mpamv2-bad.d | 2 +-
 gas/testsuite/gas/aarch64/sysreg/mpamv2.d     | 2 +-
 include/opcode/aarch64.h                      | 2 --
 opcodes/aarch64-sys-regs.def                  | 8 ++++----
 6 files changed, 6 insertions(+), 11 deletions(-)

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index ae59edcdce9..715df4de4bf 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -11138,7 +11138,6 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"f16f32mm",		AARCH64_FEATURE (F16F32MM), AARCH64_FEATURES (2, SIMD, F16)},
   {"f16mm",		AARCH64_FEATURE (F16MM), AARCH64_FEATURES (2, SIMD, F16)},
   {"sve-b16mm",		AARCH64_FEATURE (SVE_B16MM), AARCH64_FEATURE (SVE)},
-  {"mpamv2",		AARCH64_FEATURE (MPAMv2), AARCH64_NO_FEATURES},
   {"mtetc",		AARCH64_FEATURE (MTETC), AARCH64_FEATURE (MEMTAG)},
   {"tlbid",		AARCH64_FEATURE (TLBID), AARCH64_NO_FEATURES},
   {NULL,		AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 0620ad8f4d2..4ac0ae6dae1 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -268,8 +268,6 @@ automatically cause those extensions to be disabled.
  @tab Enable Armv8.8-A memcpy and memset acceleration instructions.
 @item @code{mops-go} @tab @code{mops}, @code{memtag}
  @tab Enable tag only variants of MOPS instructions.
-@item @code{mpamv2} @tab
- @tab Enable MPAMv2 system registers.
 @item @code{mtetc} @tab @code{memtag}
  @tab Enable Data cache tag block operations.
 @item @code{occmo} @tab
diff --git a/gas/testsuite/gas/aarch64/sysreg/mpamv2-bad.d b/gas/testsuite/gas/aarch64/sysreg/mpamv2-bad.d
index af47db767c9..8490318937b 100644
--- a/gas/testsuite/gas/aarch64/sysreg/mpamv2-bad.d
+++ b/gas/testsuite/gas/aarch64/sysreg/mpamv2-bad.d
@@ -1,3 +1,3 @@
-#as: -march=armv9.4-a -menable-sysreg-checking -I$srcdir/$subdir
+#as: -march=armv9.3-a -menable-sysreg-checking -I$srcdir/$subdir
 #source: mpamv2.s
 #error_output: mpamv2-bad.l
diff --git a/gas/testsuite/gas/aarch64/sysreg/mpamv2.d b/gas/testsuite/gas/aarch64/sysreg/mpamv2.d
index 159f6a3ec61..270e3c20848 100644
--- a/gas/testsuite/gas/aarch64/sysreg/mpamv2.d
+++ b/gas/testsuite/gas/aarch64/sysreg/mpamv2.d
@@ -1,4 +1,4 @@
-#as: -menable-sysreg-checking -march=armv8-a+mpamv2 -I$srcdir/$subdir
+#as: -menable-sysreg-checking -march=armv9.4-a -I$srcdir/$subdir
 #objdump: -dr
 
 .*:     file format .*
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index ea5c507d06e..9851f4ad248 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -284,8 +284,6 @@ enum aarch64_feature_bit {
   AARCH64_FEATURE_POE2,
   /* TEV instructions.  */
   AARCH64_FEATURE_TEV,
-  /* MPAMv2.  */
-  AARCH64_FEATURE_MPAMv2,
   /* MTETC.  */
   AARCH64_FEATURE_MTETC,
   /* TLBI Domains.  */
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index 6f9f2b4c0a8..1fbf56f0926 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -922,10 +922,10 @@
   SYSREG ("mpambwcap_el2",	CPENC (3,4,10,5,6),	0,		AARCH64_FEATURE (V9_3A)) /* MPAM_PE_BW_CTRL */
   SYSREG ("mpambwidr_el1",	CPENC (3,0,10,4,5),	F_REG_READ,	AARCH64_FEATURE (V9_3A)) /* MPAM_PE_BW_CTRL */
   SYSREG ("mpambwsm_el1",	CPENC (3,0,10,5,7),	0,		AARCH64_FEATURES (2, SME, V9_3A)) /* SME && MPAM_PE_BW_CTRL */
-  SYSREG ("mpamctl_el1",	CPENC (3,0,10,5,2),	0,		AARCH64_FEATURE (MPAMv2))
-  SYSREG ("mpamctl_el12",	CPENC (3,5,10,5,2),	0,		AARCH64_FEATURE (MPAMv2))
-  SYSREG ("mpamctl_el2",	CPENC (3,4,10,5,2),	0,		AARCH64_FEATURE (MPAMv2))
-  SYSREG ("mpamctl_el3",	CPENC (3,6,10,5,2),	0,		AARCH64_FEATURE (MPAMv2))
+  SYSREG ("mpamctl_el1",	CPENC (3,0,10,5,2),	0,		AARCH64_FEATURE (V9_4A)) /* MPAMv2 */
+  SYSREG ("mpamctl_el12",	CPENC (3,5,10,5,2),	0,		AARCH64_FEATURE (V9_4A)) /* MPAMv2 */
+  SYSREG ("mpamctl_el2",	CPENC (3,4,10,5,2),	0,		AARCH64_FEATURE (V9_4A)) /* MPAMv2 */
+  SYSREG ("mpamctl_el3",	CPENC (3,6,10,5,2),	0,		AARCH64_FEATURE (V9_4A)) /* MPAMv2 */
   SYSREG ("mpamhcr_el2",	CPENC (3,4,10,4,0),	0,		AARCH64_FEATURE (V8_2A)) /* MPAM */
   SYSREG ("mpamidr_el1",	CPENC (3,0,10,4,4),	F_REG_READ,	AARCH64_FEATURE (V8_2A)) /* MPAM */
   SYSREG ("mpamsm_el1",		CPENC (3,0,10,5,3),	0,		AARCH64_FEATURES (2, SME, V8_2A)) /* SME && MPAM */
-- 
2.43.0


From rearnsha@arm.com  Tue Jun 30 09:42:03 2026
From: rearnsha@arm.com (Richard Earnshaw)
Date: Tue, 30 Jun 2026 10:42:03 +0100
Subject: [PATCH v3 7/7] NEWS: Update for withdrawal of the MPAMv2_VID feature.
In-Reply-To: <20260630094203.2328048-1-rearnsha@arm.com>
References: <20260630094203.2328048-1-rearnsha@arm.com>
Message-ID: <20260630094203.2328048-8-rearnsha@arm.com>

---
 gas/NEWS | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/gas/NEWS b/gas/NEWS
index 116d5e62be6..47f0abc5520 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,8 +1,10 @@
 -*- text -*-
 
-* The aarch64 TME extension has never been implemented in any products.  Arm
-  has withdrawn it from the architecture.  The assembler will now warn if
-  instructions from the extension are detected during assembly.
+* The aarch64 extensions TME and MPAMv2_VID have never been implemented in any
+  products.  Arm has withdrawn them from the architecture.  The assembler will
+  now warn if instructions or system registers from either extension are
+  detected during assembly.  The architecture sub-option +mpamv2 has also
+  been withdrawn as the feature no-longer has instructions to enable.
 
 * The legacy .vtable_entry and .vtable_inherit directives that were
   needed for versions of GCC prior to gcc-3.0 (when the generic C++
-- 
2.43.0


From jeffrey.law@oss.qualcomm.com  Tue Jun 30 13:56:03 2026
From: jeffrey.law@oss.qualcomm.com (Jeffrey Law)
Date: Tue, 30 Jun 2026 07:56:03 -0600
Subject: [PATCH 1/2] RISC-V: Add Zvdota extension classes
In-Reply-To: <20260630033438.143289-1-jiawei@iscas.ac.cn>
References: <20260630033438.143289-1-jiawei@iscas.ac.cn>
Message-ID: <c52037f6-234e-4e76-9a4c-885a3dbd6a99@oss.qualcomm.com>



On 6/29/2026 9:34 PM, Jiawei wrote:
> This patch adds assembler/disassembler support for the RISC-V Zvdota family of extensions [1], which compute a dot product between two vector register groups.
>
> The Zvdota extension family includes the following extensions:
>
> Zvqwdota8i: dot product of 8-bit integers with 32-bit accumulation.
> Zvqwdota16i: dot product of 16-bit integers with 64-bit accumulation.
> Zvfwdota16bf: dot product of bfloat16 floating-point numbers with 32-bit accumulation.
> Zvfqwdota8f: dot product of 8-bit floating-point numbers with 32-bit accumulation.
>
> Zvdota also uses the vtype alternative format bit, altfmt, which is bit 8 of the vtype CSR. This patch adds symbolic e8alt and e16alt vsew constants for vsetvli/vsetivli so that assembly code can select the alternative element formats required by these dot-product instructions.
>
> [1] https://github.com/riscv/riscv-isa-manual/blob/zvbdot/src/zvdota.adoc
>
> bfd/ChangeLog:
>
> 	* elfxx-riscv.c (riscv_implicit_subsets): New implies.
> 	(riscv_supported_std_z_ext): New extensions.
> 	(riscv_multi_subset_supports): Ditto.
> 	(riscv_multi_subset_supports_ext): Ditto.
>
> gas/ChangeLog:
>
> 	* NEWS: Add zvqwdota8i, zvqwdota16i, zvfwdota16bf and
> 	zvfqwdota8f extensions.
> 	* config/tc-riscv.c (riscv_vsew_altfmt): New vsew altfmt
> 	constants array for e8alt and e16alt.
> 	(riscv_vtype_altfmt_supported): New function.
> 	(my_getVsetvliExpression): Ditto.
> 	* testsuite/gas/riscv/march-help.l: New test.
> 	* testsuite/gas/riscv/vector-vtype-altfmt.d: Ditto.
> 	* testsuite/gas/riscv/vector-vtype-altfmt.s: Ditto.
> 	* testsuite/gas/riscv/zvdota.d: Ditto.
> 	* testsuite/gas/riscv/zvdota.s: Ditto.
>
> include/ChangeLog:
>
> 	* opcode/riscv-opc.h (MATCH_VQWDOTAU_VV, MASK_VQWDOTAU_VV): New encoding.
> 	(MATCH_VQWDOTAS_VV, MASK_VQWDOTAS_VV): Ditto.
> 	(MATCH_VFWDOTA_VV, MASK_VFWDOTA_VV): Ditto.
> 	(MATCH_VFQWDOTA_VV, MASK_VFQWDOTA_VV): Ditto.
> 	(MATCH_VFQWDOTA_ALT_VV, MASK_VFQWDOTA_ALT_VV): Ditto.
> 	(DECLARE_INSN): New declarations.
> 	* opcode/riscv.h (OP_MASK_VTYPE_ALTFMT, OP_SH_VTYPE_ALTFMT): New vtype altfmt.
> 	(enum riscv_insn_class): New extension classes.
>
> opcodes/ChangeLog:
>
> 	* riscv-dis.c (print_insn_args): Add altfmt support.
> 	* riscv-opc.c (riscv_opcodes): New instructions.
THanks!? I've pushed both patches in this series to the trunk.

jeff

From builder@sourceware.org  Tue Jun 30 15:14:12 2026
From: builder@sourceware.org (builder@sourceware.org)
Date: Tue, 30 Jun 2026 15:14:12 +0000
Subject: =?utf-8?q?=E2=98=A0_Buildbot_=28Sourceware=29=3A_binutils-gdb_-_failed_test_=28failure=29_=28master=29?=
Message-ID: <20260630151412.A28674BA2E2A@sourceware.org>

A new failure has been detected on builder binutils-ubuntu-riscv while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/283/builds/3216

Build state: failed test (failure)
Revision: 794f538c3e57e3f55a6224a7206fdb0ea7815a82
Worker: starfive-3
Build Reason: (unknown)
Blamelist: Jiawei <jiawei@iscas.ac.cn>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/3/logs/config_log

- 4: make ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/4/logs/stdio
        - warnings (12): https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/4/logs/warnings__12_

- 5: make check (no ld) ( failure )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/5/logs/stdio
        - gas.sum: https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/5/logs/gas_sum
        - gas.log: https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/5/logs/gas_log
        - binutils.sum: https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/5/logs/binutils_sum
        - binutils.log: https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/5/logs/binutils_log
        - libsframe.sum: https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/5/logs/libsframe_sum
        - libsframe.log: https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/5/logs/libsframe_log
        - libctf.sum: https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/5/logs/libctf_sum
        - libctf.log: https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/5/logs/libctf_log
        - warnings (8): https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/5/logs/warnings__8_

- 6: make check ld ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/6/logs/stdio
        - ld.sum: https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/6/logs/ld_sum
        - ld.log: https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/6/logs/ld_log
        - warnings (2): https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/6/logs/warnings__2_

- 7: prep ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/7/logs/stdio

- 8: collect system versions ( success )
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        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/8/logs/stdio

- 9: fetch .bunsen.* ( success )
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        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/9/logs/stdio

- 10: build bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/10/logs/stdio

- 11: fetch bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/11/logs/stdio

- 12: unpack bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/12/logs/stdio

- 13: pass .bunsen.source.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/13/logs/stdio

- 14: upload to bunsen ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/14/logs/stdio

- 15: clean up ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/15/logs/stdio

- 16: rm -rf binutils-build_1 ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3216/steps/16/logs/stdio


From evgeny.karpov@arm.com  Tue Jun 30 16:57:02 2026
From: evgeny.karpov@arm.com (Evgeny Karpov)
Date: Tue, 30 Jun 2026 18:57:02 +0200
Subject: [PATCH v10 1/1] aarch64: Implement Structured Exception Handling
 (SEH) on AArch64
In-Reply-To: <20260626133013.89140-2-evgeny.karpov@arm.com>
Message-ID: <akP1XoGoSq19O_4h@arm.com>

On Fri, 26 Jun 2026, Alice Carlotti wrote:
> > Changes in v10:
> > - Rename offset_shift/reg_shift to offset_multiplier/reg_multiplier.
> I think you misinterpreted my review - I wanted you to rename the local
> variables in seh_aarch64_add_unwind_element:
> divided_by -> offset_multipler
> regn_divided_by -> reg_multiplier
> 
> The offset_shift and reg_shift field names were fine, and the new names are
> wrong (because the values are shift amounts, not multipliers).  Please change
> the field names back to offset_shift and reg_shift.

Ok, it was not clear in the previous comment. 
 
> > Yes, something should be wrong if func_size < 0, no need to check if func_size >= 0.
> 
> Can you explain why there's no need to check when func_size >= 0?  It looks to
> me like we could end up in that case without the function size being fully
> evaluated, but I don't really understand what this is checking.
 
func_size had mostly been calculated correctly in the past,
except in some cases when the alignment was not handled correctly.
In that case, func_size was calculated as a negative value.
The issue with the code alignment has been fixed, however 
that condition still checks that case.

> > The description will be extended with text that big endian host has not been validated.
> > It will be validated, and a separate patch will be submitted if needed. 
> 
> I think deliberately committing code that is broken for a big endian host, and
> then testing and fixing it later, is the wrong approach when doing it correctly
> is no more complex (and, in my opinion, might be a bit clearer).

It does not look like a common case for aarch64-w64-mingw32 target,
however it will be validated, and required changes will be done if needed.
 
> > +      reg = atoi (symbol_name + 1);
> > +      (void) restore_line_pointer (name_end);
> > +
> > +      if (!skip_whitespace_and_comma (1))
> > +	return;
> > +
> > +      /* Check that reference registers are not higher than x30.  */
> 
> Nit: s/reference/referenced/

Ok.

> > +
> > +  /* Calculate how many unwind bytes will be emitted in .xdata record.  */
> > +  unsigned unwind_bytes = prologue_size;
> > +
> > +  /* Check if current fragment has a phantom prologue.  If yes, then
> > +      the unwinding size should be adjusted.  */
> > +  const bool has_phantom_prologue = is_fragmented_function && is_last_frag;
> This condition is still wrong.
  
Thanks for noticing this. There was an issue with phantom encoding. 

> > +      header->code_words = header->ext_code_words;
> > +      header->epilogue_count = header->ext_epilogue_count;
> > +      if (header->epilogue_count == 1)
> > +	{
> > +	  header->e = 1;
> > +	  if (has_phantom_prologue)
> > +	    header->ext_epilogue_count = 0;
> This looks wrong - surely the start index is 1 in this case (with unwind code
> index 0 being end_c, to indicate the phantom prologue).

That was fixed for the phantom prolog. The start index was correct, however 
it should be encoded in epilogue_count.
header->epilogue_count = 0;
 
> > +	      header->ext_epilogue_count = scope->epilogue_start_index;
> > +	    }
> > +	}
> > +    }
> > +
> > +  md_number_to_chars (frag_more (header_size), seh_ctx->xdata_header_value,
> > +		      header_size);
> 
> I think we should just build up the headers manually - this avoids endianess or
> other platform-specific issues, and simplifies the code a bit.  So something
> like:
> 
> +  unsigned code_words = ((unwind_bytes + 3) >> 2);
> +
> +  /* Compute and emit the xdata record header.  */
> +  uint32_t header = frag_size >> 2;
> +  if (seh_ctx->has_exception_data)
> +    header |= 1 << 20;
> +  if (epilogue_count <= 31 && code_words <= 31)
> +    {
> +      header |= epilogue_count << 22;
> +      header |= code_words << 27;
> +      md_number_to_chars (frag_more (4), header, 4));
> +    }
> +  else
> +    {
> +      md_number_to_chars (frag_more (4), header, 4));
> +      uint32_t header2 = epilogue_count | (code_words << 16)
> +      md_number_to_chars (frag_more (4), header2, 4));
> +    }
> 
> This doesn't use the E=1 format (which only saves 4 bytes) - if we wanted to
> include that then we'd need to add an initial check for:
> +  if (epilogue_count == 1 && code_words <= 31
> +      && /* Check epilogue start index <= 31.  */
> +      && /* Check epilogue is at the end of the function - this doesn't seem
> to be documented, but it's the only sensible way I can see to specify the
> offset in this case.  */)
> 
> However, I can't see clear documentation for how this works, so it might be
> better to ignore the E=1 format for now, and seek clarification before
> implementing it.

epilogue_count <= 31 && code_words <=31
This condition does not cover a case when epilogue_count == 0 && code_words == 0.
It should use the extended header in that case.
It looks like if E=1 and both code words and epilogue count are 0, the extended 
header should be used anyway.
 
> > +
> > +      /* Calculate current fragment size.  */
> > +      uintptr_t frag_size = func_size - fragment_offset;
> > +      if (frag_size > max_frag_size)
> > +	frag_size = max_frag_size;
> > +
> > +      const bool is_last_frag = (fragment_offset + frag_size) == func_size;
> This value shouldn't be needed in the function call, so we can just inline this
> condition into the loop termination check.

The condition will be inlined.

> > +
> > +  subsegT subsection;
> > +
> > +  union {
> > +    seh_aarch64_xdata_header xdata_header;
> > +    valueT xdata_header_value;
> > +  };
> The only header field that is now used outside of seh_aarch64_emit_xdata_record
> is xdata_header->x.  Please replace this union with a single boolean value
> seh_ctx_cur->has_exception_data (or some similar name).  We can keep details
> of the header layout contained to the single function that writes those other
> fields.
 
Ok, it will be changed.

Regards,
Evgeny


From builder@sourceware.org  Tue Jun 30 17:04:46 2026
From: builder@sourceware.org (builder@sourceware.org)
Date: Tue, 30 Jun 2026 17:04:46 +0000
Subject: =?utf-8?q?=E2=98=BA_Buildbot_=28Sourceware=29=3A_binutils-gdb_-_build_successful_=28master=29?=
Message-ID: <20260630170446.A986A4BA2E26@sourceware.org>

A restored build has been detected on builder binutils-ubuntu-riscv while building binutils-gdb.

Full details are available at:
    https://builder.sourceware.org/buildbot/#/builders/283/builds/3217

Build state: build successful
Revision: cd28fb866379c5dbbe431feb24aa62d369554f80
Worker: starfive-2
Build Reason: (unknown)
Blamelist: Jiawei <jiawei@iscas.ac.cn>

Steps:

- 0: worker_preparation ( success )

- 1: git checkout ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/1/logs/stdio

- 2: rm -rf binutils-build ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/2/logs/stdio

- 3: configure ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/3/logs/stdio
        - config.log: https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/3/logs/config_log

- 4: make ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/4/logs/stdio
        - warnings (12): https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/4/logs/warnings__12_

- 5: make check (no ld) ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/5/logs/stdio
        - gas.sum: https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/5/logs/gas_sum
        - gas.log: https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/5/logs/gas_log
        - binutils.sum: https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/5/logs/binutils_sum
        - binutils.log: https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/5/logs/binutils_log
        - libsframe.sum: https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/5/logs/libsframe_sum
        - libsframe.log: https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/5/logs/libsframe_log
        - libctf.sum: https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/5/logs/libctf_sum
        - libctf.log: https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/5/logs/libctf_log
        - warnings (8): https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/5/logs/warnings__8_

- 6: make check ld ( warnings )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/6/logs/stdio
        - ld.sum: https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/6/logs/ld_sum
        - ld.log: https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/6/logs/ld_log
        - warnings (2): https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/6/logs/warnings__2_

- 7: prep ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/7/logs/stdio

- 8: collect system versions ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/8/logs/stdio

- 9: fetch .bunsen.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/9/logs/stdio

- 10: build bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/10/logs/stdio

- 11: fetch bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/11/logs/stdio

- 12: unpack bunsen.cpio.gz ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/12/logs/stdio

- 13: pass .bunsen.source.* ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/13/logs/stdio

- 14: upload to bunsen ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/14/logs/stdio

- 15: clean up ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/15/logs/stdio

- 16: rm -rf binutils-build_1 ( success )
    Logs:
        - stdio: https://builder.sourceware.org/buildbot/#/builders/283/builds/3217/steps/16/logs/stdio


From jon.turney@dronecode.org.uk  Tue Jun 30 19:27:56 2026
From: jon.turney@dronecode.org.uk (Jon Turney)
Date: Tue, 30 Jun 2026 20:27:56 +0100
Subject: [PATCH] objdump: Fix private header ('-p') import table output
 for pe-aarch64
In-Reply-To: <aa44ecbb-b833-4776-aff5-92b79e3343fc@suse.com>
References: <20260619134339.73604-1-jon.turney@dronecode.org.uk>
 <aa44ecbb-b833-4776-aff5-92b79e3343fc@suse.com>
Message-ID: <17d4f2f8-e520-4c16-91a0-6db4aa75db57@dronecode.org.uk>

On 26/06/2026 08:06, Jan Beulich wrote:
> On 19.06.2026 15:43, Jon Turney wrote:
>> The private header ('-p') import table output for pe-aarch64 (and
>> probably all other 64-bit arches apart from x86_64) is truncated after the
>> first import.
>>
>> The distinction between the conditional branches here should be between
>> PE32 (32-bit) and PE32+ (somewhat confusingly, the 64-bit version of the
>> PE format).
>>
>> PE file format specification [1] states under "Import Lookup Table":
>>
>> "An import lookup table is an array of 32-bit numbers for PE32 or an
>> array of 64-bit numbers for PE32+."
>>
>> [1] https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#import-lookup-table
>>
>> 2026-06-19  Jon Turney  <jon.turney@dronecode.org.uk>
>>
>> 	* peXXigen.c (pe_print_idata): Fix conditional.
> 
> Okay, albeit preferably with ...
> 
>> --- a/bfd/peXXigen.c
>> +++ b/bfd/peXXigen.c
>> @@ -1462,7 +1462,7 @@ pe_print_idata (bfd * abfd, void * vfile)
>>   	    }
>>   
>>   	  /* Print HintName vector entries.  */
>> -#ifdef COFF_WITH_pex64
>> +#if defined COFF_WITH_pep || defined COFF_WITH_pex64 || defined COFF_WITH_peAArch64 || defined COFF_WITH_peLoongArch64 || defined COFF_WITH_peRiscV64
> 
> ... this line split for each part to remain within 80 columns (no matter

I attach a revised patch since I'm not entirely sure of the desired 
formatting and indentation here.

> that other such long lines exist). Perhaps they all should be consolidated
> into the checking of a single (new) manifest constant, such that mistakes
> like the one being fixed here are easier to avoid. But that's for later.

Yes, that seems like a very good idea.

This condition (or its negation) is repeated multiple times (along with 
some almost similar conditions which would probably benefit from a 
comment if they really are meant to be different).

-------------- next part --------------
From 62c10c5d90a3f46f8e26edd2c1d4ff5545e8c55f Mon Sep 17 00:00:00 2001
From: Jon Turney <jon.turney@dronecode.org.uk>
Date: Fri, 19 Jun 2026 13:47:03 +0100
Subject: [PATCH] objdump: Fix private header ('-p') import table output for
 pe-aarch64

The private header ('-p') import table output for pe-aarch64 (and
probably all other 64-bit arches apart from x86_64) is truncated after the
first import.

The distinction between the conditional branches here should be between
PE32 (32-bit) and PE32+ (somewhat confusingly, the 64-bit version of the
PE format).

PE file format specification [1] states under "Import Lookup Table":

"An import lookup table is an array of 32-bit numbers for PE32 or an
array of 64-bit numbers for PE32+."

[1] https://learn.microsoft.com/en-us/windows/win32/debug/pe-format#import-lookup-table

2026-06-19  Jon Turney  <jon.turney@dronecode.org.uk>

	* peXXigen.c (pe_print_idata): Fix conditional.
---
 bfd/peXXigen.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/bfd/peXXigen.c b/bfd/peXXigen.c
index bdb23dcbcab..f604a84ec0a 100644
--- a/bfd/peXXigen.c
+++ b/bfd/peXXigen.c
@@ -1462,7 +1462,9 @@ pe_print_idata (bfd * abfd, void * vfile)
 	    }
 
 	  /* Print HintName vector entries.  */
-#ifdef COFF_WITH_pex64
+#if defined COFF_WITH_pep || defined COFF_WITH_pex64 \
+    || defined COFF_WITH_peAArch64 || defined COFF_WITH_peLoongArch64 \
+    || defined COFF_WITH_peRiscV64
 	  for (j = 0; idx + j + 8 <= datasize; j += 8)
 	    {
 	      bfd_size_type amt;
-- 
2.51.0


From oleg.tolmatcev@gmail.com  Tue Jun 30 20:59:18 2026
From: oleg.tolmatcev@gmail.com (Oleg Tolmatcev)
Date: Tue, 30 Jun 2026 22:59:18 +0200
Subject: [PATCH] PE/COFF: raise normal PE section limit safely
Message-ID: <20260630205916.1179-3-oleg.tolmatcev@gmail.com>

PE/COFF stores symbol section numbers in a 16-bit field.  Binutils used
signed 16-bit handling there, which limited normal PE objects to 32767
sections even though MSVC and Clang already accept a larger unsigned
range.

Raise the normal PE section limit to 65279, while keeping the PE/COFF
special section-number values for undefined, absolute and debug symbols
working correctly.  Do this by decoding and encoding normal PE symbol
section numbers as unsigned values in the ordinary range, but preserving
the reserved PE constants explicitly.

Also add a gas test that exercises a normal PE object above the old
32767-section limit and checks that objdump reports the high section
number correctly.

bfd/ChangeLog:

	* coffcode.h (COFF_DEFAULT_MAX_NSCNS): Define.
	(bfd_coff_std_swap_table): Use it for the default maximum section
	count.
	(ticoff0_swap_table): Likewise.
	(ticoff1_swap_table): Likewise.
	* peXXigen.c (pe_decode_sym_section_number): New function.
	(pe_encode_sym_section_number): New function.
	(_bfd_XXi_swap_sym_in): Use pe_decode_sym_section_number.
	(_bfd_XXi_swap_sym_out): Use pe_encode_sym_section_number.

include/ChangeLog:

	* coff/pe.h (IMAGE_SYM_UNDEFINED): Define.
	(IMAGE_SYM_ABSOLUTE): Define.
	(IMAGE_SYM_DEBUG): Define.
	(IMAGE_SYM_SECTION_MAX): Define.

gas/ChangeLog:

	* testsuite/gas/pe/pe.exp: Run large-obj-normal.
	* testsuite/gas/pe/large-obj-normal.s: New test.
	* testsuite/gas/pe/large-obj-normal.d: New test.

Signed-off-by: Oleg Tolmatcev <oleg.tolmatcev@gmail.com>
---
 bfd/coffcode.h                          | 12 +++++--
 bfd/peXXigen.c                          | 47 +++++++++++++++++++++++--
 gas/testsuite/gas/pe/large-obj-normal.d | 17 +++++++++
 gas/testsuite/gas/pe/large-obj-normal.s | 16 +++++++++
 gas/testsuite/gas/pe/pe.exp             |  1 +
 include/coff/pe.h                       |  5 +++
 6 files changed, 93 insertions(+), 5 deletions(-)
 create mode 100644 gas/testsuite/gas/pe/large-obj-normal.d
 create mode 100644 gas/testsuite/gas/pe/large-obj-normal.s

diff --git a/bfd/coffcode.h b/bfd/coffcode.h
index 12cc7c3ca7..267c6ce278 100644
--- a/bfd/coffcode.h
+++ b/bfd/coffcode.h
@@ -376,6 +376,12 @@ extern const bfd_target TARGET_SYM_BIG;
 # define COFF_WITH_EXTENDED_RELOC_COUNTER
 #endif
 
+#if defined(COFF_WITH_PE) && !defined(COFF_IMAGE_WITH_PE)
+# define COFF_DEFAULT_MAX_NSCNS (IMAGE_SYM_SECTION_MAX + 1)
+#else
+# define COFF_DEFAULT_MAX_NSCNS 32768
+#endif
+
 #if defined (COFF_LONG_SECTION_NAMES)
 /* Needed to expand the inputs to BLANKOR1TOODD.  */
 #define COFFLONGSECTIONCATHELPER(x,y)    x ## y
@@ -5615,7 +5621,7 @@ static const bfd_coff_backend_data bfd_coff_std_swap_table ATTRIBUTE_UNUSED =
 #else
   2,
 #endif
-  32768,
+  COFF_DEFAULT_MAX_NSCNS,
   coff_SWAP_filehdr_in, coff_SWAP_aouthdr_in, coff_SWAP_scnhdr_in,
   coff_SWAP_reloc_in, coff_bad_format_hook, coff_set_arch_mach_hook,
   coff_mkobject_hook, styp_to_sec_flags, coff_set_alignment_hook,
@@ -5656,7 +5662,7 @@ static const bfd_coff_backend_data ticoff0_swap_table =
 #else
   2,
 #endif
-  32768,
+  COFF_DEFAULT_MAX_NSCNS,
   coff_SWAP_filehdr_in, coff_SWAP_aouthdr_in, coff_SWAP_scnhdr_in,
   coff_swap_reloc_v0_in, ticoff0_bad_format_hook, coff_set_arch_mach_hook,
   coff_mkobject_hook, styp_to_sec_flags, coff_set_alignment_hook,
@@ -5698,7 +5704,7 @@ static const bfd_coff_backend_data ticoff1_swap_table =
 #else
   2,
 #endif
-  32768,
+  COFF_DEFAULT_MAX_NSCNS,
   coff_SWAP_filehdr_in, coff_SWAP_aouthdr_in, coff_SWAP_scnhdr_in,
   coff_SWAP_reloc_in, ticoff1_bad_format_hook, coff_set_arch_mach_hook,
   coff_mkobject_hook, styp_to_sec_flags, coff_set_alignment_hook,
diff --git a/bfd/peXXigen.c b/bfd/peXXigen.c
index bdb23dcbca..6ceb04378c 100644
--- a/bfd/peXXigen.c
+++ b/bfd/peXXigen.c
@@ -109,6 +109,49 @@
 #define SetHighBit(val)      ((val) | 0x80000000)
 #define WithoutHighBit(val)  ((val) & 0x7fffffff)
 
+static int
+pe_decode_sym_section_number (bfd *abfd, const char *raw_scnum)
+{
+  unsigned int scnum = H_GET_16 (abfd, raw_scnum);
+
+  switch (scnum)
+    {
+    case IMAGE_SYM_UNDEFINED:
+      return N_UNDEF;
+    case IMAGE_SYM_ABSOLUTE:
+      return N_ABS;
+    case IMAGE_SYM_DEBUG:
+      return N_DEBUG;
+    default:
+      return scnum;
+    }
+}
+
+static void
+pe_encode_sym_section_number (bfd *abfd, int scnum, char *raw_scnum)
+{
+  unsigned int encoded_scnum;
+
+  switch (scnum)
+    {
+    case N_UNDEF:
+      encoded_scnum = IMAGE_SYM_UNDEFINED;
+      break;
+    case N_ABS:
+      encoded_scnum = IMAGE_SYM_ABSOLUTE;
+      break;
+    case N_DEBUG:
+      encoded_scnum = IMAGE_SYM_DEBUG;
+      break;
+    default:
+      BFD_ASSERT (scnum > 0 && (unsigned int) scnum <= IMAGE_SYM_SECTION_MAX);
+      encoded_scnum = scnum;
+      break;
+    }
+
+  H_PUT_16 (abfd, encoded_scnum, raw_scnum);
+}
+
 void
 _bfd_XXi_swap_sym_in (bfd * abfd, void * ext1, void * in1)
 {
@@ -124,7 +167,7 @@ _bfd_XXi_swap_sym_in (bfd * abfd, void * ext1, void * in1)
     memcpy (in->_n._n_name, ext->e.e_name, SYMNMLEN);
 
   in->n_value = H_GET_32 (abfd, ext->e_value);
-  in->n_scnum = (short) H_GET_16 (abfd, ext->e_scnum);
+  in->n_scnum = pe_decode_sym_section_number (abfd, ext->e_scnum);
 
   if (sizeof (ext->e_type) == 2)
     in->n_type = H_GET_16 (abfd, ext->e_type);
@@ -262,7 +305,7 @@ _bfd_XXi_swap_sym_out (bfd * abfd, void * inp, void * extp)
     }
 
   H_PUT_32 (abfd, in->n_value, ext->e_value);
-  H_PUT_16 (abfd, in->n_scnum, ext->e_scnum);
+  pe_encode_sym_section_number (abfd, in->n_scnum, ext->e_scnum);
 
   if (sizeof (ext->e_type) == 2)
     H_PUT_16 (abfd, in->n_type, ext->e_type);
diff --git a/gas/testsuite/gas/pe/large-obj-normal.d b/gas/testsuite/gas/pe/large-obj-normal.d
new file mode 100644
index 0000000000..e9009e5795
--- /dev/null
+++ b/gas/testsuite/gas/pe/large-obj-normal.d
@@ -0,0 +1,17 @@
+#objdump: -h -t
+#name: PE large normal object after raising the normal section limit
+
+# This only becomes meaningful once normal PE/COFF is allowed past the
+# old 32767-section cutoff.  Before that, BFD errors out or auto-promotes
+# to bigobj before the normal 16-bit symbol-section encoding is exercised.
+
+.*: *file format pe-(aarch64-little|i386|x86-64)
+
+Sections:
+#...
+40002 +\.data\$a39999  .*
+                  CONTENTS, ALLOC, LOAD, DATA
+
+SYMBOL TABLE:
+#...
+.*\(sec 40003\).*\(scl +2\).*\) 0x[0-9a-f]+ a39999$
diff --git a/gas/testsuite/gas/pe/large-obj-normal.s b/gas/testsuite/gas/pe/large-obj-normal.s
new file mode 100644
index 0000000000..254733023d
--- /dev/null
+++ b/gas/testsuite/gas/pe/large-obj-normal.s
@@ -0,0 +1,16 @@
+	.file "large-obj-normal.s"
+
+	.irp n,0,1,2,3
+	.irp m,0,1,2,3,4,5,6,7,8,9
+	.irp c,0,1,2,3,4,5,6,7,8,9
+	.irp d,0,1,2,3,4,5,6,7,8,9
+	.irp u,0,1,2,3,4,5,6,7,8,9
+	.globl a\n\m\c\d\u
+	.section .data$a\n\m\c\d\u,"w"
+a\n\m\c\d\u :
+	.byte 1
+	.endr
+	.endr
+	.endr
+	.endr
+	.endr
diff --git a/gas/testsuite/gas/pe/pe.exp b/gas/testsuite/gas/pe/pe.exp
index 82f217cf94..600fd2425a 100644
--- a/gas/testsuite/gas/pe/pe.exp
+++ b/gas/testsuite/gas/pe/pe.exp
@@ -71,6 +71,7 @@ if {[istarget "aarch64-*-pe*"] || [istarget "aarch64-*-mingw*"]} {
 if { [istarget "aarch64-*-*"]
      || ([istarget "i*86-*-*"] && ![istarget "*-*-interix*"])
      || [istarget "x86_64-*-*"] } then {
+	run_dump_test "large-obj-normal"
 	run_dump_test "big-obj"
 	run_dump_test "big-obj-auto"
 }
diff --git a/include/coff/pe.h b/include/coff/pe.h
index ece4bf25db..133548ff4b 100644
--- a/include/coff/pe.h
+++ b/include/coff/pe.h
@@ -388,6 +388,11 @@ struct external_SYMBOL_EX
   char e_numaux[1];
 } ATTRIBUTE_PACKED ;
 
+#define IMAGE_SYM_UNDEFINED      0
+#define IMAGE_SYM_ABSOLUTE       0xffff
+#define IMAGE_SYM_DEBUG          0xfffe
+#define IMAGE_SYM_SECTION_MAX    0xfeff
+
 #define	SYMENT_BIGOBJ	struct external_SYMBOL_EX
 #define	SYMESZ_BIGOBJ	20
 
-- 
2.55.0.windows.1


From macro@orcam.me.uk  Tue Jun 30 23:06:18 2026
From: macro@orcam.me.uk (Maciej W. Rozycki)
Date: Wed, 1 Jul 2026 00:06:18 +0100 (BST)
Subject: [PATCH v2] ld/testsuite: add support for remote testing in
 ld-cdtest
In-Reply-To: <CAJ307Ej5cutoMYAt3hGkubD3VsMc0xXtrQtOeRmEWhG5OLwMzg@mail.gmail.com>
References: <20260618075856.2258643-1-chigot@adacore.com>
 <CAJ307EghSg-BPajFHCG-3HqA5VF0FwoEoE92CMfNW5WWMqu4ug@mail.gmail.com>
 <CAJ307Ej5cutoMYAt3hGkubD3VsMc0xXtrQtOeRmEWhG5OLwMzg@mail.gmail.com>
Message-ID: <alpine.DEB.2.21.2606301537170.28563@angie.orcam.me.uk>

On Tue, 30 Jun 2026, Cl?ment Chigot wrote:

> > > This converts the existing to code to use "remote_load" allowing
> > > execution on both native and remote targets.
> > >
> > > The "diff" between the output and the expected result has been
> > > transformed to the usual regexp_diff. The previous could have been
> > > transformed into `remote_exec build diff` but tends to be fickled with
> > > new lines.
> >
> > Arf got Maciej's Redhat email rejected. Trying with macro@orcam.me.uk.
> 
> Gentle ping to Maciej.

 Hectic time here since I got back online on Jun 22nd, after a holiday.  

 I can see this works correctly here with native `powerpc64le-linux-gnu' 
system as well as remote `mips-linux-gnu' cross target, enabling the tests 
in the latter case.  I have looked through the change and it seems good to 
me except for one nit across two places; see below.

> > > diff --git a/ld/testsuite/ld-cdtest/cdtest.exp b/ld/testsuite/ld-cdtest/cdtest.exp
> > > index 89fdd581abb..81547af3c9e 100644
> > > --- a/ld/testsuite/ld-cdtest/cdtest.exp
> > > +++ b/ld/testsuite/ld-cdtest/cdtest.exp
> > > @@ -51,44 +47,39 @@ set expected_output "$srcdir/$subdir/cdtest.dat"
> > >  if ![ld_link $CC_FOR_TARGET tmpdir/cdtest "$CFLAGS_FOR_TARGET tmpdir/cdtest-foo.o tmpdir/cdtest-bar.o tmpdir/cdtest-main.o"] {
> > >      fail $test1
> > >  } else {
> > > -    send_log   "tmpdir/cdtest >tmpdir/cdtest.out\n"
> > > -    verbose    "tmpdir/cdtest >tmpdir/cdtest.out"
> > > -    catch "exec tmpdir/cdtest >tmpdir/cdtest.out" exec_output
> > > +    set failed 0
> > >
> > > -    if ![string match "" $exec_output] then {
> > > +    send_log "Running: tmpdir/cdtest\n"
> > > +    verbose "Running: tmpdir/cdtest"
> > > +    set state [remote_load target tmpdir/cdtest]
> > > +    set status [lindex $state 0]
> > > +    set exec_output [lindex $state 1]
> > > +
> > > +    if { $status != "pass"  } {
> > >         send_log "$exec_output\n"
> > >         verbose "$exec_output" 1
> > > -
> > > -       fail $test1
> > > +       set failed 1
> > >      } else {
> > > -       send_log   "diff tmpdir/cdtest.out $expected_output\n"
> > > -       verbose    "diff tmpdir/cdtest.out $expected_output"
> > > -       catch "exec diff tmpdir/cdtest.out $expected_output" exec_output
> > > -       set exec_output [prune_warnings $exec_output]
> > > -
> > > -       if ![string match "" $exec_output] then {
> > > -           send_log "$exec_output\n"
> > > -           verbose  "$exec_output" 1
> > > +       set output_filename "tmpdir/cdtest.out"
> > > +       set_file_contents $output_filename $exec_output
> > >
> > > +       send_log [file_contents $output_filename]
> > > +       verbose [file_contents $output_filename] 2
> > > +       if [regexp_diff $output_filename $expected_output] {
> > >             send_log "Checking against Named Return Value optimization\n"
> > >             verbose  "Checking against Named Return Value optimization" 1
> > >
> > >             set expected_output "$srcdir/$subdir/cdtest-nrv.dat"
> > > -
> > > -           send_log   "diff tmpdir/cdtest.out $expected_output\n"
> > > -           verbose    "diff tmpdir/cdtest.out $expected_output"
> > > -           catch "exec diff tmpdir/cdtest.out $expected_output" exec_output
> > > -           set exec_output [prune_warnings $exec_output]
> > > +           if [regexp_diff $output_filename $expected_output] {
> > > +               set failed 1
> > > +           }
> > >         }
> > > +    }
> > >
> > > -       if [string match "" $exec_output] then {
> > > -           pass $test1
> > > -       } else {
> > > -           send_log "$exec_output\n"
> > > -           verbose  "$exec_output" 1
> > > -
> > > -           fail $test1
> > > -       }
> > > +    if { $failed != 0 } {

 I find checking a boolean value against zero superfluous and tougher to 
parse for a human being.  How about just:

    if { $failed } {

instead?

> > >      } else {
> > > -       send_log   "tmpdir/cdtest >tmpdir/cdtest.out\n"
> > > -       verbose    "tmpdir/cdtest >tmpdir/cdtest.out"
> > > -       catch "exec tmpdir/cdtest >tmpdir/cdtest.out" exec_output
> > > +       set failed 0
> > > +
> > > +       send_log "Running: tmpdir/cdtest\n"
> > > +       verbose "Running: tmpdir/cdtest"
> > > +       set state [remote_load target tmpdir/cdtest]
> > > +       set status [lindex $state 0]
> > > +       set exec_output [lindex $state 1]
> > >
> > > -       if ![string match "" $exec_output] then {
> > > +       if { $status != "pass" } {
> > >             send_log "$exec_output\n"
> > > -           verbose  "$exec_output" 1
> > > +           verbose "$exec_output" 1
> > > +           set failed 1
> > > +       } else {
> > > +           set output_filename "tmpdir/cdtest.out"
> > > +           set_file_contents $output_filename $exec_output
> > >
> > > +           send_log [file_contents $output_filename]
> > > +           verbose [file_contents $output_filename] 2
> > > +           if [regexp_diff $output_filename $expected_output] {
> > > +               set failed 1
> > > +           }
> > > +       }
> > > +
> > > +       if { $failed != 0 } {

 Likewise.

 I can't approve, but I can see Alan has got that covered already and I 
suppose won't object my suggestion.  Thank you for your contribution, a 
worthwhile test robustness improvement.

  Maciej

From amodra@gmail.com  Tue Jun 30 23:52:25 2026
From: amodra@gmail.com (Alan Modra)
Date: Wed, 1 Jul 2026 09:22:25 +0930
Subject: [PATCH 3/3] ld/testsuite: Add comprehensive PE COFF weak
 external tests
In-Reply-To: <059426f9f0166c1bc11d54587e5a3c61@disroot.org>
References: <20260530191522.57144-1-peter0x44@disroot.org>
 <20260530191522.57144-4-peter0x44@disroot.org>
 <ah1hT8vkse-L4QqG@squeak.grove.modra.org>
 <059426f9f0166c1bc11d54587e5a3c61@disroot.org>
Message-ID: <akRWucmJ5Ih535lU@squeak.grove.modra.org>

On Sun, Jun 07, 2026 at 10:19:36PM +0200, Peter Damianov wrote:
> On 2026-06-01 12:39, Alan Modra wrote:
> > On Sat, May 30, 2026 at 03:15:22PM -0400, Peter Damianov wrote:
> > > Add tests covering the full matrix of weak/strong symbol interactions
> > > for PE COFF weak externals, based on testcases by Martin Storsjo.
> > 
> > On a cross build of x86_64-w64-mingw32 from x86_64-linux with gcc
> > 13.2.0-6ubuntu1+26.1 installed, I see
> > x86_64-w64-mingw32  +FAIL: weak external: strong undef + weak def (link)
> > x86_64-w64-mingw32  +FAIL: weak external: duplicate weak defs (link)
> 
> I tried this myself, and while I don't know for sure what is wrong for you,
> I saw these logs:
> 
> ERROR:
> ************************************************************************
> ERROR: Your compiler apparently ignores -B when choosing ld.
> ERROR: Hint: don't configure gcc using --with-ld (or --with-as)
> ERROR: You will not be testing the new ld in many of the following tests.
> ERROR: It seems you will be testing /usr/bin/x86_64-w64-mingw32-ld instead.
> ERROR:
> ************************************************************************
> 
> So I suspect it's testing the wrong LD.

Right, I should have checked that before I tried your patch set, and
worked around the compiler config problem by installing sym-links.

I have committed your v3 patchset upstream.  I think there are some
potential buffer overflow problems reading aux entries from fuzzed
object files, but at least some of those are pre-existing.

> FAIL: weak external: strong undef + weak def (link)
> FAIL: weak external: duplicate weak defs (link)
> 
> I did manage to reproduce your same failures, but my local gcc which is
> probably configured differently is fine.
> 

-- 
Alan Modra

