[PATCH v4 02/12] bfd/RISC-V: Zve{32, 64}f don't need to explicitly imply Zvl{32,64}b

[Nelson Chu]

Yeah right, thanks.

(Not related to this patch)  To be honest, I’ve been debating whether
this "table implies order" approach is actually a good thing.  While
it significantly reduces the number of table entries, in practice,
every time people add a new rule, they have to be extremely careful to
ensure the order is correct.  Would it be better to define some macro
to represent parts of the rules?

Nelson

On Fri, Jul 24, 2026 at 6:02 PM Jan Beulich <jbeulich@suse.com> wrote:
>
> The former referencing Zve{32,64}x already ensures the wanted implication.
> No need to perform excess processing.
> ---
> v4: New.
>
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1268,8 +1268,8 @@ static const struct riscv_implicit_subse
>    {"zvqwdota16i", "+zve64x", check_implicit_always},
>
>    {"zve64d", "+d,+zve64f", check_implicit_always},
> -  {"zve64f", "+zve32f,+zve64x,+zvl64b", check_implicit_always},
> -  {"zve32f", "+f,+zve32x,+zvl32b", check_implicit_always},
> +  {"zve64f", "+zve32f,+zve64x", check_implicit_always},
> +  {"zve32f", "+f,+zve32x", check_implicit_always},
>    {"zve64x", "+zve32x,+zvl64b", check_implicit_always},
>    {"zve32x", "+zvl32b,+zicsr", check_implicit_always},
>
>