[PATCH v3 04/13] bfd/RISC-V: Zv{b,k}* imply Zve32x

[Nelson Chu]

On Fri, Jun 19, 2026 at 7:48 PM Jan Beulich <jbeulich@suse.com> wrote:
>
> The specification is quite explicit about this.

OK, thanks.  As for ...

> Is the placement of "zve32x" after "zvbb" / "zvbc" actually correct? While
> riscv_compare_subsets() indeed does a mere strcasecmp() past "zv", it
> seems unlikely to be mere chance that Zve* come ahead of all other Zv* in
> riscv_supported_std_z_ext[].

... I checked the ISA spec again from here,
https://github.com/riscv/riscv-isa-manual/blob/main/src/unpriv/naming.adoc#additional-standard-unprivileged-extension-names,

"If multiple ext:z[] extensions are named, they should be ordered
first by category, then alphabetically within a category — for
example, Zicsr_Zifencei_Ztso"
So I think since the alphabetical order, zve* should be placed after
zvb*.  The order of riscv_supported_* tables doesn't affect the final
output, but it would be good to be maintained in the right order.

Btw (not related to this patch), the spec also said "The name must end
with an alphabetical character. The second letter from the end cannot
be numeric if the last letter is p".  I recall that some of the
ratified extensions violate this rule by ending with a number, though
I forget exactly which ones. In any case, unless the spec has been
updated, I personally wouldn't want to see them forced into
binutils...

Thanks
Nelson

>
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1306,6 +1306,15 @@ static const struct riscv_implicit_subse
>    {"zvksc", "+zvks,+zvbc", check_implicit_always},
>    {"zvks", "+zvksed,+zvksh,+zvkb,+zvkt", check_implicit_always},
>
> +  {"zvbc", "+zve32x", check_implicit_always},
> +  {"zvkb", "+zve32x", check_implicit_always},
> +  {"zvkg", "+zve32x", check_implicit_always},
> +  {"zvkned", "+zve32x", check_implicit_always},
> +  {"zvknha", "+zve32x", check_implicit_always},
> +  {"zvknhb", "+zve32x", check_implicit_always},
> +  {"zvksed", "+zve32x", check_implicit_always},
> +  {"zvksh", "+zve32x", check_implicit_always},
> +
>    {"sdtrig", "+zicsr", check_implicit_always},
>
>    {"smaia", "+ssaia", check_implicit_always},
> --- a/gas/testsuite/gas/riscv/imply.d
> +++ b/gas/testsuite/gas/riscv/imply.d
> @@ -87,13 +87,13 @@ SYMBOL TABLE:
>  [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0
>  [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0
>  [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0
> -[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zvbb1p0_zvkb1p0
> -[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0
> -[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zvbc1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0
> -[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0
> -[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0
> -[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zvbc1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0
> -[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0
> +[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zvbb1p0_zve32x1p0_zvkb1p0
> +[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zve32x1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0
> +[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zvbc1p0_zve32x1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0
> +[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zve32x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0
> +[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zve32x1p0_zvkb1p0_zvkg1p0_zvks1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0
> +[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zvbc1p0_zve32x1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0
> +[0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zve32x1p0_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0
>  [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_sdtrig1p0
>  [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_smaia1p0_ssaia1p0
>  [0-9a-f]+ l       .text        0+000 \$xrv32i2p1_zicsr2p0_smcdeleg1p0_ssccfg1p0_sscsrind1p0
>