[PATCH] x86: separate AVX10.1-aux from AVX10.2

[Jiang, Haochen]

> From: Jan Beulich <jbeulich@suse.com>
> Sent: Friday, July 10, 2026 8:23 PM
> 
> Making a dependency chain 10.1 -> 10.1aux -> 10.2 (and soon ->10.2aux) is

Just for clarification, but won't affect this patch, Intel will follow this, but I can't
speak for AMD if this is true.

> easier than having respective templates specify AVX10_1_AUX|AVX10_2. Are
> there clear reasons speaking against this approach?
> 

I believe this is the right approach for Intel and AMD current implementation.
If there is any other vendors against that, they could change afterwards.

> I'm unconvinced of spelling out the (largely deprecated) avx10.1aux/512
> etc forms in the doc. Perhaps that shouldn't even have been done for
> AVX10.2.

I agree with the current documentation based on current 512-bit vector
size support on all HW.

> 
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -1247,13 +1247,14 @@ static const arch_entry cpu_arch[] =
>    VECARCH (sm4, SM4, ANY_SM4, reset),
>    SUBARCH (pbndkb, PBNDKB, PBNDKB, false),
>    VECARCH (avx10.1, AVX10_1, ANY_AVX512F, set),
> +  VECARCH (avx10.1aux, AVX10_1_AUX, ANY_AVX10_1_AUX, set),

Maybe avx10_v1_aux instead of avx10.1aux to align with documentation?

> --- a/opcodes/i386-opc.h
> +++ b/opcodes/i386-opc.h
> @@ -209,6 +209,8 @@ enum i386_cpu
>    CpuAVX512_VP2INTERSECT,
>    /* AMD AVX-512 BMM Instructions support required.  */
>    CpuAVX512_BMM,
> +  /* Intel AVX10.1-aux Instructions support required.  */

For those joint ISAs, we might need to use x86 in the future
instead of Intel/AMD.

> +  CpuAVX10_1_AUX,

Thx,
Haochen