[committed 4/5] aarch64: Tidy architecture extensions documentation

[Alice Carlotti]

Document mops_go, add some missing full stops, and fix alphabetization
mistakes.


diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 8acf8c56dc63b5c57574418b98ddea2cfaa206a7..0620ad8f4d216f99355ab50f1da63ca21db5c5b7 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -194,8 +194,14 @@ automatically cause those extensions to be disabled.
  @tab Enable the 128-bit Page Descriptor Extension.  This implies @code{lse128}.
 @item @code{dotprod} @tab @code{simd}
  @tab Enable the Dot Product extension.
+@item @code{f16f32dot} @tab @code{simd}, @code{fp16}
+ @tab Enable Armv9.7 f16f32dot instructions.
+@item @code{f16f32mm} @tab @code{simd}, @code{fp16}
+ @tab Enable Armv9.7 f16f32mm instructions.
+@item @code{f16mm} @tab @code{simd}, @code{fp16}
+ @tab Enable f16mm instructions.
 @item @code{f32mm} @tab @code{sve}
- @tab Enable the F32 Matrix Multiply extension
+ @tab Enable the F32 Matrix Multiply extension.
 @item @code{f64mm} @tab @code{sve}
  @tab Enable the F64 Matrix Multiply extension.
 @item @code{f8f16mm} @tab @code{simd} @code{fp8}
@@ -224,12 +230,6 @@ automatically cause those extensions to be disabled.
  @tab Enable Armv8.2 16-bit floating-point multiplication variant support.
 @item @code{fp16} @tab @code{fp}
  @tab Enable Armv8.2 16-bit floating-point support.
-@item @code{f16f32dot} @tab @code{simd}, @code{fp16}
- @tab Enable Armv9.7 f16f32dot instructions.
-@item @code{f16f32mm} @tab @code{simd}, @code{fp16}
- @tab Enable Armv9.7 f16f32mm instructions.
-@item @code{f16mm} @tab @code{simd}, @code{fp16}
- @tab Enable support f16mm instructions.
 @item @code{fprcvt} @tab @code{fp}
  @tab Enable Armv9.6 fprcvt instructions.
 @item @code{frintts} @tab @code{fp}
@@ -239,7 +239,7 @@ automatically cause those extensions to be disabled.
 @item @code{gcs} @tab
  @tab Enable the Guarded Control Stack Extension.
 @item @code{hbc} @tab
- @tab Enable Armv8.8-A hinted conditional branch instructions
+ @tab Enable Armv8.8-A hinted conditional branch instructions.
 @item @code{i8mm} @tab @code{simd}
  @tab Enable the Int8 Matrix Multiply extension.
 @item @code{ite} @tab
@@ -264,18 +264,22 @@ automatically cause those extensions to be disabled.
  @tab Enable the Lookup Table (LUT) extension.
 @item @code{memtag} @tab
  @tab Enable Armv8.5-A Memory Tagging Extensions.
-@item @code{mtetc} @tab @code{memtag}
- @tab Enable Data cache tag block operations.
 @item @code{mops} @tab
- @tab Enable Armv8.8-A memcpy and memset acceleration instructions
+ @tab Enable Armv8.8-A memcpy and memset acceleration instructions.
+@item @code{mops-go} @tab @code{mops}, @code{memtag}
+ @tab Enable tag only variants of MOPS instructions.
 @item @code{mpamv2} @tab
  @tab Enable MPAMv2 system registers.
+@item @code{mtetc} @tab @code{memtag}
+ @tab Enable Data cache tag block operations.
 @item @code{occmo} @tab
  @tab Enable Outer Cacheable Cache Maintenance Operations.
 @item @code{pan} @tab
  @tab Enable Privileged Access Never support.
 @item @code{pauth} @tab
  @tab Enable Pointer Authentication.
+@item @code{poe2} @tab
+ @tab Enable Permission overlays extension 2.
 @item @code{pops} @tab
  @tab Enable Point of Physical Storage.
 @item @code{predres} @tab
@@ -284,8 +288,6 @@ automatically cause those extensions to be disabled.
  @tab Enable additional prediction restriction instructions.
 @item @code{profile} @tab
  @tab Enable statistical profiling extensions.
-@item @code{poe2} @tab
- @tab Enable Permission overlays extension 2.
 @item @code{ras} @tab
  @tab Enable the Reliability, Availability and Serviceability extension.
 @item @code{rasv2} @tab @code{ras}
@@ -360,14 +362,14 @@ automatically cause those extensions to be disabled.
  @tab Enable the SVE2 AES and PMULL Extensions.
 @item @code{sve-aes2} @tab
 @tab Enable the SVE-AES2 extension.
-@item @code{sve-bitperm} @tab
- @tab Enable the SVE2 BITPERM Extension.
 @item @code{sve-b16b16} @tab
 @tab Enable the SVE B16B16 extension.  These instructions also require either @code{+sve2} or @code{+sme2}.
 @item @code{sve-b16mm} @tab @code{sve}
  @tab Enable the SVE B16MM Extension.
 @item @code{sve-bfscale} @tab
 @tab Enable the SVE BFSCALE extension. These instructions also require either @code{+sve2} or @code{+sme2}.
+@item @code{sve-bitperm} @tab
+ @tab Enable the SVE2 BITPERM Extension.
 @item @code{sve-f16f32mm} @tab @code{sve}
 @tab Enable the SVE_F16F32MM extension.
 @item @code{sve2} @tab @code{sve}
@@ -386,14 +388,14 @@ automatically cause those extensions to be disabled.
  @tab Enable SVE2.2.
 @item @code{sve2p3} @tab @code{sve2p2}
  @tab Enable SVE2.3.
+@item @code{tev} @tab
+ @tab TIndex Exception-like Vector Extension.
 @item @code{the} @tab
  @tab Enable the Translation Hardening Extension.
 @item @code{tlbid} @tab
  @tab Enable the TLBI Domains Extension.
 @item @code{tme} @tab
  @tab Enable the Transactional Memory Extension.
-@item @code{tev} @tab
- @tab TIndex Exception-like Vector Extension.
 @item @code{wfxt} @tab
  @tab Enable @code{wfet} and @code{wfit} instructions.
 @item @code{xs} @tab