[PATCH v2 0/4] aarch64: Add support for FEAT_TLBID feature
Alice Carlotti
alice.carlotti@arm.com
Sat Jan 24 07:15:30 GMT 2026
On Fri, Jan 23, 2026 at 10:25:26PM +0000, Srinath Parvathaneni wrote:
> Changes V1 -> V2:
>
> [PATCH 1/4]:
> * Restore the original “selected processor” error
> message for TLBI/PLBI.
> * Reorder documentation alphabetically and update tests.
> * Explicitly add TLBID to TLBI table macro expansions.
>
> [PATCH 2/4]:
> * Add D128 to the clear-features list.
> * Add a negative test for -march=armv9.4-a+tlbid+nod128.
> * Explicitly add TLBID, D128_TLBID, and D128 to TLBI
> table macro expansions.
>
> [PATCH 3/4]:
> * Explicitly add TLBID and POE2 to PLBI table macro expansions.
>
> [PATCH 4/4]:
> * Already approved; rebased only.
>
> > As a general remark, I'd like to rework how we handle system instruction
> > register operands in the near future, so we can handle all the corner cases
> > more easily an consistently. In particular, I think it would be worth adapting
> > our existing 'brb' disassembly output and using a similar approach for other
> > system registers, and I think it would be sensible to move the register operand
> > checking into the parsing and/or fallback functions for that optional register.
>
> > That would be a significant refactor that mostly affects existing instructions,
> > so it should wait until after the release. So for this patch we can try to
> > minimise the changes and work around the existing code flow where possible.
>
> > Does this sound like a reasonable approach for now?
>
> > I'll also note that I've not reviewed the exact list of operations affected by
> > FEAT_TLBID yet.
>
> Yes, that sounds reasonable and achievable for now. I agree the
> existing implementation isn’t very convincing, and properly
> addressing all corner cases would require a larger, time
> consuming refactor, so minimizing changes until after the
> release makes sense.
>
> -----------------
> Hi,
>
> TLBI Domains feature changes TLBI, TLBIP and PLBI
> system instructions. For the TLBI/PLBI instruction
> with optional register argument <Rt> == 0b1111,
> with FEAT_TLBID enabled they are permitted to have
> an Rt value which is not 0b11111 and this is allowed
> for all the TLBI/PLBI instructions with a <type> of
> ALLE1*, ALLE2*, VMALL*, VMALLS12* or VMALLWS2* and a
> <shareability> of IS or OS.
>
> For all TLBIP *E1IS*, TLBIP *E1OS*, TLBIP *E2IS* and
> TLBIP *E2OS* instructions that are currently dependent
> on FEAT_D128 (+d128), will also be available with
> FEAT_TLBID (+tlbid).
>
> TLBID introduces following system registers.
>
> * tlbididr_el1 (RO)
> * vtlbid0_el2
> * vtlbid1_el2
> * vtlbid2_el2
> * vtlbid3_el2
> * vtlbidos0_el2
> * vtlbidos1_el2
> * vtlbidos2_el2
> * vtlbidos3_el2
>
> This patch series adds support for FEAT_TLBID feature,
> which is enabled by new +tlbid option.
>
> Regression tested for aarch64-none-elf target and found no
> regressions.
>
> Ok for binutils-master?
OK, thanks!
I'll commit this for you now, since we're branching later today.
Alice
>
> Regards,
> Srinath
>
> Srinath Parvathaneni (4):
> aarch64: Add support for FEAT_TLBID feature
> aarch64: Enable TLBIP instructions with tlbid option
> aarch64: TLBI Domains changes for PLBI instruction
> aarch64: Add support for TLBID system registers
>
> gas/config/tc-aarch64.c | 18 +-
> gas/doc/c-aarch64.texi | 2 +
> gas/testsuite/gas/aarch64/plbi-invalid-1.l | 48 ++--
> .../gas/aarch64/sysreg/tlbid-sysreg-1.d | 27 ++
> .../gas/aarch64/sysreg/tlbid-sysreg-1.s | 14 +
> gas/testsuite/gas/aarch64/tlbid-1.d | 32 +++
> gas/testsuite/gas/aarch64/tlbid-1.s | 28 ++
> gas/testsuite/gas/aarch64/tlbid-2.d | 73 ++++++
> gas/testsuite/gas/aarch64/tlbid-2.s | 67 +++++
> gas/testsuite/gas/aarch64/tlbid-3.d | 20 ++
> gas/testsuite/gas/aarch64/tlbid-3.s | 12 +
> gas/testsuite/gas/aarch64/tlbid-invalid-1.d | 3 +
> gas/testsuite/gas/aarch64/tlbid-invalid-1.l | 43 ++++
> gas/testsuite/gas/aarch64/tlbid-invalid-1.s | 20 ++
> gas/testsuite/gas/aarch64/tlbid-invalid-2.d | 5 +
> gas/testsuite/gas/aarch64/tlbid-invalid-2.l | 57 +++++
> gas/testsuite/gas/aarch64/tlbid-invalid-3.d | 4 +
> gas/testsuite/gas/aarch64/tlbid-invalid-3.l | 129 ++++++++++
> gas/testsuite/gas/aarch64/tlbid-invalid-4.d | 4 +
> gas/testsuite/gas/aarch64/tlbid-invalid-4.l | 13 +
> .../gas/aarch64/tlbid-nod128-invalid-1.d | 4 +
> .../gas/aarch64/tlbid-nod128-invalid-1.l | 57 +++++
> .../gas/aarch64/tlbid-nod128-invalid-1.s | 56 ++++
> include/opcode/aarch64.h | 5 +
> opcodes/aarch64-dis.c | 7 +-
> opcodes/aarch64-opc.c | 240 +++++++++++-------
> opcodes/aarch64-opc.h | 3 +
> opcodes/aarch64-sys-regs.def | 9 +
> opcodes/aarch64-tbl.h | 7 +-
> 29 files changed, 888 insertions(+), 119 deletions(-)
> create mode 100644 gas/testsuite/gas/aarch64/sysreg/tlbid-sysreg-1.d
> create mode 100644 gas/testsuite/gas/aarch64/sysreg/tlbid-sysreg-1.s
> create mode 100644 gas/testsuite/gas/aarch64/tlbid-1.d
> create mode 100644 gas/testsuite/gas/aarch64/tlbid-1.s
> create mode 100644 gas/testsuite/gas/aarch64/tlbid-2.d
> create mode 100644 gas/testsuite/gas/aarch64/tlbid-2.s
> create mode 100644 gas/testsuite/gas/aarch64/tlbid-3.d
> create mode 100644 gas/testsuite/gas/aarch64/tlbid-3.s
> create mode 100644 gas/testsuite/gas/aarch64/tlbid-invalid-1.d
> create mode 100644 gas/testsuite/gas/aarch64/tlbid-invalid-1.l
> create mode 100644 gas/testsuite/gas/aarch64/tlbid-invalid-1.s
> create mode 100644 gas/testsuite/gas/aarch64/tlbid-invalid-2.d
> create mode 100644 gas/testsuite/gas/aarch64/tlbid-invalid-2.l
> create mode 100644 gas/testsuite/gas/aarch64/tlbid-invalid-3.d
> create mode 100644 gas/testsuite/gas/aarch64/tlbid-invalid-3.l
> create mode 100644 gas/testsuite/gas/aarch64/tlbid-invalid-4.d
> create mode 100644 gas/testsuite/gas/aarch64/tlbid-invalid-4.l
> create mode 100644 gas/testsuite/gas/aarch64/tlbid-nod128-invalid-1.d
> create mode 100644 gas/testsuite/gas/aarch64/tlbid-nod128-invalid-1.l
> create mode 100644 gas/testsuite/gas/aarch64/tlbid-nod128-invalid-1.s
>
> --
> 2.25.1
>
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