[PATCH v1 4/4] aarch64: Add support for TLBID system registers

[Alice Carlotti]

On Thu, Jan 22, 2026 at 02:41:09PM +0000, Srinath Parvathaneni wrote:
> This patch adds support for following TLBID system registers.

This patch is ok.

Alice

> 
> * tlbididr_el1 (RO)
> * vtlbid0_el2
> * vtlbid1_el2
> * vtlbid2_el2
> * vtlbid3_el2
> * vtlbidos0_el2
> * vtlbidos1_el2
> * vtlbidos2_el2
> * vtlbidos3_el2
> ---
>  .../gas/aarch64/sysreg/tlbid-sysreg-1.d       | 27 +++++++++++++++++++
>  .../gas/aarch64/sysreg/tlbid-sysreg-1.s       | 14 ++++++++++
>  opcodes/aarch64-sys-regs.def                  |  9 +++++++
>  3 files changed, 50 insertions(+)
>  create mode 100644 gas/testsuite/gas/aarch64/sysreg/tlbid-sysreg-1.d
>  create mode 100644 gas/testsuite/gas/aarch64/sysreg/tlbid-sysreg-1.s
> 
> diff --git a/gas/testsuite/gas/aarch64/sysreg/tlbid-sysreg-1.d b/gas/testsuite/gas/aarch64/sysreg/tlbid-sysreg-1.d
> new file mode 100644
> index 00000000000..dc6ad0b9787
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sysreg/tlbid-sysreg-1.d
> @@ -0,0 +1,27 @@
> +#as: -menable-sysreg-checking -I$srcdir/$subdir -march=armv8-a+tlbid
> +#as: -I$srcdir/$subdir -march=armv8-a+tlbid
> +#objdump: -dr
> +[^:]+:     file format .*
> +
> +
> +
> +[^:]+:
> +
> +[^:]+:
> +.*:	d538a4c0 	mrs	x0, tlbididr_el1
> +.*:	d51c2800 	msr	vtlbid0_el2, x0
> +.*:	d53c2800 	mrs	x0, vtlbid0_el2
> +.*:	d51c2820 	msr	vtlbid1_el2, x0
> +.*:	d53c2820 	mrs	x0, vtlbid1_el2
> +.*:	d51c2840 	msr	vtlbid2_el2, x0
> +.*:	d53c2840 	mrs	x0, vtlbid2_el2
> +.*:	d51c2860 	msr	vtlbid3_el2, x0
> +.*:	d53c2860 	mrs	x0, vtlbid3_el2
> +.*:	d51c2900 	msr	vtlbidos0_el2, x0
> +.*:	d53c2900 	mrs	x0, vtlbidos0_el2
> +.*:	d51c2920 	msr	vtlbidos1_el2, x0
> +.*:	d53c2920 	mrs	x0, vtlbidos1_el2
> +.*:	d51c2940 	msr	vtlbidos2_el2, x0
> +.*:	d53c2940 	mrs	x0, vtlbidos2_el2
> +.*:	d51c2960 	msr	vtlbidos3_el2, x0
> +.*:	d53c2960 	mrs	x0, vtlbidos3_el2
> diff --git a/gas/testsuite/gas/aarch64/sysreg/tlbid-sysreg-1.s b/gas/testsuite/gas/aarch64/sysreg/tlbid-sysreg-1.s
> new file mode 100644
> index 00000000000..c10ab8af402
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sysreg/tlbid-sysreg-1.s
> @@ -0,0 +1,14 @@
> +.include "sysreg-test-utils.inc"
> +
> +.text
> +
> +.arch	armv8-a+tlbid
> +rw_sys_reg tlbididr_el1 w=0
> +rw_sys_reg vtlbid0_el2
> +rw_sys_reg vtlbid1_el2
> +rw_sys_reg vtlbid2_el2
> +rw_sys_reg vtlbid3_el2
> +rw_sys_reg vtlbidos0_el2
> +rw_sys_reg vtlbidos1_el2
> +rw_sys_reg vtlbidos2_el2
> +rw_sys_reg vtlbidos3_el2
> diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
> index 86d04b4a874..9daa178ed7b 100644
> --- a/opcodes/aarch64-sys-regs.def
> +++ b/opcodes/aarch64-sys-regs.def
> @@ -1359,6 +1359,7 @@
>    SYSREG ("tindex_el12",	CPENC (3,5,4,0,3),	0,		AARCH64_FEATURE (POE2))
>    SYSREG ("tindex_el2",		CPENC (3,4,4,0,3),	0,		AARCH64_FEATURE (POE2))
>    SYSREG ("tindex_el3",		CPENC (3,6,4,0,3),	0,		AARCH64_FEATURE (POE2))
> +  SYSREG ("tlbididr_el1",	CPENC (3,0,10,4,6),	F_REG_READ,	AARCH64_FEATURE (TLBID))
>    SYSREG ("tpidr2_el0",		CPENC (3,3,13,0,5),	0,		AARCH64_FEATURE (SME))
>    SYSREG ("tpidr3_el0",		CPENC (3,3,13,0,0),     0,		AARCH64_FEATURE (POE2))
>    SYSREG ("tpidr3_el1",		CPENC (3,0,13,0,0),	0,		AARCH64_FEATURE (POE2))
> @@ -1652,6 +1653,14 @@
>    SYSREG ("vstcr_el2",		CPENC (3,4,2,6,2),	0,		AARCH64_FEATURE (V8_3A)) /* SEL2 */
>    SYSREG ("vsttbr_el2",		CPENC (3,4,2,6,0),	0,		AARCH64_FEATURES (2, V8A, V8_3A)) /* SEL2 */
>    SYSREG ("vtcr_el2",		CPENC (3,4,2,1,2),	0,		AARCH64_NO_FEATURES)
> +  SYSREG ("vtlbid0_el2",	CPENC (3,4,2,8,0),	0,		AARCH64_FEATURE (TLBID))
> +  SYSREG ("vtlbid1_el2",	CPENC (3,4,2,8,1),	0,		AARCH64_FEATURE (TLBID))
> +  SYSREG ("vtlbid2_el2",	CPENC (3,4,2,8,2),	0,		AARCH64_FEATURE (TLBID))
> +  SYSREG ("vtlbid3_el2",	CPENC (3,4,2,8,3),	0,		AARCH64_FEATURE (TLBID))
> +  SYSREG ("vtlbidos0_el2",	CPENC (3,4,2,9,0),	0,		AARCH64_FEATURE (TLBID))
> +  SYSREG ("vtlbidos1_el2",	CPENC (3,4,2,9,1),	0,		AARCH64_FEATURE (TLBID))
> +  SYSREG ("vtlbidos2_el2",	CPENC (3,4,2,9,2),	0,		AARCH64_FEATURE (TLBID))
> +  SYSREG ("vtlbidos3_el2",	CPENC (3,4,2,9,3),	0,		AARCH64_FEATURE (TLBID))
>    SYSREG ("vttbr_el2",		CPENC (3,4,2,1,0),	F_REG_128,	AARCH64_FEATURE (V8A))
>    SYSREG ("zcr_el1",		CPENC (3,0,1,2,0),	0,		AARCH64_FEATURE (SVE))
>    SYSREG ("zcr_el12",		CPENC (3,5,1,2,0),	0,		AARCH64_FEATURE (SVE))
> -- 
> 2.25.1
>