[PATCH v2 9/9] Add MIPS Allegrex VFPU conditional move and branching instructions
David Guillen Fandos
david@davidgf.net
Tue Jan 20 23:37:25 GMT 2026
Branch instructions replace the standard CP2 branch instructions (bc2f
and bc2t) mnemonics, even though they are mostly equivalent.
Signed-off-by: David Guillen Fandos <david@davidgf.net>
---
gas/testsuite/gas/mips/allegrex-vfpu.d | 14 ++++++++++++++
gas/testsuite/gas/mips/allegrex-vfpu.s | 16 ++++++++++++++++
gas/testsuite/gas/mips/allegrex@cp2b.d | 13 +++++++++++++
gas/testsuite/gas/mips/allegrex@cp2bl.d | 13 +++++++++++++
opcodes/mips-opc.c | 14 ++++++++++++++
5 files changed, 70 insertions(+)
create mode 100644 gas/testsuite/gas/mips/allegrex@cp2b.d
create mode 100644 gas/testsuite/gas/mips/allegrex@cp2bl.d
diff --git a/gas/testsuite/gas/mips/allegrex-vfpu.d b/gas/testsuite/gas/mips/allegrex-vfpu.d
index 789e5ae6d17..d029d2eb105 100644
--- a/gas/testsuite/gas/mips/allegrex-vfpu.d
+++ b/gas/testsuite/gas/mips/allegrex-vfpu.d
@@ -289,4 +289,18 @@ Disassembly of section .text:
0x00000460 6c202082 vcmp.p LT,R000.p,R000.p
0x00000464 6c20a001 vcmp.t EQ,R000.t,R000.t
0x00000468 6c208085 vcmp.q NE,C000.q,R000.q
+0x0000046c 49090004 bvt 2,[0-9a-fx]+
+0x00000470 490c0003 bvf 3,[0-9a-fx]+
+0x00000474 49070002 bvtl 1,[0-9a-fx]+
+0x00000478 49120001 bvfl 4,[0-9a-fx]+
+0x0000047c 00000000 nop
+0x00000480 00000000 nop
+0x00000484 d2a0e020 vcmovt.t R000.t,R010.t,0
+0x00000488 d2abe020 vcmovf.t R000.t,R010.t,3
+0x0000048c d2a060a0 vcmovt.p R000.p,R020.p,0
+0x00000490 d2ab60a0 vcmovf.p R000.p,R020.p,3
+0x00000494 d2a0a0a0 vcmovt.q R000.q,R000.q,0
+0x00000498 d2aba0a0 vcmovf.q R000.q,R000.q,3
+0x0000049c d2a00100 vcmovt.s S000.s,S010.s,0
+0x000004a0 d2ab0100 vcmovf.s S000.s,S010.s,3
\.\.\.
diff --git a/gas/testsuite/gas/mips/allegrex-vfpu.s b/gas/testsuite/gas/mips/allegrex-vfpu.s
index 79d62dd3c35..45296c5f171 100644
--- a/gas/testsuite/gas/mips/allegrex-vfpu.s
+++ b/gas/testsuite/gas/mips/allegrex-vfpu.s
@@ -279,6 +279,22 @@
vcmp.t 1, R000, R000
vcmp.q NE, C000, R000
+ bvt 2, 1f
+ bvf 3, 1f
+ bvtl 1, 1f
+ bvfl 4, 1f
+ nop
+1:
+ nop
+ vcmovt.t R000, R010, 0
+ vcmovf.t R000, R010, 3
+ vcmovt.p R000, R020, 0
+ vcmovf.p R000, R020, 3
+ vcmovt.q R000, R000, 0
+ vcmovf.q R000, R000, 3
+ vcmovt.s s000, S010, 0
+ vcmovf.s s000, S010, 3
+
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 4, 0
.space 16
diff --git a/gas/testsuite/gas/mips/allegrex@cp2b.d b/gas/testsuite/gas/mips/allegrex@cp2b.d
new file mode 100644
index 00000000000..03371dd20b3
--- /dev/null
+++ b/gas/testsuite/gas/mips/allegrex@cp2b.d
@@ -0,0 +1,13 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 branch instructions
+#as: -32 -march=allegrex
+#source: cp2b.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 49000001 bvf 0,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
+[0-9a-f]+ <[^>]*> 49010001 bvt 0,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/allegrex@cp2bl.d b/gas/testsuite/gas/mips/allegrex@cp2bl.d
new file mode 100644
index 00000000000..3778ce497a2
--- /dev/null
+++ b/gas/testsuite/gas/mips/allegrex@cp2bl.d
@@ -0,0 +1,13 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 branch likely instructions
+#as: -32 -march=allegrex
+#source: cp2bl.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 49020001 bvfl 0,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
+[0-9a-f]+ <[^>]*> 49030001 bvtl 0,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
+ \.\.\.
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index dd480a2a508..e408fd39025 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -168,6 +168,8 @@ decode_mips_operand (const char *p)
case 'k': VFPU_IMM(5, 16, CONST);
case 's': UINT(5, 16);
case 'e': HINT(8, 16);
+ case 'm': UINT(3, 16);
+ case 'b': UINT(3, 18);
default:
abort();
}
@@ -718,6 +720,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"mfvc", "t,?cl.", 0x48600000, 0xffe0ff00, WR_1|RD_C2|CM, 0, ALX, 0, 0 },
{"mtvc", "t,?cl.", 0x48e00000, 0xffe0ff00, RD_1|WR_C2|CM, 0, ALX, 0, 0 },
+{"bvf", "?jb.,p", 0x49000000, 0xffe30000, RD_C2|CBD, 0, ALX, 0, 0 },
+{"bvfl", "?jb.,p", 0x49020000, 0xffe30000, RD_C2|CBD, 0, ALX, 0, 0 },
+{"bvt", "?jb.,p", 0x49010000, 0xffe30000, RD_C2|CBD, 0, ALX, 0, 0 },
+{"bvtl", "?jb.,p", 0x49030000, 0xffe30000, RD_C2|CBD, 0, ALX, 0, 0 },
{"vabs.p", "?d1a,?s1l", 0xd0010080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vabs.q", "?d3a,?s3l", 0xd0018080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vabs.s", "?d0a,?s0l", 0xd0010000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
@@ -737,6 +743,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"vbfy1.q", "?d3a,?s3n", 0xd0428080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vbfy2.q", "?d3a,?s3n", 0xd0438080, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vc2i.s", "?d3l,?s0n", 0xd0390000, 0xffff8080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vcmovf.p", "?d1a,?s1a,?jm.", 0xd2a80080, 0xfff88080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vcmovf.q", "?d3a,?s3a,?jm.", 0xd2a88080, 0xfff88080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vcmovf.s", "?d0a,?s0a,?jm.", 0xd2a80000, 0xfff88080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vcmovf.t", "?d2a,?s2a,?jm.", 0xd2a88000, 0xfff88080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vcmovt.p", "?d1a,?s1a,?jm.", 0xd2a00080, 0xfff88080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vcmovt.q", "?d3a,?s3a,?jm.", 0xd2a08080, 0xfff88080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vcmovt.s", "?d0a,?s0a,?jm.", 0xd2a00000, 0xfff88080, RD_C2|WR_C2, 0, ALX, 0, 0 },
+{"vcmovt.t", "?d2a,?s2a,?jm.", 0xd2a08000, 0xfff88080, RD_C2|WR_C2, 0, ALX, 0, 0 },
{"vcmp.p", "?jc.,?s1a,?t1a", 0x6c000080, 0xff8080f0, RD_C2, 0, ALX, 0, 0 },
{"vcmp.q", "?jc.,?s3a,?t3a", 0x6c008080, 0xff8080f0, RD_C2, 0, ALX, 0, 0 },
{"vcmp.s", "?jc.,?s0a,?t0a", 0x6c000000, 0xff8080f0, RD_C2, 0, ALX, 0, 0 },
--
2.51.1
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