[PATCH v6] PowerPC: Support for Elliptic Curve Cryptography Instructions (RFC02669)
Abhay Kandpal
abhay@linux.ibm.com
Mon Jan 19 15:05:55 GMT 2026
Hi Surya,
This patch is an older version. For the rebasing request,version 7 was released on13th January 2026.
I believe the confusion began around the release ofversion 5, but the comments were mistakenly provided onversion 4.
Those comments were incorporated inversion 6. Subsequently, you asked for rebasing on the latest trunk, for whichversion 7 was released.
BR
Abhay Kandpal
On 19/01/26 19:30, Surya Kumari Jangala wrote:
> Hi,
> I am not able to apply the patch. This patch does not appear to be
> based on the current trunk.
>
> -Surya
>
> On 12/01/26 10:55 pm, Abhay Kandpal wrote:
>> opcodes/
>> * ppc-opc.c: (insert_s3, extract_s3): New functions.
>> (XX3MUL_MASK, XX3SUM_MASK, XX3MADD_MASK, XX4EXT, P_XX4EXT_MASK
>> SFUNC, S0EXP, S1EXP, S2EXP, PSSUM, PSSUMEXT): New defines.
>> (PS, PSD): Update for new macros.
>> (powerpc_opcodes): Add xxmulmul, xxmulmulhiadd, xxmulmulloadd,
>> xxssumudm, xxssumudmc, xsmerge2t3uqm, xsaddadduqm, xsaddaddsuqm,
>> xsaddsubuqm, xsmerge3t1uqm, xsrebase2t1uqm, xsrebase2t2uqm,
>> xsrebase3t3uqm, xsrebase2t3uqm, xsrebase2t4uqm, xsaddsubsuqm,
>> xsmerge2t1uqm, xsmerge2t2uqm, xsrebase3t1uqm, xsrebase3t2uqm,
>> xxssumudmcext.
>>
>> gas/
>> * testsuite/gas/ppc/future.s: New test.
>> * testsuite/gas/ppc/future.d: Likewise.
>> ---
>> This patch is reg tested.
>> Changes from v5 -> v6
>> <Corrected indentation of commit log>
>> <Modified insert_s3()>
>> <Modifed S2EXP macro>
>>
>> gas/testsuite/gas/ppc/future.d | 22 +++++++++
>> gas/testsuite/gas/ppc/future.s | 21 +++++++++
>> opcodes/ppc-opc.c | 84 ++++++++++++++++++++++++++++++++--
>> 3 files changed, 124 insertions(+), 3 deletions(-)
>>
>> diff --git a/gas/testsuite/gas/ppc/future.d b/gas/testsuite/gas/ppc/future.d
>> index efb3ee8428d..5cd15578c93 100644
>> --- a/gas/testsuite/gas/ppc/future.d
>> +++ b/gas/testsuite/gas/ppc/future.d
>> @@ -109,4 +109,26 @@ Disassembly of section \.text:
>> .*: (4c 06 00 7c|7c 00 06 4c) ccmclean
>> .*: (cc 06 00 7c|7c 00 06 cc) ccmrl
>> .*: (26 22 40 7c|7c 40 22 26) mtlpl r4,r2
>> +.*: (0f 36 44 ec|ec 44 36 0f) xxmulmul vs34,vs36,vs38,6
>> +.*: (4d 4d a7 ec|ec a7 4d 4d) xxmulmulhiadd vs37,vs39,vs9,1,0,1
>> +.*: (8f 69 4c ed|ed 4c 69 8f) xxmulmulloadd vs42,vs44,vs45,0,1
>> +.*: (c8 34 85 ec|ec 85 34 c8) xxssumudm vs4,vs5,vs6,1
>> +.*: (c8 39 64 ec|ec 64 39 c8) xxssumudmc vs3,vs4,vs7,0
>> +.*: (07 ab 74 ee|ee 74 ab 07) xsaddadduqm vs51,vs52,vs53
>> +.*: (40 13 01 ec|ec 01 13 40) xsaddaddsuqm vs0,vs1,vs2
>> +.*: (87 fb be ef|ef be fb 87) xsaddsubuqm vs61,vs62,vs63
>> +.*: (00 2f 64 ec|ec 64 2f 00) xsaddsubsuqm vs3,vs4,vs5
>> +.*: (40 57 c8 ec|ec c8 57 40) xsmerge2t1uqm vs6,vs8,vs10
>> +.*: (80 87 8e ed|ed 8e 87 80) xsmerge2t2uqm vs12,vs14,vs16
>> +.*: (c8 a2 53 ee|ee 53 a2 c8) xsmerge2t3uqm vs18,vs19,vs20
>> +.*: (c8 cb b7 ee|ee b7 cb c8) xsmerge3t1uqm vs21,vs23,vs25
>> +.*: (88 f4 7d ef|ef 7d f4 88) xsrebase2t1uqm vs27,vs29,vs30
>> +.*: (8e 0d e0 ef|ef e0 0d 8e) xsrebase2t2uqm vs31,vs32,vs33
>> +.*: (8f 26 43 ec|ec 43 26 8f) xsrebase2t3uqm vs34,vs35,vs36
>> +.*: (cf 2e 64 ec|ec 64 2e cf) xsrebase2t4uqm vs35,vs36,vs37
>> +.*: (8f 47 c7 ec|ec c7 47 8f) xsrebase3t1uqm vs38,vs39,vs40
>> +.*: (cf 5f 2a ed|ed 2a 5f cf) xsrebase3t2uqm vs41,vs42,vs43
>> +.*: (1f 76 8d ed|ed 8d 76 1f) xsrebase3t3uqm vs44,vs45,vs46
>> +.*: (00 00 00 05|05 00 00 00) xxssumudmcext vs35,vs9,vs11,vs13,1
>> +.*: (71 5b 69 88|88 69 5b 71)[[:space:]]*
>> #pass
>> diff --git a/gas/testsuite/gas/ppc/future.s b/gas/testsuite/gas/ppc/future.s
>> index e66465a7418..0bb0e5f0eb1 100644
>> --- a/gas/testsuite/gas/ppc/future.s
>> +++ b/gas/testsuite/gas/ppc/future.s
>> @@ -83,4 +83,25 @@ _start:
>> ccmclean
>> ccmrl
>> mtlpl 4, 2
>> + xxmulmul 34, 36, 38, 6
>> + xxmulmulhiadd 37, 39, 9, 1, 0, 1
>> + xxmulmulloadd 42, 44, 45, 0, 1
>> + xxssumudm 4, 5, 6, 1
>> + xxssumudmc 3, 4, 7, 0
>> + xsaddadduqm 51, 52, 53
>> + xsaddaddsuqm 0, 1, 2
>> + xsaddsubuqm 61, 62, 63
>> + xsaddsubsuqm 3, 4, 5
>> + xsmerge2t1uqm 6, 8, 10
>> + xsmerge2t2uqm 12, 14, 16
>> + xsmerge2t3uqm 18, 19, 20
>> + xsmerge3t1uqm 21, 23, 25
>> + xsrebase2t1uqm 27, 29, 30
>> + xsrebase2t2uqm 31, 32, 33
>> + xsrebase2t3uqm 34, 35, 36
>> + xsrebase2t4uqm 35, 36, 37
>> + xsrebase3t1uqm 38, 39, 40
>> + xsrebase3t2uqm 41, 42, 43
>> + xsrebase3t3uqm 44, 45, 46
>> + xxssumudmcext 35, 9, 11, 13, 1
>>
>> diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
>> index ddf0a8ca69c..39016ab7960 100644
>> --- a/opcodes/ppc-opc.c
>> +++ b/opcodes/ppc-opc.c
>> @@ -2359,6 +2359,31 @@ extract_xab6 (uint64_t insn,
>> return xa6;
>> }
>>
>> +/* The S field in XX3 form bit (21-23) as arithmetic function. */
>> +
>> +static uint64_t
>> +insert_s3 (uint64_t insn,
>> + int64_t value,
>> + ppc_cpu_t dialect ATTRIBUTE_UNUSED,
>> + const char **errmsg)
>> +{
>> + if (value < 0 || value > 6)
>> + *errmsg = _("invalid S value (must be 0 - 6)");
>> + return (insn | ((value & 0x7) << 8));
>> +}
>> +
>> +static int64_t
>> +extract_s3 (uint64_t insn,
>> + ppc_cpu_t dialect ATTRIBUTE_UNUSED,
>> + int *invalid)
>> +{
>> + int64_t value = (insn >> 8) & 0x7;
>> +
>> + if (value == 7)
>> + *invalid = 1;
>> + return value;
>> +}
>> +
>> /* The XC field in an XX4 form instruction. This is split. */
>>
>> static uint64_t
>> @@ -3729,8 +3754,14 @@ const struct powerpc_operand powerpc_operands[] =
>> #define MMMM SIX
>> { 0xf, 11, NULL, NULL, 0 },
>>
>> + /* The P bit in Prefix XX4-form instruction. */
>> +#define PSSUMEXT MMMM + 1
>> + { 0x1, 4, NULL, NULL, 0 },
>> +
>> + /* The S1 bit as an exponent in XX3 form bit (22). */
>> +#define S1EXP PSSUMEXT + 1
>> /* The PS field in a VX form instruction. */
>> -#define PS SIX + 1
>> +#define PS PSSUMEXT + 1
>> { 0x1, 9, NULL, NULL, 0 },
>>
>> /* The SH field in a vector shift double by bit immediate instruction. */
>> @@ -3778,6 +3809,10 @@ const struct powerpc_operand powerpc_operands[] =
>> /* PowerPC paired singles extensions. */
>> /* W bit in the pair singles instructions for x type instructions. */
>> #define PSWM WS + 1
>> + /* The P bit in scaled multiply-sum XX3 form instructions (bit 21). */
>> +#define PSSUM PSWM
>> + /* The S0 bit an exponent in XX3 form bit (21). */
>> +#define S0EXP PSWM
>> /* The BO16 field in a BD8 form instruction. */
>> #define BO16 PSWM
>> /* The pst field in a SVRM form instruction. */
>> @@ -3794,8 +3829,12 @@ const struct powerpc_operand powerpc_operands[] =
>> #define PSQM PSQ + 1
>> { 0x7, 7, 0, 0, PPC_OPERAND_GQR },
>>
>> + /* The S field in XX3 form bit (21-23) as arithmetic function. */
>> +#define SFUNC PSQM + 1
>> + { 0x7, 8, insert_s3, extract_s3, 0 },
>> +
>> /* Smaller D field for quantization in the pair singles instructions. */
>> -#define PSD PSQM + 1
>> +#define PSD SFUNC + 1
>> { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },
>>
>> /* The L field in an mtmsrd or A form instruction or R or W in an
>> @@ -4026,6 +4065,8 @@ const struct powerpc_operand powerpc_operands[] =
>>
>> #define ms vs + 1
>> #define yx ms
>> + /* The S2 bit as an exponent in XX3 form bit (23). */
>> +#define S2EXP ms
>> /* The P field in Galois Field XX3 form instruction. */
>> #define PGF1 yx
>> { 0x1, 8, NULL, NULL, 0 },
>> @@ -4105,6 +4146,7 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
>> #define P_XX4_MASK (PREFIX_MASK | XX4_MASK)
>> #define P_UXX4_MASK (P_XX4_MASK & ~(7ULL << 32))
>> #define P_U8XX4_MASK (P_XX4_MASK & ~(0xffULL << 32))
>> +#define P_XX4EXT_MASK (PREFIX_MASK | XX4EXT (0x3f, 0x1))
>>
>> /* MMIRR:XX3-form 8-byte outer product instructions. */
>> #define P_GER_MASK ((-1ULL << 40) | XX3ACC_MASK)
>> @@ -4597,6 +4639,9 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
>> /* An XX4 form instruction. */
>> #define XX4(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3) << 4))
>>
>> +/* An XX4 form instruction with 1 bit carry extended. */
>> +#define XX4EXT(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1) << 5))
>> +
>> /* A Z form instruction. */
>> #define Z(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1ff) << 1))
>>
>> @@ -4671,10 +4716,11 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
>> /* An X_MASK with two dense math register. */
>> #define XDMRDMR_MASK (X_MASK | RA_MASK | (3 << 21) | (3 << 11))
>>
>> -/* The mask for an XX3 form instruction with the DM or SHW bits
>> +/* The mask for an XX3 form instruction with the S1, S2, DM or SHW bits
>> specified. */
>> #define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
>> #define XX3SHW_MASK XX3DM_MASK
>> +#define XX3MADD_MASK XX3DM_MASK
>>
>> /* The masks for X* form instructions with an ACC/DMR register. */
>> #define XX2ACC_MASK (XX2 (0x3f, 0x1ff) | (3 << 21) | 1)
>> @@ -4694,6 +4740,12 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
>> /* The masks for XX3 GF instructions with P bit. */
>> #define XX3GF_MASK (XX3 (0x3f, 0xff) & ~(1 << 8))
>>
>> +/* The masks for VSX multiply XX3 instructions with scale bits. */
>> +#define XX3MUL_MASK (XX3 (0x3f, 0x1f))
>> +
>> +/* The masks for VSX multiplty-sum XX3 instructions with p bits. */
>> +#define XX3SUM_MASK (XX3 (0x3f, 0x7f))
>> +
>> /* The mask for an XX4 form instruction. */
>> #define XX4_MASK XX4 (0x3f, 0x3)
>>
>> @@ -9164,6 +9216,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
>> {"dadd", XRC(59,2,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
>> {"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
>>
>> +{"xxmulmul", XX3(59,1), XX3MUL_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6, SFUNC}},
>> +
>> {"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
>> {"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}},
>>
>> @@ -9215,6 +9269,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
>> {"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
>> {"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}},
>>
>> +{"xxmulmulhiadd", XX3(59,9), XX3MUL_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6, S0EXP, S1EXP, S2EXP}},
>> {"dmxvi8gerx4pp", XX3(59,10), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
>> {"dmxvi8gerx4", XX3(59,11), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
>>
>> @@ -9224,6 +9279,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
>> {"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
>> {"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}},
>>
>> +{"xxmulmulloadd",XX3(59,17), XX3MADD_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6, S1EXP, S2EXP}},
>> {"dmxvf16ger2pp",XX3(59,18), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>> {"xvf16ger2pp", XX3(59,18), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>> {"dmxvf16ger2", XX3(59,19), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>> @@ -9235,6 +9291,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
>> {"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
>> {"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
>>
>> +{"xxssumudm", XX3(59,25), XX3SUM_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6, PSSUM}},
>> {"dmxvf32gerpp",XX3(59,26), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>> {"xvf32gerpp", XX3(59,26), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>> {"dmxvf32ger", XX3(59,27), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>> @@ -9266,6 +9323,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
>> {"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
>> {"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
>>
>> +{"xxssumudmc", XX3(59,57), XX3SUM_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6, PSSUM}},
>> {"dmxvf64gerpp",XX3(59,58), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}},
>> {"xvf64gerpp", XX3(59,58), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}},
>> {"dmxvf64ger", XX3(59,59), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}},
>> @@ -9294,21 +9352,26 @@ const struct powerpc_opcode powerpc_opcodes[] = {
>> {"dxex", XRC(59,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
>> {"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
>>
>> +{"xsmerge2t3uqm", XX3(59,89), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
>> {"dmxvf32gernp", XX3(59,90), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>> {"xvf32gernp", XX3(59,90), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>> {"dmxvbf16gerx2", XX3(59,91), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
>>
>> +{"xsaddadduqm", XX3(59,96), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
>> {"dmxvi8gerx4spp",XX3(59,98), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
>> {"dmxvi8ger4spp", XX3(59,99), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>> {"xvi8ger4spp", XX3(59,99), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>>
>> +{"xsaddaddsuqm", XX3(59,104), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
>> {"dmxvi16ger2pp", XX3(59,107), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>> {"xvi16ger2pp", XX3(59,107), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>>
>> +{"xsaddsubuqm", XX3(59,112), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
>> {"dmxvbf16ger2np",XX3(59,114), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>> {"xvbf16ger2np", XX3(59,114), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>> {"dmxvbf16gerx2np",XX3(59,115), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
>>
>> +{"xsmerge3t1uqm", XX3(59,121), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
>> {"dmxvf64gernp", XX3(59,122), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}},
>> {"xvf64gernp", XX3(59,122), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}},
>>
>> @@ -9318,6 +9381,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
>> {"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
>> {"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
>>
>> +{"xsrebase2t1uqm",XX3(59,145), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
>> {"dmxvf16ger2pn", XX3(59,146), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>> {"xvf16ger2pn", XX3(59,146), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>> {"dmxvf16gerx2pn",XX3(59,147), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
>> @@ -9330,6 +9394,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
>> {"dtstsf", X(59,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
>> {"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRB}},
>>
>> +{"xsrebase2t2uqm",XX3(59,177), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
>> {"dmxvbf16ger2pn",XX3(59,178), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>> {"xvbf16ger2pn", XX3(59,178), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>> {"dmxvbf16gerx2pn", XX3(59,179),XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
>> @@ -9340,6 +9405,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
>> {"drsp", XRC(59,770,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
>> {"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
>>
>> +{"xsrebase3t3uqm",XX3(59,195), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
>> +
>> {"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
>> {"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}},
>>
>> @@ -9348,6 +9415,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
>> {"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
>> {"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}},
>>
>> +{"xsrebase2t3uqm",XX3(59,209), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
>> {"dmxvf16ger2nn", XX3(59,210), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>> {"xvf16ger2nn", XX3(59,210), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>>
>> @@ -9357,17 +9425,26 @@ const struct powerpc_opcode powerpc_opcodes[] = {
>> {"diex", XRC(59,866,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
>> {"diex.", XRC(59,866,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
>>
>> +{"xsrebase2t4uqm",XX3(59,217), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
>> +
>> {"dmxvf32gernn",XX3(59,218), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>> {"xvf32gernn", XX3(59,218), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>>
>> +{"xsaddsubsuqm", XX3(59,224), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
>> +{"xsmerge2t1uqm", XX3(59,232), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
>> +
>> {"dmxvbf16gerx2nn", XX3(59,234),XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
>>
>> +{"xsmerge2t2uqm", XX3(59,240), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
>> +{"xsrebase3t1uqm",XX3(59,241), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
>> {"dmxvbf16ger2nn",XX3(59,242), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>> {"xvbf16ger2nn", XX3(59,242), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>>
>> {"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
>> {"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}},
>>
>> +{"xsrebase3t2uqm",XX3(59,249), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
>> +
>> {"dmxvf64gernn",XX3(59,250), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}},
>> {"xvf64gernn", XX3(59,250), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}},
>>
>> @@ -9968,6 +10045,7 @@ const struct powerpc_opcode prefix_opcodes[] = {
>> {"xxblendvd", P8RR|XX4(33,3), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
>> {"xxpermx", P8RR|XX4(34,0), P_UXX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6, UIM3}},
>> {"xxeval", P8RR|XX4(34,1), P_U8XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6, UIM8}},
>> +{"xxssumudmcext", P8RR|XX4EXT(34,1), P_XX4EXT_MASK, FUTURE, 0, {XT6, XA6, XB6, XC6, PSSUMEXT}},
>> {"plbz", PMLS|OP(34), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}},
>> {"pstw", PMLS|OP(36), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}},
>> {"pstb", PMLS|OP(38), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}},
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <https://sourceware.org/pipermail/binutils/attachments/20260119/68723cf5/attachment-0001.htm>
More information about the Binutils
mailing list