RFC: Risc-V: Allow assembler to adjust relocs against symbols in mergeable sections

[Jan Beulich]

On 19.01.2026 12:46, Mark Wielaard wrote:
> Hi Florian,
> 
> On Mon, Jan 19, 2026 at 11:53:59AM +0100, Florian Weimer wrote:
>> * Nick Clifton:
>>> +bool
>>> +riscv_fix_adjustable (fixS * fixP)
>>> +{
>>> +  /* PR33723 and 33789: Allow fixups that reference symbols in
>>> +     mergeable sections to be adjusted.  Disallow all others.  */
>>> +  if (fixP->fx_addsy != NULL
>>> +      && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0)
>>> +    return true;
>>> +
>>> +  return false;
>>> +}
>>
>> Is this actually correct for RISC-V, though?  I thought that RISC-V
>> relocations can significantly alter section layout, which means that the
>> offset from the section start that the assembler sees may not match
>> reality after relaxation.
> 
> Yes, in general for sections containing code that is true. But this is
> for relocations to sections containing mergable (debug) string
> tables.

Except that above code has no constraint towards "debug sections only".
In fact, text (i.e. executable) sections can in principle also be
SHF_MERGE, and I'd be curious how merging and relaxing would work
together. (What might save us right now is that iirc sections with
relocations aren't merged [yet].)

Jan

> Currently for RISC-V it generates a symbol and a relocation
> for each string referenced. While for other architectures there is
> just a relocation against the (start of) the string table section
> symbol. It seems like relocations to string tables can generally be
> expressed without an extra symbol.
> 
> Cheers,
> 
> Mark