RFC: Risc-V: Allow assembler to adjust relocs against symbols in mergeable sections

[Nick Clifton]

Hi Florian,

>>    Attached is a small patch which allows the Risc-V assembler to adjust
>>    fixups against symbols in mergeable sections.  Doing this results in
>>    relocations against the section's symbol instead of local symbols.

>> +  /* PR33723 and 33789: Allow fixups that reference symbols in
>> +     mergeable sections to be adjusted.  Disallow all others.  */
>> +  if (fixP->fx_addsy != NULL
>> +      && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0)
>> +    return true;

> Is this actually correct for RISC-V, though?  I thought that RISC-V
> relocations can significantly alter section layout, 

I thought that it was linker relaxation that was the cause for section
changes here, rather than relocations.  But I take your point that
Risc-V section layout is not really fixed until quite late in the linking
process.

> which means that the
> offset from the section start that the assembler sees may not match
> reality after relaxation.

I am not a Risc-V expert, which is why I am not planning on applying the
patch myself.  But ... I am pretty sure that neither relocations nor
relaxation are going to change the contents of mergeable sections.  (The
merge process itself will change the contents of course, but there is
already code present to update symbols, relocations and offsets when this
happens).

But maybe I am wrong and the Risc-V is a special case.  The patch is just
a suggestion, nothing more.

Cheers
   Nick