[PATCH v5] PowerPC: Support for SHA2 and SHA3 Compute Instructions (RFC02654)

[Jan Beulich]

On 05.12.2025 10:04, Abhay Kandpal wrote:
> @@ -2965,9 +3022,13 @@ const struct powerpc_operand powerpc_operands[] =
>  #define DMRAB DMR + 1
>    { 0x7, 13, NULL, NULL, PPC_OPERAND_DMR },
>  
> -  /* An optional BF field.  This is used for comparison instructions,
> +  /* The DMR field in a MMA instruction.  */
> +#define DMRATp DMRAB + 1
> +  { 0x3, 24, NULL, NULL, PPC_OPERAND_DMR },

The comment looks as if it was copied without editing. It doesn't properly
describe this kind of operand, does it?

> @@ -3544,7 +3611,10 @@ const struct powerpc_operand powerpc_operands[] =
>  #define UIM5 SH
>    { 0x1f, 11, NULL, NULL, 0 },
>  
> -#define RRWn SH + 1
> +#define HASHSR UIM5 + 1
> +  { 0x1f, 11, insert_sr, extract_sr, 0 },
> +
> +#define RRWn HASHSR + 1
>    { 0x1f, 11, insert_rrwn, extract_rrwn, 0 },

The pre-existing RRWn lack a comment, true, but I think the new HASHSR
better wouldn't follow that practice.

> @@ -4671,6 +4762,12 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
>  /* An X_MASK with two dense math register.  */
>  #define XDMRDMR_MASK (X_MASK | RA_MASK | (3 << 21) | (3 << 11))
>  
> +/* Masks for DMR-based hash forms.  */
> +#define XDMR2HASH_MASK (X_MASK | RA_MASK | (1 << 22) | (3 << 11))
> +#define XDMRSR_MASK    (X_MASK | RA_MASK | (7 << 21))
> +#define XDMR3HASH_MASK (X_MASK | RA_MASK | RB_MASK | (7 << 21))
> +
> +
>  /* The mask for an XX3 form instruction with the DM or SHW bits
>     specified.  */

Nit: Why two successive blank lines?

Jan