[PATCH v2] MIPS/opcodes: Fix floor/round exclusions for R5900

[David Guillen Fandos]

MIPS R5900 does not feature ceil/floor/round instructions, but only
ceil is correctly excluded at the moment. Correct the other two.

Signed-off-by: David Guillen Fandos <david@davidgf.net>
---
 gas/testsuite/gas/mips/r5900@c1.d | 8 ++++----
 opcodes/mips-opc.c                | 4 ++--
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/gas/testsuite/gas/mips/r5900@c1.d b/gas/testsuite/gas/mips/r5900@c1.d
index 12a6e4e5f15..1ec8314005e 100644
--- a/gas/testsuite/gas/mips/r5900@c1.d
+++ b/gas/testsuite/gas/mips/r5900@c1.d
@@ -18,10 +18,10 @@ Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 46000009 	trunc\.l\.s	\$f0,\$f0
 [0-9a-f]+ <[^>]*> 4600000a 	ceil\.l\.s	\$f0,\$f0
 [0-9a-f]+ <[^>]*> 4600000b 	floor\.l\.s	\$f0,\$f0
-[0-9a-f]+ <[^>]*> 4600000c 	round\.w\.s	\$f0,\$f0
+[0-9a-f]+ <[^>]*> 4600000c 	c1	0xc
 [0-9a-f]+ <[^>]*> 4600000d 	c1	0xd
 [0-9a-f]+ <[^>]*> 4600000e 	c1	0xe
-[0-9a-f]+ <[^>]*> 4600000f 	floor\.w\.s	\$f0,\$f0
+[0-9a-f]+ <[^>]*> 4600000f 	c1	0xf
 [0-9a-f]+ <[^>]*> 46000010 	c1	0x10
 [0-9a-f]+ <[^>]*> 46000011 	c1	0x11
 [0-9a-f]+ <[^>]*> 46000012 	c1	0x12
@@ -146,10 +146,10 @@ Disassembly of section \.text:
 [0-9a-f]+ <[^>]*> 46000009 	trunc\.l\.s	\$f0,\$f0
 [0-9a-f]+ <[^>]*> 4600000a 	ceil\.l\.s	\$f0,\$f0
 [0-9a-f]+ <[^>]*> 4600000b 	floor\.l\.s	\$f0,\$f0
-[0-9a-f]+ <[^>]*> 4600000c 	round\.w\.s	\$f0,\$f0
+[0-9a-f]+ <[^>]*> 4600000c 	c1	0xc
 [0-9a-f]+ <[^>]*> 4600000d 	c1	0xd
 [0-9a-f]+ <[^>]*> 4600000e 	c1	0xe
-[0-9a-f]+ <[^>]*> 4600000f 	floor\.w\.s	\$f0,\$f0
+[0-9a-f]+ <[^>]*> 4600000f 	c1	0xf
 [0-9a-f]+ <[^>]*> 46000010 	c1	0x10
 [0-9a-f]+ <[^>]*> 46000011 	c1	0x11
 [0-9a-f]+ <[^>]*> 46000012 	c1	0x12
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 234e8bb3409..1d7d72ae0a7 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -1206,7 +1206,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"floor.l.d",		"D,S",		0x4620000b, 0xffff003f, WR_1|RD_2|FP_D,		0,		I3_33,		0,	0 },
 {"floor.l.s",		"D,S",		0x4600000b, 0xffff003f, WR_1|RD_2|FP_S|FP_D,	0,		I3_33,		0,	0 },
 {"floor.w.d",		"D,S",		0x4620000f, 0xffff003f, WR_1|RD_2|FP_S|FP_D,	0,		I2,		0,	SF },
-{"floor.w.s",		"D,S",		0x4600000f, 0xffff003f, WR_1|RD_2|FP_S,		0,		I2,		0,	0 },
+{"floor.w.s",		"D,S",		0x4600000f, 0xffff003f,	WR_1|RD_2|FP_S,		0,		I2,		0,	EE },
 {"hibernate",		"",		0x42000023, 0xffffffff,	0, 			0,		V1,		0,	0 },
 {"hypcall",		"",		0x42000028, 0xffffffff, TRAP,			0,		0,		IVIRT,	0 },
 {"hypcall",		"+J",		0x42000028, 0xffe007ff, TRAP,			0,		0,		IVIRT,	0 },
@@ -1823,7 +1823,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"round.l.d",		"D,S",		0x46200008, 0xffff003f, WR_1|RD_2|FP_D,		0,		I3_33,		0,	0 },
 {"round.l.s",		"D,S",		0x46000008, 0xffff003f, WR_1|RD_2|FP_S|FP_D,	0,		I3_33,		0,	0 },
 {"round.w.d",		"D,S",		0x4620000c, 0xffff003f, WR_1|RD_2|FP_S|FP_D,	0,		I2,		0,	SF },
-{"round.w.s",		"D,S",		0x4600000c, 0xffff003f, WR_1|RD_2|FP_S,		0,		I2,		0,	0 },
+{"round.w.s",		"D,S",		0x4600000c, 0xffff003f,	WR_1|RD_2|FP_S,		0,		I2,		0,	EE },
 {"rsqrt.d",		"D,S",		0x46200016, 0xffff003f, WR_1|RD_2|FP_D,		0,		I4_33,		0,	0 },
 {"rsqrt.ps",		"D,S",		0x46c00016, 0xffff003f, WR_1|RD_2|FP_D,		0,		SB1,		0,	0 },
 {"rsqrt.s",		"D,S",		0x46000016, 0xffff003f, WR_1|RD_2|FP_S,		0,		I4_33,		0,	0 },
-- 
2.51.1