[PATCH] aarch64: Add support for FEAT_MTETC

[Alice Carlotti]

On Fri, Jan 16, 2026 at 04:40:30PM +0000, richard.ball@arm.com wrote:
> From: Richard Ball <Richard.Ball@arm.com>
> 
> This patch adds two new DC operations:
> 
>    *gbva
>    *zgbva
> ---
>  gas/config/tc-aarch64.c                   |  1 +
>  gas/doc/c-aarch64.texi                    |  2 ++
>  gas/testsuite/gas/aarch64/mtetc-invalid.d |  4 ++++
>  gas/testsuite/gas/aarch64/mtetc-invalid.l |  5 +++++
>  gas/testsuite/gas/aarch64/mtetc.d         | 12 ++++++++++++
>  gas/testsuite/gas/aarch64/mtetc.s         |  5 +++++
>  include/opcode/aarch64.h                  |  2 ++
>  opcodes/aarch64-opc.c                     |  2 ++
>  8 files changed, 33 insertions(+)
>  create mode 100644 gas/testsuite/gas/aarch64/mtetc-invalid.d
>  create mode 100644 gas/testsuite/gas/aarch64/mtetc-invalid.l
>  create mode 100644 gas/testsuite/gas/aarch64/mtetc.d
>  create mode 100644 gas/testsuite/gas/aarch64/mtetc.s
> 
> diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
> index 61bd81ca0b6..38c3cfda7f2 100644
> --- a/gas/config/tc-aarch64.c
> +++ b/gas/config/tc-aarch64.c
> @@ -11011,6 +11011,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
>    {"f16mm",		AARCH64_FEATURE (F16MM), AARCH64_FEATURES (2, SIMD, F16)},
>    {"sve-b16mm",		AARCH64_FEATURE (SVE_B16MM), AARCH64_FEATURE (SVE)},
>    {"mpamv2",		AARCH64_FEATURE (MPAMv2), AARCH64_NO_FEATURES},
> +  {"mtetc",		AARCH64_FEATURE (MTETC), AARCH64_FEATURE (MEMTAG)},
>    {NULL,		AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
>  };
>  
> diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
> index ddb4c610922..a56934653d6 100644
> --- a/gas/doc/c-aarch64.texi
> +++ b/gas/doc/c-aarch64.texi
> @@ -259,6 +259,8 @@ automatically cause those extensions to be disabled.
>   @tab Enable the Lookup Table (LUT) extension.
>  @item @code{memtag} @tab
>   @tab Enable Armv8.5-A Memory Tagging Extensions.
> +@item @code{mtetc} @tab @code{memtag}
> + @tab Enable Data cache tag block operations.
>  @item @code{mops} @tab
>   @tab Enable Armv8.8-A memcpy and memset acceleration instructions
>  @item @code{mpamv2} @tab
> diff --git a/gas/testsuite/gas/aarch64/mtetc-invalid.d b/gas/testsuite/gas/aarch64/mtetc-invalid.d
> new file mode 100644
> index 00000000000..b40d9361bd8
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/mtetc-invalid.d
> @@ -0,0 +1,4 @@
> +#name: FEAT_MTETC dc instructions without +mtetc.
> +#as: -march=armv8-a
> +#source: mtetc.s
> +#error_output: mtetc-invalid.l
> diff --git a/gas/testsuite/gas/aarch64/mtetc-invalid.l b/gas/testsuite/gas/aarch64/mtetc-invalid.l
> new file mode 100644
> index 00000000000..51db697bcd3
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/mtetc-invalid.l
> @@ -0,0 +1,5 @@
> +.*: Assembler messages:
> +.*: Error: selected processor does not support system register name 'gbva'
> +.*: Error: selected processor does not support system register name 'gbva'
> +.*: Error: selected processor does not support system register name 'zgbva'
> +.*: Error: selected processor does not support system register name 'zgbva'
> diff --git a/gas/testsuite/gas/aarch64/mtetc.d b/gas/testsuite/gas/aarch64/mtetc.d
> new file mode 100644
> index 00000000000..54b5cddde8b
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/mtetc.d
> @@ -0,0 +1,12 @@
> +#as: -march=armv8-a+mtetc
> +#objdump: -dr
> +
> +[^:]+:     file format .*
> +
> +Disassembly of section \.text:
> +
> +[^:]+:
> +.*:	d50b74e0 	dc	gbva, x0
> +.*:	d50b74ff 	dc	gbva, xzr
> +.*:	d50b74a0 	dc	zgbva, x0
> +.*:	d50b74bf 	dc	zgbva, xzr
> diff --git a/gas/testsuite/gas/aarch64/mtetc.s b/gas/testsuite/gas/aarch64/mtetc.s
> new file mode 100644
> index 00000000000..ec6e1cde35d
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/mtetc.s
> @@ -0,0 +1,5 @@
> +	.irp	dc_op gbva,zgbva
> +	.irp    rt, x0, xzr
> +	dc	\dc_op, \rt
> +	.endr
> +	.endr

I think it would be easier and clearer to just write out the four instructions
separately, rather than using five lines of nested assembler directives.

Ok with that change (and also ok as is if you'd prefer to keep the
directives).

Alice


> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
> index 4a38953ea57..42ff6eff26d 100644
> --- a/include/opcode/aarch64.h
> +++ b/include/opcode/aarch64.h
> @@ -285,6 +285,8 @@ enum aarch64_feature_bit {
>    AARCH64_FEATURE_TEV,
>    /* MPAMv2.  */
>    AARCH64_FEATURE_MPAMv2,
> +  /* MTETC.  */
> +  AARCH64_FEATURE_MTETC,
>  
>    /* Virtual features.  These are used to gate instructions that are enabled
>       by either of two (or more) sets of command line flags.  */
> diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
> index e3fbb4f5257..67b6e67dde8 100644
> --- a/opcodes/aarch64-opc.c
> +++ b/opcodes/aarch64-opc.c
> @@ -5312,6 +5312,8 @@ const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
>      { "zva",	    CPENS (3, C7, C4, 1),  F_HASXT, AARCH64_NO_FEATURES },
>      { "gva",	    CPENS (3, C7, C4, 3),  F_HASXT, AARCH64_FEATURE (MEMTAG) },
>      { "gzva",	    CPENS (3, C7, C4, 4),  F_HASXT, AARCH64_FEATURE (MEMTAG) },
> +    { "zgbva",	    CPENS (3, C7, C4, 5),  F_HASXT, AARCH64_FEATURE (MTETC) },
> +    { "gbva",	    CPENS (3, C7, C4, 7),  F_HASXT, AARCH64_FEATURE (MTETC) },
>      { "ivac",       CPENS (0, C7, C6, 1),  F_HASXT, AARCH64_NO_FEATURES },
>      { "igvac",      CPENS (0, C7, C6, 3),  F_HASXT, AARCH64_FEATURE (MEMTAG) },
>      { "igsw",       CPENS (0, C7, C6, 4),  F_HASXT, AARCH64_FEATURE (MEMTAG) },
> -- 
> 2.34.1
>