[PATCH] aarch64: Add FEAT_NV3, FEAT_SRMASK2 system registers

[Ezra.Sitorus@arm.com]

From: Ezra Sitorus <ezra.sitorus@arm.com>

Some of the registers require both features - I've put them in the
SRMASK2 test files. Does that look ok?

Regression tested on aarch64-none-linux-gnu.

Ezra
---
 gas/testsuite/gas/aarch64/sysreg/nv3.d     | 13 +++++++++++++
 gas/testsuite/gas/aarch64/sysreg/nv3.s     |  4 ++++
 gas/testsuite/gas/aarch64/sysreg/srmask2.d | 17 +++++++++++++++++
 gas/testsuite/gas/aarch64/sysreg/srmask2.s |  6 ++++++
 opcodes/aarch64-sys-regs.def               |  6 ++++++
 5 files changed, 46 insertions(+)
 create mode 100644 gas/testsuite/gas/aarch64/sysreg/nv3.d
 create mode 100644 gas/testsuite/gas/aarch64/sysreg/nv3.s
 create mode 100644 gas/testsuite/gas/aarch64/sysreg/srmask2.d
 create mode 100644 gas/testsuite/gas/aarch64/sysreg/srmask2.s

diff --git a/gas/testsuite/gas/aarch64/sysreg/nv3.d b/gas/testsuite/gas/aarch64/sysreg/nv3.d
new file mode 100644
index 00000000000..3a3d526eb67
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg/nv3.d
@@ -0,0 +1,13 @@
+#name: NV3 System Register
+#as: -march=armv9.3-a -I$srcdir/$subdir
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+[^:]*:	d51c1500 	msr	nvhcr_el2, x0
+[^:]*:	d53c1500 	mrs	x0, nvhcr_el2
+[^:]*:	d51c1580 	msr	nvhcrmask_el2, x0
+[^:]*:	d53c1580 	mrs	x0, nvhcrmask_el2
diff --git a/gas/testsuite/gas/aarch64/sysreg/nv3.s b/gas/testsuite/gas/aarch64/sysreg/nv3.s
new file mode 100644
index 00000000000..7005b268569
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg/nv3.s
@@ -0,0 +1,4 @@
+.include "sysreg-test-utils.inc"
+
+	rw_sys_reg nvhcr_el2
+	rw_sys_reg nvhcrmask_el2
diff --git a/gas/testsuite/gas/aarch64/sysreg/srmask2.d b/gas/testsuite/gas/aarch64/sysreg/srmask2.d
new file mode 100644
index 00000000000..2170b729756
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg/srmask2.d
@@ -0,0 +1,17 @@
+#name: SRMASK2 System Register
+#as: -march=armv9.6-a -I$srcdir/$subdir
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*:	d51c15c0 	msr	hcrmask_el2, x0
+.*:	d53c15c0 	mrs	x0, hcrmask_el2
+.*:	d51c15e0 	msr	hcrxmask_el2, x0
+.*:	d53c15e0 	mrs	x0, hcrxmask_el2
+.*:	d51c1580 	msr	nvhcrmask_el2, x0
+.*:	d53c1580 	mrs	x0, nvhcrmask_el2
+.*:	d51c15a0 	msr	nvhcrxmask_el2, x0
+.*:	d53c15a0 	mrs	x0, nvhcrxmask_el2
diff --git a/gas/testsuite/gas/aarch64/sysreg/srmask2.s b/gas/testsuite/gas/aarch64/sysreg/srmask2.s
new file mode 100644
index 00000000000..e29f07276ee
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg/srmask2.s
@@ -0,0 +1,6 @@
+.include "sysreg-test-utils.inc"
+
+	rw_sys_reg hcrmask_el2
+	rw_sys_reg hcrxmask_el2
+	rw_sys_reg nvhcrmask_el2
+	rw_sys_reg nvhcrxmask_el2
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index 17c1c9d0c01..42c34d1b15b 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -444,6 +444,8 @@
   SYSREG ("hafgrtr_el2",	CPENC (3,4,3,1,6),	0,		AARCH64_FEATURE (V8_5A)) /* AMUv1 && FGT */
   SYSREG ("hcr_el2",		CPENC (3,4,1,1,0),	0,		AARCH64_NO_FEATURES)
   SYSREG ("hcrx_el2",		CPENC (3,4,1,2,2),	0,		AARCH64_FEATURE (V8_6A)) /* HCX */
+  SYSREG ("hcrmask_el2",	CPENC (3,4,1,5,6),	0,		AARCH64_FEATURE (V9_6A)) /* SRMASK2 */
+  SYSREG ("hcrxmask_el2",	CPENC (3,4,1,5,7),	0,		AARCH64_FEATURE (V9_6A)) /* SRMASK2 */
   SYSREG ("hdbssbr_el2",	CPENC (3,4,2,3,2),	0,		AARCH64_FEATURE (V9_4A)) /* HDBSS */
   SYSREG ("hdbssprod_el2",	CPENC (3,4,2,3,3),	0,		AARCH64_FEATURE (V9_4A)) /* HDBSS */
   SYSREG ("hdfgrtr_el2",	CPENC (3,4,3,1,4),	0,		AARCH64_FEATURE (V8_5A)) /* FGT */
@@ -696,6 +698,10 @@
   SYSREG ("mvfr0_el1",		CPENC (3,0,0,3,0),	F_REG_READ,	AARCH64_NO_FEATURES)
   SYSREG ("mvfr1_el1",		CPENC (3,0,0,3,1),	F_REG_READ,	AARCH64_NO_FEATURES)
   SYSREG ("mvfr2_el1",		CPENC (3,0,0,3,2),	F_REG_READ,	AARCH64_NO_FEATURES)
+  SYSREG ("nvhcr_el2",		CPENC (3,4,1,5,0),	0,		AARCH64_FEATURE (V9_3A)) /* NV3 */
+  SYSREG ("nvhcrx_el2",		CPENC (3,4,1,5,1),	0,		AARCH64_FEATURE (V9_6A)) /* NV3 && SRMASK2 */
+  SYSREG ("nvhcrmask_el2",	CPENC (3,4,1,5,4),	0,		AARCH64_FEATURE (V9_6A)) /* NV3 && SRMASK2 */
+  SYSREG ("nvhcrxmask_el2",	CPENC (3,4,1,5,5),	0,		AARCH64_FEATURE (V9_6A)) /* NV3 && SRMASK2 */
   SYSREG ("nzcv",		CPENC (3,3,4,2,0),	0,		AARCH64_NO_FEATURES)
   SYSREG ("osdlr_el1",		CPENC (2,0,1,3,4),	0,		AARCH64_NO_FEATURES)
   SYSREG ("osdtrrx_el1",	CPENC (2,0,0,0,2),	0,		AARCH64_NO_FEATURES)
-- 
2.43.0