[PATCH v8] PowerPC: Support for SHA2 and SHA3 Compute Instructions (RFC02654)
Abhay Kandpal
abhay@linux.ibm.com
Wed Feb 18 06:47:43 GMT 2026
opcodes/
* ppc-opc.c: (insert_sr, extract_sr, insert_bl, extract_bl):
New functions.
(DMRATp, PADE, HASHT, HASHSR, PADID, PADBL, XSHAHASH, XSHA3HASH,
XSHA2HASH, XX2PAD, XX2PADE, XSHAHASH_MASK, XSHA2HASH_MASK,
XSHA3SR_MASK, XSHA3HASH_MASK, XX2PAD_MASK, XX2PADE_MASK): New defines.
(OBF, PMSK8, L, RRWn, UIM): Update for new macros.
(powerpc_opcodes): Add dmsha256hash, dmsha512hash, dmsha2hash,
dmsha3dw, dmcryshash, dmsha3hash, dmxxsha3512pad, dmxxsha3384pad,
dmxxsha3256pad, dmxxsha3224pad, dmxxshake256pad, dmxxshake128pad,
dmxxsha384512pad, dmxxsha224256pad, dmxxshapad.
gas/
* testsuite/gas/ppc/future.s: New test.
* testsuite/gas/ppc/future.d: Likewise.
---
This patch is reg tested.
Changes from v1->v2:
<Added more test cases for dmsha2hash, dmsha3hash, dmxxshapad>
Changes from v2->v3:
<Added Extended mnemonics>
<Added related macros & testcases>
Changes from v3->v4:
<Updated the patch on latest trunk>
<Modifed L macro>
<Move the dmxxshapad related instructions to correct place>
<Rename the Macros>
Changed from v4->v5
<Added New functions>
<Modified existing macros(RRWn, S)>
Changed from v5->v6
<Format correction of commit log>
<Remove return from insert_sr & insert_id>
<Indentation correction of insert_id/extract_id>
<Format correction of instructions>
<Reframing the comments>
<Cosmetic corrections>
Changed from v6->v7
<Reframing the comments>
<Renaming of Macros>
<Corrected instruction opcode name>
<Added more test cases>
<Added insert_bl()/extract_bl()>
<Deleted insert_id()/extract_id()>
Changed from v7->v8
<Renaming of Macros>
gas/testsuite/gas/ppc/future.d | 21 ++++++
gas/testsuite/gas/ppc/future.s | 21 ++++++
opcodes/ppc-opc.c | 127 +++++++++++++++++++++++++++++++--
3 files changed, 164 insertions(+), 5 deletions(-)
diff --git a/gas/testsuite/gas/ppc/future.d b/gas/testsuite/gas/ppc/future.d
index 4ad0a34e6fb..428d489c307 100644
--- a/gas/testsuite/gas/ppc/future.d
+++ b/gas/testsuite/gas/ppc/future.d
@@ -158,4 +158,25 @@ Disassembly of section \.text:
.*: (1f 76 8d ed|ed 8d 76 1f) xsrebase3t3uqm vs44,vs45,vs46
.*: (00 00 00 05|05 00 00 00) xxssumudmcext vs35,vs9,vs11,vs13,1
.*: (71 5b 69 88|88 69 5b 71)
+.*: (62 c1 8e 7e|7e 8e c1 62) dmsha256hash dm5,dm6
+.*: (62 e1 ae 7e|7e ae e1 62) dmsha512hash dm5,dm7
+.*: (62 61 0e 7d|7d 0e 61 62) dmsha256hash dm2,dm3
+.*: (62 c1 2e 7e|7e 2e c1 62) dmsha512hash dm4,dm6
+.*: (62 01 0f 7d|7d 0f 01 62) dmsha3dw dm1
+.*: (62 61 0f 7f|7f 0f 61 62) dmcryshash dm3
+.*: (62 01 0f 7f|7f 0f 01 62) dmsha3dw dm3
+.*: (62 41 0f 7e|7e 0f 41 62) dmsha3hash dm2,8
+.*: (62 61 0f 7e|7e 0f 61 62) dmcryshash dm2
+.*: (94 26 84 f1|f1 84 26 94) dmxxsha3512pad dm3,vs4,1
+.*: (94 16 85 f1|f1 85 16 94) dmxxsha3384pad dm3,vs2,1
+.*: (94 1e 86 f0|f0 86 1e 94) dmxxsha3256pad dm1,vs3,1
+.*: (96 2e 03 f1|f1 03 2e 96) dmxxsha3224pad dm2,vs37,0
+.*: (96 36 8a f1|f1 8a 36 96) dmxxshake256pad dm3,vs38,0
+.*: (96 3e 0b f2|f2 0b 3e 96) dmxxshake128pad dm4,vs39,0
+.*: (94 46 90 f2|f2 90 46 94) dmxxsha384512pad dm5,vs8
+.*: (96 4e 18 f3|f3 18 4e 96) dmxxsha224256pad dm6,vs41
+.*: (94 1e 80 f3|f3 80 1e 94) dmxxsha3512pad dm7,vs3,0
+.*: (96 46 1e f3|f3 1e 46 96) dmxxshapad dm6,vs40,3,1,2
+.*: (96 4e 8e f3|f3 8e 4e 96) dmxxshake256pad dm7,vs41,1
+.*: (96 56 0b f3|f3 56 0b 96) dmxxshake128pad dm6,vs42,0
#pass
diff --git a/gas/testsuite/gas/ppc/future.s b/gas/testsuite/gas/ppc/future.s
index aa20245c947..305a0678e6d 100644
--- a/gas/testsuite/gas/ppc/future.s
+++ b/gas/testsuite/gas/ppc/future.s
@@ -131,4 +131,25 @@ _start:
xsrebase3t2uqm 41, 42, 43
xsrebase3t3uqm 44, 45, 46
xxssumudmcext 35, 9, 11, 13, 1
+ dmsha256hash 5, 6
+ dmsha512hash 5, 7
+ dmsha2hash 2, 3, 0
+ dmsha2hash 4, 6, 1
+ dmsha3dw 1
+ dmcryshash 3
+ dmsha3hash 3, 0
+ dmsha3hash 2, 8
+ dmsha3hash 2, 12
+ dmxxsha3512pad 3, 4, 1
+ dmxxsha3384pad 3, 2, 1
+ dmxxsha3256pad 1, 3, 1
+ dmxxsha3224pad 2, 37, 0
+ dmxxshake256pad 3, 38, 0
+ dmxxshake128pad 4, 39, 0
+ dmxxsha384512pad 5, 8
+ dmxxsha224256pad 6, 41
+ dmxxshapad 7, 3, 0, 0, 0
+ dmxxshapad 6, 40, 3, 1, 2
+ dmxxshapad 7, 41, 1, 1, 2
+ dmxxshapad 6, 42, 1, 0, 3
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index a0bbd9e5e29..af96fbba3fc 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -1815,6 +1815,58 @@ extract_oimm (uint64_t insn,
return ((insn >> 4) & 0x1f) + 1;
}
+/* The SR field in the SHA3 Hash instruction.
+ Values 0–23 are valid; SR>23 are reserved. */
+
+static uint64_t
+insert_sr (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+{
+ if (value < 0 || value > 23)
+ *errmsg = _("invalid SR value (must be 0–23)");
+ return insn | ((value & 0x1f) << 11);
+}
+
+static int64_t
+extract_sr (uint64_t insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid)
+{
+ int64_t value = (insn >> 11) & 0x1f;
+ if (value > 23)
+ *invalid = 1;
+ return value;
+}
+
+/* The 2-bit BL field in the SHA Pad instruction.
+ Invalid combinations: ID=1 with BL=0 or BL=1. */
+
+static uint64_t
+insert_bl (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+{
+ int id = (insn >> 19) & 0x3;
+ if (id == 1 && (value == 0 || value == 1))
+ *errmsg = _("invalid combination: ID=1 with BL=0 or BL=1");
+ return insn | ((value & 0x3) << 16);
+}
+
+static int64_t
+extract_bl (uint64_t insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid)
+{
+ int64_t id = (insn >> 19) & 0x3;
+ int64_t bl = (insn >> 16) & 0x3;
+ if (id == 1 && (bl == 0 || bl == 1))
+ *invalid = 1;
+ return bl;
+}
+
/* The n operand of rotrwi, sets SH = 32 - n. */
static uint64_t
@@ -2990,9 +3042,14 @@ const struct powerpc_operand powerpc_operands[] =
#define DMRAB DMR + 1
{ 0x7, 13, NULL, NULL, PPC_OPERAND_DMR },
+ /* The field in a SHA3 instruction representing the target
+ DMR pair registers. */
+#define DMRATp DMRAB + 1
+ { 0x3, 24, NULL, NULL, PPC_OPERAND_DMR },
+
/* An optional BF field. This is used for comparison instructions,
in which an omitted BF field is taken as zero. */
-#define OBF DMRAB + 1
+#define OBF DMRATp + 1
{ 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
/* The BFA field in an X or XL form instruction. */
@@ -3170,8 +3227,12 @@ const struct powerpc_operand powerpc_operands[] =
#define IX UIM8 + 1
{ 0x1, 17, NULL, NULL, 0 },
+ /* The 1-bit E field in SHA Pad instruction. */
+#define PADE IX + 1
+ { 0x1, 18, NULL, NULL, 0 },
+
/* The PMSK field in GER rank 8 prefix instructions. */
-#define PMSK8 IX + 1
+#define PMSK8 PADE + 1
{ 0xff, 40, NULL, NULL, 0 },
/* The PMSK field in GER rank 4 prefix instructions. */
@@ -3289,8 +3350,10 @@ const struct powerpc_operand powerpc_operands[] =
#define IMM20 FXM4 + 1
{ 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED},
+ /* The 1-bit T field denoting the hash mode in SHA2 instruction. */
+#define HASHT IMM20 + 1
/* The L field in a D or X form instruction. */
-#define L IMM20 + 1
+#define L HASHT
{ 0x1, 21, NULL, NULL, 0 },
/* The optional L field in tlbie and tlbiel instructions. */
@@ -3569,7 +3632,12 @@ const struct powerpc_operand powerpc_operands[] =
#define UIM5 SH
{ 0x1f, 11, NULL, NULL, 0 },
-#define RRWn SH + 1
+ /* The SR field indicating number of hash computation
+ rounds in SHA3 Hash instruction. */
+#define HASHSR SH + 1
+ { 0x1f, 11, insert_sr, extract_sr, 0 },
+
+#define RRWn HASHSR + 1
{ 0x1f, 11, insert_rrwn, extract_rrwn, 0 },
#define SLWn RRWn + 1
@@ -3864,6 +3932,8 @@ const struct powerpc_operand powerpc_operands[] =
{ 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL },
#define SP PRS + 1
+ /* The 2-bit ID field in SHA Pad instruction. */
+#define PADID SP
#define mi0 SP
{ 0x3, 19, NULL, NULL, 0 },
@@ -4010,8 +4080,12 @@ const struct powerpc_operand powerpc_operands[] =
#define AESM DMEX + 1
{ 0x3, PPC_OPSHIFT_INV, insert_m2, extract_m2, 0 },
+ /* The 2-bit BL field in SHA Pad instruction. */
+#define PADBL AESM + 1
+ { 0x3, 16, insert_bl, extract_bl, 0 },
+
/* The UIM field in an XX2 form instruction. */
-#define UIM AESM + 1
+#define UIM PADBL + 1
/* The 2-bit UIMM field in a VX form instruction. */
#define UIMM2 UIM
/* The 2-bit L field in a darn instruction. */
@@ -4601,6 +4675,15 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
/* A X form instruction for Quad-Precision FP Instructions. */
#define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16))
+/* An X form instruction for SHA hash. */
+#define XSHAHASH XVA
+
+/* An X form instruction for SHA3 hash. */
+#define XSHA3HASH(op, xop, vaop, sr) (XSHAHASH(op, xop, vaop) | ((sr) << 11))
+
+/* An X form instruction for SHA2 hash. */
+#define XSHA2HASH(op, xop, vaop, t) (XSHAHASH(op, xop, vaop) | ((t) << 21))
+
/* An EX form instruction. */
#define EX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7ff))
@@ -4610,6 +4693,15 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
/* An XX2 form instruction. */
#define XX2(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1ff) << 2))
+/* An XX2 form SHA pad instruction. */
+#define XX2PAD(op, xop, id, bl) \
+ (XX2(op, xop) \
+ | (((uint64_t)(id) & 0x3) << 19) \
+ | (((uint64_t)(bl) & 0x3) << 16))
+
+/* An XX2 form SHA pad instruction with E bit as 0. */
+#define XX2PADE(op, xop, id, bl) (XX2PAD(op, xop, id, bl) | (0 << 18))
+
/* A XX2 form instruction with the VA bits specified. */
#define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16))
@@ -4723,6 +4815,12 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
/* An X_MASK with two dense math register. */
#define XDMRDMR_MASK (X_MASK | RA_MASK | (3 << 21) | (3 << 11))
+/* Masks for X form SHA instructions. */
+#define XSHAHASH_MASK XVA_MASK
+#define XSHA2HASH_MASK (XSHAHASH_MASK | (1 << 22) | (3 << 11))
+#define XSHA3SR_MASK (XSHAHASH_MASK | (7 << 21))
+#define XSHA3HASH_MASK (XSHA3SR_MASK | RB_MASK)
+
/* The mask for an XX3 form instruction with the S1, S2, DM or SHW bits
specified. */
#define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
@@ -4736,6 +4834,10 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
#define XX2DMR_MASK (XX2ACC_MASK | (0xf << 17))
#define XX3GERX_MASK (XX3ACC_MASK | (1 << 16))
+/* Masks for XX2 form SHA pad instructions. */
+#define XX2PAD_MASK (XX2ACC_MASK | (3 << 19) | (3 << 16))
+#define XX2PADE_MASK (XX2PAD_MASK | (1 << 18))
+
/* The masks for XX2 AES instructions with m0, m1 bits. */
#define XX2AES_MASK (XX2 (0x3f, 0x1ff) | (0xf << 17) | 1)
#define XX2AESM_MASK (XX2AES_MASK | (1 << 16) | (1 << 11))
@@ -7569,6 +7671,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"xxsetaccz", XVA(31,177,3), XACC_MASK, POWER10, 0, {ACC}},
{"dmmr", XVA(31,177,6), XDMRDMR_MASK,FUTURE, 0, {DMR, DMRAB}},
{"dmxor", XVA(31,177,7), XDMRDMR_MASK,FUTURE, 0, {DMR, DMRAB}},
+{"dmsha256hash", XSHA2HASH(31,177,14,0), XDMRDMR_MASK, FUTURE, EXT, {DMR, DMRAB}},
+{"dmsha512hash", XSHA2HASH(31,177,14,1), XDMRDMR_MASK, FUTURE, EXT, {DMR, DMRAB}},
+{"dmsha2hash", XSHAHASH(31,177,14), XSHA2HASH_MASK, FUTURE, 0, {DMR, DMRAB, HASHT}},
+{"dmsha3dw", XSHA3HASH(31,177,15,0), XSHA3HASH_MASK, FUTURE, EXT, {DMRATp}},
+{"dmcryshash", XSHA3HASH(31,177,15,12), XSHA3HASH_MASK, FUTURE, EXT, {DMRATp}},
+{"dmsha3hash", XSHAHASH(31,177,15), XSHA3SR_MASK, FUTURE, 0, {DMRATp, HASHSR}},
{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}},
@@ -9671,6 +9779,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"xxaes256genlkp",XX2M(60,420,2),XX2AESM_MASK, PPCVSXF, PPCVLE|EXT, {XTP, XB5p}},
{"xxaesgenlkp", XX2M(60,420,0),XX2AES_MASK, PPCVSXF, PPCVLE, {XTP, XB5p, AESM}},
+{"dmxxsha3512pad", XX2PAD(60,421,0,0), XX2PAD_MASK, FUTURE, PPCVLE|EXT, {DMR, XB6, PADE}},
+{"dmxxsha3384pad", XX2PAD(60,421,0,1), XX2PAD_MASK, FUTURE, PPCVLE|EXT, {DMR, XB6, PADE}},
+{"dmxxsha3256pad", XX2PAD(60,421,0,2), XX2PAD_MASK, FUTURE, PPCVLE|EXT, {DMR, XB6, PADE}},
+{"dmxxsha3224pad", XX2PAD(60,421,0,3), XX2PAD_MASK, FUTURE, PPCVLE|EXT, {DMR, XB6, PADE}},
+{"dmxxshake256pad", XX2PAD(60,421,1,2), XX2PAD_MASK, FUTURE, PPCVLE|EXT, {DMR, XB6, PADE}},
+{"dmxxshake128pad", XX2PAD(60,421,1,3), XX2PAD_MASK, FUTURE, PPCVLE|EXT, {DMR, XB6, PADE}},
+{"dmxxsha384512pad", XX2PADE(60,421,2,0), XX2PADE_MASK, FUTURE, PPCVLE|EXT, {DMR, XB6}},
+{"dmxxsha224256pad", XX2PADE(60,421,3,0), XX2PADE_MASK, FUTURE, PPCVLE|EXT, {DMR, XB6}},
+{"dmxxshapad", XX2(60,421), XX2ACC_MASK, FUTURE, PPCVLE, {DMR, XB6, PADID, PADE, PADBL}},
{"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
{"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
{"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
--
2.47.3
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