[PATCH] csky: Fix BMASKI disassembly for immediate 32 on C-SKY v1

[Michal Sobon]

On Thu, Feb 5, 2026 at 12:23 PM Jan Beulich <jbeulich@suse.com> wrote:
>
> Short of them responding, I will: Unlike for your earlier M*Core change,
> the situation doesn't look as clear here. This is what I found in what I
> hope is the applicable doc:
>
> "When OIMM5 is 0 or 32, all bits of RX are set as 1."
>
> and later, after discussing immediates 1...16:
>
> "The range of immediate operand is 0 and 17-32."
>
> Hence 0 looks to be a spec-conforming representation in disassembly,
> albeit perhaps not as human friendly as 32.
>
> Comparing with the v2 version of the insn also doesn't look quite fair:
> That appears to take a 5-bit immediate in the range 16...31, with 1 then
> added in.
>
> Jan

While I agree that 0 is the literal value in the immediate field, I
found a note in my documentation regarding the assembler behavior
(translated from Chinese):

"Set the lower IMM5 bit of register RX to 1, and clear the remaining
higher bits to 0. Register RX can be set from bit 1 to bit 32. When the
IMM5 field is 00000, the assembler will interpret it as 32 bits."

My main motivation for the change is avoiding confusion. To someone not
fully familiar with the ISA details, BMASKI 0 could give the impression
that the instruction does not set any bits (or clears the register),
whereas the actual behavior is setting all 32 bits.

Since the assembler interprets an input of 32 by encoding it as 0, I
felt it was safer for the disassembler to close that loop and display
32.

However, I realize this is largely a matter of preference. If you think
disassembling as 0 is better, I am totally fine with that too.

Michal