[PATCH 3 09/16] MIPS: Add CRYPTO ASE support

Jovan Dmitrovic jovan.dmitrovic@htecgroup.com
Thu Feb 5 16:24:04 GMT 2026 

From: Scott Egerton <scott.egerton@imgtec.com>

Add support for the CRYPTO Application Specific Extension for Release 6 of
the MIPS Architecture.

ChangeLog:

bfd/
	* elfxx-mips.c (print_mips_ases): Add CRYPTO.

binutils/
	* readelf.c (print_mips_ases): Add CRYPTO.

gas/
	* config/tc-mips.c (options): Add OPTION_CRYPTO and
	OPTION_NO_CRYPTO.
	(md_longopts): Likewise.
	(md_show_usage): Add help for -mcrypto and -mno-crypto.
	(mips_ases): Define availability for CRYPTO.
	(mips_convert_ase_flags): Map ASE_CRYPTO to AFL_ASE_CRYPTO.
	* doc/as.texinfo: Document -mcrypto, -mno-crypto.
	* doc/c-mips.texi: Document -mcrypto, -mno-crypto, .set crypto and
	.set no-crypto.
	* testsuite/gas/mips/ase-errors-1.l: Add error checks for CRYPTO ASE.
	* testsuite/gas/mips/ase-errors-1.s: Likewise.
	* testsuite/gas/mips/ase-errors-2.l: Likewise.
	* testsuite/gas/mips/ase-errors-2.s: Likewise.
	* testsuite/gas/mips/crypto.d: New test.
	* testsuite/gas/mips/crypto.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

include/
	* elf/mips.h (AFL_ASE_CRYPTO): New macro.
	(AFL_ASE_MASK): Update to include AFL_ASE_CRYPTO.
	* opcode/mips.h (ASE_CRYPTO): New macro.

opcodes/
	* mips-dis.c (mips_arch_choices): Add ASE_CRYPTO to mips32r6 and
	mips64r6.
	* mips-opc.c (CRYPTO): New macro.
	(mips_builtin_opcodes): Define new cryptography instructions.
---
 bfd/elfxx-mips.c                      |  2 ++
 binutils/readelf.c                    |  2 ++
 gas/config/tc-mips.c                  | 17 ++++++++++
 gas/doc/as.texi                       |  7 +++++
 gas/doc/c-mips.texi                   | 16 +++++++++-
 gas/testsuite/gas/mips/ase-errors-1.l |  5 +++
 gas/testsuite/gas/mips/ase-errors-1.s |  9 ++++++
 gas/testsuite/gas/mips/ase-errors-2.l |  4 +++
 gas/testsuite/gas/mips/ase-errors-2.s |  9 ++++++
 gas/testsuite/gas/mips/crypto.d       | 45 +++++++++++++++++++++++++++
 gas/testsuite/gas/mips/crypto.s       | 38 ++++++++++++++++++++++
 gas/testsuite/gas/mips/mips.exp       |  4 ++-
 include/elf/mips.h                    |  4 +--
 include/opcode/mips.h                 |  4 ++-
 opcodes/mips-dis.c                    |  4 +--
 opcodes/mips-opc.c                    | 34 ++++++++++++++++++++
 16 files changed, 197 insertions(+), 7 deletions(-)
 create mode 100644 gas/testsuite/gas/mips/crypto.d
 create mode 100644 gas/testsuite/gas/mips/crypto.s

diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index e44cea87740..d38c43d171c 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -16731,6 +16731,8 @@ print_mips_ases (FILE *file, unsigned int mask)
     fputs ("\n\tLoongson EXT ASE", file);
   if (mask & AFL_ASE_LOONGSON_EXT2)
     fputs ("\n\tLoongson EXT2 ASE", file);
+  if (mask & AFL_ASE_CRYPTO)
+    fputs ("\n\tCRYPTO ASE", file);
   if (mask == 0)
     fprintf (file, "\n\t%s", _("None"));
   else if ((mask & ~AFL_ASE_MASK) != 0)
diff --git a/binutils/readelf.c b/binutils/readelf.c
index c98569a14b4..056d2b3d543 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -20417,6 +20417,8 @@ print_mips_ases (unsigned int mask)
     fputs ("\n\tLoongson EXT ASE", stdout);
   if (mask & AFL_ASE_LOONGSON_EXT2)
     fputs ("\n\tLoongson EXT2 ASE", stdout);
+  if (mask & AFL_ASE_CRYPTO)
+    fputs ("\n\tCRYPTO ASE", stdout);
   if (mask == 0)
     fprintf (stdout, "\n\t%s", _("None"));
   else if ((mask & ~AFL_ASE_MASK) != 0)
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 148a7af9b06..8651e0e7beb 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -1506,6 +1506,8 @@ enum options
     OPTION_NO_MIPS16E2,
     OPTION_CRC,
     OPTION_NO_CRC,
+    OPTION_CRYPTO,
+    OPTION_NO_CRYPTO,
     OPTION_M4650,
     OPTION_NO_M4650,
     OPTION_M4010,
@@ -1653,6 +1655,8 @@ const struct option md_longopts[] =
   {"mno-loongson-ext", no_argument, NULL, OPTION_NO_LOONGSON_EXT},
   {"mloongson-ext2", no_argument, NULL, OPTION_LOONGSON_EXT2},
   {"mno-loongson-ext2", no_argument, NULL, OPTION_NO_LOONGSON_EXT2},
+  {"mcrypto", no_argument, NULL, OPTION_CRYPTO},
+  {"mno-crypto", no_argument, NULL, OPTION_NO_CRYPTO},
 
   /* Old-style architecture options.  Don't add more of these.  */
   {"m4650", no_argument, NULL, OPTION_M4650},
@@ -1874,6 +1878,11 @@ static const struct mips_ase mips_ases[] = {
     OPTION_LOONGSON_EXT2, OPTION_NO_LOONGSON_EXT2,
     0, 0, -1, -1,
     -1 },
+
+  { "crypto", ASE_CRYPTO, 0,
+    OPTION_CRYPTO, OPTION_NO_CRYPTO,
+    6,  6, -1, -1,
+    -1 },
 };
 
 /* The set of ASEs that require -mfp64.  */
@@ -6405,6 +6414,9 @@ match_tied_reg_operand (struct mips_arg_info *arg, unsigned int other_regno)
 {
   unsigned int regno;
 
+  if (match_reg (arg, OP_REG_MSA, &regno) && regno == other_regno)
+    return TRUE;
+
   return match_reg (arg, OP_REG_GP, &regno) && regno == other_regno;
 }
 
@@ -20006,6 +20018,8 @@ mips_convert_ase_flags (int ase)
     ext_ases |= AFL_ASE_LOONGSON_EXT;
   if (ase & ASE_LOONGSON_EXT2)
     ext_ases |= AFL_ASE_LOONGSON_EXT2;
+  if (ase & ASE_CRYPTO)
+    ext_ases |= AFL_ASE_CRYPTO;
 
   return ext_ases;
 }
@@ -21049,6 +21063,9 @@ MIPS options:\n\
 -mloongson-ext2		generate Loongson EXTensions R2 (EXT2) instructions\n\
 -mno-loongson-ext2	do not generate Loongson EXTensions R2 Instructions\n"));
   fprintf (stream, _("\
+-mcrypto			generate crypto instructions\n\
+-mno-crypto		do not generate crypto instructions\n"));
+  fprintf (stream, _("\
 -minsn32		only generate 32-bit microMIPS instructions\n\
 -mno-insn32		generate all microMIPS instructions\n"));
 #if DEFAULT_MIPS_FIX_LOONGSON3_LLSC
diff --git a/gas/doc/as.texi b/gas/doc/as.texi
index 6114a178a0d..636a9b64d46 100644
--- a/gas/doc/as.texi
+++ b/gas/doc/as.texi
@@ -482,6 +482,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
    [@b{-mloongson-cam}] [@b{-mno-loongson-cam}]
    [@b{-mloongson-ext}] [@b{-mno-loongson-ext}]
    [@b{-mloongson-ext2}] [@b{-mno-loongson-ext2}]
+   [@b{-mcrypto}] [@b{-mno-crypto}]
    [@b{-minsn32}] [@b{-mno-insn32}]
    [@b{-mfix7000}] [@b{-mno-fix7000}]
    [@b{-mfix-rm7000}] [@b{-mno-fix-rm7000}]
@@ -1730,6 +1731,12 @@ This option implies @samp{-mloongson-ext}.
 This tells the assembler to accept Loongson EXT2 instructions.
 @samp{-mno-loongson-ext2} turns off this option.
 
+@item -mcrypto
+@itemx -mno-crypto
+Generate code for the MIPS Crypto Application Specific Extension.
+This tells the assembler to accept crypto instructions.
+@samp{-mno-crypto} turns off this option.
+
 @item -minsn32
 @itemx -mno-insn32
 Only use 32-bit instruction encodings when generating code for the
diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 44ad746c54f..9d33c0516ed 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -274,6 +274,13 @@ Application Specific Extension.  This tells the assembler to accept EXT2
 instructions.
 @samp{-mno-loongson-ext2} turns off this option.
 
+@item -mcrypto
+@itemx -mno-crypto
+Generate code for the Crypto Application Specific
+Extension.
+This tells the assembler to accept crypto instructions.
+@samp{-mno-crypto} turns off this option.
+
 @item -minsn32
 @itemx -mno-insn32
 Only use 32-bit instruction encodings when generating code for the
@@ -1163,7 +1170,7 @@ instructions from being accepted.
 @kindex @code{.set xpa}
 @kindex @code{.set noxpa}
 The directive @code{.set xpa} makes the assembler accept instructions
-from the XPA Extension from that point on in the assembly.  The 
+from the XPA Extension from that point on in the assembly.  The
 @code{.set noxpa} directive prevents XPA instructions from being accepted.
 
 @cindex MIPS16e2 instruction generation override
@@ -1223,6 +1230,13 @@ This directive implies @code{.set loognson-ext}.
 The @code{.set noloongson-ext2} directive prevents Loongson EXT2 instructions
 from being accepted.
 
+@cindex MIPS crypto instruction generation override
+@kindex @code{.set crypto}
+@kindex @code{.set nocrypto}
+The directive @code{.set crypto} makes the assembler accept instructions
+from the crypto extension from that point on in the assembly.  The
+@code{.set nocrypto} directive prevents crypto instructions from being accepted.
+
 Traditional MIPS assemblers do not support these directives.
 
 @node MIPS Floating-Point
diff --git a/gas/testsuite/gas/mips/ase-errors-1.l b/gas/testsuite/gas/mips/ase-errors-1.l
index b51db4fa545..ba9c677c218 100644
--- a/gas/testsuite/gas/mips/ase-errors-1.l
+++ b/gas/testsuite/gas/mips/ase-errors-1.l
@@ -52,3 +52,8 @@
 .*:128: Error: opcode not supported .* `scwpe \$2,\$3,\$4'
 .*:131: Error: opcode not supported .* `llwpe \$2,\$3,\$4'
 .*:132: Error: opcode not supported .* `scwpe \$2,\$3,\$4'
+# ----------------------------------------------------------------------------
+.*:137: Error: invalid operands `sha1.ms.2 \$w4,\$w7,\$w6'
+.*:138: Warning: the `crypto' extension requires MIPS32 revision 6 or greater
+.*:141: Error: opcode not supported.* `sha1.ms.1 \$w4,\$w7,\$w6'
+# ----------------------------------------------------------------------------
diff --git a/gas/testsuite/gas/mips/ase-errors-1.s b/gas/testsuite/gas/mips/ase-errors-1.s
index 7deeea1df26..9bdc15b80e8 100644
--- a/gas/testsuite/gas/mips/ase-errors-1.s
+++ b/gas/testsuite/gas/mips/ase-errors-1.s
@@ -131,6 +131,15 @@
 	llwpe	$2, $3, $4	# ERROR: only avaialable on R6
 	scwpe	$2, $3, $4	# ERROR: only avaialable on R6
 
+	.set mips32r6
+	.set crypto		# OK
+	aes128.enc	$w4,$w7	# OK
+	sha1.ms.2 	$w4,$w7,$w6	#ERROR: Invalid operands
+	.set mips32r5		# ERROR: too low
+	aes256.enc	$w4,$w7,$w6	# OK
+	.set nocrypto
+	sha1.ms.1	$w4,$w7,$w6	# ERROR: crypto not enabled
+
 	# There should be no errors after this.
 	.set fp=32
 	.set mips1
diff --git a/gas/testsuite/gas/mips/ase-errors-2.l b/gas/testsuite/gas/mips/ase-errors-2.l
index 6ac51630d44..7c5a3e2b000 100644
--- a/gas/testsuite/gas/mips/ase-errors-2.l
+++ b/gas/testsuite/gas/mips/ase-errors-2.l
@@ -40,3 +40,7 @@
 .*:103: Warning: the `ginv' extension requires MIPS64 revision 6 or greater
 .*:106: Error: opcode not supported.* `ginvi \$a0'
 # ----------------------------------------------------------------------------
+.*:111: Error: invalid operands `sha1.ms.2 \$w4,\$w7,\$w6'
+.*:112: Warning: the `crypto' extension requires MIPS64 revision 6 or greater
+.*:115: Error: opcode not supported.* `sha1.ms.1 \$w4,\$w7,\$w6'
+# ----------------------------------------------------------------------------
diff --git a/gas/testsuite/gas/mips/ase-errors-2.s b/gas/testsuite/gas/mips/ase-errors-2.s
index 2b31517e6e1..0b1684b87a1 100644
--- a/gas/testsuite/gas/mips/ase-errors-2.s
+++ b/gas/testsuite/gas/mips/ase-errors-2.s
@@ -105,6 +105,15 @@
 	.set noginv
 	ginvi $a0		# ERROR: ginv not enabled
 
+	.set mips64r6
+	.set crypto		# OK
+	aes128.enc	$w4,$w7	# OK
+	sha1.ms.2	$w4,$w7,$w6	# ERROR: Invalid operands
+	.set mips64r5		# ERROR: too low
+	aes256.enc	$w4,$w7,$w6	# OK
+	.set nocrypto
+	sha1.ms.1	$w4,$w7,$w6	# ERROR: crypto not enabled
+
 	# There should be no errors after this.
 	.set fp=32
 	.set mips4
diff --git a/gas/testsuite/gas/mips/crypto.d b/gas/testsuite/gas/mips/crypto.d
new file mode 100644
index 00000000000..30bb26ec06e
--- /dev/null
+++ b/gas/testsuite/gas/mips/crypto.d
@@ -0,0 +1,45 @@
+#objdump: -pdr --prefix-addresses --show-raw-insn
+#name: MIPS CRYPTO
+#as: -mcrypto -32
+
+# Test the CRYPTO instructions
+
+.*: +file format .*mips.*
+#...
+ASEs:
+#...
+	CRYPTO ASE
+#...
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 78003917 	aes128.enc	\$w4,\$w7
+[0-9a-f]+ <[^>]*> 78013917 	aes128.dec	\$w4,\$w7
+[0-9a-f]+ <[^>]*> 78463917 	aes192.enc	\$w4,\$w7,\$w6
+[0-9a-f]+ <[^>]*> 78663917 	aes192.dec	\$w4,\$w7,\$w6
+[0-9a-f]+ <[^>]*> 78863917 	aes256.enc	\$w4,\$w7,\$w6
+[0-9a-f]+ <[^>]*> 78a63917 	aes256.dec	\$w4,\$w7,\$w6
+[0-9a-f]+ <[^>]*> 781a3917 	aes.kg	\$w4,\$w7
+[0-9a-f]+ <[^>]*> 78103917 	aes.fr.enc	\$w4,\$w7
+[0-9a-f]+ <[^>]*> 78113917 	aes.fr.dec	\$w4,\$w7
+[0-9a-f]+ <[^>]*> 78123917 	aes.lr.enc	\$w4,\$w7
+[0-9a-f]+ <[^>]*> 78133917 	aes.lr.dec	\$w4,\$w7
+[0-9a-f]+ <[^>]*> 78160117 	aes.mc.enc	\$w4
+[0-9a-f]+ <[^>]*> 78170117 	aes.mc.dec	\$w4
+[0-9a-f]+ <[^>]*> 78140117 	aes.sb.enc	\$w4
+[0-9a-f]+ <[^>]*> 78150117 	aes.sb.dec	\$w4
+[0-9a-f]+ <[^>]*> 78180117 	aes.sr.enc	\$w4
+[0-9a-f]+ <[^>]*> 78190117 	aes.sr.dec	\$w4
+[0-9a-f]+ <[^>]*> 7be63917 	md5.ms	\$w4,\$w7,\$w6
+[0-9a-f]+ <[^>]*> 7ae63917 	md5.4r	\$w4,\$w7,\$w6
+[0-9a-f]+ <[^>]*> 7b063917 	sha1.ms.1	\$w4,\$w7,\$w6
+[0-9a-f]+ <[^>]*> 7b203917 	sha1.ms.2	\$w4,\$w7,\$w4
+[0-9a-f]+ <[^>]*> 7a063917 	sha1.hash.4r	\$w4,\$w7,\$w6
+[0-9a-f]+ <[^>]*> 7b463917 	sha256.ms.1	\$w4,\$w7,\$w6
+[0-9a-f]+ <[^>]*> 7b663917 	sha256.ms.2	\$w4,\$w7,\$w6
+[0-9a-f]+ <[^>]*> 7a463917 	sha256.hash.2r	\$w4,\$w7,\$w6
+[0-9a-f]+ <[^>]*> 7b863917 	sha512.ms.1	\$w4,\$w7,\$w6
+[0-9a-f]+ <[^>]*> 7ba63917 	sha512.ms.2	\$w4,\$w7,\$w6
+[0-9a-f]+ <[^>]*> 7a863917 	sha512.hash.r.1	\$w4,\$w7,\$w6
+[0-9a-f]+ <[^>]*> 7aa63917 	sha512.hash.r.2	\$w4,\$w7,\$w6
+
+	\.\.\.
diff --git a/gas/testsuite/gas/mips/crypto.s b/gas/testsuite/gas/mips/crypto.s
new file mode 100644
index 00000000000..d7e2db0e79e
--- /dev/null
+++ b/gas/testsuite/gas/mips/crypto.s
@@ -0,0 +1,38 @@
+	.set	noreorder
+	.set	noat
+
+	.text
+test_crypto:
+	aes128.enc	$w4, $w7
+	aes128.dec	$w4, $w7
+	aes192.enc	$w4, $w7, $w6
+	aes192.dec	$w4, $w7, $w6
+	aes256.enc	$w4, $w7, $w6
+	aes256.dec	$w4, $w7, $w6
+	aes.kg		$w4, $w7
+	aes.fr.enc	$w4, $w7
+	aes.fr.dec	$w4, $w7
+	aes.lr.enc	$w4, $w7
+	aes.lr.dec	$w4, $w7
+	aes.mc.enc	$w4
+	aes.mc.dec	$w4
+	aes.sb.enc	$w4
+	aes.sb.dec	$w4
+	aes.sr.enc	$w4
+	aes.sr.dec	$w4
+	md5.ms		$w4, $w7, $w6
+	md5.4r		$w4, $w7, $w6
+	sha1.ms.1	$w4, $w7, $w6
+	sha1.ms.2	$w4, $w7, $w4
+	sha1.hash.4r	$w4, $w7, $w6
+	sha256.ms.1	$w4, $w7, $w6
+	sha256.ms.2	$w4, $w7, $w6
+	sha256.hash.2r	$w4, $w7, $w6
+	sha512.ms.1	$w4, $w7, $w6
+	sha512.ms.2	$w4, $w7, $w6
+	sha512.hash.r.1	$w4, $w7, $w6
+	sha512.hash.r.2	$w4, $w7, $w6
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+	.align	2
+	.space	8
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index da9839a8af9..4f9ac01f21d 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -2291,8 +2291,8 @@ if { [istarget mips*-*-vxworks*] } {
 			      [mips_arch_list_matching mips32r6 !mips64r6]
 
     run_dump_test "llpscp-32"
-    run_dump_test "llpscp-64"
     run_dump_test "llpscp-32-micromips"
+    run_dump_test "llpscp-64"
     run_dump_test "llpscp-64-micromips"
 
     run_dump_test "pr14798${imips}"
@@ -2317,4 +2317,6 @@ if { [istarget mips*-*-vxworks*] } {
 					    !mips32r6]
     run_dump_test_arches "trap-opt"	[mips_arch_list_matching mips1 \
 					    !mips32r6]
+    run_dump_test_arches "crypto"	[mips_arch_list_matching mips32r6 \
+					     !micromipsr6]
 }
diff --git a/include/elf/mips.h b/include/elf/mips.h
index 2dac5dc3bd7..35faad3f1bf 100644
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -1299,13 +1299,13 @@ extern void bfd_mips_elf_swap_abiflags_v0_out
 #define AFL_ASE_DSPR3        0x00002000 /* DSP R3 ASE.  */
 #define AFL_ASE_MIPS16E2     0x00004000 /* MIPS16e2 ASE.  */
 #define AFL_ASE_CRC          0x00008000 /* CRC ASE.  */
-#define AFL_ASE_RESERVED1    0x00010000 /* Reserved by MIPS Tech for WIP.  */
+#define AFL_ASE_CRYPTO       0x00010000 /* CRYPTO ASE.  */
 #define AFL_ASE_GINV         0x00020000 /* GINV ASE.  */
 #define AFL_ASE_LOONGSON_MMI 0x00040000 /* Loongson MMI ASE.  */
 #define AFL_ASE_LOONGSON_CAM 0x00080000 /* Loongson CAM ASE.  */
 #define AFL_ASE_LOONGSON_EXT 0x00100000 /* Loongson EXT instructions.  */
 #define AFL_ASE_LOONGSON_EXT2 0x00200000 /* Loongson EXT2 instructions.  */
-#define AFL_ASE_MASK         0x003effff /* All ASEs.  */
+#define AFL_ASE_MASK         0x003fffff /* All ASEs.  */
 
 /* Values for the isa_ext word of an ABI flags structure.  */
 
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 5d22fcf1a36..35b4273fdfe 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -925,7 +925,7 @@ mips_opcode_32bit_p (const struct mips_opcode *mo)
 #define INSN_ISA32R3              8
 #define INSN_ISA32R5              9
 #define INSN_ISA32R6              10
-#define INSN_ISA64                11 
+#define INSN_ISA64                11
 #define INSN_ISA64R2              12
 #define INSN_ISA64R3              13
 #define INSN_ISA64R5              14
@@ -1083,6 +1083,8 @@ static const unsigned int mips_isa_table[] = {
 /* The Enhanced VA Scheme (EVA) extension has instructions which are
    only valid for the R6 ISA.  */
 #define ASE_EVA_R6		0x02000000
+/* Crypto ASE */
+#define ASE_CRYPTO		0x04000000
 
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index c5f723392ce..e000d762d32 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -618,7 +618,7 @@ const struct mips_arch_choice mips_arch_choices[] =
   { "mips32r6",	1, bfd_mach_mipsisa32r6, CPU_MIPS32R6,
     ISA_MIPS32R6,
     (ASE_EVA | ASE_MSA | ASE_VIRT | ASE_XPA | ASE_MCU | ASE_MT | ASE_DSP
-     | ASE_DSPR2 | ASE_DSPR3 | ASE_CRC | ASE_GINV),
+     | ASE_DSPR2 | ASE_DSPR3 | ASE_CRC | ASE_GINV | ASE_CRYPTO),
     mips_cp0_names_mips3264r2,
     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
     mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
@@ -658,7 +658,7 @@ const struct mips_arch_choice mips_arch_choices[] =
     ISA_MIPS64R6,
     (ASE_EVA | ASE_MSA | ASE_MSA64 | ASE_XPA | ASE_VIRT | ASE_VIRT64
      | ASE_MCU | ASE_MT | ASE_DSP | ASE_DSPR2 | ASE_DSPR3 | ASE_CRC
-     | ASE_CRC64 | ASE_GINV),
+     | ASE_CRC64 | ASE_GINV | ASE_CRYPTO),
     mips_cp0_names_mips3264r2,
     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
     mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index a407e514a15..7324952a64a 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -406,6 +406,9 @@ decode_mips_operand (const char *p)
 #define MSA	ASE_MSA
 #define MSA64	ASE_MSA64
 
+/* Crypto support.  */
+#define CRYPTO	ASE_CRYPTO
+
 /* eXtended Physical Address (XPA) support.  */
 #define XPA     ASE_XPA
 #define XPAVZ	ASE_XPA_VIRT
@@ -3150,6 +3153,37 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"restore",		"-m",		0x7000001f, 0xfc00603f, WR_31|NODS,		MOD_SP,		IAMR2,		0,	0 },
 {"save",		"-m",		0x7000201f, 0xfc00603f, NODS,			RD_31|MOD_SP,	IAMR2,		0,	0 },
 
+/* MIPS Crypto ASE.  */
+{"aes128.enc",		"+d,+e",	0x78000017, 0xffff003f,	MOD_1|RD_2,		0,		0,		CRYPTO,	0 },
+{"aes128.dec",		"+d,+e",	0x78010017, 0xffff003f,	MOD_1|RD_2,		0,		0,		CRYPTO,	0 },
+{"aes192.enc",		"+d,+e,+h",	0x78400017, 0xffe0003f,	MOD_1|RD_2|RD_3,	0,		0,		CRYPTO,	0 },
+{"aes192.dec",		"+d,+e,+h",	0x78600017, 0xffe0003f,	MOD_1|RD_2|RD_3,	0,		0,		CRYPTO,	0 },
+{"aes256.enc",		"+d,+e,+h",	0x78800017, 0xffe0003f,	MOD_1|RD_2|RD_3,	0,		0,		CRYPTO,	0 },
+{"aes256.dec",		"+d,+e,+h",	0x78a00017, 0xffe0003f,	MOD_1|RD_2|RD_3,	0,		0,		CRYPTO,	0 },
+{"aes.kg",		"+d,+e",	0x781a0017, 0xffff003f,	MOD_1|RD_2,		0,		0,		CRYPTO,	0 },
+{"aes.fr.enc",		"+d,+e",	0x78100017, 0xffff003f,	MOD_1|RD_2,		0,		0,		CRYPTO,	0 },
+{"aes.fr.dec",		"+d,+e",	0x78110017, 0xffff003f,	MOD_1|RD_2,		0,		0,		CRYPTO,	0 },
+{"aes.lr.enc",		"+d,+e",	0x78120017, 0xffff003f,	MOD_1|RD_2,		0,		0,		CRYPTO,	0 },
+{"aes.lr.dec",		"+d,+e",	0x78130017, 0xffff003f,	MOD_1|RD_2,		0,		0,		CRYPTO,	0 },
+{"aes.mc.enc",		"+d",		0x78160017, 0xfffff83f,	MOD_1,			0,		0,		CRYPTO,	0 },
+{"aes.mc.dec",		"+d",		0x78170017, 0xfffff83f,	MOD_1,			0,		0,		CRYPTO,	0 },
+{"aes.sb.enc",		"+d",		0x78140017, 0xfffff83f,	MOD_1,			0,		0,		CRYPTO,	0 },
+{"aes.sb.dec",		"+d",		0x78150017, 0xfffff83f,	MOD_1,			0,		0,		CRYPTO,	0 },
+{"aes.sr.enc",		"+d",		0x78180017, 0xfffff83f,	MOD_1,			0,		0,		CRYPTO,	0 },
+{"aes.sr.dec",		"+d",		0x78190017, 0xfffff83f,	MOD_1,			0,		0,		CRYPTO,	0 },
+{"md5.ms",		"+d,+e,+h",	0x7be00017, 0xffe0003f,	MOD_1|RD_2|RD_3,	0,		0,		CRYPTO,	0 },
+{"md5.4r",		"+d,+e,+h",	0x7ae00017, 0xffe0003f,	MOD_1|RD_2|RD_3,	0,		0,		CRYPTO,	0 },
+{"sha1.ms.1",		"+d,+e,+h",	0x7b000017, 0xffe0003f,	MOD_1|RD_2|RD_3,	0,		0,		CRYPTO,	0 },
+{"sha1.ms.2",		"+d,+e,-d",	0x7b200017, 0xffff003f,	MOD_1|RD_2,		0,		0,		CRYPTO,	0 },
+{"sha1.hash.4r",	"+d,+e,+h",	0x7a000017, 0xffe0003f,	MOD_1|RD_2|RD_3,	0,		0,		CRYPTO,	0 },
+{"sha256.ms.1",		"+d,+e,+h",	0x7b400017, 0xffe0003f,	WR_1|RD_2|RD_3,		0,		0,		CRYPTO,	0 },
+{"sha256.ms.2",		"+d,+e,+h",	0x7b600017, 0xffe0003f,	WR_1|RD_2|RD_3,		0,		0,		CRYPTO,	0 },
+{"sha256.hash.2r",	"+d,+e,+h",	0x7a400017, 0xffe0003f,	MOD_1|RD_2|RD_3,	0,		0,		CRYPTO,	0 },
+{"sha512.ms.1",		"+d,+e,+h",	0x7b800017, 0xffe0003f,	MOD_1|RD_2|RD_3,	0,		0,		CRYPTO,	0 },
+{"sha512.ms.2",		"+d,+e,+h",	0x7ba00017, 0xffe0003f,	MOD_1|RD_2|RD_3,	0,		0,		CRYPTO,	0 },
+{"sha512.hash.r.1",	"+d,+e,+h",	0x7a800017, 0xffe0003f,	MOD_1|RD_2|RD_3,	0,		0,		CRYPTO,	0 },
+{"sha512.hash.r.2",	"+d,+e,+h",	0x7aa00017, 0xffe0003f,	MOD_1|RD_2|RD_3,	0,		0,		CRYPTO,	0 },
+
 /* User Defined Instruction.  */
 {"udi0",		"s,t,d,+1",	0x70000010, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
 {"udi0",		"s,t,+2",	0x70000010, 0xfc00003f,	UDI,			0,		I33,		0,	0 },
-- 
2.34.1

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