[PATCH v3] Support AVX10_V2_AUX instructions

[Jan Beulich]

On 27.08.2026 09:13, Jiang, Haochen wrote:
>> From: Rohan Shenoy <RohanRadhesh.Shenoy@amd.com>
>> Sent: Thursday, August 27, 2026 2:44 PM
>>
>> diff --git a/opcodes/i386-dis-evex-prefix.h b/opcodes/i386-dis-evex-prefix.h
>> index 1aeac210c5d..0135703912a 100644
>> --- a/opcodes/i386-dis-evex-prefix.h
>> +++ b/opcodes/i386-dis-evex-prefix.h
>> +  /* PREFIX_EVEX_MAP5_3C_W_0 */
>> +  {
>> +    { Bad_Opcode },
>> +    { "vcvthf82hf6s",	{ XM, Ux }, 0 },
>> +  },
>> +  /* PREFIX_EVEX_MAP5_3D */
>> +  {
>> +    { Bad_Opcode },
>> +    { "vcvt%HB82bf4s",	{ EXxmmq, XM }, 0 },
>> +  },
>> +  /* PREFIX_EVEX_MAP5_3E_W_1 */
>> +  {
>> +    { Bad_Opcode },
>> +    { "vcvtbf82bf6s",	{ XM, Ux }, 0 },
>> +  },
> 
> 
> We need to hold the patch (or part of the patch) for these
> insns.
> 
> This line
>> +    { "vcvt%HB82bf4s",	{ EXxmmq, XM }, 0 },
> is not matching the documentation where documentation
> uses modrm.reg for operand1 and modrm.r/m for operand2.
> It is a documentation bug since we have memory for operand1.
> 
> While for those FP8 to FP6 insns, I am not sure if the current
> documentation is the correct version. I saw a version using
> modrm.r/m for operand1 and modrm.reg for operand2, where
> current SDE is also using this version.

In fact doc version 1.15 section 9.4.2 is inconsistent in itself here:

Form
xmm1/m64, xmm2
xmm1/m128, ymm2
ymm1/m256, zmm2

vs

Instruction	Operand 1	Operand 2	Operand 3
VCVTBF82BF4S
VCVTHF82BF4S	MODRM.REG(w)	MODRM.R/M(r)	N/A

Jan