[PATCH] include, opcodes: prefix REG_* macros in cris.h, nds32.h and microblaze-opcm.h
Simon Marchi
simon.marchi@efficios.com
Tue Aug 18 20:27:29 GMT 2026
Bug 34537 reports:
When building gdb with the default configure options of gdb buildbots (which
include --enable-targets=all), gdb fails to build:
CXX microblaze-tdep.o
In file included from ../../binutils-gdb/gdb/microblaze-tdep.c:37:
../../binutils-gdb/gdb/../opcodes/microblaze-opcm.h:101:9: error: ‘REG_PC’ redefined [-Werror]
101 | #define REG_PC 32 /* PC. */
| ^~~~~~
In file included from /usr/include/sys/ucontext.h:14,
from /usr/include/sys/signal.h:197,
from /usr/include/sys/procset.h:17,
from /usr/include/sys/wait.h:22,
from ../gnulib/import/sys/wait.h:28,
from /usr/include/stdlib.h:16,
from /usr/gcc/16/include/c++/16.1.0/cstdlib:83,
from ../../binutils-gdb/gdb/../gdbsupport/common-defs.h:107,
from ./../../binutils-gdb/gdb/defs.h:26,
from <command-line>:
/usr/include/sys/regset.h:158:9: note: this is the location of the previous definition
158 | #define REG_PC REG_RIP
| ^~~~~~
../../binutils-gdb/gdb/../opcodes/microblaze-opcm.h:120:9: error: ‘REG_SP’ redefined [-Werror]
120 | #define REG_SP 1 /* stack pointer. */
| ^~~~~~
/usr/include/sys/regset.h:160:9: note: this is the location of the previous definition
160 | #define REG_SP REG_RSP
| ^~~~~~
There are more instances of this issue:
gdb/../include/opcode/cris.h:34:9: error: ‘REG_SP’ redefined [-Werror]
gdb/../include/opcode/cris.h:35:9: error: ‘REG_PC’ redefined [-Werror]
gdb/../include/opcode/nds32.h:24:9: error: ‘REG_R0’ redefined [-Werror]
gdb/../include/opcode/nds32.h:26:9: error: ‘REG_R8’ redefined [-Werror]
gdb/../include/opcode/nds32.h:27:9: error: ‘REG_R10’ redefined [-Werror]
gdb/../include/opcode/nds32.h:28:9: error: ‘REG_R12’ redefined [-Werror]
gdb/../include/opcode/nds32.h:29:9: error: ‘REG_R15’ redefined [-Werror]
gdb/../include/opcode/nds32.h:34:9: error: ‘REG_FP’ redefined [-Werror]
gdb/../include/opcode/nds32.h:37:9: error: ‘REG_SP’ redefined [-Werror]
Attempt to fix it by prefixing the macros with the arch name.
I only modified the macros starting with "REG_", but there are other
macros with very generic names (e.g. "MAX_REG") that could be renamed
too (for consistency, IMO, all the macros in those files should be
prefixed the same way).
I couldn't build-test this patch on Solaris, but it build with
--enable-targets=all on Linux.
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=34537
Change-Id: I33ff448fe26be76c14a89ac698fa9f9dc17208b0
---
bfd/elf32-nds32.c | 131 +++++++++++++++------------
gas/config/tc-cris.c | 14 +--
gas/config/tc-microblaze.c | 179 +++++++++++++++++++------------------
gas/config/tc-nds32.c | 4 +-
gdb/cris-tdep.c | 151 +++++++++++++++----------------
gdb/microblaze-tdep.c | 30 +++++--
gdb/nds32-tdep.c | 60 +++++++------
include/opcode/cris.h | 12 +--
include/opcode/nds32.h | 62 ++++++-------
opcodes/microblaze-dis.c | 39 ++++----
opcodes/microblaze-opcm.h | 74 +++++++--------
11 files changed, 394 insertions(+), 362 deletions(-)
diff --git a/bfd/elf32-nds32.c b/bfd/elf32-nds32.c
index daad1deb85dd..b265e720e6a4 100644
--- a/bfd/elf32-nds32.c
+++ b/bfd/elf32-nds32.c
@@ -7732,7 +7732,7 @@ nds32_convert_32_to_16_alu1 (bfd *abfd, uint32_t insn, uint16_t *pinsn16,
break;
case N32_ALU1_SLT:
- if (N32_RT5 (insn) == REG_R15 && N32_IS_RA4 (insn))
+ if (N32_RT5 (insn) == N32_REG_R15 && N32_IS_RA4 (insn))
{
/* Implicit r15. */
insn16 = N16_TYPE45 (SLT45, N32_RA54 (insn), N32_RB5 (insn));
@@ -7741,7 +7741,7 @@ nds32_convert_32_to_16_alu1 (bfd *abfd, uint32_t insn, uint16_t *pinsn16,
break;
case N32_ALU1_SLTS:
- if (N32_RT5 (insn) == REG_R15 && N32_IS_RA4 (insn))
+ if (N32_RT5 (insn) == N32_REG_R15 && N32_IS_RA4 (insn))
{
/* Implicit r15. */
insn16 = N16_TYPE45 (SLTS45, N32_RA54 (insn), N32_RB5 (insn));
@@ -7839,7 +7839,7 @@ bfd_elf_nds32_convert_32_to_16 (bfd *abfd, uint32_t insn, uint16_t *pinsn16,
/* Do not convert `addi $sp, $sp, 0' to `mov55 $sp, $sp',
because `mov55 $sp, $sp' is ifret16 in V3 ISA. */
if (mach <= MACH_V2
- || N32_RT5 (insn) != REG_SP || N32_RA5 (insn) != REG_SP)
+ || N32_RT5 (insn) != N32_REG_SP || N32_RA5 (insn) != N32_REG_SP)
{
insn16 = N16_TYPE55 (MOV55, N32_RT5 (insn), N32_RA5 (insn));
insn_type = NDS32_INSN_MOV55;
@@ -7859,7 +7859,7 @@ bfd_elf_nds32_convert_32_to_16 (bfd *abfd, uint32_t insn, uint16_t *pinsn16,
insn16 = N16_TYPE45 (ADDI45, N32_RT54 (insn), N32_IMM15S (insn));
insn_type = NDS32_INSN_ADDI45;
}
- else if (mach >= MACH_V2 && N32_RT5 (insn) == REG_SP
+ else if (mach >= MACH_V2 && N32_RT5 (insn) == N32_REG_SP
&& N32_RT5 (insn) == N32_RA5 (insn)
&& N32_IMM15S (insn) < 512)
{
@@ -7867,7 +7867,7 @@ bfd_elf_nds32_convert_32_to_16 (bfd *abfd, uint32_t insn, uint16_t *pinsn16,
insn_type = NDS32_INSN_ADDI10_SP;
}
else if (mach >= MACH_V3 && N32_IS_RT3 (insn)
- && N32_RA5 (insn) == REG_SP && N32_IMM15S (insn) < 256
+ && N32_RA5 (insn) == N32_REG_SP && N32_IMM15S (insn) < 256
&& (N32_IMM15S (insn) % 4 == 0))
{
insn16 = N16_TYPE36 (ADDRI36_SP, N32_RT5 (insn),
@@ -7891,7 +7891,7 @@ bfd_elf_nds32_convert_32_to_16 (bfd *abfd, uint32_t insn, uint16_t *pinsn16,
0 - N32_IMM15S (insn));
insn_type = NDS32_INSN_SUBI45;
}
- else if (mach >= MACH_V2 && N32_RT5 (insn) == REG_SP
+ else if (mach >= MACH_V2 && N32_RT5 (insn) == N32_REG_SP
&& N32_RT5 (insn) == N32_RA5 (insn)
&& N32_IMM15S (insn) >= -512)
{
@@ -7907,7 +7907,7 @@ bfd_elf_nds32_convert_32_to_16 (bfd *abfd, uint32_t insn, uint16_t *pinsn16,
/* Do not convert `ori $sp, $sp, 0' to `mov55 $sp, $sp',
because `mov55 $sp, $sp' is ifret16 in V3 ISA. */
if (mach <= MACH_V2
- || N32_RT5 (insn) != REG_SP || N32_RA5 (insn) != REG_SP)
+ || N32_RT5 (insn) != N32_REG_SP || N32_RA5 (insn) != N32_REG_SP)
{
insn16 = N16_TYPE55 (MOV55, N32_RT5 (insn), N32_RA5 (insn));
insn_type = NDS32_INSN_MOV55;
@@ -7968,7 +7968,7 @@ bfd_elf_nds32_convert_32_to_16 (bfd *abfd, uint32_t insn, uint16_t *pinsn16,
break;
case N32_OP6_SLTI:
- if (N32_RT5 (insn) == REG_R15 && N32_IS_RA4 (insn)
+ if (N32_RT5 (insn) == N32_REG_R15 && N32_IS_RA4 (insn)
&& IS_WITHIN_U (N32_IMM15S (insn), 5))
{
insn16 = N16_TYPE45 (SLTI45, N32_RA54 (insn), N32_IMM15S (insn));
@@ -7977,7 +7977,7 @@ bfd_elf_nds32_convert_32_to_16 (bfd *abfd, uint32_t insn, uint16_t *pinsn16,
break;
case N32_OP6_SLTSI:
- if (N32_RT5 (insn) == REG_R15 && N32_IS_RA4 (insn)
+ if (N32_RT5 (insn) == N32_REG_R15 && N32_IS_RA4 (insn)
&& IS_WITHIN_U (N32_IMM15S (insn), 5))
{
insn16 = N16_TYPE45 (SLTSI45, N32_RA54 (insn), N32_IMM15S (insn));
@@ -7998,19 +7998,21 @@ bfd_elf_nds32_convert_32_to_16 (bfd *abfd, uint32_t insn, uint16_t *pinsn16,
N32_IMM15S (insn));
insn_type = NDS32_INSN_LWI333;
}
- else if (N32_IS_RT3 (insn) && N32_RA5 (insn) == REG_FP
+ else if (N32_IS_RT3 (insn) && N32_RA5 (insn) == N32_REG_FP
&& IS_WITHIN_U (N32_IMM15S (insn), 7))
{
insn16 = N16_TYPE37 (XWI37, N32_RT5 (insn), 0, N32_IMM15S (insn));
insn_type = NDS32_INSN_LWI37;
}
- else if (mach >= MACH_V2 && N32_IS_RT3 (insn) && N32_RA5 (insn) == REG_SP
+ else if (mach >= MACH_V2 && N32_IS_RT3 (insn)
+ && N32_RA5 (insn) == N32_REG_SP
&& IS_WITHIN_U (N32_IMM15S (insn), 7))
{
insn16 = N16_TYPE37 (XWI37SP, N32_RT5 (insn), 0, N32_IMM15S (insn));
insn_type = NDS32_INSN_LWI37_SP;
}
- else if (mach >= MACH_V2 && N32_IS_RT4 (insn) && N32_RA5 (insn) == REG_R8
+ else if (mach >= MACH_V2 && N32_IS_RT4 (insn)
+ && N32_RA5 (insn) == N32_REG_R8
&& -32 <= N32_IMM15S (insn) && N32_IMM15S (insn) < 0)
{
insn16 = N16_TYPE45 (LWI45_FE, N32_RT54 (insn),
@@ -8032,13 +8034,14 @@ bfd_elf_nds32_convert_32_to_16 (bfd *abfd, uint32_t insn, uint16_t *pinsn16,
N32_IMM15S (insn));
insn_type = NDS32_INSN_SWI333;
}
- else if (N32_IS_RT3 (insn) && N32_RA5 (insn) == REG_FP
+ else if (N32_IS_RT3 (insn) && N32_RA5 (insn) == N32_REG_FP
&& IS_WITHIN_U (N32_IMM15S (insn), 7))
{
insn16 = N16_TYPE37 (XWI37, N32_RT5 (insn), 1, N32_IMM15S (insn));
insn_type = NDS32_INSN_SWI37;
}
- else if (mach >= MACH_V2 && N32_IS_RT3 (insn) && N32_RA5 (insn) == REG_SP
+ else if (mach >= MACH_V2 && N32_IS_RT3 (insn)
+ && N32_RA5 (insn) == N32_REG_SP
&& IS_WITHIN_U (N32_IMM15S (insn), 7))
{
insn16 = N16_TYPE37 (XWI37SP, N32_RT5 (insn), 1, N32_IMM15S (insn));
@@ -8119,11 +8122,11 @@ bfd_elf_nds32_convert_32_to_16 (bfd *abfd, uint32_t insn, uint16_t *pinsn16,
if ((insn & N32_BIT (14)) == 0)
{
/* N32_BR1_BEQ */
- if (N32_IS_RT3 (insn) && N32_RA5 (insn) == REG_R5
- && N32_RT5 (insn) != REG_R5)
+ if (N32_IS_RT3 (insn) && N32_RA5 (insn) == N32_REG_R5
+ && N32_RT5 (insn) != N32_REG_R5)
insn16 = N16_TYPE38 (BEQS38, N32_RT5 (insn), N32_IMM14S (insn));
- else if (N32_IS_RA3 (insn) && N32_RT5 (insn) == REG_R5
- && N32_RA5 (insn) != REG_R5)
+ else if (N32_IS_RA3 (insn) && N32_RT5 (insn) == N32_REG_R5
+ && N32_RA5 (insn) != N32_REG_R5)
insn16 = N16_TYPE38 (BEQS38, N32_RA5 (insn), N32_IMM14S (insn));
insn_type = NDS32_INSN_BEQS38;
break;
@@ -8131,11 +8134,11 @@ bfd_elf_nds32_convert_32_to_16 (bfd *abfd, uint32_t insn, uint16_t *pinsn16,
else
{
/* N32_BR1_BNE */
- if (N32_IS_RT3 (insn) && N32_RA5 (insn) == REG_R5
- && N32_RT5 (insn) != REG_R5)
+ if (N32_IS_RT3 (insn) && N32_RA5 (insn) == N32_REG_R5
+ && N32_RT5 (insn) != N32_REG_R5)
insn16 = N16_TYPE38 (BNES38, N32_RT5 (insn), N32_IMM14S (insn));
- else if (N32_IS_RA3 (insn) && N32_RT5 (insn) == REG_R5
- && N32_RA5 (insn) != REG_R5)
+ else if (N32_IS_RA3 (insn) && N32_RT5 (insn) == N32_REG_R5
+ && N32_RA5 (insn) != N32_REG_R5)
insn16 = N16_TYPE38 (BNES38, N32_RA5 (insn), N32_IMM14S (insn));
insn_type = NDS32_INSN_BNES38;
break;
@@ -8151,7 +8154,7 @@ bfd_elf_nds32_convert_32_to_16 (bfd *abfd, uint32_t insn, uint16_t *pinsn16,
insn16 = N16_TYPE38 (BEQZ38, N32_RT5 (insn), N32_IMM16S (insn));
insn_type = NDS32_INSN_BEQZ38;
}
- else if (N32_RT5 (insn) == REG_R15
+ else if (N32_RT5 (insn) == N32_REG_R15
&& IS_WITHIN_S (N32_IMM16S (insn), 8))
{
insn16 = N16_TYPE8 (BEQZS8, N32_IMM16S (insn));
@@ -8165,7 +8168,7 @@ bfd_elf_nds32_convert_32_to_16 (bfd *abfd, uint32_t insn, uint16_t *pinsn16,
insn16 = N16_TYPE38 (BNEZ38, N32_RT5 (insn), N32_IMM16S (insn));
insn_type = NDS32_INSN_BNEZ38;
}
- else if (N32_RT5 (insn) == REG_R15
+ else if (N32_RT5 (insn) == N32_REG_R15
&& IS_WITHIN_S (N32_IMM16S (insn), 8))
{
insn16 = N16_TYPE8 (BNEZS8, N32_IMM16S (insn));
@@ -8217,7 +8220,7 @@ bfd_elf_nds32_convert_32_to_16 (bfd *abfd, uint32_t insn, uint16_t *pinsn16,
else if (N32_JREG_HINT (insn) == 3)
{
/* ifret = mov55 $sp, $sp */
- insn16 = N16_TYPE55 (MOV55, REG_SP, REG_SP);
+ insn16 = N16_TYPE55 (MOV55, N32_REG_SP, N32_REG_SP);
insn_type = NDS32_INSN_IFRET;
}
break;
@@ -8225,7 +8228,7 @@ bfd_elf_nds32_convert_32_to_16 (bfd *abfd, uint32_t insn, uint16_t *pinsn16,
case N32_JREG_JRAL:
/* It's convertible when return rt5 is $lp and address
translation is kept. */
- if (N32_RT5 (insn) == REG_LP && N32_JREG_HINT (insn) == 0)
+ if (N32_RT5 (insn) == N32_REG_LP && N32_JREG_HINT (insn) == 0)
{
insn16 = N16_TYPE5 (JRAL5, N32_RB5 (insn));
insn_type = NDS32_INSN_JRAL5;
@@ -8276,11 +8279,11 @@ special_convert_32_to_16 (unsigned long insn, uint16_t *pinsn16,
switch (N32_OP6 (insn))
{
case N32_OP6_LWI:
- if (N32_RA5 (insn) == REG_GP && IS_WITHIN_U (N32_IMM15S (insn), 7))
+ if (N32_RA5 (insn) == N32_REG_GP && IS_WITHIN_U (N32_IMM15S (insn), 7))
insn16 = N16_TYPE37 (XWI37, N32_RT5 (insn), 0, N32_IMM15S (insn));
break;
case N32_OP6_SWI:
- if (N32_RA5 (insn) == REG_GP && IS_WITHIN_U (N32_IMM15S (insn), 7))
+ if (N32_RA5 (insn) == N32_REG_GP && IS_WITHIN_U (N32_IMM15S (insn), 7))
insn16 = N16_TYPE37 (XWI37, N32_RT5 (insn), 1, N32_IMM15S (insn));
break;
case N32_OP6_HWGP:
@@ -8392,11 +8395,11 @@ bfd_elf_nds32_convert_16_to_32 (bfd *abfd, uint16_t insn16, uint32_t *pinsn)
N16_IMM3U (insn16));
goto done;
case 0x18: /* addri36.sp */
- insn = N32_TYPE2 (ADDI, N16_RT3 (insn16), REG_SP,
+ insn = N32_TYPE2 (ADDI, N16_RT3 (insn16), N32_REG_SP,
N16_IMM6U (insn16) << 2);
goto done;
case 0x19: /* lwi45.fe */
- insn = N32_TYPE2 (LWI, N16_RT4 (insn16), REG_R8,
+ insn = N32_TYPE2 (LWI, N16_RT4 (insn16), N32_REG_R8,
(N16_IMM5U (insn16) - 32));
goto done;
case 0x1a: /* lwi450 */
@@ -8408,22 +8411,24 @@ bfd_elf_nds32_convert_16_to_32 (bfd *abfd, uint16_t insn16, uint32_t *pinsn)
/* These are r15 implied instructions. */
case 0x30: /* slts45 */
- insn = N32_ALU1 (SLTS, REG_TA, N16_RT4 (insn16), N16_RA5 (insn16));
+ insn = N32_ALU1 (SLTS, N32_REG_TA, N16_RT4 (insn16), N16_RA5 (insn16));
goto done;
case 0x31: /* slt45 */
- insn = N32_ALU1 (SLT, REG_TA, N16_RT4 (insn16), N16_RA5 (insn16));
+ insn = N32_ALU1 (SLT, N32_REG_TA, N16_RT4 (insn16), N16_RA5 (insn16));
goto done;
case 0x32: /* sltsi45 */
- insn = N32_TYPE2 (SLTSI, REG_TA, N16_RT4 (insn16), N16_IMM5U (insn16));
+ insn = N32_TYPE2 (SLTSI, N32_REG_TA, N16_RT4 (insn16),
+ N16_IMM5U (insn16));
goto done;
case 0x33: /* slti45 */
- insn = N32_TYPE2 (SLTI, REG_TA, N16_RT4 (insn16), N16_IMM5U (insn16));
+ insn = N32_TYPE2 (SLTI, N32_REG_TA, N16_RT4 (insn16),
+ N16_IMM5U (insn16));
goto done;
case 0x34: /* beqzs8, bnezs8 */
if (insn16 & N32_BIT (8))
- insn = N32_BR2 (BNEZ, REG_TA, N16_IMM8S (insn16));
+ insn = N32_BR2 (BNEZ, N32_REG_TA, N16_IMM8S (insn16));
else
- insn = N32_BR2 (BEQZ, REG_TA, N16_IMM8S (insn16));
+ insn = N32_BR2 (BEQZ, N32_REG_TA, N16_IMM8S (insn16));
goto done;
case 0x35: /* break16, ex9.it */
@@ -8503,7 +8508,7 @@ bfd_elf_nds32_convert_16_to_32 (bfd *abfd, uint16_t insn16, uint32_t *pinsn)
switch (__GF (insn16, 10, 5))
{
case 0x0: /* mov55 or ifret16 */
- if (mach >= MACH_V3 && N16_RT5 (insn16) == REG_SP
+ if (mach >= MACH_V3 && N16_RT5 (insn16) == N32_REG_SP
&& N16_RT5 (insn16) == N16_RA5 (insn16))
insn = N32_JREG (JR, 0, 0, 0, 3);
else
@@ -8513,7 +8518,7 @@ bfd_elf_nds32_convert_16_to_32 (bfd *abfd, uint16_t insn16, uint32_t *pinsn)
insn = N32_TYPE1 (MOVI, N16_RT5 (insn16), N16_IMM5S (insn16));
goto done;
case 0x1b: /* addi10s (V2) */
- insn = N32_TYPE2 (ADDI, REG_SP, REG_SP, N16_IMM10S (insn16));
+ insn = N32_TYPE2 (ADDI, N32_REG_SP, N32_REG_SP, N16_IMM10S (insn16));
goto done;
}
@@ -8521,9 +8526,11 @@ bfd_elf_nds32_convert_16_to_32 (bfd *abfd, uint16_t insn16, uint32_t *pinsn)
{
case 0x7: /* lwi37.fp/swi37.fp */
if (insn16 & N32_BIT (7)) /* swi37.fp */
- insn = N32_TYPE2 (SWI, N16_RT38 (insn16), REG_FP, N16_IMM7U (insn16));
+ insn = N32_TYPE2 (SWI, N16_RT38 (insn16), N32_REG_FP,
+ N16_IMM7U (insn16));
else /* lwi37.fp */
- insn = N32_TYPE2 (LWI, N16_RT38 (insn16), REG_FP, N16_IMM7U (insn16));
+ insn = N32_TYPE2 (LWI, N16_RT38 (insn16), N32_REG_FP,
+ N16_IMM7U (insn16));
goto done;
case 0x8: /* beqz38 */
insn = N32_BR2 (BEQZ, N16_RT38 (insn16), N16_IMM8S (insn16));
@@ -8535,7 +8542,8 @@ bfd_elf_nds32_convert_16_to_32 (bfd *abfd, uint16_t insn16, uint32_t *pinsn)
if (N16_RT38 (insn16) == 5)
insn = N32_JI (J, N16_IMM8S (insn16));
else
- insn = N32_BR1 (BEQ, N16_RT38 (insn16), REG_R5, N16_IMM8S (insn16));
+ insn = N32_BR1 (BEQ, N16_RT38 (insn16), N32_REG_R5,
+ N16_IMM8S (insn16));
goto done;
case 0xb: /* bnes38 and others. */
if (N16_RT38 (insn16) == 5)
@@ -8549,7 +8557,7 @@ bfd_elf_nds32_convert_16_to_32 (bfd *abfd, uint16_t insn16, uint32_t *pinsn)
insn = N32_JREG (JR, 0, N16_RA5 (insn16), 0, 1);
break;
case 1: /* jral5 */
- insn = N32_JREG (JRAL, REG_LP, N16_RA5 (insn16), 0, 0);
+ insn = N32_JREG (JRAL, N32_REG_LP, N16_RA5 (insn16), 0, 0);
break;
case 2: /* ex9.it imm5 */
/* ex9.it had no 32-bit variantl. */
@@ -8560,13 +8568,16 @@ bfd_elf_nds32_convert_16_to_32 (bfd *abfd, uint16_t insn16, uint32_t *pinsn)
}
}
else /* bnes38 */
- insn = N32_BR1 (BNE, N16_RT38 (insn16), REG_R5, N16_IMM8S (insn16));
+ insn = N32_BR1 (BNE, N16_RT38 (insn16), N32_REG_R5,
+ N16_IMM8S (insn16));
goto done;
case 0xe: /* lwi37/swi37 */
if (insn16 & (1 << 7)) /* swi37.sp */
- insn = N32_TYPE2 (SWI, N16_RT38 (insn16), REG_SP, N16_IMM7U (insn16));
+ insn = N32_TYPE2 (SWI, N16_RT38 (insn16), N32_REG_SP,
+ N16_IMM7U (insn16));
else /* lwi37.sp */
- insn = N32_TYPE2 (LWI, N16_RT38 (insn16), REG_SP, N16_IMM7U (insn16));
+ insn = N32_TYPE2 (LWI, N16_RT38 (insn16), N32_REG_SP,
+ N16_IMM7U (insn16));
goto done;
}
@@ -8671,7 +8682,7 @@ turn_insn_to_sda_access (uint32_t insn, bfd_signed_vma type, uint32_t *pinsn)
case R_NDS32_LO12S2_DP_RELA:
case R_NDS32_LO12S2_SP_RELA:
- oinsn = (insn & 0x7ff07000) | (REG_GP << 15);
+ oinsn = (insn & 0x7ff07000) | (N32_REG_GP << 15);
break;
}
@@ -10134,7 +10145,7 @@ nds32_elf_convert_branch (uint16_t insn16, uint32_t insn,
{
/* beqs label. */
comp_insn = (insn ^ 0x4000) & 0xffffc000;
- if (N32_IS_RT3 (insn) && N32_RA5 (insn) == REG_R5)
+ if (N32_IS_RT3 (insn) && N32_RA5 (insn) == N32_REG_R5)
{
/* Insn can be contracted to 16-bit implied r5. */
comp_insn16 =
@@ -10160,7 +10171,7 @@ nds32_elf_convert_branch (uint16_t insn16, uint32_t insn,
(comp_insn & 0x10000) ? INSN_BNEZ38 : INSN_BEQZ38;
comp_insn16 |= (N32_RT5 (insn) & 0x7) << 8;
}
- else if (N32_RT5 (insn) == REG_R15)
+ else if (N32_RT5 (insn) == N32_REG_R15)
{
/* Insn can be contracted to 16-bit. */
comp_insn16 =
@@ -10185,14 +10196,14 @@ nds32_elf_convert_branch (uint16_t insn16, uint32_t insn,
comp_insn16 = (insn16 ^ 0x0800) & 0xff00;
comp_insn = (comp_insn16 & 0x0800) ? INSN_BNE : INSN_BEQ;
comp_insn |= (((comp_insn16 & 0x0700) >> 8) << 20)
- | (REG_R5 << 15);
+ | (N32_REG_R5 << 15);
break;
case 0xe:
/* beqzS8 or bnezS8 */
comp_insn16 = (insn16 ^ 0x0100) & 0xff00;
comp_insn = (comp_insn16 & 0x0100) ? INSN_BNEZ : INSN_BEQZ;
- comp_insn |= REG_R15 << 20;
+ comp_insn |= N32_REG_R15 << 20;
break;
default:
@@ -11629,7 +11640,7 @@ nds32_elf_relax_loadstore (struct bfd_link_info *link_info, bfd *abfd,
return false;
/* Case for set gp register. */
- if (N32_RT5 (insn) == REG_GP)
+ if (N32_RT5 (insn) == N32_REG_GP)
return false;
if (range_type == NDS32_LOADSTORE_FLOAT_S
@@ -11754,7 +11765,7 @@ nds32_elf_relax_lo12 (struct bfd_link_info *link_info, bfd *abfd,
|| (local_sda > access_addr && (local_sda - access_addr) <= range_l)
|| (h && strcmp (h->root.root.string, FP_BASE_NAME) == 0))
{
- if (N32_OP6 (insn) == N32_OP6_ORI && N32_RT5 (insn) == REG_GP)
+ if (N32_OP6 (insn) == N32_OP6_ORI && N32_RT5 (insn) == N32_REG_GP)
{
/* Maybe we should add R_NDS32_INSN16 reloc type here
or manually do some optimization. sethi can't be
@@ -11897,7 +11908,7 @@ nds32_elf_relax_flsi (struct bfd_link_info *link_info, bfd *abfd,
|| (local_sda > access_addr && (local_sda - access_addr) <= range_l))
{
/* Turn flsi instruction into sda access format. */
- insn = (insn & 0x7ff07000) | (REG_GP << 15);
+ insn = (insn & 0x7ff07000) | (N32_REG_GP << 15);
/* Add relocation type to flsi. */
irel->r_info = ELF32_R_INFO (ELF32_R_SYM (irel->r_info), reloc);
@@ -13739,8 +13750,8 @@ nds32_elf_unify_tls_model (bfd *inbfd, asection *insec, bfd_byte *incontents,
break;
case R_NDS32_TLS_DESC_CALL:
{
- uint32_t insn = N32_ALU1(ADD, REG_R0, add_rt,
- REG_TP);
+ uint32_t insn = N32_ALU1(ADD, N32_REG_R0, add_rt,
+ N32_REG_TP);
bfd_putb32 (insn, contents + irel->r_offset);
irel->r_info = ELF32_R_INFO(r_symndx, R_NDS32_NONE);
@@ -13772,7 +13783,8 @@ nds32_elf_unify_tls_model (bfd *inbfd, asection *insec, bfd_byte *incontents,
{
uint32_t insn = bfd_getb32 (contents + irel->r_offset);
add_rt = N32_RT5 (insn);
- insn = N32_MEM(LW, add_rt, sethi_rt, REG_GP, 0);
+ insn = N32_MEM(LW, add_rt, sethi_rt,
+ N32_REG_GP, 0);
bfd_putb32 (insn, contents + irel->r_offset);
irel->r_info = ELF32_R_INFO(r_symndx, R_NDS32_NONE);
@@ -13785,8 +13797,8 @@ nds32_elf_unify_tls_model (bfd *inbfd, asection *insec, bfd_byte *incontents,
break;
case R_NDS32_TLS_DESC_CALL:
{
- uint32_t insn = N32_ALU1(ADD, REG_R0, add_rt,
- REG_TP);
+ uint32_t insn = N32_ALU1(ADD, N32_REG_R0, add_rt,
+ N32_REG_TP);
bfd_putb32 (insn, contents + irel->r_offset);
irel->r_info = ELF32_R_INFO(r_symndx, R_NDS32_NONE);
@@ -13817,7 +13829,8 @@ nds32_elf_unify_tls_model (bfd *inbfd, asection *insec, bfd_byte *incontents,
uint32_t insn = bfd_getb32 (contents + irel->r_offset);
add_rt = N32_RT5 (insn);
- insn = N32_ALU1 (ADD, REG_R0, sethi_rt, REG_TP);
+ insn = N32_ALU1 (ADD, N32_REG_R0, sethi_rt,
+ N32_REG_TP);
bfd_putb32 (insn, contents + irel->r_offset);
irel->r_info = ELF32_R_INFO (r_symndx, R_NDS32_TLS_LE_ADD);
diff --git a/gas/config/tc-cris.c b/gas/config/tc-cris.c
index 7dce7004e169..24055f69cb91 100644
--- a/gas/config/tc-cris.c
+++ b/gas/config/tc-cris.c
@@ -1306,7 +1306,7 @@ md_assemble (char *str)
/* General register. */
opcodep[0] = -4;
}
- opcodep[1] = (REG_SP << 4) + (BDAP_QUICK_OPCODE >> 8);
+ opcodep[1] = (CRIS_REG_SP << 4) + (BDAP_QUICK_OPCODE >> 8);
break;
default:
@@ -2381,7 +2381,7 @@ get_gen_reg (char **cPP, int *regnop)
{
/* It's "PC": consume the "c" and we're done. */
(*cPP)++;
- *regnop = REG_PC;
+ *regnop = CRIS_REG_PC;
return 1;
}
break;
@@ -2441,7 +2441,7 @@ get_gen_reg (char **cPP, int *regnop)
{
/* It's "SP": consume the "p" and we're done. */
(*cPP)++;
- *regnop = REG_SP;
+ *regnop = CRIS_REG_SP;
return 1;
}
break;
@@ -2750,7 +2750,7 @@ get_autoinc_prefix_or_indir_op (char **cPP, struct cris_prefix *prefixp,
| (prefixp->base_reg_number << 12)
| (AUTOINCR_BIT << 8)
| (2 << 4)
- | REG_PC /* << 0 */);
+ | CRIS_REG_PC /* << 0 */);
/* This can have a PIC suffix, specifying reloc
type to use. */
@@ -2826,7 +2826,7 @@ get_autoinc_prefix_or_indir_op (char **cPP, struct cris_prefix *prefixp,
/* Expression found, this is immediate mode. */
prefixp->kind = PREFIX_NONE;
*is_autoincp = 1;
- *src_regnop = REG_PC;
+ *src_regnop = CRIS_REG_PC;
*imm_foundp = 1;
/* This can have a PIC suffix, specifying reloc type to use. The
@@ -2997,7 +2997,7 @@ get_3op_or_dip_prefix_op (char **cPP, struct cris_prefix *prefixp)
| (prefixp->base_reg_number << 12)
| (AUTOINCR_BIT << 8)
| (2 << 4)
- | REG_PC /* << 0 */);
+ | CRIS_REG_PC /* << 0 */);
/* This can have a PIC suffix, specifying reloc type to use. */
if ((pic || tls) && **cPP == RELOC_SUFFIX_CHAR)
@@ -3062,7 +3062,7 @@ get_3op_or_dip_prefix_op (char **cPP, struct cris_prefix *prefixp)
/* Expression found, the so called absolute mode for a
double-indirect prefix on PC. */
prefixp->kind = PREFIX_DIP;
- prefixp->opcode = DIP_OPCODE | (AUTOINCR_BIT << 8) | REG_PC;
+ prefixp->opcode = DIP_OPCODE | (AUTOINCR_BIT << 8) | CRIS_REG_PC;
prefixp->reloc = BFD_RELOC_32;
/* For :GD and :IE, it makes sense to have TLS specifiers here. */
diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c
index 42ce97b3fd8e..3e3dca819218 100644
--- a/gas/config/tc-microblaze.c
+++ b/gas/config/tc-microblaze.c
@@ -407,68 +407,68 @@ parse_reg (char * s, unsigned * reg)
if (strncasecmp (s, "rpc", 3) == 0)
{
- *reg = REG_PC;
+ *reg = MICROBLAZE_REG_PC;
return s + 3;
}
else if (strncasecmp (s, "rmsr", 4) == 0)
{
- *reg = REG_MSR;
+ *reg = MICROBLAZE_REG_MSR;
return s + 4;
}
else if (strncasecmp (s, "rear", 4) == 0)
{
- *reg = REG_EAR;
+ *reg = MICROBLAZE_REG_EAR;
return s + 4;
}
else if (strncasecmp (s, "resr", 4) == 0)
{
- *reg = REG_ESR;
+ *reg = MICROBLAZE_REG_ESR;
return s + 4;
}
else if (strncasecmp (s, "rfsr", 4) == 0)
{
- *reg = REG_FSR;
+ *reg = MICROBLAZE_REG_FSR;
return s + 4;
}
else if (strncasecmp (s, "rbtr", 4) == 0)
{
- *reg = REG_BTR;
+ *reg = MICROBLAZE_REG_BTR;
return s + 4;
}
else if (strncasecmp (s, "redr", 4) == 0)
{
- *reg = REG_EDR;
+ *reg = MICROBLAZE_REG_EDR;
return s + 4;
}
/* MMU registers start. */
else if (strncasecmp (s, "rpid", 4) == 0)
{
- *reg = REG_PID;
+ *reg = MICROBLAZE_REG_PID;
return s + 4;
}
else if (strncasecmp (s, "rzpr", 4) == 0)
{
- *reg = REG_ZPR;
+ *reg = MICROBLAZE_REG_ZPR;
return s + 4;
}
else if (strncasecmp (s, "rtlbx", 5) == 0)
{
- *reg = REG_TLBX;
+ *reg = MICROBLAZE_REG_TLBX;
return s + 5;
}
else if (strncasecmp (s, "rtlblo", 6) == 0)
{
- *reg = REG_TLBLO;
+ *reg = MICROBLAZE_REG_TLBLO;
return s + 6;
}
else if (strncasecmp (s, "rtlbhi", 6) == 0)
{
- *reg = REG_TLBHI;
+ *reg = MICROBLAZE_REG_TLBHI;
return s + 6;
}
else if (strncasecmp (s, "rtlbsx", 6) == 0)
{
- *reg = REG_TLBSX;
+ *reg = MICROBLAZE_REG_TLBSX;
return s + 6;
}
/* MMU registers end. */
@@ -488,17 +488,17 @@ parse_reg (char * s, unsigned * reg)
else
as_bad (_("register expected, but saw '%.6s'"), s);
if (tmpreg - MIN_PVR_REGNUM <= MAX_PVR_REGNUM - MIN_PVR_REGNUM)
- *reg = REG_PVR + tmpreg;
+ *reg = MICROBLAZE_REG_PVR + tmpreg;
else
{
as_bad (_("Invalid register number at '%.6s'"), s);
- *reg = REG_PVR;
+ *reg = MICROBLAZE_REG_PVR;
}
return s;
}
else if (strncasecmp (s, "rsp", 3) == 0)
{
- *reg = REG_SP;
+ *reg = MICROBLAZE_REG_SP;
return s + 3;
}
else if (strncasecmp (s, "rfsl", 4) == 0)
@@ -528,12 +528,12 @@ parse_reg (char * s, unsigned * reg)
/* Stack protection registers. */
else if (strncasecmp (s, "rshr", 4) == 0)
{
- *reg = REG_SHR;
+ *reg = MICROBLAZE_REG_SHR;
return s + 4;
}
else if (strncasecmp (s, "rslr", 4) == 0)
{
- *reg = REG_SLR;
+ *reg = MICROBLAZE_REG_SLR;
return s + 4;
}
else
@@ -835,14 +835,16 @@ static const char * str_microblaze_rw_anchor = "RW";
static bool
check_spl_reg (unsigned * reg)
{
- if ((*reg == REG_MSR) || (*reg == REG_PC)
- || (*reg == REG_EAR) || (*reg == REG_ESR)
- || (*reg == REG_FSR) || (*reg == REG_BTR) || (*reg == REG_EDR)
- || (*reg == REG_PID) || (*reg == REG_ZPR)
- || (*reg == REG_TLBX) || (*reg == REG_TLBLO)
- || (*reg == REG_TLBHI) || (*reg == REG_TLBSX)
- || (*reg == REG_SHR) || (*reg == REG_SLR)
- || (*reg >= REG_PVR+MIN_PVR_REGNUM && *reg <= REG_PVR+MAX_PVR_REGNUM))
+ if ((*reg == MICROBLAZE_REG_MSR) || (*reg == MICROBLAZE_REG_PC)
+ || (*reg == MICROBLAZE_REG_EAR) || (*reg == MICROBLAZE_REG_ESR)
+ || (*reg == MICROBLAZE_REG_FSR) || (*reg == MICROBLAZE_REG_BTR)
+ || (*reg == MICROBLAZE_REG_EDR)
+ || (*reg == MICROBLAZE_REG_PID) || (*reg == MICROBLAZE_REG_ZPR)
+ || (*reg == MICROBLAZE_REG_TLBX) || (*reg == MICROBLAZE_REG_TLBLO)
+ || (*reg == MICROBLAZE_REG_TLBHI) || (*reg == MICROBLAZE_REG_TLBSX)
+ || (*reg == MICROBLAZE_REG_SHR) || (*reg == MICROBLAZE_REG_SLR)
+ || (*reg >= MICROBLAZE_REG_PVR+MIN_PVR_REGNUM
+ && *reg <= MICROBLAZE_REG_PVR+MAX_PVR_REGNUM))
return true;
return false;
@@ -1011,9 +1013,9 @@ md_assemble (char * str)
else if (streq (name, "smi"))
as_fatal (_("smi pseudo instruction should not use a label in imm field"));
- if (reg2 == REG_ROSDP)
+ if (reg2 == MICROBLAZE_REG_ROSDP)
opc = str_microblaze_ro_anchor;
- else if (reg2 == REG_RWSDP)
+ else if (reg2 == MICROBLAZE_REG_RWSDP)
opc = str_microblaze_rw_anchor;
else
opc = NULL;
@@ -1422,36 +1424,37 @@ md_assemble (char * str)
reg2 = 0;
}
- if (reg2 == REG_MSR)
- immed = opcode->immval_mask | REG_MSR_MASK;
- else if (reg2 == REG_PC)
- immed = opcode->immval_mask | REG_PC_MASK;
- else if (reg2 == REG_EAR)
- immed = opcode->immval_mask | REG_EAR_MASK;
- else if (reg2 == REG_ESR)
- immed = opcode->immval_mask | REG_ESR_MASK;
- else if (reg2 == REG_FSR)
- immed = opcode->immval_mask | REG_FSR_MASK;
- else if (reg2 == REG_BTR)
- immed = opcode->immval_mask | REG_BTR_MASK;
- else if (reg2 == REG_EDR)
- immed = opcode->immval_mask | REG_EDR_MASK;
- else if (reg2 == REG_PID)
- immed = opcode->immval_mask | REG_PID_MASK;
- else if (reg2 == REG_ZPR)
- immed = opcode->immval_mask | REG_ZPR_MASK;
- else if (reg2 == REG_TLBX)
- immed = opcode->immval_mask | REG_TLBX_MASK;
- else if (reg2 == REG_TLBLO)
- immed = opcode->immval_mask | REG_TLBLO_MASK;
- else if (reg2 == REG_TLBHI)
- immed = opcode->immval_mask | REG_TLBHI_MASK;
- else if (reg2 == REG_SHR)
- immed = opcode->immval_mask | REG_SHR_MASK;
- else if (reg2 == REG_SLR)
- immed = opcode->immval_mask | REG_SLR_MASK;
- else if (reg2 >= (REG_PVR+MIN_PVR_REGNUM) && reg2 <= (REG_PVR+MAX_PVR_REGNUM))
- immed = opcode->immval_mask | REG_PVR_MASK | reg2;
+ if (reg2 == MICROBLAZE_REG_MSR)
+ immed = opcode->immval_mask | MICROBLAZE_REG_MSR_MASK;
+ else if (reg2 == MICROBLAZE_REG_PC)
+ immed = opcode->immval_mask | MICROBLAZE_REG_PC_MASK;
+ else if (reg2 == MICROBLAZE_REG_EAR)
+ immed = opcode->immval_mask | MICROBLAZE_REG_EAR_MASK;
+ else if (reg2 == MICROBLAZE_REG_ESR)
+ immed = opcode->immval_mask | MICROBLAZE_REG_ESR_MASK;
+ else if (reg2 == MICROBLAZE_REG_FSR)
+ immed = opcode->immval_mask | MICROBLAZE_REG_FSR_MASK;
+ else if (reg2 == MICROBLAZE_REG_BTR)
+ immed = opcode->immval_mask | MICROBLAZE_REG_BTR_MASK;
+ else if (reg2 == MICROBLAZE_REG_EDR)
+ immed = opcode->immval_mask | MICROBLAZE_REG_EDR_MASK;
+ else if (reg2 == MICROBLAZE_REG_PID)
+ immed = opcode->immval_mask | MICROBLAZE_REG_PID_MASK;
+ else if (reg2 == MICROBLAZE_REG_ZPR)
+ immed = opcode->immval_mask | MICROBLAZE_REG_ZPR_MASK;
+ else if (reg2 == MICROBLAZE_REG_TLBX)
+ immed = opcode->immval_mask | MICROBLAZE_REG_TLBX_MASK;
+ else if (reg2 == MICROBLAZE_REG_TLBLO)
+ immed = opcode->immval_mask | MICROBLAZE_REG_TLBLO_MASK;
+ else if (reg2 == MICROBLAZE_REG_TLBHI)
+ immed = opcode->immval_mask | MICROBLAZE_REG_TLBHI_MASK;
+ else if (reg2 == MICROBLAZE_REG_SHR)
+ immed = opcode->immval_mask | MICROBLAZE_REG_SHR_MASK;
+ else if (reg2 == MICROBLAZE_REG_SLR)
+ immed = opcode->immval_mask | MICROBLAZE_REG_SLR_MASK;
+ else if (reg2 >= (MICROBLAZE_REG_PVR+MIN_PVR_REGNUM)
+ && reg2 <= (MICROBLAZE_REG_PVR+MAX_PVR_REGNUM))
+ immed = opcode->immval_mask | MICROBLAZE_REG_PVR_MASK | reg2;
else
as_fatal (_("invalid value for special purpose register"));
inst |= (reg1 << RD_LOW) & RD_MASK;
@@ -1475,36 +1478,36 @@ md_assemble (char * str)
reg2 = 0;
}
- if (reg1 == REG_MSR)
- immed = opcode->immval_mask | REG_MSR_MASK;
- else if (reg1 == REG_PC)
- immed = opcode->immval_mask | REG_PC_MASK;
- else if (reg1 == REG_EAR)
- immed = opcode->immval_mask | REG_EAR_MASK;
- else if (reg1 == REG_ESR)
- immed = opcode->immval_mask | REG_ESR_MASK;
- else if (reg1 == REG_FSR)
- immed = opcode->immval_mask | REG_FSR_MASK;
- else if (reg1 == REG_BTR)
- immed = opcode->immval_mask | REG_BTR_MASK;
- else if (reg1 == REG_EDR)
- immed = opcode->immval_mask | REG_EDR_MASK;
- else if (reg1 == REG_PID)
- immed = opcode->immval_mask | REG_PID_MASK;
- else if (reg1 == REG_ZPR)
- immed = opcode->immval_mask | REG_ZPR_MASK;
- else if (reg1 == REG_TLBX)
- immed = opcode->immval_mask | REG_TLBX_MASK;
- else if (reg1 == REG_TLBLO)
- immed = opcode->immval_mask | REG_TLBLO_MASK;
- else if (reg1 == REG_TLBHI)
- immed = opcode->immval_mask | REG_TLBHI_MASK;
- else if (reg1 == REG_TLBSX)
- immed = opcode->immval_mask | REG_TLBSX_MASK;
- else if (reg1 == REG_SHR)
- immed = opcode->immval_mask | REG_SHR_MASK;
- else if (reg1 == REG_SLR)
- immed = opcode->immval_mask | REG_SLR_MASK;
+ if (reg1 == MICROBLAZE_REG_MSR)
+ immed = opcode->immval_mask | MICROBLAZE_REG_MSR_MASK;
+ else if (reg1 == MICROBLAZE_REG_PC)
+ immed = opcode->immval_mask | MICROBLAZE_REG_PC_MASK;
+ else if (reg1 == MICROBLAZE_REG_EAR)
+ immed = opcode->immval_mask | MICROBLAZE_REG_EAR_MASK;
+ else if (reg1 == MICROBLAZE_REG_ESR)
+ immed = opcode->immval_mask | MICROBLAZE_REG_ESR_MASK;
+ else if (reg1 == MICROBLAZE_REG_FSR)
+ immed = opcode->immval_mask | MICROBLAZE_REG_FSR_MASK;
+ else if (reg1 == MICROBLAZE_REG_BTR)
+ immed = opcode->immval_mask | MICROBLAZE_REG_BTR_MASK;
+ else if (reg1 == MICROBLAZE_REG_EDR)
+ immed = opcode->immval_mask | MICROBLAZE_REG_EDR_MASK;
+ else if (reg1 == MICROBLAZE_REG_PID)
+ immed = opcode->immval_mask | MICROBLAZE_REG_PID_MASK;
+ else if (reg1 == MICROBLAZE_REG_ZPR)
+ immed = opcode->immval_mask | MICROBLAZE_REG_ZPR_MASK;
+ else if (reg1 == MICROBLAZE_REG_TLBX)
+ immed = opcode->immval_mask | MICROBLAZE_REG_TLBX_MASK;
+ else if (reg1 == MICROBLAZE_REG_TLBLO)
+ immed = opcode->immval_mask | MICROBLAZE_REG_TLBLO_MASK;
+ else if (reg1 == MICROBLAZE_REG_TLBHI)
+ immed = opcode->immval_mask | MICROBLAZE_REG_TLBHI_MASK;
+ else if (reg1 == MICROBLAZE_REG_TLBSX)
+ immed = opcode->immval_mask | MICROBLAZE_REG_TLBSX_MASK;
+ else if (reg1 == MICROBLAZE_REG_SHR)
+ immed = opcode->immval_mask | MICROBLAZE_REG_SHR_MASK;
+ else if (reg1 == MICROBLAZE_REG_SLR)
+ immed = opcode->immval_mask | MICROBLAZE_REG_SLR_MASK;
else
as_fatal (_("invalid value for special purpose register"));
inst |= (reg2 << RA_LOW) & RA_MASK;
diff --git a/gas/config/tc-nds32.c b/gas/config/tc-nds32.c
index 12a77eb607b8..b155af8d41b6 100644
--- a/gas/config/tc-nds32.c
+++ b/gas/config/tc-nds32.c
@@ -6130,8 +6130,8 @@ nds32_elf_append_relax_relocs (const char *key, const void *value)
/* Extra to NDS32_SYM. */
/* Detect if DESC_FUNC relax type do apply. */
- if ((REG_GP == N32_RA5 (pattern_now->insn))
- || (REG_GP == N32_RB5 (pattern_now->insn)))
+ if ((N32_REG_GP == N32_RA5 (pattern_now->insn))
+ || (N32_REG_GP == N32_RB5 (pattern_now->insn)))
{
fixP = fix_new_exp (fragP, where - fragP->fr_literal,
fixup_size, &exp, pcrel,
diff --git a/gdb/cris-tdep.c b/gdb/cris-tdep.c
index 593c4f1e5287..68f4698b1046 100644
--- a/gdb/cris-tdep.c
+++ b/gdb/cris-tdep.c
@@ -2095,10 +2095,8 @@ process_autoincrement (int size, unsigned short inst, inst_env_type *inst_env)
/* The PC must be word aligned, so increase the PC with one
word even if the size is byte. */
- if (cris_get_operand1 (inst) == REG_PC)
- {
- inst_env->reg[REG_PC] += 1;
- }
+ if (cris_get_operand1 (inst) == CRIS_REG_PC)
+ inst_env->reg[CRIS_REG_PC] += 1;
}
else if (size == INST_WORD_SIZE)
{
@@ -2179,10 +2177,8 @@ biap_prefix (unsigned short inst, inst_env_type *inst_env)
/* If the PC is operand1 (base) the address used is the address after
the main instruction, i.e. address + 2 (the PC is already compensated
for the prefix operation). */
- if (cris_get_operand1 (inst) == REG_PC)
- {
- inst_env->prefix_value += 2;
- }
+ if (cris_get_operand1 (inst) == CRIS_REG_PC)
+ inst_env->prefix_value += 2;
/* A prefix doesn't change the xflag_found. But the rest of the flags
need updating. */
@@ -2254,7 +2250,7 @@ eight_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
offset &= ~BRANCH_SIGNED_SHORT_OFFSET_MASK;
inst_env->branch_found = 1;
- inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
+ inst_env->branch_break_address = inst_env->reg[CRIS_REG_PC] + offset;
inst_env->slot_needed = 1;
inst_env->prefix_found = 0;
@@ -2277,15 +2273,15 @@ sixteen_bit_offset_branch_op (unsigned short inst, inst_env_type *inst_env)
}
/* We have a branch, find out the offset for the branch. */
- offset = read_memory_integer (inst_env->reg[REG_PC], 2,
+ offset = read_memory_integer (inst_env->reg[CRIS_REG_PC], 2,
inst_env->byte_order);
/* The instruction is one word longer than normal, so add one word
to the PC. */
- inst_env->reg[REG_PC] += 2;
+ inst_env->reg[CRIS_REG_PC] += 2;
inst_env->branch_found = 1;
- inst_env->branch_break_address = inst_env->reg[REG_PC] + offset;
+ inst_env->branch_break_address = inst_env->reg[CRIS_REG_PC] + offset;
inst_env->slot_needed = 1;
@@ -2310,7 +2306,7 @@ abs_op (unsigned short inst, inst_env_type *inst_env)
}
/* Check if the operation affects the PC. */
- if (cris_get_operand2 (inst) == REG_PC)
+ if (cris_get_operand2 (inst) == CRIS_REG_PC)
{
/* It's invalid to change to the PC if we are in a delay slot. */
@@ -2320,13 +2316,13 @@ abs_op (unsigned short inst, inst_env_type *inst_env)
return;
}
- value = (long) inst_env->reg[REG_PC];
+ value = (long) inst_env->reg[CRIS_REG_PC];
/* The value of abs (SIGNED_DWORD_MASK) is SIGNED_DWORD_MASK. */
if (value != SIGNED_DWORD_MASK)
{
value = -value;
- inst_env->reg[REG_PC] = (long) value;
+ inst_env->reg[CRIS_REG_PC] = (long) value;
}
}
@@ -2343,7 +2339,7 @@ addi_op (unsigned short inst, inst_env_type *inst_env)
{
/* It's invalid to have the PC as base register. And ADDI can't have
a prefix. */
- if (inst_env->prefix_found || (cris_get_operand1 (inst) == REG_PC))
+ if (inst_env->prefix_found || (cris_get_operand1 (inst) == CRIS_REG_PC))
{
inst_env->invalid = 1;
return;
@@ -2372,7 +2368,7 @@ asr_op (unsigned short inst, inst_env_type *inst_env)
}
/* Check if the PC is the target register. */
- if (cris_get_operand2 (inst) == REG_PC)
+ if (cris_get_operand2 (inst) == CRIS_REG_PC)
{
/* It's invalid to change the PC in a delay slot. */
if (inst_env->slot_needed)
@@ -2383,7 +2379,7 @@ asr_op (unsigned short inst, inst_env_type *inst_env)
/* Get the number of bits to shift. */
shift_steps
= cris_get_asr_shift_steps (inst_env->reg[cris_get_operand1 (inst)]);
- value = inst_env->reg[REG_PC];
+ value = inst_env->reg[CRIS_REG_PC];
/* Find out how many bits the operation should apply to. */
if (cris_get_size (inst) == INST_BYTE_SIZE)
@@ -2397,8 +2393,8 @@ asr_op (unsigned short inst, inst_env_type *inst_env)
value = value >> shift_steps;
value |= signed_extend_mask;
value &= 0xFF;
- inst_env->reg[REG_PC] &= 0xFFFFFF00;
- inst_env->reg[REG_PC] |= value;
+ inst_env->reg[CRIS_REG_PC] &= 0xFFFFFF00;
+ inst_env->reg[CRIS_REG_PC] |= value;
}
else if (cris_get_size (inst) == INST_WORD_SIZE)
{
@@ -2411,8 +2407,8 @@ asr_op (unsigned short inst, inst_env_type *inst_env)
value = value >> shift_steps;
value |= signed_extend_mask;
value &= 0xFFFF;
- inst_env->reg[REG_PC] &= 0xFFFF0000;
- inst_env->reg[REG_PC] |= value;
+ inst_env->reg[CRIS_REG_PC] &= 0xFFFF0000;
+ inst_env->reg[CRIS_REG_PC] |= value;
}
else if (cris_get_size (inst) == INST_DWORD_SIZE)
{
@@ -2424,7 +2420,7 @@ asr_op (unsigned short inst, inst_env_type *inst_env)
}
value = value >> shift_steps;
value |= signed_extend_mask;
- inst_env->reg[REG_PC] = value;
+ inst_env->reg[CRIS_REG_PC] = value;
}
}
inst_env->slot_needed = 0;
@@ -2451,7 +2447,7 @@ asrq_op (unsigned short inst, inst_env_type *inst_env)
}
/* Check if the PC is the target register. */
- if (cris_get_operand2 (inst) == REG_PC)
+ if (cris_get_operand2 (inst) == CRIS_REG_PC)
{
/* It's invalid to change the PC in a delay slot. */
@@ -2463,7 +2459,7 @@ asrq_op (unsigned short inst, inst_env_type *inst_env)
/* The shift size is given as a 5 bit quick value, i.e. we don't
want the sign bit of the quick value. */
shift_steps = cris_get_asr_shift_steps (inst);
- value = inst_env->reg[REG_PC];
+ value = inst_env->reg[CRIS_REG_PC];
if (value & SIGNED_DWORD_MASK)
{
signed_extend_mask = 0xFFFFFFFF;
@@ -2472,7 +2468,7 @@ asrq_op (unsigned short inst, inst_env_type *inst_env)
}
value = value >> shift_steps;
value |= signed_extend_mask;
- inst_env->reg[REG_PC] = value;
+ inst_env->reg[CRIS_REG_PC] = value;
}
inst_env->slot_needed = 0;
inst_env->prefix_found = 0;
@@ -2525,7 +2521,7 @@ static void
two_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
{
/* It's invalid to have the PC as the index operand. */
- if (cris_get_operand2 (inst) == REG_PC)
+ if (cris_get_operand2 (inst) == CRIS_REG_PC)
{
inst_env->invalid = 1;
return;
@@ -2559,7 +2555,7 @@ three_operand_bound_op (unsigned short inst, inst_env_type *inst_env)
{
/* It's an error if we haven't got a prefix. And it's also an error
if the PC is the destination register. */
- if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == REG_PC))
+ if ((!inst_env->prefix_found) || (cris_get_operand1 (inst) == CRIS_REG_PC))
{
inst_env->invalid = 1;
return;
@@ -2612,22 +2608,19 @@ static void
reg_mode_clear_op (unsigned short inst, inst_env_type *inst_env)
{
/* Check if the target is the PC. */
- if (cris_get_operand2 (inst) == REG_PC)
+ if (cris_get_operand2 (inst) == CRIS_REG_PC)
{
/* The instruction will clear the instruction's size bits. */
int clear_size = cris_get_clear_size (inst);
if (clear_size == INST_BYTE_SIZE)
- {
- inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFFFF00;
- }
+ inst_env->delay_slot_pc = inst_env->reg[CRIS_REG_PC] & 0xFFFFFF00;
+
if (clear_size == INST_WORD_SIZE)
- {
- inst_env->delay_slot_pc = inst_env->reg[REG_PC] & 0xFFFF0000;
- }
+ inst_env->delay_slot_pc = inst_env->reg[CRIS_REG_PC] & 0xFFFF0000;
+
if (clear_size == INST_DWORD_SIZE)
- {
- inst_env->delay_slot_pc = 0x0;
- }
+ inst_env->delay_slot_pc = 0x0;
+
/* The jump will be delayed with one delay slot. So we need a delay
slot. */
inst_env->slot_needed = 1;
@@ -2694,7 +2687,7 @@ dstep_logshift_mstep_neg_not_op (unsigned short inst, inst_env_type *inst_env)
{
/* It's invalid to have the PC as the destination. The instruction can't
have a prefix. */
- if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
+ if ((cris_get_operand2 (inst) == CRIS_REG_PC) || inst_env->prefix_found)
{
inst_env->invalid = 1;
return;
@@ -2732,7 +2725,7 @@ scc_op (unsigned short inst, inst_env_type *inst_env)
{
/* It's invalid to have the PC as the destination. The instruction can't
have a prefix. */
- if ((cris_get_operand2 (inst) == REG_PC) || inst_env->prefix_found)
+ if ((cris_get_operand2 (inst) == CRIS_REG_PC) || inst_env->prefix_found)
{
inst_env->invalid = 1;
return;
@@ -2758,7 +2751,7 @@ reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
}
/* Just change the PC. */
- inst_env->reg[REG_PC] = inst_env->reg[cris_get_operand1 (inst)];
+ inst_env->reg[CRIS_REG_PC] = inst_env->reg[cris_get_operand1 (inst)];
inst_env->slot_needed = 0;
inst_env->prefix_found = 0;
inst_env->xflag_found = 0;
@@ -2803,7 +2796,7 @@ none_reg_mode_jump_op (unsigned short inst, inst_env_type *inst_env)
inst_env->reg[cris_get_operand1 (inst)] += 4;
}
}
- inst_env->reg[REG_PC] = newpc;
+ inst_env->reg[CRIS_REG_PC] = newpc;
}
inst_env->slot_needed = 0;
inst_env->prefix_found = 0;
@@ -2824,7 +2817,7 @@ move_to_preg_op (struct gdbarch *gdbarch, unsigned short inst,
if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
{
/* The prefix handles the problem if we are in a delay slot. */
- if (cris_get_operand1 (inst) == REG_PC)
+ if (cris_get_operand1 (inst) == CRIS_REG_PC)
{
/* Just take care of the assign. */
check_assign (inst, inst_env);
@@ -2835,7 +2828,7 @@ move_to_preg_op (struct gdbarch *gdbarch, unsigned short inst,
{
/* The instruction doesn't have a prefix, the only case left that we
are interested in is the autoincrement mode. */
- if (cris_get_operand1 (inst) == REG_PC)
+ if (cris_get_operand1 (inst) == CRIS_REG_PC)
{
/* If the PC is to be incremented it's invalid to be in a
delay slot. */
@@ -2880,7 +2873,7 @@ none_reg_mode_move_from_preg_op (struct gdbarch *gdbarch, unsigned short inst,
if (cris_get_mode (inst) == PREFIX_ASSIGN_MODE)
{
/* The prefix handles the problem if we are in a delay slot. */
- if (cris_get_operand1 (inst) == REG_PC)
+ if (cris_get_operand1 (inst) == CRIS_REG_PC)
{
/* Just take care of the assign. */
check_assign (inst, inst_env);
@@ -2891,7 +2884,7 @@ none_reg_mode_move_from_preg_op (struct gdbarch *gdbarch, unsigned short inst,
are interested in is the autoincrement mode. */
else if (cris_get_mode (inst) == AUTOINC_MODE)
{
- if (cris_get_operand1 (inst) == REG_PC)
+ if (cris_get_operand1 (inst) == CRIS_REG_PC)
{
/* If the PC is to be incremented it's invalid to be in a
delay slot. */
@@ -2935,7 +2928,7 @@ reg_mode_move_from_preg_op (unsigned short inst, inst_env_type *inst_env)
return;
}
- if (cris_get_operand1 (inst) == REG_PC)
+ if (cris_get_operand1 (inst) == CRIS_REG_PC)
{
/* It's invalid to change the PC in a delay slot. */
if (inst_env->slot_needed)
@@ -2967,25 +2960,25 @@ move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env)
{
/* The prefix handles the problem if we are in a delay slot. Is the
MOVEM instruction going to change the PC? */
- if (cris_get_operand2 (inst) >= REG_PC)
+ if (cris_get_operand2 (inst) >= CRIS_REG_PC)
{
- inst_env->reg[REG_PC] =
+ inst_env->reg[CRIS_REG_PC] =
read_memory_unsigned_integer (inst_env->prefix_value,
4, inst_env->byte_order);
}
/* The assign value is the value after the increment. Normally, the
assign value is the value before the increment. */
- if ((cris_get_operand1 (inst) == REG_PC)
+ if ((cris_get_operand1 (inst) == CRIS_REG_PC)
&& (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
{
- inst_env->reg[REG_PC] = inst_env->prefix_value;
- inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
+ inst_env->reg[CRIS_REG_PC] = inst_env->prefix_value;
+ inst_env->reg[CRIS_REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
}
}
else
{
/* Is the MOVEM instruction going to change the PC? */
- if (cris_get_operand2 (inst) == REG_PC)
+ if (cris_get_operand2 (inst) == CRIS_REG_PC)
{
/* It's invalid to change the PC in a delay slot. */
if (inst_env->slot_needed)
@@ -2993,13 +2986,13 @@ move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env)
inst_env->invalid = 1;
return;
}
- inst_env->reg[REG_PC] =
+ inst_env->reg[CRIS_REG_PC] =
read_memory_unsigned_integer (inst_env->reg[cris_get_operand1 (inst)],
4, inst_env->byte_order);
}
/* The increment is not depending on the size, instead it's depending
on the number of registers loaded from memory. */
- if ((cris_get_operand1 (inst) == REG_PC)
+ if ((cris_get_operand1 (inst) == CRIS_REG_PC)
&& (cris_get_mode (inst) == AUTOINC_MODE))
{
/* It's invalid to change the PC in a delay slot. */
@@ -3008,7 +3001,7 @@ move_mem_to_reg_movem_op (unsigned short inst, inst_env_type *inst_env)
inst_env->invalid = 1;
return;
}
- inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
+ inst_env->reg[CRIS_REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
}
}
inst_env->slot_needed = 0;
@@ -3026,19 +3019,19 @@ move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env)
{
/* The assign value is the value after the increment. Normally, the
assign value is the value before the increment. */
- if ((cris_get_operand1 (inst) == REG_PC)
+ if ((cris_get_operand1 (inst) == CRIS_REG_PC)
&& (cris_get_mode (inst) == PREFIX_ASSIGN_MODE))
{
/* The prefix handles the problem if we are in a delay slot. */
- inst_env->reg[REG_PC] = inst_env->prefix_value;
- inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
+ inst_env->reg[CRIS_REG_PC] = inst_env->prefix_value;
+ inst_env->reg[CRIS_REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
}
}
else
{
/* The increment is not depending on the size, instead it's depending
on the number of registers loaded to memory. */
- if ((cris_get_operand1 (inst) == REG_PC)
+ if ((cris_get_operand1 (inst) == CRIS_REG_PC)
&& (cris_get_mode (inst) == AUTOINC_MODE))
{
/* It's invalid to change the PC in a delay slot. */
@@ -3047,7 +3040,7 @@ move_reg_to_mem_movem_op (unsigned short inst, inst_env_type *inst_env)
inst_env->invalid = 1;
return;
}
- inst_env->reg[REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
+ inst_env->reg[CRIS_REG_PC] += 4 * (cris_get_operand2 (inst) + 1);
}
}
inst_env->slot_needed = 0;
@@ -3078,7 +3071,7 @@ xor_op (unsigned short inst, inst_env_type *inst_env)
}
/* Check if the PC is the target. */
- if (cris_get_operand2 (inst) == REG_PC)
+ if (cris_get_operand2 (inst) == CRIS_REG_PC)
{
/* It's invalid to change the PC in a delay slot. */
if (inst_env->slot_needed)
@@ -3086,7 +3079,7 @@ xor_op (unsigned short inst, inst_env_type *inst_env)
inst_env->invalid = 1;
return;
}
- inst_env->reg[REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)];
+ inst_env->reg[CRIS_REG_PC] ^= inst_env->reg[cris_get_operand1 (inst)];
}
inst_env->slot_needed = 0;
inst_env->prefix_found = 0;
@@ -3107,7 +3100,7 @@ muls_op (unsigned short inst, inst_env_type *inst_env)
}
/* Consider it invalid if the PC is the target. */
- if (cris_get_operand2 (inst) == REG_PC)
+ if (cris_get_operand2 (inst) == CRIS_REG_PC)
{
inst_env->invalid = 1;
return;
@@ -3131,7 +3124,7 @@ mulu_op (unsigned short inst, inst_env_type *inst_env)
}
/* Consider it invalid if the PC is the target. */
- if (cris_get_operand2 (inst) == REG_PC)
+ if (cris_get_operand2 (inst) == CRIS_REG_PC)
{
inst_env->invalid = 1;
return;
@@ -3218,8 +3211,8 @@ add_sub_cmp_and_or_move_action (unsigned short inst, inst_env_type *inst_env,
source2 &= operation_mask;
/* Calculate the new breakpoint address. */
- inst_env->reg[REG_PC] &= pc_mask;
- inst_env->reg[REG_PC] |= source1;
+ inst_env->reg[CRIS_REG_PC] &= pc_mask;
+ inst_env->reg[CRIS_REG_PC] |= source1;
}
@@ -3280,7 +3273,7 @@ reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
return;
}
/* Check if the instruction has PC as its target. */
- if (cris_get_operand2 (inst) == REG_PC)
+ if (cris_get_operand2 (inst) == CRIS_REG_PC)
{
if (inst_env->slot_needed)
{
@@ -3289,7 +3282,7 @@ reg_mode_add_sub_cmp_and_or_move_op (unsigned short inst,
}
/* The instruction has the PC as its target register. */
operand1 = inst_env->reg[cris_get_operand1 (inst)];
- operand2 = inst_env->reg[REG_PC];
+ operand2 = inst_env->reg[CRIS_REG_PC];
/* Check if it's a extend, signed or zero instruction. */
if (cris_get_opcode (inst) < 4)
@@ -3347,9 +3340,9 @@ handle_prefix_assign_mode_for_aritm_op (unsigned short inst,
unsigned long operand3;
check_assign (inst, inst_env);
- if (cris_get_operand2 (inst) == REG_PC)
+ if (cris_get_operand2 (inst) == CRIS_REG_PC)
{
- operand2 = inst_env->reg[REG_PC];
+ operand2 = inst_env->reg[CRIS_REG_PC];
/* Get the value of the third operand. */
operand3 = get_data_from_address (&inst, inst_env->prefix_value,
@@ -3376,7 +3369,7 @@ three_operand_add_sub_cmp_and_or_op (unsigned short inst,
unsigned long operand2;
unsigned long operand3;
- if (cris_get_operand1 (inst) == REG_PC)
+ if (cris_get_operand1 (inst) == CRIS_REG_PC)
{
/* The PC will be changed by the instruction. */
operand2 = inst_env->reg[cris_get_operand2 (inst)];
@@ -3437,12 +3430,12 @@ handle_inc_and_index_mode_for_aritm_op (unsigned short inst,
/* The instruction is either an indirect or autoincrement addressing mode.
Check if the destination register is the PC. */
- if (cris_get_operand2 (inst) == REG_PC)
+ if (cris_get_operand2 (inst) == CRIS_REG_PC)
{
/* Must be done here, get_data_from_address may change the size
field. */
size = cris_get_size (inst);
- operand2 = inst_env->reg[REG_PC];
+ operand2 = inst_env->reg[CRIS_REG_PC];
/* Get the value of the third operand, i.e. the indirect operand. */
operand1 = inst_env->reg[cris_get_operand1 (inst)];
@@ -3454,7 +3447,7 @@ handle_inc_and_index_mode_for_aritm_op (unsigned short inst,
}
/* If this is an autoincrement addressing mode, check if the increment
changes the PC. */
- if ((cris_get_operand1 (inst) == REG_PC)
+ if ((cris_get_operand1 (inst) == CRIS_REG_PC)
&& (cris_get_mode (inst) == AUTOINC_MODE))
{
/* Get the size field. */
@@ -3521,7 +3514,7 @@ quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env)
}
/* Check if the instruction has PC as its target. */
- if (cris_get_operand2 (inst) == REG_PC)
+ if (cris_get_operand2 (inst) == CRIS_REG_PC)
{
if (inst_env->slot_needed)
{
@@ -3529,7 +3522,7 @@ quick_mode_add_sub_op (unsigned short inst, inst_env_type *inst_env)
return;
}
operand1 = cris_get_quick_value (inst);
- operand2 = inst_env->reg[REG_PC];
+ operand2 = inst_env->reg[CRIS_REG_PC];
/* The size should now be dword. */
cris_set_size_to_dword (&inst);
@@ -3560,7 +3553,7 @@ quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env)
return;
}
/* Check if the instruction has PC as its target. */
- if (cris_get_operand2 (inst) == REG_PC)
+ if (cris_get_operand2 (inst) == CRIS_REG_PC)
{
if (inst_env->slot_needed)
{
@@ -3569,7 +3562,7 @@ quick_mode_and_cmp_move_or_op (unsigned short inst, inst_env_type *inst_env)
}
/* The instruction has the PC as its target register. */
operand1 = cris_get_quick_value (inst);
- operand2 = inst_env->reg[REG_PC];
+ operand2 = inst_env->reg[CRIS_REG_PC];
/* The quick value is signed, so check if we must do a signed extend. */
if (operand1 & SIGNED_QUICK_VALUE_MASK)
diff --git a/gdb/microblaze-tdep.c b/gdb/microblaze-tdep.c
index fd0200853fc8..97b453a147f6 100644
--- a/gdb/microblaze-tdep.c
+++ b/gdb/microblaze-tdep.c
@@ -49,19 +49,35 @@
This set also needs to be verified if it is complete. */
#define IS_RETURN(op) (op == rtsd || op == rtid)
#define IS_UPDATE_SP(op, rd, ra) \
- ((op == addik || op == addi) && rd == REG_SP && ra == REG_SP)
+ ((op == addik || op == addi) \
+ && rd == MICROBLAZE_REG_SP \
+ && ra == MICROBLAZE_REG_SP)
#define IS_SPILL_SP(op, rd, ra) \
- ((op == swi || op == sw) && rd == REG_SP && ra == REG_SP)
+ ((op == swi || op == sw) \
+ && rd == MICROBLAZE_REG_SP \
+ && ra == MICROBLAZE_REG_SP)
#define IS_SPILL_REG(op, rd, ra) \
- ((op == swi || op == sw) && rd != REG_SP && ra == REG_SP)
+ ((op == swi || op == sw) \
+ && rd != MICROBLAZE_REG_SP \
+ && ra == MICROBLAZE_REG_SP)
#define IS_ALSO_SPILL_REG(op, rd, ra, rb) \
- ((op == swi || op == sw) && rd != REG_SP && ra == 0 && rb == REG_SP)
+ ((op == swi || op == sw) \
+ && rd != MICROBLAZE_REG_SP \
+ && ra == 0 \
+ && rb == MICROBLAZE_REG_SP)
#define IS_SETUP_FP(op, ra, rb) \
- ((op == add || op == addik || op == addk) && ra == REG_SP && rb == 0)
+ ((op == add || op == addik || op == addk) \
+ && ra == MICROBLAZE_REG_SP \
+ && rb == 0)
#define IS_SPILL_REG_FP(op, rd, ra, fpregnum) \
- ((op == swi || op == sw) && rd != REG_SP && ra == fpregnum && ra != 0)
+ ((op == swi || op == sw) \
+ && rd != MICROBLAZE_REG_SP \
+ && ra == fpregnum \
+ && ra != 0)
#define IS_SAVE_HIDDEN_PTR(op, rd, ra, rb) \
- ((op == add || op == addik) && ra == MICROBLAZE_FIRST_ARGREG && rb == 0)
+ ((op == add || op == addik) \
+ && ra == MICROBLAZE_FIRST_ARGREG \
+ && rb == 0)
/* The registers of the Xilinx microblaze processor. */
diff --git a/gdb/nds32-tdep.c b/gdb/nds32-tdep.c
index 5af91e307808..5291ebace8f8 100644
--- a/gdb/nds32-tdep.c
+++ b/gdb/nds32-tdep.c
@@ -53,7 +53,7 @@
#define N32_LMW_BIM \
N32_TYPE4 (LSMW, 0, 0, 0, 0, (N32_LSMW_BIM << 2) | N32_LSMW_LSMW)
#define N32_FLDI_SP \
- N32_TYPE2 (LDC, 0, REG_SP, 0)
+ N32_TYPE2 (LDC, 0, N32_REG_SP, 0)
/* Use an invalid address value as 'not available' marker. */
enum { REG_UNAVAIL = (CORE_ADDR) -1 };
@@ -588,7 +588,7 @@ nds32_push_multiple_words (struct nds32_frame_cache *cache, int rb, int re,
}
/* Skip case where re == rb == sp. */
- if ((rb < REG_FP) && (re < REG_FP))
+ if ((rb < N32_REG_FP) && (re < N32_REG_FP))
{
for (i = re; i >= rb; i--)
{
@@ -626,7 +626,8 @@ nds32_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
/* 32-bit instruction */
insn_len = 4;
- if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0))
+ if (CHOP_BITS (insn, 15)
+ == N32_TYPE2 (ADDI, N32_REG_SP, N32_REG_SP, 0))
{
/* addi $sp, $sp, imm15s */
int imm15s = N32_IMM15S (insn);
@@ -640,7 +641,8 @@ nds32_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
continue;
}
}
- else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_FP, REG_SP, 0))
+ else if (CHOP_BITS (insn, 15)
+ == N32_TYPE2 (ADDI, N32_REG_FP, N32_REG_SP, 0))
{
/* addi $fp, $sp, imm15s */
int imm15s = N32_IMM15S (insn);
@@ -655,7 +657,7 @@ nds32_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
}
}
else if ((insn & ~(__MASK (19) << 6)) == N32_SMW_ADM
- && N32_RA5 (insn) == REG_SP)
+ && N32_RA5 (insn) == N32_REG_SP)
{
/* smw.adm Rb, [$sp], Re, enable4 */
if (cache != NULL)
@@ -665,8 +667,9 @@ nds32_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
in_prologue_bb = 1;
continue;
}
- else if (insn == N32_ALU1 (ADD, REG_SP, REG_SP, REG_TA)
- || insn == N32_ALU1 (ADD, REG_SP, REG_TA, REG_SP))
+ else if (insn == N32_ALU1 (ADD, N32_REG_SP, N32_REG_SP, N32_REG_TA)
+ || insn == N32_ALU1 (ADD, N32_REG_SP, N32_REG_TA,
+ N32_REG_SP))
{
/* add $sp, $sp, $ta */
/* add $sp, $ta, $sp */
@@ -679,7 +682,7 @@ nds32_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
continue;
}
}
- else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, REG_TA, 0))
+ else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, N32_REG_TA, 0))
{
/* movi $ta, imm20s */
if (cache != NULL)
@@ -687,7 +690,7 @@ nds32_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
continue;
}
- else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, REG_TA, 0))
+ else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, N32_REG_TA, 0))
{
/* sethi $ta, imm20u */
if (cache != NULL)
@@ -695,7 +698,8 @@ nds32_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
continue;
}
- else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ORI, REG_TA, REG_TA, 0))
+ else if (CHOP_BITS (insn, 15)
+ == N32_TYPE2 (ORI, N32_REG_TA, N32_REG_TA, 0))
{
/* ori $ta, $ta, imm15u */
if (cache != NULL)
@@ -703,7 +707,8 @@ nds32_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
continue;
}
- else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_TA, REG_TA, 0))
+ else if (CHOP_BITS (insn, 15)
+ == N32_TYPE2 (ADDI, N32_REG_TA, N32_REG_TA, 0))
{
/* addi $ta, $ta, imm15s */
if (cache != NULL)
@@ -711,27 +716,28 @@ nds32_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
continue;
}
- if (insn == N32_ALU1 (ADD, REG_GP, REG_TA, REG_GP)
- || insn == N32_ALU1 (ADD, REG_GP, REG_GP, REG_TA))
+ if (insn == N32_ALU1 (ADD, N32_REG_GP, N32_REG_TA, N32_REG_GP)
+ || insn == N32_ALU1 (ADD, N32_REG_GP, N32_REG_GP, N32_REG_TA))
{
/* add $gp, $ta, $gp */
/* add $gp, $gp, $ta */
in_prologue_bb = 1;
continue;
}
- else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, REG_GP, 0))
+ else if (CHOP_BITS (insn, 20) == N32_TYPE1 (MOVI, N32_REG_GP, 0))
{
/* movi $gp, imm20s */
in_prologue_bb = 1;
continue;
}
- else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, REG_GP, 0))
+ else if (CHOP_BITS (insn, 20) == N32_TYPE1 (SETHI, N32_REG_GP, 0))
{
/* sethi $gp, imm20u */
in_prologue_bb = 1;
continue;
}
- else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ORI, REG_GP, REG_GP, 0))
+ else if (CHOP_BITS (insn, 15)
+ == N32_TYPE2 (ORI, N32_REG_GP, N32_REG_GP, 0))
{
/* ori $gp, $gp, imm15u */
in_prologue_bb = 1;
@@ -761,7 +767,7 @@ nds32_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
normal form (bit [12] == 0) is used. */
/* fsdi FDt, [$sp + (imm12s << 2)] */
- if (N32_RA5 (insn) == REG_SP)
+ if (N32_RA5 (insn) == N32_REG_SP)
continue;
}
@@ -814,13 +820,13 @@ nds32_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
in_prologue_bb = 1;
continue;
}
- else if (insn == N16_TYPE5 (ADD5PC, REG_GP))
+ else if (insn == N16_TYPE5 (ADD5PC, N32_REG_GP))
{
/* add5.pc $gp */
in_prologue_bb = 1;
continue;
}
- else if (CHOP_BITS (insn, 5) == N16_TYPE55 (MOVI55, REG_GP, 0))
+ else if (CHOP_BITS (insn, 5) == N16_TYPE55 (MOVI55, N32_REG_GP, 0))
{
/* movi55 $gp, imm5s */
in_prologue_bb = 1;
@@ -1028,7 +1034,7 @@ nds32_pop_multiple_words (struct nds32_frame_cache *cache, int rb, int re,
int i;
/* Skip case where re == rb == sp. */
- if ((rb < REG_FP) && (re < REG_FP))
+ if ((rb < N32_REG_FP) && (re < N32_REG_FP))
{
for (i = rb; i <= re; i++)
{
@@ -1066,16 +1072,16 @@ static inline int
nds32_analyze_epilogue_insn32 (int abi_use_fpr, uint32_t insn,
struct nds32_frame_cache *cache)
{
- if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_SP, 0)
+ if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, N32_REG_SP, N32_REG_SP, 0)
&& N32_IMM15S (insn) > 0)
/* addi $sp, $sp, imm15s */
return INSN_RESET_SP;
- else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, REG_SP, REG_FP, 0)
+ else if (CHOP_BITS (insn, 15) == N32_TYPE2 (ADDI, N32_REG_SP, N32_REG_FP, 0)
&& N32_IMM15S (insn) < 0)
/* addi $sp, $fp, imm15s */
return INSN_RESET_SP;
else if ((insn & ~(__MASK (19) << 6)) == N32_LMW_BIM
- && N32_RA5 (insn) == REG_SP)
+ && N32_RA5 (insn) == N32_REG_SP)
{
/* lmw.bim Rb, [$sp], Re, enable4 */
if (cache != NULL)
@@ -1084,11 +1090,11 @@ nds32_analyze_epilogue_insn32 (int abi_use_fpr, uint32_t insn,
return INSN_RECOVER;
}
- else if (insn == N32_JREG (JR, 0, REG_LP, 0, 1))
+ else if (insn == N32_JREG (JR, 0, N32_REG_LP, 0, 1))
/* ret $lp */
return INSN_RETURN;
- else if (insn == N32_ALU1 (ADD, REG_SP, REG_SP, REG_TA)
- || insn == N32_ALU1 (ADD, REG_SP, REG_TA, REG_SP))
+ else if (insn == N32_ALU1 (ADD, N32_REG_SP, N32_REG_SP, N32_REG_TA)
+ || insn == N32_ALU1 (ADD, N32_REG_SP, N32_REG_TA, N32_REG_SP))
/* add $sp, $sp, $ta */
/* add $sp, $ta, $sp */
return INSN_RESET_SP;
@@ -1122,7 +1128,7 @@ nds32_analyze_epilogue_insn32 (int abi_use_fpr, uint32_t insn,
static inline int
nds32_analyze_epilogue_insn16 (uint32_t insn, struct nds32_frame_cache *cache)
{
- if (insn == N16_TYPE5 (RET5, REG_LP))
+ if (insn == N16_TYPE5 (RET5, N32_REG_LP))
/* ret5 $lp */
return INSN_RETURN;
else if (CHOP_BITS (insn, 10) == N16_TYPE10 (ADDI10S, 0))
diff --git a/include/opcode/cris.h b/include/opcode/cris.h
index 35dc595858bd..fa6bdf69af1a 100644
--- a/include/opcode/cris.h
+++ b/include/opcode/cris.h
@@ -31,8 +31,8 @@
/* Registers. */
#define MAX_REG (15)
-#define REG_SP (14)
-#define REG_PC (15)
+#define CRIS_REG_SP (14)
+#define CRIS_REG_PC (15)
/* CPU version control of disassembly and assembly of instructions.
May affect how the instruction is assembled, at least the size of
@@ -140,7 +140,7 @@ extern const struct cris_cond15 cris_conds15[];
#define BDAP_INDIR_OPCODE (BDAP_INDIR_HIGH * 0x0100 + BDAP_INDIR_LOW)
#define BDAP_INDIR_Z_BITS (BDAP_INDIR_HIGH_Z * 0x100 + BDAP_INDIR_LOW_Z)
-#define BDAP_PC_LOW (BDAP_INDIR_LOW + REG_PC)
+#define BDAP_PC_LOW (BDAP_INDIR_LOW + CRIS_REG_PC)
#define BDAP_INCR_HIGH (BDAP_INDIR_HIGH + AUTOINCR_BIT)
/* No prefix must have this code for its "match" bits in the
@@ -194,16 +194,16 @@ extern const char *const cris_cc_strings[];
#define JUMP_INDIR_OPCODE (0x0930)
#define JUMP_INDIR_Z_BITS (0xf2c0)
#define JUMP_PC_INCR_OPCODE \
- (JUMP_INDIR_OPCODE + AUTOINCR_BIT * 0x0100 + REG_PC)
+ (JUMP_INDIR_OPCODE + AUTOINCR_BIT * 0x0100 + CRIS_REG_PC)
#define MOVE_M_TO_PREG_OPCODE 0x0a30
#define MOVE_M_TO_PREG_ZBITS 0x01c0
/* BDAP.D N,PC. */
#define MOVE_PC_INCR_OPCODE_PREFIX \
- (((BDAP_INCR_HIGH | (REG_PC << 4)) << 8) | BDAP_PC_LOW | (2 << 4))
+ (((BDAP_INCR_HIGH | (CRIS_REG_PC << 4)) << 8) | BDAP_PC_LOW | (2 << 4))
#define MOVE_PC_INCR_OPCODE_SUFFIX \
- (MOVE_M_TO_PREG_OPCODE | REG_PC | (AUTOINCR_BIT << 8))
+ (MOVE_M_TO_PREG_OPCODE | CRIS_REG_PC | (AUTOINCR_BIT << 8))
#define JUMP_PC_INCR_OPCODE_V32 (0x0DBF)
diff --git a/include/opcode/nds32.h b/include/opcode/nds32.h
index 6184c4b30b42..bf6d02b0f050 100644
--- a/include/opcode/nds32.h
+++ b/include/opcode/nds32.h
@@ -21,20 +21,20 @@
#define OPCODE_NDS32_H
/* Registers. */
-#define REG_R0 (0)
-#define REG_R5 (5)
-#define REG_R8 (8)
-#define REG_R10 (10)
-#define REG_R12 (12)
-#define REG_R15 (15)
-#define REG_R16 (16)
-#define REG_R20 (20)
-#define REG_TA (15)
-#define REG_TP (25)
-#define REG_FP (28)
-#define REG_GP (29)
-#define REG_LP (30)
-#define REG_SP (31)
+#define N32_REG_R0 (0)
+#define N32_REG_R5 (5)
+#define N32_REG_R8 (8)
+#define N32_REG_R10 (10)
+#define N32_REG_R12 (12)
+#define N32_REG_R15 (15)
+#define N32_REG_R16 (16)
+#define N32_REG_R20 (20)
+#define N32_REG_TA (15)
+#define N32_REG_TP (25)
+#define N32_REG_FP (28)
+#define N32_REG_GP (29)
+#define N32_REG_LP (30)
+#define N32_REG_SP (31)
/* Macros for extracting fields or making an instruction. */
static const int nds32_r45map[] ATTRIBUTE_UNUSED =
@@ -967,24 +967,24 @@ enum n16_opcodes
#define INSN_MFUSR_PC_MASK 0xFE0FFFFF
/* Instructions use $ta register as operand. */
-#define INSN_SETHI_TA (INSN_SETHI | (REG_TA << 20))
-#define INSN_ORI_TA (INSN_ORI | (REG_TA << 20) | (REG_TA << 15))
-#define INSN_ADD_TA (INSN_ADD | (REG_TA << 20))
-#define INSN_ADD45_TA (INSN_ADD45 | (REG_TA << 5))
-#define INSN_JR5_TA (INSN_JR5 | (REG_TA << 0))
-#define INSN_RET5_TA (INSN_RET5 | (REG_TA << 0))
-#define INSN_JR_TA (INSN_JR | (REG_TA << 10))
-#define INSN_RET_TA (INSN_RET | (REG_TA << 10))
-#define INSN_JRAL_TA (INSN_JRAL | (REG_LP << 20) | (REG_TA << 10))
-#define INSN_JRAL5_TA (INSN_JRAL5 | (REG_TA << 0))
-#define INSN_BEQZ_TA (INSN_BEQZ | (REG_TA << 20))
-#define INSN_BNEZ_TA (INSN_BNEZ | (REG_TA << 20))
-#define INSN_MOVI_TA (INSN_MOVI | (REG_TA << 20))
-#define INSN_BEQ_TA (INSN_BEQ | (REG_TA << 15))
-#define INSN_BNE_TA (INSN_BNE | (REG_TA << 15))
+#define INSN_SETHI_TA (INSN_SETHI | (N32_REG_TA << 20))
+#define INSN_ORI_TA (INSN_ORI | (N32_REG_TA << 20) | (N32_REG_TA << 15))
+#define INSN_ADD_TA (INSN_ADD | (N32_REG_TA << 20))
+#define INSN_ADD45_TA (INSN_ADD45 | (N32_REG_TA << 5))
+#define INSN_JR5_TA (INSN_JR5 | (N32_REG_TA << 0))
+#define INSN_RET5_TA (INSN_RET5 | (N32_REG_TA << 0))
+#define INSN_JR_TA (INSN_JR | (N32_REG_TA << 10))
+#define INSN_RET_TA (INSN_RET | (N32_REG_TA << 10))
+#define INSN_JRAL_TA (INSN_JRAL | (N32_REG_LP << 20) | (N32_REG_TA << 10))
+#define INSN_JRAL5_TA (INSN_JRAL5 | (N32_REG_TA << 0))
+#define INSN_BEQZ_TA (INSN_BEQZ | (N32_REG_TA << 20))
+#define INSN_BNEZ_TA (INSN_BNEZ | (N32_REG_TA << 20))
+#define INSN_MOVI_TA (INSN_MOVI | (N32_REG_TA << 20))
+#define INSN_BEQ_TA (INSN_BEQ | (N32_REG_TA << 15))
+#define INSN_BNE_TA (INSN_BNE | (N32_REG_TA << 15))
/* Instructions use $r5 register as operand. */
-#define INSN_BNE_R5 (INSN_BNE | (REG_R5 << 15))
-#define INSN_BEQ_R5 (INSN_BEQ | (REG_R5 << 15))
+#define INSN_BNE_R5 (INSN_BNE | (N32_REG_R5 << 15))
+#define INSN_BEQ_R5 (INSN_BEQ | (N32_REG_R5 << 15))
#endif
diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c
index 89770a7abe52..c4fa6e2e493d 100644
--- a/opcodes/microblaze-dis.c
+++ b/opcodes/microblaze-dis.c
@@ -133,58 +133,59 @@ get_field_special (struct string_buf *buf, long instr,
switch ((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask))
{
- case REG_MSR_MASK :
+ case MICROBLAZE_REG_MSR_MASK:
spr = "msr";
break;
- case REG_PC_MASK :
+ case MICROBLAZE_REG_PC_MASK:
spr = "pc";
break;
- case REG_EAR_MASK :
+ case MICROBLAZE_REG_EAR_MASK:
spr = "ear";
break;
- case REG_ESR_MASK :
+ case MICROBLAZE_REG_ESR_MASK:
spr = "esr";
break;
- case REG_FSR_MASK :
+ case MICROBLAZE_REG_FSR_MASK:
spr = "fsr";
break;
- case REG_BTR_MASK :
+ case MICROBLAZE_REG_BTR_MASK:
spr = "btr";
break;
- case REG_EDR_MASK :
+ case MICROBLAZE_REG_EDR_MASK:
spr = "edr";
break;
- case REG_PID_MASK :
+ case MICROBLAZE_REG_PID_MASK:
spr = "pid";
break;
- case REG_ZPR_MASK :
+ case MICROBLAZE_REG_ZPR_MASK:
spr = "zpr";
break;
- case REG_TLBX_MASK :
+ case MICROBLAZE_REG_TLBX_MASK:
spr = "tlbx";
break;
- case REG_TLBLO_MASK :
+ case MICROBLAZE_REG_TLBLO_MASK:
spr = "tlblo";
break;
- case REG_TLBHI_MASK :
+ case MICROBLAZE_REG_TLBHI_MASK:
spr = "tlbhi";
break;
- case REG_TLBSX_MASK :
+ case MICROBLAZE_REG_TLBSX_MASK:
spr = "tlbsx";
break;
- case REG_SHR_MASK :
+ case MICROBLAZE_REG_SHR_MASK:
spr = "shr";
break;
- case REG_SLR_MASK :
+ case MICROBLAZE_REG_SLR_MASK:
spr = "slr";
break;
- default :
+ default:
if (((((instr & IMM_MASK) >> IMM_LOW) ^ op->immval_mask) & 0xE000)
- == REG_PVR_MASK)
+ == MICROBLAZE_REG_PVR_MASK)
{
sprintf (p, "%spvr%d", register_prefix,
- (unsigned short)(((instr & IMM_MASK) >> IMM_LOW)
- ^ op->immval_mask) ^ REG_PVR_MASK);
+ ((unsigned short)(((instr & IMM_MASK) >> IMM_LOW)
+ ^ op->immval_mask)
+ ^ MICROBLAZE_REG_PVR_MASK));
return p;
}
else
diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h
index faa520ff2692..f95ef1492b92 100644
--- a/opcodes/microblaze-opcm.h
+++ b/opcodes/microblaze-opcm.h
@@ -74,23 +74,23 @@ enum microblaze_instr_type
/* Gen purpose regs go from 0 to 31. */
/* Mask is reg num - max_reg_num, ie reg_num - 32 in this case. */
-#define REG_PC_MASK 0x8000
-#define REG_MSR_MASK 0x8001
-#define REG_EAR_MASK 0x8003
-#define REG_ESR_MASK 0x8005
-#define REG_FSR_MASK 0x8007
-#define REG_BTR_MASK 0x800b
-#define REG_EDR_MASK 0x800d
-#define REG_PVR_MASK 0xa000
-#define REG_SLR_MASK 0x8800
-#define REG_SHR_MASK 0x8802
+#define MICROBLAZE_REG_PC_MASK 0x8000
+#define MICROBLAZE_REG_MSR_MASK 0x8001
+#define MICROBLAZE_REG_EAR_MASK 0x8003
+#define MICROBLAZE_REG_ESR_MASK 0x8005
+#define MICROBLAZE_REG_FSR_MASK 0x8007
+#define MICROBLAZE_REG_BTR_MASK 0x800b
+#define MICROBLAZE_REG_EDR_MASK 0x800d
+#define MICROBLAZE_REG_PVR_MASK 0xa000
+#define MICROBLAZE_REG_SLR_MASK 0x8800
+#define MICROBLAZE_REG_SHR_MASK 0x8802
-#define REG_PID_MASK 0x9000
-#define REG_ZPR_MASK 0x9001
-#define REG_TLBX_MASK 0x9002
-#define REG_TLBLO_MASK 0x9003
-#define REG_TLBHI_MASK 0x9004
-#define REG_TLBSX_MASK 0x9005
+#define MICROBLAZE_REG_PID_MASK 0x9000
+#define MICROBLAZE_REG_ZPR_MASK 0x9001
+#define MICROBLAZE_REG_TLBX_MASK 0x9002
+#define MICROBLAZE_REG_TLBLO_MASK 0x9003
+#define MICROBLAZE_REG_TLBHI_MASK 0x9004
+#define MICROBLAZE_REG_TLBSX_MASK 0x9005
#define MIN_REGNUM 0
#define MAX_REGNUM 31
@@ -98,32 +98,32 @@ enum microblaze_instr_type
#define MIN_PVR_REGNUM 0
#define MAX_PVR_REGNUM 15
-#define REG_PC 32 /* PC. */
-#define REG_MSR 33 /* Machine status reg. */
-#define REG_EAR 35 /* Exception reg. */
-#define REG_ESR 37 /* Exception reg. */
-#define REG_FSR 39 /* FPU Status reg. */
-#define REG_BTR 43 /* Branch Target reg. */
-#define REG_EDR 45 /* Exception reg. */
-#define REG_SHR 50 /* Stack High reg. */
-#define REG_SLR 51 /* Stack Low reg. */
-#define REG_PVR 40960 /* Program Verification reg. */
+#define MICROBLAZE_REG_PC 32 /* PC. */
+#define MICROBLAZE_REG_MSR 33 /* Machine status reg. */
+#define MICROBLAZE_REG_EAR 35 /* Exception reg. */
+#define MICROBLAZE_REG_ESR 37 /* Exception reg. */
+#define MICROBLAZE_REG_FSR 39 /* FPU Status reg. */
+#define MICROBLAZE_REG_BTR 43 /* Branch Target reg. */
+#define MICROBLAZE_REG_EDR 45 /* Exception reg. */
+#define MICROBLAZE_REG_SHR 50 /* Stack High reg. */
+#define MICROBLAZE_REG_SLR 51 /* Stack Low reg. */
+#define MICROBLAZE_REG_PVR 40960 /* Program Verification reg. */
-#define REG_PID 36864 /* MMU: Process ID reg. */
-#define REG_ZPR 36865 /* MMU: Zone Protect reg. */
-#define REG_TLBX 36866 /* MMU: TLB Index reg. */
-#define REG_TLBLO 36867 /* MMU: TLB Low reg. */
-#define REG_TLBHI 36868 /* MMU: TLB High reg. */
-#define REG_TLBSX 36869 /* MMU: TLB Search Index reg. */
+#define MICROBLAZE_REG_PID 36864 /* MMU: Process ID reg. */
+#define MICROBLAZE_REG_ZPR 36865 /* MMU: Zone Protect reg. */
+#define MICROBLAZE_REG_TLBX 36866 /* MMU: TLB Index reg. */
+#define MICROBLAZE_REG_TLBLO 36867 /* MMU: TLB Low reg. */
+#define MICROBLAZE_REG_TLBHI 36868 /* MMU: TLB High reg. */
+#define MICROBLAZE_REG_TLBSX 36869 /* MMU: TLB Search Index reg. */
/* Alternate names for gen purpose regs. */
-#define REG_SP 1 /* stack pointer. */
-#define REG_ROSDP 2 /* read-only small data pointer. */
-#define REG_RWSDP 13 /* read-write small data pointer. */
+#define MICROBLAZE_REG_SP 1 /* stack pointer. */
+#define MICROBLAZE_REG_ROSDP 2 /* read-only small data pointer. */
+#define MICROBLAZE_REG_RWSDP 13 /* read-write small data pointer. */
/* Assembler Register - Used in Delay Slot Optimization. */
-#define REG_AS 18
-#define REG_ZERO 0
+#define MICROBLAZE_REG_AS 18
+#define MICROBLAZE_REG_ZERO 0
#define RD_LOW 21 /* Low bit for RD. */
#define RA_LOW 16 /* Low bit for RA. */
base-commit: 2452e480ae871587ef4e34ce1da368c71b43b425
--
2.55.0
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