[PING][PATCH 0/7] RISC-V: Add support for Andes floating-point and vector extensions

[Ethan Y. C. Liang]

Hi Jan,

Could you please help me commit the patches approved by Nelson?

Thanks,
Ethan


On Thu, Aug 06, 2026 at 09:29:28AM +0800, Ethan Y. C. Liang wrote:
> Hi Nelson,
> 
> It seems the patches haven't been committed yet.
> 
> Could you please help commit them? I don't have commit access.
> 
> Thanks,
> Ethan
> 
> On Thu, Jul 30, 2026 at 10:34:15AM +0800, Ethan Y. C. Liang wrote:
> > Got it. Please go ahead and commit it.
> > 
> > Thanks,
> > Ethan
> > 
> > 
> > On Wed, Jul 29, 2026 at 07:56:18PM +0800, Nelson Chu wrote:
> > > Okay to commit.  I don’t remember exactly when, but Palmer once told me that vendor stuff could be committed even before the risc-v convention spec itself was updated.  If that so then accept vendor extension is always Okay, provide you take responsibility for maintaining them moving forward.
> > > 
> > > Thanks
> > > Nelson
> > > 
> > > Ethan Y. C. Liang via Binutils <binutils@sourceware.org<mailto:binutils@sourceware.org>>於 2026年7月23日週四，上午11:25寫道：
> > > Hi Nelson,
> > > 
> > > Just a quick ping on the patch series.
> > > Let me know if you need anything from my side.
> > > 
> > > Thanks,
> > > Ethan
> > > 
> > > 
> > > On Tue, Nov 18, 2025 at 05:13:43PM +0800, Ethan Y. C. Liang wrote:
> > > > This patch series adds support for seven Andes RISC-V extensions in binutils.
> > > > The extensions provide enhanced capabilities for floating-point conversion, vector operations, and integer processing.
> > > >
> > > > These extensions have been part of Andes' commercial toolchain for several years and have been extensively validated through our internal testing and production usage. Any feedback to help ensure smooth integration with the open-source ecosystem would be greatly appreciated.
> > > >
> > > > The Andes RISC-V extensions are documented in the AndeStar V5 ISA specification [1].
> > > >
> > > > [1] https://github.com/andestech/andes-v5-isa/releases/download/ast-v5_4_0-release/AndeStar_V5_ISA_Spec_UM165-v1.5.08-20250317.pdf
> > > >
> > > > Ethan Y. C. Liang (7):
> > > >   RISC-V: Add support for XAndesBFHCvt extension
> > > >   RISC-V: Add support for XAndesVBFHCvt extension
> > > >   RISC-V: Add support for XAndesVSIntLoad extension
> > > >   RISC-V: Add support for XAndesVPackFPH extension
> > > >   RISC-V: Add support for XAndesVDot extension
> > > >   RISC-V: Add support for XAndesVSIntH extension
> > > >   RISC-V: Add support for XAndesVQMac extension
> > > >
> > > >  bfd/elfxx-riscv.c                           | 35 +++++++++
> > > >  gas/doc/c-riscv.texi                        | 35 +++++++++
> > > >  gas/testsuite/gas/riscv/march-help.l        |  7 ++
> > > >  gas/testsuite/gas/riscv/x-andes-bfhcvt.d    | 12 +++
> > > >  gas/testsuite/gas/riscv/x-andes-bfhcvt.s    |  3 +
> > > >  gas/testsuite/gas/riscv/x-andes-vbfhcvt.d   | 12 +++
> > > >  gas/testsuite/gas/riscv/x-andes-vbfhcvt.s   |  3 +
> > > >  gas/testsuite/gas/riscv/x-andes-vdot.d      | 16 ++++
> > > >  gas/testsuite/gas/riscv/x-andes-vdot.s      |  7 ++
> > > >  gas/testsuite/gas/riscv/x-andes-vpackfph.d  | 14 ++++
> > > >  gas/testsuite/gas/riscv/x-andes-vpackfph.s  |  5 ++
> > > >  gas/testsuite/gas/riscv/x-andes-vqmac.d     | 24 ++++++
> > > >  gas/testsuite/gas/riscv/x-andes-vqmac.s     | 15 ++++
> > > >  gas/testsuite/gas/riscv/x-andes-vsinth.d    | 20 +++++
> > > >  gas/testsuite/gas/riscv/x-andes-vsinth.s    | 11 +++
> > > >  gas/testsuite/gas/riscv/x-andes-vsintload.d | 16 ++++
> > > >  gas/testsuite/gas/riscv/x-andes-vsintload.s |  7 ++
> > > >  include/opcode/riscv-opc.h                  | 83 +++++++++++++++++++++
> > > >  include/opcode/riscv.h                      |  7 ++
> > > >  opcodes/riscv-opc.c                         | 37 +++++++++
> > > >  20 files changed, 369 insertions(+)
> > > >  create mode 100644 gas/testsuite/gas/riscv/x-andes-bfhcvt.d
> > > >  create mode 100644 gas/testsuite/gas/riscv/x-andes-bfhcvt.s
> > > >  create mode 100644 gas/testsuite/gas/riscv/x-andes-vbfhcvt.d
> > > >  create mode 100644 gas/testsuite/gas/riscv/x-andes-vbfhcvt.s
> > > >  create mode 100644 gas/testsuite/gas/riscv/x-andes-vdot.d
> > > >  create mode 100644 gas/testsuite/gas/riscv/x-andes-vdot.s
> > > >  create mode 100644 gas/testsuite/gas/riscv/x-andes-vpackfph.d
> > > >  create mode 100644 gas/testsuite/gas/riscv/x-andes-vpackfph.s
> > > >  create mode 100644 gas/testsuite/gas/riscv/x-andes-vqmac.d
> > > >  create mode 100644 gas/testsuite/gas/riscv/x-andes-vqmac.s
> > > >  create mode 100644 gas/testsuite/gas/riscv/x-andes-vsinth.d
> > > >  create mode 100644 gas/testsuite/gas/riscv/x-andes-vsinth.s
> > > >  create mode 100644 gas/testsuite/gas/riscv/x-andes-vsintload.d
> > > >  create mode 100644 gas/testsuite/gas/riscv/x-andes-vsintload.s
> > > >
> > > > --
> > > > 2.49.0
> > > >