[PATCH 08/19] RISC-V: drop FCVT.Q.L{,U} forms with rounding mode

[Jiawei]

> Like FCVT.D.W{,U} and FCVT.Q.W{,U} these also are unaffected by rounding
> mode, and hence allowing for a respective operand is bogus. (Otherwise
> MASK_RM should also be used in the match field for the respectively other
> forms.)
>
LGTM.

Dropping the rounding-mode operand forms for fcvt.q.l and fcvt.q.lu looks
right to me. These conversions are unaffected by the rounding mode, and
keeping the ",m" forms would misleadingly suggest that the operand has an
effect. This also makes the table consistent with the existing
fcvt.d.w{,u} and fcvt.q.w{,u} forms.

Best regards,

Jiawei

>
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -1165,9 +1165,7 @@ const struct riscv_opcode riscv_opcodes[
>  {"fcvt.lu.q", 64, INSN_CLASS_Q_INX,   "d,S", 
>  MATCH_FCVT_LU_Q|MASK_RM, MASK_FCVT_LU_Q|MASK_RM, match_opcode, 0 },
>  {"fcvt.lu.q", 64, INSN_CLASS_Q_INX,   "d,S,m",  MATCH_FCVT_LU_Q, 
> MASK_FCVT_LU_Q, match_opcode, 0 },
>  {"fcvt.q.l",  64, INSN_CLASS_Q_INX,   "D,s",  MATCH_FCVT_Q_L, 
> MASK_FCVT_Q_L|MASK_RM, match_opcode, 0 },
> -{"fcvt.q.l",  64, INSN_CLASS_Q_INX,   "D,s,m",  MATCH_FCVT_Q_L, 
> MASK_FCVT_Q_L, match_opcode, 0 },
>  {"fcvt.q.lu", 64, INSN_CLASS_Q_INX,   "D,s",  MATCH_FCVT_Q_LU, 
> MASK_FCVT_Q_LU|MASK_RM, match_opcode, 0 },
> -{"fcvt.q.lu", 64, INSN_CLASS_Q_INX,   "D,s,m",  MATCH_FCVT_Q_LU, 
> MASK_FCVT_Q_LU, match_opcode, 0 },
>
>  /* Compressed instructions.  */
>  {"c.unimp",    0, INSN_CLASS_ZCA,   "",          0, 0xffffU, 
> match_opcode, 0 },
>