[PATCH 07/19] bfd/RISC-V: Zvfbfwma implies Zvfbfmin

[Jiawei]

> This is pretty clear from the spec.
> ---
> While the spec is also explicit there: I would have expected Zvfbfmin (not
> Zvfbfwma) to be what implies Zfbfmin. Is there an explanation for this?
>
LGTM.

This matches the current BF16 specification:

https://github.com/riscv/riscv-isa-manual/blob/main/src/unpriv/zvfbfwma.adoc


Zvfbfmin only depends on Zve32f, while Zvfbfwma depends on both Zvfbfmin and
Zfbfmin.

Regarding the question in the note, I think the distinction makes sense:
Zvfbfmin only provides vector BF16/FP32 conversions, while Zvfbfwma also has
the vector-scalar form, and the specification describes it in terms of
fcvt.s.bf16 for the scalar BF16 input. So following the spec here looks
right to me.

Best regards,
Jiawei
>
>
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -1232,7 +1232,7 @@ static const struct riscv_implicit_subse
>    {"v", "+zve64d,+zvl128b", check_implicit_always},
>    {"zvfh", "+zvfhmin,+zfhmin", check_implicit_always},
>    {"zvfhmin", "+zve32f", check_implicit_always},
> -  {"zvfbfwma", "+zve32f,+zfbfmin", check_implicit_always},
> +  {"zvfbfwma", "+zfbfmin,+zvfbfmin", check_implicit_always},
>    {"zvfbfmin", "+zve32f", check_implicit_always},
>    {"zve64d", "+d,+zve64f", check_implicit_always},
>    {"zve64f", "+zve32f,+zve64x,+zvl64b", check_implicit_always},
> --- a/gas/testsuite/gas/riscv/imply.d
> +++ b/gas/testsuite/gas/riscv/imply.d
> @@ -27,7 +27,7 @@ SYMBOL TABLE:
>  [0-9a-f]+ l       .text    0+000 
> \$xrv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0
>  [0-9a-f]+ l       .text    0+000 
> \$xrv32i2p1_f2p2_zicsr2p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfh1p0_zvfhmin1p0_zvl32b1p0
>  [0-9a-f]+ l       .text    0+000 
> \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfhmin1p0_zvl32b1p0
> -[0-9a-f]+ l       .text    0+000 
> \$xrv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfbfwma1p0_zvl32b1p0
> +[0-9a-f]+ l       .text    0+000 
> \$xrv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zfhmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0
>  [0-9a-f]+ l       .text    0+000 
> \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0
>  [0-9a-f]+ l       .text    0+000 
> \$xrv32i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0
>  [0-9a-f]+ l       .text    0+000 
> \$xrv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0
>