[PATCH v4 0/1] RISC-V: Add SpacemiT vendor extensions xsmtvdot

[Jan Beulich]

On 10.04.2026 17:11, Mark Zhuang wrote:
> From: Mark Zhuang <mark.zhuang@spacemit.com>
> 
> On 10.04.2026 12:25, Jan Beulich wrote:
>> Doesn't this file need to be named x-smt-vdot-fail.d, for the test to be
>> executed at all? And isn't the real x-smt-vdot-fail.l missing?
> 
> I apologize for not catching this before sending. v4 fix it. Thanks.
> 
>> Only i8 being tested? (And no invalid i<N> in the -fail test?)
> 
> For the SpacemiT K1 chip (X60 core), only i8 is currently implemented
> in hardware, so only i8 being tested. In the v4 update, the fail test
> has been extended to include invalid i<N>

Hmm, depends on how you look at it. Something like "i3" isn't tested for
example.

> Although the K1 hardware only supports i8, we retain handling for
> i2, i4, and i16 in the patch because the upcoming SpacemiT K3 chip
> will utilize them, allowing for code reuse.
> We are currently preparing the documentation and patches for K3.

I'm not a RISC-V maintainer, but if you ask me: Please have testing for
what you implement. That may either mean to drop the handling of "i2",
"i4", and "i16", or properly add support. (I'll comment on that part of
the patch itself, too.)

Jan