[PATCH 2/5] gas: aarch64: Add instructions for GICv5
Alice Carlotti
alice.carlotti@arm.com
Tue Sep 30 18:23:19 GMT 2025
On Tue, Sep 02, 2025 at 06:55:35AM +0100, saurabh.jha@arm.com wrote:
> From: Saurabh Jha <saurabh.jha@arm.com>
>
> Add new instructions from the Generic Interrupt Controller, GICv5,
> extension. These instructions are aliases to system instructions and are
> the following:
>
> * gic <operation>, <reg>
> * gicr <reg>, <operation>
> * gsb <operation>
Just two comments; the rest looks good to me.
Firstly, I think XZR is a valid input/output for the GIC/GICR instructions (at
least from an assembly/disassembly perspective) - could this be included in the
tests please? Incidentally, I don't think it's necessary to test six different
registers for each system instruction (x0 and xzr should be sufficient
coverage), but I've no objection to leaving that in.
Secondly, I think we should check that Rt = 0b11111 before disassembling an
encoding as a GSB instruction, since the behaviour when Rt != 0b11111 is
possibly undefined. This would match the way we (and I believe LLVM) handle
similar instructions like GCSPOPX. In this case you could handle the
restriction simply by updating the value and mask in the opcode table entry.
Of course, this should also get a test (you can just use the SYS alias for
assembly input).
(Incidentally, we do currently ignore Rt when disassembling IC IALLU, and some
other instructions, so perhaps we should adjust those at some point).
Alice
> ---
> gas/config/tc-aarch64.c | 34 ++++
> gas/testsuite/gas/aarch64/gcie-bad.d | 3 +
> gas/testsuite/gas/aarch64/gcie-bad.l | 165 +++++++++++++++++
> gas/testsuite/gas/aarch64/gcie-illegal.d | 3 +
> gas/testsuite/gas/aarch64/gcie-illegal.l | 16 ++
> gas/testsuite/gas/aarch64/gcie-illegal.s | 22 +++
> gas/testsuite/gas/aarch64/gcie.d | 172 ++++++++++++++++++
> gas/testsuite/gas/aarch64/gcie.s | 221 +++++++++++++++++++++++
> include/opcode/aarch64.h | 6 +
> opcodes/aarch64-asm-2.c | 6 +
> opcodes/aarch64-dis-2.c | 14 +-
> opcodes/aarch64-dis.c | 3 +
> opcodes/aarch64-opc-2.c | 3 +
> opcodes/aarch64-opc.c | 47 +++++
> opcodes/aarch64-tbl-2.h | 3 +
> opcodes/aarch64-tbl.h | 15 +-
> 16 files changed, 731 insertions(+), 2 deletions(-)
> create mode 100644 gas/testsuite/gas/aarch64/gcie-bad.d
> create mode 100644 gas/testsuite/gas/aarch64/gcie-bad.l
> create mode 100644 gas/testsuite/gas/aarch64/gcie-illegal.d
> create mode 100644 gas/testsuite/gas/aarch64/gcie-illegal.l
> create mode 100644 gas/testsuite/gas/aarch64/gcie-illegal.s
> create mode 100644 gas/testsuite/gas/aarch64/gcie.d
> create mode 100644 gas/testsuite/gas/aarch64/gcie.s
>
> diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
> index 4e9b60205ff..2813b643427 100644
> --- a/gas/config/tc-aarch64.c
> +++ b/gas/config/tc-aarch64.c
> @@ -564,6 +564,9 @@ static htab_t aarch64_barrier_opt_hsh;
> static htab_t aarch64_nzcv_hsh;
> static htab_t aarch64_pldop_hsh;
> static htab_t aarch64_hint_opt_hsh;
> +static htab_t aarch64_sys_ins_gic_hsh;
> +static htab_t aarch64_sys_ins_gicr_hsh;
> +static htab_t aarch64_sys_ins_gsb_hsh;
>
> /* Stuff needed to resolve the label ambiguity
> As:
> @@ -8080,6 +8083,22 @@ parse_operands (char *str, const aarch64_opcode *opcode)
> case AARCH64_OPND_SYSREG_TLBIP:
> inst.base.operands[i].sysins_op =
> parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh, true);
> + goto sys_reg_ins;
> +
> + case AARCH64_OPND_GIC:
> + inst.base.operands[i].sysins_op =
> + parse_sys_ins_reg (&str, aarch64_sys_ins_gic_hsh, false);
> + goto sys_reg_ins;
> +
> + case AARCH64_OPND_GICR:
> + inst.base.operands[i].sysins_op =
> + parse_sys_ins_reg (&str, aarch64_sys_ins_gicr_hsh, false);
> + goto sys_reg_ins;
> +
> + case AARCH64_OPND_GSB:
> + inst.base.operands[i].sysins_op =
> + parse_sys_ins_reg (&str, aarch64_sys_ins_gsb_hsh, false);
> +
> sys_reg_ins:
> if (inst.base.operands[i].sysins_op == NULL)
> {
> @@ -10413,6 +10432,9 @@ md_begin (void)
> aarch64_nzcv_hsh = str_htab_create ();
> aarch64_pldop_hsh = str_htab_create ();
> aarch64_hint_opt_hsh = str_htab_create ();
> + aarch64_sys_ins_gic_hsh = str_htab_create ();
> + aarch64_sys_ins_gicr_hsh = str_htab_create ();
> + aarch64_sys_ins_gsb_hsh = str_htab_create ();
>
> fill_instruction_hash_table ();
>
> @@ -10536,6 +10558,18 @@ md_begin (void)
> aarch64_hint_options + i);
> }
>
> + for (i = 0; aarch64_sys_ins_gic[i].name != NULL; i++)
> + sysreg_hash_insert (aarch64_sys_ins_gic_hsh, aarch64_sys_ins_gic[i].name,
> + aarch64_sys_ins_gic + i);
> +
> + for (i = 0; aarch64_sys_ins_gicr[i].name != NULL; i++)
> + sysreg_hash_insert (aarch64_sys_ins_gicr_hsh, aarch64_sys_ins_gicr[i].name,
> + aarch64_sys_ins_gicr + i);
> +
> + for (i = 0; aarch64_sys_ins_gsb[i].name != NULL; i++)
> + sysreg_hash_insert (aarch64_sys_ins_gsb_hsh, aarch64_sys_ins_gsb[i].name,
> + aarch64_sys_ins_gsb + i);
> +
> /* Set the cpu variant based on the command-line options. */
> if (!mcpu_cpu_opt)
> mcpu_cpu_opt = march_cpu_opt;
> diff --git a/gas/testsuite/gas/aarch64/gcie-bad.d b/gas/testsuite/gas/aarch64/gcie-bad.d
> new file mode 100644
> index 00000000000..9220a31bc8d
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/gcie-bad.d
> @@ -0,0 +1,3 @@
> +#as:
> +#source: gcie.s
> +#error_output: gcie-bad.l
> diff --git a/gas/testsuite/gas/aarch64/gcie-bad.l b/gas/testsuite/gas/aarch64/gcie-bad.l
> new file mode 100644
> index 00000000000..badf8b18d16
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/gcie-bad.l
> @@ -0,0 +1,165 @@
> +[^ :]+: Assembler messages:
> +.*: Error: selected processor does not support `gic cdaff,x0'
> +.*: Error: selected processor does not support `gic cdaff,x1'
> +.*: Error: selected processor does not support `gic cdaff,x6'
> +.*: Error: selected processor does not support `gic cdaff,x15'
> +.*: Error: selected processor does not support `gic cdaff,x23'
> +.*: Error: selected processor does not support `gic cdaff,x30'
> +.*: Error: selected processor does not support `gic cddi,x0'
> +.*: Error: selected processor does not support `gic cddi,x1'
> +.*: Error: selected processor does not support `gic cddi,x6'
> +.*: Error: selected processor does not support `gic cddi,x15'
> +.*: Error: selected processor does not support `gic cddi,x23'
> +.*: Error: selected processor does not support `gic cddi,x30'
> +.*: Error: selected processor does not support `gic cddis,x0'
> +.*: Error: selected processor does not support `gic cddis,x1'
> +.*: Error: selected processor does not support `gic cddis,x6'
> +.*: Error: selected processor does not support `gic cddis,x15'
> +.*: Error: selected processor does not support `gic cddis,x23'
> +.*: Error: selected processor does not support `gic cddis,x30'
> +.*: Error: selected processor does not support `gic cden,x0'
> +.*: Error: selected processor does not support `gic cden,x1'
> +.*: Error: selected processor does not support `gic cden,x6'
> +.*: Error: selected processor does not support `gic cden,x15'
> +.*: Error: selected processor does not support `gic cden,x23'
> +.*: Error: selected processor does not support `gic cden,x30'
> +.*: Error: selected processor does not support `gic cdeoi,x0'
> +.*: Error: selected processor does not support `gic cdeoi,x1'
> +.*: Error: selected processor does not support `gic cdeoi,x6'
> +.*: Error: selected processor does not support `gic cdeoi,x15'
> +.*: Error: selected processor does not support `gic cdeoi,x23'
> +.*: Error: selected processor does not support `gic cdeoi,x30'
> +.*: Error: selected processor does not support `gic cdhm,x0'
> +.*: Error: selected processor does not support `gic cdhm,x1'
> +.*: Error: selected processor does not support `gic cdhm,x6'
> +.*: Error: selected processor does not support `gic cdhm,x15'
> +.*: Error: selected processor does not support `gic cdhm,x23'
> +.*: Error: selected processor does not support `gic cdhm,x30'
> +.*: Error: selected processor does not support `gic cdpend,x0'
> +.*: Error: selected processor does not support `gic cdpend,x1'
> +.*: Error: selected processor does not support `gic cdpend,x6'
> +.*: Error: selected processor does not support `gic cdpend,x15'
> +.*: Error: selected processor does not support `gic cdpend,x23'
> +.*: Error: selected processor does not support `gic cdpend,x30'
> +.*: Error: selected processor does not support `gic cdpri,x0'
> +.*: Error: selected processor does not support `gic cdpri,x1'
> +.*: Error: selected processor does not support `gic cdpri,x6'
> +.*: Error: selected processor does not support `gic cdpri,x15'
> +.*: Error: selected processor does not support `gic cdpri,x23'
> +.*: Error: selected processor does not support `gic cdpri,x30'
> +.*: Error: selected processor does not support `gic cdrcfg,x0'
> +.*: Error: selected processor does not support `gic cdrcfg,x1'
> +.*: Error: selected processor does not support `gic cdrcfg,x6'
> +.*: Error: selected processor does not support `gic cdrcfg,x15'
> +.*: Error: selected processor does not support `gic cdrcfg,x23'
> +.*: Error: selected processor does not support `gic cdrcfg,x30'
> +.*: Error: selected processor does not support `gicr x0,cdia'
> +.*: Error: selected processor does not support `gicr x1,cdia'
> +.*: Error: selected processor does not support `gicr x6,cdia'
> +.*: Error: selected processor does not support `gicr x15,cdia'
> +.*: Error: selected processor does not support `gicr x23,cdia'
> +.*: Error: selected processor does not support `gicr x30,cdia'
> +.*: Error: selected processor does not support `gicr x0,cdnmia'
> +.*: Error: selected processor does not support `gicr x1,cdnmia'
> +.*: Error: selected processor does not support `gicr x6,cdnmia'
> +.*: Error: selected processor does not support `gicr x15,cdnmia'
> +.*: Error: selected processor does not support `gicr x23,cdnmia'
> +.*: Error: selected processor does not support `gicr x30,cdnmia'
> +.*: Error: selected processor does not support `gic vdaff,x0'
> +.*: Error: selected processor does not support `gic vdaff,x1'
> +.*: Error: selected processor does not support `gic vdaff,x6'
> +.*: Error: selected processor does not support `gic vdaff,x15'
> +.*: Error: selected processor does not support `gic vdaff,x23'
> +.*: Error: selected processor does not support `gic vdaff,x30'
> +.*: Error: selected processor does not support `gic vddi,x0'
> +.*: Error: selected processor does not support `gic vddi,x1'
> +.*: Error: selected processor does not support `gic vddi,x6'
> +.*: Error: selected processor does not support `gic vddi,x15'
> +.*: Error: selected processor does not support `gic vddi,x23'
> +.*: Error: selected processor does not support `gic vddi,x30'
> +.*: Error: selected processor does not support `gic vddis,x0'
> +.*: Error: selected processor does not support `gic vddis,x1'
> +.*: Error: selected processor does not support `gic vddis,x6'
> +.*: Error: selected processor does not support `gic vddis,x15'
> +.*: Error: selected processor does not support `gic vddis,x23'
> +.*: Error: selected processor does not support `gic vddis,x30'
> +.*: Error: selected processor does not support `gic vden,x0'
> +.*: Error: selected processor does not support `gic vden,x1'
> +.*: Error: selected processor does not support `gic vden,x6'
> +.*: Error: selected processor does not support `gic vden,x15'
> +.*: Error: selected processor does not support `gic vden,x23'
> +.*: Error: selected processor does not support `gic vden,x30'
> +.*: Error: selected processor does not support `gic vdhm,x0'
> +.*: Error: selected processor does not support `gic vdhm,x1'
> +.*: Error: selected processor does not support `gic vdhm,x6'
> +.*: Error: selected processor does not support `gic vdhm,x15'
> +.*: Error: selected processor does not support `gic vdhm,x23'
> +.*: Error: selected processor does not support `gic vdhm,x30'
> +.*: Error: selected processor does not support `gic vdpend,x0'
> +.*: Error: selected processor does not support `gic vdpend,x1'
> +.*: Error: selected processor does not support `gic vdpend,x6'
> +.*: Error: selected processor does not support `gic vdpend,x15'
> +.*: Error: selected processor does not support `gic vdpend,x23'
> +.*: Error: selected processor does not support `gic vdpend,x30'
> +.*: Error: selected processor does not support `gic vdpri,x0'
> +.*: Error: selected processor does not support `gic vdpri,x1'
> +.*: Error: selected processor does not support `gic vdpri,x6'
> +.*: Error: selected processor does not support `gic vdpri,x15'
> +.*: Error: selected processor does not support `gic vdpri,x23'
> +.*: Error: selected processor does not support `gic vdpri,x30'
> +.*: Error: selected processor does not support `gic vdrcfg,x0'
> +.*: Error: selected processor does not support `gic vdrcfg,x1'
> +.*: Error: selected processor does not support `gic vdrcfg,x6'
> +.*: Error: selected processor does not support `gic vdrcfg,x15'
> +.*: Error: selected processor does not support `gic vdrcfg,x23'
> +.*: Error: selected processor does not support `gic vdrcfg,x30'
> +.*: Error: selected processor does not support `gic ldaff,x0'
> +.*: Error: selected processor does not support `gic ldaff,x1'
> +.*: Error: selected processor does not support `gic ldaff,x6'
> +.*: Error: selected processor does not support `gic ldaff,x15'
> +.*: Error: selected processor does not support `gic ldaff,x23'
> +.*: Error: selected processor does not support `gic ldaff,x30'
> +.*: Error: selected processor does not support `gic lddi,x0'
> +.*: Error: selected processor does not support `gic lddi,x1'
> +.*: Error: selected processor does not support `gic lddi,x6'
> +.*: Error: selected processor does not support `gic lddi,x15'
> +.*: Error: selected processor does not support `gic lddi,x23'
> +.*: Error: selected processor does not support `gic lddi,x30'
> +.*: Error: selected processor does not support `gic lddis,x0'
> +.*: Error: selected processor does not support `gic lddis,x1'
> +.*: Error: selected processor does not support `gic lddis,x6'
> +.*: Error: selected processor does not support `gic lddis,x15'
> +.*: Error: selected processor does not support `gic lddis,x23'
> +.*: Error: selected processor does not support `gic lddis,x30'
> +.*: Error: selected processor does not support `gic lden,x0'
> +.*: Error: selected processor does not support `gic lden,x1'
> +.*: Error: selected processor does not support `gic lden,x6'
> +.*: Error: selected processor does not support `gic lden,x15'
> +.*: Error: selected processor does not support `gic lden,x23'
> +.*: Error: selected processor does not support `gic lden,x30'
> +.*: Error: selected processor does not support `gic ldhm,x0'
> +.*: Error: selected processor does not support `gic ldhm,x1'
> +.*: Error: selected processor does not support `gic ldhm,x6'
> +.*: Error: selected processor does not support `gic ldhm,x15'
> +.*: Error: selected processor does not support `gic ldhm,x23'
> +.*: Error: selected processor does not support `gic ldhm,x30'
> +.*: Error: selected processor does not support `gic ldpend,x0'
> +.*: Error: selected processor does not support `gic ldpend,x1'
> +.*: Error: selected processor does not support `gic ldpend,x6'
> +.*: Error: selected processor does not support `gic ldpend,x15'
> +.*: Error: selected processor does not support `gic ldpend,x23'
> +.*: Error: selected processor does not support `gic ldpend,x30'
> +.*: Error: selected processor does not support `gic ldpri,x0'
> +.*: Error: selected processor does not support `gic ldpri,x1'
> +.*: Error: selected processor does not support `gic ldpri,x6'
> +.*: Error: selected processor does not support `gic ldpri,x15'
> +.*: Error: selected processor does not support `gic ldpri,x23'
> +.*: Error: selected processor does not support `gic ldpri,x30'
> +.*: Error: selected processor does not support `gic ldrcfg,x0'
> +.*: Error: selected processor does not support `gic ldrcfg,x1'
> +.*: Error: selected processor does not support `gic ldrcfg,x6'
> +.*: Error: selected processor does not support `gic ldrcfg,x15'
> +.*: Error: selected processor does not support `gic ldrcfg,x23'
> +.*: Error: selected processor does not support `gic ldrcfg,x30'
> +.*: Error: selected processor does not support `gsb sys'
> +.*: Error: selected processor does not support `gsb ack'
> diff --git a/gas/testsuite/gas/aarch64/gcie-illegal.d b/gas/testsuite/gas/aarch64/gcie-illegal.d
> new file mode 100644
> index 00000000000..85a2b99eccf
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/gcie-illegal.d
> @@ -0,0 +1,3 @@
> +#as: -march=armv8-a+gcie
> +#source: gcie-illegal.s
> +#error_output: gcie-illegal.l
> diff --git a/gas/testsuite/gas/aarch64/gcie-illegal.l b/gas/testsuite/gas/aarch64/gcie-illegal.l
> new file mode 100644
> index 00000000000..48966e6fcea
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/gcie-illegal.l
> @@ -0,0 +1,16 @@
> +[^ :]+: Assembler messages:
> +[^ :]+:[0-9]+: Error: comma expected between operands at operand 2 -- `gic cdaff'
> +[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `gic cdaff,'
> +[^ :]+:[0-9]+: Error: comma expected between operands at operand 2 -- `gicr x0'
> +[^ :]+:[0-9]+: Error: unknown or missing operation name at operand 2 -- `gicr x0,'
> +[^ :]+:[0-9]+: Error: unknown or missing operation name at operand 1 -- `gsb'
> +[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 2 -- `gic cdaff,x0,x1'
> +[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 2 -- `gicr x0,cdia,x1'
> +[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 1 -- `gsb ack,x0'
> +[^ :]+:[0-9]+: Error: unknown or missing operation name at operand 1 -- `gic x0'
> +[^ :]+:[0-9]+: Error: unknown or missing operation name at operand 1 -- `gic x0,cdaff'
> +[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 1 -- `gicr cdia'
> +[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 1 -- `gicr cdia,x0'
> +[^ :]+:[0-9]+: Error: unknown or missing operation name at operand 1 -- `gic cdwat,x0'
> +[^ :]+:[0-9]+: Error: unknown or missing operation name at operand 2 -- `gicr x0,cdwat'
> +[^ :]+:[0-9]+: Error: unknown or missing operation name at operand 1 -- `gsb awt'
> diff --git a/gas/testsuite/gas/aarch64/gcie-illegal.s b/gas/testsuite/gas/aarch64/gcie-illegal.s
> new file mode 100644
> index 00000000000..18d3d988851
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/gcie-illegal.s
> @@ -0,0 +1,22 @@
> + // Less operands
> + gic cdaff
> + gic cdaff,
> + gicr x0
> + gicr x0,
> + gsb
> +
> + // More operands
> + gic cdaff, x0, x1
> + gicr x0, cdia, x1
> + gsb ack, x0
> +
> + // Incorrect operands
> + gic x0
> + gic x0, cdaff
> + gicr cdia
> + gicr cdia, x0
> +
> + // Incorrect operation
> + gic cdwat, x0
> + gicr x0, cdwat
> + gsb awt
> diff --git a/gas/testsuite/gas/aarch64/gcie.d b/gas/testsuite/gas/aarch64/gcie.d
> new file mode 100644
> index 00000000000..c50541a8553
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/gcie.d
> @@ -0,0 +1,172 @@
> +#objdump: -dr
> +#as: -march=armv8-a+gcie
> +
> +.*: file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <.*>:
> +[^:]+: d508c160 gic cdaff, x0
> +[^:]+: d508c161 gic cdaff, x1
> +[^:]+: d508c166 gic cdaff, x6
> +[^:]+: d508c16f gic cdaff, x15
> +[^:]+: d508c177 gic cdaff, x23
> +[^:]+: d508c17e gic cdaff, x30
> +[^:]+: d508c200 gic cddi, x0
> +[^:]+: d508c201 gic cddi, x1
> +[^:]+: d508c206 gic cddi, x6
> +[^:]+: d508c20f gic cddi, x15
> +[^:]+: d508c217 gic cddi, x23
> +[^:]+: d508c21e gic cddi, x30
> +[^:]+: d508c100 gic cddis, x0
> +[^:]+: d508c101 gic cddis, x1
> +[^:]+: d508c106 gic cddis, x6
> +[^:]+: d508c10f gic cddis, x15
> +[^:]+: d508c117 gic cddis, x23
> +[^:]+: d508c11e gic cddis, x30
> +[^:]+: d508c120 gic cden, x0
> +[^:]+: d508c121 gic cden, x1
> +[^:]+: d508c126 gic cden, x6
> +[^:]+: d508c12f gic cden, x15
> +[^:]+: d508c137 gic cden, x23
> +[^:]+: d508c13e gic cden, x30
> +[^:]+: d508c1e0 gic cdeoi, x0
> +[^:]+: d508c1e1 gic cdeoi, x1
> +[^:]+: d508c1e6 gic cdeoi, x6
> +[^:]+: d508c1ef gic cdeoi, x15
> +[^:]+: d508c1f7 gic cdeoi, x23
> +[^:]+: d508c1fe gic cdeoi, x30
> +[^:]+: d508c220 gic cdhm, x0
> +[^:]+: d508c221 gic cdhm, x1
> +[^:]+: d508c226 gic cdhm, x6
> +[^:]+: d508c22f gic cdhm, x15
> +[^:]+: d508c237 gic cdhm, x23
> +[^:]+: d508c23e gic cdhm, x30
> +[^:]+: d508c180 gic cdpend, x0
> +[^:]+: d508c181 gic cdpend, x1
> +[^:]+: d508c186 gic cdpend, x6
> +[^:]+: d508c18f gic cdpend, x15
> +[^:]+: d508c197 gic cdpend, x23
> +[^:]+: d508c19e gic cdpend, x30
> +[^:]+: d508c140 gic cdpri, x0
> +[^:]+: d508c141 gic cdpri, x1
> +[^:]+: d508c146 gic cdpri, x6
> +[^:]+: d508c14f gic cdpri, x15
> +[^:]+: d508c157 gic cdpri, x23
> +[^:]+: d508c15e gic cdpri, x30
> +[^:]+: d508c1a0 gic cdrcfg, x0
> +[^:]+: d508c1a1 gic cdrcfg, x1
> +[^:]+: d508c1a6 gic cdrcfg, x6
> +[^:]+: d508c1af gic cdrcfg, x15
> +[^:]+: d508c1b7 gic cdrcfg, x23
> +[^:]+: d508c1be gic cdrcfg, x30
> +[^:]+: d508c300 gicr x0, cdia
> +[^:]+: d508c301 gicr x1, cdia
> +[^:]+: d508c306 gicr x6, cdia
> +[^:]+: d508c30f gicr x15, cdia
> +[^:]+: d508c317 gicr x23, cdia
> +[^:]+: d508c31e gicr x30, cdia
> +[^:]+: d508c320 gicr x0, cdnmia
> +[^:]+: d508c321 gicr x1, cdnmia
> +[^:]+: d508c326 gicr x6, cdnmia
> +[^:]+: d508c32f gicr x15, cdnmia
> +[^:]+: d508c337 gicr x23, cdnmia
> +[^:]+: d508c33e gicr x30, cdnmia
> +[^:]+: d50cc160 gic vdaff, x0
> +[^:]+: d50cc161 gic vdaff, x1
> +[^:]+: d50cc166 gic vdaff, x6
> +[^:]+: d50cc16f gic vdaff, x15
> +[^:]+: d50cc177 gic vdaff, x23
> +[^:]+: d50cc17e gic vdaff, x30
> +[^:]+: d50cc200 gic vddi, x0
> +[^:]+: d50cc201 gic vddi, x1
> +[^:]+: d50cc206 gic vddi, x6
> +[^:]+: d50cc20f gic vddi, x15
> +[^:]+: d50cc217 gic vddi, x23
> +[^:]+: d50cc21e gic vddi, x30
> +[^:]+: d50cc100 gic vddis, x0
> +[^:]+: d50cc101 gic vddis, x1
> +[^:]+: d50cc106 gic vddis, x6
> +[^:]+: d50cc10f gic vddis, x15
> +[^:]+: d50cc117 gic vddis, x23
> +[^:]+: d50cc11e gic vddis, x30
> +[^:]+: d50cc120 gic vden, x0
> +[^:]+: d50cc121 gic vden, x1
> +[^:]+: d50cc126 gic vden, x6
> +[^:]+: d50cc12f gic vden, x15
> +[^:]+: d50cc137 gic vden, x23
> +[^:]+: d50cc13e gic vden, x30
> +[^:]+: d50cc220 gic vdhm, x0
> +[^:]+: d50cc221 gic vdhm, x1
> +[^:]+: d50cc226 gic vdhm, x6
> +[^:]+: d50cc22f gic vdhm, x15
> +[^:]+: d50cc237 gic vdhm, x23
> +[^:]+: d50cc23e gic vdhm, x30
> +[^:]+: d50cc180 gic vdpend, x0
> +[^:]+: d50cc181 gic vdpend, x1
> +[^:]+: d50cc186 gic vdpend, x6
> +[^:]+: d50cc18f gic vdpend, x15
> +[^:]+: d50cc197 gic vdpend, x23
> +[^:]+: d50cc19e gic vdpend, x30
> +[^:]+: d50cc140 gic vdpri, x0
> +[^:]+: d50cc141 gic vdpri, x1
> +[^:]+: d50cc146 gic vdpri, x6
> +[^:]+: d50cc14f gic vdpri, x15
> +[^:]+: d50cc157 gic vdpri, x23
> +[^:]+: d50cc15e gic vdpri, x30
> +[^:]+: d50cc1a0 gic vdrcfg, x0
> +[^:]+: d50cc1a1 gic vdrcfg, x1
> +[^:]+: d50cc1a6 gic vdrcfg, x6
> +[^:]+: d50cc1af gic vdrcfg, x15
> +[^:]+: d50cc1b7 gic vdrcfg, x23
> +[^:]+: d50cc1be gic vdrcfg, x30
> +[^:]+: d50ec160 gic ldaff, x0
> +[^:]+: d50ec161 gic ldaff, x1
> +[^:]+: d50ec166 gic ldaff, x6
> +[^:]+: d50ec16f gic ldaff, x15
> +[^:]+: d50ec177 gic ldaff, x23
> +[^:]+: d50ec17e gic ldaff, x30
> +[^:]+: d50ec200 gic lddi, x0
> +[^:]+: d50ec201 gic lddi, x1
> +[^:]+: d50ec206 gic lddi, x6
> +[^:]+: d50ec20f gic lddi, x15
> +[^:]+: d50ec217 gic lddi, x23
> +[^:]+: d50ec21e gic lddi, x30
> +[^:]+: d50ec100 gic lddis, x0
> +[^:]+: d50ec101 gic lddis, x1
> +[^:]+: d50ec106 gic lddis, x6
> +[^:]+: d50ec10f gic lddis, x15
> +[^:]+: d50ec117 gic lddis, x23
> +[^:]+: d50ec11e gic lddis, x30
> +[^:]+: d50ec120 gic lden, x0
> +[^:]+: d50ec121 gic lden, x1
> +[^:]+: d50ec126 gic lden, x6
> +[^:]+: d50ec12f gic lden, x15
> +[^:]+: d50ec137 gic lden, x23
> +[^:]+: d50ec13e gic lden, x30
> +[^:]+: d50ec220 gic ldhm, x0
> +[^:]+: d50ec221 gic ldhm, x1
> +[^:]+: d50ec226 gic ldhm, x6
> +[^:]+: d50ec22f gic ldhm, x15
> +[^:]+: d50ec237 gic ldhm, x23
> +[^:]+: d50ec23e gic ldhm, x30
> +[^:]+: d50ec180 gic ldpend, x0
> +[^:]+: d50ec181 gic ldpend, x1
> +[^:]+: d50ec186 gic ldpend, x6
> +[^:]+: d50ec18f gic ldpend, x15
> +[^:]+: d50ec197 gic ldpend, x23
> +[^:]+: d50ec19e gic ldpend, x30
> +[^:]+: d50ec140 gic ldpri, x0
> +[^:]+: d50ec141 gic ldpri, x1
> +[^:]+: d50ec146 gic ldpri, x6
> +[^:]+: d50ec14f gic ldpri, x15
> +[^:]+: d50ec157 gic ldpri, x23
> +[^:]+: d50ec15e gic ldpri, x30
> +[^:]+: d50ec1a0 gic ldrcfg, x0
> +[^:]+: d50ec1a1 gic ldrcfg, x1
> +[^:]+: d50ec1a6 gic ldrcfg, x6
> +[^:]+: d50ec1af gic ldrcfg, x15
> +[^:]+: d50ec1b7 gic ldrcfg, x23
> +[^:]+: d50ec1be gic ldrcfg, x30
> +[^:]+: d508c000 gsb sys
> +[^:]+: d508c020 gsb ack
> diff --git a/gas/testsuite/gas/aarch64/gcie.s b/gas/testsuite/gas/aarch64/gcie.s
> new file mode 100644
> index 00000000000..21c4049ee88
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/gcie.s
> @@ -0,0 +1,221 @@
> + // GIC CDAFF
> + gic cdaff, x0
> + gic cdaff, x1
> + gic cdaff, x6
> + gic cdaff, x15
> + gic cdaff, x23
> + gic cdaff, x30
> +
> + // GIC CDDI
> + gic cddi, x0
> + gic cddi, x1
> + gic cddi, x6
> + gic cddi, x15
> + gic cddi, x23
> + gic cddi, x30
> +
> + // GIC CDDIS
> + gic cddis, x0
> + gic cddis, x1
> + gic cddis, x6
> + gic cddis, x15
> + gic cddis, x23
> + gic cddis, x30
> +
> + // GIC CDEN
> + gic cden, x0
> + gic cden, x1
> + gic cden, x6
> + gic cden, x15
> + gic cden, x23
> + gic cden, x30
> +
> + // GIC CDEOI
> + gic cdeoi, x0
> + gic cdeoi, x1
> + gic cdeoi, x6
> + gic cdeoi, x15
> + gic cdeoi, x23
> + gic cdeoi, x30
> +
> + // GIC CDHM
> + gic cdhm, x0
> + gic cdhm, x1
> + gic cdhm, x6
> + gic cdhm, x15
> + gic cdhm, x23
> + gic cdhm, x30
> +
> + // GIC CDPEND
> + gic cdpend, x0
> + gic cdpend, x1
> + gic cdpend, x6
> + gic cdpend, x15
> + gic cdpend, x23
> + gic cdpend, x30
> +
> + // GIC CDPRI
> + gic cdpri, x0
> + gic cdpri, x1
> + gic cdpri, x6
> + gic cdpri, x15
> + gic cdpri, x23
> + gic cdpri, x30
> +
> + // GIC CDRCFG
> + gic cdrcfg, x0
> + gic cdrcfg, x1
> + gic cdrcfg, x6
> + gic cdrcfg, x15
> + gic cdrcfg, x23
> + gic cdrcfg, x30
> +
> + // GICR CDIA
> + gicr x0, cdia
> + gicr x1, cdia
> + gicr x6, cdia
> + gicr x15, cdia
> + gicr x23, cdia
> + gicr x30, cdia
> +
> + // GICR CDNMIA
> + gicr x0, cdnmia
> + gicr x1, cdnmia
> + gicr x6, cdnmia
> + gicr x15, cdnmia
> + gicr x23, cdnmia
> + gicr x30, cdnmia
> +
> + // GIC VDAFF
> + gic vdaff, x0
> + gic vdaff, x1
> + gic vdaff, x6
> + gic vdaff, x15
> + gic vdaff, x23
> + gic vdaff, x30
> +
> + // GIC VDDI
> + gic vddi, x0
> + gic vddi, x1
> + gic vddi, x6
> + gic vddi, x15
> + gic vddi, x23
> + gic vddi, x30
> +
> + // GIC VDDIS
> + gic vddis, x0
> + gic vddis, x1
> + gic vddis, x6
> + gic vddis, x15
> + gic vddis, x23
> + gic vddis, x30
> +
> + // GIC VDEN
> + gic vden, x0
> + gic vden, x1
> + gic vden, x6
> + gic vden, x15
> + gic vden, x23
> + gic vden, x30
> +
> + // GIC VDHM
> + gic vdhm, x0
> + gic vdhm, x1
> + gic vdhm, x6
> + gic vdhm, x15
> + gic vdhm, x23
> + gic vdhm, x30
> +
> + // GIC VDPEND
> + gic vdpend, x0
> + gic vdpend, x1
> + gic vdpend, x6
> + gic vdpend, x15
> + gic vdpend, x23
> + gic vdpend, x30
> +
> + // GIC VDPRI
> + gic vdpri, x0
> + gic vdpri, x1
> + gic vdpri, x6
> + gic vdpri, x15
> + gic vdpri, x23
> + gic vdpri, x30
> +
> + // GIC VDRCFG
> + gic vdrcfg, x0
> + gic vdrcfg, x1
> + gic vdrcfg, x6
> + gic vdrcfg, x15
> + gic vdrcfg, x23
> + gic vdrcfg, x30
> +
> + // GIC LDAFF
> + gic ldaff, x0
> + gic ldaff, x1
> + gic ldaff, x6
> + gic ldaff, x15
> + gic ldaff, x23
> + gic ldaff, x30
> +
> + // GIC LDDI
> + gic lddi, x0
> + gic lddi, x1
> + gic lddi, x6
> + gic lddi, x15
> + gic lddi, x23
> + gic lddi, x30
> +
> + // GIC LDDIS
> + gic lddis, x0
> + gic lddis, x1
> + gic lddis, x6
> + gic lddis, x15
> + gic lddis, x23
> + gic lddis, x30
> +
> + // GIC LDEN
> + gic lden, x0
> + gic lden, x1
> + gic lden, x6
> + gic lden, x15
> + gic lden, x23
> + gic lden, x30
> +
> + // GIC LDHM
> + gic ldhm, x0
> + gic ldhm, x1
> + gic ldhm, x6
> + gic ldhm, x15
> + gic ldhm, x23
> + gic ldhm, x30
> +
> + // GIC LDPEND
> + gic ldpend, x0
> + gic ldpend, x1
> + gic ldpend, x6
> + gic ldpend, x15
> + gic ldpend, x23
> + gic ldpend, x30
> +
> + // GIC LDPRI
> + gic ldpri, x0
> + gic ldpri, x1
> + gic ldpri, x6
> + gic ldpri, x15
> + gic ldpri, x23
> + gic ldpri, x30
> +
> + // GIC LDRCFG
> + gic ldrcfg, x0
> + gic ldrcfg, x1
> + gic ldrcfg, x6
> + gic ldrcfg, x15
> + gic ldrcfg, x23
> + gic ldrcfg, x30
> +
> + // GSB SYS
> + gsb sys
> +
> + // GSB ACK
> + gsb ack
> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
> index ee98a711ce4..9485e72dc4d 100644
> --- a/include/opcode/aarch64.h
> +++ b/include/opcode/aarch64.h
> @@ -1027,6 +1027,9 @@ enum aarch64_opnd
> AARCH64_OPND_RCPC3_ADDR_POSTIND, /* [<Xn|SP>], #<imm>. */
> AARCH64_OPND_RCPC3_ADDR_PREIND_WB, /* [<Xn|SP>, #<imm>]!. */
> AARCH64_OPND_RCPC3_ADDR_OFFSET,
> + AARCH64_OPND_GIC,
> + AARCH64_OPND_GICR,
> + AARCH64_OPND_GSB,
> };
>
> /* Qualifier constrains an operand. It either specifies a variant of an
> @@ -1711,6 +1714,9 @@ extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
> extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
> extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
> extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
> +extern const aarch64_sys_ins_reg aarch64_sys_ins_gic [];
> +extern const aarch64_sys_ins_reg aarch64_sys_ins_gicr [];
> +extern const aarch64_sys_ins_reg aarch64_sys_ins_gsb [];
> extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
>
> /* Shift/extending operator kinds.
> diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
> index fa3866781e4..ac0bf7a70be 100644
> --- a/opcodes/aarch64-asm-2.c
> +++ b/opcodes/aarch64-asm-2.c
> @@ -556,6 +556,9 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
> case A64_OPID_d503323f_dsb_BARRIER_DSB_NXS:
> value = A64_OPID_d503323f_dsb_BARRIER_DSB_NXS;
> break;
> + case A64_OPID_d5080000_gsb_GSB:
> + case A64_OPID_d5080000_gicr_Rd_GICR:
> + case A64_OPID_d5080000_gic_GIC_Rd:
> case A64_OPID_d50b72e0_trcit_Rt:
> case A64_OPID_d5097280_brb_BRBOP_Rt_IN_SYS_ALIASES:
> case A64_OPID_d50b73c0_cosp_SYSREG_SR_Rt:
> @@ -1012,6 +1015,9 @@ aarch64_insert_operand (const aarch64_operand *self,
> case AARCH64_OPND_SYSREG_TLBI:
> case AARCH64_OPND_SYSREG_TLBIP:
> case AARCH64_OPND_SYSREG_SR:
> + case AARCH64_OPND_GIC:
> + case AARCH64_OPND_GICR:
> + case AARCH64_OPND_GSB:
> return aarch64_ins_sysins_op (self, info, code, inst, errors);
> case AARCH64_OPND_BARRIER:
> case AARCH64_OPND_BARRIER_ISB:
> diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
> index 6e66d54885b..275d295d7f9 100644
> --- a/opcodes/aarch64-dis-2.c
> +++ b/opcodes/aarch64-dis-2.c
> @@ -34859,7 +34859,7 @@ aarch64_find_alias_opcode (const aarch64_opcode *opcode)
> value = A64_OPID_d503323f_dsb_BARRIER_DSB_NXS;
> break;
> case A64_OPID_d5080000_sys_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt:
> - value = A64_OPID_d50b72e0_trcit_Rt;
> + value = A64_OPID_d5080000_gsb_GSB;
> break;
> case A64_OPID_d5480000_sysp_UIMM3_OP1_CRn_CRm_UIMM3_OP2_Rt_PAIRREG_OR_XZR:
> value = A64_OPID_d5480000_tlbip_SYSREG_TLBIP_Rt_SYS_PAIRREG_OR_XZR;
> @@ -35508,6 +35508,15 @@ aarch64_find_next_alias_opcode (const aarch64_opcode *opcode)
> case A64_OPID_d5033c9f_dfb:
> value = A64_OPID_d503309f_dsb_BARRIER;
> break;
> + case A64_OPID_d5080000_gsb_GSB:
> + value = A64_OPID_d5080000_gicr_Rd_GICR;
> + break;
> + case A64_OPID_d5080000_gicr_Rd_GICR:
> + value = A64_OPID_d5080000_gic_GIC_Rd;
> + break;
> + case A64_OPID_d5080000_gic_GIC_Rd:
> + value = A64_OPID_d50b72e0_trcit_Rt;
> + break;
> case A64_OPID_d50b72e0_trcit_Rt:
> value = A64_OPID_d5097280_brb_BRBOP_Rt_IN_SYS_ALIASES;
> break;
> @@ -35946,6 +35955,9 @@ aarch64_extract_operand (const aarch64_operand *self,
> case AARCH64_OPND_SYSREG_TLBI:
> case AARCH64_OPND_SYSREG_TLBIP:
> case AARCH64_OPND_SYSREG_SR:
> + case AARCH64_OPND_GIC:
> + case AARCH64_OPND_GICR:
> + case AARCH64_OPND_GSB:
> return aarch64_ext_sysins_op (self, info, code, inst, errors);
> case AARCH64_OPND_BARRIER:
> case AARCH64_OPND_BARRIER_ISB:
> diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
> index 3ca22bb5c8a..4a4be31c813 100644
> --- a/opcodes/aarch64-dis.c
> +++ b/opcodes/aarch64-dis.c
> @@ -1428,6 +1428,9 @@ aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED,
>
> switch (info->type)
> {
> + case AARCH64_OPND_GIC: sysins_ops = aarch64_sys_ins_gic; break;
> + case AARCH64_OPND_GICR: sysins_ops = aarch64_sys_ins_gicr; break;
> + case AARCH64_OPND_GSB: sysins_ops = aarch64_sys_ins_gsb; break;
> case AARCH64_OPND_SYSREG_AT: sysins_ops = aarch64_sys_regs_at; break;
> case AARCH64_OPND_SYSREG_DC: sysins_ops = aarch64_sys_regs_dc; break;
> case AARCH64_OPND_SYSREG_IC: sysins_ops = aarch64_sys_regs_ic; break;
> diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
> index c70824a615d..90cbf8fd0bf 100644
> --- a/opcodes/aarch64-opc-2.c
> +++ b/opcodes/aarch64-opc-2.c
> @@ -364,6 +364,9 @@ const struct aarch64_operand aarch64_operands[] =
> {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_POSTIND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with post-incrementing by ammount of loaded bytes"},
> {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_PREIND_WB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with pre-incrementing with write-back by ammount of stored bytes"},
> {AARCH64_OPND_CLASS_ADDRESS, "RCPC3_ADDR_OFFSET", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm9}, "an address with an optional 8-bit signed immediate offset"},
> + {AARCH64_OPND_CLASS_SYSTEM, "GIC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "Generic Interrupt Controller"},
> + {AARCH64_OPND_CLASS_SYSTEM, "GICR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "Generic Interrupt Controller"},
> + {AARCH64_OPND_CLASS_SYSTEM, "GSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "Generic Interrupt Controller Synchronization Barrier"},
> {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"},
> };
>
> diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
> index 5980841c394..efb290c3bd1 100644
> --- a/opcodes/aarch64-opc.c
> +++ b/opcodes/aarch64-opc.c
> @@ -5019,6 +5019,9 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
> style_reg (styler, aarch64_pstatefields[i].name));
> break;
>
> + case AARCH64_OPND_GIC:
> + case AARCH64_OPND_GICR:
> + case AARCH64_OPND_GSB:
> case AARCH64_OPND_SYSREG_AT:
> case AARCH64_OPND_SYSREG_DC:
> case AARCH64_OPND_SYSREG_IC:
> @@ -5396,6 +5399,50 @@ const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
> { 0, CPENS(0,0,0,0), 0, AARCH64_NO_FEATURES }
> };
>
> +const aarch64_sys_ins_reg aarch64_sys_ins_gic[] =
> +{
> + { "cdaff", CPENS (0,C12,C1,3), 0, AARCH64_NO_FEATURES },
> + { "cddi", CPENS (0,C12,C2,0), 0, AARCH64_NO_FEATURES },
> + { "cddis", CPENS (0,C12,C1,0), 0, AARCH64_NO_FEATURES },
> + { "cden", CPENS (0,C12,C1,1), 0, AARCH64_NO_FEATURES },
> + { "cdeoi", CPENS (0,C12,C1,7), 0, AARCH64_NO_FEATURES },
> + { "cdhm", CPENS (0,C12,C2,1), 0, AARCH64_NO_FEATURES },
> + { "cdpend", CPENS (0,C12,C1,4), 0, AARCH64_NO_FEATURES },
> + { "cdpri", CPENS (0,C12,C1,2), 0, AARCH64_NO_FEATURES },
> + { "cdrcfg", CPENS (0,C12,C1,5), 0, AARCH64_NO_FEATURES },
> + { "vdaff", CPENS (4,C12,C1,3), 0, AARCH64_NO_FEATURES },
> + { "vddi", CPENS (4,C12,C2,0), 0, AARCH64_NO_FEATURES },
> + { "vddis", CPENS (4,C12,C1,0), 0, AARCH64_NO_FEATURES },
> + { "vden", CPENS (4,C12,C1,1), 0, AARCH64_NO_FEATURES },
> + { "vdhm", CPENS (4,C12,C2,1), 0, AARCH64_NO_FEATURES },
> + { "vdpend", CPENS (4,C12,C1,4), 0, AARCH64_NO_FEATURES },
> + { "vdpri", CPENS (4,C12,C1,2), 0, AARCH64_NO_FEATURES },
> + { "vdrcfg", CPENS (4,C12,C1,5), 0, AARCH64_NO_FEATURES },
> + { "ldaff", CPENS (6,C12,C1,3), 0, AARCH64_NO_FEATURES },
> + { "lddi", CPENS (6,C12,C2,0), 0, AARCH64_NO_FEATURES },
> + { "lddis", CPENS (6,C12,C1,0), 0, AARCH64_NO_FEATURES },
> + { "lden", CPENS (6,C12,C1,1), 0, AARCH64_NO_FEATURES },
> + { "ldhm", CPENS (6,C12,C2,1), 0, AARCH64_NO_FEATURES },
> + { "ldpend", CPENS (6,C12,C1,4), 0, AARCH64_NO_FEATURES },
> + { "ldpri", CPENS (6,C12,C1,2), 0, AARCH64_NO_FEATURES },
> + { "ldrcfg", CPENS (6,C12,C1,5), 0, AARCH64_NO_FEATURES },
> + { 0, CPENS (0,0,0,0), 0, AARCH64_NO_FEATURES }
> +};
> +
> +const aarch64_sys_ins_reg aarch64_sys_ins_gicr[] =
> +{
> + { "cdia", CPENS (0,C12,C3,0), 0, AARCH64_NO_FEATURES },
> + { "cdnmia", CPENS (0,C12,C3,1), 0, AARCH64_NO_FEATURES },
> + { 0, CPENS (0,0,0,0), 0, AARCH64_NO_FEATURES }
> +};
> +
> +const aarch64_sys_ins_reg aarch64_sys_ins_gsb[] =
> +{
> + { "sys", CPENS (0,C12,0,0), 0, AARCH64_NO_FEATURES },
> + { "ack", CPENS (0,C12,0,1), 0, AARCH64_NO_FEATURES },
> + { 0, CPENS (0,0,0,0), 0, AARCH64_NO_FEATURES }
> +};
> +
> const aarch64_sys_ins_reg aarch64_sys_regs_sr[] =
> {
> /* RCTX is somewhat unique in a way that it has different values
> diff --git a/opcodes/aarch64-tbl-2.h b/opcodes/aarch64-tbl-2.h
> index 808a6c5ad5b..01a984dd849 100644
> --- a/opcodes/aarch64-tbl-2.h
> +++ b/opcodes/aarch64-tbl-2.h
> @@ -3843,5 +3843,8 @@ enum aarch64_opcode_idx
> A64_OPID_c121e800_fmul_SME_Zdnx4_SME_Znx4_SME_Zm_17,
> A64_OPID_c120e400_fmul_SME_Zdnx2_SME_Znx2_SME_Zmx2,
> A64_OPID_c121e400_fmul_SME_Zdnx4_SME_Znx4_SME_Zmx4,
> + A64_OPID_d5080000_gic_GIC_Rd,
> + A64_OPID_d5080000_gicr_Rd_GICR,
> + A64_OPID_d5080000_gsb_GSB,
> A64_OPID_MAX,
> };
> diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
> index 34b551eb64c..6b90120ee51 100644
> --- a/opcodes/aarch64-tbl.h
> +++ b/opcodes/aarch64-tbl.h
> @@ -3410,6 +3410,8 @@ static const aarch64_feature_set aarch64_feature_gcie =
> #define SME2p2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \
> { NAME, OPCODE, MASK, CLASS, 0, SME2p2, OPS, QUALS, \
> F_STRICT | FLAGS, 0, TIED, NULL }
> +#define GCIE_INSN(NAME,OPCODE,MASK,OPS,QUALS,FLAGS) \
> + { NAME, OPCODE, MASK, ic_system, 0, GCIE, OPS, QUALS, FLAGS, 0, 0, NULL }
>
> #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
> MOPS_INSN (NAME, OPCODE, MASK, 0, \
> @@ -7480,6 +7482,11 @@ const struct aarch64_opcode aarch64_opcode_table[] =
> SME2p2_INSN ("fmul", 0xc120e400, 0xff21fc21, sme_size_22_hsd, OP3 (SME_Zdnx2, SME_Znx2, SME_Zmx2), OP_SVE_VVV_HSD, 0, 0),
> SME2p2_INSN ("fmul", 0xc121e400, 0xff21fc63, sme_size_22_hsd, OP3 (SME_Zdnx4, SME_Znx4, SME_Zmx4), OP_SVE_VVV_HSD, 0, 0),
>
> + /* Generalised Interrupt Controller v5 instructions. */
> + GCIE_INSN ("gic", 0xd5080000, 0xfff80000, OP2 (GIC, Rd), QL_SRC_X, F_ALIAS),
> + GCIE_INSN ("gicr", 0xd5080000, 0xfff80000, OP2 (Rd, GICR), QL_DST_X, F_ALIAS),
> + GCIE_INSN ("gsb", 0xd5080000, 0xfff80000, OP1 (GSB), QL_IMM_NIL, F_ALIAS),
> +
> {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
> };
>
> @@ -8221,4 +8228,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =
> "RCPC3_ADDR_PREIND_WB", 0, F(), \
> "an address with pre-incrementing with write-back by ammount of stored bytes") \
> Y(ADDRESS, rcpc3_addr_offset, "RCPC3_ADDR_OFFSET", 0, F(FLD_Rn,FLD_imm9), \
> - "an address with an optional 8-bit signed immediate offset")
> + "an address with an optional 8-bit signed immediate offset") \
> + Y(SYSTEM, sysins_op, "GIC", 0, F(), \
> + "Generic Interrupt Controller") \
> + Y(SYSTEM, sysins_op, "GICR", 0, F(), \
> + "Generic Interrupt Controller") \
> + Y(SYSTEM, sysins_op, "GSB", 0, F(), \
> + "Generic Interrupt Controller Synchronization Barrier")
> --
> 2.34.1
>
More information about the Binutils
mailing list