[PATCH v1] PowerPC: Support for Elliptic Curve Cryptography Acceleration Instructions (RFC02669)
Surya Kumari Jangala
jskumari@linux.ibm.com
Wed Oct 29 14:01:19 GMT 2025
Hi Abhay,
On 29/10/25 3:31 pm, Abhay Kandpal wrote:
> opcodes/
> * ppc-opc.c: (XX3SCL_MASK, XX3SUM_MASK, XX4EX, P_XX4EX_MASK,
> SCL, SCL0, SCL1, SCL2, PROD, PP): New defines.
> (PS, R): Update for new macros.
> (powerpc_opcodes): <xxmulmul, xxmulmulhiadd, xxmulmulloadd, xxssumudm,
> xxssumudmc, xsmerge2t3uqm, xsaddadduqm, xsaddaddsuqm, xsaddsubuqm,
> xsmerge3t1uqm, xsrebase2t1uqm, xsrebase2t2uqm, xsrebase3t3uqm,
> xsrebase2t3uqm, xsrebase2t4uqm, xsaddsubsuqm, xsmerge2t1uqm,
> xsmerge2t2uqm, xsrebase3t1uqm, xsrebase3t2uqm, xxssumudmcext>: New instructions.
This line exceeds 80 characters.
Also, you can say the following instead of using '<' and '>':
Add insn1, insn2...insnLast.
(like you did for your other patches).
>
> gas/
> * testsuite/gas/ppc/future.s: New test.
> * testsuite/gas/ppc/future.d: Likewise.
> ---
> This patch is reg tested.
>
> gas/testsuite/gas/ppc/future.d | 22 ++++++++++++
> gas/testsuite/gas/ppc/future.s | 21 +++++++++++
> opcodes/ppc-opc.c | 65 ++++++++++++++++++++++++++++++++--
> 3 files changed, 106 insertions(+), 2 deletions(-)
>
> diff --git a/gas/testsuite/gas/ppc/future.d b/gas/testsuite/gas/ppc/future.d
> index 8cd0b23151c..110cfe03044 100644
> --- a/gas/testsuite/gas/ppc/future.d
> +++ b/gas/testsuite/gas/ppc/future.d
> @@ -114,4 +114,26 @@ Disassembly of section \.text:
> .*: (96 46 1e f3|f3 1e 46 96) dmxxshapad dm6,vs40,3,1,2
> .*: (4c 06 00 7c|7c 00 06 4c) ccmclean
> .*: (cc 06 00 7c|7c 00 06 cc) ccmrl
> +.*: (0f 37 44 ec|ec 44 37 0f) xxmulmul vs34,vs36,vs38,7
> +.*: (4d 4d a7 ec|ec a7 4d 4d) xxmulmulhiadd vs37,vs39,vs9,1,0,1
> +.*: (8f 69 4c ed|ed 4c 69 8f) xxmulmulloadd vs42,vs44,vs45,0,1
> +.*: (c8 34 85 ec|ec 85 34 c8) xxssumudm vs4,vs5,vs6,1
> +.*: (c8 39 64 ec|ec 64 39 c8) xxssumudmc vs3,vs4,vs7,0
> +.*: (07 ab 74 ee|ee 74 ab 07) xsaddadduqm vs51,vs52,vs53
> +.*: (40 13 01 ec|ec 01 13 40) xsaddaddsuqm vs0,vs1,vs2
> +.*: (87 fb be ef|ef be fb 87) xsaddsubuqm vs61,vs62,vs63
> +.*: (00 2f 64 ec|ec 64 2f 00) xsaddsubsuqm vs3,vs4,vs5
> +.*: (40 57 c8 ec|ec c8 57 40) xsmerge2t1uqm vs6,vs8,vs10
> +.*: (80 87 8e ed|ed 8e 87 80) xsmerge2t2uqm vs12,vs14,vs16
> +.*: (c8 a2 53 ee|ee 53 a2 c8) xsmerge2t3uqm vs18,vs19,vs20
> +.*: (c8 cb b7 ee|ee b7 cb c8) xsmerge3t1uqm vs21,vs23,vs25
> +.*: (88 f4 7d ef|ef 7d f4 88) xsrebase2t1uqm vs27,vs29,vs30
> +.*: (8e 0d e0 ef|ef e0 0d 8e) xsrebase2t2uqm vs31,vs32,vs33
> +.*: (8f 26 43 ec|ec 43 26 8f) xsrebase2t3uqm vs34,vs35,vs36
> +.*: (cf 2e 64 ec|ec 64 2e cf) xsrebase2t4uqm vs35,vs36,vs37
> +.*: (8f 47 c7 ec|ec c7 47 8f) xsrebase3t1uqm vs38,vs39,vs40
> +.*: (cf 5f 2a ed|ed 2a 5f cf) xsrebase3t2uqm vs41,vs42,vs43
> +.*: (00 00 00 05|05 00 00 00) xxssumudmcext vs35,vs9,vs11,vs13,1
> +.*: (71 5b 69 88|88 69 5b 71)
> +.*: (1f 76 8d ed|ed 8d 76 1f) xsrebase3t3uqm vs44,vs45,vs46
Please group related instructions together. So xsrebase3t3uqm should
come after xsrebase3t2uqm.
> #pass
> diff --git a/gas/testsuite/gas/ppc/future.s b/gas/testsuite/gas/ppc/future.s
> index 3c35d7e932b..ab28c11b9c9 100644
> --- a/gas/testsuite/gas/ppc/future.s
> +++ b/gas/testsuite/gas/ppc/future.s
> @@ -88,4 +88,25 @@ _start:
> dmxxshapad 6, 40, 3, 1, 2
> ccmclean
> ccmrl
> + xxmulmul 34, 36, 38, 7
> + xxmulmulhiadd 37, 39, 9, 1, 0, 1
> + xxmulmulloadd 42, 44, 45, 0, 1
> + xxssumudm 4, 5, 6, 1
> + xxssumudmc 3, 4, 7, 0
> + xsaddadduqm 51, 52, 53
> + xsaddaddsuqm 0, 1, 2
> + xsaddsubuqm 61, 62, 63
> + xsaddsubsuqm 3, 4, 5
> + xsmerge2t1uqm 6, 8, 10
> + xsmerge2t2uqm 12, 14, 16
> + xsmerge2t3uqm 18, 19, 20
> + xsmerge3t1uqm 21, 23, 25
> + xsrebase2t1uqm 27, 29, 30
> + xsrebase2t2uqm 31, 32, 33
> + xsrebase2t3uqm 34, 35, 36
> + xsrebase2t4uqm 35, 36, 37
> + xsrebase3t1uqm 38, 39, 40
> + xsrebase3t2uqm 41, 42, 43
> + xxssumudmcext 35, 9, 11, 13, 1
> + xsrebase3t3uqm 44, 45, 46
>
> diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
> index f241fb3937e..07ef9df0936 100644
> --- a/opcodes/ppc-opc.c
> +++ b/opcodes/ppc-opc.c
> @@ -3740,8 +3740,14 @@ const struct powerpc_operand powerpc_operands[] =
> #define MMMM SIX
> { 0xf, 11, NULL, NULL, 0 },
>
> + /* The P bit in Prefix XX4-form instruction. */
> +#define PP MMMM + 1
> + { 0x1, 4, NULL, NULL, 0 },
> +
> + /* The Scale1 field in XX3 form bit (22) */
> +#define SCL1 PP + 1
> /* The PS field in a VX form instruction. */
> -#define PS SIX + 1
> +#define PS PP + 1
> { 0x1, 9, NULL, NULL, 0 },
>
> /* The SH field in a vector shift double by bit immediate instruction. */
> @@ -3789,6 +3795,10 @@ const struct powerpc_operand powerpc_operands[] =
> /* PowerPC paired singles extensions. */
> /* W bit in the pair singles instructions for x type instructions. */
> #define PSWM WS + 1
> + /* The Product P field in multi-sum XX3 form bit (21) */
P is not a field, it is a bit.
The P bit does not denote 'product'. So instead of PROD, rename to PSSUM.
And replace multi-sum with multiply-sum. "multi-sum" has no
meaning here.
So comment should be:
/* The P bit in scaled multiply-sum XX3 form instructions (bit 21) */
> +#define PROD PSWM
rewrite as:
#define PSSUM PSWM
> + /* The Scale0 field in XX3 form bit (21) */
> +#define SCL0 PSWM
The instruction description doesn't really call this
as a Scale field. Is it right for us to use call it as such?
-Surya
> /* The BO16 field in a BD8 form instruction. */
> #define BO16 PSWM
> /* The pst field in a SVRM form instruction. */
> @@ -3822,7 +3832,11 @@ const struct powerpc_operand powerpc_operands[] =
> #define ew RMC
> { 0x3, 9, NULL, NULL, 0 },
>
> -#define R RMC + 1
> + /* The Scale field in XX3 form bit (21-23) */
> +#define SCL RMC + 1
> + { 0x7, 8, NULL, NULL, 0 },
> +
> +#define R SCL + 1
> #define MP R
> #define UIMM1 R
> #define P1 R
> @@ -4041,6 +4055,8 @@ const struct powerpc_operand powerpc_operands[] =
>
> #define ms vs + 1
> #define yx ms
> + /* The Scale2 field in XX3 form bit (23) */
> +#define SCL2 yx
> /* The P field in Galois Field XX3 form instruction. */
> #define PGF1 yx
> { 0x1, 8, NULL, NULL, 0 },
> @@ -4120,6 +4136,7 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
> #define P_XX4_MASK (PREFIX_MASK | XX4_MASK)
> #define P_UXX4_MASK (P_XX4_MASK & ~(7ULL << 32))
> #define P_U8XX4_MASK (P_XX4_MASK & ~(0xffULL << 32))
> +#define P_XX4EX_MASK (PREFIX_MASK | XX4EX (0x3f, 0x1))
>
> /* MMIRR:XX3-form 8-byte outer product instructions. */
> #define P_GER_MASK ((-1ULL << 40) | XX3ACC_MASK)
> @@ -4612,6 +4629,9 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
> /* An XX4 form instruction. */
> #define XX4(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3) << 4))
>
> +/* An XX4 form instruction with 1 bit carry extended. */
> +#define XX4EX(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1) << 5))
> +
> /* A Z form instruction. */
> #define Z(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1ff) << 1))
>
> @@ -4715,6 +4735,12 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
> /* The masks for XX3 GF instructions with P bit. */
> #define XX3GF_MASK (XX3 (0x3f, 0xff) & ~(1 << 8))
>
> +/* The masks for VSX multiply XX3 instructions with scale bits. */
> +#define XX3SCL_MASK (XX3 (0x3f, 0x1f))
> +
> +/* The masks for VSX multiplty-sum XX3 instructions with p bits. */
> +#define XX3SUM_MASK (XX3 (0x3f, 0x7f))
> +
> /* The mask for an XX4 form instruction. */
> #define XX4_MASK XX4 (0x3f, 0x3)
>
> @@ -9183,6 +9209,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
> {"ldu", DSO(58,1), DS_MASK, PPC64, PPCVLE, {RT, DS, RAL}},
> {"lwa", DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}},
>
> +{"xxmulmul", XX3(59,1), XX3SCL_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6, SCL}},
> +
> {"dadd", XRC(59,2,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
> {"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}},
>
> @@ -9194,6 +9222,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
> {"dmxvi8ger4", XX3(59,3), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
> {"xvi8ger4", XX3(59,3), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>
> +{"xxmulmulhiadd",XX3(59,9), XX3SCL_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6, SCL0, SCL1, SCL2}},
> +{"xxmulmulloadd",XX3(59,17), XX3SHW_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6, SCL1, SCL2}},
> +
> {"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
> {"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}},
>
> @@ -9214,6 +9245,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
> {"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
> {"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}},
>
> +{"xxssumudm", XX3(59,25), XX3SUM_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6, PROD}},
> +
> {"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
> {"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}},
> {"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}},
> @@ -9240,6 +9273,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
> {"dmxvi8gerx4pp", XX3(59,10), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
> {"dmxvi8gerx4", XX3(59,11), XX3GERX_MASK, FUTURE, PPCVLE, {DMR, XA5p, XB6}},
>
> +{"xxssumudmc", XX3(59,57), XX3SUM_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6, PROD}},
> +
> {"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
> {"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
>
> @@ -9251,6 +9286,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
> {"dmxvf16ger2", XX3(59,19), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
> {"xvf16ger2", XX3(59,19), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>
> +{"xsmerge2t3uqm",XX3(59,89), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
> +
> +{"xsaddadduqm", XX3(59,96), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
> +
> {"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
> {"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}},
>
> @@ -9262,6 +9301,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
> {"dmxvf32ger", XX3(59,27), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
> {"xvf32ger", XX3(59,27), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>
> +{"xsaddaddsuqm",XX3(59,104), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
> +{"xsaddsubuqm", XX3(59,112), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
> +
> +{"xsmerge3t1uqm",XX3(59,121), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
> +
> {"dcmpo", X(59,130), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
>
> {"dmxvi4ger8pp",XX3(59,34), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
> @@ -9269,6 +9313,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
> {"dmxvi4ger8", XX3(59,35), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
> {"xvi4ger8", XX3(59,35), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>
> +{"xsrebase2t1uqm",XX3(59,145), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
> +
> {"dtstex", X(59,162), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}},
>
> {"dmxvi16ger2spp",XX3(59,42), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
> @@ -9276,6 +9322,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
> {"dmxvi16ger2s", XX3(59,43), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
> {"xvi16ger2s", XX3(59,43), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>
> +{"xsrebase2t2uqm",XX3(59,177), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
> +
> {"dtstdc", Z(59,194), Z_MASK, POWER6, PPCVLE, {BF, FRA, DCM}},
>
> {"dmxvbf16ger2pp",XX3(59,50), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
> @@ -9283,6 +9331,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
> {"dmxvbf16ger2", XX3(59,51), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
> {"xvbf16ger2", XX3(59,51), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}},
>
> +{"xsrebase3t3uqm",XX3(59,195), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
> +{"xsrebase2t3uqm",XX3(59,209), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
> +{"xsrebase2t4uqm",XX3(59,217), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
> +
> +{"xsaddsubsuqm", XX3(59,224), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
> +
> {"dtstdg", Z(59,226), Z_MASK, POWER6, PPCVLE, {BF, FRA, DGM}},
>
> {"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}},
> @@ -9293,6 +9347,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
> {"dmxvf64ger", XX3(59,59), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}},
> {"xvf64ger", XX3(59,59), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}},
>
> +{"xsmerge2t1uqm",XX3(59,232), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
> +{"xsmerge2t2uqm",XX3(59,240), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
> +
> +{"xsrebase3t1uqm",XX3(59,241), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
> +{"xsrebase3t2uqm",XX3(59,249), XX3_MASK, FUTURE, PPCVLE, {XT6, XA6, XB6}},
> +
> {"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
> {"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}},
>
> @@ -9991,6 +10051,7 @@ const struct powerpc_opcode prefix_opcodes[] = {
> {"xxblendvd", P8RR|XX4(33,3), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}},
> {"xxpermx", P8RR|XX4(34,0), P_UXX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6, UIM3}},
> {"xxeval", P8RR|XX4(34,1), P_U8XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6, UIM8}},
> +{"xxssumudmcext", P8RR|XX4EX(34,1), P_XX4EX_MASK, FUTURE, 0, {XT6, XA6, XB6, XC6, PP}},
> {"plbz", PMLS|OP(34), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}},
> {"pstw", PMLS|OP(36), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}},
> {"pstb", PMLS|OP(38), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}},
More information about the Binutils
mailing list