[PATCH v2] PowerPC: Support for SHA2 and SHA3 Compute Instructions (RFC02654)
Abhay Kandpal
abhay@linux.ibm.com
Tue Oct 28 11:54:49 GMT 2025
opcodes/
* ppc-opc.c: (DMRATp, HASHT, HASHSR, PADE, PADID, PADBL, XDMRHSH_MASK,
XDMRSR_MASK): New defines.
(OBF, PMSK8): Update for new macros.
(powerpc_opcodes): <dmsha2hash, dmsha3hash, dmxxshapad>: New instructions.
gas/
* testsuite/gas/ppc/future.s: New test.
* testsuite/gas/ppc/future.d: Likewise.
---
This patch is reg tested.
Changes from v1->v2:
<Added more test cases for dmsha2hash, dmsha3hash, dmxxshapad>
gas/testsuite/gas/ppc/future.d | 6 ++++++
gas/testsuite/gas/ppc/future.s | 6 ++++++
opcodes/ppc-opc.c | 30 +++++++++++++++++++++++++++---
3 files changed, 39 insertions(+), 3 deletions(-)
diff --git a/gas/testsuite/gas/ppc/future.d b/gas/testsuite/gas/ppc/future.d
index 19e96fac345..89951e76bad 100644
--- a/gas/testsuite/gas/ppc/future.d
+++ b/gas/testsuite/gas/ppc/future.d
@@ -106,4 +106,10 @@ Disassembly of section \.text:
.*: (83 b9 2f 12|12 2f b9 83) vupkint8tofp32 v17,v23,3
.*: (da 9e 72 7c|7c 72 9e da) lxvpb32x vs34,r18,r19
.*: (da af 74 7c|7c 74 af da) stxvpb32x vs34,r20,r21
+.*: (62 61 0e 7d|7d 0e 61 62) dmsha2hash dm2,dm3,0
+.*: (62 01 0f 7f|7f 0f 01 62) dmsha3hash dm3,0
+.*: (94 1e 80 f3|f3 80 1e 94) dmxxshapad dm7,vs3,0,0,0
+.*: (62 c1 2e 7e|7e 2e c1 62) dmsha2hash dm4,dm6,1
+.*: (62 41 0f 7e|7e 0f 41 62) dmsha3hash dm2,8
+.*: (96 46 1e f3|f3 1e 46 96) dmxxshapad dm6,vs40,3,1,2
#pass
diff --git a/gas/testsuite/gas/ppc/future.s b/gas/testsuite/gas/ppc/future.s
index 492b963c96c..79db5165863 100644
--- a/gas/testsuite/gas/ppc/future.s
+++ b/gas/testsuite/gas/ppc/future.s
@@ -80,4 +80,10 @@ _start:
vupkint8tofp32 17, 23, 3
lxvpb32x 34, 18, 19
stxvpb32x 34, 20, 21
+ dmsha2hash 2, 3, 0
+ dmsha3hash 3, 0
+ dmxxshapad 7, 3, 0, 0, 0
+ dmsha2hash 4, 6, 1
+ dmsha3hash 2, 8
+ dmxxshapad 6, 40, 3, 1, 2
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 08d6a38d22f..642581133f6 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2965,9 +2965,13 @@ const struct powerpc_operand powerpc_operands[] =
#define DMRAB DMR + 1
{ 0x7, 13, NULL, NULL, PPC_OPERAND_DMR },
- /* An optional BF field. This is used for comparison instructions,
+ /* The DMR field in a MMA instruction. */
+#define DMRATp DMRAB + 1
+ { 0x3, 24, NULL, NULL, PPC_OPERAND_DMR },
+
+/* An optional BF field. This is used for comparison instructions,
in which an omitted BF field is taken as zero. */
-#define OBF DMRAB + 1
+#define OBF DMRATp + 1
{ 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL },
/* The BFA field in an X or XL form instruction. */
@@ -3145,8 +3149,12 @@ const struct powerpc_operand powerpc_operands[] =
#define IX UIM8 + 1
{ 0x1, 17, NULL, NULL, 0 },
+ /* SHA pad E field (bit 18). */
+#define PADE IX + 1
+ { 0x1, 18, NULL, NULL, 0 },
+
/* The PMSK field in GER rank 8 prefix instructions. */
-#define PMSK8 IX + 1
+#define PMSK8 PADE + 1
{ 0xff, 40, NULL, NULL, 0 },
/* The PMSK field in GER rank 4 prefix instructions. */
@@ -3264,6 +3272,8 @@ const struct powerpc_operand powerpc_operands[] =
#define IMM20 FXM4 + 1
{ 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED},
+ /* The Third field in MMA instruction for Hash. */
+#define HASHT IMM20 + 1
/* The L field in a D or X form instruction. */
#define L IMM20 + 1
{ 0x1, 21, NULL, NULL, 0 },
@@ -3541,6 +3551,7 @@ const struct powerpc_operand powerpc_operands[] =
#define EVUIMM SH
/* The FC field in an atomic X form instruction. */
#define FC SH
+#define HASHSR SH
#define UIM5 SH
{ 0x1f, 11, NULL, NULL, 0 },
@@ -3824,6 +3835,8 @@ const struct powerpc_operand powerpc_operands[] =
{ 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL },
#define SP PRS + 1
+ /* SHA pad mode field ID (bits 19–20). */
+#define PADID SP
#define mi0 SP
{ 0x3, 19, NULL, NULL, 0 },
@@ -3974,6 +3987,8 @@ const struct powerpc_operand powerpc_operands[] =
#define UIM AESM + 1
/* The 2-bit UIMM field in a VX form instruction. */
#define UIMM2 UIM
+ /* SHA pad block length BL (bits 16–17). */
+#define PADBL UIM
/* The 2-bit L field in a darn instruction. */
#define LRAND UIM
{ 0x3, 16, NULL, NULL, 0 },
@@ -4671,6 +4686,12 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
/* An X_MASK with two dense math register. */
#define XDMRDMR_MASK (X_MASK | RA_MASK | (3 << 21) | (3 << 11))
+/* An X_MASK with two dense math register with Hash. */
+#define XDMRHSH_MASK (X_MASK | RA_MASK | (1 << 22) | (3 << 11))
+
+/* An X_MASK with one dense math register with Hash. */
+#define XDMRSR_MASK (X_MASK | RA_MASK | (7 << 21))
+
/* The mask for an XX3 form instruction with the DM or SHW bits
specified. */
#define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10))
@@ -7507,6 +7528,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"xxsetaccz", XVA(31,177,3), XACC_MASK, POWER10, 0, {ACC}},
{"dmmr", XVA(31,177,6), XDMRDMR_MASK,FUTURE, 0, {DMR, DMRAB}},
{"dmxor", XVA(31,177,7), XDMRDMR_MASK,FUTURE, 0, {DMR, DMRAB}},
+{"dmsha2hash", XVA(31,177,14), XDMRHSH_MASK,FUTURE, 0, {DMR, DMRAB, HASHT}},
+{"dmsha3hash", XVA(31,177,15), XDMRSR_MASK, FUTURE, 0, {DMRATp, HASHSR}},
{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}},
@@ -9602,6 +9625,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE|EXT, {XT6, XAB6}},
{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
{"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
+{"dmxxshapad", XX2(60,421), XX2ACC_MASK, FUTURE, PPCVLE, {DMR, XB6, PADID, PADE, PADBL}},
{"dmxxextfdmr256",XX2(60,484), XX2DMR_MASK, FUTURE, PPCVLE, {XB5p, DMR, P2}},
{"dmxxinstdmr256",XX2(60,485), XX2DMR_MASK, FUTURE, PPCVLE, {DMR, XB5p, P2}},
{"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
--
2.47.3
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