[PATCH 1/1] AArch64: Add FEAT_F16F32MM
Sivan Shani
sivan.shani@arm.com
Thu Oct 23 14:35:04 GMT 2025
This patch includes:
- The feature flag for the FEAT_F16F32MM feature.
- Instruction FMMLA Half-precision matrix multiply-accumulate to single-precision.
---
gas/config/tc-aarch64.c | 1 +
gas/doc/c-aarch64.texi | 2 ++
gas/testsuite/gas/aarch64/f16f32mm-simd.d | 12 ++++++++++++
gas/testsuite/gas/aarch64/f16f32mm-simd.s | 4 ++++
include/opcode/aarch64.h | 2 ++
opcodes/aarch64-dis-2.c | 24 ++++++++++++++++-------
opcodes/aarch64-tbl-2.h | 1 +
opcodes/aarch64-tbl.h | 14 +++++++++++++
8 files changed, 53 insertions(+), 7 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/f16f32mm-simd.d
create mode 100644 gas/testsuite/gas/aarch64/f16f32mm-simd.s
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 974951cef25..a9d0d544382 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10863,6 +10863,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"pops", AARCH64_FEATURE (PoPS), AARCH64_NO_FEATURES},
{"sve2p2", AARCH64_FEATURE (SVE2p2), AARCH64_FEATURE (SVE2p1)},
{"sme2p2", AARCH64_FEATURE (SME2p2), AARCH64_FEATURE (SME2p1)},
+ {"f16f32mm", AARCH64_FEATURE (F16F32MM), AARCH64_FEATURE (SIMD)},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
};
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 8f5702f5b13..5b06e7eff4f 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -219,6 +219,8 @@ automatically cause those extensions to be disabled.
@tab Enable Armv8.2 16-bit floating-point multiplication variant support.
@item @code{fp16} @tab @code{fp}
@tab Enable Armv8.2 16-bit floating-point support.
+@item @code{f16f32mm} @tab @code{simd}
+ @tab Enable Armv9.7 f16f32mm instructions.
@item @code{fprcvt} @tab @code{fp}
@tab Enable Armv9.6 fprcvt instructions.
@item @code{frintts} @tab @code{fp}
diff --git a/gas/testsuite/gas/aarch64/f16f32mm-simd.d b/gas/testsuite/gas/aarch64/f16f32mm-simd.d
new file mode 100644
index 00000000000..3740ad1c2d8
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/f16f32mm-simd.d
@@ -0,0 +1,12 @@
+#as: -march=armv8-a+f16f32mm
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+:[ \t]+4e40ec00[ \t]+fmmla[ \t]+v0\.4s, v0\.8h, v0\.8h
+ *[0-9a-f]+:[ \t]+4e40ec1f[ \t]+fmmla[ \t]+v31\.4s, v0\.8h, v0\.8h
+ *[0-9a-f]+:[ \t]+4e40efe0[ \t]+fmmla[ \t]+v0\.4s, v31\.8h, v0\.8h
+ *[0-9a-f]+:[ \t]+4e5fec00[ \t]+fmmla[ \t]+v0\.4s, v0\.8h, v31\.8h
diff --git a/gas/testsuite/gas/aarch64/f16f32mm-simd.s b/gas/testsuite/gas/aarch64/f16f32mm-simd.s
new file mode 100644
index 00000000000..0cd034f2012
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/f16f32mm-simd.s
@@ -0,0 +1,4 @@
+fmmla v0.4s, v0.8h, v0.8h
+fmmla v31.4s, v0.8h, v0.8h
+fmmla v0.4s, v31.8h, v0.8h
+fmmla v0.4s, v0.8h, v31.8h
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 4425dd46a45..0ebf9e401e9 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -310,6 +310,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_FPRCVT,
/* Point of Physical Storage. */
AARCH64_FEATURE_PoPS,
+ /* F16F32MM instructions. */
+ AARCH64_FEATURE_F16F32MM,
/* Virtual features. These are used to gate instructions that are enabled
by either of two (or more) sets of command line flags. */
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 6e66d54885b..0b4a933b555 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -27033,19 +27033,29 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 15) & 0x1) == 0)
+ if (((word >> 14) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 0x001110xx0xxxxx0x1011xxxxxxxxxx. */
- return A64_OPID_0e002c00_smov_Rd_En;
+ if (((word >> 15) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110xx0xxxxx001011xxxxxxxxxx. */
+ return A64_OPID_0e002c00_smov_Rd_En;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 0x001110xx0xxxxx101011xxxxxxxxxx. */
+ return A64_OPID_4e80ac00_usmmla_Vd_Vn_Vm;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 0x001110xx0xxxxx1x1011xxxxxxxxxx. */
- return A64_OPID_4e80ac00_usmmla_Vd_Vn_Vm;
+ 0x001110xx0xxxxxx11011xxxxxxxxxx. */
+ return A64_OPID_4e40ec00_fmmla_Vd_Vn_Vm;
}
}
}
diff --git a/opcodes/aarch64-tbl-2.h b/opcodes/aarch64-tbl-2.h
index 808a6c5ad5b..de27ee8b561 100644
--- a/opcodes/aarch64-tbl-2.h
+++ b/opcodes/aarch64-tbl-2.h
@@ -3843,5 +3843,6 @@ enum aarch64_opcode_idx
A64_OPID_c121e800_fmul_SME_Zdnx4_SME_Znx4_SME_Zm_17,
A64_OPID_c120e400_fmul_SME_Zdnx2_SME_Znx2_SME_Zmx2,
A64_OPID_c121e400_fmul_SME_Zdnx4_SME_Znx4_SME_Zmx4,
+ A64_OPID_4e40ec00_fmmla_Vd_Vn_Vm,
A64_OPID_MAX,
};
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 0ae7342e2e1..498e3c02e90 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2788,6 +2788,12 @@
{ \
QLF3(V_4S, V_8H, S_H), \
}
+
+/* e.g. FMMLA <Vd>.4s, <Vn>.8h, <Vm>.8h */
+#define QL_VF16VF32 \
+{ \
+ QLF3(V_4S, V_8H, V_8H),\
+}
/* Opcode table. */
@@ -3009,6 +3015,8 @@ static const aarch64_feature_set aarch64_feature_sve_sme2p2 =
AARCH64_FEATURE (SVE_SME2p2);
static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 =
AARCH64_FEATURE (SVE2p2_SME2p2);
+static const aarch64_feature_set aarch64_feature_f16f32mm =
+ AARCH64_FEATURE (F16F32MM);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@@ -3119,6 +3127,7 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 =
#define SME2p2 &aarch64_feature_sme2p2
#define SVE_SME2p2 &aarch64_feature_sve_sme2p2
#define SVE2p2_SME2p2 &aarch64_feature_sve2p2_sme2p2
+#define F16F32MM &aarch64_feature_f16f32mm
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
@@ -3407,6 +3416,8 @@ static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 =
#define SME2p2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, 0, SME2p2, OPS, QUALS, \
F_STRICT | FLAGS, 0, TIED, NULL }
+#define F16F32MM_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+ { NAME, OPCODE, MASK, CLASS, 0, F16F32MM, OPS, QUALS, FLAGS, 0, 0, NULL }
#define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
MOPS_INSN (NAME, OPCODE, MASK, 0, \
@@ -7477,6 +7488,9 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME2p2_INSN ("fmul", 0xc120e400, 0xff21fc21, sme_size_22_hsd, OP3 (SME_Zdnx2, SME_Znx2, SME_Zmx2), OP_SVE_VVV_HSD, 0, 0),
SME2p2_INSN ("fmul", 0xc121e400, 0xff21fc63, sme_size_22_hsd, OP3 (SME_Zdnx4, SME_Znx4, SME_Zmx4), OP_SVE_VVV_HSD, 0, 0),
+ /* F16F32MM instructions. */
+ F16F32MM_INSN ("fmmla", 0x4e40ec00, 0xffe0fc00, asimdmisc, OP3 (Vd, Vn, Vm), QL_VF16VF32, F_SIZEQ),
+
{0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
};
--
2.43.0
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