[PATCH 1/1] AArch64: Add FEAT_F16F32DOT instructions
Saurabh Jha
saurabh.jha@arm.com
Thu Oct 23 14:16:32 GMT 2025
On 10/23/2025 3:05 PM, Sivan Shani wrote:
> This includes the instructions for the F16F32DOT feature:
> - FDOT half-precision to single-precision, by element
> - FDOT half-precision to single-precision, vector
The code looks good to me but you can add more description in your
commit message. Specifically, you can add that you added a feature flag
and two new operands.
Thanks,
Saurabh
> ---
> gas/config/tc-aarch64.c | 1 +
> gas/doc/c-aarch64.texi | 2 ++
> gas/testsuite/gas/aarch64/f16f32dot-simd.d | 24 +++++++++++++
> gas/testsuite/gas/aarch64/f16f32dot-simd.s | 19 ++++++++++
> include/opcode/aarch64.h | 2 ++
> opcodes/aarch64-dis-2.c | 42 ++++++++++++++++------
> opcodes/aarch64-tbl-2.h | 2 ++
> opcodes/aarch64-tbl.h | 8 +++++
> 8 files changed, 89 insertions(+), 11 deletions(-)
> create mode 100644 gas/testsuite/gas/aarch64/f16f32dot-simd.d
> create mode 100644 gas/testsuite/gas/aarch64/f16f32dot-simd.s
>
> diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
> index 0ca54c3bd40..e9188a883d3 100644
> --- a/gas/config/tc-aarch64.c
> +++ b/gas/config/tc-aarch64.c
> @@ -10905,6 +10905,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
> {"ssve-fexpa", AARCH64_FEATURE (SSVE_FEXPA), AARCH64_FEATURE (SME2)},
> {"sme-tmop", AARCH64_FEATURE (SME_TMOP), AARCH64_FEATURE (SME2)},
> {"sme-mop4", AARCH64_FEATURE (SME_MOP4), AARCH64_FEATURE (SME2)},
> + {"f16f32dot", AARCH64_FEATURE (F16F32DOT), AARCH64_FEATURE (SIMD)},
> {NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
> };
>
> diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
> index 9683d411ce9..4a541ce9fad 100644
> --- a/gas/doc/c-aarch64.texi
> +++ b/gas/doc/c-aarch64.texi
> @@ -219,6 +219,8 @@ automatically cause those extensions to be disabled.
> @tab Enable Armv8.2 16-bit floating-point multiplication variant support.
> @item @code{fp16} @tab @code{fp}
> @tab Enable Armv8.2 16-bit floating-point support.
> +@item @code{f16f32dot} @tab @code{simd}
> + @tab Enable Armv9.7 f16f32dot instructions.
> @item @code{fprcvt} @tab @code{fp}
> @tab Enable Armv9.6 fprcvt instructions.
> @item @code{frintts} @tab @code{fp}
> diff --git a/gas/testsuite/gas/aarch64/f16f32dot-simd.d b/gas/testsuite/gas/aarch64/f16f32dot-simd.d
> new file mode 100644
> index 00000000000..53b00f95b7b
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/f16f32dot-simd.d
> @@ -0,0 +1,24 @@
> +#as: -march=armv8-a+f16f32dot
> +#objdump: -dr
> +
> +.*: file format .*
> +
> +Disassembly of section \.text:
> +
> +0+ <\.text>:
> + *[0-9a-f]+:[ \t]+0f409000[ \t]+fdot[ \t]+v0\.2s, v0\.4h, v0\.2h\[0\]
> + *[0-9a-f]+:[ \t]+0f60901f[ \t]+fdot[ \t]+v31\.2s, v0\.4h, v0\.2h\[1\]
> + *[0-9a-f]+:[ \t]+0f409be0[ \t]+fdot[ \t]+v0\.2s, v31\.4h, v0\.2h\[2\]
> + *[0-9a-f]+:[ \t]+0f7f9800[ \t]+fdot[ \t]+v0\.2s, v0\.4h, v31\.2h\[3\]
> + *[0-9a-f]+:[ \t]+4f409000[ \t]+fdot[ \t]+v0\.4s, v0\.8h, v0\.2h\[0\]
> + *[0-9a-f]+:[ \t]+4f60901f[ \t]+fdot[ \t]+v31\.4s, v0\.8h, v0\.2h\[1\]
> + *[0-9a-f]+:[ \t]+4f409be0[ \t]+fdot[ \t]+v0\.4s, v31\.8h, v0\.2h\[2\]
> + *[0-9a-f]+:[ \t]+4f7f9800[ \t]+fdot[ \t]+v0\.4s, v0\.8h, v31\.2h\[3\]
> + *[0-9a-f]+:[ \t]+0e80fc00[ \t]+fdot[ \t]+v0\.2s, v0\.4h, v0\.4h
> + *[0-9a-f]+:[ \t]+0e80fc1f[ \t]+fdot[ \t]+v31\.2s, v0\.4h, v0\.4h
> + *[0-9a-f]+:[ \t]+0e80ffe0[ \t]+fdot[ \t]+v0\.2s, v31\.4h, v0\.4h
> + *[0-9a-f]+:[ \t]+0e9ffc00[ \t]+fdot[ \t]+v0\.2s, v0\.4h, v31\.4h
> + *[0-9a-f]+:[ \t]+4e80fc00[ \t]+fdot[ \t]+v0\.4s, v0\.8h, v0\.8h
> + *[0-9a-f]+:[ \t]+4e80fc1f[ \t]+fdot[ \t]+v31\.4s, v0\.8h, v0\.8h
> + *[0-9a-f]+:[ \t]+4e80ffe0[ \t]+fdot[ \t]+v0\.4s, v31\.8h, v0\.8h
> + *[0-9a-f]+:[ \t]+4e9ffc00[ \t]+fdot[ \t]+v0\.4s, v0\.8h, v31\.8h
> diff --git a/gas/testsuite/gas/aarch64/f16f32dot-simd.s b/gas/testsuite/gas/aarch64/f16f32dot-simd.s
> new file mode 100644
> index 00000000000..ff9203307b6
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/f16f32dot-simd.s
> @@ -0,0 +1,19 @@
> +fdot v0.2s, v0.4h, v0.2h[0]
> +fdot v31.2s, v0.4h, v0.2h[1]
> +fdot v0.2s, v31.4h, v0.2h[2]
> +fdot v0.2s, v0.4h, v31.2h[3]
> +
> +fdot v0.4s, v0.8h, v0.2h[0]
> +fdot v31.4s, v0.8h, v0.2h[1]
> +fdot v0.4s, v31.8h, v0.2h[2]
> +fdot v0.4s, v0.8h, v31.2h[3]
> +
> +fdot v0.2s, v0.4h, v0.4h
> +fdot v31.2s, v0.4h, v0.4h
> +fdot v0.2s, v31.4h, v0.4h
> +fdot v0.2s, v0.4h, v31.4h
> +
> +fdot v0.4s, v0.8h, v0.8h
> +fdot v31.4s, v0.8h, v0.8h
> +fdot v0.4s, v31.8h, v0.8h
> +fdot v0.4s, v0.8h, v31.8h
> diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
> index e65b61c3f9c..3344db2a705 100644
> --- a/include/opcode/aarch64.h
> +++ b/include/opcode/aarch64.h
> @@ -263,6 +263,8 @@ enum aarch64_feature_bit {
> AARCH64_FEATURE_SME_TMOP,
> /* SME MOP4 instructions. */
> AARCH64_FEATURE_SME_MOP4,
> + /* F16F32DOT instructions. */
> + AARCH64_FEATURE_F16F32DOT,
>
> /* Virtual features. These are used to gate instructions that are enabled
> by either of two (or more) sets of command line flags. */
> diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
> index ecaea2d2fdb..5c613c618da 100644
> --- a/opcodes/aarch64-dis-2.c
> +++ b/opcodes/aarch64-dis-2.c
> @@ -28611,10 +28611,20 @@ aarch64_opcode_lookup_1 (uint32_t word)
> {
> if (((word >> 22) & 0x1) == 0)
> {
> - /* 33222222222211111111110000000000
> - 10987654321098765432109876543210
> - 0x001110x00xxxxxx11111xxxxxxxxxx. */
> - return A64_OPID_0e00fc00_fdot_Vd_Vn_Vm;
> + if (((word >> 23) & 0x1) == 0)
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 0x001110000xxxxxx11111xxxxxxxxxx. */
> + return A64_OPID_0e00fc00_fdot_Vd_Vn_Vm;
> + }
> + else
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + 0x001110100xxxxxx11111xxxxxxxxxx. */
> + return A64_OPID_0e80fc00_fdot_Vd_Vn_Vm;
> + }
> }
> else
> {
> @@ -34411,19 +34421,29 @@ aarch64_opcode_lookup_1 (uint32_t word)
> {
> if (((word >> 23) & 0x1) == 0)
> {
> - if (((word >> 29) & 0x1) == 0)
> + if (((word >> 22) & 0x1) == 0)
> {
> - /* 33222222222211111111110000000000
> - 10987654321098765432109876543210
> - xx0011110xxxxxxx1001x0xxxxxxxxxx. */
> - return A64_OPID_0f009000_fmul_Vd_Vn_Em16;
> + if (((word >> 29) & 0x1) == 0)
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + xx00111100xxxxxx1001x0xxxxxxxxxx. */
> + return A64_OPID_0f009000_fmul_Vd_Vn_Em16;
> + }
> + else
> + {
> + /* 33222222222211111111110000000000
> + 10987654321098765432109876543210
> + xx10111100xxxxxx1001x0xxxxxxxxxx. */
> + return A64_OPID_2f009000_fmulx_Vd_Vn_Em16;
> + }
> }
> else
> {
> /* 33222222222211111111110000000000
> 10987654321098765432109876543210
> - xx1011110xxxxxxx1001x0xxxxxxxxxx. */
> - return A64_OPID_2f009000_fmulx_Vd_Vn_Em16;
> + xxx0111101xxxxxx1001x0xxxxxxxxxx. */
> + return A64_OPID_0f409000_fdot_Vd_Vn_Em16;
> }
> }
> else
> diff --git a/opcodes/aarch64-tbl-2.h b/opcodes/aarch64-tbl-2.h
> index 1263f1f9bd8..1e7ad140145 100644
> --- a/opcodes/aarch64-tbl-2.h
> +++ b/opcodes/aarch64-tbl-2.h
> @@ -3995,5 +3995,7 @@ enum aarch64_opcode_idx
> A64_OPID_a1c00018_usmop4s_SME_ZAda_3b_SME_Zn_6_3_SME_Zm_17_3,
> A64_OPID_a1c00218_usmop4s_SME_ZAda_3b_SME_Znx2_6_3_SME_Zm_17_3,
> A64_OPID_a1d00218_usmop4s_SME_ZAda_3b_SME_Znx2_6_3_SME_Zmx2_17_3,
> + A64_OPID_0f409000_fdot_Vd_Vn_Em16,
> + A64_OPID_0e80fc00_fdot_Vd_Vn_Vm,
> A64_OPID_MAX,
> };
> diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
> index e7b17061d82..13b5a3b48df 100644
> --- a/opcodes/aarch64-tbl.h
> +++ b/opcodes/aarch64-tbl.h
> @@ -3057,6 +3057,8 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_f8f32 =
> AARCH64_FEATURES (2, SME_MOP4, SME_F8F32);
> static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 =
> AARCH64_FEATURES (2, SME_MOP4, SME_I16I64);
> +static const aarch64_feature_set aarch64_feature_f16f32dot =
> + AARCH64_FEATURE (F16F32DOT);
>
> #define CORE &aarch64_feature_v8
> #define FP &aarch64_feature_fp
> @@ -3181,6 +3183,7 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 =
> #define SME_MOP4_F8F16 &aarch64_feature_sme_mop4_f8f16
> #define SME_MOP4_F8F32 &aarch64_feature_sme_mop4_f8f32
> #define SME_MOP4_I16I64 &aarch64_feature_sme_mop4_i16i64
> +#define F16F32DOT &aarch64_feature_f16f32dot
>
> #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
> { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
> @@ -3510,6 +3513,8 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 =
> #define SME_MOP4_I16I64_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \
> { NAME, OPCODE, MASK, CLASS, 0, SME_MOP4_I16I64, OPS, QUALS, \
> FLAGS | F_STRICT, 0, TIED, NULL }
> +#define F16F32DOT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
> + { NAME, OPCODE, MASK, CLASS, 0, F16F32DOT, OPS, QUALS, FLAGS, 0, 0, NULL }
>
> #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
> MOPS_INSN (NAME, OPCODE, MASK, 0, \
> @@ -7737,6 +7742,9 @@ const struct aarch64_opcode aarch64_opcode_table[] =
> SME_MOP4_I16I64_INSN ("usmop4s", 0xa1c00018, 0xfff1fe38, sme_misc, OP3 (SME_ZAda_3b, SME_Zn_6_3, SME_Zm_17_3), OP_SVE_DHH, 0, 0),
> SME_MOP4_I16I64_INSN ("usmop4s", 0xa1c00218, 0xfff1fe38, sme_misc, OP3 (SME_ZAda_3b, SME_Znx2_6_3, SME_Zm_17_3), OP_SVE_DHH, 0, 0),
> SME_MOP4_I16I64_INSN ("usmop4s", 0xa1d00218, 0xfff1fe38, sme_misc, OP3 (SME_ZAda_3b, SME_Znx2_6_3, SME_Zmx2_17_3), OP_SVE_DHH, 0, 0),
> + /* F16F32DOT instructions. */
> + F16F32DOT_INSN ("fdot", 0x0f409000, 0xbfc0f400, dotproduct, OP3 (Vd, Vn, Em16), QL_BFDOT64I, F_SIZEQ),
> + F16F32DOT_INSN ("fdot", 0x0e80fc00, 0xbfe0fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_BFDOT64, F_SIZEQ),
>
> {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
> };
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