[PATCH v2 1/9] aarch64: Extend aarch64_field to support constants

[Alice Carlotti]

On Thu, Oct 09, 2025 at 10:24:21AM +0100, Richard Earnshaw wrote:
> On 09/10/2025 08:41, Alice Carlotti wrote:
...
> > -/* Field description.  */
> > +/* Field description.
> > +
> > +   If is_const is false, this identifies a bitfield in an instruction encoding
> > +   that has size WIDTH and has its least significant bit at position NUM.
> > +
> > +   If is_const is true, this represents the constant bit string of size WIDTH
> > +   bits stored in the least significant bits of NUM.  In this case, the
> > +   leading 8-WIDTH bits of VALUE must be zero.
> > +
> > +   A sequence of fields can be used to describe how instruction operands are
> > +   represented in the 32-bit instruction encoding.
> > +
> > +   For example, consider an instruction operand Zd that is an even numbered
> > +   register in z16-z30, with the middle three bits of the register number
> > +   stored in bits [19:17] of the encoding.  The register number can then be
> > +   constructed by concatenating:
> > +   - a constant bit '1' (represented here as {1, 1, true}),
> > +   - bits [19:17] of the encoding (represented here as {17, 3, false}), and
> > +   - a constant bit '0' (represented here as {1, 1, true}).
> 
> Surely this should be {1, 0, true}??

Yes, and also the previous line should be {3, 17, false}.  I've fixed them both
locally.

> 
> > +   This sequence of fields fully describes both the constraints on which
> > +   register numbers are valid, and how valid register numbers are represented
> > +   in the instruction encoding.  */
> >   struct aarch64_field
> >   {
> > -  int lsb;
> > -  int width;
> > +  unsigned int width:8;
> > +  unsigned int num:7;
> > +  bool is_const:1;
> >   };
> >   typedef struct aarch64_field aarch64_field;
...
> Looks much better otherwise.
> R.
> 
Thanks.  I'll leave it till this evening (or longer if you'd prefer) in case
there are any other comments.

Alice