[PATCH 8/9] aarch64: Add support for FEAT_SSVE_FEXPA
Alice Carlotti
alice.carlotti@arm.com
Wed Oct 8 00:40:57 GMT 2025
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 625b6de06c952854e184f58a4dfe0d02aeeea8b7..623fbcf7549605e14340fd1897c6b962914bfaf7 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10863,6 +10863,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"pops", AARCH64_FEATURE (PoPS), AARCH64_NO_FEATURES},
{"sve2p2", AARCH64_FEATURE (SVE2p2), AARCH64_FEATURE (SVE2p1)},
{"sme2p2", AARCH64_FEATURE (SME2p2), AARCH64_FEATURE (SME2p1)},
+ {"ssve-fexpa", AARCH64_FEATURE (SSVE_FEXPA), AARCH64_FEATURE (SME2)},
{"sme-tmop", AARCH64_FEATURE (SME_TMOP), AARCH64_FEATURE (SME2)},
{"sme-mop4", AARCH64_FEATURE (SME_MOP4), AARCH64_FEATURE (SME2)},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
@@ -10879,6 +10880,8 @@ struct aarch64_virtual_dependency_table
static const struct aarch64_virtual_dependency_table aarch64_dependencies[] = {
{AARCH64_FEATURE (SVE2), AARCH64_FEATURE (SVE2_SSVE_AES)},
{AARCH64_FEATURE (SSVE_AES), AARCH64_FEATURE (SVE2_SSVE_AES)},
+ {AARCH64_FEATURE (SVE), AARCH64_FEATURE (SVE_SSVE_FEXPA)},
+ {AARCH64_FEATURE (SSVE_FEXPA), AARCH64_FEATURE (SVE_SSVE_FEXPA)},
{AARCH64_FEATURES (2, FP8FMA, SVE2), AARCH64_FEATURE (FP8FMA_SVE)},
{AARCH64_FEATURE (SSVE_FP8FMA), AARCH64_FEATURE (FP8FMA_SVE)},
{AARCH64_FEATURES (2, FP8DOT4, SVE2), AARCH64_FEATURE (FP8DOT4_SVE)},
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 3946f52b33b987f325dafee6eb381779a7f55036..44433f1ee882a54e95bab99722181b999831e88d 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -321,6 +321,8 @@ automatically cause those extensions to be disabled.
@tab Enable Speculative Store Bypassing Safe state read and write.
@item @code{ssve-aes} @tab @code{sme2}, @code{sve-aes}
@tab Enable SVE AES instructions in streaming mode.
+@item @code{ssve-fexpa} @tab @code{sme2}
+ @tab Enable the SVE FEXPA instruction in streaming mode.
@item @code{ssve-fp8dot2} @tab @code{sme2}, @code{fp8}
@tab Enable the Streaming SVE FP8 2-way dot product instructions.
@item @code{ssve-fp8dot4} @tab @code{sme2}, @code{fp8}
diff --git a/gas/testsuite/gas/aarch64/sve-fexpa.d b/gas/testsuite/gas/aarch64/sve-fexpa.d
new file mode 100644
index 0000000000000000000000000000000000000000..c47c27479f12b1bcefccbfc7bf80950a9af05f21
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-fexpa.d
@@ -0,0 +1,19 @@
+#as: -march=armv8-a+sve
+#as: -march=armv8-a+ssve-fexpa
+#objdump: -dr
+
+.*: file format .*
+
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: 0460b800 fexpa z0\.h, z0\.h
+ *[0-9a-f]+: 0460b81f fexpa z31\.h, z0\.h
+ *[0-9a-f]+: 0460bbe0 fexpa z0\.h, z31\.h
+ *[0-9a-f]+: 04a0b800 fexpa z0\.s, z0\.s
+ *[0-9a-f]+: 04a0b81f fexpa z31\.s, z0\.s
+ *[0-9a-f]+: 04a0bbe0 fexpa z0\.s, z31\.s
+ *[0-9a-f]+: 04e0b800 fexpa z0\.d, z0\.d
+ *[0-9a-f]+: 04e0b81f fexpa z31\.d, z0\.d
+ *[0-9a-f]+: 04e0bbe0 fexpa z0\.d, z31\.d
diff --git a/gas/testsuite/gas/aarch64/sve-fexpa.s b/gas/testsuite/gas/aarch64/sve-fexpa.s
new file mode 100644
index 0000000000000000000000000000000000000000..301865530c6d85a6fcdb62e97f5b254e7a814635
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve-fexpa.s
@@ -0,0 +1,9 @@
+ fexpa z0.h, z0.h
+ fexpa z31.h, z0.h
+ fexpa z0.h, z31.h
+ fexpa z0.s, z0.s
+ fexpa z31.s, z0.s
+ fexpa z0.s, z31.s
+ fexpa z0.d, z0.d
+ fexpa z31.d, z0.d
+ fexpa z0.d, z31.d
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 055b70e38a99868bceca372479f912f2d458c3e3..b05591799947b7a7b47d302ac826ae0d9b98c209 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -251,6 +251,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_FPRCVT,
/* Point of Physical Storage. */
AARCH64_FEATURE_PoPS,
+ /* SVE FEXPA instruction in streaming mode. */
+ AARCH64_FEATURE_SSVE_FEXPA,
/* SME TMOP instructions. */
AARCH64_FEATURE_SME_TMOP,
/* SME MOP4 instructions. */
@@ -260,6 +262,8 @@ enum aarch64_feature_bit {
by either of two (or more) sets of command line flags. */
/* +sve2 or +ssve-aes */
AARCH64_FEATURE_SVE2_SSVE_AES,
+ /* +sve or +ssve-fexpa */
+ AARCH64_FEATURE_SVE_SSVE_FEXPA,
/* +fp8fma+sve or +ssve-fp8fma */
AARCH64_FEATURE_FP8FMA_SVE,
/* +fp8dot4+sve or +ssve-fp8dot4 */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 8e0d663b3cf0228a00fd179e9245aa60731e42b8..a363f4021b1e8f3e8c7c5fadadf83079062f9195 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -3029,6 +3029,8 @@ static const aarch64_feature_set aarch64_feature_sve_sme2p2 =
AARCH64_FEATURE (SVE_SME2p2);
static const aarch64_feature_set aarch64_feature_sve2p2_sme2p2 =
AARCH64_FEATURE (SVE2p2_SME2p2);
+static const aarch64_feature_set aarch64_feature_sve_ssve_fexpa =
+ AARCH64_FEATURE (SVE_SSVE_FEXPA);
static const aarch64_feature_set aarch64_feature_sme_tmop =
AARCH64_FEATURE (SME_TMOP);
static const aarch64_feature_set aarch64_feature_sme_tmop_b16b16 =
@@ -3163,6 +3165,7 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 =
#define SME2p2 &aarch64_feature_sme2p2
#define SVE_SME2p2 &aarch64_feature_sve_sme2p2
#define SVE2p2_SME2p2 &aarch64_feature_sve2p2_sme2p2
+#define SVE_SSVE_FEXPA &aarch64_feature_sve_ssve_fexpa
#define SME_TMOP &aarch64_feature_sme_tmop
#define SME_TMOP_B16B16 &aarch64_feature_sme_tmop_b16b16
#define SME_TMOP_F16F16 &aarch64_feature_sme_tmop_f16f16
@@ -3463,6 +3466,9 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 =
#define SME2p2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, 0, SME2p2, OPS, QUALS, \
F_STRICT | FLAGS, 0, TIED, NULL }
+#define _SVE_SSVE_FEXPA_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
+ { NAME, OPCODE, MASK, CLASS, OP, SVE_SSVE_FEXPA, OPS, QUALS, \
+ FLAGS | F_STRICT, 0, TIED, NULL }
#define SME_TMOP_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, 0, SME_TMOP, OPS, QUALS, \
FLAGS | F_STRICT, 0, TIED, NULL }
@@ -5243,7 +5249,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
_SVE_INSNC ("fdiv", 0x650d8000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2),
_SVE_INSNC ("fdivr", 0x650c8000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2),
_SVE_INSN ("fdup", 0x2539c000, 0xff3fe000, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_FPIMM8), OP_SVE_VU_HSD, F_HAS_ALIAS, 0),
- _SVE_INSN ("fexpa", 0x0420b800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD, 0, 0),
+ _SVE_SSVE_FEXPA_INSN ("fexpa", 0x0420b800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD, 0, 0),
_SVE_INSNC ("fmad", 0x65208000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0),
_SVE_INSNC ("fmax", 0x65068000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2),
_SVE_INSNC ("fmax", 0x651e8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2),
More information about the Binutils
mailing list