[PATCH v3 3/5] aarch64: GICv5 CPU interface system registers
saurabh.jha@arm.com
saurabh.jha@arm.com
Mon Oct 6 16:49:03 GMT 2025
From: Matthieu Longo <matthieu.longo@arm.com>
This patch adds support for 13 new AArch64 system registers for the CPU
interface, which are enabled on using Generic Interrupt Controller v5
(+gcie flag) feature:
- 7 R/W registers: ICC_APR_EL1, ICC_APR_EL3, ICC_CR0_EL1, ICC_CR0_EL3
ICC_ICSR_EL1, ICC_PCR_EL1, ICC_PCR_EL3.
- 6 RO registers: ICC_DOMHPPIR_EL3, ICC_HAPR_EL1, ICC_HPPIR_EL1,
ICC_HPPIR_EL3, ICC_IAFFIDR_EL1, ICC_IDR0_EL1.
Note: the already-existing ID_AA64PFR2_EL1 register is required by the
GICv5 feature.
---
.../gas/aarch64/sysreg/gcie-sysregs.d | 30 +++++++++++++++++++
.../gas/aarch64/sysreg/gcie-sysregs.s | 21 +++++++++++++
.../sysreg/sysregs_with_no_restrictions-bad.l | 4 +++
.../sysreg/sysregs_with_no_restrictions.d | 2 ++
.../sysreg/sysregs_with_no_restrictions.s | 1 +
.../sysreg/sysregs_with_restrictions.d | 2 ++
.../sysreg/sysregs_with_restrictions.s | 2 ++
opcodes/aarch64-sys-regs.def | 13 ++++++++
8 files changed, 75 insertions(+)
create mode 100644 gas/testsuite/gas/aarch64/sysreg/gcie-sysregs.d
create mode 100644 gas/testsuite/gas/aarch64/sysreg/gcie-sysregs.s
diff --git a/gas/testsuite/gas/aarch64/sysreg/gcie-sysregs.d b/gas/testsuite/gas/aarch64/sysreg/gcie-sysregs.d
new file mode 100644
index 00000000000..05d2206b318
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg/gcie-sysregs.d
@@ -0,0 +1,30 @@
+#name: Test of system registers for Generic Interrupt Controller version 5
+#as: -menable-sysreg-checking -I$srcdir/$subdir -march=armv9.5-a+gcie
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+.*: d519c000 msr icc_apr_el1, x0
+.*: d539c000 mrs x0, icc_apr_el1
+.*: d51ec800 msr icc_apr_el3, x0
+.*: d53ec800 mrs x0, icc_apr_el3
+.*: d519c020 msr icc_cr0_el1, x0
+.*: d539c020 mrs x0, icc_cr0_el1
+.*: d51ec900 msr icc_cr0_el3, x0
+.*: d53ec900 mrs x0, icc_cr0_el3
+.*: d518ca80 msr icc_icsr_el1, x0
+.*: d538ca80 mrs x0, icc_icsr_el1
+.*: d519c040 msr icc_pcr_el1, x0
+.*: d539c040 mrs x0, icc_pcr_el1
+.*: d51ec820 msr icc_pcr_el3, x0
+.*: d53ec820 mrs x0, icc_pcr_el3
+.*: d53ec840 mrs x0, icc_domhppir_el3
+.*: d539c060 mrs x0, icc_hapr_el1
+.*: d538ca60 mrs x0, icc_hppir_el1
+.*: d53ec920 mrs x0, icc_hppir_el3
+.*: d538caa0 mrs x0, icc_iaffidr_el1
+.*: d538ca40 mrs x0, icc_idr0_el1
+.*: d5380440 mrs x0, id_aa64pfr2_el1
diff --git a/gas/testsuite/gas/aarch64/sysreg/gcie-sysregs.s b/gas/testsuite/gas/aarch64/sysreg/gcie-sysregs.s
new file mode 100644
index 00000000000..eddeca750bf
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sysreg/gcie-sysregs.s
@@ -0,0 +1,21 @@
+ .include "sysreg-test-utils.inc"
+
+.text
+
+ /* CPU Interface registers. */
+
+ rw_sys_reg icc_apr_el1
+ rw_sys_reg icc_apr_el3
+ rw_sys_reg icc_cr0_el1
+ rw_sys_reg icc_cr0_el3
+ rw_sys_reg icc_icsr_el1
+ rw_sys_reg icc_pcr_el1
+ rw_sys_reg icc_pcr_el3
+
+ rw_sys_reg icc_domhppir_el3 w=0
+ rw_sys_reg icc_hapr_el1 w=0
+ rw_sys_reg icc_hppir_el1 w=0
+ rw_sys_reg icc_hppir_el3 w=0
+ rw_sys_reg icc_iaffidr_el1 w=0
+ rw_sys_reg icc_idr0_el1 w=0
+ rw_sys_reg id_aa64pfr2_el1 w=0
diff --git a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions-bad.l b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions-bad.l
index fce23070fd2..d563712ec2c 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions-bad.l
+++ b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions-bad.l
@@ -139,6 +139,10 @@
.*: Info: macro invoked from here
.*: Error: selected processor does not support system register name 'ssbs'
.*: Info: macro invoked from here
+.*: Error: selected processor does not support system register name 'icc_apr_el1'
+.*: Info: macro invoked from here
+.*: Error: selected processor does not support system register name 'icc_apr_el1'
+.*: Info: macro invoked from here
.*: Error: selected processor does not support system register name 'rcwmask_el1'
.*: Info: macro invoked from here
.*: Error: selected processor does not support system register name 'rcwmask_el1'
diff --git a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.d b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.d
index ac5d1721338..68ff860aa73 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.d
+++ b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.d
@@ -86,6 +86,8 @@
.*: d5384260 mrs x0, pan
.*: d51b42c0 msr ssbs, x0
.*: d53b42c0 mrs x0, ssbs
+.*: d519c000 msr icc_apr_el1, x0
+.*: d539c000 mrs x0, icc_apr_el1
.*: d558d0c2 msrr rcwmask_el1, x2, x3
.*: d578d0c2 mrrs x2, x3, rcwmask_el1
.*: d55c2002 msrr ttbr0_el2, x2, x3
diff --git a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.s b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.s
index 89e7388c1dc..3619951fb3c 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.s
+++ b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_no_restrictions.s
@@ -49,6 +49,7 @@
rw_sys_reg disr_el1 // RAS
rw_sys_reg pan // PAN
rw_sys_reg ssbs // SSBS
+ rw_sys_reg icc_apr_el1 // GCIE
.arch_extension d128 // For the msrr and mrrs instructions.
rw_sys_reg_128 rcwmask_el1 xreg1=x2 xreg2=x3 // THE
diff --git a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.d b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.d
index 38cc6ddc82f..dd7c7a5dbf6 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.d
+++ b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.d
@@ -86,6 +86,8 @@
.*: d5384260 mrs x0, pan
.*: d51b42c0 msr ssbs, x0
.*: d53b42c0 mrs x0, ssbs
+.*: d519c000 msr icc_apr_el1, x0
+.*: d539c000 mrs x0, icc_apr_el1
.*: d558d0c2 msrr rcwmask_el1, x2, x3
.*: d578d0c2 mrrs x2, x3, rcwmask_el1
.*: d55c2002 msrr ttbr0_el2, x2, x3
diff --git a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.s b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.s
index 3ad53e94f21..2102ea8bdcc 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.s
+++ b/gas/testsuite/gas/aarch64/sysreg/sysregs_with_restrictions.s
@@ -82,6 +82,8 @@
rw_sys_reg pan // PAN
.arch_extension ssbs
rw_sys_reg ssbs // SSBS
+ .arch_extension gcie
+ rw_sys_reg icc_apr_el1 // GCIE
.arch_extension d128 // For the msrr and mrrs instructions.
.arch_extension the
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index 51aab230bfa..bad559be320 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -458,6 +458,8 @@
SYSREG ("hfgwtr2_el2", CPENC (3,4,3,1,3), 0, AARCH64_FEATURE (V8_8A)) /* FGT2 */
SYSREG ("hpfar_el2", CPENC (3,4,6,0,4), 0, AARCH64_NO_FEATURES)
SYSREG ("hstr_el2", CPENC (3,4,1,1,3), 0, AARCH64_NO_FEATURES)
+ SYSREG ("icc_apr_el1", CPENC (3,1,12,0,0), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_apr_el3", CPENC (3,6,12,8,0), 0, AARCH64_FEATURE (GCIE))
SYSREG ("icc_ap0r0_el1", CPENC (3,0,12,8,4), 0, AARCH64_NO_FEATURES)
SYSREG ("icc_ap0r1_el1", CPENC (3,0,12,8,5), 0, AARCH64_NO_FEATURES)
SYSREG ("icc_ap0r2_el1", CPENC (3,0,12,8,6), 0, AARCH64_NO_FEATURES)
@@ -469,19 +471,30 @@
SYSREG ("icc_asgi1r_el1", CPENC (3,0,12,11,6), F_REG_WRITE, AARCH64_NO_FEATURES)
SYSREG ("icc_bpr0_el1", CPENC (3,0,12,8,3), 0, AARCH64_NO_FEATURES)
SYSREG ("icc_bpr1_el1", CPENC (3,0,12,12,3), 0, AARCH64_NO_FEATURES)
+ SYSREG ("icc_cr0_el1", CPENC (3,1,12,0,1), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_cr0_el3", CPENC (3,6,12,9,0), 0, AARCH64_FEATURE (GCIE))
SYSREG ("icc_ctlr_el1", CPENC (3,0,12,12,4), 0, AARCH64_NO_FEATURES)
SYSREG ("icc_ctlr_el3", CPENC (3,6,12,12,4), 0, AARCH64_NO_FEATURES)
SYSREG ("icc_dir_el1", CPENC (3,0,12,11,1), F_REG_WRITE, AARCH64_NO_FEATURES)
+ SYSREG ("icc_domhppir_el3", CPENC (3,6,12,8,2), F_REG_READ, AARCH64_FEATURE (GCIE))
SYSREG ("icc_eoir0_el1", CPENC (3,0,12,8,1), F_REG_WRITE, AARCH64_NO_FEATURES)
SYSREG ("icc_eoir1_el1", CPENC (3,0,12,12,1), F_REG_WRITE, AARCH64_NO_FEATURES)
+ SYSREG ("icc_hapr_el1", CPENC (3,1,12,0,3), F_REG_READ, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_hppir_el1", CPENC (3,0,12,10,3), F_REG_READ, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_hppir_el3", CPENC (3,6,12,9,1), F_REG_READ, AARCH64_FEATURE (GCIE))
SYSREG ("icc_hppir0_el1", CPENC (3,0,12,8,2), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("icc_hppir1_el1", CPENC (3,0,12,12,2), F_REG_READ, AARCH64_NO_FEATURES)
+ SYSREG ("icc_iaffidr_el1", CPENC (3,0,12,10,5), F_REG_READ, AARCH64_FEATURE (GCIE))
SYSREG ("icc_iar0_el1", CPENC (3,0,12,8,0), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("icc_iar1_el1", CPENC (3,0,12,12,0), F_REG_READ, AARCH64_NO_FEATURES)
+ SYSREG ("icc_icsr_el1", CPENC (3,0,12,10,4), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_idr0_el1", CPENC (3,0,12,10,2), F_REG_READ, AARCH64_FEATURE (GCIE))
SYSREG ("icc_igrpen0_el1", CPENC (3,0,12,12,6), 0, AARCH64_NO_FEATURES)
SYSREG ("icc_igrpen1_el1", CPENC (3,0,12,12,7), 0, AARCH64_NO_FEATURES)
SYSREG ("icc_igrpen1_el3", CPENC (3,6,12,12,7), 0, AARCH64_NO_FEATURES)
SYSREG ("icc_nmiar1_el1", CPENC (3,0,12,9,5), F_REG_READ, AARCH64_FEATURE (V8_7A)) /* GICv3_NMI */
+ SYSREG ("icc_pcr_el1", CPENC (3,1,12,0,2), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_pcr_el3", CPENC (3,6,12,8,1), 0, AARCH64_FEATURE (GCIE))
SYSREG ("icc_pmr_el1", CPENC (3,0,4,6,0), 0, AARCH64_NO_FEATURES)
SYSREG ("icc_rpr_el1", CPENC (3,0,12,11,3), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("icc_sgi0r_el1", CPENC (3,0,12,11,7), F_REG_WRITE, AARCH64_NO_FEATURES)
--
2.34.1
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