[PATCH v2 4/5] gas: aarch64: GICv5 PPI system registers
saurabh.jha@arm.com
saurabh.jha@arm.com
Mon Oct 6 14:40:06 GMT 2025
From: Matthieu Longo <matthieu.longo@arm.com>
This patch adds support for PPI registers on AArch64, available via the
Generic Interrupt Controller v5 feature, and enabled via the +gcie flag.
- icc_ppi_cactiver[0,1]_el1
- icc_ppi_cpendr[0,1]_el1
- icc_ppi_enabler[0,1]_el1
- icc_ppi_hmr[0,1]_el1 (RO)
- icc_ppi_priorityr[0,15]_el1
- icc_ppi_sactiver[0,1]_el1
- icc_ppi_spendr[0,1]_el1
Also, the new system register 'icc_ppi_priorityr8_el1' clashed with the
encoding of 's3_0_c12_c15_0' used in a test for the generic syntax of
system registers using mrs and msr.
This patch replaces 's3_0_c12_c15_0' in the test by an unused encoding:
s3_7_c0_c15_0.
---
.../gas/aarch64/sysreg/gcie-sysregs.d | 62 +++++++++++++++++++
.../gas/aarch64/sysreg/gcie-sysregs.s | 35 +++++++++++
gas/testsuite/gas/aarch64/sysreg/sysreg.d | 2 +-
gas/testsuite/gas/aarch64/sysreg/sysreg.s | 2 +-
opcodes/aarch64-sys-regs.def | 32 ++++++++++
5 files changed, 131 insertions(+), 2 deletions(-)
diff --git a/gas/testsuite/gas/aarch64/sysreg/gcie-sysregs.d b/gas/testsuite/gas/aarch64/sysreg/gcie-sysregs.d
index 05d2206b318..c31fe4bf168 100644
--- a/gas/testsuite/gas/aarch64/sysreg/gcie-sysregs.d
+++ b/gas/testsuite/gas/aarch64/sysreg/gcie-sysregs.d
@@ -28,3 +28,65 @@ Disassembly of section \.text:
.*: d538caa0 mrs x0, icc_iaffidr_el1
.*: d538ca40 mrs x0, icc_idr0_el1
.*: d5380440 mrs x0, id_aa64pfr2_el1
+.*: d518cd00 msr icc_ppi_cactiver0_el1, x0
+.*: d538cd00 mrs x0, icc_ppi_cactiver0_el1
+.*: d518cd20 msr icc_ppi_cactiver1_el1, x0
+.*: d538cd20 mrs x0, icc_ppi_cactiver1_el1
+.*: d518cd80 msr icc_ppi_cpendr0_el1, x0
+.*: d538cd80 mrs x0, icc_ppi_cpendr0_el1
+.*: d518cda0 msr icc_ppi_cpendr1_el1, x0
+.*: d538cda0 mrs x0, icc_ppi_cpendr1_el1
+.*: d51ec880 msr icc_ppi_domainr0_el3, x0
+.*: d53ec880 mrs x0, icc_ppi_domainr0_el3
+.*: d51ec8a0 msr icc_ppi_domainr1_el3, x0
+.*: d53ec8a0 mrs x0, icc_ppi_domainr1_el3
+.*: d51ec8c0 msr icc_ppi_domainr2_el3, x0
+.*: d53ec8c0 mrs x0, icc_ppi_domainr2_el3
+.*: d51ec8e0 msr icc_ppi_domainr3_el3, x0
+.*: d53ec8e0 mrs x0, icc_ppi_domainr3_el3
+.*: d518cac0 msr icc_ppi_enabler0_el1, x0
+.*: d538cac0 mrs x0, icc_ppi_enabler0_el1
+.*: d518cae0 msr icc_ppi_enabler1_el1, x0
+.*: d538cae0 mrs x0, icc_ppi_enabler1_el1
+.*: d538ca00 mrs x0, icc_ppi_hmr0_el1
+.*: d538ca20 mrs x0, icc_ppi_hmr1_el1
+.*: d518ce00 msr icc_ppi_priorityr0_el1, x0
+.*: d538ce00 mrs x0, icc_ppi_priorityr0_el1
+.*: d518ce20 msr icc_ppi_priorityr1_el1, x0
+.*: d538ce20 mrs x0, icc_ppi_priorityr1_el1
+.*: d518ce40 msr icc_ppi_priorityr2_el1, x0
+.*: d538ce40 mrs x0, icc_ppi_priorityr2_el1
+.*: d518ce60 msr icc_ppi_priorityr3_el1, x0
+.*: d538ce60 mrs x0, icc_ppi_priorityr3_el1
+.*: d518ce80 msr icc_ppi_priorityr4_el1, x0
+.*: d538ce80 mrs x0, icc_ppi_priorityr4_el1
+.*: d518cea0 msr icc_ppi_priorityr5_el1, x0
+.*: d538cea0 mrs x0, icc_ppi_priorityr5_el1
+.*: d518cec0 msr icc_ppi_priorityr6_el1, x0
+.*: d538cec0 mrs x0, icc_ppi_priorityr6_el1
+.*: d518cee0 msr icc_ppi_priorityr7_el1, x0
+.*: d538cee0 mrs x0, icc_ppi_priorityr7_el1
+.*: d518cf00 msr icc_ppi_priorityr8_el1, x0
+.*: d538cf00 mrs x0, icc_ppi_priorityr8_el1
+.*: d518cf20 msr icc_ppi_priorityr9_el1, x0
+.*: d538cf20 mrs x0, icc_ppi_priorityr9_el1
+.*: d518cf40 msr icc_ppi_priorityr10_el1, x0
+.*: d538cf40 mrs x0, icc_ppi_priorityr10_el1
+.*: d518cf60 msr icc_ppi_priorityr11_el1, x0
+.*: d538cf60 mrs x0, icc_ppi_priorityr11_el1
+.*: d518cf80 msr icc_ppi_priorityr12_el1, x0
+.*: d538cf80 mrs x0, icc_ppi_priorityr12_el1
+.*: d518cfa0 msr icc_ppi_priorityr13_el1, x0
+.*: d538cfa0 mrs x0, icc_ppi_priorityr13_el1
+.*: d518cfc0 msr icc_ppi_priorityr14_el1, x0
+.*: d538cfc0 mrs x0, icc_ppi_priorityr14_el1
+.*: d518cfe0 msr icc_ppi_priorityr15_el1, x0
+.*: d538cfe0 mrs x0, icc_ppi_priorityr15_el1
+.*: d518cd40 msr icc_ppi_sactiver0_el1, x0
+.*: d538cd40 mrs x0, icc_ppi_sactiver0_el1
+.*: d518cd60 msr icc_ppi_sactiver1_el1, x0
+.*: d538cd60 mrs x0, icc_ppi_sactiver1_el1
+.*: d518cdc0 msr icc_ppi_spendr0_el1, x0
+.*: d538cdc0 mrs x0, icc_ppi_spendr0_el1
+.*: d518cde0 msr icc_ppi_spendr1_el1, x0
+.*: d538cde0 mrs x0, icc_ppi_spendr1_el1
diff --git a/gas/testsuite/gas/aarch64/sysreg/gcie-sysregs.s b/gas/testsuite/gas/aarch64/sysreg/gcie-sysregs.s
index eddeca750bf..9bf0a07c6b8 100644
--- a/gas/testsuite/gas/aarch64/sysreg/gcie-sysregs.s
+++ b/gas/testsuite/gas/aarch64/sysreg/gcie-sysregs.s
@@ -19,3 +19,38 @@
rw_sys_reg icc_iaffidr_el1 w=0
rw_sys_reg icc_idr0_el1 w=0
rw_sys_reg id_aa64pfr2_el1 w=0
+
+ /* PPI registers. */
+
+ rw_sys_reg icc_ppi_cactiver0_el1
+ rw_sys_reg icc_ppi_cactiver1_el1
+ rw_sys_reg icc_ppi_cpendr0_el1
+ rw_sys_reg icc_ppi_cpendr1_el1
+ rw_sys_reg icc_ppi_domainr0_el3
+ rw_sys_reg icc_ppi_domainr1_el3
+ rw_sys_reg icc_ppi_domainr2_el3
+ rw_sys_reg icc_ppi_domainr3_el3
+ rw_sys_reg icc_ppi_enabler0_el1
+ rw_sys_reg icc_ppi_enabler1_el1
+ rw_sys_reg icc_ppi_hmr0_el1 w=0
+ rw_sys_reg icc_ppi_hmr1_el1 w=0
+ rw_sys_reg icc_ppi_priorityr0_el1
+ rw_sys_reg icc_ppi_priorityr1_el1
+ rw_sys_reg icc_ppi_priorityr2_el1
+ rw_sys_reg icc_ppi_priorityr3_el1
+ rw_sys_reg icc_ppi_priorityr4_el1
+ rw_sys_reg icc_ppi_priorityr5_el1
+ rw_sys_reg icc_ppi_priorityr6_el1
+ rw_sys_reg icc_ppi_priorityr7_el1
+ rw_sys_reg icc_ppi_priorityr8_el1
+ rw_sys_reg icc_ppi_priorityr9_el1
+ rw_sys_reg icc_ppi_priorityr10_el1
+ rw_sys_reg icc_ppi_priorityr11_el1
+ rw_sys_reg icc_ppi_priorityr12_el1
+ rw_sys_reg icc_ppi_priorityr13_el1
+ rw_sys_reg icc_ppi_priorityr14_el1
+ rw_sys_reg icc_ppi_priorityr15_el1
+ rw_sys_reg icc_ppi_sactiver0_el1
+ rw_sys_reg icc_ppi_sactiver1_el1
+ rw_sys_reg icc_ppi_spendr0_el1
+ rw_sys_reg icc_ppi_spendr1_el1
diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg.d b/gas/testsuite/gas/aarch64/sysreg/sysreg.d
index d17c77f76e8..36d9b592bee 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysreg.d
+++ b/gas/testsuite/gas/aarch64/sysreg/sysreg.d
@@ -35,7 +35,7 @@ Disassembly of section \.text:
.*: d538065e mrs x30, id_aa64isar2_el1
.*: d5380660 mrs x0, id_aa64isar3_el1
.*: d538067e mrs x30, id_aa64isar3_el1
-.*: d538cf00 mrs x0, s3_0_c12_c15_0
+.*: d53f0f00 mrs x0, s3_7_c0_c15_0
.*: d5184b00 msr s3_0_c4_c11_0, x0
.*: d5384b00 mrs x0, s3_0_c4_c11_0
.*: d5110300 msr trcstatr, x0
diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg.s b/gas/testsuite/gas/aarch64/sysreg/sysreg.s
index cd33810ec15..00766f76acf 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysreg.s
+++ b/gas/testsuite/gas/aarch64/sysreg/sysreg.s
@@ -31,7 +31,7 @@
rw_sys_reg sys_reg=id_aa64isar3_el1 xreg=x0 w=0
rw_sys_reg sys_reg=id_aa64isar3_el1 xreg=x30 w=0
- rw_sys_reg sys_reg=s3_0_c12_c15_0 w=0
+ rw_sys_reg sys_reg=s3_7_c0_c15_0 w=0
rw_sys_reg sys_reg=s3_0_c4_c11_0
rw_sys_reg sys_reg=s2_1_c0_c3_0
rw_sys_reg sys_reg=id_aa64fpfr0_el1 w=0
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index bad559be320..6d0eb1de3bd 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -496,6 +496,38 @@
SYSREG ("icc_pcr_el1", CPENC (3,1,12,0,2), 0, AARCH64_FEATURE (GCIE))
SYSREG ("icc_pcr_el3", CPENC (3,6,12,8,1), 0, AARCH64_FEATURE (GCIE))
SYSREG ("icc_pmr_el1", CPENC (3,0,4,6,0), 0, AARCH64_NO_FEATURES)
+ SYSREG ("icc_ppi_cactiver0_el1", CPENC (3,0,12,13,0), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_cactiver1_el1", CPENC (3,0,12,13,1), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_cpendr0_el1", CPENC (3,0,12,13,4), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_cpendr1_el1", CPENC (3,0,12,13,5), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_domainr0_el3", CPENC (3,6,12,8,4), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_domainr1_el3", CPENC (3,6,12,8,5), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_domainr2_el3", CPENC (3,6,12,8,6), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_domainr3_el3", CPENC (3,6,12,8,7), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_enabler0_el1", CPENC (3,0,12,10,6), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_enabler1_el1", CPENC (3,0,12,10,7), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_hmr0_el1", CPENC (3,0,12,10,0), F_REG_READ, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_hmr1_el1", CPENC (3,0,12,10,1), F_REG_READ, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_priorityr0_el1", CPENC (3,0,12,14,0), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_priorityr1_el1", CPENC (3,0,12,14,1), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_priorityr2_el1", CPENC (3,0,12,14,2), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_priorityr3_el1", CPENC (3,0,12,14,3), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_priorityr4_el1", CPENC (3,0,12,14,4), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_priorityr5_el1", CPENC (3,0,12,14,5), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_priorityr6_el1", CPENC (3,0,12,14,6), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_priorityr7_el1", CPENC (3,0,12,14,7), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_priorityr8_el1", CPENC (3,0,12,15,0), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_priorityr9_el1", CPENC (3,0,12,15,1), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_priorityr10_el1", CPENC (3,0,12,15,2), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_priorityr11_el1", CPENC (3,0,12,15,3), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_priorityr12_el1", CPENC (3,0,12,15,4), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_priorityr13_el1", CPENC (3,0,12,15,5), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_priorityr14_el1", CPENC (3,0,12,15,6), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_priorityr15_el1", CPENC (3,0,12,15,7), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_sactiver0_el1", CPENC (3,0,12,13,2), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_sactiver1_el1", CPENC (3,0,12,13,3), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_spendr0_el1", CPENC (3,0,12,13,6), 0, AARCH64_FEATURE (GCIE))
+ SYSREG ("icc_ppi_spendr1_el1", CPENC (3,0,12,13,7), 0, AARCH64_FEATURE (GCIE))
SYSREG ("icc_rpr_el1", CPENC (3,0,12,11,3), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("icc_sgi0r_el1", CPENC (3,0,12,11,7), F_REG_WRITE, AARCH64_NO_FEATURES)
SYSREG ("icc_sgi1r_el1", CPENC (3,0,12,11,5), F_REG_WRITE, AARCH64_NO_FEATURES)
--
2.34.1
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